<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MipsABIInfo ABI = Subtarget . getABI ( ) ; DebugLoc DL ; unsigned ADDu = ABI . GetPtrAdduOp ( ) ; unsigned ADDiu = ABI . GetPtrAddiuOp ( ) ; if ( Amount == 0 ) return ; if ( isInt < 16 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> bool MSP430FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static void expand_set_up_frame_pointer ( void ) { int offset ; if ( ! frame_pointer_needed ) return ; INITIAL_ELIMINATION_OFFSET ( HARD_FRAME_POINTER_REGNUM , STACK_POINTER_REGNUM , offset ) ; emit_frame_insn ( gen_MOVEI ( hard_frame_pointer_rtx , plus_constant ( stack_pointer_rtx , offset ) ) ) ; } </s>

Emit an instruction to set up the frame pointer .


<s> static unsigned long thumb1_compute_save_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= 504 ) { for ( reg = LAST_ARG_REGNUM + 1 ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( 1 << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= 1 << LAST_LO_REGNUM ; } } return mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
int
AArch64FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
Register
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
IgnoreSPUpdates
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Offset from the SP for "
<<
FI
<<
" is "
<<
MFI
.
getObjectOffset
(
FI
)
<<
"\n"
)
;
FrameReg
=
AArch64
::
SP
;
return
MFI
.
getObjectOffset
(
FI
)
;
}
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { unsigned Reg = I . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , I . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static rtx ix86_expand_sse_ptest ( const struct builtin_description * d , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; tree arg1 = CALL_EXPR_ARG ( exp , 1 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode mode0 = insn_data [ d -> icode ] . operand [ 0 ] . mode ; machine_mode mode1 = insn_data [ d -> icode ] . operand [ 1 ] . mode ; enum rtx_code comparison = d -> comparison ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( VECTOR_MODE_P ( mode1 ) ) op1 = safe_vector_operand ( op1 , mode1 ) ; target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const0_rtx ) ; target = gen_rtx_SUBREG ( QImode , target , 0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_data [ d -> icode ] . operand [ 0 ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_data [ d -> icode ] . operand [ 1 ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; emit_insn ( gen_rtx_SET ( VOIDmode , gen_rtx_STRICT_LOW_PART ( VOIDmode , target ) , gen_rtx_fmt_ee ( comparison , QImode , SET_DEST ( pat ) , const0_rtx ) ) ) ; return SUBREG_REG ( target ) ; } </s>

Subroutine of ix86_expand_builtin to take care of ptest insns .


<s> rtx frv_return_addr_rtx ( int count , rtx frame ) { if ( count != 0 ) return const0_rtx ; cfun -> machine -> frame_needed = 1 ; return gen_rtx_MEM ( Pmode , plus_constant ( Pmode , frame , 8 ) ) ; } </s>

A C expression whose value is RTL representing the value of the return address for the frame COUNT steps up from the current frame , after the prologue . FRAMEADDR is the frame pointer of the COUNT frame , or the frame pointer of the COUNT - 1 frame if ` RETURN_ADDR_IN_PREVIOUS_FRAME ' is defined . The value of the expression must always be the correct address when COUNT is zero , but may be ` NULL_RTX ' if there is not way to determine the return address of other frames .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static int get_jump_cycle ( int n ) { if ( n >= 12 ) return 0 ; n += ss . jump_cycle_index ; if ( n >= 12 ) n -= 12 ; return ss . jump_cycles [ n ] ; } </s>

Look up the jump cycle with index N. For an out-of-bounds N , we return 0 , so the caller does not specifically have to test for it .


"\nrs6000_preferred_reload_class, return %s, rclass = %s, "

Debug version of rs6000_preferred_reload_class .


<s> static void CreateReg ( OwningPtr < ARMOperand > & Op , unsigned RegNum , bool Writeback , SMLoc S , SMLoc E ) { Op . reset ( new ARMOperand ) ; Op -> Kind = Register ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Writeback = Writeback ; Op -> StartLoc = S ; Op -> EndLoc = E ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void mips_expand_vec_unpack ( rtx operands [ 2 ] , bool unsigned_p , bool high_p ) { machine_mode imode = GET_MODE ( operands [ 1 ] ) ; rtx ( * unpack ) ( rtx , rtx , rtx ) ; rtx ( * cmpFunc ) ( rtx , rtx , rtx ) ; rtx tmp , dest , zero ; if ( ISA_HAS_MSA ) { switch ( imode ) { case V4SImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_w ; else unpack = gen_msa_ilvr_w ; cmpFunc = gen_msa_clt_s_w ; break ; case V8HImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_h ; else unpack = gen_msa_ilvr_h ; cmpFunc = gen_msa_clt_s_h ; break ; case V16QImode : if ( BYTES_BIG_ENDIAN != high_p ) unpack = gen_msa_ilvl_b ; else unpack = gen_msa_ilvr_b ; cmpFunc = gen_msa_clt_s_b ; break ; default : gcc_unreachable ( ) ; break ; } if ( ! unsigned_p ) { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , operands [ 1 ] , CONST0_RTX ( imode ) ) ) ; } else tmp = force_reg ( imode , CONST0_RTX ( imode ) ) ; dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ 1 ] , tmp ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( GET_MODE ( operands [ 0 ] ) , dest ) ) ; return ; } switch ( imode ) { case V8QImode : if ( high_p ) unpack = gen_loongson_punpckhbh ; else unpack = gen_loongson_punpcklbh ; cmpFunc = gen_loongson_pcmpgtb ; break ; case V4HImode : if ( high_p ) unpack = gen_loongson_punpckhhw ; else unpack = gen_loongson_punpcklhw ; cmpFunc = gen_loongson_pcmpgth ; break ; default : gcc_unreachable ( ) ; } zero = force_reg ( imode , CONST0_RTX ( imode ) ) ; if ( unsigned_p ) tmp = zero ; else { tmp = gen_reg_rtx ( imode ) ; emit_insn ( cmpFunc ( tmp , zero , operands [ 1 ] ) ) ; } dest = gen_reg_rtx ( imode ) ; emit_insn ( unpack ( dest , operands [ 1 ] , tmp ) ) ; emit_move_insn ( operands [ 0 ] , gen_lowpart ( GET_MODE ( operands [ 0 ] ) , dest ) ) ; } </s>

Expand an integral vector unpack operation .


<s>
bool
ARMTargetLowering
::
getPostIndexedAddressParts
(
SDNode
*
N
,
SDNode
*
Op
,
SDValue
&
Base
,
SDValue
&
Offset
,
ISD
::
MemIndexedMode
&
AM
,
SelectionDAG
&
DAG
)
const
{
EVT
VT
;
SDValue
Ptr
;
unsigned
Align
;
bool
isSEXTLoad
=
false
,
isNonExt
;
if
(
LoadSDNode
*
LD
=
dyn_cast
<
LoadSDNode
>
(
N
)
)
{
VT
=
LD
->
getMemoryVT
(
)
;
Ptr
=
LD
->
getBasePtr
(
)
;
Align
=
LD
->
getAlignment
(
)
;
isSEXTLoad
=
LD
->
getExtensionType
(
)
==
ISD
::
SEXTLOAD
;
isNonExt
=
LD
->
getExtensionType
(
)
==
ISD
::
NON_EXTLOAD
;
}
else
if
(
StoreSDNode
*
ST
=
dyn_cast
<
StoreSDNode
>
(
N
)
)
{
VT
=
ST
->
getMemoryVT
(
)
;
Ptr
=
ST
->
getBasePtr
(
)
;
Align
=
ST
->
getAlignment
(
)
;
isNonExt
=
!
ST
->
isTruncatingStore
(
)
;
}
else
return
false
;
if
(
Subtarget
->
isThumb1Only
(
)
)
{
assert
(
Op
->
getValueType
(
0
)
==
MVT
::
i32
&&
"Non-i32 post-inc op?!"
)
;
if
(
Op
->
getOpcode
(
)
!=
ISD
::
ADD
||
!
isNonExt
)
return
false
;
auto
*
RHS
=
dyn_cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
if
(
!
RHS
||
RHS
->
getZExtValue
(
)
!=
4
)
return
false
;
Offset
=
Op
->
getOperand
(
1
)
;
Base
=
Op
->
getOperand
(
0
)
;
AM
=
ISD
::
POST_INC
;
return
true
;
}
bool
isInc
;
bool
isLegal
=
false
;
if
(
VT
.
isVector
(
)
)
isLegal
=
Subtarget
->
hasMVEIntegerOps
(
)
&&
getMVEIndexedAddressParts
(
Op
,
VT
,
Align
,
isSEXTLoad
,
Subtarget
->
isLittle
(
)
,
Base
,
Offset
,
isInc
,
DAG
)
;
else
{
if
(
Subtarget
->
isThumb2
(
)
)
isLegal
=
getT2IndexedAddressParts
(
Op
,
VT
,
isSEXTLoad
,
Base
,
Offset
,
isInc
,
DAG
)
;
else
isLegal
=
getARMIndexedAddressParts
(
Op
,
VT
,
isSEXTLoad
,
Base
,
Offset
,
isInc
,
DAG
)
;
}
if
(
!
isLegal
)
return
false
;
if
(
Ptr
!=
Base
)
{
if
(
Ptr
==
Offset
&&
Op
->
getOpcode
(
)
==
ISD
::
ADD
&&
!
Subtarget
->
isThumb2
(
)
)
std
::
swap
(
Base
,
Offset
)
;
if
(
Ptr
!=
Base
)
return
false
;
}
AM
=
isInc
ISD
::
POST_INC
:
ISD
::
POST_DEC
;
return
true
;
}
</s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool IsIEEEMode = MFI -> getMode ( ) . IEEE ; bool HasNSZ = MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; MachineOperand * CurrentKnownM0Val = nullptr ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( CurrentKnownM0Val && MI . modifiesRegister ( AMDGPU :: M0 , TRI ) ) CurrentKnownM0Val = nullptr ; if ( IsIEEEMode || ( ! HasNSZ && ! MI . getFlag ( MachineInstr :: FmNsz ) ) || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } if ( MI . getOperand ( 0 ) . getReg ( ) == AMDGPU :: M0 ) { MachineOperand & NewM0Val = MI . getOperand ( 1 ) ; if ( CurrentKnownM0Val && CurrentKnownM0Val -> isIdenticalTo ( NewM0Val ) ) { MI . eraseFromParent ( ) ; continue ; } CurrentKnownM0Val = ( NewM0Val . isReg ( ) && NewM0Val . getReg ( ) . isPhysical ( ) ) ? nullptr : & NewM0Val ; continue ; } MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) || OpToFold . isGlobal ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! OpToFold . getReg ( ) . isVirtual ( ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! Dst . getReg ( ) . isVirtual ( ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned GBZ80InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const GBZ80TargetMachine & TM = static_cast < const GBZ80TargetMachine & > ( MF . getTarget ( ) ) ; const GBZ80Subtarget & STI = MF . getSubtarget < GBZ80Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


"the layout of aggregates containing vectors with"

" %d-byte alignment has changed in GCC 5"

Previous GCC releases forced all vector types to have 16-byte alignment .


<s> rtx scalar_chain :: convert_compare ( rtx op1 , rtx op2 , rtx_insn * insn ) { rtx src , tmp ; if ( op2 != const0_rtx ) { convert_op ( & op1 , insn ) ; convert_op ( & op2 , insn ) ; if ( MEM_P ( op1 ) && MEM_P ( op2 ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , op1 ) , insn ) ; src = tmp ; } else src = op1 ; src = gen_rtx_XOR ( vmode , src , op2 ) ; } else if ( GET_CODE ( op1 ) == AND && GET_CODE ( XEXP ( op1 , 0 ) ) == NOT ) { rtx op11 = XEXP ( XEXP ( op1 , 0 ) , 0 ) ; rtx op12 = XEXP ( op1 , 1 ) ; convert_op ( & op11 , insn ) ; convert_op ( & op12 , insn ) ; if ( ! REG_P ( op11 ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , op11 ) , insn ) ; op11 = tmp ; } src = gen_rtx_AND ( vmode , gen_rtx_NOT ( vmode , op11 ) , op12 ) ; } else if ( GET_CODE ( op1 ) == AND ) { rtx op11 = XEXP ( op1 , 0 ) ; rtx op12 = XEXP ( op1 , 1 ) ; convert_op ( & op11 , insn ) ; convert_op ( & op12 , insn ) ; if ( ! REG_P ( op11 ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , op11 ) , insn ) ; op11 = tmp ; } return gen_rtx_UNSPEC ( CCmode , gen_rtvec ( 2 , op11 , op12 ) , UNSPEC_PTEST ) ; } else { convert_op ( & op1 , insn ) ; src = op1 ; } if ( ! REG_P ( src ) ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_rtx_SET ( tmp , src ) , insn ) ; src = tmp ; } if ( vmode == V2DImode ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_vec_interleave_lowv2di ( tmp , src , src ) , insn ) ; src = tmp ; } else if ( vmode == V4SImode ) { tmp = gen_reg_rtx ( vmode ) ; emit_insn_before ( gen_sse2_pshufd ( tmp , src , const0_rtx ) , insn ) ; src = tmp ; } return gen_rtx_UNSPEC ( CCmode , gen_rtvec ( 2 , src , src ) , UNSPEC_PTEST ) ; } </s>


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } if ( emitPseudoExpansionLowering ( OutStreamer , MI ) ) return ; MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst0 ; MCInstLowering . Lower ( I ++ , TmpInst0 ) ; if ( ! OutStreamer . hasRawTextSupport ( ) ) { switch ( TmpInst0 . getOpcode ( ) ) { case Mips :: DSLL : case Mips :: DSRL : case Mips :: DSRA : Mips :: LowerLargeShift ( TmpInst0 ) ; break ; case Mips :: DEXT : case Mips :: DINS : Mips :: LowerDextDins ( TmpInst0 ) ; } } OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Mips Mips 128 Mips::DSLL Mips::DSRL Mips::DSRA Mips::LowerLargeShift Mips::DEXT Mips::DINS Mips::LowerDextDins


<s> static const char * gen_prefix ( tree decl ) { if ( DECL_ONE_ONLY ( decl ) ) return NULL ; if ( has_attr ( "section" , decl ) ) return NULL ; if ( has_section_name ( ".lowtext" , decl ) ) return NULL ; if ( has_attr ( ATTR_LOWER , decl ) ) return lower_prefix ; if ( ! msp430x ) return NULL ; if ( has_attr ( ATTR_UPPER , decl ) ) return upper_prefix ; if ( has_attr ( ATTR_EITHER , decl ) ) return either_prefix ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { if ( msp430_code_region == MSP430_REGION_LOWER ) return lower_prefix ; if ( msp430_code_region == MSP430_REGION_UPPER ) return upper_prefix ; if ( msp430_code_region == MSP430_REGION_EITHER ) return either_prefix ; } else { if ( msp430_data_region == MSP430_REGION_LOWER ) return lower_prefix ; if ( msp430_data_region == MSP430_REGION_UPPER ) return upper_prefix ; if ( msp430_data_region == MSP430_REGION_EITHER ) return either_prefix ; } return NULL ; } </s>

Generate a prefix for a section name , based upon the region into which the object should be placed .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: EXTRACTURP : return "HexagonISD::EXTRACTURP" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: INSERTRP : return "HexagonISD::INSERTRP" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: PACKHL : return "HexagonISD::PACKHL" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VCOMBINE : return "HexagonISD::VCOMBINE" ; case HexagonISD :: VPACKE : return "HexagonISD::VPACKE" ; case HexagonISD :: VPACKO : return "HexagonISD::VPACKO" ; case HexagonISD :: VASL : return "HexagonISD::VASL" ; case HexagonISD :: VASR : return "HexagonISD::VASR" ; case HexagonISD :: VLSR : return "HexagonISD::VLSR" ; case HexagonISD :: VSPLAT : return "HexagonISD::VSPLAT" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::EXTRACTURP "HexagonISD::EXTRACTURP" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::INSERTRP "HexagonISD::INSERTRP" HexagonISD::JT "HexagonISD::JT" HexagonISD::PACKHL "HexagonISD::PACKHL" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VCOMBINE "HexagonISD::VCOMBINE" HexagonISD::VPACKE "HexagonISD::VPACKE" HexagonISD::VPACKO "HexagonISD::VPACKO" HexagonISD::VASL "HexagonISD::VASL" HexagonISD::VASR "HexagonISD::VASR" HexagonISD::VLSR "HexagonISD::VLSR" HexagonISD::VSPLAT "HexagonISD::VSPLAT" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::OP_END


<s> OperandMatchResultTy MSP430AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { auto Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) . lower ( ) ; RegNo = MatchRegisterName ( Name ) ; if ( RegNo == MSP430 :: NoRegister ) { RegNo = MatchRegisterAltName ( Name ) ; if ( RegNo == MSP430 :: NoRegister ) return MatchOperand_NoMatch ; } AsmToken const & T = getParser ( ) . getTok ( ) ; StartLoc = T . getLoc ( ) ; EndLoc = T . getEndLoc ( ) ; getLexer ( ) . Lex ( ) ; return MatchOperand_Success ; } return MatchOperand_ParseFail ; } </s>

tryParseRegister - parse one register if possible


<s> static void tilegx_output_mi_thunk ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { const char * fnname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( thunk_fndecl ) ) ; rtx this_rtx , funexp , addend ; rtx_insn * insn ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this_rtx = gen_rtx_REG ( Pmode , 1 ) ; else this_rtx = gen_rtx_REG ( Pmode , 0 ) ; if ( ! ( delta >= - 32868 && delta <= 32767 ) ) { addend = gen_rtx_REG ( Pmode , 29 ) ; emit_move_insn ( addend , GEN_INT ( delta ) ) ; } else addend = GEN_INT ( delta ) ; if ( TARGET_32BIT ) emit_insn ( gen_addsi3 ( this_rtx , this_rtx , addend ) ) ; else emit_insn ( gen_adddi3 ( this_rtx , this_rtx , addend ) ) ; if ( vcall_offset ) { rtx tmp ; tmp = gen_rtx_REG ( Pmode , 29 ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; if ( ! ( vcall_offset >= - 32868 && vcall_offset <= 32767 ) ) { addend = gen_rtx_REG ( Pmode , 28 ) ; emit_move_insn ( addend , GEN_INT ( vcall_offset ) ) ; } else addend = GEN_INT ( vcall_offset ) ; if ( TARGET_32BIT ) emit_insn ( gen_addsi3 ( tmp , tmp , addend ) ) ; else emit_insn ( gen_adddi3 ( tmp , tmp , addend ) ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp ) ) ; if ( TARGET_32BIT ) emit_insn ( gen_addsi3 ( this_rtx , this_rtx , tmp ) ) ; else emit_insn ( gen_adddi3 ( this_rtx , this_rtx , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; assemble_end_function ( thunk_fndecl , fnname ) ; reload_completed = 0 ; } </s>


<s> static void mips_reorg_process_insns ( void ) { rtx_insn * insn , * last_insn , * subinsn , * next_insn ; rtx lo_reg , delayed_reg ; int hilo_delay ; split_all_insns_noflow ( ) ; cfun -> machine -> ignore_hazard_length_p = true ; shorten_branches ( get_insns ( ) ) ; cfun -> machine -> all_noreorder_p = true ; if ( TARGET_MIPS16 ) cfun -> machine -> all_noreorder_p = false ; if ( ! TARGET_EXPLICIT_RELOCS ) cfun -> machine -> all_noreorder_p = false ; if ( crtl -> profile ) cfun -> machine -> all_noreorder_p = false ; if ( TARGET_FIX_VR4120 || TARGET_FIX_RM7000 || TARGET_FIX_24K || TARGET_MIPS5900 ) cfun -> machine -> all_noreorder_p = false ; if ( TARGET_FIX_VR4130 && ! ISA_HAS_MACCHI ) cfun -> machine -> all_noreorder_p = false ; mips_offset_table htab ( 37 ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = NEXT_INSN ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) if ( USEFUL_INSN_P ( subinsn ) ) { rtx body = PATTERN ( insn ) ; int noperands = asm_noperands ( body ) ; if ( noperands >= 0 ) { rtx * ops = XALLOCAVEC ( rtx , noperands ) ; bool * used = XALLOCAVEC ( bool , noperands ) ; const char * string = decode_asm_operands ( body , ops , NULL , NULL , NULL , NULL ) ; get_referenced_operands ( string , used , noperands ) ; for ( int i = 0 ; i < noperands ; ++ i ) if ( used [ i ] ) mips_record_lo_sums ( ops [ i ] , & htab ) ; } else mips_record_lo_sums ( PATTERN ( subinsn ) , & htab ) ; } last_insn = 0 ; hilo_delay = 2 ; delayed_reg = 0 ; lo_reg = gen_rtx_REG ( SImode , LO_REGNUM ) ; for ( insn = get_insns ( ) ; insn != 0 ; insn = next_insn ) { next_insn = NEXT_INSN ( insn ) ; if ( USEFUL_INSN_P ( insn ) ) { if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { FOR_EACH_SUBINSN ( subinsn , insn ) if ( INSN_P ( subinsn ) ) { if ( mips_orphaned_high_part_p ( & htab , subinsn ) ) { PATTERN ( subinsn ) = gen_nop ( ) ; INSN_CODE ( subinsn ) = CODE_FOR_nop ; } mips_avoid_hazard ( last_insn , subinsn , & hilo_delay , & delayed_reg , lo_reg ) ; } last_insn = insn ; } else { if ( mips_orphaned_high_part_p ( & htab , insn ) ) delete_insn ( insn ) ; else if ( recog_memoized ( insn ) == CODE_FOR_r10k_cache_barrier && last_insn && JUMP_P ( SEQ_BEGIN ( last_insn ) ) && INSN_ANNULLED_BRANCH_P ( SEQ_BEGIN ( last_insn ) ) ) delete_insn ( insn ) ; else { mips_avoid_hazard ( last_insn , insn , & hilo_delay , & delayed_reg , lo_reg ) ; last_insn = insn ; } } } } } </s>

Go through the instruction stream and insert nops where necessary . Also delete any high-part relocations whose partnering low parts are now all dead . See if the whole function can then be put into .set noreorder and .set nomacro .


<s> static std :: unique_ptr < ARMOperand > CreateMem ( unsigned BaseRegNum , const MCConstantExpr * OffsetImm , unsigned OffsetRegNum , ARM_AM :: ShiftOpc ShiftType , unsigned ShiftImm , unsigned Alignment , bool isNegative , SMLoc S , SMLoc E , SMLoc AlignmentLoc = SMLoc ( ) ) { auto Op = make_unique < ARMOperand > ( k_Memory ) ; Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return Op ; } </s>


<s> void ix86_fixup_binary_operands_no_copy ( enum rtx_code code , enum machine_mode mode , rtx operands [ ] ) { rtx dst = ix86_fixup_binary_operands ( code , mode , operands ) ; gcc_assert ( dst == operands [ 0 ] ) ; } </s>

Similarly , but assume that the destination has already been set up properly .


<s> const char * umips_output_save_restore ( bool save_p , rtx pattern ) { static char buffer [ 300 ] ; char * s ; int n ; HOST_WIDE_INT offset ; rtx base , mem , set , last_set , last_reg ; gcc_assert ( umips_save_restore_pattern_p ( save_p , pattern ) ) ; s = strcpy ( buffer , save_p ? "swm\t" : "lwm\t" ) ; s += strlen ( s ) ; n = XVECLEN ( pattern , 0 ) ; set = XVECEXP ( pattern , 0 , 0 ) ; mem = save_p ? SET_DEST ( set ) : SET_SRC ( set ) ; mips_split_plus ( XEXP ( mem , 0 ) , & base , & offset ) ; last_set = XVECEXP ( pattern , 0 , n - 1 ) ; last_reg = save_p ? SET_SRC ( last_set ) : SET_DEST ( last_set ) ; if ( REGNO ( last_reg ) == 31 ) n -- ; gcc_assert ( n <= 9 ) ; if ( n == 0 ) ; else if ( n == 1 ) s += sprintf ( s , "%s," , reg_names [ 16 ] ) ; else if ( n < 9 ) s += sprintf ( s , "%s-%s," , reg_names [ 16 ] , reg_names [ 15 + n ] ) ; else if ( n == 9 ) s += sprintf ( s , "%s-%s,%s," , reg_names [ 16 ] , reg_names [ 23 ] , reg_names [ 30 ] ) ; if ( REGNO ( last_reg ) == 31 ) s += sprintf ( s , "%s," , reg_names [ 31 ] ) ; s += sprintf ( s , "%d(%s)" , ( int ) offset , reg_names [ REGNO ( base ) ] ) ; return buffer ; } </s>

Return the assembly instruction for microMIPS LWM or SWM . SAVE_P and PATTERN are as for umips_save_restore_pattern_p .


<s> void MipsAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { if ( MI -> isDebugValue ( ) ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; PrintDebugValueComment ( MI , OS ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( OutStreamer , & * I ) ) continue ; MCInst TmpInst0 ; MCInstLowering . Lower ( I , TmpInst0 ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>


<s> bool M88kFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int64_t CurOffset = - 4 ; for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; if ( M88k :: GPRRCRegClass . contains ( Reg ) ) { CS . setFrameIdx ( MFI . CreateFixedSpillStackObject ( 4 , CurOffset ) ) ; CurOffset -= 4 ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; Align Alignment = TRI -> getSpillAlign ( * RC ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; Alignment = std :: min ( Alignment , getStackAlign ( ) ) ; CS . setFrameIdx ( MFI . CreateSpillStackObject ( Size , Alignment ) ) ; } } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static rtx aarch64_expand_sve_const_pred_trn ( rtx target , rtx_vector_builder & builder , unsigned int elt_size , unsigned int permute_size ) { unsigned int a_elt_size = GET_MODE_SIZE ( DImode ) ; unsigned int b_elt_size = GET_MODE_SIZE ( DImode ) ; for ( unsigned int i = 0 ; i < builder . encoded_nelts ( ) ; i += elt_size ) if ( INTVAL ( builder . elt ( i ) ) != 0 ) { if ( i & permute_size ) b_elt_size |= i - permute_size ; else a_elt_size |= i ; } a_elt_size &= - a_elt_size ; b_elt_size &= - b_elt_size ; rtx_vector_builder a_builder ( VNx16BImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; rtx_vector_builder b_builder ( VNx16BImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; unsigned int nelts = builder . encoded_nelts ( ) ; for ( unsigned int i = 0 ; i < nelts ; ++ i ) if ( i & ( elt_size - 1 ) ) { a_builder . quick_push ( const0_rtx ) ; b_builder . quick_push ( const0_rtx ) ; } else if ( ( i & permute_size ) == 0 ) { a_builder . quick_push ( builder . elt ( i ) ) ; b_builder . quick_push ( builder . elt ( i + permute_size ) ) ; } else { if ( a_elt_size > permute_size ) a_builder . quick_push ( const0_rtx ) ; else a_builder . quick_push ( a_builder . elt ( i - a_elt_size ) ) ; if ( b_elt_size > permute_size ) b_builder . quick_push ( const0_rtx ) ; else b_builder . quick_push ( b_builder . elt ( i - b_elt_size ) ) ; } a_builder . finalize ( ) ; b_builder . finalize ( ) ; rtx_insn * last = get_last_insn ( ) ; rtx a = aarch64_expand_sve_const_pred_1 ( NULL_RTX , a_builder , false ) ; if ( ! a ) return NULL_RTX ; rtx b = a ; if ( a_builder != b_builder ) { b = aarch64_expand_sve_const_pred_1 ( NULL_RTX , b_builder , false ) ; if ( ! b ) { delete_insns_since ( last ) ; return NULL_RTX ; } } machine_mode mode = aarch64_sve_pred_mode ( permute_size ) . require ( ) ; target = aarch64_target_reg ( target , mode ) ; emit_insn ( gen_aarch64_sve ( UNSPEC_TRN1 , mode , target , gen_lowpart ( mode , a ) , gen_lowpart ( mode , b ) ) ) ; return target ; } </s>

BUILDER is a constant predicate in which the index of every set bit is a multiple of ELT_SIZE ( which is < = 8 ) . Try to load the constant using a TRN1 of size PERMUTE_SIZE , which is > = ELT_SIZE . Return the register on success , otherwise return null . Use TARGET as the register if nonnull and convenient .


<s> bool VideoCore4FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { return false ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void OR1KRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> const AArch64AuthMCExpr * AArch64AuthMCExpr :: create ( const MCExpr * Expr , uint16_t Discriminator , AArch64PACKey :: ID Key , bool HasAddressDiversity , MCContext & Ctx ) { return new ( Ctx ) AArch64AuthMCExpr ( Expr , Discriminator , Key , HasAddressDiversity ) ; } </s>


<s>
static
void
ix86_function_specific_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
char
*
target_string
=
ix86_target_string
(
ptr
->
x_ix86_isa_flags
,
ptr
->
x_ix86_isa_flags2
,
ptr
->
x_target_flags
,
ptr
->
x_ix86_target_flags
,
,
,
ptr
->
x_ix86_fpmath
,
false
,
true
)
;
gcc_assert
(
ptr
->
arch
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*sarch = %d (%s)\n"
,
indent
,
""
,
ptr
->
arch
,
processor_names
[
ptr
->
arch
]
)
;
gcc_assert
(
ptr
->
tune
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*stune = %d (%s)\n"
,
indent
,
""
,
ptr
->
tune
,
processor_names
[
ptr
->
tune
]
)
;
fprintf
(
file
,
"%*sbranch_cost = %d\n"
,
indent
,
""
,
ptr
->
branch_cost
)
;
if
(
target_string
)
{
fprintf
(
file
,
"%*s%s\n"
,
indent
,
""
,
target_string
)
;
free
(
target_string
)
;
}
}
</s>


"this operation requires the RVV ISA extension"

"you can enable RVV using the command-line"

" option %<-march%>, or by using the %<target%>"

Report when we try to do something that requires vector when vector is disabled . This is an error of last resort and is n't very high-quality . It usually involves attempts to measure the vector length in some way .


<s> EVT HSAILTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static void note_invalid_constants ( rtx_insn * insn , HOST_WIDE_INT address , int do_pushes ) { int opno ; extract_constrain_insn ( insn ) ; if ( recog_data . n_alternatives == 0 ) return ; preprocess_constraints ( insn ) ; const operand_alternative * op_alt = which_op_alt ( ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] != OP_IN ) continue ; if ( op_alt [ opno ] . memory_ok ) { rtx op = recog_data . operand [ opno ] ; if ( CONSTANT_P ( op ) ) { if ( do_pushes ) push_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , op ) ; } else if ( MEM_P ( op ) && GET_CODE ( XEXP ( op , 0 ) ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( XEXP ( op , 0 ) ) ) { if ( do_pushes ) { rtx cop = avoid_constant_pool_reference ( op ) ; if ( op == cop ) cop = get_pool_constant ( XEXP ( op , 0 ) ) ; push_minipool_fix ( insn , address , recog_data . operand_loc [ opno ] , recog_data . operand_mode [ opno ] , cop ) ; } } } } return ; } </s>

Scan INSN and note any of its operands that need fixing . If DO_PUSHES is false we do not actually push any of the fixups needed . The function returns TRUE if any fixups were needed/pushed . This is used by arm_memory_load_p ( ) which needs to know about loads of constants that will be converted into minipool loads .


<s> static rtx frv_expand_set_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; if ( ! frv_check_constant_argument ( icode , 1 , op0 ) ) return NULL_RTX ; target = frv_legitimize_target ( icode , target ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take a single , constant argument . At the moment , only MHDSETS falls into this category .


<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l' : case 'x' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> const M88kRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


Remember to generate a branch island for far calls to the given function .


<s> static int h8300_saveall_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; a = lookup_attribute ( "saveall" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return nonzero if FUNC is a saveall function as specified by the `` saveall '' attribute .


<s> static rtx ix86_load_bounds ( rtx slot , rtx ptr , rtx slot_no ) { rtx reg = gen_reg_rtx ( BNDmode ) ; rtx addr ; addr = ix86_get_arg_address_for_bt ( slot , slot_no , arg_pointer_rtx ) ; if ( ! ptr ) { gcc_assert ( MEM_P ( slot ) ) ; ptr = copy_addr_to_reg ( slot ) ; } if ( ! register_operand ( ptr , Pmode ) ) ptr = ix86_zero_extend_to_Pmode ( ptr ) ; emit_insn ( BNDmode == BND64mode ? gen_bnd64_ldx ( reg , addr , ptr ) : gen_bnd32_ldx ( reg , addr , ptr ) ) ; return reg ; } </s>

Expand pass uses this hook to load bounds for function parameter PTR passed in SLOT in case its bounds are not passed in a register . If SLOT is a memory , then bounds are loaded as for regular pointer loaded from memory . PTR may be NULL in case SLOT is a memory . In such case value of PTR ( if required ) may be loaded from SLOT . If SLOT is NULL or a register then SLOT_NO is an integer constant holding number of the target dependent special slot which should be used to obtain bounds . Return loaded bounds .


<s> static void emit_cfa_restores ( rtx cfa_restores ) { rtx_insn * insn = get_last_insn ( ) ; rtx * loc = & REG_NOTES ( insn ) ; while ( * loc ) loc = & XEXP ( * loc , 1 ) ; * loc = cfa_restores ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Append CFA_RESTORES to any existing REG_NOTES on the last insn .


<s> const uint16_t * MCS51RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const MCS51MachineFunctionInfo * AFI = MF -> getInfo < MCS51MachineFunctionInfo > ( ) ; return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ; } </s>


<s> static rtx_insn * rs6000_frame_related ( rtx_insn * insn , rtx reg , HOST_WIDE_INT val , rtx reg2 , rtx repl2 ) { rtx repl ; if ( REGNO ( reg ) == STACK_POINTER_REGNUM ) { gcc_checking_assert ( val == 0 ) ; repl = NULL_RTX ; } else repl = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ; rtx pat = PATTERN ( insn ) ; if ( ! repl && ! reg2 ) { if ( GET_CODE ( pat ) == PARALLEL ) for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( ! REG_P ( SET_SRC ( set ) ) || interesting_frame_related_regno ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; return insn ; } set_used_flags ( pat ) ; if ( GET_CODE ( pat ) == SET ) { if ( repl ) pat = simplify_replace_rtx ( pat , reg , repl ) ; if ( reg2 ) pat = simplify_replace_rtx ( pat , reg2 , repl2 ) ; } else if ( GET_CODE ( pat ) == PARALLEL ) { pat = shallow_copy_rtx ( pat ) ; XVEC ( pat , 0 ) = shallow_copy_rtvec ( XVEC ( pat , 0 ) ) ; for ( int i = 0 ; i < XVECLEN ( pat , 0 ) ; i ++ ) if ( GET_CODE ( XVECEXP ( pat , 0 , i ) ) == SET ) { rtx set = XVECEXP ( pat , 0 , i ) ; if ( repl ) set = simplify_replace_rtx ( set , reg , repl ) ; if ( reg2 ) set = simplify_replace_rtx ( set , reg2 , repl2 ) ; XVECEXP ( pat , 0 , i ) = set ; if ( ! REG_P ( SET_SRC ( set ) ) || interesting_frame_related_regno ( REGNO ( SET_SRC ( set ) ) ) ) RTX_FRAME_RELATED_P ( set ) = 1 ; } } else gcc_unreachable ( ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , copy_rtx_if_shared ( pat ) ) ; return insn ; } </s>

Add to 'insn ' a note which is PATTERN ( INSN ) but with REG replaced with ( plus : P ( reg 1 ) VAL ) , and with REG2 replaced with RREG if REG2 is not NULL . It would be nice if dwarf2out_frame_debug_expr could deduce these equivalences by itself so it was n't necessary to hold its hand so much . Do n't be tempted to always supply d2_f_d_e with the actual cfa register , ie . r31 when we are using a hard frame pointer . That fails when saving regs off r1 , and sched moves the r31 setup past the reg saves .


<s> rtx aarch64_gen_compare_reg ( RTX_CODE code , rtx x , rtx y ) { machine_mode mode = SELECT_CC_MODE ( code , x , y ) ; rtx cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_set_insn ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode .


<s> static bool umips_load_store_pair_p_1 ( bool load_p , bool swap_p , rtx first_reg , rtx mem1 , rtx mem2 ) { rtx base1 , base2 ; HOST_WIDE_INT offset1 , offset2 ; if ( ! MEM_P ( mem1 ) || ! MEM_P ( mem2 ) ) return false ; mips_split_plus ( XEXP ( mem1 , 0 ) , & base1 , & offset1 ) ; mips_split_plus ( XEXP ( mem2 , 0 ) , & base2 , & offset2 ) ; if ( ! REG_P ( base1 ) || ! rtx_equal_p ( base1 , base2 ) ) return false ; if ( load_p && REGNO ( first_reg ) == REGNO ( base1 ) ) return false ; if ( load_p && swap_p && REGNO ( first_reg ) + 1 == REGNO ( base1 ) ) return false ; if ( offset2 != offset1 + 4 ) return false ; if ( ! UMIPS_12BIT_OFFSET_P ( offset1 ) ) return false ; return true ; } </s>

Return true if MEM1 and MEM2 use the same base register , and the offset of MEM2 equals the offset of MEM1 plus 4 . FIRST_REG is the register into ( from ) which the contents of MEM1 will be loaded ( stored ) , depending on the value of LOAD_P . SWAP_P is true when the 1st and 2nd instructions are swapped .


<s>
int
rs6000_arg_partial_bytes
(
cumulative_args_t
cum_v
,
const
function_arg_info
&
arg
)
{
CUMULATIVE_ARGS
*
cum
=
get_cumulative_args
(
cum_v
)
;
bool
passed_in_gprs
=
true
;
int
ret
=
0
;
int
align_words
;
machine_mode
elt_mode
;
int
n_elts
;
rs6000_discover_homogeneous_aggregate
(
arg
.
mode
,
arg
.
type
,
&
elt_mode
,
&
n_elts
)
;
if
(
DEFAULT_ABI
==
ABI_V4
)
return
0
;
if
(
USE_ALTIVEC_FOR_ARG_P
(
cum
,
elt_mode
,
arg
.
named
)
)
{
if
(
TARGET_64BIT
&&
!
cum
->
prototype
&&
(
!
cum
->
libcall
||
!
FLOAT128_VECTOR_P
(
elt_mode
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
vregno
+
n_elts
>
ALTIVEC_ARG_MAX_REG
+
1
)
ret
=
(
ALTIVEC_ARG_MAX_REG
+
1
cum
->
vregno
)
*
16
;
}
if
(
TARGET_MACHO
&&
rs6000_darwin64_struct_check_p
(
arg
.
mode
,
arg
.
type
)
)
return
0
;
align_words
=
rs6000_parm_start
(
arg
.
mode
,
arg
.
type
,
cum
->
words
)
;
if
(
USE_FP_FOR_ARG_P
(
cum
,
elt_mode
)
&&
!
(
TARGET_AIX
&&
!
TARGET_ELF
&&
arg
.
aggregate_type_p
(
)
)
)
{
unsigned
long
n_fpreg
=
(
GET_MODE_SIZE
(
elt_mode
)
+
7
)
>>
3
;
if
(
arg
.
type
&&
(
cum
->
nargs_prototype
<=
0
||
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_XL_COMPAT
&&
align_words
>=
GP_ARG_NUM_REG
)
)
)
return
0
;
passed_in_gprs
=
false
;
if
(
cum
->
fregno
+
n_elts
*
n_fpreg
>
FP_ARG_MAX_REG
+
1
)
{
int
fpr
=
(
(
FP_ARG_MAX_REG
+
1
cum
->
fregno
)
*
MIN
(
8
,
GET_MODE_SIZE
(
elt_mode
)
)
)
;
int
fpr_words
=
fpr
/
(
TARGET_32BIT
4
:
8
)
;
if
(
align_words
+
fpr_words
<
GP_ARG_NUM_REG
)
passed_in_gprs
=
true
;
else
ret
=
fpr
;
}
}
if
(
passed_in_gprs
&&
align_words
<
GP_ARG_NUM_REG
&&
GP_ARG_NUM_REG
<
align_words
+
rs6000_arg_size
(
arg
.
mode
,
arg
.
type
)
)
ret
=
(
GP_ARG_NUM_REG
align_words
)
*
(
TARGET_32BIT
4
:
8
)
;
if
(
ret
!=
0
&&
TARGET_DEBUG_ARG
)
fprintf
(
stderr
,
"rs6000_arg_partial_bytes: %d\n"
,
ret
)
;
return
ret
;
}
</s>

For an arg passed partly in registers and partly in memory , this is the number of bytes passed in registers . For args passed entirely in registers or entirely in memory , zero . When an arg is described by a PARALLEL , perhaps using more than one register type , this function returns the number of bytes used by the first element of the PARALLEL .


<s> const unsigned * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return ( STI . isTargetIOS ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } </s>


<s> const SNESMCExpr * SNESMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool Negated , MCContext & Ctx ) { return new ( Ctx ) SNESMCExpr ( Kind , Expr , Negated ) ; } </s>


<s> bool ix86_gimple_fold_builtin ( gimple_stmt_iterator * gsi ) { gimple * stmt = gsi_stmt ( * gsi ) ; tree fndecl = gimple_call_fndecl ( stmt ) ; gcc_checking_assert ( fndecl && DECL_BUILT_IN_CLASS ( fndecl ) == BUILT_IN_MD ) ; int n_args = gimple_call_num_args ( stmt ) ; enum ix86_builtins fn_code = ( enum ix86_builtins ) DECL_FUNCTION_CODE ( fndecl ) ; tree decl = NULL_TREE ; tree arg0 , arg1 ; switch ( fn_code ) { case IX86_BUILTIN_TZCNT32 : decl = builtin_decl_implicit ( BUILT_IN_CTZ ) ; goto fold_tzcnt_lzcnt ; case IX86_BUILTIN_TZCNT64 : decl = builtin_decl_implicit ( BUILT_IN_CTZLL ) ; goto fold_tzcnt_lzcnt ; case IX86_BUILTIN_LZCNT32 : decl = builtin_decl_implicit ( BUILT_IN_CLZ ) ; goto fold_tzcnt_lzcnt ; case IX86_BUILTIN_LZCNT64 : decl = builtin_decl_implicit ( BUILT_IN_CLZLL ) ; goto fold_tzcnt_lzcnt ; fold_tzcnt_lzcnt : gcc_assert ( n_args == 1 ) ; arg0 = gimple_call_arg ( stmt , 0 ) ; if ( TREE_CODE ( arg0 ) == SSA_NAME && decl && gimple_call_lhs ( stmt ) ) { int prec = TYPE_PRECISION ( TREE_TYPE ( arg0 ) ) ; if ( ! expr_not_equal_to ( arg0 , wi :: zero ( prec ) ) ) return false ; location_t loc = gimple_location ( stmt ) ; gimple * g = gimple_build_call ( decl , 1 , arg0 ) ; gimple_set_location ( g , loc ) ; tree lhs = make_ssa_name ( integer_type_node ) ; gimple_call_set_lhs ( g , lhs ) ; gsi_insert_before ( gsi , g , GSI_SAME_STMT ) ; g = gimple_build_assign ( gimple_call_lhs ( stmt ) , NOP_EXPR , lhs ) ; gimple_set_location ( g , loc ) ; gsi_replace ( gsi , g , false ) ; return true ; } break ; case IX86_BUILTIN_BZHI32 : case IX86_BUILTIN_BZHI64 : gcc_assert ( n_args == 2 ) ; arg1 = gimple_call_arg ( stmt , 1 ) ; if ( tree_fits_uhwi_p ( arg1 ) && gimple_call_lhs ( stmt ) ) { unsigned int idx = tree_to_uhwi ( arg1 ) & 0xff ; arg0 = gimple_call_arg ( stmt , 0 ) ; if ( idx < TYPE_PRECISION ( TREE_TYPE ( arg0 ) ) ) break ; location_t loc = gimple_location ( stmt ) ; gimple * g = gimple_build_assign ( gimple_call_lhs ( stmt ) , arg0 ) ; gimple_set_location ( g , loc ) ; gsi_replace ( gsi , g , false ) ; return true ; } break ; case IX86_BUILTIN_PDEP32 : case IX86_BUILTIN_PDEP64 : case IX86_BUILTIN_PEXT32 : case IX86_BUILTIN_PEXT64 : gcc_assert ( n_args == 2 ) ; arg1 = gimple_call_arg ( stmt , 1 ) ; if ( integer_all_onesp ( arg1 ) && gimple_call_lhs ( stmt ) ) { location_t loc = gimple_location ( stmt ) ; arg0 = gimple_call_arg ( stmt , 0 ) ; gimple * g = gimple_build_assign ( gimple_call_lhs ( stmt ) , arg0 ) ; gimple_set_location ( g , loc ) ; gsi_replace ( gsi , g , false ) ; return true ; } break ; default : break ; } return false ; } </s>

Fold a MD builtin ( use ix86_fold_builtin for folding into constant ) in GIMPLE .


<s>
MCSymbol
*
M680x0MCInstLower
::
GetSymbolFromOperand
(
const
MachineOperand
&
MO
)
const
{
assert
(
(
MO
.
isGlobal
(
)
||
MO
.
isSymbol
(
)
||
MO
.
isMBB
(
)
)
&&
"Isn't a symbol reference"
)
;
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
MCSymbol
*
Sym
=
nullptr
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
MO
.
isGlobal
(
)
)
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
AsmPrinter
.
getNameWithPrefix
(
Name
,
GV
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
{
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
if
(
MO
.
isMBB
(
)
)
{
assert
(
Suffix
.
empty
(
)
)
;
Sym
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
}
Name
+=
Suffix
;
if
(
!
Sym
)
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> void ia64_split_tmode_move ( rtx operands [ ] ) { rtx in [ 2 ] , out [ 2 ] , insn ; rtx fixup [ 2 ] ; bool dead = false ; bool reversed = false ; if ( GET_CODE ( operands [ 1 ] ) == MEM && reg_overlap_mentioned_p ( operands [ 0 ] , operands [ 1 ] ) ) { rtx base = XEXP ( operands [ 1 ] , 0 ) ; while ( GET_CODE ( base ) != REG ) base = XEXP ( base , 0 ) ; if ( REGNO ( base ) == REGNO ( operands [ 0 ] ) ) reversed = true ; dead = true ; } if ( GET_CODE ( operands [ 0 ] ) == REG && GET_CODE ( operands [ 1 ] ) == REG && REGNO ( operands [ 0 ] ) == REGNO ( operands [ 1 ] ) + 1 ) reversed = true ; fixup [ 0 ] = ia64_split_tmode ( in , operands [ 1 ] , reversed , dead ) ; fixup [ 1 ] = ia64_split_tmode ( out , operands [ 0 ] , reversed , dead ) ; if ( GET_CODE ( EXP ) == MEM \ && ( GET_CODE ( XEXP ( EXP , 0 ) ) == POST_MODIFY \ || GET_CODE ( XEXP ( EXP , 0 ) ) == POST_INC \ || GET_CODE ( XEXP ( EXP , 0 ) ) == POST_DEC ) ) \ REG_NOTES ( INSN ) = gen_rtx_EXPR_LIST ( REG_INC , \ XEXP ( XEXP ( EXP , 0 ) , 0 ) , \ REG_NOTES ( INSN ) ) insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ 0 ] , in [ 0 ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ 0 ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ 0 ] ) ; insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ 1 ] , in [ 1 ] ) ) ; MAYBE_ADD_REG_INC_NOTE ( insn , in [ 1 ] ) ; MAYBE_ADD_REG_INC_NOTE ( insn , out [ 1 ] ) ; if ( fixup [ 0 ] ) emit_insn ( fixup [ 0 ] ) ; if ( fixup [ 1 ] ) emit_insn ( fixup [ 1 ] ) ; } </s>

Split a TImode or TFmode move instruction after reload . This is used by * movtf_internal and * movti_internal .


<s>
const
char
*
avr_out_movmem
(
rtx_insn
*
insn
ATTRIBUTE_UNUSED
,
rtx
*
op
,
int
*
plen
)
{
addr_space_t
as
=
(
addr_space_t
)
INTVAL
(
op
[
0
]
)
;
machine_mode
loop_mode
=
GET_MODE
(
op
[
1
]
)
;
bool
sbiw_p
=
test_hard_reg_class
(
ADDW_REGS
,
op
[
1
]
)
;
rtx
xop
[
3
]
;
if
(
plen
)
*
plen
=
0
;
xop
[
0
]
=
op
[
0
]
;
xop
[
1
]
=
op
[
1
]
;
xop
[
2
]
=
tmp_reg_rtx
;
avr_asm_len
(
"0:"
,
xop
,
plen
,
0
)
;
switch
(
as
)
{
default
:
gcc_unreachable
(
)
;
case
ADDR_SPACE_GENERIC
:
avr_asm_len
(
"ld %2,Z+"
,
xop
,
plen
,
1
)
;
break
;
case
ADDR_SPACE_FLASH
:
if
(
AVR_HAVE_LPMX
)
avr_asm_len
(
"lpm %2,Z+"
,
xop
,
plen
,
1
)
;
else
avr_asm_len
(
"lpm"
CR_TAB
"adiw r30,1"
,
xop
,
plen
,
2
)
;
break
;
case
ADDR_SPACE_FLASH1
:
case
ADDR_SPACE_FLASH2
:
case
ADDR_SPACE_FLASH3
:
case
ADDR_SPACE_FLASH4
:
case
ADDR_SPACE_FLASH5
:
if
(
AVR_HAVE_ELPMX
)
avr_asm_len
(
"elpm %2,Z+"
,
xop
,
plen
,
1
)
;
else
avr_asm_len
(
"elpm"
CR_TAB
"adiw r30,1"
,
xop
,
plen
,
2
)
;
break
;
}
avr_asm_len
(
"st X+,%2"
,
xop
,
plen
,
1
)
;
if
(
QImode
==
loop_mode
)
{
avr_asm_len
(
"dec %1"
,
xop
,
plen
,
1
)
;
}
else
if
(
sbiw_p
)
{
avr_asm_len
(
"sbiw %1,1"
,
xop
,
plen
,
1
)
;
}
else
{
avr_asm_len
(
"subi %A1,1"
CR_TAB
"sbci %B1,0"
,
xop
,
plen
,
2
)
;
}
return
avr_asm_len
(
"brne 0b"
,
xop
,
plen
,
1
)
;
}
</s>

Print assembler for movmem_qi , movmem_hi insns ... $ 0 : Address Space $ 1 , $ 2 : Loop register Z : Source address X : Destination address


<s> static void frv_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { gcc_assert ( size == 4 ) ; fputs ( "\t.picptr\ttlsmoff(" , file ) ; output_addr_const ( file , plus_constant ( x , TLS_BIAS ) ) ; fputs ( ")" , file ) ; } </s>

This is called from dwarf2out.cc via TARGET_ASM_OUTPUT_DWARF_DTPREL . We need to emit DTP-relative relocations .


<s> static reg_class_t reduce_class ( reg_class_t original_class , reg_class_t limiting_class , reg_class_t returned_if_empty ) { HARD_REG_SET cc ; int i ; reg_class_t best = NO_REGS ; unsigned int best_size = 0 ; if ( original_class == limiting_class ) return original_class ; cc = reg_class_contents [ original_class ] & reg_class_contents [ limiting_class ] ; for ( i = 0 ; i < LIM_REG_CLASSES ; i ++ ) { if ( hard_reg_set_subset_p ( reg_class_contents [ i ] , cc ) ) if ( best_size < reg_class_size [ i ] ) { best = ( reg_class_t ) i ; best_size = reg_class_size [ i ] ; } } if ( best == NO_REGS ) return returned_if_empty ; return best ; } </s>

Given two register classes , find the largest intersection between them . If there is no intersection , return RETURNED_IF_EMPTY instead .


<s> static bool pa_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { if ( from == to ) return true ; if ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) ) return true ; if ( ! GET_MODE_SIZE ( from ) || ! GET_MODE_SIZE ( to ) ) return false ; if ( COMPLEX_MODE_P ( from ) || VECTOR_MODE_P ( from ) || COMPLEX_MODE_P ( to ) || VECTOR_MODE_P ( to ) ) return false ; if ( MAYBE_FP_REG_CLASS_P ( rclass ) ) return false ; if ( GET_MODE_SIZE ( to ) > UNITS_PER_WORD && GET_MODE_SIZE ( to ) > GET_MODE_SIZE ( from ) ) return false ; return true ; } </s>


<s> int m68hc11_valid_addressing_p ( rtx operand , enum machine_mode mode , int addr_mode ) { rtx base , offset ; switch ( GET_CODE ( operand ) ) { case MEM : if ( ( addr_mode & ADDR_INDIRECT ) && GET_MODE_SIZE ( mode ) <= 2 ) return m68hc11_valid_addressing_p ( XEXP ( operand , 0 ) , mode , addr_mode & ( ADDR_STRICT | ADDR_OFFSET ) ) ; return 0 ; case POST_INC : case PRE_INC : case POST_DEC : case PRE_DEC : if ( addr_mode & ADDR_INCDEC ) return m68hc11_valid_addressing_p ( XEXP ( operand , 0 ) , mode , addr_mode & ADDR_STRICT ) ; return 0 ; case PLUS : base = XEXP ( operand , 0 ) ; if ( GET_CODE ( base ) == MEM ) return 0 ; offset = XEXP ( operand , 1 ) ; if ( GET_CODE ( offset ) == MEM ) return 0 ; if ( GET_CODE ( base ) == REG && GET_CODE ( offset ) == REG ) { if ( ! ( addr_mode & ADDR_INDEXED ) ) return 0 ; addr_mode &= ADDR_STRICT ; if ( REGNO_OK_FOR_BASE_P2 ( REGNO ( base ) , addr_mode ) && REGNO_OK_FOR_INDEX_P2 ( REGNO ( offset ) , addr_mode ) ) return 1 ; if ( REGNO_OK_FOR_BASE_P2 ( REGNO ( offset ) , addr_mode ) && REGNO_OK_FOR_INDEX_P2 ( REGNO ( base ) , addr_mode ) ) return 1 ; return 0 ; } if ( ! ( addr_mode & ADDR_OFFSET ) ) return 0 ; if ( GET_CODE ( base ) == REG ) { if ( ! VALID_CONSTANT_OFFSET_P ( offset , mode ) ) return 0 ; if ( ! ( addr_mode & ADDR_STRICT ) ) return 1 ; return REGNO_OK_FOR_BASE_P2 ( REGNO ( base ) , 1 ) ; } if ( GET_CODE ( offset ) == REG ) { if ( ! VALID_CONSTANT_OFFSET_P ( base , mode ) ) return 0 ; if ( ! ( addr_mode & ADDR_STRICT ) ) return 1 ; return REGNO_OK_FOR_BASE_P2 ( REGNO ( offset ) , 1 ) ; } return 0 ; case REG : return REGNO_OK_FOR_BASE_P2 ( REGNO ( operand ) , addr_mode & ADDR_STRICT ) ; case CONST_INT : if ( addr_mode & ADDR_CONST ) return VALID_CONSTANT_OFFSET_P ( operand , mode ) ; return 0 ; default : return 0 ; } } </s>

Return 1 if the operand is a valid indexed addressing mode . For 68hc11 : n , r with n in [ 0 .. 255 ] and r in A_REGS class For 68hc12 : n , r no constraint on the constant , r in A_REGS class .


<s>
SDValue
SNESTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
SHL
:
case
ISD
::
SRA
:
case
ISD
::
SRL
:
case
ISD
::
ROTL
:
case
ISD
::
ROTR
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
return
LowerDivRem
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

SNES
SNES
"Don't know how to custom lower this!"
ISD::SHL
ISD::SRA
ISD::SRL
ISD::ROTL
ISD::ROTR
ISD::GlobalAddress
ISD::BlockAddress
ISD::BR_CC
ISD::SELECT_CC
ISD::SETCC
ISD::VASTART
ISD::SDIVREM
ISD::UDIVREM


<s> inline const AMDGPUSubtarget * AMDGPUTargetMachine :: getSubtargetImpl ( const Function & F ) const { if ( getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) return static_cast < const GCNTargetMachine * > ( this ) -> getSubtargetImpl ( F ) ; return static_cast < const R600TargetMachine * > ( this ) -> getSubtargetImpl ( F ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool ARMBaseRegisterInfo :: isInlineAsmReadOnlyReg ( const MachineFunction & MF , unsigned PhysReg ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , ARM :: PC ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , STI . getFramePointerReg ( ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved . test ( PhysReg ) ; } </s>

Returns true if PhysReg can not be written to in inline asm statements .


<s> Value * ARM64TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm64_ldaxp : Intrinsic :: arm64_ldxp ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldxr , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm64_ldaxr : Intrinsic :: arm64_ldxr ; Function * Ldxr = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldxr , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s>
SDValue
BlackfinTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AllocateStack
(
12
,
4
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_Blackfin
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
if
(
VA
.
isRegLoc
(
)
)
{
EVT
RegVT
=
VA
.
getLocVT
(
)
;
TargetRegisterClass
*
RC
=
VA
.
getLocReg
(
)
==
BF
::
P0
BF
::
PRegisterClass
:
BF
::
DRegisterClass
;
assert
(
RC
->
contains
(
VA
.
getLocReg
(
)
)
&&
"Unexpected regclass in CCState"
)
;
assert
(
RC
->
hasType
(
RegVT
)
&&
"Unexpected regclass in CCState"
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MF
.
getRegInfo
(
)
.
addLiveIn
(
VA
.
getLocReg
(
)
,
Reg
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Reg
,
RegVT
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
if
(
VA
.
getLocInfo
(
)
!=
CCValAssign
::
Full
)
ArgValue
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
ArgValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
else
{
assert
(
VA
.
isMemLoc
(
)
&&
"CCValAssign must be RegLoc or MemLoc"
)
;
unsigned
ObjSize
=
VA
.
getLocVT
(
)
.
getStoreSizeInBits
(
)
/
8
;
int
FI
=
MFI
->
CreateFixedObject
(
ObjSize
,
VA
.
getLocMemOffset
(
)
)
;
SDValue
FIN
=
DAG
.
getFrameIndex
(
FI
,
MVT
::
i32
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
dl
,
Chain
,
FIN
,
,
0
)
)
;
}
}
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == X86 :: CATCHRET ) { const Function & F = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( F . getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> unsigned X86RegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned FPDiff = TFI -> hasFP ( MF ) ? 1 : 0 ; switch ( RC -> getID ( ) ) { default : return 0 ; case X86 :: GR32RegClassID : return 4 - FPDiff ; case X86 :: GR64RegClassID : return 12 - FPDiff ; case X86 :: VR128RegClassID : return Is64Bit ? 10 : 4 ; case X86 :: VR64RegClassID : return 4 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool mep_vliw_mode_match ( rtx tgt ) { bool src_vliw = mep_vliw_function_p ( cfun -> decl ) ; bool tgt_vliw = INTVAL ( tgt ) ; return src_vliw == tgt_vliw ; } </s>

Irritatingly , the `` jsrv '' insn * toggles * PSW.OM rather than set it to one specific value . So the insn chosen depends on whether the source and destination modes match .


<s> void tilegx_expand_tablejump ( rtx op0 , rtx op1 ) { if ( flag_pic ) { rtx temp = gen_reg_rtx ( Pmode ) ; rtx temp2 = gen_reg_rtx ( Pmode ) ; tilegx_compute_pcrel_address ( temp , gen_rtx_LABEL_REF ( Pmode , op1 ) ) ; emit_move_insn ( temp2 , gen_rtx_PLUS ( Pmode , convert_to_mode ( Pmode , op0 , false ) , temp ) ) ; op0 = temp2 ; } emit_jump_insn ( gen_tablejump_aux ( op0 , op1 ) ) ; } </s>


<s> static tree nds32_merge_decl_attributes ( tree olddecl , tree newdecl ) { tree combined_attrs ; combined_attrs = merge_attributes ( DECL_ATTRIBUTES ( olddecl ) , DECL_ATTRIBUTES ( newdecl ) ) ; if ( TREE_CODE ( olddecl ) == FUNCTION_DECL ) { nds32_check_isr_attrs_conflict ( olddecl , combined_attrs ) ; } return combined_attrs ; } </s>

Add some checking after merging attributes .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


"Only expecting s register spills during emergencies"

Spill the register so it can be used by the register scavenger .


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , DAGCombinerInfo & DCI , unsigned & RefinementSteps ) const { EVT VT = Op . getValueType ( ) ; const char * RecipOp ; if ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) RecipOp = "divf" ; else if ( ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) ) RecipOp = "vec-divf" ; else return SDValue ( ) ; TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue ( ) ; RefinementSteps = Recips . getRefinementSteps ( RecipOp ) ; return DCI . DAG . getNode ( X86ISD :: FRCP , SDLoc ( Op ) , VT , Op ) ; } </s>

Return a reciprocal estimate value for the input operand .


<s> static void ix86_avx256_split_vector_move_misalign ( rtx op0 , rtx op1 ) { rtx m ; rtx ( * extract ) ( rtx , rtx , rtx ) ; machine_mode mode ; if ( ( MEM_P ( op1 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_LOAD ) || ( MEM_P ( op0 ) && ! TARGET_AVX256_SPLIT_UNALIGNED_STORE ) ) { emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; return ; } rtx orig_op0 = NULL_RTX ; mode = GET_MODE ( op0 ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( mode != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; op1 = gen_lowpart ( V32QImode , op1 ) ; mode = V32QImode ; } break ; case MODE_VECTOR_FLOAT : break ; default : gcc_unreachable ( ) ; } switch ( mode ) { default : gcc_unreachable ( ) ; case E_V32QImode : extract = gen_avx_vextractf128v32qi ; mode = V16QImode ; break ; case E_V16HFmode : extract = gen_avx_vextractf128v16hf ; mode = V8HFmode ; break ; case E_V8SFmode : extract = gen_avx_vextractf128v8sf ; mode = V4SFmode ; break ; case E_V4DFmode : extract = gen_avx_vextractf128v4df ; mode = V2DFmode ; break ; } if ( MEM_P ( op1 ) ) { rtx r = gen_reg_rtx ( mode ) ; m = adjust_address ( op1 , mode , 0 ) ; emit_move_insn ( r , m ) ; m = adjust_address ( op1 , mode , 16 ) ; r = gen_rtx_VEC_CONCAT ( GET_MODE ( op0 ) , r , m ) ; emit_move_insn ( op0 , r ) ; } else if ( MEM_P ( op0 ) ) { m = adjust_address ( op0 , mode , 0 ) ; emit_insn ( extract ( m , op1 , const0_rtx ) ) ; m = adjust_address ( op0 , mode , 16 ) ; emit_insn ( extract ( m , copy_rtx ( op1 ) , const1_rtx ) ) ; } else gcc_unreachable ( ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; } </s>

Split 32-byte AVX unaligned load and store if needed .


<s> void printPCRelImm ( const MCInst * MI , uint64_t , unsigned OpNo , raw_ostream & O ) { printPCRelImm ( MI , OpNo , O ) ; } </s>


"End of MachineConstPropagator (Changed="

Run the analysis pass over a function and produce a dominator tree .


<s>
SDValue
MSP430TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
if
(
CallConv
==
CallingConv
::
MSP430_INTR
&&
!
Outs
.
empty
(
)
)
report_fatal_error
(
"ISRs cannot return any value"
)
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
AnalyzeReturnValues
(
CCInfo
,
RVLocs
,
Outs
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
unsigned
Opc
=
(
CallConv
==
CallingConv
::
MSP430_INTR
MSP430ISD
::
RETI_FLAG
:
MSP430ISD
::
RET_FLAG
)
;
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void PatmosFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetInstrInfo * TII = STC . getInstrInfo ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; MachineInstr * MI = emitSTC ( MF , MBB , MBBI , Patmos :: SFREEi ) ; if ( MI ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; unsigned stackSize = MFI . getStackSize ( ) ; if ( stackSize ) { if ( stackSize <= 0xFFF ) { MachineInstr * MI = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII -> get ( Patmos :: ADDi ) , Patmos :: RSP ) ) . addReg ( Patmos :: RSP ) . addImm ( stackSize ) ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; } else { MachineInstr * MI = AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII -> get ( Patmos :: ADDl ) , Patmos :: RSP ) ) . addReg ( Patmos :: RSP ) . addImm ( stackSize ) ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; } } } </s>

Patmos Patmos Patmos::SFREEi 0xFFF Patmos::ADDi Patmos::RSP Patmos::RSP Patmos::ADDl Patmos::RSP Patmos::RSP


<s> bool PatmosSubtarget :: enablePostRAScheduler ( ) const { return hasPostRAScheduler ( OptLevel ) ; } </s>

True if the subtarget should run a scheduler after register allocation .


"No space allowed between comma that separates operand entries"

ParseInstruction - Parse one assembly instruction .


"target %s %qs does not accept an argument"

"target %s %qs does not allow a negated form"

Parse ARG_STR which contains the definition of one target attribute . Show appropriate errors if any or return true if the attribute is valid . PRAGMA_OR_ATTR holds the string to use in error messages about whether we 're processing a target attribute or pragma .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
AArch64_SVE_VectorCall
:
report_fatal_error
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
Subtarget
->
isTargetWindows
(
)
&&
IsVarArg
)
return
CC_AArch64_Win64_VarArg
;
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
if
(
!
IsVarArg
)
return
CC_AArch64_DarwinPCS
;
return
Subtarget
->
isTargetILP32
(
)
CC_AArch64_DarwinPCS_ILP32_VarArg
:
CC_AArch64_DarwinPCS_VarArg
;
case
CallingConv
::
Win64
:
return
IsVarArg
CC_AArch64_Win64_VarArg
:
CC_AArch64_AAPCS
;
case
CallingConv
::
CFGuard_Check
:
return
CC_AArch64_Win64_CFGuard_Check
;
case
CallingConv
::
AArch64_VectorCall
:
return
CC_AArch64_AAPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static void aarch64_push_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment ) { rtx_insn * insn ; machine_mode mode = ( regno1 <= R30_REGNUM ) ? DImode : DFmode ; if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 2 ) ) = 1 ; RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , 1 ) ) = 1 ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Push registers numbered REGNO1 and REGNO2 to the stack , adjusting the stack pointer by ADJUSTMENT .


<s> void GCNPassConfig :: addPreRegAlloc ( ) { const AMDGPUSubtarget & ST = * getAMDGPUTargetMachine ( ) . getSubtargetImpl ( ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) { insertPass ( & MachineSchedulerID , & SIFixControlFlowLiveIntervalsID ) ; } if ( getOptLevel ( ) > CodeGenOpt :: None && ST . loadStoreOptEnabled ( ) ) { insertPass ( & MachineSchedulerID , & SILoadStoreOptimizerID ) ; insertPass ( & MachineSchedulerID , & RegisterCoalescerID ) ; } addPass ( createSIShrinkInstructionsPass ( ) , false ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static void ATTRIBUTE_UNUSED loongarch_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case 4 : fputs ( "\t.dtprelword\t" , file ) ; break ; case 8 : fputs ( "\t.dtpreldword\t" , file ) ; break ; default : gcc_unreachable ( ) ; } output_addr_const ( file , x ) ; fputs ( "+0x8000" , file ) ; } </s>


<s>
bool
ARMConstantIslands
::
isBBInRange
(
MachineInstr
*
MI
,
MachineBasicBlock
*
DestBB
,
unsigned
MaxDisp
)
{
unsigned
PCAdj
=
isThumb
4
:
8
;
unsigned
BrOffset
=
getOffsetOf
(
MI
)
+
PCAdj
;
unsigned
DestOffset
=
BBInfo
[
DestBB
->
getNumber
(
)
]
.
Offset
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Branch of destination "
<<
printMBBReference
(
*
DestBB
)
<<
" from "
<<
printMBBReference
(
*
MI
->
getParent
(
)
)
<<
" max delta="
<<
MaxDisp
<<
" from "
<<
getOffsetOf
(
MI
)
<<
" to "
<<
DestOffset
<<
" offset "
<<
int
(
DestOffset
BrOffset
)
<<
"\t"
<<
*
MI
)
;
if
(
BrOffset
<=
DestOffset
)
{
if
(
DestOffset
BrOffset
<=
MaxDisp
)
return
true
;
}
else
{
if
(
BrOffset
DestOffset
<=
MaxDisp
)
return
true
;
}
return
false
;
}
</s>

isBBInRange - Returns true if the distance between specific MI and specific BB can fit in MI 's displacement field .

ARM
ARM
4
8
"Branch of destination "
" from "
" max delta="
" from "
" to "
" offset "
"\t"


<s> bool TVMTargetLowering :: CanLowerReturn ( CallingConv :: ID , MachineFunction & , bool , const SmallVectorImpl < ISD :: OutputArg > & , LLVMContext & ) const { return true ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s> const Region * getRegionFor ( const MachineBasicBlock * MBB ) { const auto * ML = MLI . getLoopFor ( MBB ) ; const auto * WE = WEI . getExceptionFor ( MBB ) ; if ( ! ML && ! WE ) return nullptr ; if ( ( ML && ! WE ) || ( ML && WE && ML -> getNumBlocks ( ) < WE -> getNumBlocks ( ) ) ) { if ( LoopMap . count ( ML ) ) return LoopMap [ ML ] . get ( ) ; LoopMap [ ML ] = std :: make_unique < ConcreteRegion < MachineLoop >> ( ML ) ; return LoopMap [ ML ] . get ( ) ; } else { if ( ExceptionMap . count ( WE ) ) return ExceptionMap [ WE ] . get ( ) ; ExceptionMap [ WE ] = std :: make_unique < ConcreteRegion < WebAssemblyException >> ( WE ) ; return ExceptionMap [ WE ] . get ( ) ; } } </s>

Get the smallest region that contains a BasicBlock .


<s> void AlphaInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( RC == Alpha :: F4RCRegisterClass ) BuildMI ( MBB , MI , DL , get ( Alpha :: STS ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FrameIdx ) . addReg ( Alpha :: F31 ) ; else if ( RC == Alpha :: F8RCRegisterClass ) BuildMI ( MBB , MI , DL , get ( Alpha :: STT ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FrameIdx ) . addReg ( Alpha :: F31 ) ; else if ( RC == Alpha :: GPRCRegisterClass ) BuildMI ( MBB , MI , DL , get ( Alpha :: STQ ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FrameIdx ) . addReg ( Alpha :: F31 ) ; else abort ( ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void nvptx_globalize_label ( FILE * , const char * ) { } </s>

Implement TARGET_ASM_GLOBALIZE_LABEL by doing nothing .


<s> void neon_split_vcombine ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = REG_NREGS ( operands [ 1 ] ) ; rtx destlo , desthi ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( src2 == dest && src1 == dest + halfregs ) { rtx x = gen_rtx_SET ( destlo , operands [ 1 ] ) ; rtx y = gen_rtx_SET ( desthi , operands [ 2 ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x , y ) ) ) ; return ; } if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s> int arc_address_cost ( rtx addr , machine_mode , addr_space_t , bool speed ) { switch ( GET_CODE ( addr ) ) { case REG : return speed || satisfies_constraint_Rcq ( addr ) ? 0 : 1 ; case PRE_INC : case PRE_DEC : case POST_INC : case POST_DEC : case PRE_MODIFY : case POST_MODIFY : return ! speed ; case LABEL_REF : case SYMBOL_REF : case CONST : if ( TARGET_NPS_CMEM && cmem_address ( addr , SImode ) ) return 0 ; return COSTS_N_INSNS ( 1 ) ; case PLUS : { register rtx plus0 = XEXP ( addr , 0 ) ; register rtx plus1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) != MULT || ! CONST_INT_P ( XEXP ( plus0 , 1 ) ) || ( INTVAL ( XEXP ( plus0 , 1 ) ) != 2 && INTVAL ( XEXP ( plus0 , 1 ) ) != 4 ) ) ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return ( ! RTX_OK_FOR_OFFSET_P ( SImode , plus1 ) ? COSTS_N_INSNS ( 1 ) : speed ? 0 : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_O ( plus1 ) ) ? 0 : 1 ) ; case REG : return ( speed < 1 ? 0 : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_Rcq ( plus1 ) ) ? 0 : 1 ) ; case CONST : case SYMBOL_REF : case LABEL_REF : return COSTS_N_INSNS ( 1 ) ; default : break ; } break ; } default : break ; } return 4 ; } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s>
MCSymbol
*
TLCS900MCInstLower
::
GetExternalSymbolSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
;
}
</s>

Return the MCSymbol for the specified ExternalSymbol .


<s>
const
char
*
avr_out_cpymem
(
rtx_insn
*
insn
ATTRIBUTE_UNUSED
,
rtx
*
op
,
int
*
plen
)
{
addr_space_t
as
=
(
addr_space_t
)
INTVAL
(
op
[
0
]
)
;
machine_mode
loop_mode
=
GET_MODE
(
op
[
1
]
)
;
bool
sbiw_p
=
test_hard_reg_class
(
ADDW_REGS
,
op
[
1
]
)
;
rtx
xop
[
3
]
;
if
(
plen
)
*
plen
=
0
;
xop
[
0
]
=
op
[
0
]
;
xop
[
1
]
=
op
[
1
]
;
xop
[
2
]
=
tmp_reg_rtx
;
avr_asm_len
(
"0:"
,
xop
,
plen
,
0
)
;
switch
(
as
)
{
default
:
gcc_unreachable
(
)
;
case
ADDR_SPACE_GENERIC
:
avr_asm_len
(
"ld %2,Z+"
,
xop
,
plen
,
1
)
;
break
;
case
ADDR_SPACE_FLASH
:
if
(
AVR_HAVE_LPMX
)
avr_asm_len
(
"lpm %2,Z+"
,
xop
,
plen
,
1
)
;
else
avr_asm_len
(
"lpm"
CR_TAB
"adiw r30,1"
,
xop
,
plen
,
2
)
;
break
;
case
ADDR_SPACE_FLASH1
:
case
ADDR_SPACE_FLASH2
:
case
ADDR_SPACE_FLASH3
:
case
ADDR_SPACE_FLASH4
:
case
ADDR_SPACE_FLASH5
:
if
(
AVR_HAVE_ELPMX
)
avr_asm_len
(
"elpm %2,Z+"
,
xop
,
plen
,
1
)
;
else
avr_asm_len
(
"elpm"
CR_TAB
"adiw r30,1"
,
xop
,
plen
,
2
)
;
break
;
}
avr_asm_len
(
"st X+,%2"
,
xop
,
plen
,
1
)
;
if
(
QImode
==
loop_mode
)
{
avr_asm_len
(
"dec %1"
,
xop
,
plen
,
1
)
;
}
else
if
(
sbiw_p
)
{
avr_asm_len
(
"sbiw %1,1"
,
xop
,
plen
,
1
)
;
}
else
{
avr_asm_len
(
"subi %A1,1"
CR_TAB
"sbci %B1,0"
,
xop
,
plen
,
2
)
;
}
return
avr_asm_len
(
"brne 0b"
,
xop
,
plen
,
1
)
;
}
</s>

Print assembler for cpymem_qi , cpymem_hi insns ... $ 0 : Address Space $ 1 , $ 2 : Loop register Z : Source address X : Destination address


<s> static bool classof ( const CAHPMCExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool X86DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , Op2 , Op3 , Op4 ; switch ( ConstraintCode ) { case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( nullptr , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool SparcTargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createSparcISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool mips_return_in_msb ( tree valtype ) { tree fields [ 2 ] ; return ( TARGET_NEWABI && TARGET_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && mips_fpr_return_fields ( valtype , fields ) == 0 ) ; } </s>

Implement TARGET_RETURN_IN_MSB . For n32 & n64 , we should return a value in the most significant part of $ 2/ $ 3 if : - the target is big-endian ; - the value has a structure or union type ( we generalize this to cover aggregates from other languages too ) ; and - the structure is not returned in floating-point registers .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static tree make_resolver_func ( const tree default_decl , const tree dispatch_decl , basic_block * empty_bb ) { char * resolver_name ; tree decl , type , decl_name , t ; bool is_uniq = false ; if ( TREE_PUBLIC ( default_decl ) == 0 ) is_uniq = true ; resolver_name = make_name ( default_decl , "resolver" , is_uniq ) ; type = build_function_type_list ( ptr_type_node , NULL_TREE ) ; decl = build_fn_decl ( resolver_name , type ) ; decl_name = get_identifier ( resolver_name ) ; SET_DECL_ASSEMBLER_NAME ( decl , decl_name ) ; DECL_NAME ( decl ) = decl_name ; TREE_USED ( decl ) = 1 ; DECL_ARTIFICIAL ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 0 ; TREE_PUBLIC ( decl ) = 1 ; DECL_UNINLINABLE ( decl ) = 1 ; DECL_EXTERNAL ( decl ) = 0 ; DECL_EXTERNAL ( dispatch_decl ) = 0 ; DECL_CONTEXT ( decl ) = NULL_TREE ; DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; DECL_STATIC_CONSTRUCTOR ( decl ) = 0 ; if ( DECL_COMDAT_GROUP ( default_decl ) || TREE_PUBLIC ( default_decl ) ) { DECL_COMDAT ( decl ) = 1 ; make_decl_one_only ( decl , DECL_ASSEMBLER_NAME ( decl ) ) ; } t = build_decl ( UNKNOWN_LOCATION , RESULT_DECL , NULL_TREE , ptr_type_node ) ; DECL_ARTIFICIAL ( t ) = 1 ; DECL_IGNORED_P ( t ) = 1 ; DECL_RESULT ( decl ) = t ; gimplify_function_tree ( decl ) ; push_cfun ( DECL_STRUCT_FUNCTION ( decl ) ) ; * empty_bb = init_lowered_empty_function ( decl , false , 0 ) ; cgraph_node :: add_new_function ( decl , true ) ; symtab -> call_cgraph_insertion_hooks ( cgraph_node :: get_create ( decl ) ) ; pop_cfun ( ) ; gcc_assert ( dispatch_decl != NULL ) ; DECL_ATTRIBUTES ( dispatch_decl ) = make_attribute ( "ifunc" , resolver_name , DECL_ATTRIBUTES ( dispatch_decl ) ) ; cgraph_node :: create_same_body_alias ( dispatch_decl , decl ) ; XDELETEVEC ( resolver_name ) ; return decl ; } </s>

Make the resolver function decl to dispatch the versions of a multi- versioned function , DEFAULT_DECL . Create an empty basic block in the resolver and store the pointer in EMPTY_BB . Return the decl of the resolver function .


<s> void GCNMaxOccupancySchedStrategy :: pickNodeFromQueue ( SchedBoundary & Zone , const CandPolicy & ZonePolicy , const RegPressureTracker & RPTracker , SchedCandidate & Cand ) { const SISubtarget & ST = DAG -> MF . getSubtarget < SISubtarget > ( ) ; const SIRegisterInfo * SRI = static_cast < const SIRegisterInfo * > ( TRI ) ; ArrayRef < unsigned > Pressure = RPTracker . getRegSetPressureAtPos ( ) ; unsigned SGPRPressure = Pressure [ SRI -> getSGPRPressureSet ( ) ] ; unsigned VGPRPressure = Pressure [ SRI -> getVGPRPressureSet ( ) ] ; unsigned SGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & AMDGPU :: SGPR_32RegClass ) ; unsigned VGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & AMDGPU :: VGPR_32RegClass ) ; unsigned MaxWaves = getMaxWaves ( SGPRPressure , VGPRPressure , DAG -> MF ) ; unsigned SGPRCriticalLimit = SRI -> getMaxNumSGPRs ( ST , MaxWaves , true ) ; unsigned VGPRCriticalLimit = SRI -> getMaxNumVGPRs ( MaxWaves ) ; ReadyQueue & Q = Zone . Available ; for ( SUnit * SU : Q ) { SchedCandidate TryCand ( ZonePolicy ) ; initCandidate ( TryCand , SU , Zone . isTop ( ) , RPTracker , SRI , SGPRPressure , VGPRPressure , SGPRExcessLimit , VGPRExcessLimit , SGPRCriticalLimit , VGPRCriticalLimit ) ; SchedBoundary * ZoneArg = Cand . AtTop == TryCand . AtTop ? & Zone : nullptr ; GenericScheduler :: tryCandidate ( Cand , TryCand , ZoneArg ) ; if ( TryCand . Reason != NoCand ) { if ( TryCand . ResDelta == SchedResourceDelta ( ) ) TryCand . initResourceDelta ( Zone . DAG , SchedModel ) ; Cand . setBest ( TryCand ) ; } } } </s>

Pick the best candidate from the queue .

AMDGPU SI SI SI SI AMDGPU::SGPR_32RegClass AMDGPU::VGPR_32RegClass


<s> virtual unsigned int execute ( function * ) { return cris_postdbr_cmpelim ( ) ; } </s>


<s> bool X86PassConfig :: addPostRegAlloc ( ) { PM -> add ( createX86FloatingPointStackifierPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> bool WinEHStatePass :: doFinalization ( Module & M ) { assert ( TheModule == & M ) ; TheModule = nullptr ; EHLinkRegistrationTy = nullptr ; CXXEHRegistrationTy = nullptr ; SEHRegistrationTy = nullptr ; FrameEscape = nullptr ; FrameRecover = nullptr ; FrameAddress = nullptr ; return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool isMem ( ) const { return Kind == K_Memory ; } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"ARM Execution Dependency Fix"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
unsigned
getReg
(
)
const
{
assert
(
isReg
(
)
&&
"Wrong CountValue accessor"
)
;
return
Contents
.
R
.
Reg
;
}
</s>

Returns the register associated with this edge .


<s> bool ARMBaseRegisterInfo :: isInlineAsmReadOnlyReg ( const MachineFunction & MF , unsigned PhysReg ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , ARM :: PC ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved . test ( PhysReg ) ; } </s>

Returns true if PhysReg can not be written to in inline asm statements .


"Frame offsets outside of the signed 32-bit range not supported"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static const char * riscv_mangle_type ( const_tree type ) { if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == 16 ) return "DF16_" ; if ( TYPE_NAME ( type ) != NULL ) { const char * res = riscv_vector :: mangle_builtin_type ( type ) ; if ( res ) return res ; } return NULL ; } </s>


<s> bool ARMCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { auto & TLI = * getTLI < ARMTargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 4 > SplitRegs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , Idx + AttributeList :: FirstArgIndex , DL , F ) ; SplitRegs . clear ( ) ; splitToValueTypes ( AInfo , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; if ( ! SplitRegs . empty ( ) ) MIRBuilder . buildMerge ( VRegs [ Idx ] , SplitRegs ) ; Idx ++ ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; return handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void AArch64TTI :: getUnrollingPreferences ( const Function * F , Loop * L , UnrollingPreferences & UP ) const { UP . PartialOptSizeThreshold = 0 ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


Return a register that is zero if CMP0 and CMP1 are equal . The register will have the same mode as CMP0 .


<s> bool invalidate ( Function & , const PreservedAnalyses & , FunctionAnalysisManager :: Invalidator & Inv ) { return false ; } </s>

Handle invalidation events from the new pass manager .


<s> void mips_save_gp_to_cprestore_slot ( rtx mem , rtx offset , rtx gp , rtx temp ) { if ( TARGET_CPRESTORE_DIRECTIVE ) { gcc_assert ( gp == pic_offset_table_rtx ) ; emit_insn ( PMODE_INSN ( gen_cprestore , ( mem , offset ) ) ) ; } else mips_emit_move ( mips_cprestore_slot ( temp , false ) , gp ) ; } </s>

Emit instructions to save global pointer value GP into cprestore slot MEM . OFFSET is the offset that MEM applies to the base register . MEM may not be a legitimate address . If it is n't , TEMP is a temporary register that can be used , otherwise it is a SCRATCH .


<s> static unsigned int csky_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( regno >= CSKY_FIRST_VFP_REGNUM && ! CSKY_TARGET_ARCH ( CK803 ) ) return 1 ; else return CSKY_NUM_REGS ( mode ) ; } </s>


<s>
void
nvptx_declare_object_name
(
FILE
*
file
,
const
char
*
name
,
const_tree
decl
)
{
if
(
decl
&&
DECL_SIZE
(
decl
)
)
{
tree
type
=
TREE_TYPE
(
decl
)
;
unsigned
HOST_WIDE_INT
size
;
init_output_initializer
(
file
,
name
,
type
,
TREE_PUBLIC
(
decl
)
)
;
size
=
tree_to_uhwi
(
DECL_SIZE_UNIT
(
decl
)
)
;
const
char
*
section
=
nvptx_section_for_decl
(
decl
)
;
fprintf
(
file
,
"\t%s%s .align %d .u%d "
,
TREE_PUBLIC
(
decl
)
" .visible"
:
""
,
section
,
DECL_ALIGN
(
decl
)
/
BITS_PER_UNIT
,
decl_chunk_size
*
BITS_PER_UNIT
)
;
assemble_name
(
file
,
name
)
;
if
(
size
>
0
)
fprintf
(
file
,
"["
HOST_WIDE_INT_PRINT_DEC
"]"
,
(
size
+
decl_chunk_size
1
)
/
decl_chunk_size
)
;
else
object_finished
=
true
;
object_size
=
size
;
}
}
</s>

Implement the ASM_DECLARE_OBJECT_NAME macro . Used to start writing a variable DECL with NAME to FILE .

nvptx
"\t%s%s .align %d .u%d "
" .visible"
""
0
"["
"]"
1


<s> static bool pa_expand_compare_and_swap_loop ( rtx mem , rtx old_reg , rtx new_reg , rtx seq ) { machine_mode mode = GET_MODE ( mem ) ; rtx_code_label * label ; rtx cmp_reg , success , oldval ; label = gen_label_rtx ( ) ; cmp_reg = gen_reg_rtx ( mode ) ; emit_move_insn ( cmp_reg , mem ) ; emit_label ( label ) ; emit_move_insn ( old_reg , cmp_reg ) ; if ( seq ) emit_insn ( seq ) ; success = NULL_RTX ; oldval = cmp_reg ; if ( ! expand_atomic_compare_and_swap ( & success , & oldval , mem , old_reg , new_reg , false , MEMMODEL_SYNC_SEQ_CST , MEMMODEL_RELAXED ) ) return false ; if ( oldval != cmp_reg ) emit_move_insn ( cmp_reg , oldval ) ; emit_cmp_and_jump_insns ( success , const0_rtx , EQ , const0_rtx , GET_MODE ( success ) , 1 , label , 0 ) ; return true ; } </s>

This is a helper function for the other atomic operations . This function emits a loop that contains SEQ that iterates until a compare-and-swap operation at the end succeeds . MEM is the memory to be modified . SEQ is a set of instructions that takes a value from OLD_REG as an input and produces a value in NEW_REG as an output . Before SEQ , OLD_REG will be set to the current contents of MEM . After SEQ , a compare-and-swap will attempt to update MEM with NEW_REG . The function returns true when the loop was generated successfully .


<s>
void
MCS51InstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
O
)
{
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
switch
(
Opcode
)
{
case
MCS51
::
LDRdPtr
:
case
MCS51
::
LDRdPtrPi
:
case
MCS51
::
LDRdPtrPd
:
O
<<
"\tld\t"
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
if
(
Opcode
==
MCS51
::
LDRdPtrPd
)
O
<<
'-'
;
printOperand
(
MI
,
1
,
O
)
;
if
(
Opcode
==
MCS51
::
LDRdPtrPi
)
O
<<
'+'
;
break
;
case
MCS51
::
STPtrRr
:
O
<<
"\tst\t"
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
", "
;
printOperand
(
MI
,
1
,
O
)
;
break
;
case
MCS51
::
STPtrPiRr
:
case
MCS51
::
STPtrPdRr
:
O
<<
"\tst\t"
;
if
(
Opcode
==
MCS51
::
STPtrPdRr
)
O
<<
'-'
;
printOperand
(
MI
,
1
,
O
)
;
if
(
Opcode
==
MCS51
::
STPtrPiRr
)
O
<<
'+'
;
O
<<
", "
;
printOperand
(
MI
,
2
,
O
)
;
break
;
default
:
if
(
!
printAliasInstr
(
MI
,
Address
,
O
)
)
printInstruction
(
MI
,
Address
,
O
)
;
printAnnotation
(
O
,
Annot
)
;
break
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .


<s>
const
MCFixupKindInfo
&
SystemZMCAsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
SystemZ
::
NumTargetFixupKinds
]
=
{
{
"FK_390_PC12DBL"
,
4
,
12
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC16DBL"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC24DBL"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_PC32DBL"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"FK_390_TLS_CALL"
,
0
,
0
,
0
}
,
{
"FK_390_12"
,
4
,
12
,
0
}
,
{
"FK_390_20"
,
4
,
20
,
0
}
}
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
FK_NONE
)
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> int direct_return ( void ) { if ( reload_completed ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; if ( info -> first_gp_reg_save == 32 && info -> first_fp_reg_save == 64 && info -> first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1 && ! info -> lr_save_p && ! info -> cr_save_p && info -> vrsave_mask == 0 && ! info -> push_p ) return 1 ; } return 0 ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> bool rvexAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { rvexFI = MF . getInfo < rvexFunctionInfo > ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> void MipsInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( Mips :: NOP ) ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> int null_epilogue ( ) { return ( reload_completed && first_reg_to_save ( ) == 16 && ! romp_pushes_stack ( ) ) ; } </s>

return 1 if there is n't anything tricky to do


<s> static bool frv_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( mode == BLKmode ) return true ; if ( type == NULL ) return false ; return AGGREGATE_TYPE_P ( type ) ; } </s>

Return true if we should pass an argument on the stack rather than in registers .