<s> rtx legitimize_pic_address ( rtx orig , enum machine_mode mode , rtx reg ) { if ( GET_CODE ( orig ) == SYMBOL_REF || GET_CODE ( orig ) == LABEL_REF ) { rtx pic_ref , address ; rtx insn ; int subregs = 0 ; if ( reg == 0 ) { gcc_assert ( ! no_new_pseudos ) ; reg = gen_reg_rtx ( Pmode ) ; subregs = 1 ; } insn = emit_insn ( gen_pic_load_addr_based ( reg , orig ) ) ; if ( subregs ) address = gen_reg_rtx ( Pmode ) ; else address = reg ; if ( TARGET_ARM ) emit_insn ( gen_pic_load_addr_arm ( address , orig ) ) ; else emit_insn ( gen_pic_load_addr_thumb ( address , orig ) ) ; if ( ( GET_CODE ( orig ) == LABEL_REF || ( GET_CODE ( orig ) == SYMBOL_REF && SYMBOL_REF_LOCAL_P ( orig ) ) ) && NEED_GOT_RELOC ) pic_ref = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ; else { pic_ref = gen_const_mem ( Pmode , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , address ) ) ; } insn = emit_move_insn ( reg , pic_ref ) ; current_function_uses_pic_offset_table = 1 ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_EQUAL , orig , REG_NOTES ( insn ) ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS && XEXP ( XEXP ( orig , 0 ) , 0 ) == pic_offset_table_rtx ) return orig ; if ( GET_CODE ( XEXP ( orig , 0 ) ) == UNSPEC && XINT ( XEXP ( orig , 0 ) , 1 ) == UNSPEC_TLS ) return orig ; if ( reg == 0 ) { gcc_assert ( ! no_new_pseudos ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 0 ) , Pmode , reg ) ; offset = legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 1 ) , Pmode , base == reg ? 0 : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( ! arm_legitimate_index_p ( mode , offset , SET , 0 ) ) { gcc_assert ( ! no_new_pseudos ) ; offset = force_reg ( Pmode , offset ) ; } if ( GET_CODE ( offset ) == CONST_INT ) return plus_constant ( base , INTVAL ( offset ) ) ; } if ( GET_MODE_SIZE ( mode ) > 4 && ( GET_MODE_CLASS ( mode ) == MODE_INT || TARGET_SOFT_FLOAT ) ) { emit_insn ( gen_addsi3 ( reg , base , offset ) ) ; return reg ; } return gen_rtx_PLUS ( Pmode , base , offset ) ; } return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


"initialized variable %q+D is marked dllimport"


<s> const uint32_t * TPCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_AllRegs_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void insert_insn_end_basic_block ( rtx_insn * rinsn , basic_block cfg_bb ) { rtx_insn * end_rinsn = BB_END ( cfg_bb ) ; rtx_insn * new_insn ; rtx_insn * pat , * pat_end ; pat = rinsn ; gcc_assert ( pat && INSN_P ( pat ) ) ; pat_end = pat ; while ( NEXT_INSN ( pat_end ) != NULL_RTX ) pat_end = NEXT_INSN ( pat_end ) ; if ( JUMP_P ( end_rinsn ) || ( NONJUMP_INSN_P ( end_rinsn ) && ( ! single_succ_p ( cfg_bb ) || single_succ_edge ( cfg_bb ) -> flags & EDGE_ABNORMAL ) ) ) { new_insn = emit_insn_before_noloc ( pat , end_rinsn , cfg_bb ) ; } else if ( CALL_P ( end_rinsn ) && ( ! single_succ_p ( cfg_bb ) || single_succ_edge ( cfg_bb ) -> flags & EDGE_ABNORMAL ) ) { end_rinsn = find_first_parameter_load ( end_rinsn , BB_HEAD ( cfg_bb ) ) ; while ( LABEL_P ( end_rinsn ) || NOTE_INSN_BASIC_BLOCK_P ( end_rinsn ) ) end_rinsn = NEXT_INSN ( end_rinsn ) ; new_insn = emit_insn_before_noloc ( pat , end_rinsn , cfg_bb ) ; } else new_insn = emit_insn_after_noloc ( pat , end_rinsn , cfg_bb ) ; while ( 1 ) { if ( INSN_P ( pat ) ) add_label_notes ( PATTERN ( pat ) , new_insn ) ; if ( pat == pat_end ) break ; pat = NEXT_INSN ( pat ) ; } } </s>

Add EXPR to the end of basic block BB . This is used by both the PRE and code hoisting .


<s> static int rs6000_emit_int_cmove ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { rtx condition_rtx , cr ; machine_mode mode = GET_MODE ( dest ) ; enum rtx_code cond_code ; rtx ( * isel_func ) ( rtx , rtx , rtx , rtx , rtx ) ; bool signedp ; if ( mode != SImode && ( ! TARGET_POWERPC64 || mode != DImode ) ) return 0 ; condition_rtx = rs6000_generate_compare ( op , mode ) ; cond_code = GET_CODE ( condition_rtx ) ; cr = XEXP ( condition_rtx , 0 ) ; signedp = GET_MODE ( cr ) == CCmode ; isel_func = ( mode == SImode ? ( signedp ? gen_isel_signed_si : gen_isel_unsigned_si ) : ( signedp ? gen_isel_signed_di : gen_isel_unsigned_di ) ) ; switch ( cond_code ) { case LT : case GT : case LTU : case GTU : case EQ : break ; default : { std :: swap ( false_cond , true_cond ) ; PUT_CODE ( condition_rtx , reverse_condition ( cond_code ) ) ; } break ; } false_cond = force_reg ( mode , false_cond ) ; if ( true_cond != const0_rtx ) true_cond = force_reg ( mode , true_cond ) ; emit_insn ( isel_func ( dest , condition_rtx , true_cond , false_cond , cr ) ) ; return 1 ; } </s>


<s> int adjacent_mem_locations ( rtx a , rtx b ) { if ( volatile_refs_p ( a ) || volatile_refs_p ( b ) ) return 0 ; if ( ( GET_CODE ( XEXP ( a , 0 ) ) == REG || ( GET_CODE ( XEXP ( a , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( a , 0 ) , 1 ) ) == CONST_INT ) ) && ( GET_CODE ( XEXP ( b , 0 ) ) == REG || ( GET_CODE ( XEXP ( b , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( b , 0 ) , 1 ) ) == CONST_INT ) ) ) { HOST_WIDE_INT val0 = 0 , val1 = 0 ; rtx reg0 , reg1 ; int val_diff ; if ( GET_CODE ( XEXP ( a , 0 ) ) == PLUS ) { reg0 = XEXP ( XEXP ( a , 0 ) , 0 ) ; val0 = INTVAL ( XEXP ( XEXP ( a , 0 ) , 1 ) ) ; } else reg0 = XEXP ( a , 0 ) ; if ( GET_CODE ( XEXP ( b , 0 ) ) == PLUS ) { reg1 = XEXP ( XEXP ( b , 0 ) , 0 ) ; val1 = INTVAL ( XEXP ( XEXP ( b , 0 ) , 1 ) ) ; } else reg1 = XEXP ( b , 0 ) ; if ( ! const_ok_for_op ( PLUS , val0 ) || ! const_ok_for_op ( PLUS , val1 ) ) return 0 ; if ( arm_eliminable_register ( reg0 ) ) return 0 ; val_diff = val1 - val0 ; if ( arm_ld_sched ) { return ( optimize_size && ( REGNO ( reg0 ) == REGNO ( reg1 ) ) && ( val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4 ) && ( val_diff == 4 || val_diff == - 4 ) ) ; } return ( ( REGNO ( reg0 ) == REGNO ( reg1 ) ) && ( val_diff == 4 || val_diff == - 4 ) ) ; } return 0 ; } </s>

If the target storage locations of arguments MEM1 and MEM2 are adjacent , then return the argument that has the lower address . Otherwise , return NULL_RTX .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s>
bool
AArch64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64AdvSIMDScalar *****\n"
)
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
mf
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
&
*
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static Value * buildMul ( IRBuilder < > & B , Value * LHS , Value * RHS ) { const ConstantInt * CI = dyn_cast < ConstantInt > ( LHS ) ; return ( CI && CI -> isOne ( ) ) ? RHS : B . CreateMul ( LHS , RHS ) ; } </s>

Build and insert Res = G_MUL Op0 , Op1 .


Create builtin functions for VIS 1.0 instructions .


<s> void avr_notice_update_cc ( rtx body ATTRIBUTE_UNUSED , rtx_insn * insn ) { rtx set ; enum attr_cc cc = get_attr_cc ( insn ) ; switch ( cc ) { default : break ; case CC_PLUS : case CC_LDI : { rtx * op = recog_data . operand ; int len_dummy , icc ; extract_constrain_insn_cached ( insn ) ; switch ( cc ) { default : gcc_unreachable ( ) ; case CC_PLUS : avr_out_plus ( insn , op , & len_dummy , & icc ) ; cc = ( enum attr_cc ) icc ; break ; case CC_LDI : cc = ( op [ 1 ] == CONST0_RTX ( GET_MODE ( op [ 0 ] ) ) && reg_overlap_mentioned_p ( op [ 0 ] , zero_reg_rtx ) ) ? CC_CLOBBER : CC_NONE ; break ; } break ; } } switch ( cc ) { default : gcc_unreachable ( ) ; break ; case CC_NONE : if ( cc_status . value1 || cc_status . value2 ) { HARD_REG_SET regs_used ; HARD_REG_SET regs_set ; CLEAR_HARD_REG_SET ( regs_used ) ; if ( cc_status . value1 && ! CONSTANT_P ( cc_status . value1 ) ) { find_all_hard_regs ( cc_status . value1 , & regs_used ) ; } if ( cc_status . value2 && ! CONSTANT_P ( cc_status . value2 ) ) { find_all_hard_regs ( cc_status . value2 , & regs_used ) ; } find_all_hard_reg_sets ( insn , & regs_set , false ) ; if ( hard_reg_set_intersect_p ( regs_used , regs_set ) ) { CC_STATUS_INIT ; } } break ; case CC_SET_N : CC_STATUS_INIT ; break ; case CC_SET_ZN : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) { cc_status . flags |= CC_NO_OVERFLOW ; cc_status . value1 = SET_DEST ( set ) ; } break ; case CC_SET_VZN : CC_STATUS_INIT ; break ; case CC_SET_CZN : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) { cc_status . value1 = SET_DEST ( set ) ; cc_status . flags |= CC_OVERFLOW_UNUSABLE ; } break ; case CC_COMPARE : set = single_set ( insn ) ; CC_STATUS_INIT ; if ( set ) cc_status . value1 = SET_SRC ( set ) ; break ; case CC_CLOBBER : CC_STATUS_INIT ; break ; } } </s>


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + 1 , DL , F ) ; LLT Ty = MRI . getType ( VRegs [ Idx ] ) ; unsigned Dst = VRegs [ Idx ] ; bool Split = false ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ Idx ] ) MIRBuilder . buildCopy ( VRegs [ Idx ] , Dst ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 , DL ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool PTXMFInfoExtract :: runOnMachineFunction ( MachineFunction & MF ) { PTXMachineFunctionInfo * MFI = MF . getInfo < PTXMachineFunctionInfo > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( unsigned i = 0 ; i < MRI . getNumVirtRegs ( ) ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; const TargetRegisterClass * TRC = MRI . getRegClass ( Reg ) ; MFI -> addVirtualRegister ( TRC , Reg ) ; } return false ; } </s>


<s> MachineInstrBuilder MipsInstrInfo :: genInstrWithNewOpc ( unsigned NewOpc , MachineBasicBlock :: iterator I ) const { MachineInstrBuilder MIB ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; for ( unsigned J = 0 , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) MIB . addOperand ( I -> getOperand ( J ) ) ; MIB . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; return MIB ; } </s>

Create an instruction which has the same operands and memory operands as MI but has a new opcode .


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


<s> static void xstormy16_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx temp = gen_reg_rtx ( HImode ) ; rtx reg_fnaddr = gen_reg_rtx ( HImode ) ; rtx reg_addr , reg_addr_mem ; reg_addr = copy_to_reg ( XEXP ( m_tramp , 0 ) ) ; reg_addr_mem = adjust_automodify_address ( m_tramp , HImode , reg_addr , 0 ) ; emit_move_insn ( temp , GEN_INT ( 0x3130 | STATIC_CHAIN_REGNUM ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode , NULL , 2 ) ; emit_move_insn ( temp , static_chain ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode , NULL , 2 ) ; emit_move_insn ( reg_fnaddr , XEXP ( DECL_RTL ( fndecl ) , 0 ) ) ; emit_move_insn ( temp , reg_fnaddr ) ; emit_insn ( gen_andhi3 ( temp , temp , GEN_INT ( 0xFF ) ) ) ; emit_insn ( gen_iorhi3 ( temp , temp , GEN_INT ( 0x0200 ) ) ) ; emit_move_insn ( reg_addr_mem , temp ) ; emit_insn ( gen_addhi3 ( reg_addr , reg_addr , const2_rtx ) ) ; reg_addr_mem = adjust_automodify_address ( reg_addr_mem , VOIDmode , NULL , 2 ) ; emit_insn ( gen_lshrhi3 ( reg_fnaddr , reg_fnaddr , GEN_INT ( 8 ) ) ) ; emit_move_insn ( reg_addr_mem , reg_fnaddr ) ; } </s>

Worker function for TARGET_TRAMPOLINE_INIT .


<s> static HOST_WIDE_INT mmix_starting_frame_offset ( void ) { return ( - 8 + ( MMIX_CFUN_HAS_LANDING_PAD ? - 16 : ( MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS ? - 8 : 0 ) ) ) ; } </s>


<s> bool Thumb1InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = false ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static cpp_hashnode * spu_macro_to_expand ( cpp_reader * pfile , const cpp_token * tok ) { cpp_hashnode * expand_this = tok -> val . node . node ; cpp_hashnode * ident ; ident = spu_categorize_keyword ( tok ) ; if ( ident == C_CPP_HASHNODE ( __vector_keyword ) ) { tok = cpp_peek_token ( pfile , 0 ) ; ident = spu_categorize_keyword ( tok ) ; if ( ident ) { enum rid rid_code = ( enum rid ) ( ident -> rid_code ) ; if ( ident -> type == NT_MACRO ) { ( void ) cpp_get_token ( pfile ) ; tok = cpp_peek_token ( pfile , 0 ) ; ident = spu_categorize_keyword ( tok ) ; if ( ident ) rid_code = ( enum rid ) ( ident -> rid_code ) ; } if ( rid_code == RID_UNSIGNED || rid_code == RID_LONG || rid_code == RID_SHORT || rid_code == RID_SIGNED || rid_code == RID_INT || rid_code == RID_CHAR || rid_code == RID_FLOAT || rid_code == RID_DOUBLE ) expand_this = C_CPP_HASHNODE ( __vector_keyword ) ; } } return expand_this ; } </s>

Called to decide whether a conditional macro should be expanded . Since we have exactly one such macro ( i.e , 'vector ' ) , we do not need to examine the 'tok ' parameter .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? DAG . getTarget ( ) . getSubtarget < AArch64Subtarget > ( ) . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * static_cast < const AArch64TargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; EVT IntPtr = TLI . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> static rtx csky_function_arg ( cumulative_args_t pcum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; if ( * pcum < CSKY_NPARM_REGS ) return gen_rtx_REG ( mode , CSKY_FIRST_PARM_REGNUM + * pcum ) ; return NULL_RTX ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s>
StringRef
getPassName
(
)
const
override
{
return
"GCN NSA Reassign"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
TTI
::
PopcntSupportKind
getPopcntSupport
(
unsigned
TyWidth
)
{
assert
(
isPowerOf2_32
(
TyWidth
)
&&
"Ty width must be power of 2"
)
;
return
TTI
::
PSK_FastHardware
;
}
</s>

Return hardware support for population count .


<s> bool SIInsertSkips :: runOnMachineFunction ( MachineFunction & MF ) { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; SkipThreshold = SkipThresholdFlag ; bool HaveKill = false ; bool MadeChange = false ; SmallVector < MachineBasicBlock * , 16 > ExecBranchStack ; MachineFunction :: iterator NextBB ; MachineBasicBlock * EmptyMBBAtEnd = nullptr ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; bool HaveSkipBlock = false ; if ( ! ExecBranchStack . empty ( ) && ExecBranchStack . back ( ) == & MBB ) { ExecBranchStack . pop_back ( ) ; } if ( HaveKill && ExecBranchStack . empty ( ) ) { HaveKill = false ; } MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_MASK_BRANCH : ExecBranchStack . push_back ( MI . getOperand ( 0 ) . getMBB ( ) ) ; MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case AMDGPU :: S_BRANCH : if ( MBB . isLayoutSuccessor ( MI . getOperand ( 0 ) . getMBB ( ) ) ) { MI . eraseFromParent ( ) ; } else if ( HaveSkipBlock ) { MI . eraseFromParent ( ) ; } break ; case AMDGPU :: SI_KILL_F32_COND_IMM_TERMINATOR : case AMDGPU :: SI_KILL_I1_TERMINATOR : MadeChange = true ; kill ( MI ) ; if ( ExecBranchStack . empty ( ) ) { if ( skipIfDead ( MI , * NextBB ) ) { HaveSkipBlock = true ; NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; } } else { HaveKill = true ; } MI . eraseFromParent ( ) ; break ; case AMDGPU :: SI_RETURN_TO_EPILOG : assert ( ! MF . getInfo < SIMachineFunctionInfo > ( ) -> returnsVoid ( ) ) ; if ( BI != -- MF . end ( ) || I != MBB . getFirstTerminator ( ) ) { if ( ! EmptyMBBAtEnd ) { EmptyMBBAtEnd = MF . CreateMachineBasicBlock ( ) ; MF . insert ( MF . end ( ) , EmptyMBBAtEnd ) ; } MBB . addSuccessor ( EmptyMBBAtEnd ) ; BuildMI ( * BI , I , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_BRANCH ) ) . addMBB ( EmptyMBBAtEnd ) ; I -> eraseFromParent ( ) ; } break ; default : break ; } } } return MadeChange ; } </s>


<s> MVT :: SimpleValueType BlackfinTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s> unsigned X86InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI . getOpcode ( ) ) ) if ( MI . getOperand ( X86 :: AddrNumOperands ) . getSubReg ( ) == 0 && isFrameOperand ( MI , 0 , FrameIndex ) ) return MI . getOperand ( X86 :: AddrNumOperands ) . getReg ( ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> MSP430Subtarget :: MSP430Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : MSP430GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static bool aarch64_evpc_trn ( struct expand_vec_perm_d * d ) { HOST_WIDE_INT odd ; poly_uint64 nelt = d -> perm . length ( ) ; rtx out , in0 , in1 , x ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > 8 ) return false ; if ( ! d -> perm [ 0 ] . is_constant ( & odd ) || ( odd != 0 && odd != 1 ) || ! d -> perm . series_p ( 0 , 2 , odd , 2 ) || ! d -> perm . series_p ( 1 , 2 , nelt + odd , 2 ) ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1 , in1 = x ; odd = ! odd ; } out = d -> target ; emit_set_insn ( out , gen_rtx_UNSPEC ( vmode , gen_rtvec ( 2 , in0 , in1 ) , odd ? UNSPEC_TRN2 : UNSPEC_TRN1 ) ) ; return true ; } </s>

Recognize patterns suitable for the TRN instructions .


<s> virtual const PatmosInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> const uint32_t * AArch64CA53ErratumStub :: getData ( ) const { return m_pData ; } </s>

Get the data pointed to by this extractor .


<s> rtx rs6000_expand_ldst_mask ( rtx target , tree arg0 ) { int icode2 = BYTES_BIG_ENDIAN ? ( int ) CODE_FOR_altivec_lvsr_direct : ( int ) CODE_FOR_altivec_lvsl_direct ; machine_mode tmode = insn_data [ icode2 ] . operand [ 0 ] . mode ; machine_mode mode = insn_data [ icode2 ] . operand [ 1 ] . mode ; gcc_assert ( TARGET_ALTIVEC ) ; gcc_assert ( POINTER_TYPE_P ( TREE_TYPE ( arg0 ) ) ) ; rtx op = expand_expr ( arg0 , NULL_RTX , Pmode , EXPAND_NORMAL ) ; rtx addr = memory_address ( mode , op ) ; op = gen_reg_rtx ( GET_MODE ( addr ) ) ; emit_insn ( gen_rtx_SET ( op , gen_rtx_NEG ( GET_MODE ( addr ) , addr ) ) ) ; op = gen_rtx_MEM ( mode , op ) ; if ( target == 0 || GET_MODE ( target ) != tmode || ! insn_data [ icode2 ] . operand [ 0 ] . predicate ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; rtx pat = GEN_FCN ( icode2 ) ( target , op ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> int avr_hard_regno_mode_ok ( int regno , machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) == 1 ) return 1 ; if ( GET_MODE_SIZE ( mode ) >= 4 && regno >= REG_X ) return 0 ; return ! ( regno & 1 ) ; } </s>

Returns 1 if a value of mode MODE can be stored starting with hard register number REGNO . On the enhanced core , anything larger than 1 byte must start in even numbered register for `` movw '' to work ( this way we do n't have to check for odd registers everywhere ) .


<s> bool HexagonTTIImpl :: isLegalMaskedStore ( Type * DataType , Align ) { return HexagonMaskedVMem && ST . isTypeForHVX ( DataType ) ; } </s>

Return true if the target supports masked store .


<s> MachineInstr * AMDGPUInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineInstr * LoadMI ) const { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> const rvexRegisterInfo & rvexInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool csky_far_jump_used_p ( void ) { rtx_insn * insn ; if ( cfun -> machine -> far_jump_used ) return true ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && get_attr_far_jump ( insn ) == FAR_JUMP_YES ) { cfun -> machine -> far_jump_used = 1 ; return true ; } return false ; } </s>

Check to see if the current function contains a branch insn with the far jump attribute set . Such a function uses the LR register .


<s> bool HexagonInstrInfo :: isSchedulingBoundary ( const MachineInstr * MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI -> isDebugValue ( ) ) return false ; if ( MI -> getDesc ( ) . isTerminator ( ) || MI -> isLabel ( ) || MI -> isInlineAsm ( ) ) return true ; return false ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> static void nds32_register_passes ( void ) { nds32_register_pass ( make_pass_nds32_relax_opt , PASS_POS_INSERT_AFTER , "mach" ) ; } </s>

This function is called from nds32_option_override ( ) . All new passes should be registered here .


<s> void fixup_addr_diff_vecs ( rtx_insn * first ) { rtx_insn * insn ; for ( insn = first ; insn ; insn = NEXT_INSN ( insn ) ) { rtx vec_lab , pat , prevpat , x , braf_label ; rtx_insn * prev ; if ( ! JUMP_TABLE_DATA_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC ) continue ; pat = PATTERN ( insn ) ; vec_lab = XEXP ( XEXP ( pat , 0 ) , 0 ) ; for ( prev = as_a < rtx_insn * > ( vec_lab ) ; ; prev = PREV_INSN ( prev ) ) { if ( ! JUMP_P ( prev ) ) continue ; prevpat = PATTERN ( prev ) ; if ( GET_CODE ( prevpat ) != PARALLEL || XVECLEN ( prevpat , 0 ) != 2 ) continue ; x = XVECEXP ( prevpat , 0 , 1 ) ; if ( GET_CODE ( x ) != USE ) continue ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == LABEL_REF && XEXP ( x , 0 ) == vec_lab ) break ; } if ( ! prev ) continue ; braf_label = XEXP ( XEXP ( SET_SRC ( XVECEXP ( prevpat , 0 , 0 ) ) , 1 ) , 0 ) ; emit_label_after ( braf_label , prev ) ; XEXP ( XEXP ( pat , 0 ) , 0 ) = braf_label ; } } </s>


<s> bool AAPAsmPrinter :: lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) { AAPMCInstLower MCInstLowering ( OutContext , * this ) ; return MCInstLowering . LowerMachineOperand ( MO , MCOp ) ; } </s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Lanai Assembly Printer"
;
}
</s>


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , ISD :: ArgFlagsTy Flags ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; const LLT PtrTy = LLT :: pointer ( AMDGPUAS :: PRIVATE_ADDRESS , 32 ) ; const LLT S32 = LLT :: scalar ( 32 ) ; if ( IsTailCall ) { Offset += FPDiff ; int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , Offset , true ) ; auto FIReg = MIRBuilder . buildFrameIndex ( PtrTy , FI ) ; MPO = MachinePointerInfo :: getFixedStack ( MF , FI ) ; return FIReg . getReg ( 0 ) ; } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( ! SPReg ) { const GCNSubtarget & ST = MIRBuilder . getMF ( ) . getSubtarget < GCNSubtarget > ( ) ; if ( ST . enableFlatScratch ( ) ) { SPReg = MIRBuilder . buildCopy ( PtrTy , MFI -> getStackPtrOffsetReg ( ) ) . getReg ( 0 ) ; } else { SPReg = MIRBuilder . buildInstr ( AMDGPU :: G_AMDGPU_WAVE_ADDRESS , { PtrTy } , { MFI -> getStackPtrOffsetReg ( ) } ) . getReg ( 0 ) ; } } auto OffsetReg = MIRBuilder . buildConstant ( S32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( PtrTy , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MF , Offset ) ; return AddrReg . getReg ( 0 ) ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


"every device must have an associate ELF architecture"

Gets the ELF architecture for the e_flags field of an ELF object file .


<s>
CCAssignFn
*
ARMFastISel
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
Return
)
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
(
void
)
RetFastCC_ARM_APCS
;
(
void
)
FastCC_ARM_APCS
;
case
CallingConv
::
C
:
if
(
Subtarget
->
isAAPCS_ABI
(
)
)
{
if
(
Subtarget
->
hasVFP2
(
)
&&
FloatABIType
==
FloatABI
::
Hard
)
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
else
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
}
else
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
case
CallingConv
::
ARM_AAPCS_VFP
:
return
(
Return
RetCC_ARM_AAPCS_VFP
:
CC_ARM_AAPCS_VFP
)
;
case
CallingConv
::
ARM_AAPCS
:
return
(
Return
RetCC_ARM_AAPCS
:
CC_ARM_AAPCS
)
;
case
CallingConv
::
ARM_APCS
:
return
(
Return
RetCC_ARM_APCS
:
CC_ARM_APCS
)
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .

ARM
ARM
"Unsupported calling convention"
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM
ARM


<s> static rtx arc_trampoline_adjust_address ( rtx addr ) { return plus_constant ( Pmode , addr , 2 ) ; } </s>

Allow the profiler to easily distinguish trampolines from normal functions .


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> const MCPhysReg * M68kRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_STD_SaveList ; } </s>


<s> static rtx c6x_expand_unop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; machine_mode op0mode = GET_MODE ( op0 ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( op0mode == SImode && mode0 == HImode ) { op0mode = HImode ; op0 = gen_lowpart ( HImode , op0 ) ; } gcc_assert ( op0mode == mode0 || op0mode == VOIDmode ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of c6x_expand_builtin to take care of unop insns .


<s> bool PPCTargetLowering :: preferIncOfAddToSubOfNot ( EVT VT ) const { return VT . isScalarInteger ( ) ; } </s>

These two forms are equivalent : sub y , ( xor x , -1 ) add ( add x , 1 ) , y The variant with two add 's is IR-canonical .


<s> static bool ia64_expand_vecint_compare ( enum rtx_code code , machine_mode mode , rtx dest , rtx op0 , rtx op1 ) { bool negate = false ; rtx x ; switch ( code ) { case EQ : case GT : case GTU : break ; case NE : case LE : case LEU : code = reverse_condition ( code ) ; negate = true ; break ; case GE : case GEU : code = reverse_condition ( code ) ; negate = true ; case LT : case LTU : code = swap_condition ( code ) ; x = op0 , op0 = op1 , op1 = x ; break ; default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V2SImode : { rtx t1 , t2 , mask ; mask = gen_int_mode ( 0x80000000 , SImode ) ; mask = gen_rtx_CONST_VECTOR ( V2SImode , gen_rtvec ( 2 , mask , mask ) ) ; mask = force_reg ( mode , mask ) ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv2si3 ( t1 , op0 , mask ) ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv2si3 ( t2 , op1 , mask ) ) ; op0 = t1 ; op1 = t2 ; code = GT ; } break ; case V8QImode : case V4HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_US_MINUS ( mode , op0 , op1 ) ) ) ; code = EQ ; op0 = x ; op1 = CONST0_RTX ( mode ) ; negate = ! negate ; break ; default : gcc_unreachable ( ) ; } } x = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; return negate ; } </s>

Generate an integral vector comparison . Return true if the condition has been reversed , and so the sense of the comparison should be inverted .


<s> static void rs6000_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; if ( cost_data -> loop_info ) rs6000_density_test ( cost_data ) ; * prologue_cost = cost_data -> cost [ vect_prologue ] ; * body_cost = cost_data -> cost [ vect_body ] ; * epilogue_cost = cost_data -> cost [ vect_epilogue ] ; } </s>


<s> bool SIRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & Fn ) const { return Fn . getFrameInfo ( ) -> hasStackObjects ( ) ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> static bool arc_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { if ( AGGREGATE_TYPE_P ( type ) || TREE_ADDRESSABLE ( type ) ) return true ; else { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - 1 || size > 8 ) ; } } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s>
bool
TVMInstrInfo
::
SubsumesPredicate
(
ArrayRef
<
MachineOperand
>
Pred1
,
ArrayRef
<
MachineOperand
>
Pred2
)
const
{
assert
(
Pred1
.
size
(
)
==
2
&&
"Invalid TVM first predicate"
)
;
assert
(
Pred2
.
size
(
)
==
2
&&
"Invalid TVM second predicate"
)
;
return
Pred1
[
0
]
.
getImm
(
)
==
Pred2
[
0
]
.
getImm
(
)
&&
Pred1
[
1
]
.
getReg
(
)
==
Pred2
[
1
]
.
getReg
(
)
;
}
</s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> static void rs6000_finish_cost ( void * data , unsigned * prologue_cost , unsigned * body_cost , unsigned * epilogue_cost ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; if ( cost_data -> loop_info ) rs6000_density_test ( cost_data ) ; if ( cost_data -> loop_info ) { loop_vec_info vec_info = loop_vec_info_for_loop ( cost_data -> loop_info ) ; if ( ! rs6000_vect_nonmem && LOOP_VINFO_VECT_FACTOR ( vec_info ) == 2 && LOOP_REQUIRES_VERSIONING ( vec_info ) ) cost_data -> cost [ vect_body ] += 10000 ; } * prologue_cost = cost_data -> cost [ vect_prologue ] ; * body_cost = cost_data -> cost [ vect_body ] ; * epilogue_cost = cost_data -> cost [ vect_epilogue ] ; } </s>


<s> static bool is_function_default_version ( const tree decl ) { if ( TREE_CODE ( decl ) != FUNCTION_DECL || ! DECL_FUNCTION_VERSIONED ( decl ) ) return false ; tree attr = lookup_attribute ( "target" , DECL_ATTRIBUTES ( decl ) ) ; gcc_assert ( attr ) ; attr = TREE_VALUE ( TREE_VALUE ( attr ) ) ; return ( TREE_CODE ( attr ) == STRING_CST && strcmp ( TREE_STRING_POINTER ( attr ) , "default" ) == 0 ) ; } </s>

Returns true if decl is multi-versioned and DECL is the default function , that is it is not tagged with target specific optimization .


<s> void c4x_override_options ( void ) { set_fast_math_flags ( 1 ) ; if ( ! TARGET_ALIASES && ! flag_argument_noalias ) flag_argument_noalias = 1 ; if ( ! TARGET_C3X ) target_flags |= MASK_MPYI | MASK_DB ; if ( optimize < 2 ) target_flags &= ~ ( MASK_RPTB | MASK_PARALLEL ) ; if ( ! TARGET_PARALLEL ) target_flags &= ~ MASK_PARALLEL_MPY ; } </s>

Override command line options . Called once after all options have been parsed . Mostly we process the processor type and sometimes adjust other TARGET_ options .


<s>
void
dump
(
)
{
errs
(
)
<<
"RISCVAddressingMode "
<<
this
<<
'\n'
;
errs
(
)
<<
" Base "
;
if
(
Base
.
getNode
(
)
!=
0
)
Base
.
getNode
(
)
->
dump
(
)
;
else
errs
(
)
<<
"null\n"
;
errs
(
)
<<
" Offset "
<<
Offset
;
}
</s>

Dump the plan to stderr ( for debugging ) .

RISCV
"RISCVAddressingMode "
" Base "
0
"null\n"
" Offset "


<s> void HexagonSubtarget :: adjustSchedDependency ( SUnit * Src , int SrcOpIdx , SUnit * Dst , int DstOpIdx , SDep & Dep ) const { if ( ! Src -> isInstr ( ) || ! Dst -> isInstr ( ) ) return ; MachineInstr * SrcInst = Src -> getInstr ( ) ; MachineInstr * DstInst = Dst -> getInstr ( ) ; const HexagonInstrInfo * QII = getInstrInfo ( ) ; SmallSet < SUnit * , 4 > ExclSrc ; SmallSet < SUnit * , 4 > ExclDst ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } if ( DstInst -> isCopy ( ) ) Dep . setLatency ( 0 ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) ) { Register DReg = DstInst -> getOperand ( 0 ) . getReg ( ) ; int DLatency = - 1 ; for ( const auto & DDep : Dst -> Succs ) { MachineInstr * DDst = DDep . getSUnit ( ) -> getInstr ( ) ; int UseIdx = - 1 ; for ( unsigned OpNum = 0 ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } if ( UseIdx == - 1 ) continue ; int Latency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , 0 , * DDst , UseIdx ) ) ; DLatency = ( DLatency == - 1 ) ? Latency : DLatency ; if ( DLatency != Latency ) { DLatency = - 1 ; break ; } } DLatency = std :: max ( DLatency , 0 ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } int Latency = Dep . getLatency ( ) ; bool IsArtificial = Dep . isArtificial ( ) ; Latency = updateLatency ( * SrcInst , * DstInst , IsArtificial , Latency ) ; Dep . setLatency ( Latency ) ; } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s> static void compute_save_world_info ( rs6000_stack_t * info ) { info -> world_save_p = 1 ; info -> world_save_p = ( WORLD_SAVE_P ( info ) && DEFAULT_ABI == ABI_DARWIN && ! cfun -> has_nonlocal_label && info -> first_fp_reg_save == FIRST_SAVED_FP_REGNO && info -> first_gp_reg_save == FIRST_SAVED_GP_REGNO && info -> first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO && info -> cr_save_p ) ; if ( WORLD_SAVE_P ( info ) ) { rtx_insn * insn ; for ( insn = get_last_insn_anywhere ( ) ; insn ; insn = PREV_INSN ( insn ) ) if ( CALL_P ( insn ) && SIBLING_CALL_P ( insn ) ) { info -> world_save_p = 0 ; break ; } } if ( WORLD_SAVE_P ( info ) ) { info -> vrsave_size = 4 ; info -> lr_save_p = 1 ; if ( info -> vrsave_mask == 0 ) info -> vrsave_mask = compute_vrsave_mask ( ) ; gcc_assert ( info -> first_fp_reg_save >= FIRST_SAVED_FP_REGNO && ( info -> first_altivec_reg_save >= FIRST_SAVED_ALTIVEC_REGNO ) ) ; } return ; } </s>

For a very restricted set of circumstances , we can cut down the size of prologues/epilogues by calling our own save/restore-the-world routines .


<s> bool FalkorHWPFFix :: runOnMachineFunction ( MachineFunction & Fn ) { auto & ST = static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; if ( ST . getProcFamily ( ) != AArch64Subtarget :: Falkor ) return false ; if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; TII = static_cast < const AArch64InstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; MachineLoopInfo & LI = getAnalysis < MachineLoopInfo > ( ) ; Modified = false ; for ( MachineLoop * I : LI ) for ( MachineLoop * L : depth_first ( I ) ) if ( L -> isInnermost ( ) ) runOnLoop ( * L , Fn ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"Unknown opcode to check as cheap as a move!"

Return true if the instruction is as cheap as a move instruction .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
if
(
Subtarget
.
hasVector
(
)
)
VerifyVectorTypes
(
Outs
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
unsigned
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = Size / 2 ; i > 0 ; ) { unsigned Shift = -- i * 16 ; EmitShort ( ( Val >> Shift ) & 0xffff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
void
relaxInstruction
(
MCInst
const
&
,
MCInst
&
)
const
override
{
llvm_unreachable
(
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


"BPF DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool GCNPassConfig :: addInstSelector ( ) { AMDGPUPassConfig :: addInstSelector ( ) ; addPass ( & SIFixSGPRCopiesID ) ; addPass ( createSILowerI1CopiesPass ( ) ) ; addPass ( & FinalizeISelID ) ; addPass ( createSIFixupVectorISelPass ( ) ) ; addPass ( createSIAddIMGInitPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> TargetLowering :: ConstraintWeight Z80TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'c' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s>
bool
Z80
::
splitReg
(
unsigned
ByteSize
,
unsigned
Opc8
,
unsigned
Opc16
,
unsigned
Opc24
,
unsigned
&
RC
,
unsigned
&
LoOpc
,
unsigned
&
LoIdx
,
unsigned
&
HiOpc
,
unsigned
&
HiIdx
,
unsigned
&
HiOff
,
bool
Has16BitEZ80Ops
)
{
switch
(
ByteSize
)
{
default
:
llvm_unreachable
(
"Unexpected Size!"
)
;
case
1
:
RC
=
Z80
::
R8RegClassID
;
LoOpc
=
HiOpc
=
Opc8
;
LoIdx
=
HiIdx
=
Z80
::
NoSubRegister
;
HiOff
=
0
;
return
false
;
case
2
:
if
(
Has16BitEZ80Ops
)
{
RC
=
Z80
::
R16RegClassID
;
LoOpc
=
HiOpc
=
Opc16
;
LoIdx
=
HiIdx
=
Z80
::
NoSubRegister
;
HiOff
=
0
;
return
false
;
}
RC
=
Z80
::
R16RegClassID
;
LoOpc
=
HiOpc
=
Opc8
;
LoIdx
=
Z80
::
sub_low
;
HiIdx
=
Z80
::
sub_high
;
HiOff
=
1
;
return
true
;
case
3
:
RC
=
Z80
::
R24RegClassID
;
LoOpc
=
HiOpc
=
Opc24
;
LoIdx
=
HiIdx
=
Z80
::
NoSubRegister
;
HiOff
=
0
;
return
false
;
}
}
</s>

Splits a 16-bit DREGS register into the lo/hi register pair .


<s> void PatmosAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { MCFixupKind Kind = Fixup . getKind ( ) ; Value = adjustFixupValue ( Fixup , Value ) ; if ( ! Value ) return ; unsigned TargetSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned TargetOffset = getFixupKindInfo ( Kind ) . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( TargetSize + 7 ) / 8 ; unsigned FullSize = ( TargetOffset + TargetSize + 7 ) / 8 ; uint64_t CurVal = 0 ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * 8 ) ; } uint64_t Mask = ( ( uint64_t ) ( - 1 ) >> ( 64 - TargetSize ) ) ; unsigned Shift = FullSize * 8 - ( TargetOffset + TargetSize ) ; CurVal |= ( Value & Mask ) << Shift ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - 1 - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static int s390_issue_rate ( void ) { switch ( s390_tune ) { case PROCESSOR_2084_Z990 : case PROCESSOR_2094_Z9_109 : case PROCESSOR_2094_Z9_EC : case PROCESSOR_2817_Z196 : return 3 ; case PROCESSOR_2097_Z10 : return 2 ; case PROCESSOR_2064_Z900 : case PROCESSOR_2827_ZEC12 : case PROCESSOR_2964_Z13 : case PROCESSOR_3906_Z14 : case PROCESSOR_8561_Z15 : case PROCESSOR_3931_Z16 : default : return 1 ; } } </s>

The number of instructions that can be issued per cycle .


<s> auto HexagonVectorCombine :: concat ( IRBuilder < > & Builder , ArrayRef < Value * > Vecs ) const -> Value * { assert ( ! Vecs . empty ( ) ) ; SmallVector < int , 256 > SMask ; std :: vector < Value * > Work [ 2 ] ; int ThisW = 0 , OtherW = 1 ; Work [ ThisW ] . assign ( Vecs . begin ( ) , Vecs . end ( ) ) ; while ( Work [ ThisW ] . size ( ) > 1 ) { auto * Ty = cast < VectorType > ( Work [ ThisW ] . front ( ) -> getType ( ) ) ; int ElemCount = Ty -> getElementCount ( ) . getFixedValue ( ) ; SMask . resize ( ElemCount * 2 ) ; std :: iota ( SMask . begin ( ) , SMask . end ( ) , 0 ) ; Work [ OtherW ] . clear ( ) ; if ( Work [ ThisW ] . size ( ) % 2 != 0 ) Work [ ThisW ] . push_back ( UndefValue :: get ( Ty ) ) ; for ( int i = 0 , e = Work [ ThisW ] . size ( ) ; i < e ; i += 2 ) { Value * Joined = Builder . CreateShuffleVector ( Work [ ThisW ] [ i ] , Work [ ThisW ] [ i + 1 ] , SMask ) ; Work [ OtherW ] . push_back ( Joined ) ; } std :: swap ( ThisW , OtherW ) ; } SMask . resize ( Vecs . size ( ) * getSizeOf ( Vecs . front ( ) -> getType ( ) ) ) ; std :: iota ( SMask . begin ( ) , SMask . end ( ) , 0 ) ; Value * Total = Work [ OtherW ] . front ( ) ; return Builder . CreateShuffleVector ( Total , UndefValue :: get ( Total -> getType ( ) ) , SMask ) ; } </s>

Concatenate the bits from Lo onto the bottom of * this .


<s> void mmix_asm_output_labelref ( FILE * stream , const char * name ) { int is_extern = 1 ; for ( ; ( * name == '@' || * name == '*' ) ; name ++ ) if ( * name == '@' ) is_extern = 0 ; asm_fprintf ( stream , "%s%U%s" , is_extern && TARGET_TOPLEVEL_SYMBOLS ? ":" : "" , name ) ; } </s>

ASM_OUTPUT_LABELREF . Strip GCC 's ' * ' and our own ' @ ' . No order is assumed .


<s> static bool riscv_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 ) { return ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ( class1 == FP_REGS ) != ( class2 == FP_REGS ) ) ; } </s>

Implement TARGET_SECONDARY_MEMORY_NEEDED . When floating-point registers are wider than integer ones , moves between them must go through memory .


<s>
void
AArch64TargetLowering
::
computeKnownBitsForTargetNode
(
const
SDValue
Op
,
KnownBits
&
Known
,
const
APInt
&
DemandedElts
,
const
SelectionDAG
&
DAG
,
unsigned
Depth
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64ISD
::
CSEL
:
{
KnownBits
Known2
;
Known
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
Depth
+
1
)
;
Known2
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
1
)
,
Depth
+
1
)
;
Known
=
KnownBits
::
commonBits
(
Known
,
Known2
)
;
break
;
}
case
AArch64ISD
::
LOADgot
:
case
AArch64ISD
::
ADDlow
:
{
if
(
!
Subtarget
->
isTargetILP32
(
)
)
break
;
Known
.
Zero
=
APInt
::
getHighBitsSet
(
64
,
32
)
;
break
;
}
case
AArch64ISD
::
ASSERT_ZEXT_BOOL
:
{
Known
=
DAG
.
computeKnownBits
(
Op
->
getOperand
(
0
)
,
Depth
+
1
)
;
Known
.
Zero
|=
APInt
(
Known
.
getBitWidth
(
)
,
0xFE
)
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
ConstantSDNode
*
CN
=
cast
<
ConstantSDNode
>
(
Op
->
getOperand
(
1
)
)
;
Intrinsic
::
ID
IntID
=
static_cast
<
Intrinsic
::
ID
>
(
CN
->
getZExtValue
(
)
)
;
switch
(
IntID
)
{
default
:
return
;
case
Intrinsic
::
aarch64_ldaxr
:
case
Intrinsic
::
aarch64_ldxr
:
{
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
EVT
VT
=
cast
<
MemIntrinsicSDNode
>
(
Op
)
->
getMemoryVT
(
)
;
unsigned
MemBits
=
VT
.
getScalarSizeInBits
(
)
;
Known
.
Zero
|=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
MemBits
)
;
return
;
}
}
break
;
}
case
ISD
::
INTRINSIC_WO_CHAIN
:
case
ISD
::
INTRINSIC_VOID
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Op
.
getOperand
(
0
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
default
:
break
;
case
Intrinsic
::
aarch64_neon_umaxv
:
case
Intrinsic
::
aarch64_neon_uminv
:
{
MVT
VT
=
Op
.
getOperand
(
1
)
.
getValueType
(
)
.
getSimpleVT
(
)
;
unsigned
BitWidth
=
Known
.
getBitWidth
(
)
;
if
(
VT
==
MVT
::
v8i8
||
VT
==
MVT
::
v16i8
)
{
assert
(
BitWidth
>=
8
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
8
)
;
Known
.
Zero
|=
Mask
;
}
else
if
(
VT
==
MVT
::
v4i16
||
VT
==
MVT
::
v8i16
)
{
assert
(
BitWidth
>=
16
&&
"Unexpected width!"
)
;
APInt
Mask
=
APInt
::
getHighBitsSet
(
BitWidth
,
BitWidth
16
)
;
Known
.
Zero
|=
Mask
;
}
break
;
}
break
;
}
}
}
}
</s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static bool quad_aligned_load_p ( swap_web_entry * insn_entry , rtx_insn * insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use = DF_INSN_INFO_USES ( insn_info ) ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , 0 ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , 0 ) ; rtx base_reg = XEXP ( mem , 0 ) ; return ( ( REG_P ( base_reg ) || rs6000_sum_of_two_registers_p ( base_reg ) ) && MEM_ALIGN ( mem ) >= 128 ) ? true : false ; } </s>

Return TRUE if INSN represents a swap of a swapped load from memory and the memory address is quad-word aligned .


<s> static bool aarch64_could_trap_p ( unsigned int f , machine_mode mode ) { unsigned int flags = aarch64_call_properties ( f , mode ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( FLAG_READ_MEMORY | FLAG_WRITE_MEMORY ) ) return true ; return false ; } </s>

Return true if calls to the function could raise a signal .


<s>
void
X86InstrInfo
::
insertSelect
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DstReg
,
ArrayRef
<
MachineOperand
>
Cond
,
unsigned
TrueReg
,
unsigned
FalseReg
)
const
{
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid Cond array"
)
;
unsigned
Opc
=
getCMovFromCond
(
(
X86
::
CondCode
)
Cond
[
0
]
.
getImm
(
)
,
MRI
.
getRegClass
(
DstReg
)
->
getSize
(
)
,
false
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
,
DstReg
)
.
addReg
(
FalseReg
)
.
addReg
(
TrueReg
)
;
}
</s>

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true , and FalseReg to DstReg when Cond is false .


<s> bool isImm ( ) const override { return Kind == k_Immediate ; } </s>


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> static bool frv_frame_pointer_required ( void ) { if ( ! TARGET_LINKED_FP ) return ! crtl -> sp_is_unchanging ; if ( ! crtl -> is_leaf ) return true ; if ( get_frame_size ( ) != 0 ) return true ; if ( cfun -> stdarg ) return true ; if ( ! crtl -> sp_is_unchanging ) return true ; if ( ! TARGET_FDPIC && flag_pic && crtl -> uses_pic_offset_table ) return true ; if ( profile_flag ) return true ; if ( cfun -> machine -> frame_needed ) return true ; return false ; } </s>

On frv , create a frame whenever we need to create stack .


<s> void XtensaTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { } </s>

This method must be called before any actual lowering is done .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


<s> bool PPCTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseOffs <= - ( 1LL << 16 ) || AM . BaseOffs >= ( 1LL << 16 ) - 1 ) return false ; if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg && AM . BaseOffs ) return false ; break ; case 2 : if ( AM . HasBaseReg || AM . BaseOffs ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static void s390_chunkify_finish ( struct constant_pool * pool_list ) { struct constant_pool * curr_pool = NULL ; rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) replace_ltrel_base ( & PATTERN ( insn ) ) ; curr_pool = s390_find_pool ( pool_list , insn ) ; if ( ! curr_pool ) continue ; if ( GET_CODE ( insn ) == INSN || GET_CODE ( insn ) == CALL_INSN ) { rtx addr , pool_ref = NULL_RTX ; find_constant_pool_ref ( PATTERN ( insn ) , & pool_ref ) ; if ( pool_ref ) { if ( s390_execute_label ( insn ) ) addr = s390_find_execute ( curr_pool , insn ) ; else addr = s390_find_constant ( curr_pool , get_pool_constant ( pool_ref ) , get_pool_mode ( pool_ref ) ) ; replace_constant_pool_ref ( & PATTERN ( insn ) , pool_ref , addr ) ; INSN_CODE ( insn ) = - 1 ; } } } for ( curr_pool = pool_list ; curr_pool ; curr_pool = curr_pool -> next ) s390_dump_pool ( curr_pool , 0 ) ; while ( pool_list ) { struct constant_pool * next = pool_list -> next ; s390_free_pool ( pool_list ) ; pool_list = next ; } } </s>

POOL_LIST is a chunk list as prepared by s390_chunkify_start . After we have decided to use this list , finish implementing all changes to the current function as required .


<s> Optional < Value * > X86TTIImpl :: simplifyDemandedUseBitsIntrinsic ( InstCombiner & IC , IntrinsicInst & II , APInt DemandedMask , KnownBits & Known , bool & KnownBitsComputed ) const { switch ( II . getIntrinsicID ( ) ) { default : break ; case Intrinsic :: x86_mmx_pmovmskb : case Intrinsic :: x86_sse_movmsk_ps : case Intrinsic :: x86_sse2_movmsk_pd : case Intrinsic :: x86_sse2_pmovmskb_128 : case Intrinsic :: x86_avx_movmsk_ps_256 : case Intrinsic :: x86_avx_movmsk_pd_256 : case Intrinsic :: x86_avx2_pmovmskb : { unsigned ArgWidth ; if ( II . getIntrinsicID ( ) == Intrinsic :: x86_mmx_pmovmskb ) { ArgWidth = 8 ; } else { auto * ArgType = cast < FixedVectorType > ( II . getArgOperand ( 0 ) -> getType ( ) ) ; ArgWidth = ArgType -> getNumElements ( ) ; } APInt DemandedElts = DemandedMask . zextOrTrunc ( ArgWidth ) ; Type * VTy = II . getType ( ) ; if ( DemandedElts . isZero ( ) ) { return ConstantInt :: getNullValue ( VTy ) ; } Known . Zero . setBitsFrom ( ArgWidth ) ; KnownBitsComputed = true ; break ; } } return None ; } </s>

Can be used to implement target-specific instruction combining .


<s> static rtx or1k_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree , bool named ) { if ( mode == VOIDmode ) return NULL_RTX ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int nreg = CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; gcc_assert ( nreg <= 2 ) ; if ( named && * cum + nreg <= 6 ) return gen_rtx_REG ( mode , * cum + 3 ) ; else return NULL_RTX ; } </s>

Worker for TARGET_FUNCTION_ARG . Return the next register to be used to hold a function argument or NULL_RTX if there 's no more space . Arugment CUM_V represents the current argument offset , zero for the first function argument . OpenRISC function arguments maybe be passed in registers r3 to r8 .


<s> rtx riscv_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ; } </s>

Emit a move from SRC to DEST . Assume that the move expanders can handle all moves if ! can_create_pseudo_p ( ) . The distinction is important because , unlike emit_move_insn , the move expanders know how to force Pmode objects into the constant pool even when the constant pool address is not itself legitimate .


<s> bool RISCVCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { if ( F . arg_empty ( ) ) return true ; return false ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) == 0 ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < AArch64Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>


<s> void SIRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const SISubtarget & Subtarget = MF -> getSubtarget < SISubtarget > ( ) ; const SIInstrInfo * TII = Subtarget . getInstrInfo ( ) ; if ( Offset == 0 ) { BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_MOV_B32_e32 ) , BaseReg ) . addFrameIndex ( FrameIdx ) ; return ; } MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; unsigned UnusedCarry = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; BuildMI ( * MBB , Ins , DL , TII -> get ( AMDGPU :: V_ADD_I32_e64 ) , BaseReg ) . addReg ( UnusedCarry , RegState :: Define | RegState :: Dead ) . addImm ( Offset ) . addFrameIndex ( FrameIdx ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> StringRef getPassName ( ) const override { return SYSTEMZ_COPYPHYSREGS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
MachineBasicBlock
*
MBlazeTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
MBB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
false
&&
"Unexpected instr type to insert"
)
;
case
MBlaze
::
ShiftRL
:
case
MBlaze
::
ShiftRA
:
case
MBlaze
::
ShiftL
:
return
EmitCustomShift
(
MI
,
MBB
)
;
case
MBlaze
::
Select_FCC
:
case
MBlaze
::
Select_CC
:
return
EmitCustomSelect
(
MI
,
MBB
)
;
case
MBlaze
::
CAS32
:
case
MBlaze
::
SWP32
:
case
MBlaze
::
LAA32
:
case
MBlaze
::
LAS32
:
case
MBlaze
::
LAD32
:
case
MBlaze
::
LAO32
:
case
MBlaze
::
LAX32
:
case
MBlaze
::
LAN32
:
return
EmitCustomAtomic
(
MI
,
MBB
)
;
case
MBlaze
::
MEMBARRIER
:
MI
->
eraseFromParent
(
)
;
return
MBB
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static void mn10300_encode_section_info ( tree decl , rtx rtl , int first ATTRIBUTE_UNUSED ) { rtx symbol ; if ( GET_CODE ( rtl ) != MEM ) return ; symbol = XEXP ( rtl , 0 ) ; if ( GET_CODE ( symbol ) != SYMBOL_REF ) return ; if ( flag_pic ) SYMBOL_REF_FLAG ( symbol ) = ( * targetm . binds_local_p ) ( decl ) ; } </s>

If using PIC , mark a SYMBOL_REF for a non-global symbol so that we may access it using GOTOFF instead of GOT .


<s> bool runOnModule ( Module & M ) override { DEBUG ( dbgs ( ) << getPassName ( ) << '\n' ) ; bool Changed = false ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF ) ; } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> bool XtensaAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( ( Count % 3 ) != 0 ) return false ; uint32_t Hex = 0 ; for ( uint64_t i = 0 ; i < Count ; ++ i ) { support :: endian :: write < uint8_t > ( OS , ( Hex >> 0 ) & 0xff , llvm :: support :: little ) ; support :: endian :: write < uint8_t > ( OS , ( Hex >> 8 ) & 0xff , llvm :: support :: little ) ; support :: endian :: write < uint8_t > ( OS , ( Hex >> 16 ) & 0xff , llvm :: support :: little ) ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool HexagonEarlyIfConversion :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & ST = MF . getSubtarget < HexagonSubtarget > ( ) ; HII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = EnableHexagonBP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; Changed |= visitLoop ( nullptr ) ; return Changed ; } </s>


<s> TargetTransformInfo PPCTargetMachine :: getTargetTransformInfo ( const Function & F ) { return TargetTransformInfo ( PPCTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; MCSymbol * Sym = Printer . GetExternalSymbolSymbol ( Name ) ; if ( isa < MCSymbolELF > ( Sym ) ) return Sym ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Sym ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 ) return WasmSym ; SmallVector < unsigned , 4 > Returns ; SmallVector < unsigned , 4 > Params ; GetSignature ( Subtarget , Name , Returns , Params ) ; WasmSym -> setReturns ( std :: move ( Returns ) ) ; WasmSym -> setParams ( std :: move ( Params ) ) ; WasmSym -> setIsFunction ( true ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> int fmpysuboperands ( rtx * operands ) { enum machine_mode mode = GET_MODE ( operands [ 0 ] ) ; if ( mode != SFmode && mode != DFmode ) return 0 ; if ( ! ( mode == GET_MODE ( operands [ 1 ] ) && mode == GET_MODE ( operands [ 2 ] ) && mode == GET_MODE ( operands [ 3 ] ) && mode == GET_MODE ( operands [ 4 ] ) && mode == GET_MODE ( operands [ 5 ] ) ) ) return 0 ; if ( ! ( GET_CODE ( operands [ 1 ] ) == REG && GET_CODE ( operands [ 2 ] ) == REG && GET_CODE ( operands [ 3 ] ) == REG && GET_CODE ( operands [ 4 ] ) == REG && GET_CODE ( operands [ 5 ] ) == REG ) ) return 0 ; if ( ! rtx_equal_p ( operands [ 3 ] , operands [ 4 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 5 ] , operands [ 0 ] ) ) return 0 ; if ( rtx_equal_p ( operands [ 3 ] , operands [ 0 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 1 ] ) || rtx_equal_p ( operands [ 3 ] , operands [ 2 ] ) ) return 0 ; if ( mode == SFmode && ( REGNO_REG_CLASS ( REGNO ( operands [ 0 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 1 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 2 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 3 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 4 ] ) ) != FPUPPER_REGS || REGNO_REG_CLASS ( REGNO ( operands [ 5 ] ) ) != FPUPPER_REGS ) ) return 0 ; return 1 ; } </s>

Returns 1 if the 6 operands specified in OPERANDS are suitable for use in fmpysub instructions .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT ISD::AND ISD::OR


<s>
void
dump
(
)
{
cerr
<<
"SystemZRRIAddressMode "
<<
this
<<
'\n'
;
if
(
BaseType
==
RegBase
)
{
cerr
<<
"Base.Reg "
;
if
(
Base
.
Reg
.
getNode
(
)
!=
0
)
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
'\n'
;
}
else
{
cerr
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
'\n'
;
}
if
(
!
isRI
)
{
cerr
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
!=
0
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
cerr
<<
"nul"
;
}
cerr
<<
" Disp "
<<
Disp
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

SystemZ
"SystemZRRIAddressMode "
"Base.Reg "
0
"nul"
" Base.FrameIndex "
"IndexReg "
0
"nul"
" Disp "


<s>
const
char
*
nds32_output_32bit_store
(
rtx
*
operands
,
int
byte
)
{
char
pattern
[
100
]
;
unsigned
char
size
;
rtx
code
=
XEXP
(
operands
[
0
]
,
0
)
;
size
=
nds32_byte_to_size
(
byte
)
;
switch
(
GET_CODE
(
code
)
)
{
case
REG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci\t%%1, %%0"
,
size
)
;
break
;
case
SYMBOL_REF
:
case
CONST
:
operands
[
0
]
=
XEXP
(
operands
[
0
]
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci.gp\t%%1, [ + %%0]"
,
size
)
;
break
;
case
POST_INC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci.bi\t%%1, %%0, %d"
,
size
,
byte
)
;
break
;
case
POST_DEC
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci.bi\t%%1, %%0, -%d"
,
size
,
byte
)
;
break
;
case
POST_MODIFY
:
switch
(
GET_CODE
(
XEXP
(
XEXP
(
code
,
1
)
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%c.bi\t%%1, %%0"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci.bi\t%%1, %%0"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
PLUS
:
switch
(
GET_CODE
(
XEXP
(
code
,
1
)
)
)
{
case
REG
:
case
SUBREG
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%c\t%%1, %%0"
,
size
)
;
break
;
case
CONST_INT
:
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci\t%%1, %%0"
,
size
)
;
break
;
default
:
abort
(
)
;
}
break
;
case
LO_SUM
:
operands
[
2
]
=
XEXP
(
code
,
1
)
;
operands
[
0
]
=
XEXP
(
code
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"s%ci\t%%1, [%%0 + lo12(%%2)]"
,
size
)
;
break
;
default
:
abort
(
)
;
}
output_asm_insn
(
pattern
,
operands
)
;
return
""
;
}
</s>


"StoreResults expects liveness tracking"

runOnMachineFunction - Emit the function body .


<s> void SIFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) { emitEntryFunctionPrologue ( MF , MBB ) ; return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; const SIRegisterInfo & TRI = TII -> getRegisterInfo ( ) ; unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; unsigned FramePtrReg = FuncInfo -> getFrameOffsetReg ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL ; bool NeedFP = hasFP ( MF ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; uint32_t RoundedSize = NumBytes ; const bool NeedsRealignment = TRI . needsStackRealignment ( MF ) ; if ( NeedsRealignment ) { assert ( NeedFP ) ; const unsigned Alignment = MFI . getMaxAlignment ( ) ; RoundedSize += Alignment ; unsigned ScratchSPReg = findScratchNonCalleeSaveRegister ( MBB ) ; assert ( ScratchSPReg != AMDGPU :: NoRegister ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_ADD_U32 ) , ScratchSPReg ) . addReg ( StackPtrReg ) . addImm ( ( Alignment - 1 ) * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_AND_B32 ) , FramePtrReg ) . addReg ( ScratchSPReg , RegState :: Kill ) . addImm ( - Alignment * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; FuncInfo -> setIsStackRealigned ( true ) ; } else if ( NeedFP ) { BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: COPY ) , FramePtrReg ) . addReg ( StackPtrReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( RoundedSize != 0 && hasSP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( AMDGPU :: S_ADD_U32 ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( const SIMachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; TII -> storeRegToStackSlot ( MBB , MBBI , Reg . VGPR , true , Reg . FI . getValue ( ) , & AMDGPU :: VGPR_32RegClass , & TII -> getRegisterInfo ( ) ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


Return the first register that is required to be saved . 16 if none .


<s> static bool riscv_classify_address ( struct riscv_address_info * info , rtx x , enum machine_mode mode , bool strict_p ) { switch ( GET_CODE ( x ) ) { case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , 0 ) ; info -> offset = XEXP ( x , 1 ) ; info -> symbol_type = riscv_classify_symbolic_expression ( info -> offset ) ; return ( riscv_valid_base_register_p ( info -> reg , mode , strict_p ) && riscv_valid_lo_sum_p ( info -> symbol_type , mode ) ) ; case CONST_INT : info -> type = ADDRESS_CONST_INT ; return SMALL_OPERAND ( INTVAL ( x ) ) ; default : return false ; } } </s>

Return true if X is a valid address for machine mode MODE . If it is , fill in INFO appropriately . STRICT_P is true if REG_OK_STRICT is in effect .


<s> void PIC16TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & tm ) { TargetLoweringObjectFile :: Initialize ( Ctx , tm ) ; TM = & tm ; ROMDATASection_ = NULL ; SHAREDUDATASection_ = NULL ; } </s>

This method must be called before any actual lowering is done .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> int HexagonMCInst :: getMaxValue ( void ) const { const uint64_t F = getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return ~ ( - 1U << ( bits - 1 ) ) ; else return ~ ( - 1U << bits ) ; } </s>

Return the maximal unsigned value possible given these KnownBits .

Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1U 1 1U


<s> void SPIRVAsmPrinter :: emitFunctionBodyEnd ( ) { outputOpFunctionEnd ( ) ; MAI -> BBNumToRegMap . clear ( ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> void SIInstrInfo :: legalizeOpWithMove ( MachineInstr & MI , unsigned OpIdx ) const { MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineOperand & MO = MI . getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI . getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Size = RI . getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == 64 ) ? AMDGPU :: V_MOV_B64_PSEUDO : AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) Opcode = AMDGPU :: COPY ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == 64 ) ? AMDGPU :: S_MOV_B64 : AMDGPU :: S_MOV_B32 ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & AMDGPU :: VReg_64RegClass , VRC ) ) VRC = & AMDGPU :: VReg_64RegClass ; else VRC = & AMDGPU :: VGPR_32RegClass ; Register Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI . getParent ( ) , I , DL , get ( Opcode ) , Reg ) . add ( MO ) ; MO . ChangeToRegister ( Reg , false ) ; } </s>

Legalize the OpIndex operand of this instruction by inserting a MOV .


<s> bool HexagonPacketizerList :: updateOffset ( SUnit * SUI , SUnit * SUJ ) { assert ( SUI -> getInstr ( ) && SUJ -> getInstr ( ) ) ; MachineInstr & MI = * SUI -> getInstr ( ) ; MachineInstr & MJ = * SUJ -> getInstr ( ) ; unsigned BPI , OPI ; if ( ! HII -> getBaseAndOffsetPosition ( MI , BPI , OPI ) ) return false ; unsigned BPJ , OPJ ; if ( ! HII -> getBaseAndOffsetPosition ( MJ , BPJ , OPJ ) ) return false ; unsigned Reg = MI . getOperand ( BPI ) . getReg ( ) ; if ( Reg != MJ . getOperand ( BPJ ) . getReg ( ) ) return false ; for ( const auto & PI : SUI -> Preds ) if ( PI . getKind ( ) != SDep :: Anti && ( PI . getKind ( ) != SDep :: Data || PI . getReg ( ) != Reg ) ) return false ; int Incr ; if ( ! HII -> getIncrementValue ( MJ , Incr ) ) return false ; int64_t Offset = MI . getOperand ( OPI ) . getImm ( ) ; MI . getOperand ( OPI ) . setImm ( Offset + Incr ) ; ChangedOffset = Offset ; return true ; } </s>

Return true if we can update the offset in MI so that MI and MJ can be packetized together .


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags Flags , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( VT == MVT :: Other || ( VT != MVT :: Other && VT . getSizeInBits ( ) > 1024 && VT . getStoreSize ( ) > 16 ) ) { return false ; } return allowsMisalignedMemoryAccessesImpl ( VT . getSizeInBits ( ) , AddrSpace , Align , Flags , IsFast ) ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static bool sh_legitimate_address_p ( machine_mode mode , rtx x , bool strict ) { if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return true ; if ( MAYBE_BASE_REGISTER_RTX_P ( x , strict ) ) return true ; else if ( ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( x , 0 ) , strict ) ) return true ; else if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; if ( REG_P ( xop0 ) && REGNO ( xop0 ) == GBR_REG ) return gbr_displacement ( xop1 , mode ) ; if ( GET_MODE_SIZE ( mode ) <= 8 && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) && sh_legitimate_index_p ( mode , xop1 , TARGET_SH2A , false ) ) return true ; if ( GET_MODE_SIZE ( mode ) <= 4 || ( TARGET_FPU_DOUBLE && TARGET_FMOVD && mode == DFmode ) ) { if ( MAYBE_BASE_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_INDEX_REGISTER_RTX_P ( xop0 , strict ) ) return true ; if ( MAYBE_INDEX_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) ) return true ; } } return false ; } </s>

Recognize an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . Allow REG REG+disp REG+r0 REG++ -- REG GBR GBR+disp


<s>
void
TriCoreAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
isPCRel
)
const
{
unsigned
NumBytes
=
4
;
Value
=
adjustFixupValue
(
Fixup
,
Value
)
;
if
(
!
Value
)
{
return
;
}
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


" was Pass-through, is now Dirty-out.\n"


<s> static void do_and3 ( rtx dest , rtx src1 , rtx src2 ) { if ( GET_MODE ( dest ) == DImode ) emit_insn ( gen_anddi3 ( dest , src1 , src2 ) ) ; else emit_insn ( gen_andsi3 ( dest , src1 , src2 ) ) ; } </s>

Emit an and of the proper mode for DEST . DEST is the destination register for the and . SRC1 is the first and input . SRC2 is the second and input . Computes DEST = SRC1 & SRC2 .


<s>
MachineBasicBlock
*
MSP430TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
if
(
Opc
==
MSP430
::
Shl8
||
Opc
==
MSP430
::
Shl16
||
Opc
==
MSP430
::
Sra8
||
Opc
==
MSP430
::
Sra16
||
Opc
==
MSP430
::
Srl8
||
Opc
==
MSP430
::
Srl16
)
return
EmitShiftInstr
(
MI
,
BB
)
;
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getSubtargetImpl
(
)
->
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
Opc
==
MSP430
::
Select16
||
Opc
==
MSP430
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
MSP430
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
->
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
MSP430
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void HexagonShuffler :: append ( MCInst const * ID , MCInst const * Extender , unsigned S , bool X ) { HexagonInstr PI ( ID , Extender , S , X ) ; Packet . push_back ( PI ) ; } </s>


<s> static void arc_initialize_trampoline ( rtx tramp , tree fndecl , rtx cxt ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_store_direct ( tramp , 0 , TARGET_BIG_ENDIAN ? 0x78e0d403 : 0xd40378e0 ) ; emit_store_direct ( tramp , 4 , TARGET_BIG_ENDIAN ? 0x170c700b : 0x700b170c ) ; emit_store_direct ( tramp , 8 , TARGET_BIG_ENDIAN ? 0x7c0078e0 : 0x78e07c00 ) ; emit_move_insn ( adjust_address ( tramp , SImode , 12 ) , fnaddr ) ; emit_move_insn ( adjust_address ( tramp , SImode , 16 ) , cxt ) ; emit_insn ( gen_flush_icache ( adjust_address ( tramp , SImode , 0 ) ) ) ; } </s>

With potentially multiple shared objects loaded , and multiple stacks present for multiple thereds where trampolines might reside , a simple range check will likely not suffice for the profiler to tell if a callee is a trampoline . We a speedier check by making the trampoline start at an address that is not 4-byte aligned . A trampoline looks like this : nop_s 0x78e0entry : ld_s r12 , [ pcl,12 ] 0xd403 ld r11 , [ pcl,12 ] 0x170c 700b j_s [ r12 ] 0x7c00 nop_s 0x78e0 The fastest trampoline to execute for trampolines within +-8KB of CTX would be : add2 r11 , pcl , s12 j [ limm ] 0x20200f80 limm and that would also be faster to write to the stack by computing the offset from CTX to TRAMP at compile time . However , it would really be better to get rid of the high cost of cache invalidation when generating trampolines , which requires that the code part of trampolines stays constant , and additionally either - making sure that no executable code but trampolines is on the stack , no icache entries linger for the area of the stack from when before the stack was allocated , and allocating trampolines in trampoline-only cache lines or - allocate trampolines fram a special pool of pre-allocated trampolines .


<s> void RISCVFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( RISCV :: X1 ) ; SavedRegs . set ( RISCV :: X8 ) ; } if ( hasBP ( MF ) ) SavedRegs . set ( RISCVABI :: getBPReg ( ) ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { RISCV :: X1 , RISCV :: X5 , RISCV :: X6 , RISCV :: X7 , RISCV :: X10 , RISCV :: X11 , RISCV :: X12 , RISCV :: X13 , RISCV :: X14 , RISCV :: X15 , RISCV :: X16 , RISCV :: X17 , RISCV :: X28 , RISCV :: X29 , RISCV :: X30 , RISCV :: X31 , 0 } ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = 0 ; Regs [ i ] ; ++ i ) if ( RISCV :: FPR16RegClass . contains ( Regs [ i ] ) || RISCV :: FPR32RegClass . contains ( Regs [ i ] ) || RISCV :: FPR64RegClass . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool RISCVPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> FastISel * X86TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { return X86 :: createFastISel ( funcInfo , libInfo ) ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> void TPCAsmInstCompress :: flushPendingInstructions ( MCStreamer & Out , const MCSubtargetInfo & STI ) { if ( ! compressEnabled ) { return ; } if ( ! Buffer . empty ( ) ) { flushBuffer ( Out , STI , true ) ; } if ( pInst != nullptr ) { Out . EmitInstruction ( prevInst , STI ) ; pInst = nullptr ; } } </s>

Ensure that all previously parsed instructions have been emitted to the output streamer , if the target does not emit them immediately .


<s> static void riscv_conditional_register_usage ( void ) { if ( TARGET_RVE ) { for ( int r = 16 ; r <= 31 ; r ++ ) fixed_regs [ r ] = 1 ; } if ( riscv_abi == ABI_ILP32E ) { for ( int r = 16 ; r <= 31 ; r ++ ) call_used_regs [ r ] = 1 ; } if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( UNITS_PER_FP_ARG == 0 ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = 1 ; } } </s>


<s> bool HexagonTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return TM . getSubtarget < HexagonSubtarget > ( ) . hasV5TOps ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


"PowerPC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static void nds32_group_tls_insn ( rtx insn ) { rtx pat = PATTERN ( insn ) ; rtx unspec_relax_group = XEXP ( XVECEXP ( pat , 0 , 1 ) , 0 ) ; int group_id = nds32_alloc_relax_group_id ( ) ; while ( GET_CODE ( pat ) != SET && GET_CODE ( pat ) == PARALLEL ) { pat = XVECEXP ( pat , 0 , 0 ) ; } if ( GET_CODE ( unspec_relax_group ) == UNSPEC && XINT ( unspec_relax_group , 1 ) == UNSPEC_VOLATILE_RELAX_GROUP ) { XVECEXP ( unspec_relax_group , 0 , 0 ) = GEN_INT ( group_id ) ; } } </s>


"%qs attribute only applies to functions"

Handle a `` naked '' attribute ; arguments as in struct attribute_spec.handler .


<s> bool XCoreInstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) { return true ; } MachineFunction * MF = MBB . getParent ( ) ; XCoreFunctionInfo * XFI = MF -> getInfo < XCoreFunctionInfo > ( ) ; bool emitFrameMoves = XCoreRegisterInfo :: needsFrameMoves ( * MF ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { MBB . addLiveIn ( it -> getReg ( ) ) ; storeRegToStackSlot ( MBB , MI , it -> getReg ( ) , true , it -> getFrameIdx ( ) , it -> getRegClass ( ) ) ; if ( emitFrameMoves ) { MCSymbol * SaveLabel = MF -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MI , DL , get ( XCore :: DBG_LABEL ) ) . addSym ( SaveLabel ) ; XFI -> getSpillLabels ( ) . push_back ( std :: make_pair ( SaveLabel , * it ) ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

XCore XCore XCore XCore XCore XCore::DBG_LABEL


<s> bool AMDGPUAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( ! AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ) return false ; if ( MBB -> empty ( ) ) return true ; return ( MBB -> back ( ) . getOpcode ( ) != AMDGPU :: S_SETPC_B64 ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> int condexec_memory_operand ( rtx op , machine_mode mode ) { machine_mode op_mode = GET_MODE ( op ) ; rtx addr ; if ( mode != VOIDmode && op_mode != mode ) return FALSE ; switch ( op_mode ) { default : return FALSE ; case E_QImode : case E_HImode : case E_SImode : case E_SFmode : break ; } if ( GET_CODE ( op ) != MEM ) return FALSE ; addr = XEXP ( op , 0 ) ; return frv_legitimate_address_p_1 ( mode , addr , reload_completed , TRUE , FALSE ) ; } </s>

Return true if the memory operand is one that can be conditionally executed .


<s> const char * X86TargetLowering :: LowerXConstraint ( MVT ConstraintVT ) const { if ( ConstraintVT . isFloatingPoint ( ) ) { if ( Subtarget -> hasSSE2 ( ) ) return "Y" ; if ( Subtarget -> hasSSE1 ( ) ) return "x" ; } return TargetLowering :: LowerXConstraint ( ConstraintVT ) ; } </s>

Try to replace an X constraint , which matches anything , with another that has more specific requirements based on the type of the corresponding operand .


<s> tree aarch64_general_fold_builtin ( unsigned int fcode , tree type , unsigned int n_args ATTRIBUTE_UNUSED , tree * args ) { switch ( fcode ) { BUILTIN_VDQF ( UNOP , abs , 2 , ALL ) return fold_build1 ( ABS_EXPR , type , args [ 0 ] ) ; VAR1 ( UNOP , floatv2si , 2 , ALL , v2sf ) VAR1 ( UNOP , floatv4si , 2 , ALL , v4sf ) VAR1 ( UNOP , floatv2di , 2 , ALL , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ 0 ] ) ; case AARCH64_SIMD_BUILTIN_LANE_CHECK : gcc_assert ( n_args == 3 ) ; if ( aarch64_fold_builtin_lane_check ( args [ 0 ] , args [ 1 ] , args [ 2 ] ) ) return void_node ; break ; default : break ; } return NULL_TREE ; } </s>

Try to fold a call to the built-in function with subcode FCODE . The function is passed the N_ARGS arguments in ARGS and it returns a value of type TYPE . Return the new expression on success and NULL_TREE on failure .


<s> bool R600InstrInfo :: fitsReadPortLimitations ( const std :: vector < MachineInstr * > & IG , const DenseMap < unsigned , unsigned > & PV , std :: vector < BankSwizzle > & ValidSwizzle , bool isLastAluTrans ) const { std :: vector < std :: vector < std :: pair < int , unsigned > > > IGSrcs ; ValidSwizzle . clear ( ) ; unsigned ConstCount ; BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = 0 , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( * IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , AMDGPU :: OpName :: bank_swizzle ) ; ValidSwizzle . push_back ( ( R600InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned > > TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const R600InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ; for ( unsigned i = 0 ; i < 4 ; i ++ ) { TransBS = TransSwz [ i ] ; if ( ! isConstCompatible ( TransBS , TransOps , ConstCount ) ) continue ; bool Result = FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; if ( Result ) { ValidSwizzle . push_back ( TransBS ) ; return true ; } } return false ; } </s>

Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ( in lexical order ) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available .


<s> static bool moxie_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { unsigned HOST_WIDE_INT size ; if ( type ) { if ( AGGREGATE_TYPE_P ( type ) ) return true ; size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; return size > 4 * 6 ; } </s>

Return non-zero if the function argument described by TYPE is to be passed by reference .


<s> static unsigned int ix86_select_alt_pic_regnum ( void ) { if ( current_function_is_leaf && ! current_function_profile ) { int i ; for ( i = 2 ; i >= 0 ; -- i ) if ( ! regs_ever_live [ i ] ) return i ; } return INVALID_REGNUM ; } </s>

Return > = 0 if there is an unused call-clobbered register available for the entire function .


<s> BasicBlock * getResult ( ) { return Result ; } </s>

Get the result of an analysis pass for a given IR unit .


<s> static bool rs6000_can_eliminate ( const int from , const int to ) { return ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : from == RS6000_PIC_OFFSET_TABLE_REGNUM ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size ( ) == 0 : true ) ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . Frame pointer elimination is automatically handled . For the RS/6000 , if frame pointer elimination is being done , we would like to convert ap into fp , not sp . We need r30 if -mminimal-toc was specified , and there are constant pool references .


<s> Instruction * llvm :: getInst ( Value * base , char * instName ) { Function * F = getParentFunction ( base ) ; if ( ! F ) return nullptr ; for ( inst_iterator it = inst_begin ( F ) , ie = inst_end ( F ) ; it != ie ; ++ it ) { Instruction * I = & * it ; if ( strcmp ( I -> getName ( ) . data ( ) , instName ) == 0 ) { return I ; } } return nullptr ; } </s>

If this is a normal dependency , returns the instruction that is depended on .


"Memory locations not expected for call return"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .