<s> bool Cpu0AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "0x" << StringRef ( utohexstr ( MO . getImm ( ) ) ) . lower ( ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << "0x" << StringRef ( utohexstr ( MO . getImm ( ) & 0xffff ) ) . lower ( ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - 1 ; return false ; case 'z' : { if ( MO . getType ( ) != MachineOperand :: MO_Immediate ) return true ; int64_t Val = MO . getImm ( ) ; if ( Val ) O << Val ; else O << "$0" ; return false ; } } } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool MipsTargetObjectFile :: IsGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM , SectionKind Kind ) const { return ( IsGlobalInSmallSectionImpl ( GO , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> TargetTransformInfo XCoreTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( XCoreTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s> void xstormy16_expand_arith ( enum machine_mode mode , enum rtx_code code , rtx dest , rtx src0 , rtx src1 , rtx carry ) { int num_words = GET_MODE_BITSIZE ( mode ) / BITS_PER_WORD ; int i ; int firstloop = 1 ; if ( code == NEG ) emit_move_insn ( src0 , const0_rtx ) ; for ( i = 0 ; i < num_words ; i ++ ) { rtx w_src0 , w_src1 , w_dest ; rtx insn ; w_src0 = simplify_gen_subreg ( word_mode , src0 , mode , i * UNITS_PER_WORD ) ; w_src1 = simplify_gen_subreg ( word_mode , src1 , mode , i * UNITS_PER_WORD ) ; w_dest = simplify_gen_subreg ( word_mode , dest , mode , i * UNITS_PER_WORD ) ; switch ( code ) { case PLUS : if ( firstloop && GET_CODE ( w_src1 ) == CONST_INT && INTVAL ( w_src1 ) == 0 ) continue ; if ( firstloop ) insn = gen_addchi4 ( w_dest , w_src0 , w_src1 , carry ) ; else insn = gen_addchi5 ( w_dest , w_src0 , w_src1 , carry , carry ) ; break ; case NEG : case MINUS : case COMPARE : if ( code == COMPARE && i == num_words - 1 ) { rtx branch , sub , clobber , sub_1 ; sub_1 = gen_rtx_MINUS ( HImode , w_src0 , gen_rtx_ZERO_EXTEND ( HImode , carry ) ) ; sub = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_MINUS ( HImode , sub_1 , w_src1 ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , carry ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( HImode , sub_1 , w_src1 ) , pc_rtx , pc_rtx ) ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 3 , branch , sub , clobber ) ) ; } else if ( firstloop && code != COMPARE && GET_CODE ( w_src1 ) == CONST_INT && INTVAL ( w_src1 ) == 0 ) continue ; else if ( firstloop ) insn = gen_subchi4 ( w_dest , w_src0 , w_src1 , carry ) ; else insn = gen_subchi5 ( w_dest , w_src0 , w_src1 , carry , carry ) ; break ; case IOR : case XOR : case AND : if ( GET_CODE ( w_src1 ) == CONST_INT && INTVAL ( w_src1 ) == - ( code == AND ) ) continue ; insn = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_fmt_ee ( code , mode , w_src0 , w_src1 ) ) ; break ; case NOT : insn = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_NOT ( mode , w_src0 ) ) ; break ; default : gcc_unreachable ( ) ; } firstloop = 0 ; emit ( insn ) ; } if ( firstloop ) emit ( gen_nop ( ) ) ; } </s>

Expander for arithmetic operations ; emit insns to compute ( set DEST ( CODE : MODE SRC0 SRC1 ) ) using CARRY as a temporary . When CODE is COMPARE , a branch template is generated ( this saves duplicating code in xstormy16_split_cbranch ) .


<s> void riscv_cpu_cpp_builtins ( cpp_reader * pfile ) { builtin_define ( "__riscv" ) ; if ( TARGET_RVC ) builtin_define ( "__riscv_compressed" ) ; if ( TARGET_ATOMIC ) builtin_define ( "__riscv_atomic" ) ; if ( TARGET_MUL ) builtin_define ( "__riscv_mul" ) ; if ( TARGET_DIV ) builtin_define ( "__riscv_div" ) ; if ( TARGET_DIV && TARGET_MUL ) builtin_define ( "__riscv_muldiv" ) ; builtin_define_with_int_value ( "__riscv_xlen" , UNITS_PER_WORD * 8 ) ; if ( TARGET_HARD_FLOAT ) builtin_define_with_int_value ( "__riscv_flen" , UNITS_PER_FP_REG * 8 ) ; if ( TARGET_HARD_FLOAT && TARGET_FDIV ) { builtin_define ( "__riscv_fdiv" ) ; builtin_define ( "__riscv_fsqrt" ) ; } switch ( riscv_abi ) { case ABI_ILP32 : case ABI_LP64 : builtin_define ( "__riscv_float_abi_soft" ) ; break ; case ABI_ILP32F : case ABI_LP64F : builtin_define ( "__riscv_float_abi_single" ) ; break ; case ABI_ILP32D : case ABI_LP64D : builtin_define ( "__riscv_float_abi_double" ) ; break ; } switch ( riscv_cmodel ) { case CM_MEDLOW : builtin_define ( "__riscv_cmodel_medlow" ) ; break ; case CM_MEDANY : builtin_define ( "__riscv_cmodel_medany" ) ; break ; case CM_PIC : builtin_define ( "__riscv_cmodel_pic" ) ; break ; } } </s>


<s> static bool rs6000_use_blocks_for_constant_p ( machine_mode mode , const_rtx x ) { return ! ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ; } </s>


<s> inline bool vgpr_vector_mode_p ( machine_mode mode ) { return ( mode == V64QImode || mode == V64HImode || mode == V64SImode || mode == V64DImode || mode == V64HFmode || mode == V64SFmode || mode == V64DFmode ) ; } </s>

Return true if MODE can be handled directly by VGPR operations .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasOpaqueSPAdjustment ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . hasEHFunclets ( ) || MMI . callsEHReturn ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , isLittle ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ; } </s>


<s> void emitBundleLock ( bool AlignToEnd ) override { } </s>

The following instructions are a bundle-locked group .


<s> bool Cpu0SEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Cpu0 :: RetLR : expandRetLR ( MBB , MI ) ; break ; case Cpu0 :: CPU0eh_return32 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> tree aarch64_fold_builtin ( tree fndecl , int n_args ATTRIBUTE_UNUSED , tree * args , bool ignore ATTRIBUTE_UNUSED ) { int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree type = TREE_TYPE ( TREE_TYPE ( fndecl ) ) ; switch ( fcode ) { BUILTIN_VDQF ( UNOP , abs , 2 ) return fold_build1 ( ABS_EXPR , type , args [ 0 ] ) ; break ; VAR1 ( UNOP , floatv2si , 2 , v2sf ) VAR1 ( UNOP , floatv4si , 2 , v4sf ) VAR1 ( UNOP , floatv2di , 2 , v2df ) return fold_build1 ( FLOAT_EXPR , type , args [ 0 ] ) ; default : break ; } return NULL_TREE ; } </s>


<s> void LanaiInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annotation , const MCSubtargetInfo & STI ) { if ( ! printAlias ( MI , OS ) && ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annotation ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
PPC
::
NumTargetFixupKinds
]
=
{
{
"fixup_ppc_br24"
,
6
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_brcond14"
,
16
,
14
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_ppc_half16"
,
0
,
16
,
0
}
,
{
"fixup_ppc_half16ds"
,
0
,
14
,
0
}
,
{
"fixup_ppc_tlsreg"
,
0
,
0
,
0
}
,
{
"fixup_ppc_nofixup"
,
0
,
0
,
0
}
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


"frame pointer should not have been eliminated"

"SecondSPAdjustAmount should be greater than zero"


<s> static bool rs6000_legitimate_address_p ( machine_mode mode , rtx x , bool reg_ok_strict ) { bool reg_offset_p = reg_offset_addressing_ok_p ( mode ) ; if ( VECTOR_MEM_ALTIVEC_P ( mode ) && GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && INTVAL ( XEXP ( x , 1 ) ) == - 16 ) x = XEXP ( x , 0 ) ; if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return 0 ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) ) return 1 ; if ( virtual_stack_registers_memory_p ( x ) ) return 1 ; if ( reg_offset_p && legitimate_small_data_p ( mode , x ) ) return 1 ; if ( reg_offset_p && legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return 1 ; if ( reg_offset_p && reg_addr [ mode ] . fused_toc && GET_CODE ( x ) == UNSPEC && XINT ( x , 1 ) == UNSPEC_FUSION_ADDIS ) return 1 ; if ( mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE ) return 0 ; if ( ! reg_ok_strict && reg_offset_p && GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == REG && ( XEXP ( x , 0 ) == virtual_stack_vars_rtx || XEXP ( x , 0 ) == arg_pointer_rtx ) && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) return 1 ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return 1 ; if ( ! FLOAT128_2REG_P ( mode ) && ( ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ) || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) || ( TARGET_E500_DOUBLE && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , 1 ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , 1 ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) return 1 ; if ( reg_offset_p && legitimate_lo_sum_address_p ( mode , x , reg_ok_strict ) ) return 1 ; return 0 ; } </s>

TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . On the RS/6000 , there are four valid address : a SYMBOL_REF that refers to a constant pool entry of an address ( or the sum of it plus a constant ) , a short ( 16-bit signed ) constant plus a register , the sum of two registers , or a register indirect , possibly with an auto-increment . For DFmode , DDmode and DImode with a constant plus register , we must ensure that both words are addressable or PowerPC64 with offset word aligned . For modes spanning multiple registers ( DFmode and DDmode in 32-bit GPRs , 32-bit DImode , TImode , TFmode , TDmode ) , indexed addressing can not be used because adjacent memory cells are accessed by adding word-sized offsets during assembly output .


<s> bool HSAILTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return true ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> StringRef getPassName ( ) const override { return "AMDGPUPostLegalizerCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static opt_scalar_float_mode rs6000_floatn_mode ( int n , bool extended ) { if ( extended ) { switch ( n ) { case 32 : return DFmode ; case 64 : if ( TARGET_FLOAT128_TYPE ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return opt_scalar_float_mode ( ) ; case 128 : return opt_scalar_float_mode ( ) ; default : gcc_unreachable ( ) ; } } else { switch ( n ) { case 32 : return SFmode ; case 64 : return DFmode ; case 128 : if ( TARGET_FLOAT128_TYPE ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return opt_scalar_float_mode ( ) ; default : return opt_scalar_float_mode ( ) ; } } } </s>


<s> bool AArch64_MC :: isFpOrNEON ( const MCInst & MI , const MCInstrInfo * MCII ) { const auto & FPR128 = AArch64MCRegisterClasses [ AArch64 :: FPR128RegClassID ] ; const auto & FPR64 = AArch64MCRegisterClasses [ AArch64 :: FPR64RegClassID ] ; const auto & FPR32 = AArch64MCRegisterClasses [ AArch64 :: FPR32RegClassID ] ; const auto & FPR16 = AArch64MCRegisterClasses [ AArch64 :: FPR16RegClassID ] ; const auto & FPR8 = AArch64MCRegisterClasses [ AArch64 :: FPR8RegClassID ] ; auto IsFPR = [ & ] ( const MCOperand & Op ) { if ( ! Op . isReg ( ) ) return false ; auto Reg = Op . getReg ( ) ; return FPR128 . contains ( Reg ) || FPR64 . contains ( Reg ) || FPR32 . contains ( Reg ) || FPR16 . contains ( Reg ) || FPR8 . contains ( Reg ) ; } ; return llvm :: any_of ( MI , IsFPR ) ; } </s>

Returns whether the instruction is FP or NEON .


<s> static void riscv_emit_float_compare ( enum rtx_code * code , rtx * op0 , rtx * op1 ) { rtx tmp0 , tmp1 , cmp_op0 = * op0 , cmp_op1 = * op1 ; enum rtx_code fp_code = * code ; * code = NE ; switch ( fp_code ) { case UNORDERED : * code = EQ ; case ORDERED : tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; case UNEQ : * code = EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; break ; case LTGT : tmp0 = riscv_force_binary ( word_mode , LT , cmp_op0 , cmp_op1 ) ; tmp1 = riscv_force_binary ( word_mode , GT , cmp_op0 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , IOR , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; default : gcc_unreachable ( ) ; } } </s>

Like riscv_emit_int_compare , but for floating-point comparisons .


<s> ARMSubtarget :: ARMSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const ARMBaseTargetMachine & TM , bool IsLittle ) : ARMGenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( ARMBaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( ARMBaseInstrInfo * ) new ARMInstrInfo ( * this ) : ( ARMBaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .


runOnMachineFunction - Emit the function body .


<s> void TPCHazardRecognizer :: reserveResources ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( ! MI -> isPseudo ( ) ) Resources -> reserveResources ( * MI ) ; CurrentPacket . push_back ( SU ) ; } </s>


<s>
void
CAHPAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
if
(
!
Value
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
return
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> static bool isThumb ( const MCSubtargetInfo & STI ) { return STI . getFeatureBits ( ) [ ARM :: ModeThumb ] ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> static rtx cris_function_arg ( cumulative_args_t ca , machine_mode mode , const_tree type , bool named ) { return cris_function_arg_1 ( ca , mode , type , named , false ) ; } </s>

Worker function for TARGET_FUNCTION_ARG . The void_type_node is sent as a `` closing '' call .


<s>
static
tree
h8300_handle_eightbit_data_attribute
(
tree
*
node
,
tree
name
,
tree
args
ATTRIBUTE_UNUSED
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
tree
decl
=
*
node
;
if
(
TREE_STATIC
(
decl
)
||
DECL_EXTERNAL
(
decl
)
)
{
set_decl_section_name
(
decl
,
".eight"
)
;
}
else
{
warning
(
OPT_Wattributes
,
"%qE attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
return
NULL_TREE
;
}
</s>

Handle an `` eightbit_data '' attribute ; arguments as in struct attribute_spec.handler .


<s> int nds32_can_use_bset_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) ) ; return ( TARGET_PERF_EXT && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bset ' instruction can be used with IVAL .


<s> inline static bool isMem ( const MachineInstr * MI , unsigned Op ) { if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + 4 <= MI -> getNumOperands ( ) && MI -> getOperand ( Op ) . isReg ( ) && isScale ( MI -> getOperand ( Op + 1 ) ) && MI -> getOperand ( Op + 2 ) . isReg ( ) && ( MI -> getOperand ( Op + 3 ) . isImm ( ) || MI -> getOperand ( Op + 3 ) . isGlobal ( ) || MI -> getOperand ( Op + 3 ) . isCPI ( ) || MI -> getOperand ( Op + 3 ) . isJTI ( ) ) ; } </s>


<s> int nds32_target_alignment ( rtx_insn * label ) { rtx_insn * insn ; if ( optimize_size ) return 0 ; insn = next_active_insn ( label ) ; if ( insn == 0 ) return 0 ; else if ( ( get_attr_length ( insn ) % 4 ) == 0 ) return 2 ; else return 0 ; } </s>

Return align 2 ( log base 2 ) if the next instruction of LABEL is 4 byte .


<s> bool ARMAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { const uint16_t Thumb1_16bitNopEncoding = 0x46c0 ; const uint16_t Thumb2_16bitNopEncoding = 0xbf00 ; const uint32_t ARMv4_NopEncoding = 0xe1a00000 ; const uint32_t ARMv6T2_NopEncoding = 0xe320f000 ; if ( isThumb ( ) ) { const uint16_t nopEncoding = hasNOP ( ) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write16 ( nopEncoding ) ; if ( Count & 1 ) OW -> Write8 ( 0 ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % 4 ) { default : break ; case 1 : OW -> Write8 ( 0 ) ; break ; case 2 : OW -> Write16 ( 0 ) ; break ; case 3 : OW -> Write16 ( 0 ) ; OW -> Write8 ( 0xa0 ) ; break ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
static
void
arc_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
,
tree
function
)
{
const
char
*
fnname
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
thunk
)
)
;
int
mi_delta
=
delta
;
const
char
*
const
mi_op
=
mi_delta
<
0
"sub"
:
"add"
;
int
shift
=
0
;
int
this_regno
=
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
1
:
0
;
rtx
fnaddr
;
assemble_start_function
(
thunk
,
fnname
)
;
if
(
mi_delta
<
0
)
mi_delta
=
mi_delta
;
while
(
mi_delta
!=
0
)
{
if
(
(
mi_delta
&
(
3
<<
shift
)
)
==
0
)
shift
+=
2
;
else
{
asm_fprintf
(
file
,
"\t%s\t%s, %s, %d\n"
,
mi_op
,
reg_names
[
this_regno
]
,
reg_names
[
this_regno
]
,
mi_delta
&
(
0xff
<<
shift
)
)
;
mi_delta
&=
~
(
0xff
<<
shift
)
;
shift
+=
8
;
}
}
if
(
vcall_offset
!=
0
)
{
asm_fprintf
(
file
,
"\tld\t%s, [%s]\n"
,
ARC_TEMP_SCRATCH_REG
,
reg_names
[
this_regno
]
)
;
asm_fprintf
(
file
,
"\tadd\t%s, %s, "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
ARC_TEMP_SCRATCH_REG
,
ARC_TEMP_SCRATCH_REG
,
vcall_offset
)
;
asm_fprintf
(
file
,
"\tld\t%s, [%s]\n"
,
ARC_TEMP_SCRATCH_REG
,
ARC_TEMP_SCRATCH_REG
)
;
asm_fprintf
(
file
,
"\tadd\t%s, %s, %s\n"
,
reg_names
[
this_regno
]
,
reg_names
[
this_regno
]
,
ARC_TEMP_SCRATCH_REG
)
;
}
fnaddr
=
XEXP
(
DECL_RTL
(
function
)
,
0
)
;
if
(
arc_is_longcall_p
(
fnaddr
)
)
{
if
(
flag_pic
)
{
asm_fprintf
(
file
,
"\tld\t%s, [pcl, @"
,
ARC_TEMP_SCRATCH_REG
)
;
assemble_name
(
file
,
XSTR
(
fnaddr
,
0
)
)
;
fputs
(
"@gotpc]\n"
,
file
)
;
asm_fprintf
(
file
,
"\tj\t[%s]"
,
ARC_TEMP_SCRATCH_REG
)
;
}
else
{
fputs
(
"\tj\t@"
,
file
)
;
assemble_name
(
file
,
XSTR
(
fnaddr
,
0
)
)
;
}
}
else
{
fputs
(
"\tb\t@"
,
file
)
;
assemble_name
(
file
,
XSTR
(
fnaddr
,
0
)
)
;
if
(
flag_pic
)
fputs
(
"@plt\n"
,
file
)
;
}
fputc
(
'\n'
,
file
)
;
assemble_end_function
(
thunk
,
fnname
)
;
}
</s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


"All regions recorded, starting actual scheduling.\n"

"Retrying function scheduling without clustering.\n"

"Retrying function scheduling with lowest recorded occupancy "

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


<s> void X86FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( 0 ) . getImm ( ) : 0 ; uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( 1 ) . getImm ( ) : 0 ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { if ( Amount == 0 ) return ; unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; Amount -= InternalAmt ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( MF . getFunction ( ) -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ; } return ; } if ( isDestroy && InternalAmt ) { MachineBasicBlock :: iterator B = MBB . begin ( ) ; while ( I != B && ! std :: prev ( I ) -> isCall ( ) ) -- I ; BuildStackAdjustment ( MBB , I , DL , - InternalAmt , false ) ; } } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> SDValue AMDGPUTargetLowering :: SplitVectorStore ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; SDValue Val = Store -> getValue ( ) ; EVT VT = Val . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return scalarizeVectorStore ( Store , DAG ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , BaseAlign ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , HiAlign ) ; return DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoStore , HiStore ) ; } </s>

Split a vector store into 2 stores of half the vector .

AMDGPU AMDGPU 2 ISD::ADD ISD::TokenFactor MVT::Other


<s> bool AMDGPUTargetLowering :: isKnownNeverNaNForTargetNode ( SDValue Op , const SelectionDAG & DAG , bool SNaN , unsigned Depth ) const { unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case AMDGPUISD :: FMIN_LEGACY : case AMDGPUISD :: FMAX_LEGACY : { if ( SNaN ) return true ; return false ; } case AMDGPUISD :: FMUL_LEGACY : case AMDGPUISD :: CVT_PKRTZ_F16_F32 : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: FMED3 : case AMDGPUISD :: FMIN3 : case AMDGPUISD :: FMAX3 : case AMDGPUISD :: FMAD_FTZ : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 2 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: CVT_F32_UBYTE0 : case AMDGPUISD :: CVT_F32_UBYTE1 : case AMDGPUISD :: CVT_F32_UBYTE2 : case AMDGPUISD :: CVT_F32_UBYTE3 : return true ; case AMDGPUISD :: RCP : case AMDGPUISD :: RSQ : case AMDGPUISD :: RCP_LEGACY : case AMDGPUISD :: RSQ_CLAMP : { if ( SNaN ) return true ; return false ; } case AMDGPUISD :: LDEXP : case AMDGPUISD :: FRACT : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 0 ) , SNaN , Depth + 1 ) ; } case AMDGPUISD :: DIV_SCALE : case AMDGPUISD :: DIV_FMAS : case AMDGPUISD :: DIV_FIXUP : case AMDGPUISD :: TRIG_PREOP : return SNaN ; case AMDGPUISD :: SIN_HW : case AMDGPUISD :: COS_HW : { return SNaN ; } case ISD :: INTRINSIC_WO_CHAIN : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; switch ( IntrinsicID ) { case Intrinsic :: amdgcn_cubeid : return true ; case Intrinsic :: amdgcn_frexp_mant : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) ; } case Intrinsic :: amdgcn_cvt_pkrtz : { if ( SNaN ) return true ; return DAG . isKnownNeverNaN ( Op . getOperand ( 1 ) , SNaN , Depth + 1 ) && DAG . isKnownNeverNaN ( Op . getOperand ( 2 ) , SNaN , Depth + 1 ) ; } case Intrinsic :: amdgcn_rcp : case Intrinsic :: amdgcn_rsq : case Intrinsic :: amdgcn_rcp_legacy : case Intrinsic :: amdgcn_rsq_legacy : case Intrinsic :: amdgcn_rsq_clamp : { if ( SNaN ) return true ; return false ; } case Intrinsic :: amdgcn_fdot2 : return SNaN ; default : return false ; } } default : return false ; } } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"optimise teak move immediate pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

Teak
"optimise teak move immediate pass"


<s> TargetPassConfig * CAHPTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new CAHPPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool ARMBaseTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createARMISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void addFastRegAlloc ( ) override { addOptimizedRegAlloc ( ) ; } </s>

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation .


<s> void RISCVInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned LoadOpcode , StoreOpcode ; getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , get ( StoreOpcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) , FrameIdx ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s>
MachineBasicBlock
*
RISCVTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
assert
(
MI
.
getOpcode
(
)
==
RISCV
::
Select_GPR_Using_CC_GPR
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
HeadMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
TailMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
IfFalseMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
IfFalseMBB
)
;
F
->
insert
(
I
,
TailMBB
)
;
TailMBB
->
splice
(
TailMBB
->
begin
(
)
,
HeadMBB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
HeadMBB
->
end
(
)
)
;
TailMBB
->
transferSuccessorsAndUpdatePHIs
(
HeadMBB
)
;
HeadMBB
->
addSuccessor
(
IfFalseMBB
)
;
HeadMBB
->
addSuccessor
(
TailMBB
)
;
unsigned
LHS
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
unsigned
RHS
=
MI
.
getOperand
(
2
)
.
getReg
(
)
;
auto
CC
=
static_cast
<
ISD
::
CondCode
>
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
unsigned
Opcode
=
getBranchOpcodeForIntCondCode
(
CC
)
;
BuildMI
(
HeadMBB
,
DL
,
TII
.
get
(
Opcode
)
)
.
addReg
(
LHS
)
.
addReg
(
RHS
)
.
addMBB
(
TailMBB
)
;
IfFalseMBB
->
addSuccessor
(
TailMBB
)
;
BuildMI
(
*
TailMBB
,
TailMBB
->
begin
(
)
,
DL
,
TII
.
get
(
RISCV
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
4
)
.
getReg
(
)
)
.
addMBB
(
HeadMBB
)
.
addReg
(
MI
.
getOperand
(
5
)
.
getReg
(
)
)
.
addMBB
(
IfFalseMBB
)
;
MI
.
eraseFromParent
(
)
;
return
TailMBB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
MachineBasicBlock
::
iterator
SIFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
==
0
)
return
MBB
.
erase
(
I
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
const
DebugLoc
&
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
I
->
getOpcode
(
)
;
bool
IsDestroy
=
Opc
==
TII
->
getCallFrameDestroyOpcode
(
)
;
uint64_t
CalleePopAmount
=
IsDestroy
I
->
getOperand
(
1
)
.
getImm
(
)
:
0
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
unsigned
Align
=
getStackAlignment
(
)
;
Amount
=
alignTo
(
Amount
,
Align
)
;
assert
(
isUInt
<
32
>
(
Amount
)
&&
"exceeded stack address space size"
)
;
const
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
unsigned
SPReg
=
MFI
->
getStackPtrOffsetReg
(
)
;
unsigned
Op
=
IsDestroy
AMDGPU
::
S_SUB_U32
:
AMDGPU
::
S_ADD_U32
;
BuildMI
(
MBB
,
I
,
DL
,
TII
->
get
(
Op
)
,
SPReg
)
.
addReg
(
SPReg
)
.
addImm
(
Amount
*
ST
.
getWavefrontSize
(
)
)
;
}
else
if
(
CalleePopAmount
!=
0
)
{
llvm_unreachable
(
"is this used?"
)
;
}
return
MBB
.
erase
(
I
)
;
}
</s>


<s> bool RISCVTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( Subtarget . is64Bit ( ) && Type == MVT :: i32 ) return true ; return IsSigned ; } </s>

Returns true if arguments should be sign-extended in lib calls .


<s> void setName ( StringRef N ) { Name = std :: string ( N ) ; } </s>

Change the name of this type to the specified name , or to a name with a suffix if there is a collision .


<s> unsigned AllocateReg ( const unsigned * Regs , const unsigned * ShadowRegs , unsigned NumRegs ) { unsigned FirstUnalloc = getFirstUnallocated ( Regs , NumRegs ) ; if ( FirstUnalloc == NumRegs ) return 0 ; unsigned Reg = Regs [ FirstUnalloc ] , ShadowReg = ShadowRegs [ FirstUnalloc ] ; MarkAllocated ( Reg ) ; MarkAllocated ( ShadowReg ) ; return Reg ; } </s>

Version of AllocateReg with list of registers to be shadowed .


<s> bool R600InstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( MI -> getOpcode ( ) == AMDGPU :: KILLGT ) { return false ; } else if ( MI -> getOpcode ( ) == AMDGPU :: CF_ALU ) { if ( MI -> getParent ( ) -> begin ( ) != MachineBasicBlock :: iterator ( MI ) ) return false ; if ( MI -> getOperand ( 3 ) . getImm ( ) != 0 || MI -> getOperand ( 4 ) . getImm ( ) != 0 ) return false ; return true ; } else if ( isVector ( * MI ) ) { return false ; } else { return AMDGPUInstrInfo :: isPredicable ( MI ) ; } } </s>

Return true if the specified instruction can be predicated .


<s> const char * MCS51TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { case MCS51ISD :: name : \ return # name switch ( Opcode ) { default : return nullptr ; NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ; NODE ( ROR ) ; NODE ( ASR ) ; NODE ( LSLLOOP ) ; NODE ( LSRLOOP ) ; NODE ( ROLLOOP ) ; NODE ( RORLOOP ) ; NODE ( ASRLOOP ) ; NODE ( BRCOND ) ; NODE ( CMP ) ; NODE ( CMPC ) ; NODE ( TST ) ; NODE ( SELECT_CC ) ; } </s>

getTargetNodeName - This method returns the name of a target specific


"-mcall-ms2sysv-xlogues is not compatible with %s"

Emits a warning for unsupported msabi to sysv pro/epilogues .


"ReadCycleWrite is only to be used on riscv32"


<s> void ix86_emit_i387_sinh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx half = const_double_from_real_value ( dconsthalf , XFmode ) ; rtx cst1 , tmp ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx_insn * insn ; emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_absxf2 ( e2 , op1 ) ) ; emit_insn ( gen_expm1xf2 ( e1 , e2 ) ) ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( e2 , e1 , cst1 ) ) ; emit_insn ( gen_divxf3 ( e2 , e1 , e2 ) ) ; emit_insn ( gen_addxf3 ( e2 , e2 , e1 ) ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( 0x02 ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * 50 / 100 ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = 1 ; half = force_reg ( XFmode , half ) ; emit_insn ( gen_mulxf3 ( op0 , e2 , half ) ) ; } </s>

Output code to perform an sinh XFmode calculation .


<s> inline bool mips_lo_sum_offset_hasher :: equal ( const mips_lo_sum_offset * entry , const rtx_def * value ) { return rtx_equal_p ( entry -> base , value ) ; } </s>


<s> bool ARM64TargetLowering :: hasPairedLoad ( EVT LoadedType , unsigned & RequiredAligment ) const { if ( ! LoadedType . isSimple ( ) || ( ! LoadedType . isInteger ( ) && ! LoadedType . isFloatingPoint ( ) ) ) return false ; RequiredAligment = 0 ; unsigned NumBits = LoadedType . getSizeInBits ( ) ; return NumBits == 32 || NumBits == 64 ; } </s>

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory .


<s>
void
PPCAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
MCInst
TmpInst
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
break
;
case
TargetOpcode
::
DBG_VALUE
:
{
if
(
!
isVerbose
(
)
||
!
OutStreamer
.
hasRawTextSupport
(
)
)
return
;
SmallString
<
32
>
Str
;
raw_svector_ostream
O
(
Str
)
;
unsigned
NOps
=
MI
->
getNumOperands
(
)
;
assert
(
NOps
==
4
)
;
O
<<
'\t'
<<
MAI
->
getCommentString
(
)
<<
"DEBUG_VALUE: "
;
DIVariable
V
(
const_cast
<
MDNode
*
>
(
MI
->
getOperand
(
NOps
1
)
.
getMetadata
(
)
)
)
;
O
<<
V
.
getName
(
)
;
O
<<
" <- "
;
assert
(
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
MI
->
getOperand
(
1
)
.
isImm
(
)
)
;
O
<<
'['
;
printOperand
(
MI
,
0
,
O
)
;
O
<<
'+'
;
printOperand
(
MI
,
1
,
O
)
;
O
<<
']'
;
O
<<
"+"
;
printOperand
(
MI
,
NOps
2
,
O
)
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
return
;
}
case
PPC
::
MovePCtoLR
:
case
PPC
::
MovePCtoLR8
:
{
MCSymbol
*
PICBase
=
MF
->
getPICBaseSymbol
(
)
;
TmpInst
.
setOpcode
(
PPC
::
BL_Darwin
)
;
TmpInst
.
addOperand
(
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
PICBase
,
OutContext
)
)
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
OutStreamer
.
EmitLabel
(
PICBase
)
;
return
;
}
case
PPC
::
LDtoc
:
{
LowerPPCMachineInstrToMCInst
(
MI
,
TmpInst
,
*
this
,
Subtarget
.
isDarwin
(
)
)
;
TmpInst
.
setOpcode
(
PPC
::
LD
)
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
1
)
;
assert
(
MO
.
isGlobal
(
)
)
;
MCSymbol
*
&
TOCEntry
=
TOC
[
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
]
;
if
(
TOCEntry
==
0
)
TOCEntry
=
GetTempSymbol
(
"C"
,
TOCLabelID
++
)
;
const
MCExpr
*
Exp
=
MCSymbolRefExpr
::
Create
(
TOCEntry
,
MCSymbolRefExpr
::
VK_PPC_TOC
,
OutContext
)
;
TmpInst
.
getOperand
(
1
)
=
MCOperand
::
CreateExpr
(
Exp
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
return
;
}
case
PPC
::
MFCRpseud
:
OutStreamer
.
AddComment
(
PPCInstPrinter
::
getRegisterName
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
)
;
TmpInst
.
setOpcode
(
PPC
::
MFCR
)
;
TmpInst
.
addOperand
(
MCOperand
::
CreateReg
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
return
;
}
LowerPPCMachineInstrToMCInst
(
MI
,
TmpInst
,
*
this
,
Subtarget
.
isDarwin
(
)
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool F2003fFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void emitImportModule ( const MCSymbolWasm * Sym , StringRef ModuleName ) override { } </s>


<s>
void
VEInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
if
(
IsAliasOfSX
(
SrcReg
)
&&
IsAliasOfSX
(
DestReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
ORri
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
}
else
if
(
VE
::
V64RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
Register
TmpReg
=
VE
::
SX16
;
Register
SubTmp
=
TRI
->
getSubReg
(
TmpReg
,
VE
::
sub_i32
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
LEAzii
)
,
TmpReg
)
.
addImm
(
0
)
.
addImm
(
0
)
.
addImm
(
256
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
VE
::
VORmvl
)
,
DestReg
)
.
addImm
(
M1
(
0
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addReg
(
SubTmp
,
getKillRegState
(
true
)
)
;
MIB
.
getInstr
(
)
->
addRegisterKilled
(
TmpReg
,
TRI
,
true
)
;
}
else
if
(
VE
::
F128RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
const
unsigned
SubRegIdx
[
]
=
{
VE
::
sub_even
,
VE
::
sub_odd
}
;
unsigned
int
NumSubRegs
=
2
;
copyPhysSubRegs
(
MBB
,
I
,
DL
,
DestReg
,
SrcReg
,
KillSrc
,
get
(
VE
::
ORri
)
,
NumSubRegs
,
SubRegIdx
,
&
getRegisterInfo
(
)
)
;
}
else
{
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
dbgs
(
)
<<
"Impossible reg-to-reg copy from "
<<
printReg
(
SrcReg
,
TRI
)
<<
" to "
<<
printReg
(
DestReg
,
TRI
)
<<
"\n"
;
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
}
</s>


<s> void cris_emit_trap_for_misalignment ( rtx mem ) { rtx addr , reg , ok_label , andop ; rtx_insn * jmp ; int natural_alignment ; gcc_assert ( MEM_P ( mem ) ) ; natural_alignment = GET_MODE_SIZE ( GET_MODE ( mem ) ) ; addr = XEXP ( mem , 0 ) ; reg = force_reg ( Pmode , addr ) ; ok_label = gen_label_rtx ( ) ; andop = gen_rtx_AND ( Pmode , reg , GEN_INT ( natural_alignment - 1 ) ) ; emit_cmp_and_jump_insns ( force_reg ( SImode , andop ) , const0_rtx , EQ , NULL_RTX , Pmode , 1 , ok_label ) ; jmp = get_last_insn ( ) ; gcc_assert ( JUMP_P ( jmp ) ) ; predict_insn_def ( jmp , PRED_NORETURN , TAKEN ) ; expand_builtin_trap ( ) ; emit_label ( ok_label ) ; } </s>

Emit checking that MEM is aligned for an access in MODE , failing that , executing a `` break 8 '' ( or call to abort , if `` break 8 '' is disabled ) .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; ModulePass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const char * IA64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case IA64ISD :: GETFD : return "IA64ISD::GETFD" ; case IA64ISD :: BRCALL : return "IA64ISD::BRCALL" ; case IA64ISD :: RET_FLAG : return "IA64ISD::RET_FLAG" ; } } </s>


<s> static void arm_block_move_unaligned_loop ( rtx dest , rtx src , HOST_WIDE_INT length , unsigned int interleave_factor , HOST_WIDE_INT bytes_per_iter ) { rtx src_reg , dest_reg , final_src , test ; HOST_WIDE_INT leftover ; leftover = length % bytes_per_iter ; length -= leftover ; arm_adjust_block_mem ( src , bytes_per_iter , & src_reg , & src ) ; arm_adjust_block_mem ( dest , bytes_per_iter , & dest_reg , & dest ) ; final_src = expand_simple_binop ( Pmode , PLUS , src_reg , GEN_INT ( length ) , 0 , 0 , OPTAB_WIDEN ) ; rtx_code_label * label = gen_label_rtx ( ) ; emit_label ( label ) ; arm_block_move_unaligned_straight ( dest , src , bytes_per_iter , interleave_factor ) ; emit_move_insn ( src_reg , plus_constant ( Pmode , src_reg , bytes_per_iter ) ) ; emit_move_insn ( dest_reg , plus_constant ( Pmode , dest_reg , bytes_per_iter ) ) ; test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ; if ( leftover ) arm_block_move_unaligned_straight ( dest , src , leftover , interleave_factor ) ; } </s>

From mips_block_move_loop : Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER bytes at a time . LENGTH must be at least BYTES_PER_ITER . Assume that the memory regions do not overlap .


<s> virtual ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) return createR600MachineScheduler ( C ) ; return 0 ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> uint64_t HexagonPLT :: emit ( MemoryRegion & pRegion ) { uint64_t result = 0x0 ; iterator it = begin ( ) ; unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < HexagonPLT0 > ( ( * it ) ) . getValue ( ) , HexagonPLT0 :: EntrySize ) ; result += HexagonPLT0 :: EntrySize ; ++ it ; HexagonPLT1 * plt1 = 0 ; HexagonPLT :: iterator ie = end ( ) ; while ( it != ie ) { plt1 = & ( llvm :: cast < HexagonPLT1 > ( * it ) ) ; memcpy ( buffer + result , plt1 -> getValue ( ) , HexagonPLT1 :: EntrySize ) ; result += HexagonPLT1 :: EntrySize ; ++ it ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .

Hexagon Hexagon 0x0 Hexagon Hexagon Hexagon Hexagon 0 Hexagon Hexagon Hexagon Hexagon


<s> void MOSInstructionSelector :: setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CovInfo , ProfileSummaryInfo * PSI , BlockFrequencyInfo * BFI , AAResults * AA ) { InstructionSelector :: setupMF ( MF , KB , CovInfo , PSI , BFI , AA ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { switch ( MI . getOpcode ( ) ) { case MOS :: G_PTRTOINT : case MOS :: G_INTTOPTR : MI . setDesc ( TII . get ( MOS :: COPY ) ) ; break ; } } } } </s>


<s> static rtx mmix_function_arg ( cumulative_args_t argsp , const function_arg_info & arg ) { return mmix_function_arg_1 ( argsp , arg , false ) ; } </s>

Return an rtx for a function argument to go in a register , and 0 for one that must go on stack .


<s> void F2003fInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; BuildMI ( MBB , MI , DL , get ( F2003f :: KRZmr ) ) . addFrameIndex ( FrameIdx ) . addReg ( 0 ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? "e-p:64:64-i64:64-n32:64-S128" : "e-p:32:32-i64:64-n32:64-S128" , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < WebAssemblyTargetObjectFile > ( ) ) { this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; setRequiresStructuredCFG ( true ) ; } </s>

Create an WebAssembly architecture model .

WebAssembly WebAssembly WebAssembly "e-p:64:64-i64:64-n32:64-S128" "e-p:32:32-i64:64-n32:64-S128" WebAssembly


<s>
bool
LVLGen
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** Begin LVLGen **********\n"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"********** Function: "
<<
F
.
getName
(
)
<<
'\n'
)
;
LLVM_DEBUG
(
F
.
dump
(
)
)
;
bool
Changed
=
false
;
const
VESubtarget
&
Subtarget
=
F
.
getSubtarget
<
VESubtarget
>
(
)
;
TII
=
Subtarget
.
getInstrInfo
(
)
;
TRI
=
Subtarget
.
getRegisterInfo
(
)
;
for
(
MachineBasicBlock
&
MBB
:
F
)
Changed
|=
runOnMachineBasicBlock
(
MBB
)
;
if
(
Changed
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"\n"
)
;
LLVM_DEBUG
(
F
.
dump
(
)
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"********** End LVLGen **********\n"
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static poly_int64 calculate_x_in_sequence ( rtx reg ) { std :: map < unsigned , rtx > regno_to_rtx ; rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { rtx pat = PATTERN ( insn ) ; rtx dest = SET_DEST ( pat ) ; if ( GET_CODE ( pat ) == CLOBBER ) continue ; if ( SUBREG_P ( dest ) ) continue ; gcc_assert ( REG_P ( dest ) ) ; rtx note = find_reg_equal_equiv_note ( insn ) ; unsigned regno = REGNO ( dest ) ; if ( note ) regno_to_rtx [ regno ] = XEXP ( note , 0 ) ; else regno_to_rtx [ regno ] = SET_SRC ( pat ) ; } return eval_value ( reg , regno_to_rtx ) ; } </s>

Calculate the value of x register in the sequence .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"IA64 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const F2003fInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> static rtx m32c_addr_space_convert ( rtx op , tree from_type , tree to_type ) { addr_space_t from_as = TYPE_ADDR_SPACE ( TREE_TYPE ( from_type ) ) ; addr_space_t to_as = TYPE_ADDR_SPACE ( TREE_TYPE ( to_type ) ) ; rtx result ; gcc_assert ( from_as == ADDR_SPACE_GENERIC || from_as == ADDR_SPACE_FAR ) ; gcc_assert ( to_as == ADDR_SPACE_GENERIC || to_as == ADDR_SPACE_FAR ) ; if ( to_as == ADDR_SPACE_GENERIC && from_as == ADDR_SPACE_FAR ) { result = gen_reg_rtx ( HImode ) ; emit_move_insn ( result , simplify_subreg ( HImode , op , SImode , 0 ) ) ; return result ; } else if ( to_as == ADDR_SPACE_FAR && from_as == ADDR_SPACE_GENERIC ) { result = gen_reg_rtx ( SImode ) ; emit_insn ( gen_zero_extendhisi2 ( result , op ) ) ; return result ; } else gcc_unreachable ( ) ; } </s>

Convert from one address space to another .


<s> static bool is_nonpipeline_insn ( rtx_insn * insn ) { enum attr_type type ; if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; type = get_attr_type ( insn ) ; if ( type == TYPE_MUL || type == TYPE_DIV || type == TYPE_SDIV || type == TYPE_DDIV || type == TYPE_SSQRT || type == TYPE_DSQRT || type == TYPE_MFCR || type == TYPE_MFCRF || type == TYPE_MFJMPR ) { return true ; } return false ; } </s>

Return true if the instruction is nonpipelined on the Cell .


<s>
uint32_t
getTypeId
(
const
DIType
*
Ty
)
{
assert
(
Ty
&&
"Invalid null Type"
)
;
assert
(
DIToIdMap
.
find
(
Ty
)
!=
DIToIdMap
.
end
(
)
&&
"DIType not added in the BDIToIdMap"
)
;
return
DIToIdMap
[
Ty
]
;
}
</s>

Get the type id for a particular DIType .

BPF
"Invalid null Type"
"DIType not added in the BDIToIdMap"


<s>
bool
HexagonAsmPrinter
::
PrintAsmMemoryOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
unsigned
AsmVariant
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
return
true
;
const
MachineOperand
&
Base
=
MI
->
getOperand
(
OpNo
)
;
const
MachineOperand
&
Offset
=
MI
->
getOperand
(
OpNo
+
1
)
;
if
(
Base
.
isReg
(
)
)
printOperand
(
MI
,
OpNo
,
O
)
;
else
assert
(
0
&&
"Unimplemented"
)
;
if
(
Offset
.
isImm
(
)
)
{
if
(
Offset
.
getImm
(
)
)
O
<<
" + #"
<<
Offset
.
getImm
(
)
;
}
else
assert
(
0
&&
"Unimplemented"
)
;
return
false
;
}
</s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void ia64_expand_compare ( rtx * expr , rtx * op0 , rtx * op1 ) { enum rtx_code code = GET_CODE ( * expr ) ; rtx cmp ; if ( GET_MODE ( * op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && * op1 == const0_rtx ) ; cmp = * op0 ; } else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = 1 , QCMP_UNORD = 2 , QCMP_EQ = 4 , QCMP_LT = 8 , QCMP_GT = 16 } ; int magic ; enum rtx_code ncode ; rtx ret ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , 0 , LCT_CONST , DImode , 3 , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; rtx_insn * insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ) ; code = NE ; } * expr = gen_rtx_fmt_ee ( code , VOIDmode , cmp , const0_rtx ) ; * op0 = cmp ; * op1 = const0_rtx ; } </s>

Emit comparison instruction if necessary , returning the expression that holds the compare result in the proper mode .


<s> static bool m68k_decompose_index ( rtx x , bool strict_p , struct m68k_address * address ) { int scale ; scale = 1 ; if ( ( TARGET_68020 || TARGET_COLDFIRE ) && GET_CODE ( x ) == MULT && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT && ( INTVAL ( XEXP ( x , 1 ) ) == 2 || INTVAL ( XEXP ( x , 1 ) ) == 4 || ( INTVAL ( XEXP ( x , 1 ) ) == 8 && ( TARGET_COLDFIRE_FPU || ! TARGET_COLDFIRE ) ) ) ) { scale = INTVAL ( XEXP ( x , 1 ) ) ; x = XEXP ( x , 0 ) ; } if ( ! TARGET_COLDFIRE && GET_CODE ( x ) == SIGN_EXTEND && GET_MODE ( XEXP ( x , 0 ) ) == HImode ) x = XEXP ( x , 0 ) ; if ( m68k_legitimate_index_reg_p ( x , strict_p ) ) { address -> scale = scale ; address -> index = x ; return true ; } return false ; } </s>

Return true if X is a legitimate index expression for a ( d8 , An , Xn ) or ( bd , An , Xn ) addressing mode . Fill in the INDEX and SCALE fields of ADDRESS if so . STRICT_P says whether we need strict checking .


<s>
void
i386_pe_asm_output_aligned_decl_common
(
FILE
*
stream
,
tree
decl
,
const
char
*
name
,
HOST_WIDE_INT
size
,
HOST_WIDE_INT
align
)
{
HOST_WIDE_INT
rounded
;
rounded
=
size
size
:
1
;
rounded
+=
(
BIGGEST_ALIGNMENT
/
BITS_PER_UNIT
)
1
;
rounded
=
(
rounded
/
(
BIGGEST_ALIGNMENT
/
BITS_PER_UNIT
)
*
(
BIGGEST_ALIGNMENT
/
BITS_PER_UNIT
)
)
;
i386_pe_maybe_record_exported_symbol
(
decl
,
name
,
1
)
;
fprintf
(
stream
,
"\t.comm\t"
)
;
assemble_name
(
stream
,
name
)
;
if
(
use_pe_aligned_common
)
fprintf
(
stream
,
", "
HOST_WIDE_INT_PRINT_DEC
", %d\n"
,
size
size
:
HOST_WIDE_INT_1
,
exact_log2
(
align
)
exact_log2
(
CHAR_BIT
)
)
;
else
fprintf
(
stream
,
", "
HOST_WIDE_INT_PRINT_DEC
"\t"
ASM_COMMENT_START
" "
HOST_WIDE_INT_PRINT_DEC
"\n"
,
rounded
,
size
)
;
}
</s>

Beware , DECL may be NULL if compile_file ( ) is emitting the LTO marker .


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
DataLayout
&
DL
,
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
switch
(
AS
)
{
case
AMDGPUAS
::
GLOBAL_ADDRESS
:
if
(
Subtarget
->
getGeneration
(
)
>=
SISubtarget
::
VOLCANIC_ISLANDS
)
{
return
isLegalFlatAddressingMode
(
AM
)
;
}
return
isLegalMUBUFAddressingMode
(
AM
)
;
case
AMDGPUAS
::
CONSTANT_ADDRESS
:
if
(
AM
.
BaseOffs
%
4
!=
0
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
DL
.
getTypeStoreSize
(
Ty
)
<
4
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
Subtarget
->
getGeneration
(
)
==
SISubtarget
::
SOUTHERN_ISLANDS
)
{
if
(
!
isUInt
<
8
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
SISubtarget
::
SEA_ISLANDS
)
{
if
(
!
isUInt
<
32
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
SISubtarget
::
VOLCANIC_ISLANDS
)
{
if
(
!
isUInt
<
20
>
(
AM
.
BaseOffs
)
)
return
false
;
}
else
llvm_unreachable
(
"unhandled generation"
)
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
case
AMDGPUAS
::
PRIVATE_ADDRESS
:
return
isLegalMUBUFAddressingMode
(
AM
)
;
case
AMDGPUAS
::
LOCAL_ADDRESS
:
case
AMDGPUAS
::
REGION_ADDRESS
:
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
case
AMDGPUAS
::
FLAT_ADDRESS
:
case
AMDGPUAS
::
UNKNOWN_ADDRESS_SPACE
:
return
isLegalFlatAddressingMode
(
AM
)
;
default
:
llvm_unreachable
(
"unhandled address space"
)
;
}
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool X86ATTAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'c' : printOperand ( MI , OpNo , "mem" , true ) ; return false ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MI -> getOperand ( OpNo ) . isReg ( ) ) return printAsmMRegister ( MI -> getOperand ( OpNo ) , ExtraCode [ 0 ] ) ; printOperand ( MI , OpNo ) ; return false ; case 'P' : printOperand ( MI , OpNo , "mem" , true ) ; return false ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void VEPassConfig :: addPreEmitPass ( ) { addPass ( createLVLGenPass ( ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> uint64_t PPCTargetLowering :: getByValTypeAlignment ( Type * Ty , const DataLayout & DL ) const { Align Alignment = Subtarget . isPPC64 ( ) ? Align ( 8 ) : Align ( 4 ) ; if ( Subtarget . hasAltivec ( ) ) getMaxByValAlign ( Ty , Alignment , Align ( 16 ) ) ; return Alignment . value ( ) ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> static void mips_macc_chains_record ( rtx_insn * insn ) { if ( get_attr_may_clobber_hilo ( insn ) ) mips_macc_chains_last_hilo = insn ; } </s>

A TUNE_MACC_CHAINS helper function . Record that instruction INSN has been scheduled , updating mips_macc_chains_last_hilo appropriately .


"Not expecting modifiers with immediates"

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .


<s> void Z80InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static bool nios2_valid_addr_offset_p ( rtx offset ) { return ( CONST_INT_P ( offset ) && ( ( TARGET_ARCH_R2 && ( TARGET_BYPASS_CACHE || TARGET_BYPASS_CACHE_VOLATILE ) ) ? SMALL_INT12 ( INTVAL ( offset ) ) : SMALL_INT ( INTVAL ( offset ) ) ) ) ; } </s>

Return true if OFFSET is permitted in a load/store address expression . Normally any 16-bit value is permitted , but on R2 if we may be emitting the IO forms of these instructions we must restrict the offset to fit in a 12-bit field instead .


<s> void XCoreInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: LDWFI ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> machine_mode mips_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( mode == VOIDmode ) return choose_hard_reg_mode ( regno , nregs , NULL ) ; else return mode ; } </s>


<s> bool AArch64RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; DomBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; OptBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( & MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
GCNUpwardRPTracker
::
recede
(
const
MachineInstr
&
MI
)
{
assert
(
MRI
&&
"call reset first"
)
;
LastTrackedMI
=
&
MI
;
if
(
MI
.
isDebugInstr
(
)
)
return
;
auto
const
RegUses
=
collectVirtualRegUses
(
MI
,
LIS
,
*
MRI
)
;
auto
AtMIPressure
=
CurPressure
;
for
(
const
auto
&
U
:
RegUses
)
{
auto
LiveMask
=
LiveRegs
[
U
.
RegUnit
]
;
AtMIPressure
.
inc
(
U
.
RegUnit
,
LiveMask
,
LiveMask
|
U
.
LaneMask
,
*
MRI
)
;
}
MaxPressure
=
max
(
AtMIPressure
,
MaxPressure
)
;
for
(
const
auto
&
MO
:
MI
.
operands
(
)
)
{
if
(
!
MO
.
isReg
(
)
||
!
MO
.
isDef
(
)
||
!
MO
.
getReg
(
)
.
isVirtual
(
)
||
MO
.
isDead
(
)
)
continue
;
auto
Reg
=
MO
.
getReg
(
)
;
auto
I
=
LiveRegs
.
find
(
Reg
)
;
if
(
I
==
LiveRegs
.
end
(
)
)
continue
;
auto
&
LiveMask
=
I
->
second
;
auto
PrevMask
=
LiveMask
;
LiveMask
&=
~
getDefRegMask
(
MO
,
*
MRI
)
;
CurPressure
.
inc
(
Reg
,
PrevMask
,
LiveMask
,
*
MRI
)
;
if
(
LiveMask
.
(
)
)
LiveRegs
.
erase
(
I
)
;
}
for
(
const
auto
&
U
:
RegUses
)
{
auto
&
LiveMask
=
LiveRegs
[
U
.
RegUnit
]
;
auto
PrevMask
=
LiveMask
;
LiveMask
|=
U
.
LaneMask
;
CurPressure
.
inc
(
U
.
RegUnit
,
PrevMask
,
LiveMask
,
*
MRI
)
;
}
assert
(
CurPressure
==
getRegPressure
(
*
MRI
,
LiveRegs
)
)
;
}
</s>

Recede across the previous instruction .


<s> bool SystemZElimCompare :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( F . getFunction ( ) ) ) return false ; TII = static_cast < const SystemZInstrInfo * > ( F . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>


<s> unsigned SparcAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & GOp , unsigned Kind ) { SparcOperand & Op = ( SparcOperand & ) GOp ; if ( Op . isFloatOrDoubleReg ( ) ) { switch ( Kind ) { default : break ; case MCK_DFPRegs : if ( ! Op . isFloatReg ( ) || SparcOperand :: MorphToDoubleReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_QFPRegs : if ( SparcOperand :: MorphToQuadReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; } } if ( Op . isIntReg ( ) && Kind == MCK_IntPair ) { if ( SparcOperand :: MorphToIntPairReg ( Op ) ) return MCTargetAsmParser :: Match_Success ; } return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .

Sparc Sparc Sparc Sparc SparcOperand::MorphToDoubleReg SparcOperand::MorphToQuadReg SparcOperand::MorphToIntPairReg


<s> bool TeakTargetLowering :: isTruncateFree ( EVT SrcVT , EVT DstVT ) const { if ( SrcVT . isVector ( ) || DstVT . isVector ( ) || ! SrcVT . isInteger ( ) || ! DstVT . isInteger ( ) ) return false ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; unsigned DestBits = DstVT . getSizeInBits ( ) ; return ( SrcBits == 40 && DestBits == 16 ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> std :: pair < unsigned , unsigned > AMDGPUSubtarget :: getWavesPerEU ( const Function & F ) const { std :: pair < unsigned , unsigned > Default ( 1 , getMaxWavesPerEU ( ) ) ; std :: pair < unsigned , unsigned > FlatWorkGroupSizes = getFlatWorkGroupSizes ( F ) ; unsigned MinImpliedByFlatWorkGroupSize = getMaxWavesPerEU ( FlatWorkGroupSizes . second ) ; bool RequestedFlatWorkGroupSize = false ; if ( F . hasFnAttribute ( "amdgpu-flat-work-group-size" ) ) { Default . first = MinImpliedByFlatWorkGroupSize ; RequestedFlatWorkGroupSize = true ; } std :: pair < unsigned , unsigned > Requested = AMDGPU :: getIntegerPairAttribute ( F , "amdgpu-waves-per-eu" , Default , true ) ; if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . first > getMaxWavesPerEU ( ) ) return Default ; if ( Requested . second > getMaxWavesPerEU ( ) ) return Default ; if ( RequestedFlatWorkGroupSize && Requested . first < MinImpliedByFlatWorkGroupSize ) return Default ; return Requested ; } </s>

Overload which uses the specified values for the flat work group sizes , rather than querying the function itself .

AMDGPU AMDGPU 1 "amdgpu-flat-work-group-size" AMDGPU::getIntegerPairAttribute "amdgpu-waves-per-eu"


<s> const HexagonRegisterInfo * getRegisterInfo ( ) const override { return getSubtargetImpl ( ) -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
bool
PPCCTRLoopsVerify
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
for
(
MachineFunction
::
iterator
I
=
MF
.
begin
(
)
,
IE
=
MF
.
end
(
)
;
I
!=
IE
;
++
I
)
{
MachineBasicBlock
*
MBB
=
&
*
I
;
if
(
!
MDT
->
isReachableFromEntry
(
MBB
)
)
continue
;
for
(
MachineBasicBlock
::
iterator
MII
=
MBB
->
getFirstTerminator
(
)
,
MIIE
=
MBB
->
end
(
)
;
MII
!=
MIIE
;
++
MII
)
{
unsigned
Opc
=
MII
->
getOpcode
(
)
;
if
(
Opc
==
PPC
::
BDNZ8
||
Opc
==
PPC
::
BDNZ
||
Opc
==
PPC
::
BDZ8
||
Opc
==
PPC
::
BDZ
)
if
(
!
verifyCTRBranch
(
MBB
,
MII
)
)
llvm_unreachable
(
"Invalid PPC CTR loop!"
)
;
}
}
return
false
;
}
</s>

PowerPC
PPC
PPC::BDNZ8
PPC::BDNZ
PPC::BDZ8
PPC::BDZ
"Invalid PPC CTR loop!"


<s> bool direct_move_p ( rtx op0 , rtx op1 ) { if ( ! REG_P ( op0 ) || ! REG_P ( op1 ) ) return false ; if ( ! TARGET_DIRECT_MOVE ) return false ; int regno0 = REGNO ( op0 ) ; int regno1 = REGNO ( op1 ) ; if ( ! HARD_REGISTER_NUM_P ( regno0 ) || ! HARD_REGISTER_NUM_P ( regno1 ) ) return false ; if ( INT_REGNO_P ( regno0 ) && VSX_REGNO_P ( regno1 ) ) return true ; if ( VSX_REGNO_P ( regno0 ) && INT_REGNO_P ( regno1 ) ) return true ; return false ; } </s>

Return true if this is a move direct operation between GPR registers and floating point/VSX registers .


<s> bool PPCLinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getDataLayout ( ) ; bool isPPC64 = TD -> getPointerSizeInBits ( ) == 64 ; if ( isPPC64 && ! TOC . empty ( ) ) { const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( ".toc" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; OutStreamer . EmitTCEntry ( * S ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool hasModifiers ( ) const { assert ( isRegKind ( ) ) ; return Reg . Modifiers != - 1 ; } </s>

Return true if this instruction has any modifiers .


<s> unsigned MSP430RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ? MSP430 :: FPW : MSP430 :: SPW ; } </s>


<s>
bool
CFGStructurizer
<
PassT
>
::
prepare
(
FuncT
&
func
,
PassT
&
pass
,
const
AMDGPURegisterInfo
*
tri
)
{
passRep
=
&
pass
;
funcRep
=
&
func
;
TRI
=
tri
;
bool
changed
=
false
;
if
(
DEBUGME
)
{
errs
(
)
<<
"AMDGPUCFGStructurizer::prepare\n"
;
}
loopInfo
=
CFGTraits
::
getLoopInfo
(
pass
)
;
if
(
DEBUGME
)
{
errs
(
)
<<
"LoopInfo:\n"
;
PrintLoopinfo
(
*
loopInfo
,
errs
(
)
)
;
}
orderBlocks
(
)
;
if
(
DEBUGME
)
{
errs
(
)
<<
"Ordered blocks:\n"
;
printOrderedBlocks
(
errs
(
)
)
;
}
SmallVector
<
BlockT
*
,
DEFAULT_VEC_SLOTS
>
retBlks
;
for
(
typename
LoopInfoT
::
iterator
iter
=
loopInfo
->
begin
(
)
,
iterEnd
=
loopInfo
->
end
(
)
;
iter
!=
iterEnd
;
++
iter
)
{
LoopT
*
loopRep
=
(
*
iter
)
;
BlockTSmallerVector
exitingBlks
;
loopRep
->
getExitingBlocks
(
exitingBlks
)
;
if
(
exitingBlks
.
size
(
)
==
0
)
{
BlockT
*
dummyExitBlk
=
normalizeInfiniteLoopExit
(
loopRep
)
;
if
(
dummyExitBlk
!=
)
retBlks
.
push_back
(
dummyExitBlk
)
;
}
}
for
(
typename
SmallVectorImpl
<
BlockT
*
>
::
const_iterator
iterBlk
=
orderedBlks
.
begin
(
)
,
iterEndBlk
=
orderedBlks
.
end
(
)
;
iterBlk
!=
iterEndBlk
;
++
iterBlk
)
{
BlockT
*
curBlk
=
*
iterBlk
;
removeUnconditionalBranch
(
curBlk
)
;
removeRedundantConditionalBranch
(
curBlk
)
;
if
(
CFGTraits
::
isReturnBlock
(
curBlk
)
)
{
retBlks
.
push_back
(
curBlk
)
;
}
assert
(
curBlk
->
succ_size
(
)
<=
2
)
;
}
if
(
retBlks
.
size
(
)
>=
2
)
{
addDummyExitBlock
(
retBlks
)
;
changed
=
true
;
}
return
changed
;
}
</s>

prepare - Reset state and prepare for a new spill placement computation .


<s> bool ARMRegisterInfo :: hasReservedCallFrame ( MachineFunction & MF ) const { const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> isThumbFunction ( ) ) { if ( CFSize >= ( ( 1 << 8 ) - 1 ) * 4 / 2 ) return false ; } else { if ( CFSize >= ( ( 1 << 12 ) - 1 ) / 2 ) return false ; } return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static int sh_pr_n_sets ( void ) { return DF_REG_DEF_COUNT ( TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ) ; } </s>

For use by ALLOCATE_INITIAL_VALUE . Note that sh.md contains some 'special function ' patterns ( type sfunc ) that clobber pr , but that do not look like function calls to leaf_function_p . Hence we must do this extra check .


<s> bool SIFixControlFlowLiveIntervals :: runOnMachineFunction ( MachineFunction & MF ) { LiveIntervals * LIS = & getAnalysis < LiveIntervals > ( ) ; for ( const MachineBasicBlock & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { switch ( MI . getOpcode ( ) ) { case AMDGPU :: SI_IF : case AMDGPU :: SI_ELSE : case AMDGPU :: SI_BREAK : case AMDGPU :: SI_IF_BREAK : case AMDGPU :: SI_ELSE_BREAK : case AMDGPU :: SI_END_CF : { unsigned Reg = MI . getOperand ( 0 ) . getReg ( ) ; LIS -> getInterval ( Reg ) . markNotSpillable ( ) ; break ; } default : break ; } } } return false ; } </s>


<s>
void
X86InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIdx
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
->
getObjectSize
(
FrameIdx
)
>=
RC
->
getSize
(
)
&&
"Stack slot too small for store"
)
;
unsigned
Alignment
=
RC
->
getSize
(
)
==
32
32
:
16
;
bool
isAligned
=
(
TM
.
getFrameLowering
(
)
->
getStackAlignment
(
)
>=
Alignment
)
||
RI
.
canRealignStack
(
MF
)
;
unsigned
Opc
=
getStoreRegOpcode
(
SrcReg
,
RC
,
isAligned
,
TM
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
,
FrameIdx
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon generate mux instructions"
;
}
</s>

getPassName - Return a nice clean name for a pass .

Hexagon
"Hexagon generate mux instructions"


<s> virtual unsigned int execute ( function * ) { return sparc_do_work_around_errata ( ) ; } </s>


<s> bool SystemZInstrInfo :: isStackSlotCopy ( const MachineInstr & MI , int & DestFrameIndex , int & SrcFrameIndex ) const { const MachineFrameInfo & MFI = MI . getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; if ( MI . getOpcode ( ) != SystemZ :: MVC || ! MI . getOperand ( 0 ) . isFI ( ) || MI . getOperand ( 1 ) . getImm ( ) != 0 || ! MI . getOperand ( 3 ) . isFI ( ) || MI . getOperand ( 4 ) . getImm ( ) != 0 ) return false ; int64_t Length = MI . getOperand ( 2 ) . getImm ( ) ; unsigned FI1 = MI . getOperand ( 0 ) . getIndex ( ) ; unsigned FI2 = MI . getOperand ( 3 ) . getIndex ( ) ; if ( MFI . getObjectSize ( FI1 ) != Length || MFI . getObjectSize ( FI2 ) != Length ) return false ; DestFrameIndex = FI1 ; SrcFrameIndex = FI2 ; return true ; } </s>

Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> static int ix86_register_priority ( int hard_regno ) { if ( hard_regno == R12_REG || hard_regno == R13_REG ) return 0 ; if ( hard_regno == BP_REG ) return 1 ; if ( REX_INT_REGNO_P ( hard_regno ) ) return 2 ; if ( REX_SSE_REGNO_P ( hard_regno ) ) return 2 ; if ( EXT_REX_SSE_REGNO_P ( hard_regno ) ) return 1 ; if ( hard_regno == AX_REG ) return 4 ; return 3 ; } </s>

Return a register priority for hard reg REGNO .


<s> static void mips_emit_unary ( enum rtx_code code , rtx target , rtx op0 ) { emit_insn ( gen_rtx_SET ( VOIDmode , target , gen_rtx_fmt_e ( code , GET_MODE ( op0 ) , op0 ) ) ) ; } </s>

Emit an instruction of the form ( set TARGET ( CODE OP0 ) ) .


<s> bool TPCSymbolizer :: tryAddingSymbolicOperand ( MCInst & Inst , raw_ostream & , int64_t Value , uint64_t Address , bool IsBranch , uint64_t Offset , uint64_t ) { uint64_t SearchValue = Address + Value ; using SymbolInfoTy = std :: tuple < uint64_t , StringRef , uint8_t > ; using SectionSymbolsTy = std :: vector < SymbolInfoTy > ; if ( ! IsBranch ) { return false ; } auto * Symbols = static_cast < SectionSymbolsTy * > ( DisInfo ) ; if ( ! Symbols ) { return false ; } auto Result = std :: find_if ( Symbols -> begin ( ) , Symbols -> end ( ) , [ SearchValue ] ( const SymbolInfoTy & Val ) { return std :: get < 0 > ( Val ) == static_cast < uint64_t > ( SearchValue ) && std :: get < 2 > ( Val ) == ELF :: STT_NOTYPE ; } ) ; if ( Result != Symbols -> end ( ) ) { auto * Sym = Ctx . getOrCreateSymbol ( std :: get < 1 > ( * Result ) ) ; const auto * Add = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Inst . addOperand ( MCOperand :: createExpr ( Add ) ) ; return true ; } return false ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> bool HexagonInstrInfo :: shouldSink ( const MachineInstr & MI ) const { if ( isFloat ( MI ) && MI . hasRegisterImplicitUseOperand ( Hexagon :: USR ) ) return false ; return true ; } </s>

Return true if the instruction should be sunk by MachineSink .


<s> bool M68kAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { if ( getRelaxedOpcodeBranch ( Inst ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - 1 ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ; return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
unsigned
getStackAddress
(
uint64_t
Size
,
int64_t
Offset
,
MachinePointerInfo
&
MPO
)
override
{
assert
(
Size
==
4
&&
"Unsupported size"
)
;
auto
&
MFI
=
MIRBuilder
.
getMF
(
)
.
getFrameInfo
(
)
;
int
FI
=
MFI
.
CreateFixedObject
(
Size
,
Offset
,
true
)
;
MPO
=
MachinePointerInfo
::
getFixedStack
(
MIRBuilder
.
getMF
(
)
,
FI
)
;
unsigned
AddrReg
=
MRI
.
createGenericVirtualRegister
(
LLT
::
pointer
(
MPO
.
getAddrSpace
(
)
,
32
)
)
;
MIRBuilder
.
buildFrameIndex
(
AddrReg
,
FI
)
;
return
AddrReg
;
}
</s>

Materialize a VReg containing the address of the specified stack-based object .


<s> SDValue getNode ( unsigned OC , EVT ResVT , ArrayRef < SDValue > OpV , Optional < SDNodeFlags > Flags = None ) const { auto N = DAG . getNode ( OC , DL , ResVT , OpV ) ; if ( Flags ) N -> setFlags ( * Flags ) ; return N ; } </s>


<s>
bool
TeakInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOpc
,
int64_t
BrOffset
)
const
{
switch
(
BranchOpc
)
{
default
:
llvm_unreachable
(
"unexpected opcode!"
)
;
case
Teak
::
BR_imm18
:
case
Teak
::
CALL_imm18
:
return
true
;
case
Teak
::
BRR_rel7
:
case
Teak
::
BRRCond_rel7
:
case
Teak
::
CALLR_rel7
:
return
BrOffset
>=
63
&&
BrOffset
<=
64
;
}
}
</s>

Determine if the branch target is in range .


<s> const char * msp430_check_path_for_devices ( int argc , const char * * argv ) { const char dirsep [ 2 ] = { DIR_SEPARATOR , 0 } ; FILE * devices_file = NULL ; char * local_devices_csv_loc = NULL ; int i ; if ( msp430_devices_csv_loc || derived_devices_csv_loc ) return NULL ; for ( i = 0 ; i < argc ; i ++ ) { char * inc_path = xstrdup ( argv [ i ] ) ; canonicalize_path_dirsep ( & inc_path ) ; if ( ! IS_DIR_SEPARATOR ( inc_path [ strlen ( inc_path ) - 1 ] ) ) inc_path = concat ( inc_path , dirsep , NULL ) ; local_devices_csv_loc = concat ( inc_path , "devices.csv" , NULL ) ; devices_file = fopen ( local_devices_csv_loc , "r" ) ; if ( devices_file != NULL ) { fclose ( devices_file ) ; derived_devices_csv_loc = local_devices_csv_loc ; return concat ( "-mdevices-csv-loc=" , local_devices_csv_loc , NULL ) ; } } return NULL ; } </s>

Spec function which searches the paths passed to the -I and -L options for the `` devices.csv '' file . If it is found then the -mdevices-csv-loc option is placed on the command line so the compiler knows the location of the file .


<s> const RegisterBankInfo :: InstructionMapping & MipsRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const RegisterBankInfo :: InstructionMapping & Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_STORE : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : OperandsMapping = & Mips :: ValueMappings [ Mips :: GPRIdx ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & Mips :: ValueMappings [ Mips :: GPRIdx ] , nullptr , & Mips :: ValueMappings [ Mips :: GPRIdx ] , & Mips :: ValueMappings [ Mips :: GPRIdx ] } ) ; break ; default : return getInvalidInstructionMapping ( ) ; } return getInstructionMapping ( DefaultMappingID , 1 , OperandsMapping , NumOperands ) ; } </s>

Get the mapping of the different operands of MI on the register bank .

Mips Mips Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx Mips::ValueMappings Mips::GPRIdx 1


<s> static void nvptx_reorg ( void ) { compute_bb_for_insn ( ) ; thread_prologue_and_epilogue_insns ( ) ; bb_insn_map_t bb_insn_map ; nvptx_split_blocks ( & bb_insn_map ) ; df_clear_flags ( DF_LR_RUN_DCE ) ; df_set_flags ( DF_NO_INSN_RESCAN | DF_NO_HARD_REGS ) ; df_live_add_problem ( ) ; df_live_set_all_dirty ( ) ; if ( nvptx_init_regs == 3 ) df_mir_add_problem ( ) ; df_analyze ( ) ; regstat_init_n_sets_and_refs ( ) ; if ( dump_file ) df_dump ( dump_file ) ; int max_regs = max_reg_num ( ) ; for ( int i = LAST_VIRTUAL_REGISTER + 1 ; i < max_regs ; i ++ ) if ( REG_N_SETS ( i ) == 0 && REG_N_REFS ( i ) == 0 ) regno_reg_rtx [ i ] = const0_rtx ; workaround_uninit ( ) ; tree attr = oacc_get_fn_attrib ( current_function_decl ) ; if ( attr ) { offload_attrs oa ; populate_offload_attrs ( & oa ) ; gcc_assert ( ! ( oa . mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( oa . mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ; parallel * pars = nvptx_discover_pars ( & bb_insn_map ) ; nvptx_process_pars ( pars ) ; nvptx_neuter_pars ( pars , oa . mask , 0 ) ; delete pars ; } nvptx_reorg_subreg ( ) ; if ( TARGET_UNIFORM_SIMT ) nvptx_reorg_uniform_simt ( ) ; prevent_branch_around_nothing ( ) ; workaround_barsyncs ( ) ; regstat_free_n_sets_and_refs ( ) ; df_finish_pass ( true ) ; } </s>

Clean up subreg operands . In ptx assembly , everything is typed , and the presence of subregs would break the rules for most instructions . Replace them with a suitable new register of the right size , plus conversion copyin/copyout instructions .


<s> void aarch64_asm_file_end ( ) { aarch64_sls_emit_shared_blr_thunks ( asm_out_file ) ; TARGET_ASM_FILE_END ( ) ; } </s>


"the destination register can't equal the base register in an "

"instruction that modifies the base register."

ParseInstruction - Parse one assembly instruction .


"We have a different number of location and args?!"

Use Handler to insert code to handle the argument/return values represented by Args .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_MostRegs_64_SaveList ; break ; default : break ; } bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; bool IsNaCl = TM . getSubtarget < X86Subtarget > ( ) . isTargetNaCl ( ) ; if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( IsNaCl ) { if ( CallsEHReturn ) return CSR_NaCl64EHRet_SaveList ; return CSR_NaCl64_SaveList ; } if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( CallsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < DataLayout > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void mips_conditional_register_usage ( void ) { if ( ISA_HAS_DSP ) { global_regs [ CCDSP_PO_REGNUM ] = 1 ; global_regs [ CCDSP_SC_REGNUM ] = 1 ; } else AND_COMPL_HARD_REG_SET ( accessible_reg_set , reg_class_contents [ ( int ) DSP_ACC_REGS ] ) ; if ( ! ISA_HAS_HILO ) AND_COMPL_HARD_REG_SET ( accessible_reg_set , reg_class_contents [ ( int ) MD_REGS ] ) ; if ( ! TARGET_HARD_FLOAT ) { AND_COMPL_HARD_REG_SET ( accessible_reg_set , reg_class_contents [ ( int ) FP_REGS ] ) ; AND_COMPL_HARD_REG_SET ( accessible_reg_set , reg_class_contents [ ( int ) ST_REGS ] ) ; } else if ( ! ISA_HAS_8CC ) { AND_COMPL_HARD_REG_SET ( accessible_reg_set , reg_class_contents [ ( int ) ST_REGS ] ) ; if ( ! ISA_HAS_CCF ) SET_HARD_REG_BIT ( accessible_reg_set , FPSW_REGNUM ) ; fixed_regs [ FPSW_REGNUM ] = call_used_regs [ FPSW_REGNUM ] = 1 ; } if ( TARGET_MIPS16 ) { fixed_regs [ 18 ] = call_used_regs [ 18 ] = 1 ; fixed_regs [ 19 ] = call_used_regs [ 19 ] = 1 ; fixed_regs [ 20 ] = call_used_regs [ 20 ] = 1 ; fixed_regs [ 21 ] = call_used_regs [ 21 ] = 1 ; fixed_regs [ 22 ] = call_used_regs [ 22 ] = 1 ; fixed_regs [ 23 ] = call_used_regs [ 23 ] = 1 ; fixed_regs [ 26 ] = call_used_regs [ 26 ] = 1 ; fixed_regs [ 27 ] = call_used_regs [ 27 ] = 1 ; fixed_regs [ 30 ] = call_used_regs [ 30 ] = 1 ; if ( optimize_size ) { fixed_regs [ 8 ] = call_used_regs [ 8 ] = 1 ; fixed_regs [ 9 ] = call_used_regs [ 9 ] = 1 ; fixed_regs [ 10 ] = call_used_regs [ 10 ] = 1 ; fixed_regs [ 11 ] = call_used_regs [ 11 ] = 1 ; fixed_regs [ 12 ] = call_used_regs [ 12 ] = 1 ; fixed_regs [ 13 ] = call_used_regs [ 13 ] = 1 ; fixed_regs [ 14 ] = call_used_regs [ 14 ] = 1 ; fixed_regs [ 15 ] = call_used_regs [ 15 ] = 1 ; } AND_COMPL_HARD_REG_SET ( operand_reg_set , reg_class_contents [ ( int ) MD_REGS ] ) ; } if ( mips_abi == ABI_64 ) { int regno ; for ( regno = FP_REG_FIRST + 20 ; regno < FP_REG_FIRST + 24 ; regno ++ ) call_really_used_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( mips_abi == ABI_N32 || ( mips_abi == ABI_32 && TARGET_FLOAT64 ) ) { int regno ; for ( regno = FP_REG_FIRST + 21 ; regno <= FP_REG_FIRST + 31 ; regno += 2 ) call_really_used_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( TARGET_LITTLE_ENDIAN ) { unsigned int regno ; mips_swap_registers ( MD_REG_FIRST ) ; for ( regno = DSP_ACC_REG_FIRST ; regno <= DSP_ACC_REG_LAST ; regno += 2 ) mips_swap_registers ( regno ) ; } } </s>


<s>
const
MCPhysReg
*
AArch64RegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
assert
(
MF
&&
"Invalid MachineFunction pointer."
)
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetWindows
(
)
)
return
CSR_Win_AArch64_AAPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
GHC
)
return
CSR_AArch64_NoRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AnyReg
)
return
CSR_AArch64_AllRegs_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
AArch64_VectorCall
)
return
CSR_AArch64_AAVPCS_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
CXX_FAST_TLS
)
return
MF
->
getInfo
<
AArch64FunctionInfo
>
(
)
->
isSplitCSR
(
)
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList
:
CSR_AArch64_CXX_TLS_Darwin_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
getTargetLowering
(
)
->
supportSwiftError
(
)
&&
MF
->
getFunction
(
)
.
getAttributes
(
)
.
hasAttrSomewhere
(
Attribute
::
SwiftError
)
)
return
CSR_AArch64_AAPCS_SwiftError_SaveList
;
if
(
MF
->
getFunction
(
)
.
getCallingConv
(
)
==
CallingConv
::
PreserveMost
)
return
CSR_AArch64_RT_MostRegs_SaveList
;
if
(
MF
->
getSubtarget
<
AArch64Subtarget
>
(
)
.
isTargetDarwin
(
)
)
return
CSR_Darwin_AArch64_AAPCS_SaveList
;
return
CSR_AArch64_AAPCS_SaveList
;
}
</s>


<s> static void ix86_init_tm_builtins ( void ) { enum ix86_builtin_func_type ftype ; const struct builtin_description * d ; size_t i ; tree decl ; tree attrs_load , attrs_type_load , attrs_store , attrs_type_store ; tree attrs_log , attrs_type_log ; if ( ! flag_tm ) return ; if ( ! builtin_decl_explicit_p ( BUILT_IN_TM_LOAD_1 ) ) return ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOAD_1 ) ; attrs_load = DECL_ATTRIBUTES ( decl ) ; attrs_type_load = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_STORE_1 ) ; attrs_store = DECL_ATTRIBUTES ( decl ) ; attrs_type_store = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; decl = builtin_decl_explicit ( BUILT_IN_TM_LOG ) ; attrs_log = DECL_ATTRIBUTES ( decl ) ; attrs_type_log = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; for ( i = 0 , d = bdesc_tm ; i < ARRAY_SIZE ( bdesc_tm ) ; i ++ , d ++ ) { if ( ( d -> mask & ix86_isa_flags ) != 0 || ( lang_hooks . builtin_function == lang_hooks . builtin_function_ext_scope ) ) { tree type , attrs , attrs_type ; enum built_in_function code = ( enum built_in_function ) d -> code ; ftype = ( enum ix86_builtin_func_type ) d -> flag ; type = ix86_get_builtin_func_type ( ftype ) ; if ( BUILTIN_TM_LOAD_P ( code ) ) { attrs = attrs_load ; attrs_type = attrs_type_load ; } else if ( BUILTIN_TM_STORE_P ( code ) ) { attrs = attrs_store ; attrs_type = attrs_type_store ; } else { attrs = attrs_log ; attrs_type = attrs_type_log ; } decl = add_builtin_function ( d -> name , type , code , BUILT_IN_NORMAL , d -> name + strlen ( "__builtin_" ) , attrs ) ; decl_attributes ( & TREE_TYPE ( decl ) , attrs_type , ATTR_FLAG_BUILT_IN ) ; set_builtin_decl ( code , decl , false ) ; } } } </s>

Initialize the transactional memory vector load/store builtins .