"TRUE - Frame size is too large for D-Form.\n"

"TRUE - Not fixed frame object that requires "

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> void CJGFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Instr doesn't have FrameIndex operand!"

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> int NVPTXRegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return 0 ; } </s>

Map a target register to an equivalent dwarf register number .


<s>
char
*
rx_gen_move_template
(
rtx
*
operands
,
bool
is_movu
)
{
static
char
out_template
[
64
]
;
const
char
*
extension
=
TARGET_AS100_SYNTAX
".L"
:
""
;
const
char
*
src_template
;
const
char
*
dst_template
;
rtx
dest
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
switch
(
CONST_INT_P
(
src
)
GET_MODE
(
dest
)
:
GET_MODE
(
src
)
)
{
case
QImode
:
if
(
!
REG_P
(
dest
)
||
!
CONST_INT_P
(
src
)
)
extension
=
".B"
;
break
;
case
HImode
:
if
(
!
REG_P
(
dest
)
||
!
CONST_INT_P
(
src
)
)
extension
=
".W"
;
break
;
case
DFmode
:
case
DImode
:
case
SFmode
:
case
SImode
:
extension
=
".L"
;
break
;
case
VOIDmode
:
break
;
default
:
debug_rtx
(
src
)
;
gcc_unreachable
(
)
;
}
if
(
MEM_P
(
src
)
&&
rx_pid_data_operand
(
XEXP
(
src
,
0
)
)
==
PID_UNENCODED
)
{
gcc_assert
(
GET_MODE
(
src
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
src
)
!=
DFmode
)
;
src_template
=
"(%A1 - __pid_base)[%P1]"
;
}
else
if
(
MEM_P
(
src
)
&&
rx_small_data_operand
(
XEXP
(
src
,
0
)
)
)
{
gcc_assert
(
GET_MODE
(
src
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
src
)
!=
DFmode
)
;
src_template
=
"%%gp(%A1)[%G1]"
;
}
else
src_template
=
"%1"
;
if
(
MEM_P
(
dest
)
&&
rx_small_data_operand
(
XEXP
(
dest
,
0
)
)
)
{
gcc_assert
(
GET_MODE
(
dest
)
!=
DImode
)
;
gcc_assert
(
GET_MODE
(
dest
)
!=
DFmode
)
;
dst_template
=
"%%gp(%A0)[%G0]"
;
}
else
dst_template
=
"%0"
;
if
(
GET_MODE
(
dest
)
==
DImode
||
GET_MODE
(
dest
)
==
DFmode
)
{
gcc_assert
(
!
is_movu
)
;
if
(
REG_P
(
src
)
&&
REG_P
(
dest
)
&&
(
REGNO
(
dest
)
==
REGNO
(
src
)
+
1
)
)
sprintf
(
out_template
,
"mov.L\t%%H1, %%H0 ! mov.L\t%%1, %%0"
)
;
else
sprintf
(
out_template
,
"mov.L\t%%1, %%0 ! mov.L\t%%H1, %%H0"
)
;
}
else
sprintf
(
out_template
,
"%s%s\t%s, %s"
,
is_movu
"movu"
:
"mov"
,
extension
,
src_template
,
dst_template
)
;
return
out_template
;
}
</s>

Returns an assembler template for a move instruction .


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


<s> static bool aarch64_print_vector_float_operand ( FILE * f , rtx x , bool negate ) { rtx elt ; if ( ! const_vec_duplicate_p ( x , & elt ) ) return false ; REAL_VALUE_TYPE r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst0 ) ) asm_fprintf ( f , "0.0" ) ; else if ( real_equal ( & r , & dconst1 ) ) asm_fprintf ( f , "1.0" ) ; else if ( real_equal ( & r , & dconsthalf ) ) asm_fprintf ( f , "0.5" ) ; else return false ; return true ; } </s>

Print floating-point vector immediate operand X to F , negating it first if NEGATE is true . Return true on success , false if it is n't a constant we can handle .


<s> const DLXMCExpr * DLXMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) DLXMCExpr ( Kind , Expr ) ; } </s>


"insertBranch must not be told to insert a fallthrough"

"MSP430 branch conditions have one component!"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> void J2FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto & MFI = MF . getFrameInfo ( ) ; auto StackSize = MFI . getStackSize ( ) - MFI . getCalleeSavedInfo ( ) . size ( ) * 4 ; auto & TTI = * static_cast < const J2Subtarget & > ( MF . getSubtarget ( ) ) . getInstrInfo ( ) ; if ( StackSize == 0 ) return ; auto it = MBB . getFirstTerminator ( ) ; auto DL = it == MBB . end ( ) ? DebugLoc { } : it -> getDebugLoc ( ) ; it = std :: prev ( it , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; if ( hasFP ( MF ) ) BuildMI ( MBB , it , DL , TTI . get ( J2 :: MOV32rr ) , J2 :: R15 ) . addReg ( J2 :: R14 ) ; } </s>


<s>
bool
MipsOs16
::
runOnModule
(
Module
&
M
)
{
bool
usingMask
=
Mips32FunctionMask
.
length
(
)
>
0
;
DEBUG
(
dbgs
(
)
<<
"Run on Module MipsOs16 \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
if
(
usingMask
)
DEBUG
(
dbgs
(
)
<<
"using mask \n"
<<
Mips32FunctionMask
<<
"\n"
)
;
unsigned
int
functionIndex
=
0
;
bool
modified
=
false
;
for
(
Module
::
iterator
F
=
M
.
begin
(
)
,
E
=
M
.
end
(
)
;
F
!=
E
;
++
F
)
{
if
(
F
->
isDeclaration
(
)
)
continue
;
DEBUG
(
dbgs
(
)
<<
"Working on "
<<
F
->
getName
(
)
<<
"\n"
)
;
if
(
usingMask
)
{
if
(
functionIndex
==
Mips32FunctionMask
.
length
(
)
)
functionIndex
=
0
;
if
(
Mips32FunctionMask
[
functionIndex
]
==
'1'
)
{
DEBUG
(
dbgs
(
)
<<
"mask forced mips32: "
<<
F
->
getName
(
)
<<
"\n"
)
;
F
->
addFnAttr
(
"nomips16"
)
;
}
functionIndex
++
;
}
else
{
if
(
needsFP
(
*
F
)
)
{
DEBUG
(
dbgs
(
)
<<
"os16 forced mips32: "
<<
F
->
getName
(
)
<<
"\n"
)
;
F
->
addFnAttr
(
"nomips16"
)
;
}
else
{
DEBUG
(
dbgs
(
)
<<
"os16 forced mips16: "
<<
F
->
getName
(
)
<<
"\n"
)
;
F
->
addFnAttr
(
"mips16"
)
;
}
}
}
return
modified
;
}
</s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

Mips
Mips
Mips
0
"Run on Module MipsOs16 \n"
Mips
"\n"
"using mask \n"
Mips
"\n"
0
"Working on "
"\n"
Mips
0
Mips
"mask forced mips32: "
"\n"
"nomips16"
"os16 forced mips32: "
"\n"
"nomips16"
"os16 forced mips16: "
"\n"
"mips16"


<s> bool AMDGPUTargetLowering :: shouldReduceLoadWidth ( SDNode * N , ISD :: LoadExtType , EVT NewVT ) const { unsigned NewSize = NewVT . getStoreSizeInBits ( ) ; if ( NewSize == 32 ) return true ; EVT OldVT = N -> getValueType ( 0 ) ; unsigned OldSize = OldVT . getStoreSizeInBits ( ) ; return ( OldSize < 32 ) ; } </s>

Return true if we believe it is correct and profitable to reduce the load node to a smaller type .


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx tlsarg , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; rtx r12 = NULL_RTX ; rtx func_addr = func_desc ; if ( global_tlsarg ) tlsarg = global_tlsarg ; if ( INTVAL ( cookie ) & CALL_LONG && SYMBOL_REF_P ( func_desc ) ) { gcc_assert ( rs6000_pcrel_p ( ) ) ; func_desc = rs6000_longcall_ref ( func_desc , tlsarg ) ; } else gcc_assert ( INTVAL ( cookie ) == 0 ) ; if ( GET_CODE ( func_desc ) != SYMBOL_REF && DEFAULT_ABI == ABI_ELFv2 ) { r12 = gen_rtx_REG ( Pmode , 12 ) ; emit_move_insn ( r12 , func_desc ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , r12 ) ; } call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; if ( ! rs6000_pcrel_p ( ) ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; if ( r12 ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , r12 ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


<s> SDValue SystemZDAGToDAGISel :: getUNDEF ( SDLoc DL , EVT VT ) const { SDNode * N = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , VT ) ; return SDValue ( N , 0 ) ; } </s>

Return an UNDEF node . UNDEF does not have a useful SDLoc .


<s> bool assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const override { std :: reverse ( CSI . begin ( ) , CSI . end ( ) ) ; return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> unsigned OR1KTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return OR1K :: R3 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> static void thumb_set_frame_pointer ( arm_stack_offsets * offsets ) { HOST_WIDE_INT amount ; rtx insn , dwarf ; amount = offsets -> outgoing_args - offsets -> locals_base ; if ( amount < 1024 ) insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ; else { emit_insn ( gen_movsi ( hard_frame_pointer_rtx , GEN_INT ( amount ) ) ) ; if ( TARGET_THUMB2 ) { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } else { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; } dwarf = gen_rtx_SET ( hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , amount ) ) ; RTX_FRAME_RELATED_P ( dwarf ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Set the Thumb frame pointer from the stack pointer .


<s> void AnalyzeCallResult ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn , const TargetLowering :: CallLoweringInfo & CLI ) { PreAnalyzeCallResultForF128 ( Ins , CLI ) ; CCState :: AnalyzeCallResult ( Ins , Fn ) ; OriginalArgWasF128 . clear ( ) ; } </s>

AnalyzeCallResult - Same as above except it 's specialized for calls which produce a single value .


<s> static HOST_WIDE_INT arm_vector_alignment ( const_tree type ) { HOST_WIDE_INT align = tree_to_shwi ( TYPE_SIZE ( type ) ) ; if ( TARGET_AAPCS_BASED ) align = MIN ( align , 64 ) ; return align ; } </s>

The AAPCS sets the maximum alignment of a vector to 64 bits .


<s> static char * sorted_attr_string ( tree arglist ) { tree arg ; size_t str_len_sum = 0 ; char * * args = NULL ; char * attr_str , * ret_str ; char * attr = NULL ; unsigned int argnum = 1 ; unsigned int i ; for ( arg = arglist ; arg ; arg = TREE_CHAIN ( arg ) ) { const char * str = TREE_STRING_POINTER ( TREE_VALUE ( arg ) ) ; size_t len = strlen ( str ) ; str_len_sum += len + 1 ; if ( arg != arglist ) argnum ++ ; for ( i = 0 ; i < strlen ( str ) ; i ++ ) if ( str [ i ] == ',' ) argnum ++ ; } attr_str = XNEWVEC ( char , str_len_sum ) ; str_len_sum = 0 ; for ( arg = arglist ; arg ; arg = TREE_CHAIN ( arg ) ) { const char * str = TREE_STRING_POINTER ( TREE_VALUE ( arg ) ) ; size_t len = strlen ( str ) ; memcpy ( attr_str + str_len_sum , str , len ) ; attr_str [ str_len_sum + len ] = TREE_CHAIN ( arg ) ? ',' : '\0' ; str_len_sum += len + 1 ; } for ( i = 0 ; i < strlen ( attr_str ) ; i ++ ) if ( attr_str [ i ] == '=' || attr_str [ i ] == '-' ) attr_str [ i ] = '_' ; if ( argnum == 1 ) return attr_str ; args = XNEWVEC ( char * , argnum ) ; i = 0 ; attr = strtok ( attr_str , "," ) ; while ( attr != NULL ) { args [ i ] = attr ; i ++ ; attr = strtok ( NULL , "," ) ; } qsort ( args , argnum , sizeof ( char * ) , attr_strcmp ) ; ret_str = XNEWVEC ( char , str_len_sum ) ; str_len_sum = 0 ; for ( i = 0 ; i < argnum ; i ++ ) { size_t len = strlen ( args [ i ] ) ; memcpy ( ret_str + str_len_sum , args [ i ] , len ) ; ret_str [ str_len_sum + len ] = i < argnum - 1 ? '_' : '\0' ; str_len_sum += len + 1 ; } XDELETEVEC ( args ) ; XDELETEVEC ( attr_str ) ; return ret_str ; } </s>

ARGLIST is the argument to target attribute . This function tokenizes the comma separated arguments , sorts them and returns a string which is a unique identifier for the comma separated arguments . It also replaces non-identifier characters `` = , - '' with `` _ '' .


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> unsigned MipsMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s> bool UnmangledFuncInfo :: lookup ( StringRef Name , ID & Id ) { auto Loc = Map . find ( Name ) ; if ( Loc != Map . end ( ) ) { Id = toFuncId ( Loc -> second ) ; return true ; } Id = AMDGPULibFunc :: EI_NONE ; return false ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . isOSWindows ( ) || TargetABI == ARMBaseTargetMachine :: ARM_ABI_AAPCS16 ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ; } </s>


<s> StringRef X86ATTInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode ) ; } </s>

Return a string representation for an opcode .


<s> void spu_expand_vector_init ( rtx target , rtx vals ) { machine_mode mode = GET_MODE ( target ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 ; bool all_same = true ; rtx first , x = NULL_RTX , first_constant = NULL_RTX ; int i ; first = XVECEXP ( vals , 0 , 0 ) ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_DOUBLE || GET_CODE ( x ) == CONST_FIXED ) ) ++ n_var ; else { if ( first_constant == NULL_RTX ) first_constant = x ; } if ( i > 0 && ! rtx_equal_p ( x , first ) ) all_same = false ; } if ( all_same ) { if ( ! CONSTANT_P ( first ) && ! register_operand ( first , GET_MODE ( x ) ) ) first = force_reg ( GET_MODE ( first ) , first ) ; emit_insn ( gen_spu_splats ( target , first ) ) ; return ; } if ( n_var != n_elts ) { if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; } else { rtx constant_parts_rtx = copy_rtx ( vals ) ; gcc_assert ( first_constant != NULL_RTX ) ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( constant_parts_rtx , 0 , i ) ; if ( ! ( CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_DOUBLE || GET_CODE ( x ) == CONST_FIXED ) ) XVECEXP ( constant_parts_rtx , 0 , i ) = first_constant ; } spu_expand_vector_init ( target , constant_parts_rtx ) ; } } if ( n_var != 0 ) { rtx insert_operands [ 4 ] ; insert_operands [ 0 ] = target ; insert_operands [ 2 ] = target ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! ( CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_DOUBLE || GET_CODE ( x ) == CONST_FIXED ) ) { if ( ! register_operand ( x , GET_MODE ( x ) ) ) x = force_reg ( GET_MODE ( x ) , x ) ; insert_operands [ 1 ] = x ; insert_operands [ 3 ] = GEN_INT ( i ) ; spu_builtin_insert ( insert_operands ) ; } } } } </s>

expand vector initialization . If there are any constant parts , load constant parts first . Then load any non-constant parts .


<s> bool AMDGPUPassConfig :: addInstSelector ( ) { addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) ) ) ; addPass ( createSILowerI1CopiesPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s>
MachineInstr
*
RISCVInstrInfo
::
convertToThreeAddress
(
MachineInstr
&
MI
,
LiveVariables
*
LV
,
LiveIntervals
*
LIS
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
CASE_WIDEOP_OPCODE_LMULS_MF4
(
FWADD_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS_MF4
(
FWSUB_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WADD_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WADDU_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WSUB_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WSUBU_WV
)
:
{
unsigned
NewOpc
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected opcode"
)
;
CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4
(
FWADD_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4
(
FWSUB_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WADD_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WADDU_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WSUB_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WSUBU_WV
)
}
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
NewOpc
)
)
.
add
(
MI
.
getOperand
(
0
)
)
.
add
(
MI
.
getOperand
(
1
)
)
.
add
(
MI
.
getOperand
(
2
)
)
.
add
(
MI
.
getOperand
(
3
)
)
.
add
(
MI
.
getOperand
(
4
)
)
;
MIB
.
copyImplicitOps
(
MI
)
;
if
(
LV
)
{
unsigned
NumOps
=
MI
.
getNumOperands
(
)
;
for
(
unsigned
I
=
1
;
I
<
NumOps
;
++
I
)
{
MachineOperand
&
Op
=
MI
.
getOperand
(
I
)
;
if
(
Op
.
isReg
(
)
&&
Op
.
isKill
(
)
)
LV
->
replaceKillInstruction
(
Op
.
getReg
(
)
,
MI
,
*
MIB
)
;
}
}
if
(
LIS
)
{
SlotIndex
Idx
=
LIS
->
ReplaceMachineInstrInMaps
(
MI
,
*
MIB
)
;
if
(
MI
.
getOperand
(
0
)
.
isEarlyClobber
(
)
)
{
LiveInterval
&
LI
=
LIS
->
getInterval
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
;
LiveRange
::
Segment
*
S
=
LI
.
getSegmentContaining
(
Idx
)
;
if
(
S
->
end
==
Idx
.
getRegSlot
(
true
)
)
S
->
end
=
Idx
.
getRegSlot
(
)
;
}
}
return
MIB
;
}
}
return
nullptr
;
}
</s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s> void Cpu0PassConfig :: addPreEmitPass ( ) { Cpu0TargetMachine & TM = getCpu0TargetMachine ( ) ; addPass ( createCpu0DelJmpPass ( TM ) ) ; addPass ( createCpu0DelaySlotFillerPass ( TM ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void s390_conditional_register_usage ( void ) { int i ; if ( flag_pic ) { fixed_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; call_used_regs [ PIC_OFFSET_TABLE_REGNUM ] = 1 ; } if ( TARGET_CPU_ZARCH ) { fixed_regs [ BASE_REGNUM ] = 0 ; call_used_regs [ BASE_REGNUM ] = 0 ; fixed_regs [ RETURN_REGNUM ] = 0 ; call_used_regs [ RETURN_REGNUM ] = 0 ; } if ( TARGET_64BIT ) { for ( i = FPR8_REGNUM ; i <= FPR15_REGNUM ; i ++ ) call_used_regs [ i ] = call_really_used_regs [ i ] = 0 ; } else { call_used_regs [ FPR4_REGNUM ] = call_really_used_regs [ FPR4_REGNUM ] = 0 ; call_used_regs [ FPR6_REGNUM ] = call_really_used_regs [ FPR6_REGNUM ] = 0 ; } if ( TARGET_SOFT_FLOAT ) { for ( i = FPR0_REGNUM ; i <= FPR15_REGNUM ; i ++ ) call_used_regs [ i ] = fixed_regs [ i ] = 1 ; } } </s>


<s> bool LoongArchFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void MINA32RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void m68hc11_init_libfuncs ( void ) { memcpy_libfunc = init_one_libfunc ( "__memcpy" ) ; memcmp_libfunc = init_one_libfunc ( "__memcmp" ) ; memset_libfunc = init_one_libfunc ( "__memset" ) ; } </s>


<s> void GCNPassConfig :: addOptimizedRegAlloc ( ) { insertPass ( & MachineSchedulerID , & SIWholeQuadModeID ) ; insertPass ( & MachineSchedulerID , & SIPreAllocateWWMRegsID ) ; if ( OptExecMaskPreRA ) insertPass ( & MachineSchedulerID , & SIOptimizeExecMaskingPreRAID ) ; insertPass ( & MachineSchedulerID , & SIFormMemoryClausesID ) ; insertPass ( & PHIEliminationID , & SILowerControlFlowID , false ) ; if ( EnableDCEInRA ) insertPass ( & DetectDeadLanesID , & DeadMachineInstructionElimID ) ; TargetPassConfig :: addOptimizedRegAlloc ( ) ; } </s>

addOptimizedRegAlloc - Add passes related to register allocation .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( const TargetRegisterInfo * TRI , MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( TRI , VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget . is64Bit ( ) ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> static void arm_override_options_after_change ( void ) { arm_override_options_after_change_1 ( & global_options ) ; } </s>


<s> ARMELFStreamer & ARMTargetELFStreamer :: getStreamer ( ) { return static_cast < ARMELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s>
bool
AVRInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"unexpected opcode!"
)
;
case
AVR
::
JMPk
:
case
AVR
::
CALLk
:
assert
(
BrOffset
>=
0
&&
"offset must be absolute address"
)
;
return
isUIntN
(
16
,
BrOffset
)
;
case
AVR
::
RCALLk
:
case
AVR
::
RJMPk
:
return
isIntN
(
13
,
BrOffset
)
;
case
AVR
::
BRBSsk
:
case
AVR
::
BRBCsk
:
case
AVR
::
BREQk
:
case
AVR
::
BRNEk
:
case
AVR
::
BRSHk
:
case
AVR
::
BRLOk
:
case
AVR
::
BRMIk
:
case
AVR
::
BRPLk
:
case
AVR
::
BRGEk
:
case
AVR
::
BRLTk
:
return
isIntN
(
7
,
BrOffset
)
;
}
}
</s>

Determine if the branch target is in range .

AVR
AVR
"unexpected opcode!"
AVR::JMPk
AVR::CALLk
0
"offset must be absolute address"
16
AVR::RCALLk
AVR::RJMPk
13
AVR::BRBSsk
AVR::BRBCsk
AVR::BREQk
AVR::BRNEk
AVR::BRSHk
AVR::BRLOk
AVR::BRMIk
AVR::BRPLk
AVR::BRGEk
AVR::BRLTk
7


<s> static rtx alignment_with_canonical_addr ( rtx align ) { rtx canon ; rtx addr = XEXP ( align , 0 ) ; if ( REG_P ( addr ) ) canon = addr ; else if ( GET_CODE ( addr ) == PLUS ) { rtx addrop0 = XEXP ( addr , 0 ) ; rtx addrop1 = XEXP ( addr , 1 ) ; if ( ! REG_P ( addrop0 ) ) addrop0 = force_reg ( GET_MODE ( addrop0 ) , addrop0 ) ; if ( ! REG_P ( addrop1 ) ) addrop1 = force_reg ( GET_MODE ( addrop1 ) , addrop1 ) ; canon = gen_rtx_PLUS ( GET_MODE ( addr ) , addrop0 , addrop1 ) ; } else canon = force_reg ( GET_MODE ( addr ) , addr ) ; return gen_rtx_AND ( GET_MODE ( align ) , canon , GEN_INT ( - 16 ) ) ; } </s>

Return RTX with its address canonicalized to ( reg ) or ( + reg reg ) . Here RTX is an ( & addr ( const_int -16 ) ) . Always return a new copy to avoid problems with combine .


<s>
void
M680x0InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
unsigned
DstReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
assert
(
MF
.
getFrameInfo
(
)
.
getObjectSize
(
FrameIndex
)
==
4
&&
"Stack slot too small for store"
)
;
unsigned
Opc
=
getLoadRegOpcode
(
DstReg
,
RC
,
TRI
,
Subtarget
)
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
addFrameReference
(
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DstReg
)
,
FrameIndex
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"

runOnMachineFunction - Emit the function body .


<s> static void emit_frame_store_1 ( rtx value , rtx base_reg , HOST_WIDE_INT frame_bias , HOST_WIDE_INT base_ofs , rtx frame_reg ) { rtx addr , mem ; rtx_insn * insn ; addr = plus_constant ( Pmode , base_reg , base_ofs ) ; mem = gen_frame_mem ( DImode , addr ) ; insn = emit_move_insn ( mem , value ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( frame_bias || value != frame_reg ) { if ( frame_bias ) { addr = plus_constant ( Pmode , stack_pointer_rtx , frame_bias + base_ofs ) ; mem = gen_rtx_MEM ( DImode , addr ) ; } add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , mem , frame_reg ) ) ; } } </s>

Generates a store with the proper unwind info attached . VALUE is stored at BASE_REG+BASE_OFS . If FRAME_BIAS is nonzero , then BASE_REG contains SP+FRAME_BIAS , and that is the unwind info that should be generated . If FRAME_REG ! = VALUE , then VALUE is being stored on behalf of FRAME_REG , and FRAME_REG should be present in the unwind .


<s> static void update_total_code_bytes ( int nbytes ) { if ( ( TARGET_PORTABLE_RUNTIME || ! TARGET_GAS || ! TARGET_SOM ) && ! IN_NAMED_SECTION_P ( cfun -> decl ) ) { if ( INSN_ADDRESSES_SET_P ( ) ) { unsigned long old_total = total_code_bytes ; total_code_bytes += nbytes ; if ( old_total > total_code_bytes ) total_code_bytes = - 1 ; } else total_code_bytes = - 1 ; } } </s>

Update the total code bytes output to the text section .


<s> bool isKMergeMasked ( ) const { return ( Attributes & X86FMA3KMergeMasked ) != 0 ; } </s>

Returns true iff the group of FMA opcodes holds k-merge-masked opcodes .


<s> static rtx gen_sym_unspec ( rtx x , int kind ) { return gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , x ) , kind ) ; } </s>

Helper for or1k_legitimize_address_1 . Wrap X in an unspec .


<s> static void csky_initialize_isa ( sbitmap isa , const enum csky_isa_feature * isa_bits ) { bitmap_clear ( isa ) ; while ( * isa_bits != CSKY_ISA_FEATURE_GET ( none ) ) bitmap_set_bit ( isa , * ( isa_bits ++ ) ) ; } </s>

Convert a static initializer array of feature bits to sbitmap representation .


<s> bool AArch64RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; DomBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; OptBBClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeBlock ( & MBB ) ; return Changed ; } </s>


<s>
void
PPCHazardRecognizer970
::
AdvanceCycle
(
)
{
assert
(
NumIssued
<
5
&&
"Illegal dispatch group!"
)
;
++
NumIssued
;
if
(
NumIssued
==
5
)
EndDispatchGroup
(
)
;
}
</s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


<s> void AArch64TTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP ) { BaseT :: getUnrollingPreferences ( L , SE , UP ) ; if ( L -> getLoopDepth ( ) > 1 ) UP . PartialThreshold *= 2 ; UP . PartialOptSizeThreshold = 0 ; if ( ST -> getProcFamily ( ) == AArch64Subtarget :: Falkor && EnableFalkorHWPFUnrollFix ) getFalkorUnrollingPreferences ( L , SE , UP ) ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ; } } } if ( ST -> getProcFamily ( ) != AArch64Subtarget :: Others && ! ST -> getSchedModel ( ) . isOutOfOrder ( ) ) { UP . Runtime = true ; UP . Partial = true ; UP . UpperBound = true ; UP . UnrollRemainder = true ; UP . DefaultUnrollRuntimeCount = 4 ; UP . UnrollAndJam = true ; UP . UnrollAndJamInnerLoopThreshold = 60 ; } } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> enum reg_class mmix_secondary_reload_class ( enum reg_class rclass , machine_mode mode ATTRIBUTE_UNUSED , rtx x ATTRIBUTE_UNUSED , int in_p ATTRIBUTE_UNUSED ) { if ( rclass == REMAINDER_REG || rclass == HIMULT_REG || rclass == SYSTEM_REGS ) return GENERAL_REGS ; return NO_REGS ; } </s>

SECONDARY_RELOAD_CLASS . We need to reload regs of REMAINDER_REG and HIMULT_REG elsewhere .


"instruction requires a CPU feature not currently enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


"\nrs6000_secondary_reload_class, return %s, rclass = %s, "

Debug version of rs6000_secondary_reload_class .


<s> bool csky_simple_addr_operand_p ( rtx op ) { struct csky_address addr ; if ( ! decompose_csky_address ( op , & addr ) ) return false ; if ( addr . disp && GET_CODE ( addr . disp ) == UNSPEC ) return false ; if ( ! addr . index && ! addr . symbol ) return true ; return false ; } </s>

Helper function for the csky_simple_mem_operand predicate . Returns true if OP is an address of the form reg + displacement .


<s> static bool shouldExpandVectorDynExt ( SDNode * N ) { SDValue Idx = N -> getOperand ( N -> getNumOperands ( ) - 1 ) ; if ( isa < ConstantSDNode > ( Idx ) ) return false ; SDValue Vec = N -> getOperand ( 0 ) ; EVT VecVT = Vec . getValueType ( ) ; EVT EltVT = VecVT . getVectorElementType ( ) ; unsigned EltSize = EltVT . getSizeInBits ( ) ; unsigned NumElem = VecVT . getVectorNumElements ( ) ; return SITargetLowering :: shouldExpandVectorDynExt ( EltSize , NumElem , Idx -> isDivergent ( ) ) ; } </s>

Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT ( < n x e > , var-idx ) should be expanded into a set of cmp/select instructions .


"TeeRISC DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool prefixed_load_p ( rtx_insn * insn ) { extract_insn_cached ( insn ) ; if ( recog_data . n_operands < 2 ) return false ; rtx reg = recog_data . operand [ 0 ] ; rtx mem = recog_data . operand [ 1 ] ; if ( ! REG_P ( reg ) && ! SUBREG_P ( reg ) ) return false ; if ( ! MEM_P ( mem ) ) return false ; if ( get_attr_indexed ( insn ) == INDEXED_YES || get_attr_update ( insn ) == UPDATE_YES ) return false ; enum non_prefixed_form non_prefixed ; machine_mode reg_mode = GET_MODE ( reg ) ; machine_mode mem_mode = GET_MODE ( mem ) ; if ( mem_mode == SImode && reg_mode == DImode && get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES ) non_prefixed = NON_PREFIXED_DS ; else non_prefixed = reg_to_non_prefixed ( reg , mem_mode ) ; if ( non_prefixed == NON_PREFIXED_X && is_lfs_stfs_insn ( insn ) ) return address_is_prefixed ( XEXP ( mem , 0 ) , mem_mode , NON_PREFIXED_DEFAULT ) ; else return address_is_prefixed ( XEXP ( mem , 0 ) , mem_mode , non_prefixed ) ; } </s>

Whether a load instruction is a prefixed instruction . This is called from the prefixed attribute processing .


<s> static void adjust_subreg_index ( rtx op ) { enum rtx_code code = GET_CODE ( op ) ; if ( code == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( op ) ) < GET_MODE_SIZE ( GET_MODE ( XEXP ( op , 0 ) ) ) ) ) { unsigned int index = SUBREG_BYTE ( op ) ; if ( index < 8 ) index += 8 ; else index -= 8 ; SUBREG_BYTE ( op ) = index ; } const char * fmt = GET_RTX_FORMAT ( code ) ; int i , j ; for ( i = 0 ; i < GET_RTX_LENGTH ( code ) ; ++ i ) if ( fmt [ i ] == 'e' || fmt [ i ] == 'u' ) adjust_subreg_index ( XEXP ( op , i ) ) ; else if ( fmt [ i ] == 'E' ) for ( j = 0 ; j < XVECLEN ( op , i ) ; ++ j ) adjust_subreg_index ( XVECEXP ( op , i , j ) ) ; } </s>

Find all subregs of a vector expression that perform a narrowing , and adjust the subreg index to account for doubleword swapping .


<s> static void ia64_set_sched_context ( void * _sc ) { ia64_sched_context_t sc = ( ia64_sched_context_t ) _sc ; gcc_assert ( sc != NULL ) ; memcpy ( prev_cycle_state , sc -> prev_cycle_state , dfa_state_size ) ; last_scheduled_insn = sc -> last_scheduled_insn ; memcpy ( rws_sum , sc -> rws_sum , sizeof ( rws_sum ) ) ; memcpy ( rws_insn , sc -> rws_insn , sizeof ( rws_insn ) ) ; first_instruction = sc -> first_instruction ; pending_data_specs = sc -> pending_data_specs ; current_cycle = sc -> current_cycle ; memcpy ( mem_ops_in_group , sc -> mem_ops_in_group , sizeof ( mem_ops_in_group ) ) ; } </s>

Sets the global scheduling context to the one pointed to by _SC .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool X86InstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == X86 :: ENDBR64 || Opcode == X86 :: ENDBR32 || Opcode == X86 :: PLDTILECFGV ) return true ; return TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s>
if
(
!
TII
->
fitsConstReadLimitations
(
CurrentPacketMIs
)
)
{
DEBUG
(
{
dbgs
(
)
<<
"Couldn't pack :\n"
;
MI
.
dump
(
)
;
dbgs
(
)
<<
"with the following packets :\n"
;
for
(
unsigned
i
=
0
,
e
=
CurrentPacketMIs
.
size
(
)
1
;
i
<
e
;
i
++
)
{
CurrentPacketMIs
[
i
]
->
dump
(
)
;
dbgs
(
)
<<
"\n"
;
}
dbgs
(
)
<<
"because of Consts read limitations\n"
;
}
</s>

Same but using const index set instead of MI set .

AMDGPU
"Couldn't pack :\n"
"with the following packets :\n"
0
1
"\n"
"because of Consts read limitations\n"


<s> static bool bfin_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , const_tree type , bool named ATTRIBUTE_UNUSED ) { return type && TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ; } </s>

Variable sized types are passed by reference .


<s> Register SparcInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { SparcMachineFunctionInfo * SparcFI = MF -> getInfo < SparcMachineFunctionInfo > ( ) ; Register GlobalBaseReg = SparcFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * PtrRC = Subtarget . is64Bit ( ) ? & SP :: I64RegsRegClass : & SP :: IntRegsRegClass ; GlobalBaseReg = RegInfo . createVirtualRegister ( PtrRC ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( SP :: GETPCX ) , GlobalBaseReg ) ; SparcFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

Sparc Sparc Sparc Sparc Sparc Sparc SP::I64RegsRegClass SP::IntRegsRegClass SP::GETPCX Sparc


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> unsigned PPCTargetLowering :: combineRepeatedFPDivisors ( ) const { switch ( Subtarget . getMcpu ( ) ) { default : return 3 ; case PPC :: MCPU_440 : case PPC :: MCPU_A2 : case PPC :: MCPU_E500 : case PPC :: MCPU_E500mc : case PPC :: MCPU_E5500 : return 2 ; } } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; PPCLowering = TM . getTargetLowering ( ) ; PPCSubTarget = TM . getSubtargetImpl ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! PPCSubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> static bool have_compare_and_set_mask ( machine_mode mode ) { switch ( mode ) { case E_SFmode : case E_DFmode : return TARGET_P9_MINMAX ; case E_KFmode : case E_TFmode : return TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P ( mode ) ; default : break ; } return false ; } </s>

Helper function to return true if the target has instructions to do a compare and set mask instruction that can be used with XXSEL to implement a conditional move . It is also assumed that such a target also supports the `` C '' minimum and maximum instructions .


<s> const MipsSubtarget * MipsTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool hasMips16Attr = ! F . getFnAttribute ( "mips16" ) . hasAttribute ( Attribute :: None ) ; bool hasNoMips16Attr = ! F . getFnAttribute ( "nomips16" ) . hasAttribute ( Attribute :: None ) ; bool HasMicroMipsAttr = ! F . getFnAttribute ( "micromips" ) . hasAttribute ( Attribute :: None ) ; bool HasNoMicroMipsAttr = ! F . getFnAttribute ( "nomicromips" ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( hasMips16Attr ) FS += FS . empty ( ) ? "+mips16" : ",+mips16" ; else if ( hasNoMips16Attr ) FS += FS . empty ( ) ? "-mips16" : ",-mips16" ; if ( HasMicroMipsAttr ) FS += FS . empty ( ) ? "+micromips" : ",+micromips" ; else if ( HasNoMicroMipsAttr ) FS += FS . empty ( ) ? "-micromips" : ",-micromips" ; if ( softFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < MipsSubtarget > ( TargetTriple , CPU , FS , isLittle , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

Mips Mips Mips "target-cpu" "target-features" Mips "mips16" Mips "nomips16" Mips "micromips" Mips "nomicromips" "use-soft-float" "use-soft-float" "true" Mips "+mips16" ",+mips16" Mips "-mips16" ",-mips16" Mips "+micromips" ",+micromips" Mips "-micromips" ",-micromips" "+soft-float" ",+soft-float" Mips


<s> rtx scalar_chain :: replace_with_subreg ( rtx x , rtx reg , rtx new_reg ) { if ( x == reg ) return gen_rtx_SUBREG ( V2DImode , new_reg , 0 ) ; const char * fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; int i , j ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'e' ) XEXP ( x , i ) = replace_with_subreg ( XEXP ( x , i ) , reg , new_reg ) ; else if ( fmt [ i ] == 'E' ) for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) XVECEXP ( x , i , j ) = replace_with_subreg ( XVECEXP ( x , i , j ) , reg , new_reg ) ; } return x ; } </s>

Replace REG in X with a V2DI subreg of NEW_REG .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void rs6000_split_signbit ( rtx dest , rtx src ) { machine_mode d_mode = GET_MODE ( dest ) ; machine_mode s_mode = GET_MODE ( src ) ; rtx dest_di = ( d_mode == DImode ) ? dest : gen_lowpart ( DImode , dest ) ; rtx shift_reg = dest_di ; gcc_assert ( FLOAT128_IEEE_P ( s_mode ) && TARGET_POWERPC64 ) ; if ( MEM_P ( src ) ) { rtx mem = ( WORDS_BIG_ENDIAN ? adjust_address ( src , DImode , 0 ) : adjust_address ( src , DImode , 8 ) ) ; emit_insn ( gen_rtx_SET ( dest_di , mem ) ) ; } else { unsigned int r = reg_or_subregno ( src ) ; if ( INT_REGNO_P ( r ) ) shift_reg = gen_rtx_REG ( DImode , r + ( BYTES_BIG_ENDIAN == 0 ) ) ; else { gcc_assert ( VSX_REGNO_P ( r ) ) ; if ( s_mode == KFmode ) emit_insn ( gen_signbitkf2_dm2 ( dest_di , src ) ) ; else emit_insn ( gen_signbittf2_dm2 ( dest_di , src ) ) ; } } emit_insn ( gen_lshrdi3 ( dest_di , shift_reg , GEN_INT ( 63 ) ) ) ; return ; } </s>

Split a signbit operation on 64-bit machines with direct move . Also allow for the value to come from memory or if it is already loaded into a GPR .


<s>
const
char
*
mips_output_equal_conditional_branch
(
rtx_insn
*
insn
,
rtx
*
operands
,
bool
inverted_p
)
{
const
char
*
branch
[
2
]
;
if
(
TARGET_MICROMIPS
&&
mips_isa_rev
<=
5
&&
operands
[
3
]
==
const0_rtx
&&
get_attr_length
(
insn
)
<=
8
)
{
if
(
mips_cb
==
MIPS_CB_OPTIMAL
)
{
branch
[
!
inverted_p
]
=
"%*b%C1z%:\t%2,%0"
;
branch
[
inverted_p
]
=
"%*b%N1z%:\t%2,%0"
;
}
else
{
branch
[
!
inverted_p
]
=
"%*b%C1z\t%2,%0%/"
;
branch
[
inverted_p
]
=
"%*b%N1z\t%2,%0%/"
;
}
}
else
if
(
TARGET_CB_MAYBE
)
{
if
(
operands
[
3
]
==
const0_rtx
)
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b%C1z"
,
"%2,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH_C
(
"b%N1z"
,
"%2,%0"
)
;
}
else
if
(
REGNO
(
operands
[
2
]
)
!=
REGNO
(
operands
[
3
]
)
)
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b%C1"
,
"%2,%3,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH_C
(
"b%N1"
,
"%2,%3,%0"
)
;
}
else
{
if
(
GET_CODE
(
operands
[
1
]
)
==
NE
)
inverted_p
=
!
inverted_p
;
branch
[
!
inverted_p
]
=
MIPS_BRANCH_C
(
"b"
,
"%0"
)
;
branch
[
inverted_p
]
=
"%*\t\t# branch never"
;
}
}
else
{
branch
[
!
inverted_p
]
=
MIPS_BRANCH
(
"b%C1"
,
"%2,%z3,%0"
)
;
branch
[
inverted_p
]
=
MIPS_BRANCH
(
"b%N1"
,
"%2,%z3,%0"
)
;
}
return
mips_output_conditional_branch
(
insn
,
operands
,
branch
[
1
]
,
branch
[
0
]
)
;
}
</s>

Return the assembly code for INSN , which branches to OPERANDS [ 0 ] if some equality condition is true . The condition is given by OPERANDS [ 1 ] if ! INVERTED_P , otherwise it is the inverse of OPERANDS [ 1 ] . OPERANDS [ 2 ] is the comparison 's first operand ; OPERANDS [ 3 ] is the second operand and may be zero or a register .


<s> static int rws_access_regno ( int regno , struct reg_flags flags , int pred ) { int need_barrier = 0 ; gcc_assert ( regno < NUM_REGS ) ; if ( ! PR_REGNO_P ( regno ) ) flags . is_and = flags . is_or = 0 ; if ( flags . is_write ) { int write_count ; rws_insn_set ( regno ) ; write_count = rws_sum [ regno ] . write_count ; switch ( write_count ) { case 0 : if ( ! in_safe_group_barrier ) rws_update ( regno , flags , pred ) ; break ; case 1 : if ( flags . is_and && rws_sum [ regno ] . written_by_and ) ; else if ( flags . is_or && rws_sum [ regno ] . written_by_or ) ; else need_barrier = 1 ; if ( ! in_safe_group_barrier ) rws_update ( regno , flags , pred ) ; break ; case 2 : if ( flags . is_and && rws_sum [ regno ] . written_by_and ) ; else if ( flags . is_or && rws_sum [ regno ] . written_by_or ) ; else need_barrier = 1 ; if ( ! in_safe_group_barrier ) { rws_sum [ regno ] . written_by_and = flags . is_and ; rws_sum [ regno ] . written_by_or = flags . is_or ; } break ; default : gcc_unreachable ( ) ; } } else { if ( flags . is_branch ) { if ( REGNO_REG_CLASS ( regno ) == BR_REGS || regno == AR_PFS_REGNUM ) return 0 ; if ( REGNO_REG_CLASS ( regno ) == PR_REGS && ! rws_sum [ regno ] . written_by_fp ) return 0 ; } if ( flags . is_and && rws_sum [ regno ] . written_by_and ) return 0 ; if ( flags . is_or && rws_sum [ regno ] . written_by_or ) return 0 ; switch ( rws_sum [ regno ] . write_count ) { case 0 : break ; case 1 : need_barrier = 1 ; break ; case 2 : need_barrier = 1 ; break ; default : gcc_unreachable ( ) ; } } return need_barrier ; } </s>

Handle an access to register REGNO of type FLAGS using predicate register PRED . Update rws_insn and rws_sum arrays . Return 1 if this access creates a dependency with an earlier instruction in the same group .


<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
MCOI
::
OPERAND_FIRST_TARGET
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
OperandType
)
{
case
AMDGPU
::
OPERAND_REG_IMM_INT32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
Trunc
==
Imm
&&
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT64
:
case
AMDGPU
::
OPERAND_REG_IMM_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP64
:
{
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT16
:
case
AMDGPU
::
OPERAND_REG_IMM_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
:
{
uint32_t
Trunc
=
static_cast
<
uint32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteralV216
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
for
(
MachineInstr
&
MI
:
MBB
)
{
if
(
!
MI
.
isFullCopy
(
)
)
continue
;
MachineOperand
&
DstMO
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
SrcMO
=
MI
.
getOperand
(
1
)
;
if
(
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
!
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
SrcRC
=
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown source for a VSX copy"
)
;
Register
NewVReg
=
MRI
.
createVirtualRegister
(
SrcRC
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
SUBREG_TO_REG
)
,
NewVReg
)
.
addImm
(
1
)
.
add
(
SrcMO
)
.
addImm
(
PPC
::
sub_64
)
;
SrcMO
.
setReg
(
NewVReg
)
;
}
else
if
(
!
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
DstRC
=
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSSReg
(
DstMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown destination for a VSX copy"
)
;
Register
NewVReg
=
MRI
.
createVirtualRegister
(
DstRC
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
NewVReg
)
.
add
(
SrcMO
)
;
SrcMO
.
setReg
(
NewVReg
)
;
SrcMO
.
setSubReg
(
PPC
::
sub_64
)
;
}
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> static void rs6000_set_up_by_prologue ( struct hard_reg_set_container * set ) { if ( ! TARGET_SINGLE_PIC_BASE && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size ( ) != 0 ) add_to_hard_reg_set ( & set -> set , Pmode , RS6000_PIC_OFFSET_TABLE_REGNUM ) ; if ( cfun -> machine -> split_stack_argp_used ) add_to_hard_reg_set ( & set -> set , Pmode , 12 ) ; } </s>

Add r30 to hard reg set if the prologue sets it up and it is not pic_offset_table_rtx .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; StringRef CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) : ( StringRef ) TargetCPU ; StringRef FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) : ( StringRef ) TargetFS ; SmallString < 512 > Key ; Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) Key += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; X86GISelActualAccessor * GISel = new X86GISelActualAccessor ( ) ; GISel -> CallLoweringInfo . reset ( new X86CallLowering ( * I -> getTargetLowering ( ) ) ) ; GISel -> Legalizer . reset ( new X86LegalizerInfo ( * I , * this ) ) ; auto * RBI = new X86RegisterBankInfo ( * I -> getRegisterInfo ( ) ) ; GISel -> RegBankInfo . reset ( RBI ) ; GISel -> InstSelector . reset ( createX86InstructionSelector ( * I , * RBI ) ) ; I -> setGISelAccessor ( * GISel ) ; } return I . get ( ) ; } </s>


<s> MCSymbol * ARM64AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) [ 0 ] ) return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + "CPI" + Twine ( getFunctionNumber ( ) ) + "_" + Twine ( CPID ) ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> bool ARM64PassConfig :: addPreRegAlloc ( ) { addPass ( createARM64AdvSIMDScalar ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> const MCInstrDesc & getMCOpcodeFromPseudo ( unsigned Opcode ) const { return get ( pseudoToMCOpcode ( Opcode ) ) ; } </s>

Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode .


<s> bool PPCPassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s>
SDNode
*
ARMTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallSDNode
*
TheCall
,
unsigned
CallingConv
,
SelectionDAG
&
DAG
)
{
DebugLoc
dl
=
TheCall
->
getDebugLoc
(
)
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
bool
isVarArg
=
TheCall
->
isVarArg
(
)
;
CCState
CCInfo
(
CallingConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
)
;
CCInfo
.
AnalyzeCallResult
(
TheCall
,
RetCC_ARM
)
;
SmallVector
<
SDValue
,
8
>
ResultVals
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
VA
=
RVLocs
[
i
]
;
SDValue
Val
;
if
(
VA
.
needsCustom
(
)
)
{
SDValue
Lo
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
i32
,
InFlag
)
;
Chain
=
Lo
.
getValue
(
1
)
;
InFlag
=
Lo
.
getValue
(
2
)
;
VA
=
RVLocs
[
++
i
]
;
SDValue
Hi
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
MVT
::
i32
,
InFlag
)
;
Chain
=
Hi
.
getValue
(
1
)
;
InFlag
=
Hi
.
getValue
(
2
)
;
Val
=
DAG
.
getNode
(
ARMISD
::
FMDRR
,
dl
,
MVT
::
f64
,
Lo
,
Hi
)
;
}
else
{
Val
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
}
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
assert
(
0
&&
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Val
=
DAG
.
getNode
(
ISD
::
BIT_CONVERT
,
dl
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
ResultVals
.
push_back
(
Val
)
;
}
ResultVals
.
push_back
(
Chain
)
;
return
DAG
.
getNode
(
ISD
::
MERGE_VALUES
,
dl
,
TheCall
->
getVTList
(
)
,
&
ResultVals
[
0
]
,
ResultVals
.
size
(
)
)
.
getNode
(
)
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool AMDGPUAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { OW -> WriteZeros ( Count ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void Cpu0AsmPrinter :: emitFrameDirective ( ) { const TargetRegisterInfo & RI = * MF -> getSubtarget ( ) . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) . getStackSize ( ) ; if ( OutStreamer -> hasRawTextSupport ( ) ) OutStreamer -> EmitRawText ( "\t.frame\t$" + StringRef ( Cpu0InstPrinter :: getRegisterName ( stackReg ) ) . lower ( ) + "," + Twine ( stackSize ) + ",$" + StringRef ( Cpu0InstPrinter :: getRegisterName ( returnReg ) ) . lower ( ) ) ; } </s>


"JVM doesn't support non-C calling conventions"

"JVM hasn't implemented inalloca results"

"JVM hasn't implemented cons regs results"

"JVM hasn't implemented cons regs last results"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> TargetLowering :: ConstraintWeight Cpu0TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'c' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> bool MipsTargetMachine :: addPreRegAlloc ( PassManagerBase & PM ) { if ( ! Subtarget . hasMips64 ( ) ) PM . add ( createMipsEmitGPRestorePass ( * this ) ) ; return true ; } </s>


<s> static int xtensa_sizeof_MOVI ( HOST_WIDE_INT imm ) { return ( TARGET_DENSITY && IN_RANGE ( imm , - 32 , 95 ) ) ? 2 : 3 ; } </s>

Try to expand a block set operation to a sequence of RTL move instructions . If not optimizing , or if the block size is not a constant , or if the block is too large , or if the value to initialize the block with is not a constant , the expansion fails and GCC falls back to calling memset ( ) . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 2 ] is the initialization value operands [ 3 ] is the alignment


<s> unsigned getPrefLoopAlignment ( ) const { return PrefLoopAlignment ; } </s>


<s> static bool mips_frame_pointer_required ( void ) { if ( cfun -> calls_alloca ) return true ; if ( TARGET_MIPS16 ) { mips_compute_frame_info ( ) ; if ( ! SMALL_OPERAND ( cfun -> machine -> frame . total_size ) ) return true ; } return false ; } </s>


<s>
Sparc
::
Fixups
SparcMCExpr
::
getFixupKind
(
SparcMCExpr
::
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Unhandled SparcMCExpr::VariantKind"
)
;
case
VK_Sparc_LO
:
return
Sparc
::
fixup_sparc_lo10
;
case
VK_Sparc_HI
:
return
Sparc
::
fixup_sparc_hi22
;
case
VK_Sparc_H44
:
return
Sparc
::
fixup_sparc_h44
;
case
VK_Sparc_M44
:
return
Sparc
::
fixup_sparc_m44
;
case
VK_Sparc_L44
:
return
Sparc
::
fixup_sparc_l44
;
case
VK_Sparc_HH
:
return
Sparc
::
fixup_sparc_hh
;
case
VK_Sparc_HM
:
return
Sparc
::
fixup_sparc_hm
;
case
VK_Sparc_LM
:
return
Sparc
::
fixup_sparc_lm
;
case
VK_Sparc_PC22
:
return
Sparc
::
fixup_sparc_pc22
;
case
VK_Sparc_PC10
:
return
Sparc
::
fixup_sparc_pc10
;
case
VK_Sparc_GOT22
:
return
Sparc
::
fixup_sparc_got22
;
case
VK_Sparc_GOT10
:
return
Sparc
::
fixup_sparc_got10
;
case
VK_Sparc_GOT13
:
return
Sparc
::
fixup_sparc_got13
;
case
VK_Sparc_13
:
return
Sparc
::
fixup_sparc_13
;
case
VK_Sparc_WPLT30
:
return
Sparc
::
fixup_sparc_wplt30
;
case
VK_Sparc_WDISP30
:
return
Sparc
::
fixup_sparc_call30
;
case
VK_Sparc_TLS_GD_HI22
:
return
Sparc
::
fixup_sparc_tls_gd_hi22
;
case
VK_Sparc_TLS_GD_LO10
:
return
Sparc
::
fixup_sparc_tls_gd_lo10
;
case
VK_Sparc_TLS_GD_ADD
:
return
Sparc
::
fixup_sparc_tls_gd_add
;
case
VK_Sparc_TLS_GD_CALL
:
return
Sparc
::
fixup_sparc_tls_gd_call
;
case
VK_Sparc_TLS_LDM_HI22
:
return
Sparc
::
fixup_sparc_tls_ldm_hi22
;
case
VK_Sparc_TLS_LDM_LO10
:
return
Sparc
::
fixup_sparc_tls_ldm_lo10
;
case
VK_Sparc_TLS_LDM_ADD
:
return
Sparc
::
fixup_sparc_tls_ldm_add
;
case
VK_Sparc_TLS_LDM_CALL
:
return
Sparc
::
fixup_sparc_tls_ldm_call
;
case
VK_Sparc_TLS_LDO_HIX22
:
return
Sparc
::
fixup_sparc_tls_ldo_hix22
;
case
VK_Sparc_TLS_LDO_LOX10
:
return
Sparc
::
fixup_sparc_tls_ldo_lox10
;
case
VK_Sparc_TLS_LDO_ADD
:
return
Sparc
::
fixup_sparc_tls_ldo_add
;
case
VK_Sparc_TLS_IE_HI22
:
return
Sparc
::
fixup_sparc_tls_ie_hi22
;
case
VK_Sparc_TLS_IE_LO10
:
return
Sparc
::
fixup_sparc_tls_ie_lo10
;
case
VK_Sparc_TLS_IE_LD
:
return
Sparc
::
fixup_sparc_tls_ie_ld
;
case
VK_Sparc_TLS_IE_LDX
:
return
Sparc
::
fixup_sparc_tls_ie_ldx
;
case
VK_Sparc_TLS_IE_ADD
:
return
Sparc
::
fixup_sparc_tls_ie_add
;
case
VK_Sparc_TLS_LE_HIX22
:
return
Sparc
::
fixup_sparc_tls_le_hix22
;
case
VK_Sparc_TLS_LE_LOX10
:
return
Sparc
::
fixup_sparc_tls_le_lox10
;
}
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget . classifyGlobalReference ( AM . BaseGV ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || isPositionIndependent ( ) ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


getTargetNodeName - This method returns the name of a target specific


"invalid instruction when using jump guards!"

Perform target-specific instruction verification .


<s> static int riscv_memory_move_cost ( enum machine_mode mode , reg_class_t rclass , bool in ) { return ( tune_info -> memory_cost + memory_move_secondary_cost ( mode , rclass , in ) ) ; } </s>


<s> unsigned RISCVTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { default : break ; case RISCVISD :: SELECT_CC : { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( 3 ) , DemandedElts , Depth + 1 ) ; if ( Tmp == 1 ) return 1 ; unsigned Tmp2 = DAG . ComputeNumSignBits ( Op . getOperand ( 4 ) , DemandedElts , Depth + 1 ) ; return std :: min ( Tmp , Tmp2 ) ; } case RISCVISD :: SLLW : case RISCVISD :: SRAW : case RISCVISD :: SRLW : case RISCVISD :: DIVW : case RISCVISD :: DIVUW : case RISCVISD :: REMUW : case RISCVISD :: ROLW : case RISCVISD :: RORW : case RISCVISD :: GREVW : case RISCVISD :: GORCW : case RISCVISD :: FSLW : case RISCVISD :: FSRW : case RISCVISD :: SHFLW : case RISCVISD :: UNSHFLW : case RISCVISD :: BCOMPRESSW : case RISCVISD :: BDECOMPRESSW : case RISCVISD :: BFPW : case RISCVISD :: FCVT_W_RV64 : case RISCVISD :: FCVT_WU_RV64 : case RISCVISD :: STRICT_FCVT_W_RV64 : case RISCVISD :: STRICT_FCVT_WU_RV64 : return 33 ; case RISCVISD :: SHFL : case RISCVISD :: UNSHFL : { if ( Op . getValueType ( ) == MVT :: i64 && isa < ConstantSDNode > ( Op . getOperand ( 1 ) ) && ( Op . getConstantOperandVal ( 1 ) & 0x10 ) == 0 ) { unsigned Tmp = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; if ( Tmp > 32 ) return 33 ; } break ; } case RISCVISD :: VMV_X_S : { unsigned XLen = Subtarget . getXLen ( ) ; unsigned EltBits = Op . getOperand ( 0 ) . getScalarValueSizeInBits ( ) ; if ( EltBits <= XLen ) return XLen - EltBits + 1 ; break ; } } return 1 ; } </s>

Determine the number of bits in the operation that are sign bits .


<s> bool BPFAdjustOpt :: insertPassThrough ( ) { for ( auto & Info : PassThroughs ) { auto * CI = BPFCoreSharedInfo :: insertPassThrough ( Mod , Info . UsedInst -> getParent ( ) , Info . Input , Info . UsedInst ) ; Info . UsedInst -> setOperand ( Info . OpIdx , CI ) ; } return ! PassThroughs . empty ( ) ; } </s>

Insert a bpf passthrough builtin function .


<s> void LanaiPassConfig :: addPreSched2 ( ) { addPass ( createLanaiMemAluCombinerPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
void
HexagonAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
if
(
MI
->
isBundle
(
)
)
{
std
::
vector
<
const
MachineInstr
*
>
BundleMIs
;
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
MII
=
MI
;
++
MII
;
unsigned
int
IgnoreCount
=
0
;
while
(
MII
!=
MBB
->
end
(
)
&&
MII
->
isInsideBundle
(
)
)
{
const
MachineInstr
*
MInst
=
MII
;
if
(
MInst
->
getOpcode
(
)
==
TargetOpcode
::
DBG_VALUE
||
MInst
->
getOpcode
(
)
==
TargetOpcode
::
IMPLICIT_DEF
)
{
IgnoreCount
++
;
++
MII
;
continue
;
}
BundleMIs
.
push_back
(
MInst
)
;
++
MII
;
}
unsigned
Size
=
BundleMIs
.
size
(
)
;
assert
(
(
Size
+
IgnoreCount
)
==
MI
->
getBundleSize
(
)
&&
"Corrupt Bundle!"
)
;
for
(
unsigned
Index
=
0
;
Index
<
Size
;
Index
++
)
{
HexagonMCInst
MCI
;
MCI
.
setStartPacket
(
Index
==
0
)
;
MCI
.
setEndPacket
(
Index
==
(
Size
1
)
)
;
HexagonLowerToMC
(
BundleMIs
[
Index
]
,
MCI
,
*
this
)
;
OutStreamer
.
EmitInstruction
(
MCI
)
;
}
}
else
{
HexagonMCInst
MCI
;
if
(
MI
->
getOpcode
(
)
==
Hexagon
::
ENDLOOP0
)
{
MCI
.
setStartPacket
(
true
)
;
MCI
.
setEndPacket
(
true
)
;
}
HexagonLowerToMC
(
MI
,
MCI
,
*
this
)
;
OutStreamer
.
EmitInstruction
(
MCI
)
;
}
return
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void HexagonPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableExpandCondsets ) { Pass * Exp = createHexagonExpandCondsets ( ) ; insertPass ( & RegisterCoalescerID , IdentifyingPassPtr ( Exp ) ) ; } if ( ! DisableStoreWidening ) addPass ( createHexagonStoreWidening ( ) , false ) ; if ( ! DisableHardwareLoops ) addPass ( createHexagonHardwareLoops ( ) , false ) ; } } </s>


<s> enum vlmul_type get_vlmul ( machine_mode mode ) { if ( TARGET_MIN_VLEN == 32 ) return mode_vtype_infos . vlmul_for_min_vlen32 [ mode ] ; else return mode_vtype_infos . vlmul_for_min_vlen64 [ mode ] ; } </s>

Helper function to get VLMUL operand . We always have VLMUL value for all RVV instructions that have VTYPE OP .


"********** Fixing Irreducible Control Flow **********\n"

runOnMachineFunction - Emit the function body .


<s> void ix86_expand_lfloorceil ( rtx op0 , rtx op1 , bool do_floor ) { machine_mode fmode = GET_MODE ( op1 ) ; machine_mode imode = GET_MODE ( op0 ) ; rtx ireg , freg , tmp ; rtx_code_label * label ; ireg = gen_reg_rtx ( imode ) ; expand_fix ( ireg , op1 , 0 ) ; freg = gen_reg_rtx ( fmode ) ; expand_float ( freg , ireg , 0 ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , freg , op1 , ! do_floor ) ; tmp = expand_simple_binop ( imode , do_floor ? MINUS : PLUS , ireg , const1_rtx , NULL_RTX , 0 , OPTAB_DIRECT ) ; emit_move_insn ( ireg , tmp ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( op0 , ireg ) ; } </s>

Expand SSE2 sequence for computing lround from OPERAND1 storing into OPERAND0 .


<s> static tree aarch64_builtin_reciprocal ( tree fndecl ) { machine_mode mode = TYPE_MODE ( TREE_TYPE ( fndecl ) ) ; if ( ! use_rsqrt_p ( mode ) ) return NULL_TREE ; unsigned int code = DECL_MD_FUNCTION_CODE ( fndecl ) ; unsigned int subcode = code >> AARCH64_BUILTIN_SHIFT ; switch ( code & AARCH64_BUILTIN_CLASS ) { case AARCH64_BUILTIN_GENERAL : return aarch64_general_builtin_rsqrt ( subcode ) ; case AARCH64_BUILTIN_SVE : return NULL_TREE ; } gcc_unreachable ( ) ; } </s>

Function to decide when to use the approximate reciprocal square root builtin .


<s> bool Thumb2ITBlock :: runOnMachineFunction ( MachineFunction & Fn ) { const ARMSubtarget & STI = Fn . getSubtarget < ARMSubtarget > ( ) ; if ( ! STI . isThumb2 ( ) ) return false ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= InsertITInstructions ( MBB ) ; if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>


initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned getPointerSize ( ) const { return 8 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> unsigned SIRegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const { unsigned BaseIdx = alignDown ( getMaxWorkGroupSGPRCount ( MF ) , 4 ) - 4 ; unsigned BaseReg ( AMDGPU :: SGPR_32RegClass . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , AMDGPU :: sub0 , & AMDGPU :: SReg_128RegClass ) ; } </s>

Return the end register initially reserved for the scratch buffer in case spilling is needed .


<s> const rvexTargetMachine & getTargetMachine ( ) { return static_cast < const rvexTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> void J2AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { J2MCInstLower InstLower { OutContext , * this } ; const DataLayout & DL = getDataLayout ( ) ; auto MBB = MI -> getParent ( ) ; auto MF = MBB -> getParent ( ) ; auto MII = MI -> getIterator ( ) ; if ( MI -> getOpcode ( ) == J2 :: CONSTPOOL_ENTRY ) { auto LabelID = MI -> getOperand ( 0 ) . getImm ( ) ; auto CPIdx = MI -> getOperand ( 1 ) . getIndex ( ) ; OutStreamer -> EmitLabel ( GetCPISymbol ( LabelID ) ) ; auto & MCPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( DL , MCPE . Val . ConstVal ) ; return ; } do { MCInst TmpInst ; InstLower . Lower ( & * MII , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; ++ MII ; } while ( MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ) ; } </s>


<s>
std
::
string
getNodeLabel
(
const
SCANode
*
N
,
const
SpillCostAnalysisGraph
&
G
)
{
MCGNode
*
mcgNode
=
N
->
getMCGNode
(
)
;
std
::
string
tmp
;
raw_string_ostream
s
(
tmp
)
;
if
(
mcgNode
->
isUnknown
(
)
)
s
<<
"<UNKNOWN-"
<<
*
mcgNode
->
getType
(
)
<<
">"
;
else
{
s
<<
mcgNode
->
getMF
(
)
->
getFunction
(
)
.
getName
(
)
;
}
s
<<
(
N
->
hasCallFreePath
(
)
"* (occ:"
:
" (occ:"
)
<<
N
->
getOccupancy
(
)
<<
", spill:"
<<
N
->
getSpillCost
(
)
<<
")\n"
<<
"[rem:"
<<
N
->
getRemainingOccupancy
(
)
<<
", maxdisp:"
<<
N
->
getMaxDisplacement
(
)
<<
"]"
;
return
s
.
str
(
)
;
}
</s>

Print a DDG node either in concise form ( -ddg-dot-only ) or verbose mode ( -ddg-dot ) .

Patmos
"<UNKNOWN-"
">"
"* (occ:"
" (occ:"
", spill:"
")\n"
"[rem:"
", maxdisp:"
"]"


<s> bool HexagonAsmParser :: parseExpression ( MCExpr const * & Expr ) { llvm :: SmallVector < AsmToken , 4 > Tokens ; MCAsmLexer & Lexer = getLexer ( ) ; bool Done = false ; static char const * Comma = "," ; do { Tokens . emplace_back ( Lexer . getTok ( ) ) ; Lex ( ) ; switch ( Tokens . back ( ) . getKind ( ) ) { case AsmToken :: TokenKind :: Hash : if ( Tokens . size ( ) > 1 ) if ( ( Tokens . end ( ) - 2 ) -> getKind ( ) == AsmToken :: TokenKind :: Plus ) { Tokens . insert ( Tokens . end ( ) - 2 , AsmToken ( AsmToken :: TokenKind :: Comma , Comma ) ) ; Done = true ; } break ; case AsmToken :: TokenKind :: RCurly : case AsmToken :: TokenKind :: EndOfStatement : case AsmToken :: TokenKind :: Eof : Done = true ; break ; default : break ; } } while ( ! Done ) ; while ( ! Tokens . empty ( ) ) { Lexer . UnLex ( Tokens . back ( ) ) ; Tokens . pop_back ( ) ; } return getParser ( ) . parseExpression ( Expr ) ; } </s>


<s>
void
TeakInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
dbgs
(
)
<<
"storeRegToStackSlot\n"
;
dbgs
(
)
<<
"SrcReg: "
<<
SrcReg
<<
"\n"
;
dbgs
(
)
<<
"TargetRegisterClass: "
<<
RC
->
getID
(
)
<<
"\n"
;
dbgs
(
)
<<
"ICC live: "
<<
MBB
.
computeRegisterLiveness
(
TRI
,
Teak
::
ICC
,
I
)
<<
"\n"
;
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
->
hasSuperClassEq
(
&
Teak
::
ABRegsRegClass
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
Teak
::
STORE_REG_TO_STACK_PSEUDO_32
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addImm
(
0
)
;
else
BuildMI
(
MBB
,
I
,
DL
,
get
(
Teak
::
STORE_REG_TO_STACK_PSEUDO_16
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addImm
(
0
)
;
{
}
{
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

Teak
Teak
"storeRegToStackSlot\n"
"SrcReg: "
"\n"
"TargetRegisterClass: "
"\n"
"ICC live: "
Teak::ICC
"\n"
Teak::ABRegsRegClass
Teak::STORE_REG_TO_STACK_PSEUDO_32
0
Teak::STORE_REG_TO_STACK_PSEUDO_16
0


<s> bool SIInstrInfo :: usesConstantBus ( const MachineRegisterInfo & MRI , const MachineOperand & MO , const MCOperandInfo & OpInfo ) const { if ( MO . isImm ( ) ) return ! isInlineConstant ( MO , OpInfo ) ; if ( ! MO . isReg ( ) ) return true ; if ( ! MO . isUse ( ) ) return false ; if ( TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( ! MO . isImplicit ( ) && ( MO . getReg ( ) == AMDGPU :: FLAT_SCR ) ) return true ; if ( ! MO . isImplicit ( ) && MO . getReg ( ) == AMDGPU :: EXEC ) return true ; return ( MO . getReg ( ) == AMDGPU :: VCC || MO . getReg ( ) == AMDGPU :: M0 || ( ! MO . isImplicit ( ) && ( AMDGPU :: SGPR_32RegClass . contains ( MO . getReg ( ) ) || AMDGPU :: SGPR_64RegClass . contains ( MO . getReg ( ) ) ) ) ) ; } </s>

Returns true if this operand uses the constant bus .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Whole Quad Mode"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> StringRef AArch64NamedImmMapper :: toString ( uint32_t Value , bool & Valid ) const { for ( unsigned i = 0 ; i < NumPairs ; ++ i ) { if ( Pairs [ i ] . Value == Value ) { Valid = true ; return Pairs [ i ] . Name ; } } Valid = false ; return StringRef ( ) ; } </s>

Convert to a decimal representation in a string .


<s>
static
bool
rs6000_predict_doloop_p
(
struct
loop
*
loop
)
{
gcc_assert
(
loop
)
;
if
(
loop
->
inner
!=
)
{
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
fprintf
(
dump_file
,
"Predict doloop failure due to"
" loop nesting.\n"
)
;
return
false
;
}
return
true
;
}
</s>

Predict whether the given loop in gimple will be transformed in the RTL doloop_optimize pass .

rs6000
"Predict doloop failure due to"
" loop nesting.\n"


<s> const RV16KSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void CAHPInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static void mips_sim_issue_insn ( struct mips_sim * state , rtx_insn * insn ) { curr_state = state -> dfa_state ; state_transition ( curr_state , insn ) ; state -> insns_left = targetm . sched . variable_issue ( 0 , false , insn , state -> insns_left ) ; mips_sim_insn = insn ; note_stores ( insn , mips_sim_record_set , state ) ; } </s>

Issue instruction INSN in scheduler state STATE . Assume that INSN can issue immediately ( i.e. , that mips_sim_wait_insn has already been called ) .


<s> HexagonNoExtendOperand * HexagonNoExtendOperand :: Create ( MCExpr const * Expr , MCContext & Ctx ) { return new ( Ctx ) HexagonNoExtendOperand ( Expr ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> const unsigned * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned SingleFloatOnlyCalleeSavedRegs [ ] = { Mips :: S0 , Mips :: S1 , Mips :: S2 , Mips :: S3 , Mips :: S4 , Mips :: S5 , Mips :: S6 , Mips :: S7 , Mips :: F20 , Mips :: F21 , Mips :: F22 , Mips :: F23 , Mips :: F24 , Mips :: F25 , Mips :: F26 , Mips :: F27 , Mips :: F28 , Mips :: F29 , Mips :: F30 , 0 } ; static const unsigned BitMode32CalleeSavedRegs [ ] = { Mips :: S0 , Mips :: S1 , Mips :: S2 , Mips :: S3 , Mips :: S4 , Mips :: S5 , Mips :: S6 , Mips :: S7 , Mips :: F20 , Mips :: F22 , Mips :: F24 , Mips :: F26 , Mips :: F28 , Mips :: F30 , Mips :: D10 , Mips :: D11 , Mips :: D12 , Mips :: D13 , Mips :: D14 , Mips :: D15 , 0 } ; if ( Subtarget . isSingleFloat ( ) ) return SingleFloatOnlyCalleeSavedRegs ; else return BitMode32CalleeSavedRegs ; } </s>


<s>
void
SparcMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
unsigned
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
Ctx
.
getAsmInfo
(
)
->
isLittleEndian
(
)
support
::
little
:
support
::
big
)
;
unsigned
tlsOpNo
=
0
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
SP
::
TLS_CALL
:
tlsOpNo
=
1
;
break
;
case
SP
::
TLS_ADDrr
:
case
SP
::
TLS_ADDXrr
:
case
SP
::
TLS_LDrr
:
case
SP
::
TLS_LDXrr
:
tlsOpNo
=
3
;
break
;
}
if
(
tlsOpNo
!=
0
)
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
tlsOpNo
)
;
uint64_t
op
=
getMachineOpValue
(
MI
,
MO
,
Fixups
,
STI
)
;
assert
(
op
==
0
&&
"Unexpected operand value!"
)
;
(
void
)
op
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> BitVector SparcRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( SP :: G2 ) ; Reserved . set ( SP :: G3 ) ; Reserved . set ( SP :: G4 ) ; Reserved . set ( SP :: O6 ) ; Reserved . set ( SP :: I6 ) ; Reserved . set ( SP :: I7 ) ; Reserved . set ( SP :: G0 ) ; Reserved . set ( SP :: G5 ) ; Reserved . set ( SP :: G6 ) ; Reserved . set ( SP :: G7 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static bool expand_vec_perm_vpermt2_vpshub2 ( struct expand_vec_perm_d * d ) { if ( ! TARGET_AVX512BW || ! ( d -> vmode == V64QImode ) ) return false ; if ( d -> testing_p ) return true ; struct expand_vec_perm_d ds [ 2 ] ; rtx rperm [ 128 ] , vperm , target0 , target1 ; unsigned int i , nelt ; machine_mode vmode ; nelt = d -> nelt ; vmode = V64QImode ; for ( i = 0 ; i < 2 ; i ++ ) { ds [ i ] = * d ; ds [ i ] . vmode = V32HImode ; ds [ i ] . nelt = 32 ; ds [ i ] . target = gen_reg_rtx ( V32HImode ) ; ds [ i ] . op0 = gen_lowpart ( V32HImode , d -> op0 ) ; ds [ i ] . op1 = gen_lowpart ( V32HImode , d -> op1 ) ; } for ( i = 0 ; i < nelt ; i ++ ) { ds [ i & 1 ] . perm [ i / 2 ] = d -> perm [ i ] / 2 ; if ( i & 1 ) { rperm [ i ] = constm1_rtx ; rperm [ i + 64 ] = GEN_INT ( ( i & 14 ) + ( d -> perm [ i ] & 1 ) ) ; } else { rperm [ i ] = GEN_INT ( ( i & 14 ) + ( d -> perm [ i ] & 1 ) ) ; rperm [ i + 64 ] = constm1_rtx ; } } bool ok = expand_vec_perm_1 ( & ds [ 0 ] ) ; gcc_assert ( ok ) ; ds [ 0 ] . target = gen_lowpart ( V64QImode , ds [ 0 ] . target ) ; ok = expand_vec_perm_1 ( & ds [ 1 ] ) ; gcc_assert ( ok ) ; ds [ 1 ] . target = gen_lowpart ( V64QImode , ds [ 1 ] . target ) ; vperm = gen_rtx_CONST_VECTOR ( V64QImode , gen_rtvec_v ( 64 , rperm ) ) ; vperm = force_reg ( vmode , vperm ) ; target0 = gen_reg_rtx ( V64QImode ) ; emit_insn ( gen_avx512bw_pshufbv64qi3 ( target0 , ds [ 0 ] . target , vperm ) ) ; vperm = gen_rtx_CONST_VECTOR ( V64QImode , gen_rtvec_v ( 64 , rperm + 64 ) ) ; vperm = force_reg ( vmode , vperm ) ; target1 = gen_reg_rtx ( V64QImode ) ; emit_insn ( gen_avx512bw_pshufbv64qi3 ( target1 , ds [ 1 ] . target , vperm ) ) ; emit_insn ( gen_iorv64qi3 ( d -> target , target0 , target1 ) ) ; return true ; } </s>

Implement arbitrary permutations of two V64QImode operands with 2 vperm [ it ] 2w , 2 vpshufb and one vpor instruction .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
)
Base_Reg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
<<
" Scale"
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
"nul"
" Base.FrameIndex "
" Scale"
"IndexReg "
"nul"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" JT"
" Align"


<s> static bool nios2_plus_large_constant_p ( rtx x ) { return ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && nios2_large_constant_p ( XEXP ( x , 1 ) ) ) ; } </s>

Return true if X is an expression of the form ( PLUS reg large_constant ) .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Cpu0 Long Branch"
;
}
</s>


<s> bool AMDGPUPassConfig :: addPreRegAlloc ( ) { const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createR600VectorRegMerger ( * TM ) ) ; } else { addPass ( createSIFixSGPRCopiesPass ( * TM ) ) ; addPass ( & MachineCSEID ) ; if ( getOptLevel ( ) > CodeGenOpt :: None && ST . loadStoreOptEnabled ( ) ) { initializeSILoadStoreOptimizerPass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( & MachineSchedulerID , & SILoadStoreOptimizerID ) ; } addPass ( createSIShrinkInstructionsPass ( ) ) ; addPass ( createSIFixSGPRLiveRangesPass ( ) ) ; } return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
bool
WaitcntBrackets
::
merge
(
const
WaitcntBrackets
&
Other
)
{
bool
StrictDom
=
false
;
VgprUB
=
std
::
max
(
VgprUB
,
Other
.
VgprUB
)
;
SgprUB
=
std
::
max
(
SgprUB
,
Other
.
SgprUB
)
;
for
(
auto
T
:
inst_counter_types
(
)
)
{
const
unsigned
OldEvents
=
PendingEvents
&
WaitEventMaskForInst
[
T
]
;
const
unsigned
OtherEvents
=
Other
.
PendingEvents
&
WaitEventMaskForInst
[
T
]
;
if
(
OtherEvents
&
~
OldEvents
)
StrictDom
=
true
;
PendingEvents
|=
OtherEvents
;
const
unsigned
MyPending
=
ScoreUBs
[
T
]
ScoreLBs
[
T
]
;
const
unsigned
OtherPending
=
Other
.
ScoreUBs
[
T
]
Other
.
ScoreLBs
[
T
]
;
const
unsigned
NewUB
=
ScoreLBs
[
T
]
+
std
::
max
(
MyPending
,
OtherPending
)
;
if
(
NewUB
<
ScoreLBs
[
T
]
)
report_fatal_error
(
"waitcnt score overflow"
)
;
MergeInfo
M
;
M
.
OldLB
=
ScoreLBs
[
T
]
;
M
.
OtherLB
=
Other
.
ScoreLBs
[
T
]
;
M
.
MyShift
=
NewUB
ScoreUBs
[
T
]
;
M
.
OtherShift
=
NewUB
Other
.
ScoreUBs
[
T
]
;
ScoreUBs
[
T
]
=
NewUB
;
StrictDom
|=
mergeScore
(
M
,
LastFlat
[
T
]
,
Other
.
LastFlat
[
T
]
)
;
bool
RegStrictDom
=
false
;
for
(
int
J
=
0
;
J
<=
VgprUB
;
J
++
)
{
RegStrictDom
|=
mergeScore
(
M
,
VgprScores
[
T
]
[
J
]
,
Other
.
VgprScores
[
T
]
[
J
]
)
;
}
if
(
T
==
VM_CNT
)
{
for
(
int
J
=
0
;
J
<=
VgprUB
;
J
++
)
{
unsigned
char
NewVmemTypes
=
VgprVmemTypes
[
J
]
|
Other
.
VgprVmemTypes
[
J
]
;
RegStrictDom
|=
NewVmemTypes
!=
VgprVmemTypes
[
J
]
;
VgprVmemTypes
[
J
]
=
NewVmemTypes
;
}
}
if
(
T
==
LGKM_CNT
)
{
for
(
int
J
=
0
;
J
<=
SgprUB
;
J
++
)
{
RegStrictDom
|=
mergeScore
(
M
,
SgprScores
[
J
]
,
Other
.
SgprScores
[
J
]
)
;
}
}
if
(
RegStrictDom
)
StrictDom
=
true
;
}
return
StrictDom
;
}
</s>


<s> const Cpu0Subtarget * getSubtargetImpl ( const llvm :: Function & ) const override { return & Subtarget ; } </s>


<s> bool R600InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { return false ; } </s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> MachineSDNode * SITargetLowering :: buildRSRC ( SelectionDAG & DAG , const SDLoc & DL , SDValue Ptr , uint32_t RsrcDword1 , uint64_t RsrcDword2And3 ) const { SDValue PtrLo = DAG . getTargetExtractSubreg ( AMDGPU :: sub0 , DL , MVT :: i32 , Ptr ) ; SDValue PtrHi = DAG . getTargetExtractSubreg ( AMDGPU :: sub1 , DL , MVT :: i32 , Ptr ) ; if ( RsrcDword1 ) { PtrHi = SDValue ( DAG . getMachineNode ( AMDGPU :: S_OR_B32 , DL , MVT :: i32 , PtrHi , DAG . getConstant ( RsrcDword1 , DL , MVT :: i32 ) ) , 0 ) ; } SDValue DataLo = buildSMovImm32 ( DAG , DL , RsrcDword2And3 & UINT64_C ( 0xFFFFFFFF ) ) ; SDValue DataHi = buildSMovImm32 ( DAG , DL , RsrcDword2And3 >> 32 ) ; const SDValue Ops [ ] = { DAG . getTargetConstant ( AMDGPU :: SGPR_128RegClassID , DL , MVT :: i32 ) , PtrLo , DAG . getTargetConstant ( AMDGPU :: sub0 , DL , MVT :: i32 ) , PtrHi , DAG . getTargetConstant ( AMDGPU :: sub1 , DL , MVT :: i32 ) , DataLo , DAG . getTargetConstant ( AMDGPU :: sub2 , DL , MVT :: i32 ) , DataHi , DAG . getTargetConstant ( AMDGPU :: sub3 , DL , MVT :: i32 ) } ; return DAG . getMachineNode ( AMDGPU :: REG_SEQUENCE , DL , MVT :: v4i32 , Ops ) ; } </s>

Return a resource descriptor with the 'Add TID ' bit enabled The TID ( Thread ID ) is multiplied by the stride value ( bits [ 61:48 ] of the resource descriptor ) to create an offset , which is added to the resource pointer .


<s> static bool isShiftedMask ( uint64_t I , uint64_t & Pos , uint64_t & Size ) { if ( ! isShiftedMask_64 ( I ) ) return false ; Size = CountPopulation_64 ( I ) ; Pos = countTrailingZeros ( I ) ; return true ; } </s>

Return true if this APInt value contains a non-empty sequence of ones with the remainder zero .


<s> static int s390_check_qrst_address ( char c , rtx op , bool lit_pool_ok ) { struct s390_address addr ; bool decomposed = false ; if ( ! address_operand ( op , GET_MODE ( op ) ) ) return 0 ; if ( s390_loadrelative_operand_p ( op , NULL , NULL ) ) return 0 ; if ( ! lit_pool_ok ) { if ( ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . literal_pool ) return 0 ; decomposed = true ; } if ( lra_in_progress ) { if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; decomposed = true ; } switch ( c ) { case 'Q' : if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . indx ) return 0 ; if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; break ; case 'R' : if ( TARGET_LONG_DISPLACEMENT ) { if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; } break ; case 'S' : if ( ! decomposed && ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( addr . indx ) return 0 ; break ; case 'T' : break ; default : return 0 ; } return 1 ; } </s>

Return true if the address in OP is valid for constraint letter C if wrapped in a MEM rtx . Set LIT_POOL_OK to true if it literal pool MEMs should be accepted . Only the Q , R , S , T constraint letters are allowed for C .


<s> bool MipsFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"Expected a reg or frame index operand."

Return true if this is a load/store that can be potentially paired/merged .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"WebAssembly Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Assembly Printer"


<s> std :: pair < unsigned , unsigned > LanaiInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF , 0u ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"%<-g%> with %<-mno-apcs-frame%> may not give sensible "

"cannot use %<-mtp=cp15%> with 16-bit Thumb"

"%s only supports non-pic code on M-profile targets with the "

"%s incompatible with %<-mword-relocations%>"

Check any incompatible options that the user has specified .


<s> bool PPCFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; return findScratchRegister ( TmpMBB , false , twoUniqueScratchRegsRequired ( TmpMBB ) ) ; } </s>

Check whether or not the given MBB can be used as a prologue for the target .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Patmos Ensure Alignment"
;
}
</s>


<s> const uint32_t * SIRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold : return CSR_AMDGPU_HighRegs_RegMask ; default : return nullptr ; } } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> const_iterator begin ( ) const { return Blocks . begin ( ) ; } </s>


<s>
unsigned
getReg
(
)
const
{
assert
(
(
Kind
==
k_Register
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> bool UnmangledFuncInfo :: lookup ( StringRef Name , ID & Id ) { static const StringMap < unsigned > Map = buildNameMap ( ) ; auto Loc = Map . find ( Name ) ; if ( Loc != Map . end ( ) ) { Id = toFuncId ( Loc -> second ) ; return true ; } Id = AMDGPULibFunc :: EI_NONE ; return false ; } </s>

This method finds the value with the given Name in the the symbol table .


<s> sbitmap rs6000_components_for_bb ( basic_block bb ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; bitmap in = DF_LIVE_IN ( bb ) ; bitmap gen = & DF_LIVE_BB_INFO ( bb ) -> gen ; bitmap kill = & DF_LIVE_BB_INFO ( bb ) -> kill ; sbitmap components = sbitmap_alloc ( cfun -> machine -> n_components ) ; bitmap_clear ( components ) ; for ( unsigned regno = info -> first_gp_reg_save ; regno < 32 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; for ( unsigned regno = info -> first_fp_reg_save ; regno < 64 ; regno ++ ) if ( bitmap_bit_p ( in , regno ) || bitmap_bit_p ( gen , regno ) || bitmap_bit_p ( kill , regno ) ) bitmap_set_bit ( components , regno ) ; if ( bitmap_bit_p ( in , LR_REGNO ) || bitmap_bit_p ( gen , LR_REGNO ) || bitmap_bit_p ( kill , LR_REGNO ) ) bitmap_set_bit ( components , 0 ) ; if ( bitmap_bit_p ( in , TOC_REGNUM ) || bitmap_bit_p ( gen , TOC_REGNUM ) || bitmap_bit_p ( kill , TOC_REGNUM ) ) bitmap_set_bit ( components , 2 ) ; return components ; } </s>


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const X86Subtarget & STI = MF . getTarget ( ) . getSubtarget < X86Subtarget > ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


"Branch insertion not supported, as MBB info not "

"propagated to OpPhi instructions. Try using "

"Require non-null block for conditional branch"

Insert branch code into the end of the specified MachineBasicBlock .


<s> DecodeStatus AArch64Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & os , raw_ostream & cs ) const { CommentStream = & cs ; uint8_t bytes [ 4 ] ; if ( Region . readBytes ( Address , 4 , ( uint8_t * ) bytes , NULL ) == - 1 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint32_t insn = ( bytes [ 3 ] << 24 ) | ( bytes [ 2 ] << 16 ) | ( bytes [ 1 ] << 8 ) | ( bytes [ 0 ] << 0 ) ; DecodeStatus result = decodeInstruction ( DecoderTableA6432 , MI , insn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = 4 ; return result ; } MI . clear ( ) ; Size = 0 ; return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> static enum attr_type mt_get_attr_type ( rtx complete_insn ) { rtx insn = PATTERN ( complete_insn ) ; if ( JUMP_P ( complete_insn ) ) return TYPE_BRANCH ; if ( CALL_P ( complete_insn ) ) return TYPE_BRANCH ; if ( GET_CODE ( insn ) != SET ) return TYPE_ARITH ; if ( SET_DEST ( insn ) == pc_rtx ) return TYPE_BRANCH ; if ( GET_CODE ( SET_DEST ( insn ) ) == MEM ) return TYPE_STORE ; if ( GET_CODE ( SET_SRC ( insn ) ) == MEM ) return TYPE_LOAD ; return TYPE_ARITH ; } </s>

Given an insn , return whether it 's a memory operation or a branch operation , otherwise return TYPE_ARITH .


<s> static bool isZero ( Register Reg , MachineRegisterInfo & MRI ) { int64_t C ; if ( mi_match ( Reg , MRI , m_ICst ( C ) ) && C == 0 ) return true ; return mi_match ( Reg , MRI , m_Copy ( m_ICst ( C ) ) ) && C == 0 ; } </s>

Return true if the expression is a constant zero .


<s> static void emit_store_conditional ( machine_mode mode , rtx res , rtx mem , rtx val ) { rtx ( * fn ) ( rtx , rtx , rtx ) = NULL ; switch ( mode ) { case QImode : fn = gen_store_conditionalqi ; break ; case HImode : fn = gen_store_conditionalhi ; break ; case SImode : fn = gen_store_conditionalsi ; break ; case DImode : fn = gen_store_conditionaldi ; break ; case TImode : fn = gen_store_conditionalti ; break ; default : gcc_unreachable ( ) ; } if ( PPC405_ERRATUM77 ) emit_insn ( gen_hwsync ( ) ) ; emit_insn ( fn ( res , mem , val ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a store-conditional instruction in MODE .


<s>
void
pa_output_addr_vec
(
rtx
lab
,
rtx
body
)
{
int
idx
,
vlen
=
XVECLEN
(
body
,
0
)
;
if
(
!
TARGET_SOM
)
fputs
(
"\t.align 4\n"
,
asm_out_file
)
;
targetm
.
asm_out
.
internal_label
(
asm_out_file
,
"L"
,
CODE_LABEL_NUMBER
(
lab
)
)
;
if
(
TARGET_GAS
)
fputs
(
"\t.begin_brtab\n"
,
asm_out_file
)
;
for
(
idx
=
0
;
idx
<
vlen
;
idx
++
)
{
ASM_OUTPUT_ADDR_VEC_ELT
(
asm_out_file
,
CODE_LABEL_NUMBER
(
XEXP
(
XVECEXP
(
body
,
0
,
idx
)
,
0
)
)
)
;
}
if
(
TARGET_GAS
)
fputs
(
"\t.end_brtab\n"
,
asm_out_file
)
;
}
</s>


<s> bool PPCFastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { MVT VT ; if ( ! isLoadTypeLegal ( LI -> getType ( ) , VT ) ) return false ; bool IsZExt = false ; switch ( MI -> getOpcode ( ) ) { default : return false ; case PPC :: RLDICL : case PPC :: RLDICL_32_64 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 56 ) || ( VT == MVT :: i16 && MB <= 48 ) || ( VT == MVT :: i32 && MB <= 32 ) ) break ; return false ; } case PPC :: RLWINM : case PPC :: RLWINM8 : { IsZExt = true ; unsigned MB = MI -> getOperand ( 3 ) . getImm ( ) ; if ( ( VT == MVT :: i8 && MB <= 24 ) || ( VT == MVT :: i16 && MB <= 16 ) ) break ; return false ; } case PPC :: EXTSB : case PPC :: EXTSB8 : case PPC :: EXTSB8_32_64 : return false ; case PPC :: EXTSH : case PPC :: EXTSH8 : case PPC :: EXTSH8_32_64 : { if ( VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } case PPC :: EXTSW : case PPC :: EXTSW_32 : case PPC :: EXTSW_32_64 : { if ( VT != MVT :: i32 && VT != MVT :: i16 && VT != MVT :: i8 ) return false ; break ; } } Address Addr ; if ( ! PPCComputeAddress ( LI -> getOperand ( 0 ) , Addr ) ) return false ; Register ResultReg = MI -> getOperand ( 0 ) . getReg ( ) ; if ( ! PPCEmitLoad ( VT , ResultReg , Addr , nullptr , IsZExt , PPCSubTarget -> hasSPE ( ) ? PPC :: EVLDD : PPC :: LFD ) ) return false ; MachineBasicBlock :: iterator I ( MI ) ; removeDeadCode ( I , std :: next ( I ) ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
R600Subtarget
&
ST
=
Fn
.
getSubtarget
<
R600Subtarget
>
(
)
;
const
R600InstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
ST
,
MLI
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
if
(
Packetizer
.
getResourceTracker
(
)
->
getInstrItins
(
)
->
isEmpty
(
)
)
return
false
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
||
MI
->
getOpcode
(
)
==
AMDGPU
::
IMPLICIT_DEF
||
(
MI
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU
&&
!
MI
->
getOperand
(
8
)
.
getImm
(
)
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
*
std
::
prev
(
I
)
,
&
*
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
std
::
prev
(
RegionEnd
)
)
{
RegionEnd
=
std
::
prev
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
&
*
MBB
,
&
*
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> static rtx_insn * emit_nop_after ( int cycles , rtx after ) { rtx_insn * insn ; if ( cycles == 10 ) cycles -- ; gcc_assert ( cycles < 10 ) ; insn = emit_insn_after ( gen_nop_count ( GEN_INT ( cycles ) ) , after ) ; PUT_MODE ( insn , TImode ) ; return insn ; } </s>

Emit a NOP instruction for CYCLES cycles after insn AFTER . Return it .