<s> void LC3bFrameLowering :: emitPrologue ( MachineFunction & MF ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"eliminateCallFramePseudoInstr size too big: "

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void mips_sim_reset ( struct mips_sim * state ) { state -> time = 0 ; state -> insns_left = state -> issue_rate ; memset ( & state -> last_set , 0 , sizeof ( state -> last_set ) ) ; state_reset ( state -> dfa_state ) ; } </s>

Reset STATE to the initial simulation state .


<s> static tree avr_fold_absfx ( tree tval ) { if ( FIXED_CST != TREE_CODE ( tval ) ) return NULL_TREE ; FIXED_VALUE_TYPE fval = TREE_FIXED_CST ( tval ) ; unsigned int bits = GET_MODE_BITSIZE ( fval . mode ) ; double_int ival = fval . data . sext ( bits ) ; if ( ! ival . is_negative ( ) ) return tval ; fval . data = ( ival == double_int :: min_value ( bits , false ) . sext ( bits ) ) ? double_int :: max_value ( bits , false ) : - ival ; return build_fixed ( TREE_TYPE ( tval ) , fval ) ; } </s>

Helper for ` avr_fold_builtin ' that folds absfx ( FIXED_CST ) .


<s> static void arm_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { if ( mode == SImode ) gcc_assert ( ! TARGET_IDIV ) ; machine_mode libval_mode = smallest_mode_for_size ( 2 * GET_MODE_BITSIZE ( mode ) , MODE_INT ) ; rtx libval = emit_library_call_value ( libfunc , NULL_RTX , LCT_CONST , libval_mode , 2 , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) ) ; rtx quotient = simplify_gen_subreg ( mode , libval , libval_mode , 0 ) ; rtx remainder = simplify_gen_subreg ( mode , libval , libval_mode , GET_MODE_SIZE ( mode ) ) ; gcc_assert ( quotient ) ; gcc_assert ( remainder ) ; * quot_p = quotient ; * rem_p = remainder ; } </s>

Generate call to __aeabi_ [ mode ] divmod ( op0 , op1 ) .


<s> bool AMDGPUTargetLowering :: isNarrowingProfitable ( EVT SrcVT , EVT DestVT ) const { return SrcVT . getSizeInBits ( ) > 32 && DestVT . getSizeInBits ( ) == 32 ; } </s>

Return true if it 's profitable to narrow operations of type SrcVT to DestVT .


<s> static rtx loongarch_legitimize_tls_address ( rtx loc ) { rtx dest , tp , tmp , tmp1 , tmp2 , tmp3 ; enum tls_model model = SYMBOL_REF_TLS_MODEL ( loc ) ; rtx_insn * insn ; switch ( model ) { case TLS_MODEL_LOCAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; insn = loongarch_call_tls_get_addr ( loc , SYMBOL_TLSLDM , tmp ) ; emit_libcall_block ( insn , dest , tmp , loc ) ; break ; case TLS_MODEL_GLOBAL_DYNAMIC : tmp = gen_rtx_REG ( Pmode , GP_RETURN ) ; dest = gen_reg_rtx ( Pmode ) ; insn = loongarch_call_tls_get_addr ( loc , SYMBOL_TLSGD , tmp ) ; emit_libcall_block ( insn , dest , tmp , loc ) ; break ; case TLS_MODEL_INITIAL_EXEC : { tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp1 = gen_reg_rtx ( Pmode ) ; dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_EXPLICIT_RELOCS ) { tmp2 = loongarch_unspec_address ( loc , SYMBOL_TLS_IE ) ; tmp3 = gen_reg_rtx ( Pmode ) ; rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( tmp2 ) ) ; high = loongarch_force_temporary ( tmp3 , high ) ; if ( TARGET_CMODEL_EXTREME ) { gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; rtx tmp3 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_low ( Pmode , tmp3 , gen_rtx_REG ( Pmode , 0 ) , tmp2 ) ) ; emit_insn ( gen_lui_h_lo20 ( tmp3 , tmp3 , tmp2 ) ) ; emit_insn ( gen_lui_h_hi12 ( tmp3 , tmp3 , tmp2 ) ) ; emit_move_insn ( tmp1 , gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , high , tmp3 ) ) ) ; } else emit_insn ( gen_ld_from_got ( Pmode , tmp1 , high , tmp2 ) ) ; } else emit_insn ( loongarch_got_load_tls_ie ( tmp1 , loc ) ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; } break ; case TLS_MODEL_LOCAL_EXEC : { tp = gen_rtx_REG ( Pmode , THREAD_POINTER_REGNUM ) ; tmp1 = gen_reg_rtx ( Pmode ) ; dest = gen_reg_rtx ( Pmode ) ; if ( TARGET_EXPLICIT_RELOCS ) { tmp2 = loongarch_unspec_address ( loc , SYMBOL_TLS_LE ) ; tmp3 = gen_reg_rtx ( Pmode ) ; rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( tmp2 ) ) ; high = loongarch_force_temporary ( tmp3 , high ) ; emit_insn ( gen_ori_l_lo12 ( Pmode , tmp1 , high , tmp2 ) ) ; if ( TARGET_CMODEL_EXTREME ) { gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; emit_insn ( gen_lui_h_lo20 ( tmp1 , tmp1 , tmp2 ) ) ; emit_insn ( gen_lui_h_hi12 ( tmp1 , tmp1 , tmp2 ) ) ; } } else emit_insn ( loongarch_got_load_tls_le ( tmp1 , loc ) ) ; emit_insn ( gen_add3_insn ( dest , tmp1 , tp ) ) ; } break ; default : gcc_unreachable ( ) ; } return dest ; } </s>

Generate the code to access LOC , a thread-local SYMBOL_REF , and return its address . The return value will be both a valid address and a valid SET_SRC ( either a REG or a LO_SUM ) .


"********** Abstract Member Accesses **********\n"

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

"Branch offsets outside of the signed 32-bit range not supported"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( * MF ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function & F = MF -> getFunction ( ) ; if ( F . getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F . getCallingConv ( ) == CallingConv :: CFGuard_Check ) { return CSR_Win_AAPCS_CFGuard_Check_SaveList ; } else if ( F . getCallingConv ( ) == CallingConv :: SwiftTail ) { return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftTail_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SwiftTail_SaveList : CSR_AAPCS_SwiftTail_SaveList ) ; } else if ( F . hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F . getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) { if ( STI . isTargetDarwin ( ) ) return CSR_iOS_SwiftError_SaveList ; return UseSplitPush ? CSR_AAPCS_SplitPush_SwiftError_SaveList : CSR_AAPCS_SwiftError_SaveList ; } if ( STI . isTargetDarwin ( ) && F . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ" ARM


<s> std :: pair < unsigned , unsigned > AArch64InstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { const unsigned Mask = AArch64II :: MO_FRAGMENT ; return std :: make_pair ( TF & Mask , TF & ~ Mask ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


<s>
Register
ARMTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"sp"
,
ARM
::
SP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .

ARM
ARM
"sp"
ARM::SP
0
"Invalid register name \""
"\"."


<s> void MipsRegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { MachineInstr & MI = OpdMapper . getMI ( ) ; InstListTy NewInstrs ; MachineFunction * MF = MI . getMF ( ) ; MachineRegisterInfo & MRI = OpdMapper . getMRI ( ) ; const LegalizerInfo & LegInfo = * MF -> getSubtarget ( ) . getLegalizerInfo ( ) ; InstManager NewInstrObserver ( NewInstrs ) ; MachineIRBuilder B ( MI , NewInstrObserver ) ; LegalizerHelper Helper ( * MF , NewInstrObserver , B ) ; LegalizationArtifactCombiner ArtCombiner ( B , MF -> getRegInfo ( ) , LegInfo ) ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : case TargetOpcode :: G_PHI : case TargetOpcode :: G_SELECT : case TargetOpcode :: G_IMPLICIT_DEF : { Helper . narrowScalar ( MI , 0 , LLT :: scalar ( 32 ) ) ; while ( ! NewInstrs . empty ( ) ) { MachineInstr * NewMI = NewInstrs . pop_back_val ( ) ; if ( auto * Unmerge = dyn_cast < GUnmerge > ( NewMI ) ) combineAwayG_UNMERGE_VALUES ( ArtCombiner , * Unmerge , NewInstrObserver ) ; else if ( NewMI -> getOpcode ( ) == TargetOpcode :: G_MERGE_VALUES ) continue ; else setRegBank ( * NewMI , MRI ) ; } return ; } case TargetOpcode :: G_UNMERGE_VALUES : combineAwayG_UNMERGE_VALUES ( ArtCombiner , cast < GUnmerge > ( MI ) , NewInstrObserver ) ; return ; default : break ; } return applyDefaultMapping ( OpdMapper ) ; } </s>


<s> Register RISCVTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return RISCV :: X10 ; } </s>

If a physical register , this returns the register that receives the exception address on entry to an EH pad .


<s> static void microblaze_block_move_straight ( rtx dest , rtx src , HOST_WIDE_INT length ) { HOST_WIDE_INT offset , delta ; unsigned HOST_WIDE_INT bits ; int i ; machine_mode mode ; rtx * regs ; bits = BITS_PER_WORD ; mode = int_mode_for_size ( bits , 0 ) . require ( ) ; delta = bits / BITS_PER_UNIT ; regs = XALLOCAVEC ( rtx , length / delta ) ; for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) { regs [ i ] = gen_reg_rtx ( mode ) ; emit_move_insn ( regs [ i ] , adjust_address ( src , mode , offset ) ) ; } for ( offset = 0 , i = 0 ; offset + delta <= length ; offset += delta , i ++ ) emit_move_insn ( adjust_address ( dest , mode , offset ) , regs [ i ] ) ; if ( offset < length ) { src = adjust_address ( src , BLKmode , offset ) ; dest = adjust_address ( dest , BLKmode , offset ) ; move_by_pieces ( dest , src , length - offset , MIN ( MEM_ALIGN ( src ) , MEM_ALIGN ( dest ) ) , RETURN_BEGIN ) ; } } </s>

Emit straight-line code to move LENGTH bytes from SRC to DEST . Assume that the areas do not overlap .


Create a TOC reference for symbol_ref SYMBOL . If LARGETOC_REG is non-null , use that as the register to put the HIGH value into if register allocation is already done .


<s> bool function_checker :: argument_exists_p ( unsigned int argno ) { gcc_assert ( argno < ( unsigned int ) type_num_arguments ( m_fntype ) ) ; return argno < m_nargs ; } </s>

Return true if argument ARGNO exists . which it might not for erroneous calls . It is safe to wave through checks if this function returns false .


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned MipsSEInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: SW ) || ( Opc == Mips :: SW_P8 ) || ( Opc == Mips :: SD ) || ( Opc == Mips :: SD_P8 ) || ( Opc == Mips :: SWC1 ) || ( Opc == Mips :: SWC1_P8 ) || ( Opc == Mips :: SDC1 ) || ( Opc == Mips :: SDC164 ) || ( Opc == Mips :: SDC164_P8 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void AnalyzeCallOperands ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , const char * Func ) { PreAnalyzeCallOperands ( Outs , Fn , FuncArgs , Func ) ; CCState :: AnalyzeCallOperands ( Outs , Fn ) ; } </s>

AnalyzeCallOperands - Same as above except it takes vectors of types and argument flags .


<s> bool SystemZInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability ) const { if ( MBB . succ_empty ( ) && Probability < BranchProbability ( 1 , 8 ) ) return false ; return NumCycles == 1 ; } </s>


<s> TargetLoweringBase :: LegalizeTypeAction NVPTXTargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT . getVectorNumElements ( ) != 1 && VT . getScalarType ( ) == MVT :: i1 ) return TypeSplitVector ; if ( VT == MVT :: v2f16 ) return TypeLegal ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> int HexagonMCInst :: getMaxValue ( void ) const { const uint64_t F = MCID -> TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return ~ ( - 1U << ( bits - 1 ) ) ; else return ~ ( - 1U << bits ) ; } </s>

Return the maximal unsigned value possible given these KnownBits .

Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1U 1 1U


<s> bool m68k_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) { return ( to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ) ; } </s>

Worker function for TARGET_CAN_ELIMINATE .


<s> bool HexagonPassConfig :: addPostRegAlloc ( ) { addPass ( createHexagonCFGOptimizer ( getHexagonTargetMachine ( ) ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"Instruction should be in a basic block!"

"Generic instruction has unexpected implicit operands\n"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOStore
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSTRspi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
ARM::tSTRspi
0


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
const
ARMSubtarget
&
ST
=
static_cast
<
const
ARMSubtarget
&
>
(
mf
.
getSubtarget
(
)
)
;
if
(
!
ST
.
hasLOB
(
)
)
return
false
;
MF
=
&
mf
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
->
getName
(
)
<<
" ------------- \n"
)
;
MLI
=
&
getAnalysis
<
MachineLoopInfo
>
(
)
;
RDA
=
&
getAnalysis
<
ReachingDefAnalysis
>
(
)
;
MF
->
getProperties
(
)
.
set
(
MachineFunctionProperties
::
Property
::
TracksLiveness
)
;
MRI
=
&
MF
->
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
ST
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
*
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
->
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
*
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
Changed
|=
RevertNonLoops
(
)
;
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

ARM
ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s>
ScheduleHazardRecognizer
::
HazardType
HexagonHazardRecognizer
::
getHazardType
(
SUnit
*
SU
,
int
stalls
)
{
MachineInstr
*
MI
=
SU
->
getInstr
(
)
;
if
(
!
MI
||
TII
->
isZeroCost
(
MI
->
getOpcode
(
)
)
)
return
NoHazard
;
if
(
!
Resources
->
canReserveResources
(
*
MI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"*** Hazard in cycle "
<<
PacketNum
<<
", "
<<
*
MI
)
;
HazardType
RetVal
=
Hazard
;
if
(
TII
->
mayBeNewStore
(
*
MI
)
)
{
MachineOperand
&
MO
=
MI
->
getOperand
(
MI
->
getNumOperands
(
)
1
)
;
if
(
!
MO
.
isReg
(
)
||
RegDefs
.
count
(
MO
.
getReg
(
)
)
==
0
)
return
Hazard
;
MachineFunction
*
MF
=
MI
->
getParent
(
)
->
getParent
(
)
;
MachineInstr
*
NewMI
=
MF
->
CreateMachineInstr
(
TII
->
get
(
TII
->
getDotNewOp
(
*
MI
)
)
,
MI
->
getDebugLoc
(
)
)
;
if
(
Resources
->
canReserveResources
(
*
NewMI
)
)
RetVal
=
NoHazard
;
LLVM_DEBUG
(
dbgs
(
)
<<
"*** Try .new version? "
<<
(
RetVal
==
NoHazard
)
<<
"\n"
)
;
MF
->
deleteMachineInstr
(
NewMI
)
;
}
return
RetVal
;
}
if
(
SU
==
UsesDotCur
&&
DotCurPNum
!=
(
int
)
PacketNum
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"*** .cur Hazard in cycle "
<<
PacketNum
<<
", "
<<
*
MI
)
;
return
Hazard
;
}
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .

Hexagon
Hexagon
"*** Hazard in cycle "
", "
1
0
"*** Try .new version? "
"\n"
"*** .cur Hazard in cycle "
", "


<s> unsigned getNumFixupKinds ( ) const override { return AArch64 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> unsigned X86InstrInfo :: getOpcodeAfterMemoryUnfold ( unsigned Opc , bool UnfoldLoad , bool UnfoldStore ) const { DenseMap < unsigned * , std :: pair < unsigned , unsigned > > :: iterator I = MemOp2RegOpTable . find ( ( unsigned * ) Opc ) ; if ( I == MemOp2RegOpTable . end ( ) ) return 0 ; bool FoldedLoad = I -> second . second & ( 1 << 4 ) ; bool FoldedStore = I -> second . second & ( 1 << 5 ) ; if ( UnfoldLoad && ! FoldedLoad ) return 0 ; if ( UnfoldStore && ! FoldedStore ) return 0 ; return I -> second . first ; } </s>

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode .


<s>
virtual
unsigned
getFrameRegister
(
const
MachineFunction
&
MF
)
const
{
llvm_unreachable
(
"PTX does not have a frame register"
)
;
}
</s>

PTX
"PTX does not have a frame register"


<s> static rtx rs6000_emit_vector_compare ( enum rtx_code rcode , rtx op0 , rtx op1 , machine_mode dmode ) { rtx mask ; bool swap_operands = false ; bool try_again = false ; gcc_assert ( VECTOR_UNIT_ALTIVEC_OR_VSX_P ( dmode ) ) ; gcc_assert ( GET_MODE ( op0 ) == GET_MODE ( op1 ) ) ; mask = rs6000_emit_vector_compare_inner ( rcode , op0 , op1 ) ; if ( mask ) return mask ; switch ( rcode ) { case LT : rcode = GT ; swap_operands = true ; try_again = true ; break ; case LTU : rcode = GTU ; swap_operands = true ; try_again = true ; break ; case NE : case UNLE : case UNLT : case UNGE : case UNGT : { enum rtx_code rev_code ; enum insn_code nor_code ; rtx mask2 ; rev_code = reverse_condition_maybe_unordered ( rcode ) ; if ( rev_code == UNKNOWN ) return NULL_RTX ; nor_code = optab_handler ( one_cmpl_optab , dmode ) ; if ( nor_code == CODE_FOR_nothing ) return NULL_RTX ; mask2 = rs6000_emit_vector_compare ( rev_code , op0 , op1 , dmode ) ; if ( ! mask2 ) return NULL_RTX ; mask = gen_reg_rtx ( dmode ) ; emit_insn ( GEN_FCN ( nor_code ) ( mask , mask2 ) ) ; return mask ; } break ; case GE : case GEU : case LE : case LEU : { rtx c_rtx , eq_rtx ; enum insn_code ior_code ; enum rtx_code new_code ; switch ( rcode ) { case GE : new_code = GT ; break ; case GEU : new_code = GTU ; break ; case LE : new_code = LT ; break ; case LEU : new_code = LTU ; break ; default : gcc_unreachable ( ) ; } ior_code = optab_handler ( ior_optab , dmode ) ; if ( ior_code == CODE_FOR_nothing ) return NULL_RTX ; c_rtx = rs6000_emit_vector_compare ( new_code , op0 , op1 , dmode ) ; if ( ! c_rtx ) return NULL_RTX ; eq_rtx = rs6000_emit_vector_compare ( EQ , op0 , op1 , dmode ) ; if ( ! eq_rtx ) return NULL_RTX ; mask = gen_reg_rtx ( dmode ) ; emit_insn ( GEN_FCN ( ior_code ) ( mask , c_rtx , eq_rtx ) ) ; return mask ; } break ; default : return NULL_RTX ; } if ( try_again ) { if ( swap_operands ) std :: swap ( op0 , op1 ) ; mask = rs6000_emit_vector_compare_inner ( rcode , op0 , op1 ) ; if ( mask ) return mask ; } return NULL_RTX ; } </s>

Emit vector compare for operands OP0 and OP1 using code RCODE . DMODE is expected destination mode . This is a recursive function .


<s> bool RISCVRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return false ; auto FII = FixedCSRFIMap . find ( Reg ) ; if ( FII == FixedCSRFIMap . end ( ) ) return false ; FrameIdx = FII -> second ; return true ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .


<s>
unsigned
getReg
(
)
const
{
assert
(
isReg
(
)
&&
"Wrong CountValue accessor"
)
;
return
Contents
.
R
.
Reg
;
}
</s>

Returns the register associated with this edge .


<s> bool AArch64TargetLowering :: shouldLocalize ( const MachineInstr & MI , const TargetTransformInfo * TTI ) const { if ( MI . getOpcode ( ) == TargetOpcode :: G_GLOBAL_VALUE ) { const GlobalValue & GV = * MI . getOperand ( 1 ) . getGlobal ( ) ; if ( GV . isThreadLocal ( ) && Subtarget -> isTargetMachO ( ) ) return false ; } return TargetLoweringBase :: shouldLocalize ( MI , TTI ) ; } </s>

Check whether or not MI needs to be moved close to its uses .


<s> static void ix86_emit_save_regs ( void ) { unsigned int regno ; rtx insn ; for ( regno = FIRST_PSEUDO_REGISTER ; regno -- > 0 ; ) if ( ix86_save_reg ( regno , true ) ) { insn = emit_insn ( gen_push ( gen_rtx_REG ( Pmode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit code to save registers in the prologue .


<s> bool AArch64TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return true ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> StringRef PTXInstPrinter :: getOpcodeName ( unsigned Opcode ) const { return getInstructionName ( Opcode ) ; } </s>

Return a string representation for an opcode .


<s>
void
unicosmk_output_common
(
FILE
*
file
,
const
char
*
name
,
int
size
,
int
align
)
{
tree
name_tree
;
printf
(
"T3E__: common %s\n"
,
name
)
;
common_section
(
)
;
fputs
(
"\t.endp\n\n\t.psect "
,
file
)
;
assemble_name
(
file
,
name
)
;
fprintf
(
file
,
",%d,common\n"
,
floor_log2
(
align
/
BITS_PER_UNIT
)
)
;
fprintf
(
file
,
"\t.byte\t0:%d\n"
,
size
)
;
name_tree
=
get_identifier
(
name
)
;
TREE_ASM_WRITTEN
(
name_tree
)
=
1
;
}
</s>

Output the definition of a common variable .

alpha
"T3E__: common %s\n"
"\t.endp\n\n\t.psect "
",%d,common\n"
"\t.byte\t0:%d\n"
1


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { assert ( 0 && "UNIMP" ) ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void ScheduleDAGPostRA :: finalizeSchedule ( ) { ScheduleDAGInstrs :: finalizeSchedule ( ) ; finalizeBundles ( MF ) ; } </s>

After the schedule has been formed , call this function to combine the instructions from the different stages/cycles .


Output a dbCC ; jCC sequence . Note we do not handle the floating point version of this sequence ( Fdbcc ) . We also do not handle alternative conditions when CC_NO_OVERFLOW is set . It is assumed that valid_dbcc_comparison_p and flags_in_68881 will kick those out before we get here .


<s> unsigned X86InstrInfo :: getUndefRegClearance ( const MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) && hasUndefRegUpdate ( MI . getOpcode ( ) , OpNum ) ) return UndefRegClearance ; return 0 ; } </s>

Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads .


<s> Value * X86TargetLowering :: getSDagStackGuard ( const Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) return M . getGlobalVariable ( "__security_cookie" ) ; return TargetLowering :: getSDagStackGuard ( M ) ; } </s>

Return the variable that 's previously inserted by insertSSPDeclarations , if any , otherwise return nullptr .


<s> static void mips_sim_reset ( struct mips_sim * state ) { curr_state = state -> dfa_state ; state -> time = 0 ; state -> insns_left = state -> issue_rate ; memset ( & state -> last_set , 0 , sizeof ( state -> last_set ) ) ; state_reset ( curr_state ) ; targetm . sched . init ( 0 , false , 0 ) ; advance_state ( curr_state ) ; } </s>

Reset STATE to the initial simulation state .


"*** BPF simplify patchable insts pass ***\n\n"

Initialize the strategy after building the DAG for a new region .


<s> void gen_conditional_branch ( rtx operands [ ] , machine_mode mode ) { enum rtx_code test_code = GET_CODE ( operands [ 0 ] ) ; rtx cmp0 = operands [ 1 ] ; rtx cmp1 = operands [ 2 ] ; rtx reg ; int invert ; rtx label1 , label2 ; invert = 0 ; reg = gen_int_relational ( test_code , NULL_RTX , cmp0 , cmp1 , & invert ) ; if ( reg ) { cmp0 = reg ; cmp1 = const0_rtx ; test_code = NE ; } else if ( GET_CODE ( cmp1 ) == CONST_INT && INTVAL ( cmp1 ) != 0 ) cmp1 = force_reg ( mode , cmp1 ) ; label1 = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; label2 = pc_rtx ; if ( invert ) { label2 = label1 ; label1 = pc_rtx ; } emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0 , cmp1 ) , label1 , label2 ) ) ) ; } </s>

Emit the common code for doing conditional branches . operand [ 0 ] is the label to jump to . The comparison operands are saved away by cmp { si , di , sf , df } .


<s> static int ia64_function_arg_words ( tree type , enum machine_mode mode ) { int words ; if ( mode == BLKmode ) words = int_size_in_bytes ( type ) ; else words = GET_MODE_SIZE ( mode ) ; return ( words + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Return the number of words required to hold a quantity of TYPE and MODE when passed as an argument .


<s> static rtx generate_set_vrsave ( rtx reg , rs6000_stack_t * info , int epiloguep ) { int nclobs , i ; rtx insn , clobs [ TOTAL_ALTIVEC_REGS + 1 ] ; rtx vrsave = gen_rtx_REG ( SImode , VRSAVE_REGNO ) ; clobs [ 0 ] = gen_rtx_SET ( vrsave , gen_rtx_UNSPEC_VOLATILE ( SImode , gen_rtvec ( 2 , reg , vrsave ) , UNSPECV_SET_VRSAVE ) ) ; nclobs = 1 ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( info -> vrsave_mask & ALTIVEC_REG_BIT ( i ) ) { if ( ! epiloguep || call_used_regs [ i ] ) clobs [ nclobs ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( V4SImode , i ) ) ; else { rtx reg = gen_rtx_REG ( V4SImode , i ) ; clobs [ nclobs ++ ] = gen_rtx_SET ( reg , gen_rtx_UNSPEC ( V4SImode , gen_rtvec ( 1 , reg ) , 27 ) ) ; } } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nclobs ) ) ; for ( i = 0 ; i < nclobs ; ++ i ) XVECEXP ( insn , 0 , i ) = clobs [ i ] ; return insn ; } </s>

Returns an insn that has a vrsave set operation with the appropriate CLOBBERs .


<s> bool AMDGPUUnifyMetadata :: runOnModule ( Module & M ) { return unifyMetadataImpl ( M ) ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> static HOST_WIDE_INT cris_static_rtx_alignment ( machine_mode mode ) { return MAX ( cris_preferred_minimum_alignment ( ) , GET_MODE_ALIGNMENT ( mode ) ) ; } </s>


<s> HOST_WIDE_INT rs6000_builtin_mask_calculate ( void ) { return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : 0 ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : 0 ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : 0 ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : 0 ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : 0 ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : 0 ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : 0 ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : 0 ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : 0 ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : 0 ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : 0 ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : 0 ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : 0 ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : 0 ) | ( ( TARGET_POWERPC64 ) ? RS6000_BTM_POWERPC64 : 0 ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : 0 ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : 0 ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : 0 ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : 0 ) | ( ( TARGET_LONG_DOUBLE_128 && TARGET_HARD_FLOAT && ! TARGET_IEEEQUAD ) ? RS6000_BTM_LDBL128 : 0 ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : 0 ) | ( ( TARGET_FLOAT128_HW ) ? RS6000_BTM_FLOAT128_HW : 0 ) | ( ( TARGET_MMA ) ? RS6000_BTM_MMA : 0 ) | ( ( TARGET_POWER10 ) ? RS6000_BTM_P10 : 0 ) ) ; } </s>

Return the builtin mask of the various options used that could affect which builtins were used . In the past we used target_flags , but we 've run out of bits , and some options like PAIRED are no longer in target_flags .


<s> bool s390_split_ok_p ( rtx dst , rtx src , machine_mode mode , int first_subword ) { if ( FP_REG_P ( src ) || FP_REG_P ( dst ) ) return false ; if ( s_operand ( src , mode ) || s_operand ( dst , mode ) ) return false ; if ( ( GET_CODE ( src ) == MEM && ! offsettable_memref_p ( src ) ) || ( GET_CODE ( dst ) == MEM && ! offsettable_memref_p ( dst ) ) ) return false ; if ( register_operand ( dst , mode ) ) { rtx subreg = operand_subword ( dst , first_subword , 0 , mode ) ; if ( reg_overlap_mentioned_p ( subreg , src ) ) return false ; } return true ; } </s>

Check whether we can ( and want to ) split a double-word move in mode MODE from SRC to DST into two single-word moves , moving the subword FIRST_SUBWORD first .


<s> bool FixAllFDIVSQRT :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < SparcSubtarget > ( ) ; const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc DL = DebugLoc ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) { for ( auto MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == SP :: FSQRTD || Opcode == SP :: FDIVD ) { for ( int InsertedCount = 0 ; InsertedCount < 5 ; InsertedCount ++ ) BuildMI ( MBB , MBBI , DL , TII . get ( SP :: NOP ) ) ; MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; for ( int InsertedCount = 0 ; InsertedCount < 28 ; InsertedCount ++ ) BuildMI ( MBB , NMBBI , DL , TII . get ( SP :: NOP ) ) ; Modified = true ; } } } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> int ix86_attr_length_address_default ( rtx_insn * insn ) { int i ; if ( get_attr_type ( insn ) == TYPE_LEA ) { rtx set = PATTERN ( insn ) , addr ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , 0 , 0 ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; addr = SET_SRC ( set ) ; return memory_address_length ( addr , true ) ; } extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( MEM_P ( recog_data . operand [ i ] ) ) { constrain_operands_cached ( insn , reload_completed ) ; if ( which_alternative != - 1 ) { const char * constraints = recog_data . constraints [ i ] ; int alt = which_alternative ; while ( * constraints == '=' || * constraints == '+' ) constraints ++ ; while ( alt -- > 0 ) while ( * constraints ++ != ',' ) ; if ( * constraints == 'X' ) continue ; } return memory_address_length ( XEXP ( recog_data . operand [ i ] , 0 ) , false ) ; } return 0 ; } </s>

Compute default value for `` length_address '' attribute .


<s>
SUnit
*
R600SchedStrategy
::
pickNode
(
bool
&
IsTopNode
)
{
SUnit
*
SU
=
0
;
IsTopNode
=
true
;
NextInstKind
=
IDOther
;
bool
AllowSwitchToAlu
=
(
CurInstKind
==
IDOther
)
||
(
CurEmitted
>
InstKindLimit
[
CurInstKind
]
)
||
(
Available
[
CurInstKind
]
->
empty
(
)
)
;
bool
AllowSwitchFromAlu
=
(
CurEmitted
>
InstKindLimit
[
CurInstKind
]
)
&&
(
!
Available
[
IDFetch
]
->
empty
(
)
||
!
Available
[
IDOther
]
->
empty
(
)
)
;
if
(
(
AllowSwitchToAlu
&&
CurInstKind
!=
IDAlu
)
||
(
!
AllowSwitchFromAlu
&&
CurInstKind
==
IDAlu
)
)
{
SU
=
pickAlu
(
)
;
if
(
SU
)
{
if
(
CurEmitted
>
InstKindLimit
[
IDAlu
]
)
CurEmitted
=
0
;
NextInstKind
=
IDAlu
;
}
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDFetch
)
;
if
(
SU
)
NextInstKind
=
IDFetch
;
}
if
(
!
SU
)
{
SU
=
pickOther
(
IDOther
)
;
if
(
SU
)
NextInstKind
=
IDOther
;
}
DEBUG
(
if
(
SU
)
{
dbgs
(
)
<<
"picked node: "
;
SU
->
dump
(
DAG
)
;
}
else
{
dbgs
(
)
<<
"NO NODE "
;
for
(
int
i
=
0
;
i
<
IDLast
;
++
i
)
{
Available
[
i
]
->
dump
(
)
;
Pending
[
i
]
->
dump
(
)
;
}
for
(
unsigned
i
=
0
;
i
<
DAG
->
SUnits
.
size
(
)
;
i
++
)
{
const
SUnit
&
S
=
DAG
->
SUnits
[
i
]
;
if
(
!
S
.
isScheduled
)
S
.
dump
(
DAG
)
;
}
}
</s>

Pick the next node to schedule , or return NULL .


<s> bool AArch64TTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; return ( CallerBits & CalleeBits ) == CalleeBits ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> bool isScalarFPTypeInSSEReg ( EVT VT ) const { return ( VT == MVT :: f64 && X86ScalarSSEf64 ) || ( VT == MVT :: f32 && X86ScalarSSEf32 ) || ( VT == MVT :: f16 && X86ScalarSSEf16 ) ; } </s>

Return true if the specified scalar FP type is computed in an SSE register , not on the X87 floating point stack .


<s> static bool alpha_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { return mode == TFmode || mode == TCmode ; } </s>

Return true if TYPE should be passed by invisible reference .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ! getARMSubtarget ( ) . isTargetNaCl ( ) && TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createGlobalMergePass ( TM ) ) ; return false ; } </s>


<s> int main ( void ) { for ( const avr_mcu_t * mcu = avr_mcu_types ; mcu -> name ; mcu ++ ) print_mcu ( mcu ) ; return EXIT_SUCCESS ; } </s>

Main program to convert flat files into built-in initialization code .


<s> static struct machine_function * m32c_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

The usual ; we set up our machine_function data .


Hook to validate the current # pragma GCC target and set the arch custom mode state . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s> static void ix86_emit_restore_regs_using_mov ( HOST_WIDE_INT cfa_offset , bool maybe_eh_return ) { struct machine_function * m = cfun -> machine ; unsigned int regno ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( GENERAL_REGNO_P ( regno ) && ix86_save_reg ( regno , maybe_eh_return , true ) ) { rtx reg = gen_rtx_REG ( word_mode , regno ) ; rtx mem ; rtx_insn * insn ; mem = choose_baseaddr ( cfa_offset , NULL ) ; mem = gen_frame_mem ( word_mode , mem ) ; insn = emit_move_insn ( reg , mem ) ; if ( m -> fs . cfa_reg == crtl -> drap_reg && regno == REGNO ( crtl -> drap_reg ) ) { add_reg_note ( insn , REG_CFA_DEF_CFA , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; m -> fs . drap_valid = true ; } else ix86_add_cfa_restore_note ( NULL , reg , cfa_offset ) ; cfa_offset -= UNITS_PER_WORD ; } } </s>

Emit code to restore saved registers using MOV insns . First register is restored from POINTER + OFFSET .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> TargetIRAnalysis ARMBaseTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( ARMTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> virtual const LC3bRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned ARMBaseInstrInfo :: getNumLDMAddresses ( const MachineInstr * MI ) const { unsigned Size = 0 ; for ( MachineInstr :: mmo_iterator I = MI -> memoperands_begin ( ) , E = MI -> memoperands_end ( ) ; I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ; } return Size / 4 ; } </s>

Get the number of addresses by LDM or VLDM or zero for unknown .


<s> bool ARMFrameInfo :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return hasReservedCallFrame ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> bool MipsAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t i = 0 , e = Count % 4 ; i != e ; ++ i ) OW -> Write8 ( 0 ) ; uint64_t NumNops = Count / 4 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) OW -> Write32 ( 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> inline void classify_registers ( const_tree , HOST_WIDE_INT bitpos , bool fp , classify_data_t * data ) { if ( fp ) { data -> fp_regs = true ; if ( bitpos < BITS_PER_WORD ) data -> fp_regs_in_first_word = true ; } } </s>

A subroutine of function_arg_slotno . Classify the field .


"Can't break virtual register dependencies."

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s> bool hasModifiers ( ) const { assert ( isRegKind ( ) ) ; return Reg . Modifiers != - 1 ; } </s>

Return true if this instruction has any modifiers .


<s> static void mips_code_end ( void ) { mips_finish_stub ( & mips16_rdhwr_stub ) ; mips_finish_stub ( & mips16_get_fcsr_stub ) ; mips_finish_stub ( & mips16_set_fcsr_stub ) ; } </s>


<s> bool avr_popcount_each_byte ( rtx xval , int n_bytes , int pop_mask ) { machine_mode mode = GET_MODE ( xval ) ; if ( VOIDmode == mode ) mode = SImode ; for ( int i = 0 ; i < n_bytes ; i ++ ) { rtx xval8 = simplify_gen_subreg ( QImode , xval , mode , i ) ; unsigned int val8 = UINTVAL ( xval8 ) & GET_MODE_MASK ( QImode ) ; if ( 0 == ( pop_mask & ( 1 << popcount_hwi ( val8 ) ) ) ) return false ; } return true ; } </s>

Constraint helper function . XVAL is a CONST_INT or a CONST_DOUBLE . Return true if the least significant N_BYTES bytes of XVAL all have a popcount in POP_MASK and false , otherwise . POP_MASK represents a subset of integers which contains an integer N iff bit N of POP_MASK is set .


<s> static HOST_WIDE_INT s390_vector_alignment ( const_tree type ) { tree size = TYPE_SIZE ( type ) ; if ( ! TARGET_VX_ABI ) return default_vector_alignment ( type ) ; if ( TYPE_USER_ALIGN ( type ) ) return TYPE_ALIGN ( type ) ; if ( tree_fits_uhwi_p ( size ) && tree_to_uhwi ( size ) < BIGGEST_ALIGNMENT ) return tree_to_uhwi ( size ) ; return BIGGEST_ALIGNMENT ; } </s>

The vector ABI requires vector types to be aligned on an 8 byte boundary ( our stack alignment ) . However , we allow this to be overriden by the user , while this definitely breaks the ABI .


<s> bool AArch64LoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; Subtarget = & static_cast < const AArch64Subtarget & > ( Fn . getSubtarget ( ) ) ; TII = static_cast < const AArch64InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; TRI = Subtarget -> getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; ModifiedRegUnits . init ( * TRI ) ; UsedRegUnits . init ( * TRI ) ; bool Modified = false ; bool enableNarrowZeroStOpt = ! Subtarget -> requiresStrictAlign ( ) ; for ( auto & MBB : Fn ) Modified |= optimizeBlock ( MBB , enableNarrowZeroStOpt ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> static tree rs6000_md_asm_clobbers ( tree , tree , tree clobbers ) { tree s = build_string ( strlen ( reg_names [ CA_REGNO ] ) , reg_names [ CA_REGNO ] ) ; return tree_cons ( NULL_TREE , s , clobbers ) ; } </s>

Implement TARGET_MD_ASM_CLOBBERS . All asm statements are considered to clobber the XER [ CA ] bit because clobbering that bit without telling the compiler worked just fine with versions of GCC before GCC 5 , and breaking a lot of older code in ways that are hard to track down is not such a great idea .


<s> HOST_WIDE_INT ix86_initial_elimination_offset ( int from , int to ) { struct ix86_frame frame ; ix86_compute_frame_layout ( & frame ) ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset ; else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset - frame . frame_pointer_offset ; else { gcc_assert ( to == STACK_POINTER_REGNUM ) ; if ( from == ARG_POINTER_REGNUM ) return frame . stack_pointer_offset ; gcc_assert ( from == FRAME_POINTER_REGNUM ) ; return frame . stack_pointer_offset - frame . frame_pointer_offset ; } } </s>

Return the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> iterator begin ( ) const { return Masks . begin ( ) ; } </s>


<s> bool bfin_dsp_memref_p ( rtx x ) { if ( ! MEM_P ( x ) ) return false ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == PRE_DEC ) x = XEXP ( x , 0 ) ; return IREG_P ( x ) ; } </s>

Returns true if X is a memory reference using an I register .


<s> static void arm_emit_vfp_multi_reg_pop ( int first_reg , int num_regs , rtx base_reg ) { int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; gcc_assert ( num_regs && num_regs <= 32 ) ; if ( num_regs == 2 && ! arm_arch6 ) { if ( first_reg == 15 ) first_reg -- ; num_regs ++ ; } if ( num_regs > 16 ) { arm_emit_vfp_multi_reg_pop ( first_reg , 16 , base_reg ) ; arm_emit_vfp_multi_reg_pop ( first_reg + 16 , num_regs - 16 , base_reg ) ; return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; tmp = gen_rtx_SET ( base_reg , plus_constant ( Pmode , base_reg , 8 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 0 ) = tmp ; for ( j = 0 , i = first_reg ; j < num_regs ; i += 2 ) { reg = gen_rtx_REG ( DFmode , i ) ; tmp = gen_rtx_SET ( reg , gen_frame_mem ( DFmode , plus_constant ( Pmode , base_reg , 8 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + 1 ) = tmp ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( TARGET_VFP && REGNO ( base_reg ) == IP_REGNUM ) { RTX_FRAME_RELATED_P ( par ) = 1 ; add_reg_note ( par , REG_CFA_DEF_CFA , hard_frame_pointer_rtx ) ; } else arm_add_cfa_adjust_cfa_note ( par , 2 * UNITS_PER_WORD * num_regs , base_reg , base_reg ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi of NUM_REGS consecutive VFP regs , starting at FIRST_REG . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


"Memory Intrinsic results: call to builtin function "

"with wrong signature, from/to mismatch"

optimizeCall - Take the given call instruction and return a more optimal value to replace the instruction with or 0 if a more optimal form ca n't be found .


<s> int romp_sa_size ( ) { int size ; int i ; size = 4 + 4 + 1 + ( 16 - first_reg_to_save ( ) ) ; for ( i = 2 + ( TARGET_FP_REGS != 0 ) ; i <= 7 ; i ++ ) if ( regs_ever_live [ i + 17 ] ) { size += 18 ; break ; } return size * 4 ; } </s>

Compute the size of the save area in the stack , including the space for the first four incoming arguments .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bool Changed = false ; if ( MF . size ( ) < 2 ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ; if ( processBlock ( B ) ) Changed = true ; } return Changed ; } </s>


<s> bool SparcAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'r' : break ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void sparc_split_reg_mem ( rtx dest , rtx src , machine_mode mode ) { rtx high_part = gen_highpart ( mode , dest ) ; rtx low_part = gen_lowpart ( mode , dest ) ; rtx word0 = adjust_address ( src , mode , 0 ) ; rtx word1 = adjust_address ( src , mode , 4 ) ; if ( reg_overlap_mentioned_p ( high_part , word1 ) ) { emit_move_insn_1 ( low_part , word1 ) ; emit_move_insn_1 ( high_part , word0 ) ; } else { emit_move_insn_1 ( high_part , word0 ) ; emit_move_insn_1 ( low_part , word1 ) ; } } </s>

Split a REG < -- MEM move into a pair of moves in MODE .


<s> static tree ATTRIBUTE_UNUSED ix86_stack_protect_fail ( void ) { return TARGET_64BIT ? default_external_stack_protect_fail ( ) : default_hidden_stack_protect_fail ( ) ; } </s>

For 32-bit code we can save PIC register setup by using __stack_chk_fail_local hidden function instead of calling __stack_chk_fail directly . 64-bit code does n't need to setup any PIC register , so it is better to call __stack_chk_fail directly .


<s> void M88kInstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( M88k :: ORrr ) , M88k :: R0 ) . addReg ( M88k :: R0 ) . addReg ( M88k :: R0 ) ; } </s>

Insert a noop into the instruction stream at the specified point .


<s> static void rs6000_assemble_visibility ( tree decl , int vis ) { if ( DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS && TREE_CODE ( decl ) == FUNCTION_DECL ) { static const char * const visibility_types [ ] = { NULL , "internal" , "hidden" , "protected" } ; const char * name , * type ; name = ( ( * targetm . strip_name_encoding ) ( IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ) ; type = visibility_types [ vis ] ; fprintf ( asm_out_file , "\t.%s\t%s\n" , type , name ) ; fprintf ( asm_out_file , "\t.%s\t.%s\n" , type , name ) ; } else default_assemble_visibility ( decl , vis ) ; } </s>

Emit an assembler directive to set symbol visibility for DECL to VISIBILITY_TYPE .


<s> void HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return N -> setNodeId ( - 1 ) ; switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectConstant ( N ) ; case ISD :: ConstantFP : return SelectConstantFP ( N ) ; case ISD :: FrameIndex : return SelectFrameIndex ( N ) ; case ISD :: BITCAST : return SelectBitcast ( N ) ; case ISD :: SHL : return SelectSHL ( N ) ; case ISD :: LOAD : return SelectLoad ( N ) ; case ISD :: STORE : return SelectStore ( N ) ; case ISD :: MUL : return SelectMul ( N ) ; case ISD :: ZERO_EXTEND : return SelectZeroExtend ( N ) ; case ISD :: INTRINSIC_W_CHAIN : return SelectIntrinsicWChain ( N ) ; case ISD :: INTRINSIC_WO_CHAIN : return SelectIntrinsicWOChain ( N ) ; } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .

Hexagon Hexagon 1 ISD::Constant ISD::ConstantFP ISD::FrameIndex ISD::BITCAST ISD::SHL ISD::LOAD ISD::STORE ISD::MUL ISD::ZERO_EXTEND ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_WO_CHAIN


<s> bool ARMSubtarget :: enableSubRegLiveness ( ) const { return EnableSubRegLiveness ; } </s>

Enable tracking of subregister liveness in register allocator .


<s> static rtx nvptx_gen_vcast ( rtx reg ) { return nvptx_gen_shuffle ( reg , reg , const0_rtx , SHUFFLE_IDX ) ; } </s>

Generate an instruction or sequence to broadcast register REG across the vectors of a single warp .


<s> int m32c_extra_constraint_p2 ( rtx value , char c ATTRIBUTE_UNUSED , const char * str ) { encode_pattern ( value ) ; if ( memcmp ( str , "Sd" , 2 ) == 0 ) { rtx r ; if ( GET_CODE ( value ) == MEM && CONSTANT_P ( XEXP ( value , 0 ) ) ) return 1 ; if ( RTX_IS ( "ms" ) || RTX_IS ( "m+si" ) ) return 1 ; if ( RTX_IS ( "mr" ) ) r = patternr [ 1 ] ; else if ( RTX_IS ( "m+ri" ) || RTX_IS ( "m+rs" ) || RTX_IS ( "m+r+si" ) ) r = patternr [ 2 ] ; else return 0 ; if ( REGNO ( r ) == SP_REGNO ) return 0 ; return m32c_legitimate_address_p ( GET_MODE ( value ) , XEXP ( value , 0 ) , 1 ) ; } else if ( memcmp ( str , "Sa" , 2 ) == 0 ) { rtx r ; if ( RTX_IS ( "mr" ) ) r = patternr [ 1 ] ; else if ( RTX_IS ( "m+ri" ) ) r = patternr [ 2 ] ; else return 0 ; return ( IS_REG ( r , A0_REGNO ) || IS_REG ( r , A1_REGNO ) ) ; } else if ( memcmp ( str , "Si" , 2 ) == 0 ) { return ( RTX_IS ( "mi" ) || RTX_IS ( "ms" ) || RTX_IS ( "m+si" ) ) ; } else if ( memcmp ( str , "Ss" , 2 ) == 0 ) { return ( ( RTX_IS ( "mr" ) && ( IS_REG ( patternr [ 1 ] , SP_REGNO ) ) ) || ( RTX_IS ( "m+ri" ) && ( IS_REG ( patternr [ 2 ] , SP_REGNO ) ) ) ) ; } else if ( memcmp ( str , "Sf" , 2 ) == 0 ) { return ( ( RTX_IS ( "mr" ) && ( IS_REG ( patternr [ 1 ] , FB_REGNO ) ) ) || ( RTX_IS ( "m+ri" ) && ( IS_REG ( patternr [ 2 ] , FB_REGNO ) ) ) ) ; } else if ( memcmp ( str , "Sb" , 2 ) == 0 ) { return ( ( RTX_IS ( "mr" ) && ( IS_REG ( patternr [ 1 ] , SB_REGNO ) ) ) || ( RTX_IS ( "m+ri" ) && ( IS_REG ( patternr [ 2 ] , SB_REGNO ) ) ) ) ; } else if ( memcmp ( str , "S1" , 2 ) == 0 ) { return r1h_operand ( value , QImode ) ; } gcc_assert ( str [ 0 ] != 'S' ) ; if ( memcmp ( str , "Rpa" , 2 ) == 0 ) return GET_CODE ( value ) == PARALLEL ; return 0 ; } </s>

Implements EXTRA_CONSTRAINT_STR ( see next function too ) . 'S ' is for memory constraints , plus `` Rpa '' for PARALLEL rtx 's we use for call return values .


<s> MOSSubtarget & MOSSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { ParseSubtargetFeatures ( CPU , CPU , FS ) ; EFlags = MOS_MC :: makeEFlags ( getFeatureBits ( ) ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> unsigned getMaxPrefetchIterationsAhead ( ) const override { return MaxPrefetchIterationsAhead ; } </s>

Return the maximum prefetch distance in terms of loop iterations .


<s> static rtx cr16_legitimize_address ( rtx x , rtx orig_x ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { if ( flag_pic ) return legitimize_pic_address ( orig_x , mode , NULL_RTX ) ; else return x ; } </s>

A C compound statement that attempts to replace X with a valid memory address for an operand of mode MODE . WIN will be a C statement label elsewhere in the code . X will always be the result of a call to break_out_memory_refs ( ) , and OLDX will be the operand that was given to that function to produce X . The code generated by this macro should not alter the substructure of X . If it transforms X into a more legitimate form , it should assign X ( which will always be a C variable ) a new value .


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented byval arguments"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
static
int
getMemScale
(
MachineInstr
*
MI
)
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Opcode has unknown scale!"
)
;
case
AArch64
::
LDRBBui
:
case
AArch64
::
STRBBui
:
return
1
;
case
AArch64
::
LDRHHui
:
case
AArch64
::
STRHHui
:
return
2
;
case
AArch64
::
LDRSui
:
case
AArch64
::
LDURSi
:
case
AArch64
::
LDRSWui
:
case
AArch64
::
LDURSWi
:
case
AArch64
::
LDRWui
:
case
AArch64
::
LDURWi
:
case
AArch64
::
STRSui
:
case
AArch64
::
STURSi
:
case
AArch64
::
STRWui
:
case
AArch64
::
STURWi
:
case
AArch64
::
LDPSi
:
case
AArch64
::
LDPSWi
:
case
AArch64
::
LDPWi
:
case
AArch64
::
STPSi
:
case
AArch64
::
STPWi
:
return
4
;
case
AArch64
::
LDRDui
:
case
AArch64
::
LDURDi
:
case
AArch64
::
LDRXui
:
case
AArch64
::
LDURXi
:
case
AArch64
::
STRDui
:
case
AArch64
::
STURDi
:
case
AArch64
::
STRXui
:
case
AArch64
::
STURXi
:
case
AArch64
::
LDPDi
:
case
AArch64
::
LDPXi
:
case
AArch64
::
STPDi
:
case
AArch64
::
STPXi
:
return
8
;
case
AArch64
::
LDRQui
:
case
AArch64
::
LDURQi
:
case
AArch64
::
STRQui
:
case
AArch64
::
STURQi
:
case
AArch64
::
LDPQi
:
case
AArch64
::
STPQi
:
return
16
;
}
}
</s>

Scaling factor for ( scaled or unscaled ) load or store .


"%qs attribute only applies to functions"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> unsigned HexagonInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case Hexagon :: L2_loadri_io : case Hexagon :: L2_loadrd_io : case Hexagon :: V6_vL32b_ai : case Hexagon :: V6_vL32b_ai_128B : case Hexagon :: V6_vL32Ub_ai : case Hexagon :: V6_vL32Ub_ai_128B : case Hexagon :: LDriw_pred : case Hexagon :: LDriw_mod : case Hexagon :: PS_vloadrq_ai : case Hexagon :: PS_vloadrw_ai : case Hexagon :: PS_vloadrq_ai_128B : case Hexagon :: PS_vloadrw_ai_128B : { const MachineOperand OpFI = MI . getOperand ( 1 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 2 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } case Hexagon :: L2_ploadrit_io : case Hexagon :: L2_ploadrif_io : case Hexagon :: L2_ploadrdt_io : case Hexagon :: L2_ploadrdf_io : { const MachineOperand OpFI = MI . getOperand ( 2 ) ; if ( ! OpFI . isFI ( ) ) return 0 ; const MachineOperand OpOff = MI . getOperand ( 3 ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != 0 ) return 0 ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> bool CSKYFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static void mips_init_libfuncs ( void ) { if ( TARGET_FIX_VR4120 ) { set_optab_libfunc ( sdiv_optab , SImode , "__vr4120_divsi3" ) ; set_optab_libfunc ( smod_optab , SImode , "__vr4120_modsi3" ) ; } if ( TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI ) { set_optab_libfunc ( add_optab , SFmode , "__mips16_addsf3" ) ; set_optab_libfunc ( sub_optab , SFmode , "__mips16_subsf3" ) ; set_optab_libfunc ( smul_optab , SFmode , "__mips16_mulsf3" ) ; set_optab_libfunc ( sdiv_optab , SFmode , "__mips16_divsf3" ) ; set_optab_libfunc ( eq_optab , SFmode , "__mips16_eqsf2" ) ; set_optab_libfunc ( ne_optab , SFmode , "__mips16_nesf2" ) ; set_optab_libfunc ( gt_optab , SFmode , "__mips16_gtsf2" ) ; set_optab_libfunc ( ge_optab , SFmode , "__mips16_gesf2" ) ; set_optab_libfunc ( lt_optab , SFmode , "__mips16_ltsf2" ) ; set_optab_libfunc ( le_optab , SFmode , "__mips16_lesf2" ) ; set_optab_libfunc ( unord_optab , SFmode , "__mips16_unordsf2" ) ; set_conv_libfunc ( sfix_optab , SImode , SFmode , "__mips16_fix_truncsfsi" ) ; set_conv_libfunc ( sfloat_optab , SFmode , SImode , "__mips16_floatsisf" ) ; set_conv_libfunc ( ufloat_optab , SFmode , SImode , "__mips16_floatunsisf" ) ; if ( TARGET_DOUBLE_FLOAT ) { set_optab_libfunc ( add_optab , DFmode , "__mips16_adddf3" ) ; set_optab_libfunc ( sub_optab , DFmode , "__mips16_subdf3" ) ; set_optab_libfunc ( smul_optab , DFmode , "__mips16_muldf3" ) ; set_optab_libfunc ( sdiv_optab , DFmode , "__mips16_divdf3" ) ; set_optab_libfunc ( eq_optab , DFmode , "__mips16_eqdf2" ) ; set_optab_libfunc ( ne_optab , DFmode , "__mips16_nedf2" ) ; set_optab_libfunc ( gt_optab , DFmode , "__mips16_gtdf2" ) ; set_optab_libfunc ( ge_optab , DFmode , "__mips16_gedf2" ) ; set_optab_libfunc ( lt_optab , DFmode , "__mips16_ltdf2" ) ; set_optab_libfunc ( le_optab , DFmode , "__mips16_ledf2" ) ; set_optab_libfunc ( unord_optab , DFmode , "__mips16_unorddf2" ) ; set_conv_libfunc ( sext_optab , DFmode , SFmode , "__mips16_extendsfdf2" ) ; set_conv_libfunc ( trunc_optab , SFmode , DFmode , "__mips16_truncdfsf2" ) ; set_conv_libfunc ( sfix_optab , SImode , DFmode , "__mips16_fix_truncdfsi" ) ; set_conv_libfunc ( sfloat_optab , DFmode , SImode , "__mips16_floatsidf" ) ; set_conv_libfunc ( ufloat_optab , DFmode , SImode , "__mips16_floatunsidf" ) ; } } if ( TARGET_MIPS16 ) { synchronize_libfunc = init_one_libfunc ( "__sync_synchronize" ) ; init_sync_libfuncs ( UNITS_PER_WORD ) ; } } </s>


<s> void PPCFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; SavedRegs . reset ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool isPPC64 = Subtarget . isPPC64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( ) ; FPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( ) ; BPSI = MFI . CreateFixedObject ( isPPC64 ? 8 : 4 , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; } if ( FI -> usesPICBase ( ) ) { int PBPSI = MFI . CreateFixedObject ( 4 , - 8 , true ) ; FI -> setPICBasePointerSaveIndex ( PBPSI ) ; } if ( needsFP ( MF ) ) SavedRegs . reset ( isPPC64 ? PPC :: X31 : PPC :: R31 ) ; if ( RegInfo -> hasBasePointer ( MF ) ) SavedRegs . reset ( RegInfo -> getBaseRegister ( MF ) ) ; if ( FI -> usesPICBase ( ) ) SavedRegs . reset ( PPC :: R30 ) ; int TCSPDelta = 0 ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < 0 ) { MFI . CreateFixedObject ( - 1 * TCSPDelta , TCSPDelta , true ) ; } if ( ! isPPC64 && ! isDarwinABI && ( SavedRegs . test ( PPC :: CR2 ) || SavedRegs . test ( PPC :: CR3 ) || SavedRegs . test ( PPC :: CR4 ) ) ) { int FrameIdx = MFI . CreateFixedObject ( ( uint64_t ) 4 , ( int64_t ) - 4 , true ) ; FI -> setCRSpillFrameIndex ( FrameIdx ) ; } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"eliminateCallFramePseudoInstr size too big: "

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void TVMFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { LLVMContext & C = MF . getFunction ( ) . getContext ( ) ; const auto * TII = MF . getSubtarget < TVMSubtarget > ( ) . getInstrInfo ( ) ; auto & MFI = MF . getFrameInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == 0 && ! TraceCalls ) return ; auto InsertPt = MBB . getFirstTerminator ( ) ; DebugLoc DL ; if ( InsertPt != MBB . end ( ) ) DL = InsertPt -> getDebugLoc ( ) ; unsigned RegFrameBase = MRI . createVirtualRegister ( & TVM :: I257RegClass ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( TVM :: GETGLOB ) , RegFrameBase ) . addImm ( 5 ) ; unsigned RegFrameBaseNew = MRI . createVirtualRegister ( & TVM :: I257RegClass ) ; if ( StackSize <= 127 ) { BuildMI ( MBB , InsertPt , DL , TII -> get ( TVM :: ADDCONST ) , RegFrameBaseNew ) . addReg ( RegFrameBase ) . addImm ( StackSize ) ; } else { unsigned RegStSize = MRI . createVirtualRegister ( & TVM :: I257RegClass ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( TVM :: CONST_I257 ) , RegStSize ) . addCImm ( cimm ( C , StackSize ) ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( TVM :: ADD ) , RegFrameBaseNew ) . addReg ( RegFrameBase ) . addReg ( RegStSize ) ; } BuildMI ( MBB , InsertPt , DL , TII -> get ( TVM :: SETGLOB ) ) . addReg ( RegFrameBaseNew ) . addImm ( 5 ) ; } </s>


<s> static bool isReachable ( const MachineInstr * From , const MachineInstr * To , const MachineBasicBlock * CutOff , MachineDominatorTree & MDT ) { if ( MDT . dominates ( From , To ) ) return true ; const MachineBasicBlock * MBBFrom = From -> getParent ( ) ; const MachineBasicBlock * MBBTo = To -> getParent ( ) ; if ( MBBFrom == MBBTo ) return false ; return searchPredecessors ( MBBTo , CutOff , [ MBBFrom ] ( const MachineBasicBlock * MBB ) { return MBB == MBBFrom ; } ) ; } </s>

Returns true if instruction is reachable from entry .


<s> static void pro_epilogue_adjust_stack ( rtx dest , rtx src , rtx offset , int style , bool set_cfa ) { struct machine_function * m = cfun -> machine ; rtx insn ; bool add_frame_related_expr = false ; if ( Pmode == SImode ) insn = gen_pro_epilogue_adjust_stack_si_add ( dest , src , offset ) ; else if ( x86_64_immediate_operand ( offset , DImode ) ) insn = gen_pro_epilogue_adjust_stack_di_add ( dest , src , offset ) ; else { rtx tmp ; if ( style ) tmp = gen_rtx_REG ( DImode , R11_REG ) ; else { gcc_assert ( src != hard_frame_pointer_rtx && dest != hard_frame_pointer_rtx ) ; tmp = hard_frame_pointer_rtx ; } insn = emit_insn ( gen_rtx_SET ( DImode , tmp , offset ) ) ; if ( style < 0 ) add_frame_related_expr = true ; insn = gen_pro_epilogue_adjust_stack_di_add ( dest , src , tmp ) ; } insn = emit_insn ( insn ) ; if ( style >= 0 ) ix86_add_queued_cfa_restore_notes ( insn ) ; if ( set_cfa ) { rtx r ; gcc_assert ( m -> fs . cfa_reg == src ) ; m -> fs . cfa_offset += INTVAL ( offset ) ; m -> fs . cfa_reg = dest ; r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( VOIDmode , dest , r ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , r ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } else if ( style < 0 ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( add_frame_related_expr ) { rtx r = gen_rtx_PLUS ( Pmode , src , offset ) ; r = gen_rtx_SET ( VOIDmode , dest , r ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , r ) ; } } if ( dest == stack_pointer_rtx ) { HOST_WIDE_INT ooffset = m -> fs . sp_offset ; bool valid = m -> fs . sp_valid ; if ( src == hard_frame_pointer_rtx ) { valid = m -> fs . fp_valid ; ooffset = m -> fs . fp_offset ; } else if ( src == crtl -> drap_reg ) { valid = m -> fs . drap_valid ; ooffset = 0 ; } else { gcc_checking_assert ( src == stack_pointer_rtx || offset == const0_rtx ) ; } m -> fs . sp_offset = ooffset - INTVAL ( offset ) ; m -> fs . sp_valid = valid ; } } </s>

Expand prologue or epilogue stack adjustment . The pattern exist to put a dependency on all ebp-based memory accesses . STYLE should be negative if instructions should be marked as frame related , zero if % r11 register is live and can not be freely used and positive otherwise .


"Tiny codesize model not supported on X86"

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> const TOYSubtarget * getSubtargetImpl ( const Function & ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static void addarg ( const char * str ) { int l = strlen ( str ) ; if ( link_cmd_len + l >= link_cmd_maxlen ) { link_cmd_maxlen = link_cmd_len + l + 1024 ; link_cmd = XRESIZEVEC ( char , link_cmd , link_cmd_maxlen ) ; } memcpy ( link_cmd + link_cmd_len , str , l ) ; link_cmd_len += l ; } </s>

Append STR to the command line to invoke the linker . Expand the line as necessary to accommodate .


<s> bool match ( const MachineRegisterInfo & MRI , Register Reg ) { if ( ! MRI . hasOneNonDBGUse ( Reg ) ) return false ; MachineInstr & StoreMI = * MRI . use_instr_nodbg_begin ( Reg ) ; IncDec = getDefIgnoringCopies ( Reg , MRI ) ; switch ( IncDec -> getOpcode ( ) ) { case MOS :: G_INC : case MOS :: G_DEC : case MOS :: G_INC_TMP : case MOS :: G_DEC_TMP : break ; default : return false ; } unsigned DstIdx = 0 ; unsigned SrcIdx = IncDec -> getNumExplicitDefs ( ) ; while ( IncDec -> getOperand ( DstIdx ) . getReg ( ) != Reg ) { if ( IncDec -> getOperand ( SrcIdx ) . isReg ( ) ) ++ DstIdx ; ++ SrcIdx ; } if ( ! mi_match ( IncDec -> getOperand ( SrcIdx ) . getReg ( ) , MRI , m_all_of ( m_MInstr ( Load ) , m_FoldedLdAbs ( StoreMI , Addr , AA ) ) ) ) return false ; return Addr . isIdenticalTo ( StoreMI . getOperand ( 1 ) ) ; } </s>

matches - Match the regex against a given String .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static rtx aarch64_expand_sve_const_pred_trn ( rtx target , rtx_vector_builder & builder , unsigned int elt_size , unsigned int permute_size ) { unsigned int a_elt_size = GET_MODE_SIZE ( DImode ) ; unsigned int b_elt_size = GET_MODE_SIZE ( DImode ) ; for ( unsigned int i = 0 ; i < builder . encoded_nelts ( ) ; i += elt_size ) if ( INTVAL ( builder . elt ( i ) ) != 0 ) { if ( i & permute_size ) b_elt_size |= i - permute_size ; else a_elt_size |= i ; } a_elt_size &= - a_elt_size ; b_elt_size &= - b_elt_size ; rtx_vector_builder a_builder ( VNx16BImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; rtx_vector_builder b_builder ( VNx16BImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ; unsigned int nelts = builder . encoded_nelts ( ) ; for ( unsigned int i = 0 ; i < nelts ; ++ i ) if ( i & ( elt_size - 1 ) ) { a_builder . quick_push ( const0_rtx ) ; b_builder . quick_push ( const0_rtx ) ; } else if ( ( i & permute_size ) == 0 ) { a_builder . quick_push ( builder . elt ( i ) ) ; b_builder . quick_push ( builder . elt ( i + permute_size ) ) ; } else { if ( a_elt_size > permute_size ) a_builder . quick_push ( const0_rtx ) ; else a_builder . quick_push ( a_builder . elt ( i - a_elt_size ) ) ; if ( b_elt_size > permute_size ) b_builder . quick_push ( const0_rtx ) ; else b_builder . quick_push ( b_builder . elt ( i - b_elt_size ) ) ; } a_builder . finalize ( ) ; b_builder . finalize ( ) ; rtx_insn * last = get_last_insn ( ) ; rtx a = aarch64_expand_sve_const_pred_1 ( NULL_RTX , a_builder , false ) ; if ( ! a ) return NULL_RTX ; rtx b = a ; if ( a_builder != b_builder ) { b = aarch64_expand_sve_const_pred_1 ( NULL_RTX , b_builder , false ) ; if ( ! b ) { delete_insns_since ( last ) ; return NULL_RTX ; } } machine_mode mode = aarch64_sve_pred_mode ( permute_size ) . require ( ) ; target = aarch64_target_reg ( target , GET_MODE ( a ) ) ; rtx type_reg = CONST0_RTX ( mode ) ; emit_insn ( gen_aarch64_sve_trn1_conv ( mode , target , a , b , type_reg ) ) ; return target ; } </s>

BUILDER is a constant predicate in which the index of every set bit is a multiple of ELT_SIZE ( which is < = 8 ) . Try to load the constant using a TRN1 of size PERMUTE_SIZE , which is > = ELT_SIZE . Return the register on success , otherwise return null . Use TARGET as the register if nonnull and convenient .


Returns true if register REGNO is safe to be allocated as a scratch register in the current function .


<s> static rtx gen_varargs_mem ( machine_mode mode , rtx addr ) { rtx mem = gen_rtx_MEM ( mode , addr ) ; MEM_NOTRAP_P ( mem ) = 1 ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; return mem ; } </s>

Generate a MEM referring to a varargs argument slot .


<s> static void preprocess_args ( int * p_argc , char * * argv ) { int i ; for ( i = 1 ; i < * p_argc ; i ++ ) if ( strlen ( argv [ i ] ) >= 6 && strncmp ( argv [ i ] , "-shared" , 7 ) == 0 ) share = 1 ; for ( i = 1 ; i < * p_argc ; i ++ ) if ( strcmp ( argv [ i ] , "-o" ) == 0 ) { char * buff , * ptr ; int out_len ; int len ; i ++ ; ptr = to_host_file_spec ( argv [ i ] ) ; exefilename = xstrdup ( ptr ) ; out_len = strlen ( ptr ) ; buff = xmalloc ( out_len + 18 ) ; if ( share ) strcpy ( buff , "/share=" ) ; else strcpy ( buff , "/exe=" ) ; strcat ( buff , ptr ) ; addarg ( buff ) ; if ( share ) { sharefilename = xmalloc ( out_len + 5 ) ; if ( ptr == strchr ( argv [ i ] , ']' ) ) strcpy ( sharefilename , ++ ptr ) ; else if ( ptr == strchr ( argv [ i ] , ':' ) ) strcpy ( sharefilename , ++ ptr ) ; else if ( ptr == strrchr ( argv [ i ] , '/' ) ) strcpy ( sharefilename , ++ ptr ) ; else strcpy ( sharefilename , argv [ i ] ) ; len = strlen ( sharefilename ) ; if ( strncasecmp ( & sharefilename [ len - 4 ] , ".exe" , 4 ) == 0 ) sharefilename [ len - 4 ] = 0 ; for ( ptr = sharefilename ; * ptr ; ptr ++ ) * ptr = TOUPPER ( * ptr ) ; } } } </s>

Preprocess the number of args P_ARGC in ARGV . Look for special flags , etc . that must be handled first .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } addPass ( createAArch64StackTaggingPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> int getIntImmCostInst ( unsigned Opc , unsigned Idx , const APInt & Imm , Type * Ty ) { return getIntImmCost ( Imm , Ty ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> void HexagonTTIImpl :: getUnrollingPreferences ( Loop * L , ScalarEvolution & SE , TTI :: UnrollingPreferences & UP , OptimizationRemarkEmitter * ORE ) { UP . Runtime = UP . Partial = true ; } </s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> static void release_scratch_register_on_entry ( struct scratch_reg * sr ) { if ( sr -> saved ) { struct machine_function * m = cfun -> machine ; rtx x , insn = emit_insn ( gen_pop ( sr -> reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( UNITS_PER_WORD ) ) ; x = gen_rtx_SET ( stack_pointer_rtx , x ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , x ) ; m -> fs . sp_offset -= UNITS_PER_WORD ; } } </s>

Release a scratch register obtained from the preceding function . If RELEASE_VIA_POP is true , we just pop the register off the stack to release it . This is what non-Linux systems use with -fstack-check . Otherwise we use OFFSET to locate the saved register and the allocated stack space becomes part of the local frame and is deallocated by the epilogue .


<s> const PTXSubtarget & PTXDAGToDAGISel :: getSubtarget ( ) const { return TM . getSubtarget < PTXSubtarget > ( ) ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s> unsigned AArch64TargetLowering :: combineRepeatedFPDivisors ( ) const { return 3 ; } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> void NVPTXPassConfig :: addPreRegAlloc ( ) { addPass ( createNVPTXProxyRegErasurePass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> unsigned getUnits ( ) const { return ( Slots ) ; } </s>


"The function works only with LEA instructions"


<s> int s390_compare_and_branch_condition_mask ( rtx code ) { const int CC0 = 1 << 3 ; const int CC1 = 1 << 2 ; const int CC2 = 1 << 1 ; switch ( GET_CODE ( code ) ) { case EQ : return CC0 ; case NE : return CC1 | CC2 ; case LT : case LTU : return CC1 ; case GT : case GTU : return CC2 ; case LE : case LEU : return CC0 | CC1 ; case GE : case GEU : return CC0 | CC2 ; default : gcc_unreachable ( ) ; } return - 1 ; } </s>

Return branch condition mask to implement a compare and branch specified by CODE . Return -1 for invalid comparisons .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) { if ( Subtarget . isAIXABI ( ) && ! TM . getAIXExtendedAltivecABI ( ) ) return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask ; return CSR_64_AllRegs_VSX_RegMask ; } if ( Subtarget . hasAltivec ( ) ) { if ( Subtarget . isAIXABI ( ) && ! TM . getAIXExtendedAltivecABI ( ) ) return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask ; return CSR_64_AllRegs_Altivec_RegMask ; } return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isAIXABI ( ) ) { return TM . isPPC64 ( ) ? ( ( Subtarget . hasAltivec ( ) && TM . getAIXExtendedAltivecABI ( ) ) ? CSR_PPC64_Altivec_RegMask : CSR_PPC64_RegMask ) : ( ( Subtarget . hasAltivec ( ) && TM . getAIXExtendedAltivecABI ( ) ) ? CSR_AIX32_Altivec_RegMask : CSR_AIX32_RegMask ) ; } if ( CC == CallingConv :: Cold ) { return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR64_ColdCC_Altivec_RegMask : CSR_SVR64_ColdCC_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_RegMask : ( Subtarget . hasSPE ( ) ? CSR_SVR32_ColdCC_SPE_RegMask : CSR_SVR32_ColdCC_RegMask ) ) ; } return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_PPC64_Altivec_RegMask : CSR_PPC64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : ( Subtarget . hasSPE ( ) ? CSR_SVR432_SPE_RegMask : CSR_SVR432_RegMask ) ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .

PowerPC PPC PPC PPC PPC PPC PPC PPC PPC PPC PPC


"Should be loading %r15 and something else"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool SystemZPassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZElimComparePass ( getSystemZTargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createSystemZShortenInstPass ( getSystemZTargetMachine ( ) ) ) ; addPass ( createSystemZLongBranchPass ( getSystemZTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ SystemZ


<s> static rtx tilepro_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , 0 ) ; } </s>


<s> void arm_decompose_di_binop ( rtx op1 , rtx op2 , rtx * lo_op1 , rtx * hi_op1 , rtx * lo_op2 , rtx * hi_op2 ) { * lo_op1 = gen_lowpart ( SImode , op1 ) ; * hi_op1 = gen_highpart ( SImode , op1 ) ; * lo_op2 = simplify_gen_subreg ( SImode , op2 , DImode , subreg_lowpart_offset ( SImode , DImode ) ) ; * hi_op2 = simplify_gen_subreg ( SImode , op2 , DImode , subreg_highpart_offset ( SImode , DImode ) ) ; } </s>

Decompose operands for a 64-bit binary operation in OP1 and OP2 into its component 32-bit subregs . OP2 may be an immediate constant and we want to simplify it in that case .


<s> std :: pair < unsigned , unsigned > SIInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF & MO_MASK , TF & ~ MO_MASK ) ; } </s>

Decompose the machine operand 's target flags into two values - the direct target flag value and any of bit flags that are applied .


"Instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s>
const
char
*
arc_cpu_to_as
(
int
argc
,
const
char
*
*
argv
)
{
const
char
*
name
=
;
const
arc_cpu_t
*
arc_selected_cpu
;
if
(
argc
==
0
)
{
arc_selected_cpu
=
&
arc_cpu_types
[
(
int
)
TARGET_CPU_DEFAULT
]
;
}
else
{
name
=
argv
[
0
]
;
for
(
arc_selected_cpu
=
arc_cpu_types
;
arc_selected_cpu
->
name
;
arc_selected_cpu
++
)
{
if
(
strcmp
(
arc_selected_cpu
->
name
,
name
)
==
0
)
break
;
}
}
switch
(
arc_selected_cpu
->
arch_info
->
arch_id
)
{
case
BASE_ARCH_em
:
if
(
arc_selected_cpu
->
flags
&
FL_CD
)
name
=
"-mcode-density"
;
else
name
=
""
;
if
(
arc_selected_cpu
->
flags
&
FL_FPUDA
)
name
=
concat
(
"-mfpuda "
,
name
,
)
;
if
(
arc_selected_cpu
->
flags
&
FL_SPFP
)
name
=
concat
(
"-mspfp "
,
name
,
)
;
if
(
arc_selected_cpu
->
flags
&
FL_DPFP
)
name
=
concat
(
"-mdpfp "
,
name
,
)
;
return
concat
(
"-mcpu=arcem "
,
name
,
)
;
case
BASE_ARCH_hs
:
return
"-mcpu=archs"
;
case
BASE_ARCH_700
:
if
(
arc_selected_cpu
->
processor
==
PROCESSOR_nps400
)
return
"-mcpu=nps400 -mEA"
;
else
return
"-mcpu=arc700 -mEA"
;
case
BASE_ARCH_6xx
:
if
(
arc_selected_cpu
->
flags
&
FL_MUL64
)
return
"-mcpu=arc600 -mmul64 -mnorm"
;
if
(
arc_selected_cpu
->
flags
&
FL_MUL32x16
)
return
"-mcpu=arc600 -mdsp-packa -mnorm"
;
return
"-mcpu=arc600 -mnorm"
;
default
:
gcc_unreachable
(
)
;
}
return
;
}
</s>

Returns command line parameters to pass to as .

arc
0
0
0
"-mcode-density"
""
"-mfpuda "
"-mspfp "
"-mdpfp "
"-mcpu=arcem "
"-mcpu=archs"
"-mcpu=nps400 -mEA"
"-mcpu=arc700 -mEA"
"-mcpu=arc600 -mmul64 -mnorm"
"-mcpu=arc600 -mdsp-packa -mnorm"
"-mcpu=arc600 -mnorm"


<s>
MCSymbol
*
XNCMMCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .

XNCM
XNCM
"Unknown target flag on GV operand"
0


<s> static inline tree def_builtin_pure ( HOST_WIDE_INT mask , HOST_WIDE_INT mask2 , const char * name , enum ix86_builtin_func_type tcode , enum ix86_builtins code ) { tree decl = def_builtin ( mask , mask2 , name , tcode , code ) ; if ( decl ) DECL_PURE_P ( decl ) = 1 ; else ix86_builtins_isa [ ( int ) code ] . pure_p = true ; return decl ; } </s>

Like def_builtin , but also marks the function decl `` pure '' .


<s> AtomicExpansionKind shouldCastAtomicLoadInIR ( LoadInst * LI ) const override { return AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be cast by the IR-level AtomicExpand pass .


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


<s> int mcore_num_zeros ( HOST_WIDE_INT mask ) { return 32 - mcore_num_ones ( mask ) ; } </s>


<s> int s390_label_align ( rtx_insn * label ) { rtx_insn * prev_insn = prev_active_insn ( label ) ; rtx set , src ; if ( prev_insn == NULL_RTX ) goto old ; set = single_set ( prev_insn ) ; if ( set == NULL_RTX ) goto old ; src = SET_SRC ( set ) ; if ( GET_CODE ( src ) == UNSPEC && XINT ( src , 1 ) == UNSPEC_MAIN_BASE ) return 0 ; old : return align_labels . levels [ 0 ] . log ; } </s>

Return the alignment for LABEL . We default to the -falign-labels value except for the literal pool base label .


<s> static rtx ix86_expand_vec_ext_builtin ( tree exp , rtx target ) { machine_mode tmode , mode0 ; tree arg0 , arg1 ; int elt ; rtx op0 ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; arg1 = CALL_EXPR_ARG ( exp , 1 ) ; op0 = expand_normal ( arg0 ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg1 ) ; tmode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; mode0 = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; gcc_assert ( VECTOR_MODE_P ( mode0 ) ) ; op0 = force_reg ( mode0 , op0 ) ; if ( optimize || ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; ix86_expand_vector_extract ( true , target , op0 , elt ) ; return target ; } </s>

A subroutine of ix86_expand_builtin . These builtins are a wrapper around ix86_expand_vector_extract . They would be redundant ( for non-MMX ) if we had a language-level syntax for referencing vector elements .


<s> unsigned FISCAsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> const M88kMCExpr * M88kMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) M88kMCExpr ( Kind , Expr ) ; } </s>


"Not expecting modifiers with immediates"

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .


Return an array that contains the direct target flag values and their names .


"ARMHWLoops: Trip count does not fit into 32bits\n"

Query the target whether it would be profitable to convert the given loop into a hardware loop .


<s> bool X86TargetLowering :: isVectorShiftByScalarCheap ( Type * Ty ) const { unsigned Bits = Ty -> getScalarSizeInBits ( ) ; if ( Bits == 8 ) return false ; if ( Subtarget . hasAVX2 ( ) && ( Bits == 32 || Bits == 64 ) ) return false ; return true ; } </s>

This is used to enable splatted operand transforms for vector shifts and vector funnel shifts .


<s> void CSKYMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCInstrDesc & Desc = MII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; uint32_t Bin = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint16_t LO16 = static_cast < uint16_t > ( Bin ) ; uint16_t HI16 = static_cast < uint16_t > ( Bin >> 16 ) ; if ( Size == 4 ) support :: endian :: write < uint16_t > ( OS , HI16 , support :: little ) ; support :: endian :: write < uint16_t > ( OS , LO16 , support :: little ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .

CSKY CSKY 16 4 support::endian support::little support::endian support::little


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 pseudo instruction expansion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> InstructionCost ARMTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Imm . getActiveBits ( ) >= 64 ) return 4 ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getSOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getSOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( ST -> isThumb2 ( ) ) { if ( ( SImmVal >= 0 && SImmVal < 65536 ) || ( ARM_AM :: getT2SOImmVal ( ZImmVal ) != - 1 ) || ( ARM_AM :: getT2SOImmVal ( ~ ZImmVal ) != - 1 ) ) return 1 ; return ST -> hasV6T2Ops ( ) ? 2 : 3 ; } if ( Bits == 8 || ( SImmVal >= 0 && SImmVal < 256 ) ) return 1 ; if ( ( ~ SImmVal < 256 ) || ARM_AM :: isThumbImmShiftedVal ( ZImmVal ) ) return 2 ; return 3 ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> static void h8300_push_pop ( int regno , int nregs , bool pop_p , bool return_p ) { int i , j ; rtvec vec ; rtx sp , offset , x ; if ( ! return_p && nregs == 1 ) { if ( pop_p ) pop ( regno ) ; else push ( regno ) ; return ; } vec = rtvec_alloc ( ( return_p ? 1 : 0 ) + nregs + 1 ) ; sp = stack_pointer_rtx ; i = 0 ; if ( return_p ) { RTVEC_ELT ( vec , i ) = ret_rtx ; i ++ ; } for ( j = 0 ; j < nregs ; j ++ ) { rtx lhs , rhs ; if ( pop_p ) { lhs = gen_rtx_REG ( SImode , regno + j ) ; rhs = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp , ( nregs - j - 1 ) * 4 ) ) ; } else { lhs = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp , ( j + 1 ) * - 4 ) ) ; rhs = gen_rtx_REG ( SImode , regno + j ) ; } RTVEC_ELT ( vec , i + j ) = gen_rtx_SET ( lhs , rhs ) ; } offset = GEN_INT ( ( pop_p ? nregs : - nregs ) * 4 ) ; RTVEC_ELT ( vec , i + j ) = gen_rtx_SET ( sp , gen_rtx_PLUS ( Pmode , sp , offset ) ) ; x = gen_rtx_PARALLEL ( VOIDmode , vec ) ; if ( ! pop_p ) x = Fpa ( x ) ; if ( return_p ) emit_jump_insn ( x ) ; else emit_insn ( x ) ; } </s>

Emit an instruction to push or pop NREGS consecutive registers starting at register REGNO . POP_P selects a pop rather than a push and RETURN_P is true if the instruction should return . It must be possible to do the requested operation in a single instruction . If NREGS == 1 & & ! RETURN_P , use a normal push or pop insn . Otherwise emit a parallel of the form : ( parallel [ ( return ) ; ; if RETURN_P ( save or restore REGNO ) ( save or restore REGNO + 1 ) ... ( save or restore REGNO + NREGS - 1 ) ( set sp ( plus sp ( const_int adjust ) ) ) ]


<s> std :: pair < unsigned , const TargetRegisterClass * > mprocTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return std :: make_pair ( 0U , & mproc :: GR8RegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> MachineSDNode * SITargetLowering :: buildRSRC ( SelectionDAG & DAG , SDLoc DL , SDValue Ptr , uint32_t RsrcDword1 , uint64_t RsrcDword2And3 ) const { SDValue PtrLo = DAG . getTargetExtractSubreg ( AMDGPU :: sub0 , DL , MVT :: i32 , Ptr ) ; SDValue PtrHi = DAG . getTargetExtractSubreg ( AMDGPU :: sub1 , DL , MVT :: i32 , Ptr ) ; if ( RsrcDword1 ) { PtrHi = SDValue ( DAG . getMachineNode ( AMDGPU :: S_OR_B32 , DL , MVT :: i32 , PtrHi , DAG . getConstant ( RsrcDword1 , MVT :: i32 ) ) , 0 ) ; } SDValue DataLo = buildSMovImm32 ( DAG , DL , RsrcDword2And3 & UINT64_C ( 0xFFFFFFFF ) ) ; SDValue DataHi = buildSMovImm32 ( DAG , DL , RsrcDword2And3 >> 32 ) ; const SDValue Ops [ ] = { DAG . getTargetConstant ( AMDGPU :: SReg_128RegClassID , MVT :: i32 ) , PtrLo , DAG . getTargetConstant ( AMDGPU :: sub0 , MVT :: i32 ) , PtrHi , DAG . getTargetConstant ( AMDGPU :: sub1 , MVT :: i32 ) , DataLo , DAG . getTargetConstant ( AMDGPU :: sub2 , MVT :: i32 ) , DataHi , DAG . getTargetConstant ( AMDGPU :: sub3 , MVT :: i32 ) } ; return DAG . getMachineNode ( AMDGPU :: REG_SEQUENCE , DL , MVT :: v4i32 , Ops ) ; } </s>

Return a resource descriptor with the 'Add TID ' bit enabled The TID ( Thread ID ) is multiplied by the stride value ( bits [ 61:48 ] of the resource descriptor ) to create an offset , which is added to the resource pointer .


<s> static unsigned ix86_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( ! TARGET_ADJUST_UNROLL ) return nunroll ; subrtx_iterator :: array_type array ; bbs = get_loop_body ( loop ) ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( NONDEBUG_INSN_P ( insn ) ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( const_rtx x = * iter ) if ( MEM_P ( x ) ) { machine_mode mode = GET_MODE ( x ) ; unsigned int n_words = GET_MODE_SIZE ( mode ) / UNITS_PER_WORD ; if ( n_words > 4 ) mem_count += 2 ; else mem_count += 1 ; } free ( bbs ) ; if ( mem_count && mem_count <= 32 ) return MIN ( nunroll , 32 / mem_count ) ; return nunroll ; } </s>

This function adjusts the unroll factor based on the hardware capabilities . For ex , bdver3 has a loop buffer which makes unrolling of smaller loops less important . This function decides the unroll factor using number of memory references ( value 32 is used ) as a heuristic .


<s> static int moxie_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode , tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes_left , size ; if ( * cum >= 8 ) return 0 ; if ( moxie_pass_by_reference ( cum_v , mode , type , named ) ) size = 4 ; else if ( type ) { if ( AGGREGATE_TYPE_P ( type ) ) return 0 ; size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; bytes_left = ( 4 * 6 ) - ( ( * cum - 2 ) * 4 ) ; if ( size > bytes_left ) return bytes_left ; else return 0 ; } </s>

Some function arguments will only partially fit in the registers that hold arguments . Given a new arg , return the number of bytes that fit in argument passing registers .


<s> bool XCoreFTAOElim :: runOnMachineFunction ( MachineFunction & MF ) { const XCoreInstrInfo & TII = * static_cast < const XCoreInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackSize = MF . getFrameInfo ( ) . getStackSize ( ) ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , EE = MBB . end ( ) ; MBBI != EE ; ++ MBBI ) { if ( MBBI -> getOpcode ( ) == XCore :: FRAME_TO_ARGS_OFFSET ) { MachineInstr & OldInst = * MBBI ; Register Reg = OldInst . getOperand ( 0 ) . getReg ( ) ; MBBI = TII . loadImmediate ( MBB , MBBI , Reg , StackSize ) ; OldInst . eraseFromParent ( ) ; } } } return true ; } </s>

runOnMachineFunction - Emit the function body .

XCore XCore XCore XCore XCore::FRAME_TO_ARGS_OFFSET 0


<s> AVRSubtarget :: AVRSubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , AVRTargetMachine & TM ) : AVRGenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM ) , TSInfo ( ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , ELFArch ( false ) , m_FeatureSetDummy ( false ) { ParseSubtargetFeatures ( CPU , FS ) ; } </s>


<s> static void frv_sort_insn_group ( enum frv_insn_group group ) { struct frv_packet_group * packet_group ; unsigned int first , i , nop , max_unit , num_slots ; state_t state , test_state ; size_t dfa_size ; packet_group = & frv_packet . groups [ group ] ; packet_group -> nop = 0 ; if ( packet_group -> num_insns == 0 ) return ; memcpy ( packet_group -> sorted , packet_group -> insns , sizeof ( rtx ) * packet_group -> num_insns ) ; if ( packet_group -> num_insns > 1 ) qsort ( packet_group -> sorted , packet_group -> num_insns , sizeof ( rtx ) , frv_compare_insns ) ; if ( group == GROUP_B || group == GROUP_C ) return ; dfa_size = state_size ( ) ; state = alloca ( dfa_size ) ; test_state = alloca ( dfa_size ) ; state_reset ( test_state ) ; for ( first = 0 ; first < packet_group -> num_insns ; first ++ ) { memcpy ( state , test_state , dfa_size ) ; if ( state_transition ( test_state , packet_group -> sorted [ first ] ) >= 0 || ! cpu_unit_reservation_p ( test_state , NTH_UNIT ( group , first ) ) ) break ; } if ( first == packet_group -> num_insns ) return ; for ( nop = 0 ; nop < frv_num_nops ; nop ++ ) { max_unit = frv_insn_unit ( frv_nops [ nop ] ) ; if ( frv_unit_groups [ max_unit ] == group ) { packet_group -> nop = frv_nops [ nop ] ; num_slots = UNIT_NUMBER ( max_unit ) + 1 ; for ( i = packet_group -> num_insns ; i < num_slots ; i ++ ) packet_group -> sorted [ i ] = frv_nops [ nop ] ; if ( frv_sort_insn_group_1 ( group , first , num_slots , ( 1 << first ) - 1 , num_slots , state ) ) return ; } } gcc_unreachable ( ) ; } </s>

Copy frv_packet.groups [ GROUP ] .insns [ ] to frv_packet.groups [ GROUP ] .sorted [ ] and sort it into assembly language order . See frv.md for a description of the algorithm .


<s>
bool
X86InstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
1
&&
"Invalid X86 branch condition!"
)
;
X86
::
CondCode
CC
=
static_cast
<
X86
::
CondCode
>
(
Cond
[
0
]
.
getImm
(
)
)
;
Cond
[
0
]
.
setImm
(
GetOppositeBranchCondition
(
CC
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .


<s> static bool m32r_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { int size = arg . type_size_in_bytes ( ) ; return ( size < 0 || size > 8 ) ; } </s>

Return nonzero if TYPE must be passed by indirect reference .


<s> bool doFinalization ( Module & M ) override { return false ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static rtx aarch64_gen_loadwb_pair ( machine_mode mode , rtx base , rtx reg , rtx reg2 , HOST_WIDE_INT adjustment ) { switch ( mode ) { case E_DImode : return gen_loadwb_pairdi_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; case E_DFmode : return gen_loadwb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_WORD ) ) ; case E_TFmode : return gen_loadwb_pairtf_di ( base , base , reg , reg2 , GEN_INT ( adjustment ) , GEN_INT ( UNITS_PER_VREG ) ) ; default : gcc_unreachable ( ) ; } } </s>

Load the pair of register REG , REG2 of mode MODE from stack location BASE , adjusting it by ADJUSTMENT afterwards .


<s> bool aarch64_use_simple_return_insn_p ( void ) { if ( aarch64_simd_decl_p ( cfun -> decl ) && ! crtl -> is_leaf ) return false ; return true ; } </s>

Return false for non-leaf SIMD functions in order to avoid shrink-wrapping them . Doing this will lose the necessary save/restore of FP registers .


<s> int small_data_operand ( rtx op ATTRIBUTE_UNUSED , enum machine_mode mode ATTRIBUTE_UNUSED ) { rtx sym_ref ; if ( rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA ) return 0 ; if ( DEFAULT_ABI != ABI_V4 ) return 0 ; if ( GET_CODE ( op ) == SYMBOL_REF ) sym_ref = op ; else if ( GET_CODE ( op ) != CONST || GET_CODE ( XEXP ( op , 0 ) ) != PLUS || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) != SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) != CONST_INT ) return 0 ; else { rtx sum = XEXP ( op , 0 ) ; HOST_WIDE_INT summand ; summand = INTVAL ( XEXP ( sum , 1 ) ) ; if ( summand < 0 || ( unsigned HOST_WIDE_INT ) summand > g_switch_value ) return 0 ; sym_ref = XEXP ( sum , 0 ) ; } return SYMBOL_REF_SMALL_P ( sym_ref ) ; return 0 ; } </s>

Return 1 for an operand in small memory on V.4/eabi .


<s> bool ARMFrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; return ( RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { StringRef CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( HasSoftFloat ) HasVector = false ; if ( ! HasVector ) { HasVectorEnhancements1 = false ; HasVectorEnhancements2 = false ; HasVectorPackedDecimal = false ; HasVectorPackedDecimalEnhancement = false ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool AArch64TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( AM . BaseGV ) return false ; if ( AM . HasBaseReg && AM . BaseOffs && AM . Scale ) return false ; uint64_t NumBytes = 0 ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / 8 ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = 0 ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < 9 > ( Offset ) ) return true ; unsigned shift = Log2_64 ( NumBytes ) ; if ( NumBytes && Offset > 0 && ( Offset / NumBytes ) <= ( 1LL << 12 ) - 1 && ( Offset >> shift ) << shift == Offset ) return true ; return false ; } return AM . Scale == 1 || ( AM . Scale > 0 && ( uint64_t ) AM . Scale == NumBytes ) ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .