<s>
bool
SIFoldOperands
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
const
SIInstrInfo
*
TII
=
static_cast
<
const
SIInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
const
SIRegisterInfo
&
TRI
=
TII
->
getRegisterInfo
(
)
;
for
(
MachineFunction
::
iterator
BI
=
MF
.
begin
(
)
,
BE
=
MF
.
end
(
)
;
BI
!=
BE
;
++
BI
)
{
MachineBasicBlock
&
MBB
=
*
BI
;
MachineBasicBlock
::
iterator
I
,
Next
;
for
(
I
=
MBB
.
begin
(
)
;
I
!=
MBB
.
end
(
)
;
I
=
Next
)
{
Next
=
std
::
next
(
I
)
;
MachineInstr
&
MI
=
*
I
;
if
(
!
isSafeToFold
(
MI
.
getOpcode
(
)
)
)
continue
;
unsigned
OpSize
=
TII
->
getOpSize
(
MI
,
1
)
;
MachineOperand
&
OpToFold
=
MI
.
getOperand
(
1
)
;
bool
FoldingImm
=
OpToFold
.
isImm
(
)
;
if
(
!
FoldingImm
&&
!
OpToFold
.
isReg
(
)
)
continue
;
if
(
FoldingImm
&&
!
TII
->
isInlineConstant
(
OpToFold
,
OpSize
)
&&
!
MRI
.
hasOneUse
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
)
continue
;
if
(
OpToFold
.
isReg
(
)
&&
!
TargetRegisterInfo
::
isVirtualRegister
(
OpToFold
.
getReg
(
)
)
)
continue
;
MachineOperand
&
Dst
=
MI
.
getOperand
(
0
)
;
if
(
Dst
.
isReg
(
)
&&
!
TargetRegisterInfo
::
isVirtualRegister
(
Dst
.
getReg
(
)
)
)
continue
;
SmallVector
<
MachineInstr
*
,
4
>
CopiesToReplace
;
std
::
vector
<
FoldCandidate
>
FoldList
;
for
(
MachineRegisterInfo
::
use_iterator
Use
=
MRI
.
use_begin
(
MI
.
getOperand
(
0
)
.
getReg
(
)
)
,
E
=
MRI
.
use_end
(
)
;
Use
!=
E
;
++
Use
)
{
MachineInstr
*
UseMI
=
Use
->
getParent
(
)
;
foldOperand
(
OpToFold
,
UseMI
,
Use
.
getOperandNo
(
)
,
FoldList
,
CopiesToReplace
,
TII
,
TRI
,
MRI
)
;
}
for
(
MachineInstr
*
Copy
:
CopiesToReplace
)
Copy
->
addImplicitDefUseOperands
(
MF
)
;
for
(
FoldCandidate
&
Fold
:
FoldList
)
{
if
(
updateOperand
(
Fold
,
TRI
)
)
{
if
(
!
Fold
.
isImm
(
)
)
{
assert
(
Fold
.
OpToFold
&&
Fold
.
OpToFold
->
isReg
(
)
)
;
MRI
.
clearKillFlags
(
Fold
.
OpToFold
->
getReg
(
)
)
;
}
DEBUG
(
dbgs
(
)
<<
"Folded source from "
<<
MI
<<
" into OpNo "
<<
Fold
.
UseOpNo
<<
" of "
<<
*
Fold
.
UseMI
<<
'\n'
)
;
}
}
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> IndexType end ( ) const { return second ; } </s>

Get a const_iterator to the end of the symbol table .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 vzeroupper inserter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int ix86_address_cost ( rtx x , machine_mode , addr_space_t , bool ) { struct ix86_address parts ; int cost = 1 ; int ok = ix86_decompose_address ( x , & parts ) ; gcc_assert ( ok ) ; if ( parts . base && GET_CODE ( parts . base ) == SUBREG ) parts . base = SUBREG_REG ( parts . base ) ; if ( parts . index && GET_CODE ( parts . index ) == SUBREG ) parts . index = SUBREG_REG ( parts . index ) ; if ( parts . base && ( ! REG_P ( parts . base ) || REGNO ( parts . base ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . base ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . base ) ) ) cost ++ ; if ( parts . index && ( ! REG_P ( parts . index ) || REGNO ( parts . index ) >= FIRST_PSEUDO_REGISTER ) && ( current_pass -> type == GIMPLE_PASS || ! pic_offset_table_rtx || ! REG_P ( parts . index ) || REGNO ( pic_offset_table_rtx ) != REGNO ( parts . index ) ) ) cost ++ ; if ( TARGET_K6 && ( ( ! parts . disp && parts . base && parts . index && parts . scale != 1 ) || ( parts . disp && ! parts . base && parts . index && parts . scale != 1 ) || ( ! parts . disp && parts . base && parts . index && parts . scale == 1 ) ) ) cost += 10 ; return cost ; } </s>

Return cost of the memory address x . For i386 , it is better to use a complex address than let gcc copy the address into a reg and make a new pseudo . But not if the address requires to two regs - that would mean more pseudos with longer lifetimes .


<s> static bool originalTypeIsF128 ( const Type * Ty , const char * Func ) { if ( Ty -> isFP128Ty ( ) ) return true ; if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == 1 && Ty -> getStructElementType ( 0 ) -> isFP128Ty ( ) ) return true ; return ( Func && Ty -> isIntegerTy ( 128 ) && isF128SoftLibCall ( Func ) ) ; } </s>

This function returns true if Ty is fp128 , { f128 } or i128 which was originally a fp128 .


<s> bool AMDGPUAnnotateKernelFeatures :: runOnModule ( Module & M ) { Triple TT ( M . getTargetTriple ( ) ) ; static const StringRef IntrinsicToAttr [ ] [ 2 ] = { { "llvm.r600.read.tgid.y" , "amdgpu-work-group-id-y" } , { "llvm.r600.read.tgid.z" , "amdgpu-work-group-id-z" } , { "llvm.r600.read.tidig.y" , "amdgpu-work-item-id-y" } , { "llvm.r600.read.tidig.z" , "amdgpu-work-item-id-z" } } ; static const StringRef HSAIntrinsicToAttr [ ] [ 2 ] = { { "llvm.r600.read.local.size.x" , "amdgpu-dispatch-ptr" } , { "llvm.r600.read.local.size.y" , "amdgpu-dispatch-ptr" } , { "llvm.r600.read.local.size.z" , "amdgpu-dispatch-ptr" } , { "llvm.r600.read.global.size.x" , "amdgpu-dispatch-ptr" } , { "llvm.r600.read.global.size.y" , "amdgpu-dispatch-ptr" } , { "llvm.r600.read.global.size.z" , "amdgpu-dispatch-ptr" } , { "llvm.amdgcn.dispatch.ptr" , "amdgpu-dispatch-ptr" } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA ) Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s>
bool
AMDGPUOpenCLEnqueuedBlockLowering
::
runOnModule
(
Module
&
M
)
{
DenseSet
<
Function
*
>
Callers
;
auto
&
C
=
M
.
getContext
(
)
;
bool
Changed
=
false
;
for
(
auto
&
F
:
M
.
functions
(
)
)
{
if
(
F
.
hasFnAttribute
(
"enqueued-block"
)
)
{
if
(
!
F
.
hasName
(
)
)
{
SmallString
<
64
>
Name
;
Mangler
::
getNameWithPrefix
(
Name
,
"__amdgpu_enqueued_kernel"
,
M
.
getDataLayout
(
)
)
;
F
.
setName
(
Name
)
;
}
LLVM_DEBUG
(
dbgs
(
)
<<
"found enqueued kernel: "
<<
F
.
getName
(
)
<<
'\n'
)
;
auto
RuntimeHandle
=
(
F
.
getName
(
)
+
".runtime_handle"
)
.
str
(
)
;
auto
T
=
ArrayType
::
get
(
Type
::
getInt64Ty
(
C
)
,
2
)
;
auto
*
GV
=
new
GlobalVariable
(
M
,
T
,
false
,
GlobalValue
::
ExternalLinkage
,
Constant
::
getNullValue
(
T
)
,
RuntimeHandle
,
nullptr
,
GlobalValue
::
NotThreadLocal
,
AMDGPUAS
::
GLOBAL_ADDRESS
,
false
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"runtime handle created: "
<<
*
GV
<<
'\n'
)
;
for
(
auto
U
:
F
.
users
(
)
)
{
auto
*
UU
=
&
*
U
;
if
(
!
isa
<
ConstantExpr
>
(
UU
)
)
continue
;
collectFunctionUsers
(
UU
,
Callers
)
;
auto
*
BitCast
=
cast
<
ConstantExpr
>
(
UU
)
;
auto
*
NewPtr
=
ConstantExpr
::
getPointerCast
(
GV
,
BitCast
->
getType
(
)
)
;
BitCast
->
replaceAllUsesWith
(
NewPtr
)
;
F
.
addFnAttr
(
"runtime-handle"
,
RuntimeHandle
)
;
F
.
setLinkage
(
GlobalValue
::
ExternalLinkage
)
;
Changed
=
true
;
}
}
}
for
(
auto
F
:
Callers
)
{
if
(
F
->
getCallingConv
(
)
!=
CallingConv
::
AMDGPU_KERNEL
)
continue
;
F
->
addFnAttr
(
"calls-enqueue-kernel"
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"mark enqueue_kernel caller:"
<<
F
->
getName
(
)
<<
'\n'
)
;
}
return
Changed
;
}
</s>

AMDGPU
AMDGPU
"enqueued-block"
64
"__amdgpu_enqueued_kernel"
"found enqueued kernel: "
".runtime_handle"
2
AMDGPU
"runtime handle created: "
"runtime-handle"
AMDGPU
"calls-enqueue-kernel"
"mark enqueue_kernel caller:"


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> int pa_attr_length_indirect_call ( rtx_insn * insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) return 12 ; if ( TARGET_FAST_INDIRECT_CALLS || ( ! TARGET_LONG_CALLS && ! TARGET_PORTABLE_RUNTIME && ( ( TARGET_PA_20 && ! TARGET_SOM && distance < 7600000 ) || distance < MAX_PCREL17F_OFFSET ) ) ) return 8 ; if ( flag_pic ) return 20 ; if ( TARGET_PORTABLE_RUNTIME ) return 16 ; return 12 ; } </s>

Return the attribute length of the indirect call instruction INSN . The length must match the code generated by output_indirect call . The returned length includes the delay slot . Currently , the delay slot of an indirect call sequence is not exposed and it is used by the sequence itself .


<s>
void
Z80oldDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
SDLoc
DL
(
Node
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Selecting: "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static int epiphany_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep_insn , int cost , unsigned int ) { if ( dep_type == 0 ) { rtx dep_set ; if ( recog_memoized ( insn ) < 0 || recog_memoized ( dep_insn ) < 0 ) return cost ; dep_set = single_set ( dep_insn ) ; if ( dep_set && MEM_P ( SET_SRC ( dep_set ) ) && cost > 1 ) { rtx set = single_set ( insn ) ; if ( set && ! reg_overlap_mentioned_p ( SET_DEST ( dep_set ) , SET_SRC ( set ) ) && ( ! MEM_P ( SET_DEST ( set ) ) || ! reg_overlap_mentioned_p ( SET_DEST ( dep_set ) , XEXP ( SET_DEST ( set ) , 0 ) ) ) ) cost = 1 ; } } return cost ; } </s>

Function to update the integer COST based on the relationship between INSN that is dependent on DEP_INSN through the dependence LINK . The default is to make no adjustment to COST . This can be used for example to specify to the scheduler that an output- or anti-dependence does not incur the same cost as a data-dependence . The return value should be the new value for COST .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> const MOSTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s>
bool
AMDGPUPerfHint
::
runOnFunction
(
Function
&
F
)
{
const
Module
&
M
=
*
F
.
getParent
(
)
;
DL
=
&
M
.
getDataLayout
(
)
;
if
(
F
.
hasFnAttribute
(
"amdgpu-wave-limiter"
)
&&
F
.
hasFnAttribute
(
"amdgpu-memory-bound"
)
)
return
false
;
const
AMDGPUPerfHintAnalysis
::
FuncInfo
*
Info
=
visit
(
F
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" MemInst: "
<<
Info
->
MemInstCount
<<
'\n'
<<
" IAMInst: "
<<
Info
->
IAMInstCount
<<
'\n'
<<
" LSMInst: "
<<
Info
->
LSMInstCount
<<
'\n'
<<
" TotalInst: "
<<
Info
->
InstCount
<<
'\n'
)
;
if
(
isMemBound
(
*
Info
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" is memory bound\n"
)
;
NumMemBound
++
;
F
.
addFnAttr
(
"amdgpu-memory-bound"
,
"true"
)
;
}
if
(
AMDGPU
::
isEntryFunctionCC
(
F
.
getCallingConv
(
)
)
&&
needLimitWave
(
*
Info
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" needs limit wave\n"
)
;
NumLimitWave
++
;
F
.
addFnAttr
(
"amdgpu-wave-limiter"
,
"true"
)
;
}
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

AMDGPU
AMDGPU
"amdgpu-wave-limiter"
"amdgpu-memory-bound"
AMDGPU
" MemInst: "
" IAMInst: "
" LSMInst: "
" TotalInst: "
" is memory bound\n"
"amdgpu-memory-bound"
"true"
AMDGPU::isEntryFunctionCC
" needs limit wave\n"
"amdgpu-wave-limiter"
"true"


<s> void emitAssemblerFlag ( MCAssemblerFlag Flag ) override { } </s>


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s>
void
R600SchedStrategy
::
initialize
(
ScheduleDAGMI
*
dag
)
{
assert
(
dag
->
hasVRegLiveness
(
)
&&
"R600SchedStrategy needs vreg liveness"
)
;
DAG
=
static_cast
<
ScheduleDAGMILive
*
>
(
dag
)
;
const
R600Subtarget
&
ST
=
DAG
->
MF
.
getSubtarget
<
R600Subtarget
>
(
)
;
TII
=
static_cast
<
const
R600InstrInfo
*
>
(
DAG
->
TII
)
;
TRI
=
static_cast
<
const
R600RegisterInfo
*
>
(
DAG
->
TRI
)
;
VLIW5
=
!
ST
.
hasCaymanISA
(
)
;
MRI
=
&
DAG
->
MRI
;
CurInstKind
=
IDOther
;
CurEmitted
=
0
;
OccupedSlotsMask
=
31
;
InstKindLimit
[
IDAlu
]
=
TII
->
getMaxAlusPerClause
(
)
;
InstKindLimit
[
IDOther
]
=
32
;
InstKindLimit
[
IDFetch
]
=
ST
.
getTexVTXClauseSize
(
)
;
AluInstCount
=
0
;
FetchInstCount
=
0
;
}
</s>

Initialize the strategy after building the DAG for a new region .


<s> const PPCMCExpr * PPCMCExpr :: create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) PPCMCExpr ( Kind , Expr ) ; } </s>


<s> static rtx ix86_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; machine_mode mode = arg . mode ; HOST_WIDE_INT bytes , words ; rtx reg ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) { gcc_assert ( arg . type != NULL_TREE ) ; if ( POINTER_TYPE_P ( arg . type ) ) { gcc_assert ( TYPE_MODE ( arg . type ) == Pmode ) ; reg = plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ; } else { gcc_assert ( cfun -> machine -> func_type == TYPE_EXCEPTION && TREE_CODE ( arg . type ) == INTEGER_TYPE && TYPE_MODE ( arg . type ) == word_mode ) ; reg = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , arg_pointer_rtx , - 2 * UNITS_PER_WORD ) ) ; } return reg ; } bytes = arg . promoted_size_in_bytes ( ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( arg . type && TREE_CODE ( arg . type ) == VECTOR_TYPE ) mode = type_natural_mode ( arg . type , cum , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) reg = function_arg_ms_64 ( cum , mode , arg . mode , arg . named , arg . type , bytes ) ; else reg = function_arg_64 ( cum , mode , arg . mode , arg . type , arg . named ) ; } else reg = function_arg_32 ( cum , mode , arg . mode , arg . type , bytes , words ) ; if ( reg == NULL_RTX && cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; return reg ; } </s>

Return where to put the arguments to a function . Return zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument . It is null for libcalls where that information may not be available . CUM gives information about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s>
void
HexagonFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
bool
HasAlloca
=
MFI
.
hasVarSizedObjects
(
)
;
bool
NeedsAlign
=
(
MFI
.
getMaxAlignment
(
)
>
getStackAlignment
(
)
)
;
if
(
!
HasAlloca
||
!
NeedsAlign
)
return
;
unsigned
LFS
=
MFI
.
getLocalFrameSize
(
)
;
for
(
int
i
=
0
,
e
=
MFI
.
getObjectIndexEnd
(
)
;
i
!=
e
;
++
i
)
{
if
(
!
MFI
.
isSpillSlotObjectIndex
(
i
)
||
MFI
.
isDeadObjectIndex
(
i
)
)
continue
;
unsigned
S
=
MFI
.
getObjectSize
(
i
)
;
unsigned
A
=
std
::
max
(
MFI
.
getObjectAlignment
(
i
)
,
8U
)
;
MFI
.
setObjectAlignment
(
i
,
8
)
;
LFS
=
alignTo
(
LFS
+
S
,
A
)
;
MFI
.
mapLocalFrameObject
(
i
,
LFS
)
;
}
MFI
.
setLocalFrameSize
(
LFS
)
;
Align
A
=
MFI
.
getLocalFrameMaxAlign
(
)
;
assert
(
A
<=
8
&&
"Unexpected local frame alignment"
)
;
if
(
A
==
1
)
MFI
.
setLocalFrameMaxAlign
(
llvm
::
Align
(
8
)
)
;
MFI
.
setUseLocalStackAllocationBlock
(
true
)
;
unsigned
AP
=
0
;
if
(
const
MachineInstr
*
AI
=
getAlignaInstr
(
MF
)
)
AP
=
AI
->
getOperand
(
0
)
.
getReg
(
)
;
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
HMFI
.
setStackAlignBasePhysReg
(
AP
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> int direct_return ( void ) { return ( ! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK && reload_completed && alpha_sa_size ( ) == 0 && get_frame_size ( ) == 0 && current_function_outgoing_args_size == 0 && current_function_pretend_args_size == 0 ) ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> static bool nvptx_print_operand_punct_valid_p ( unsigned char c ) { return c == '.' || c == '#' ; } </s>


<s> void rbt_new ( struct rbt_strings * t ) { t -> rbt_nil = ( rbt_string_node * ) malloc ( sizeof ( rbt_string_node ) ) ; t -> rbt_nil -> color = RBT_BLACK ; t -> rbt_root = t -> rbt_nil ; } </s>


<s> const TargetRegisterClass * Z80oldRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case Z80old :: RR8RegClassID : case Z80old :: R16RegClassID : return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> static SDValue buildRSRC ( SelectionDAG * DAG , SDLoc DL , SDValue Ptr , uint32_t RsrcDword1 , uint64_t RsrcDword2And3 ) { SDValue PtrLo = DAG -> getTargetExtractSubreg ( AMDGPU :: sub0 , DL , MVT :: i32 , Ptr ) ; SDValue PtrHi = DAG -> getTargetExtractSubreg ( AMDGPU :: sub1 , DL , MVT :: i32 , Ptr ) ; if ( RsrcDword1 ) { PtrHi = SDValue ( DAG -> getMachineNode ( AMDGPU :: S_OR_B32 , DL , MVT :: i32 , PtrHi , DAG -> getConstant ( RsrcDword1 , MVT :: i32 ) ) , 0 ) ; } SDValue DataLo = buildSMovImm32 ( DAG , DL , RsrcDword2And3 & UINT64_C ( 0xFFFFFFFF ) ) ; SDValue DataHi = buildSMovImm32 ( DAG , DL , RsrcDword2And3 >> 32 ) ; const SDValue Ops [ ] = { DAG -> getTargetConstant ( AMDGPU :: SReg_128RegClassID , MVT :: i32 ) , PtrLo , DAG -> getTargetConstant ( AMDGPU :: sub0 , MVT :: i32 ) , PtrHi , DAG -> getTargetConstant ( AMDGPU :: sub1 , MVT :: i32 ) , DataLo , DAG -> getTargetConstant ( AMDGPU :: sub2 , MVT :: i32 ) , DataHi , DAG -> getTargetConstant ( AMDGPU :: sub3 , MVT :: i32 ) } ; return SDValue ( DAG -> getMachineNode ( AMDGPU :: REG_SEQUENCE , DL , MVT :: v4i32 , Ops ) , 0 ) ; } </s>

Return a resource descriptor with the 'Add TID ' bit enabled The TID ( Thread ID ) is multiplied by the stride value ( bits [ 61:48 ] of the resource descriptor ) to create an offset , which is added to the resource pointer .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
RootScope
=
getAnalysis
<
PatmosSPBundling
>
(
)
.
getRootScope
(
)
;
PMFI
=
MF
.
getInfo
<
PatmosMachineFunctionInfo
>
(
)
;
bool
changed
=
false
;
if
(
MF
.
getInfo
<
PatmosMachineFunctionInfo
>
(
)
->
isSinglePath
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"[Single-Path] Reducing "
<<
MF
.
getFunction
(
)
.
getName
(
)
<<
"\n"
)
;
doReduceFunction
(
MF
)
;
changed
|=
true
;
}
return
changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Patmos
Patmos
Patmos
Patmos
"[Single-Path] Reducing "
"\n"


<s> static bool mask_agnostic_p ( rtx_insn * rinsn ) { extract_insn_cached ( rinsn ) ; int ma = get_attr_ma ( rinsn ) ; return ma == INVALID_ATTRIBUTE ? get_default_ma ( ) : IS_AGNOSTIC ( ma ) ; } </s>


<s>
unsigned
getReg
(
)
const
{
assert
(
isRegBase
(
)
&&
"Invalid base register access!"
)
;
return
Base
.
Reg
;
}
</s>

Returns the register associated with this edge .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> bool SIFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( CSI . empty ( ) ) return true ; const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( ! FuncInfo -> SGPRForFPSaveRestoreCopy && ! FuncInfo -> SGPRForBPSaveRestoreCopy ) return false ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIRegisterInfo * RI = ST . getRegisterInfo ( ) ; Register FramePtrReg = FuncInfo -> getFrameOffsetReg ( ) ; Register BasePtrReg = RI -> getBaseRegister ( ) ; unsigned NumModifiedRegs = 0 ; if ( FuncInfo -> SGPRForFPSaveRestoreCopy ) NumModifiedRegs ++ ; if ( FuncInfo -> SGPRForBPSaveRestoreCopy ) NumModifiedRegs ++ ; for ( auto & CS : CSI ) { if ( CS . getReg ( ) == FramePtrReg && FuncInfo -> SGPRForFPSaveRestoreCopy ) { CS . setDstReg ( FuncInfo -> SGPRForFPSaveRestoreCopy ) ; if ( -- NumModifiedRegs ) break ; } else if ( CS . getReg ( ) == BasePtrReg && FuncInfo -> SGPRForBPSaveRestoreCopy ) { CS . setDstReg ( FuncInfo -> SGPRForBPSaveRestoreCopy ) ; if ( -- NumModifiedRegs ) break ; } } return false ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & ARM :: GPRRegClass || RC == & ARM :: tGPRRegClass || RC == & ARM :: tcGPRRegClass || RC == & ARM :: rGPRRegClass || RC == & ARM :: GPRnopcRegClass ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPair_with_gsub_1_in_rGPRRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> static void extract_devices_dir_from_exec_prefix ( char * * devices_loc ) { const char * temp ; char * gcc_exec_prefix = * devices_loc ; int len = strlen ( gcc_exec_prefix ) ; if ( len > ( int ) sizeof ( "/lib/gcc/" ) - 1 && ( IS_DIR_SEPARATOR ( gcc_exec_prefix [ len - 1 ] ) ) ) { temp = gcc_exec_prefix + len - sizeof ( "/lib/gcc/" ) + 1 ; if ( IS_DIR_SEPARATOR ( * temp ) && filename_ncmp ( temp + 1 , "lib" , 3 ) == 0 && IS_DIR_SEPARATOR ( temp [ 4 ] ) && filename_ncmp ( temp + 5 , "gcc" , 3 ) == 0 ) { len -= sizeof ( "/lib/gcc/" ) - 1 ; gcc_exec_prefix [ len + 1 ] = ( char ) 0 ; * devices_loc = concat ( gcc_exec_prefix , rest_of_devices_path , NULL ) ; return ; } } } </s>

`` The default value of GCC_EXEC_PREFIX is prefix/lib/gcc '' . Strip lib/gcc from GCC_EXEC_PREFIX to get the path to the installed toolchain .


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { return new ScheduleDAGMI ( C , std :: make_unique < SystemZPostRASchedStrategy > ( C ) , true ) ; } </s>

Similar to createMachineScheduler but used when postRA machine scheduling is enabled .


<s>
bool
PPCInstrInfo
::
FoldImmediate
(
MachineInstr
*
UseMI
,
MachineInstr
*
DefMI
,
unsigned
Reg
,
MachineRegisterInfo
*
MRI
)
const
{
unsigned
DefOpc
=
DefMI
->
getOpcode
(
)
;
if
(
DefOpc
!=
PPC
::
LI
&&
DefOpc
!=
PPC
::
LI8
)
return
false
;
if
(
!
DefMI
->
getOperand
(
1
)
.
isImm
(
)
)
return
false
;
if
(
DefMI
->
getOperand
(
1
)
.
getImm
(
)
!=
0
)
return
false
;
const
MCInstrDesc
&
UseMCID
=
UseMI
->
getDesc
(
)
;
if
(
UseMCID
.
isPseudo
(
)
)
return
false
;
unsigned
UseIdx
;
for
(
UseIdx
=
0
;
UseIdx
<
UseMI
->
getNumOperands
(
)
;
++
UseIdx
)
if
(
UseMI
->
getOperand
(
UseIdx
)
.
isReg
(
)
&&
UseMI
->
getOperand
(
UseIdx
)
.
getReg
(
)
==
Reg
)
break
;
assert
(
UseIdx
<
UseMI
->
getNumOperands
(
)
&&
"Cannot find Reg in UseMI"
)
;
assert
(
UseIdx
<
UseMCID
.
getNumOperands
(
)
&&
"No operand description for Reg"
)
;
const
MCOperandInfo
*
UseInfo
=
&
UseMCID
.
OpInfo
[
UseIdx
]
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
if
(
UseInfo
->
RegClass
!=
1
)
return
false
;
}
else
{
if
(
UseInfo
->
RegClass
!=
PPC
::
GPRC_NOR0RegClassID
&&
UseInfo
->
RegClass
!=
PPC
::
G8RC_NOX0RegClassID
)
return
false
;
}
if
(
UseInfo
->
Constraints
!=
0
)
return
false
;
unsigned
ZeroReg
;
if
(
UseInfo
->
isLookupPtrRegClass
(
)
)
{
bool
isPPC64
=
TM
.
getSubtargetImpl
(
)
->
isPPC64
(
)
;
ZeroReg
=
isPPC64
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
else
{
ZeroReg
=
UseInfo
->
RegClass
==
PPC
::
G8RC_NOX0RegClassID
PPC
::
ZERO8
:
PPC
::
ZERO
;
}
bool
DeleteDef
=
MRI
->
hasOneNonDBGUse
(
Reg
)
;
UseMI
->
getOperand
(
UseIdx
)
.
setReg
(
ZeroReg
)
;
if
(
DeleteDef
)
DefMI
->
eraseFromParent
(
)
;
return
true
;
}
</s>

Reg is known to be defined by a move immediate instruction , try to fold the immediate into the use instruction .


<s> bool function_instance :: reads_global_state_p ( ) const { unsigned int flags = call_properties ( ) ; if ( flags & CP_READ_FPCR ) return true ; return flags & ( CP_READ_MEMORY | CP_READ_CSR ) ; } </s>

Return true if calls to the function could read some form of global state .


<s> void rs6000_call_aix ( rtx value , rtx func_desc , rtx flag , rtx cookie ) { const bool direct_call_p = GET_CODE ( func_desc ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( func_desc ) ; rtx toc_reg = gen_rtx_REG ( Pmode , TOC_REGNUM ) ; rtx toc_load = NULL_RTX ; rtx toc_restore = NULL_RTX ; rtx func_addr ; rtx abi_reg = NULL_RTX ; rtx call [ 4 ] ; int n_call ; rtx insn ; if ( INTVAL ( cookie ) & CALL_LONG ) func_desc = rs6000_longcall_ref ( func_desc ) ; if ( GET_CODE ( func_desc ) != SYMBOL_REF || ( DEFAULT_ABI == ABI_AIX && ! SYMBOL_REF_FUNCTION_P ( func_desc ) ) ) { rtx stack_ptr = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; rtx stack_toc_offset = GEN_INT ( RS6000_TOC_SAVE_SLOT ) ; rtx stack_toc_mem = gen_frame_mem ( Pmode , gen_rtx_PLUS ( Pmode , stack_ptr , stack_toc_offset ) ) ; rtx stack_toc_unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , stack_toc_offset ) , UNSPEC_TOCSLOT ) ; toc_restore = gen_rtx_SET ( toc_reg , stack_toc_unspec ) ; if ( TARGET_SAVE_TOC_INDIRECT && ! cfun -> calls_alloca ) cfun -> machine -> save_toc_in_prologue = true ; else { MEM_VOLATILE_P ( stack_toc_mem ) = 1 ; emit_move_insn ( stack_toc_mem , toc_reg ) ; } if ( DEFAULT_ABI == ABI_ELFv2 ) { func_addr = gen_rtx_REG ( Pmode , 12 ) ; emit_move_insn ( func_addr , func_desc ) ; abi_reg = func_addr ; } else { func_desc = force_reg ( Pmode , func_desc ) ; func_addr = gen_reg_rtx ( Pmode ) ; emit_move_insn ( func_addr , gen_rtx_MEM ( Pmode , func_desc ) ) ; rtx func_toc_offset = GEN_INT ( GET_MODE_SIZE ( Pmode ) ) ; rtx func_toc_mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , func_desc , func_toc_offset ) ) ; toc_load = gen_rtx_USE ( VOIDmode , func_toc_mem ) ; if ( ! direct_call_p && TARGET_POINTERS_TO_NESTED_FUNCTIONS && ! chain_already_loaded ( get_current_sequence ( ) -> next -> last ) ) { rtx sc_reg = gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ; rtx func_sc_offset = GEN_INT ( 2 * GET_MODE_SIZE ( Pmode ) ) ; rtx func_sc_mem = gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , func_desc , func_sc_offset ) ) ; emit_move_insn ( sc_reg , func_sc_mem ) ; abi_reg = sc_reg ; } } } else { abi_reg = toc_reg ; func_addr = func_desc ; } call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , flag ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; n_call = 1 ; if ( toc_load ) call [ n_call ++ ] = toc_load ; if ( toc_restore ) call [ n_call ++ ] = toc_restore ; call [ n_call ++ ] = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( n_call , call ) ) ; insn = emit_call_insn ( insn ) ; if ( abi_reg ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , abi_reg ) ; } </s>

Expand code to perform a call under the AIX or ELFv2 ABI .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequiredID ( LoopSimplifyID ) ; AU . addRequiredID ( LCSSAID ) ; AU . addPreservedID ( LCSSAID ) ; AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void HexagonTargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB ) { PB . registerLateLoopOptimizationsEPCallback ( [ = ] ( LoopPassManager & LPM , OptimizationLevel Level ) { LPM . addPass ( HexagonLoopIdiomRecognitionPass ( ) ) ; } ) ; PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , OptimizationLevel Level ) { LPM . addPass ( HexagonVectorLoopCarriedReusePass ( ) ) ; } ) ; } </s>

Invoke the PassBuilder callback registration .


<s> static bool expand_vec_perm_interleave3 ( struct expand_vec_perm_d * d ) { unsigned i , nelt ; rtx ( * gen ) ( rtx , rtx , rtx ) ; if ( d -> one_operand_p ) return false ; if ( TARGET_AVX2 && GET_MODE_SIZE ( d -> vmode ) == 32 ) ; else if ( TARGET_AVX && ( d -> vmode == V8SFmode || d -> vmode == V4DFmode ) ) ; else return false ; nelt = d -> nelt ; if ( d -> perm [ 0 ] != 0 && d -> perm [ 0 ] != nelt / 2 ) return false ; for ( i = 0 ; i < nelt ; i += 2 ) if ( d -> perm [ i ] != d -> perm [ 0 ] + i / 2 || d -> perm [ i + 1 ] != d -> perm [ 0 ] + i / 2 + nelt ) return false ; if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V32QImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv32qi ; else gen = gen_vec_interleave_lowv32qi ; break ; case E_V16HImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv16hi ; else gen = gen_vec_interleave_lowv16hi ; break ; case E_V8SImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv8si ; else gen = gen_vec_interleave_lowv8si ; break ; case E_V4DImode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv4di ; else gen = gen_vec_interleave_lowv4di ; break ; case E_V8SFmode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv8sf ; else gen = gen_vec_interleave_lowv8sf ; break ; case E_V4DFmode : if ( d -> perm [ 0 ] ) gen = gen_vec_interleave_highv4df ; else gen = gen_vec_interleave_lowv4df ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( d -> target , d -> op0 , d -> op1 ) ) ; return true ; } </s>

A subroutine of ix86_expand_vec_perm_builtin_1 . Try to simplify a two vector permutation using 2 intra-lane interleave insns and cross-lane shuffle for 32-byte vectors .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
,
Reloc
::
Model
_RM
,
MipsTargetMachine
*
_TM
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
,
HasFPIdx
(
false
)
,
InMips16Mode
(
false
)
,
InMips16HardFloat
(
Mips16HardFloat
)
,
InMicroMipsMode
(
false
)
,
HasDSP
(
false
)
,
HasDSPR2
(
false
)
,
AllowMixed16_32
(
Mixed16_32
|
Mips_Os16
)
,
Os16
(
Mips_Os16
)
,
HasMSA
(
false
)
,
RM
(
_RM
)
,
OverrideMode
(
NoOverride
)
,
TM
(
_TM
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
PreviousInMips16Mode
=
InMips16Mode
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
UseSmallSection
=
!
IsLinux
&&
(
RM
==
Reloc
::
Static
)
;
if
(
inMips16Mode
(
)
)
HasBitCount
=
false
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"
Mips


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < TargetPassConfig > ( ) ; AU . addRequired < LoopInfoWrapperPass > ( ) ; } </s>


<s> static inline bool rs6000_builtin_type_compatible ( tree t , int id ) { tree builtin_type ; builtin_type = rs6000_builtin_type ( id ) ; if ( INTEGRAL_TYPE_P ( t ) && INTEGRAL_TYPE_P ( builtin_type ) ) return true ; else return lang_hooks . types_compatible_p ( t , builtin_type ) ; } </s>

Return true iff ARGTYPE can be compatibly passed as PARMTYPE .


"  Skipping pass: no machine model present.\n"


<s> unsigned PPCFastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 ) { const TargetRegisterClass * UseRC = ( RC == & PPC :: GPRCRegClass ? & PPC :: GPRC_and_GPRC_NOR0RegClass : ( RC == & PPC :: G8RCRegClass ? & PPC :: G8RC_and_G8RC_NOX0RegClass : RC ) ) ; return FastISel :: fastEmitInst_r ( MachineInstOpcode , UseRC , Op0 ) ; } </s>

Emit a MachineInstr with one register operand and a result register in the given register class .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function :: ArgumentListType & Args , ArrayRef < unsigned > VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; SmallVector < MVT , 8 > ArgTys ; for ( auto & Arg : Args ) ArgTys . push_back ( MVT :: getVT ( Arg . getType ( ) ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; return handleAssignments ( MIRBuilder , AssignFn , ArgTys , VRegs , [ ] ( MachineIRBuilder & MIRBuilder , unsigned ValReg , unsigned PhysReg ) { MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg ) ; MIRBuilder . buildCopy ( ValReg , PhysReg ) ; } ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> void MandarinFrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MandarinMachineFunctionInfo * FuncInfo = MF . getInfo < MandarinMachineFunctionInfo > ( ) ; const MandarinInstrInfo & TII = * static_cast < const MandarinInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( hasFP ( MF ) ) { MFI -> setOffsetAdjustment ( - StackSize ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MD :: STORELri ) , MD :: R31 ) . addImm ( 0 ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MD :: MOVrr ) , MD :: R31 ) . addReg ( MD :: R30 ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( MD :: R31 ) ; } if ( StackSize ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( MD :: ADDri ) , MD :: R30 ) . addReg ( MD :: R30 ) . addImm ( StackSize ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool M680x0RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > 1 ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < Register > Regs ) { MIRBuilder . buildMerge ( VRegs [ Idx ] [ 0 ] , Regs ) ; } ) ) return false ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_X86 ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>


<s> bool NVPTXLowerAlloca :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; bool Changed = false ; for ( auto & BB : F ) for ( auto & I : BB ) { if ( auto allocaInst = dyn_cast < AllocaInst > ( & I ) ) { Changed = true ; auto ETy = allocaInst -> getAllocatedType ( ) ; auto LocalAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_LOCAL ) ; auto NewASCToLocal = new AddrSpaceCastInst ( allocaInst , LocalAddrTy , "" ) ; auto GenericAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_GENERIC ) ; auto NewASCToGeneric = new AddrSpaceCastInst ( NewASCToLocal , GenericAddrTy , "" ) ; NewASCToLocal -> insertAfter ( allocaInst ) ; NewASCToGeneric -> insertAfter ( NewASCToLocal ) ; for ( Value :: use_iterator UI = allocaInst -> use_begin ( ) , UE = allocaInst -> use_end ( ) ; UI != UE ; ) { const auto & AllocaUse = * UI ++ ; auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto GI = dyn_cast < GetElementPtrInst > ( AllocaUse . getUser ( ) ) ; if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto BI = dyn_cast < BitCastInst > ( AllocaUse . getUser ( ) ) ; if ( BI && BI -> getOperand ( 0 ) == allocaInst ) { BI -> setOperand ( 0 , NewASCToGeneric ) ; continue ; } } } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void function_builder :: apply_predication ( const function_instance & instance , tree return_type , vec < tree > & argument_types ) const { if ( instance . base -> has_merge_operand_p ( ) ) if ( instance . pred == PRED_TYPE_tu || instance . pred == PRED_TYPE_tum || instance . pred == PRED_TYPE_tumu || instance . pred == PRED_TYPE_mu ) argument_types . quick_insert ( 0 , return_type ) ; vector_type_index mask_type_index = function_types [ instance . type . index ] . type_indexes [ RVV_BASE_mask ] ; tree mask_type = builtin_types [ mask_type_index ] . vector ; if ( instance . pred == PRED_TYPE_m || instance . pred == PRED_TYPE_tum || instance . pred == PRED_TYPE_tumu || instance . pred == PRED_TYPE_mu ) argument_types . quick_insert ( 0 , mask_type ) ; if ( instance . base -> apply_vl_p ( ) ) argument_types . quick_push ( size_type_node ) ; } </s>


<s> tree fully_fold_convert ( tree type , tree expr ) { tree result = fold_convert ( type , expr ) ; bool maybe_const = true ; if ( ! c_dialect_cxx ( ) ) result = c_fully_fold ( result , false , & maybe_const ) ; return result ; } </s>

In addition to calling fold_convert for EXPR of type TYPE , also call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be hiding there ( PR47197 ) .


<s> static bool mips_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( mode1 == mode2 || ( ! mips_mode_ok_for_mov_fmt_p ( mode1 ) && ! mips_mode_ok_for_mov_fmt_p ( mode2 ) ) ) ; } </s>


<s> bool RISCVInstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { const unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : break ; case RISCV :: CMove : return true ; case RISCV :: CIncOffset : return ( MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 2 ) . getReg ( ) == RISCV :: X0 ) || ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: C0 ) ; case RISCV :: CIncOffsetImm : return ( MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) || ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: C0 ) ; case RISCV :: FSGNJ_D : case RISCV :: FSGNJ_S : return MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == MI . getOperand ( 2 ) . getReg ( ) ; case RISCV :: ADDI : case RISCV :: ORI : case RISCV :: XORI : return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: X0 ) || ( MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) ; } return MI . isAsCheapAsAMove ( ) ; } </s>

Return true if the instruction is as cheap as a move instruction .


<s> static void arm_init_builtin ( unsigned int fcode , arm_builtin_datum * d , const char * prefix ) { bool print_type_signature_p = false ; char type_signature [ SIMD_MAX_BUILTIN_ARGS ] = { 0 } ; char namebuf [ 60 ] ; tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - 1 ; int arg_num = d -> qualifiers [ 0 ] & qualifier_void ? op_num + 1 : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= 0 ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum arm_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ; if ( qualifiers & qualifier_unsigned ) { type_signature [ arg_num ] = 'u' ; print_type_signature_p = true ; } else if ( qualifiers & qualifier_poly ) { type_signature [ arg_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ arg_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_predicate ) op_mode = HImode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; if ( qualifiers & qualifier_void_pointer ) eltype = qualifiers & qualifier_const ? const_ptr_type_node : ptr_type_node ; else { eltype = arm_simd_builtin_type ( op_mode , ( qualifiers & qualifier_unsigned ) != 0 , ( qualifiers & qualifier_poly ) != 0 ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; } if ( arg_num == 0 ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ; } ftype = build_function_type ( return_type , args ) ; gcc_assert ( ftype != NULL ) ; if ( print_type_signature_p && IN_RANGE ( fcode , ARM_BUILTIN_VFP_BASE , ARM_BUILTIN_ACLE_BASE - 1 ) ) snprintf ( namebuf , sizeof ( namebuf ) , "%s_%s_%s" , prefix , d -> name , type_signature ) ; else snprintf ( namebuf , sizeof ( namebuf ) , "%s_%s" , prefix , d -> name ) ; fndecl = add_builtin_function ( namebuf , ftype , fcode , BUILT_IN_MD , NULL , NULL_TREE ) ; arm_builtin_decls [ fcode ] = fndecl ; } </s>

Set up a builtin . It will use information stored in the argument struct D to derive the builtin 's type signature and name . It will append the name in D to the PREFIX passed and use these to create a builtin declaration that is then stored in 'arm_builtin_decls ' under index FCODE . This FCODE is also written back to D for future use .


<s> const MCPhysReg * Z80RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CC_Save_SaveList ; } </s>


<s> bool X86Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtarget :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtarget :: ANTIDEP_CRITICAL ; CriticalPathRCs . clear ( ) ; return OptLevel >= CodeGenOpt :: Aggressive ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Cpu0 Del Useless jmp"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { const AMDGPUSubtarget & ST = * getAMDGPUTargetMachine ( ) . getSubtargetImpl ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) return createR600MachineScheduler ( C ) ; else if ( ST . enableSIScheduler ( ) ) return createSIMachineScheduler ( C ) ; return nullptr ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static rtx push ( int rn ) { rtx x ; if ( rn == FPUL_REG ) x = gen_push_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_push_fpscr ( ) ; else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return NULL_RTX ; x = gen_push_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_push_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_push ( gen_rtx_REG ( SImode , rn ) ) ; x = frame_insn ( x ) ; add_reg_note ( x , REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ) ; return x ; } </s>

Output RTL to push register RN onto the stack .


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
SmallVectorImpl
<
MCParsedAsmOperand
*
>
&
Operands
)
{
StringRef
Mnemonic
;
if
(
requestsDoubleOperand
(
Name
)
)
{
setFpFormat
(
FP_FORMAT_D
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
Mnemonic
=
Name
;
}
else
{
setDefaultFpFormat
(
)
;
size_t
Start
=
0
,
Next
=
Name
.
find
(
'.'
)
;
Mnemonic
=
Name
.
slice
(
Start
,
Next
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Mnemonic
,
NameLoc
)
)
;
if
(
Next
!=
StringRef
::
npos
)
{
size_t
Dot
=
Name
.
find
(
'.'
,
Next
+
1
)
;
StringRef
Format
=
Name
.
slice
(
Next
,
Dot
)
;
if
(
Dot
==
StringRef
::
npos
)
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
else
{
if
(
Name
.
startswith
(
"c."
)
)
{
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
"."
,
NameLoc
)
)
;
int
Cc
=
ConvertCcString
(
Format
)
;
if
(
Cc
==
1
)
{
return
Error
(
NameLoc
,
"Invalid conditional code"
)
;
}
SMLoc
E
=
SMLoc
::
getFromPointer
(
Parser
.
getTok
(
)
.
getLoc
(
)
.
getPointer
(
)
1
)
;
Operands
.
push_back
(
MipsOperand
::
CreateImm
(
MCConstantExpr
::
Create
(
Cc
,
getContext
(
)
)
,
NameLoc
,
E
)
)
;
}
else
{
return
parseMathOperation
(
Name
,
NameLoc
,
Operands
)
;
}
Format
=
Name
.
slice
(
Dot
,
StringRef
::
npos
)
;
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Format
,
NameLoc
)
)
;
}
setFpFormat
(
Format
)
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
ParseOperand
(
Operands
,
Mnemonic
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
ParseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
Parser
.
eatToEndOfStatement
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
MipsOperand::CreateToken
0
MipsOperand::CreateToken
1
MipsOperand::CreateToken
"c."
MipsOperand::CreateToken
"."
1
"Invalid conditional code"
1
MipsOperand::CreateImm
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
TRI
=
Fn
.
getTarget
(
)
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineFunction
::
iterator
MFI
=
Fn
.
begin
(
)
,
E
=
Fn
.
end
(
)
;
MFI
!=
E
;
++
MFI
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MFI
->
begin
(
)
,
ME
=
MFI
->
end
(
)
;
MI
!=
ME
;
)
{
Modified
|=
runOnInstruction
(
MI
++
)
;
}
}
for
(
std
::
set
<
MachineInstr
*
>
::
iterator
I
=
DeadInstr
.
begin
(
)
,
E
=
DeadInstr
.
end
(
)
;
I
!=
E
;
++
I
)
{
(
*
I
)
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
void
X86AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
Size
=
getFixupKindSize
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
if
(
(
Target
.
isAbsolute
(
)
||
IsResolved
)
&&
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
.
Flags
&
MCFixupKindInfo
::
FKF_IsPCRel
)
{
if
(
Size
>
0
&&
!
isIntN
(
Size
*
8
,
SignedValue
)
)
Asm
.
getContext
(
)
.
reportError
(
Fixup
.
getLoc
(
)
,
"value of "
+
Twine
(
SignedValue
)
+
" is too large for field of "
+
Twine
(
Size
)
+
(
(
Size
==
1
)
" byte."
:
" bytes."
)
)
;
}
else
{
assert
(
(
Size
==
0
||
isIntN
(
Size
*
8
+
1
,
SignedValue
)
)
&&
"Value does not fit in the Fixup field"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void HexagonRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOp , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MB = * MI . getParent ( ) ; MachineFunction & MF = * MB . getParent ( ) ; auto & HST = MF . getSubtarget < HexagonSubtarget > ( ) ; auto & HII = * HST . getInstrInfo ( ) ; auto & HFI = * HST . getFrameLowering ( ) ; Register BP ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; int Offset = HFI . getFrameIndexReference ( MF , FI , BP ) . getFixed ( ) ; int RealOffset = Offset + MI . getOperand ( FIOp + 1 ) . getImm ( ) ; bool IsKill = false ; unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { case Hexagon :: PS_fia : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + 1 ) ; return ; case Hexagon :: PS_fi : MI . setDesc ( HII . get ( Hexagon :: A2_addi ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & Hexagon :: IntRegsRegClass ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( Hexagon :: A2_addi ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = 0 ; IsKill = true ; } MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false , IsKill ) ; MI . getOperand ( FIOp + 1 ) . ChangeToImmediate ( RealOffset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> bool RISCVCleanupVSETVLI :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const RISCVSubtarget & ST = MF . getSubtarget < RISCVSubtarget > ( ) ; if ( ! ST . hasStdExtV ( ) ) return false ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= runOnMachineBasicBlock ( MBB ) ; return Changed ; } </s>


<s>
void
BlackfinRegisterInfo
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
if
(
!
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
!=
0
)
{
assert
(
Amount
%
4
==
0
&&
"Unaligned call frame size"
)
;
if
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKDOWN
)
{
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
else
{
assert
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKUP
&&
"Unknown call frame pseudo instruction"
)
;
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
}
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
FunctionPass
*
GCNPassConfig
::
createRegAllocPass
(
bool
Optimized
)
{
llvm_unreachable
(
"should not be used"
)
;
}
</s>

addMachinePasses helper to create the target-selected or overriden regalloc pass .


<s> static void emit_reg_adjust ( rtx reg1 , int n ) { rtx reg2 ; gcc_assert ( GET_MODE ( reg1 ) == SImode && n >= - 12 && n != 0 && n <= 12 ) ; reg1 = copy_rtx ( reg1 ) ; reg2 = copy_rtx ( reg1 ) ; if ( n < 0 ) emit_insn ( gen_subsi3 ( reg1 , reg2 , GEN_INT ( - n ) ) ) ; else if ( n > 0 ) emit_insn ( gen_addsi3 ( reg1 , reg2 , GEN_INT ( n ) ) ) ; else gcc_unreachable ( ) ; } </s>


<s> void ARMTargetStreamer :: reset ( ) { } </s>

Reset an existing scalar value for Def and a given Instance .


<s> bool X86InstrInfo :: hasLiveCondCodeDef ( MachineInstr * MI ) const { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == X86 :: EFLAGS && ! MO . isDead ( ) ) { return true ; } } return false ; } </s>

True if MI has a condition code def , e.g .


<s> static tree arc_builtin_decl ( unsigned id , bool initialize_p ATTRIBUTE_UNUSED ) { if ( id < ARC_BUILTIN_COUNT ) return arc_bdesc [ id ] . fndecl ; return error_mark_node ; } </s>


<s> const MCSection * AMDGPUMCAsmInfo :: getNonexecutableStackSection ( MCContext & CTX ) const { return 0 ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s> int arm_no_early_alu_shift_value_dep ( rtx producer , rtx consumer ) { rtx value = PATTERN ( producer ) ; rtx op = PATTERN ( consumer ) ; rtx early_op ; if ( GET_CODE ( value ) == COND_EXEC ) value = COND_EXEC_CODE ( value ) ; if ( GET_CODE ( value ) == PARALLEL ) value = XVECEXP ( value , 0 , 0 ) ; value = XEXP ( value , 0 ) ; if ( GET_CODE ( op ) == COND_EXEC ) op = COND_EXEC_CODE ( op ) ; if ( GET_CODE ( op ) == PARALLEL ) op = XVECEXP ( op , 0 , 0 ) ; op = XEXP ( op , 1 ) ; early_op = XEXP ( op , 0 ) ; if ( GET_CODE ( early_op ) != REG ) early_op = XEXP ( early_op , 0 ) ; return ! reg_overlap_mentioned_p ( value , early_op ) ; } </s>

Return nonzero if the CONSUMER instruction ( an ALU op ) does not have an early register shift value dependency on the result of PRODUCER .


"PIC16 Does not have any frame register"


<s>
void
XCoreInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
bool
GRDest
=
XCore
::
GRRegsRegClass
.
contains
(
DestReg
)
;
bool
GRSrc
=
XCore
::
GRRegsRegClass
.
contains
(
SrcReg
)
;
if
(
GRDest
&&
GRSrc
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
XCore
::
ADD_2rus
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
if
(
GRDest
&&
SrcReg
==
XCore
::
SP
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
XCore
::
LDAWSP_ru6
)
,
DestReg
)
.
addImm
(
0
)
;
return
;
}
if
(
DestReg
==
XCore
::
SP
&&
GRSrc
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
XCore
::
SETSP_1r
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> int MipsAsmParser :: tryParseRegister ( StringRef Mnemonic ) { const AsmToken & Tok = Parser . getTok ( ) ; int RegNum = - 1 ; if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase ) ; } else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ; else return RegNum ; if ( isMips64 ( ) && RegNum == Mips :: ZERO_64 ) { if ( Mnemonic . find ( "ddiv" ) != StringRef :: npos ) RegNum = Mips :: ZERO ; } return RegNum ; } </s>

tryParseRegister - parse one register if possible

Mips Mips 1 Mips Mips::ZERO_64 "ddiv" Mips::ZERO


<s> bool SHUXIAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( Count == 0 ) { return true ; } return false ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> void Initialize ( MCContext & ctx , const TargetMachine & TM ) override { TargetLoweringObjectFile :: Initialize ( ctx , TM ) ; TextSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getText ( ) ) ; DataSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getData ( ) ) ; BSSSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLocSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfARangesSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfRangesSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfMacinfoSection = new NVPTXSection ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .

NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX NVPTX


<s>
StringRef
getPassName
(
)
const
override
{
return
"optimise barriers pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> EVT MipsTargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


"Functions with 'no-prototype' attribute must take varargs: "

"Functions with 'no-prototype' attribute should not have params: "

"warning: prototype-less function used with "

"could not derive a function prototype from usage: "

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


"%qE attribute only applies to functions"

"FP registers might be clobbered despite %qE attribute: compile with %<-mgeneral-regs-only%>"

Handle an `` interrupt '' or `` isr '' attribute ; arguments as in struct attribute_spec.handler .


<s> static bool avr_2word_insn_p ( rtx_insn * insn ) { if ( TARGET_SKIP_BUG || ! insn || 2 != get_attr_length ( insn ) ) { return false ; } switch ( INSN_CODE ( insn ) ) { default : return false ; case CODE_FOR_movqi_insn : case CODE_FOR_movuqq_insn : case CODE_FOR_movqq_insn : { rtx set = single_set ( insn ) ; rtx src = SET_SRC ( set ) ; rtx dest = SET_DEST ( set ) ; if ( MEM_P ( dest ) && ( REG_P ( src ) || src == CONST0_RTX ( GET_MODE ( dest ) ) ) ) { return CONSTANT_ADDRESS_P ( XEXP ( dest , 0 ) ) ; } else if ( REG_P ( dest ) && MEM_P ( src ) ) { return CONSTANT_ADDRESS_P ( XEXP ( src , 0 ) ) ; } return false ; } case CODE_FOR_call_insn : case CODE_FOR_call_value_insn : return true ; } } </s>

Helper for jump_over_one_insn_p : Test if INSN is a 2-word instruction and thus is suitable to be skipped by CPSE , SBRC , etc .


<s> bool AArch64InstrInfo :: isTailCall ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case AArch64 :: TCRETURNdi : case AArch64 :: TCRETURNri : return true ; default : return false ; } } </s>

Determines whether Inst is a tail call instruction .


<s> bool HexagonInstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case Hexagon :: C2_cmpeq : case Hexagon :: C2_cmpeqp : case Hexagon :: C2_cmpgt : case Hexagon :: C2_cmpgtp : case Hexagon :: C2_cmpgtu : case Hexagon :: C2_cmpgtup : case Hexagon :: C4_cmpneq : case Hexagon :: C4_cmplte : case Hexagon :: C4_cmplteu : case Hexagon :: C2_cmpeqi : case Hexagon :: C2_cmpgti : case Hexagon :: C2_cmpgtui : case Hexagon :: C4_cmpneqi : case Hexagon :: C4_cmplteui : case Hexagon :: C4_cmpltei : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = ~ 0 ; break ; case Hexagon :: A4_cmpbeq : case Hexagon :: A4_cmpbgt : case Hexagon :: A4_cmpbgtu : case Hexagon :: A4_cmpbeqi : case Hexagon :: A4_cmpbgti : case Hexagon :: A4_cmpbgtui : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = 0xFF ; break ; case Hexagon :: A4_cmpheq : case Hexagon :: A4_cmphgt : case Hexagon :: A4_cmphgtu : case Hexagon :: A4_cmpheqi : case Hexagon :: A4_cmphgti : case Hexagon :: A4_cmphgtui : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; Mask = 0xFFFF ; break ; } switch ( Opc ) { case Hexagon :: C2_cmpeq : case Hexagon :: C2_cmpeqp : case Hexagon :: C2_cmpgt : case Hexagon :: C2_cmpgtp : case Hexagon :: C2_cmpgtu : case Hexagon :: C2_cmpgtup : case Hexagon :: A4_cmpbeq : case Hexagon :: A4_cmpbgt : case Hexagon :: A4_cmpbgtu : case Hexagon :: A4_cmpheq : case Hexagon :: A4_cmphgt : case Hexagon :: A4_cmphgtu : case Hexagon :: C4_cmpneq : case Hexagon :: C4_cmplte : case Hexagon :: C4_cmplteu : SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; return true ; case Hexagon :: C2_cmpeqi : case Hexagon :: C2_cmpgtui : case Hexagon :: C2_cmpgti : case Hexagon :: C4_cmpneqi : case Hexagon :: C4_cmplteui : case Hexagon :: C4_cmpltei : case Hexagon :: A4_cmpbeqi : case Hexagon :: A4_cmpbgti : case Hexagon :: A4_cmpbgtui : case Hexagon :: A4_cmpheqi : case Hexagon :: A4_cmphgti : case Hexagon :: A4_cmphgtui : SrcReg2 = 0 ; Value = MI -> getOperand ( 2 ) . getImm ( ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool ix86_can_use_return_insn_p ( void ) { if ( ix86_function_ms_hook_prologue ( current_function_decl ) ) return false ; if ( ix86_function_naked ( current_function_decl ) ) return false ; if ( ! reload_completed || frame_pointer_needed || cfun -> machine -> func_type != TYPE_NORMAL ) return 0 ; if ( crtl -> args . pops_args && crtl -> args . size >= 32768 ) return 0 ; struct ix86_frame & frame = cfun -> machine -> frame ; return ( frame . stack_pointer_offset == UNITS_PER_WORD && ( frame . nregs + frame . nsseregs ) == 0 ) ; } </s>

Return 1 if it is appropriate to emit ` ret ' instructions in the body of a function . Do this only if the epilogue is simple , needing a couple of insns . Prior to reloading , we ca n't tell how many registers must be saved , so return 0 then . Return 0 if there is no frame marker to de-allocate .


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( isConditionalBranch ( Inst ) || isUnconditionalBranch ( Inst ) ) { int64_t Imm ; Imm = Inst . getOperand ( Inst . getNumOperands ( ) - 1 ) . getImm ( ) ; Target = Addr + Imm ; return true ; } if ( Inst . getOpcode ( ) == CSKY :: BSR32 ) { Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) ; return true ; } switch ( Inst . getOpcode ( ) ) { default : return false ; case CSKY :: LRW16 : case CSKY :: LRW32 : case CSKY :: JSRI32 : case CSKY :: JMPI32 : int64_t Imm = Inst . getOperand ( Inst . getNumOperands ( ) - 1 ) . getImm ( ) ; Target = ( ( Addr + Imm ) & 0xFFFFFFFC ) ; return true ; } return false ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> static bool isShiftedMask ( uint64_t Mask , EVT VT ) { assert ( VT == MVT :: i32 || VT == MVT :: i64 ) ; if ( VT == MVT :: i32 ) return isShiftedMask_32 ( Mask ) ; return isShiftedMask_64 ( Mask ) ; } </s>

Return true if this APInt value contains a non-empty sequence of ones with the remainder zero .


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { if ( VA . getLocInfo ( ) == CCValAssign :: LocInfo :: AExt ) { Size = VA . getLocVT ( ) . getSizeInBits ( ) / 8 ; ValVReg = MIRBuilder . buildAnyExt ( LLT :: scalar ( Size * 8 ) , ValVReg ) -> getOperand ( 0 ) . getReg ( ) ; } auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOStore , Size , 0 ) ; MIRBuilder . buildStore ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> explicit AMDGPULibFunc ( ) : Impl ( std :: unique_ptr < AMDGPULibFuncImpl > ( ) ) { } </s>

Construct an unmangled library function on the fly .


<s> int attr_length_millicode_call ( rtx insn ) { unsigned long distance = - 1 ; unsigned long total = IN_NAMED_SECTION_P ( cfun -> decl ) ? 0 : total_code_bytes ; if ( INSN_ADDRESSES_SET_P ( ) ) { distance = ( total + insn_current_reference_address ( insn ) ) ; if ( distance < total ) distance = - 1 ; } if ( TARGET_64BIT ) { if ( ! TARGET_LONG_CALLS && distance < 7600000 ) return 8 ; return 20 ; } else if ( TARGET_PORTABLE_RUNTIME ) return 24 ; else { if ( ! TARGET_LONG_CALLS && distance < 240000 ) return 8 ; if ( TARGET_LONG_ABS_CALL && ! flag_pic ) return 12 ; return 24 ; } } </s>

Return the attribute length for the millicode call instruction INSN . The length must match the code generated by output_millicode_call . We include the delay slot in the returned length as it is better to over estimate the length than to under estimate it .


Generate rtl for an overlapping load and compare of less than a full load_mode . This assumes that the previous word is part of the block being compared so it 's ok to back up part of a word so we can compare the last unaligned full word that ends at the end of the block . LOAD_MODE is the machine mode for the loads . ISCONST tells whether the remaining length is a constant or in a register . BYTES_REM is the remaining length if ISCONST is true . DIFF is the reg for the difference . CMP_REM is the reg containing the remaining bytes to compare if ! ISCONST . DCOND is the CCUNS reg for the compare if we are doing P9 code with setb . SRC1_ADDR is the first source address . SRC2_ADDR is the second source address . ORIG_SRC1 is the original first source block 's address rtx . ORIG_SRC2 is the original second source block 's address rtx .


" is allocatable: function has no frame pointer"

Return the register ID of the name passed in .


<s> static int hard_regs_intersect_p ( HARD_REG_SET * a , HARD_REG_SET * b ) { HARD_REG_SET c ; COPY_HARD_REG_SET ( c , * a ) ; AND_HARD_REG_SET ( c , * b ) ; GO_IF_HARD_REG_SUBSET ( c , reg_class_contents [ ( int ) NO_REGS ] , lose ) ; return 1 ; lose : return 0 ; } </s>

Determine if two hard register sets intersect . Return 1 if they do .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineModuleInfoWrapperPass > ( ) ; AU . addPreserved < MachineModuleInfoWrapperPass > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void LEGFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( I -> getOpcode ( ) == LEG :: ADJCALLSTACKUP || I -> getOpcode ( ) == LEG :: ADJCALLSTACKDOWN ) { MBB . erase ( I ) ; } return ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

LEG LEG LEG::ADJCALLSTACKUP LEG::ADJCALLSTACKDOWN


<s> bool CSKYAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void VEDAGToDAGISel :: Select ( SDNode * N ) { SDLoc dl ( N ) ; if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { case VEISD :: LEGALAVL : ReplaceNode ( N , N -> getOperand ( 0 ) . getNode ( ) ) ; return ; case VEISD :: VEC_BROADCAST : { MVT SplatResTy = N -> getSimpleValueType ( 0 ) ; if ( SplatResTy . getVectorElementType ( ) != MVT :: i1 ) break ; auto BConst = dyn_cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) ; if ( ! BConst ) break ; bool BCTrueMask = ( BConst -> getSExtValue ( ) != 0 ) ; if ( ! BCTrueMask ) break ; SDValue New ; if ( SplatResTy . getVectorNumElements ( ) == StandardVectorWidth ) { New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( N ) , VE :: VM0 , MVT :: v256i1 ) ; } else if ( SplatResTy . getVectorNumElements ( ) == PackedVectorWidth ) { New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( N ) , VE :: VMP0 , MVT :: v512i1 ) ; } else break ; ReplaceNode ( N , New . getNode ( ) ) ; return ; } case VEISD :: GLOBAL_BASE_REG : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> static bool rs6000_reg_live_or_pic_offset_p ( int reg ) { if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || ! constant_pool_empty_p ( ) ) ) return true ; if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) && flag_pic ) return true ; } return ( ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) ) && ! call_used_regs [ reg ] ) ; } </s>

Determine whether the gp REG is really used .


<s>
virtual
StringRef
getPassName
(
)
const
{
return
StringRef
(
"SHUXI Assembly Printer"
)
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static bool any_set_in_bb_p ( hash_set < set_info * > sets , const bb_info * bb ) { for ( const set_info * set : sets ) if ( set -> bb ( ) -> index ( ) == bb -> index ( ) ) return true ; return false ; } </s>

Return true if there is an INSN in insns staying in the block BB .


<s> void s390_trampoline_template ( FILE * file ) { rtx op [ 2 ] ; op [ 0 ] = gen_rtx_REG ( Pmode , 0 ) ; op [ 1 ] = gen_rtx_REG ( Pmode , 1 ) ; if ( TARGET_64BIT ) { output_asm_insn ( "basr\t%1,0" , op ) ; output_asm_insn ( "lmg\t%0,%1,14(%1)" , op ) ; output_asm_insn ( "br\t%1" , op ) ; ASM_OUTPUT_SKIP ( file , ( HOST_WIDE_INT ) ( TRAMPOLINE_SIZE - 10 ) ) ; } else { output_asm_insn ( "basr\t%1,0" , op ) ; output_asm_insn ( "lm\t%0,%1,6(%1)" , op ) ; output_asm_insn ( "br\t%1" , op ) ; ASM_OUTPUT_SKIP ( file , ( HOST_WIDE_INT ) ( TRAMPOLINE_SIZE - 8 ) ) ; } } </s>

Output assembly code for the trampoline template to stdio stream FILE . On S/390 , we use gpr 1 internally in the trampoline code ; gpr 0 is used to hold the static chain .


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
void
SIRegisterInfo
::
resolveFrameIndex
(
MachineInstr
&
MI
,
unsigned
BaseReg
,
int64_t
Offset
)
const
{
MachineBasicBlock
*
MBB
=
MI
.
getParent
(
)
;
MachineFunction
*
MF
=
MBB
->
getParent
(
)
;
const
SISubtarget
&
Subtarget
=
MF
->
getSubtarget
<
SISubtarget
>
(
)
;
const
SIInstrInfo
*
TII
=
Subtarget
.
getInstrInfo
(
)
;
bool
SeenFI
=
false
;
for
(
const
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
MO
.
isFI
(
)
)
{
if
(
SeenFI
)
llvm_unreachable
(
"should not see multiple frame indices"
)
;
SeenFI
=
true
;
}
}
MachineOperand
*
FIOp
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
vaddr
)
;
assert
(
FIOp
&&
FIOp
->
isFI
(
)
&&
"frame index must be address operand"
)
;
assert
(
TII
->
isMUBUF
(
MI
)
)
;
MachineOperand
*
OffsetOp
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
offset
)
;
int64_t
NewOffset
=
OffsetOp
->
getImm
(
)
+
Offset
;
if
(
isUInt
<
12
>
(
NewOffset
)
)
{
FIOp
->
ChangeToRegister
(
BaseReg
,
false
)
;
OffsetOp
->
setImm
(
NewOffset
)
;
return
;
}
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
unsigned
NewReg
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
VGPR_32RegClass
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
assert
(
Offset
!=
0
&&
"Non-zero offset expected"
)
;
unsigned
UnusedCarry
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
SReg_64RegClass
)
;
unsigned
OffsetReg
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
SReg_32RegClass
)
;
BuildMI
(
*
MBB
,
MI
,
DL
,
TII
->
get
(
AMDGPU
::
S_MOV_B32
)
,
OffsetReg
)
.
addImm
(
Offset
)
;
BuildMI
(
*
MBB
,
MI
,
DL
,
TII
->
get
(
AMDGPU
::
V_ADD_I32_e64
)
,
NewReg
)
.
addReg
(
UnusedCarry
,
RegState
::
Define
|
RegState
::
Dead
)
.
addReg
(
OffsetReg
,
RegState
::
Kill
)
.
addReg
(
BaseReg
)
;
FIOp
->
ChangeToRegister
(
NewReg
,
false
)
;
}
</s>

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; if ( AMDGPU :: isShader ( CallConv ) ) { CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; } else { analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & R600 :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUASI . CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = Subtarget -> getExplicitKernelArgOffset ( MF ) + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( Offset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , 4 , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
void
MSP430FrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
MSP430MachineFunctionInfo
*
MSP430FI
=
MF
.
getInfo
<
MSP430MachineFunctionInfo
>
(
)
;
const
MSP430InstrInfo
&
TII
=
*
static_cast
<
const
MSP430InstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
uint64_t
NumBytes
=
0
;
if
(
hasFP
(
MF
)
)
{
uint64_t
FrameSize
=
StackSize
2
;
NumBytes
=
FrameSize
MSP430FI
->
getCalleeSavedFrameSize
(
)
;
MFI
.
setOffsetAdjustment
(
NumBytes
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
PUSH16r
)
)
.
addReg
(
MSP430
::
R4
,
RegState
::
Kill
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
MOV16rr
)
,
MSP430
::
R4
)
.
addReg
(
MSP430
::
SP
)
;
for
(
MachineFunction
::
iterator
I
=
std
::
next
(
MF
.
begin
(
)
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
I
->
addLiveIn
(
MSP430
::
R4
)
;
}
else
NumBytes
=
StackSize
MSP430FI
->
getCalleeSavedFrameSize
(
)
;
while
(
MBBI
!=
MBB
.
end
(
)
&&
(
MBBI
->
getOpcode
(
)
==
MSP430
::
PUSH16r
)
)
++
MBBI
;
if
(
MBBI
!=
MBB
.
end
(
)
)
DL
=
MBBI
->
getDebugLoc
(
)
;
if
(
NumBytes
)
{
if
(
NumBytes
)
{
MachineInstr
*
MI
=
BuildMI
(
MBB
,
MBBI
,
DL
,
TII
.
get
(
MSP430
::
SUB16ri
)
,
MSP430
::
SP
)
.
addReg
(
MSP430
::
SP
)
.
addImm
(
NumBytes
)
;
MI
->
getOperand
(
3
)
.
setIsDead
(
)
;
}
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static rtx safe_vector_operand ( rtx x , machine_mode mode ) { if ( x != const0_rtx ) return x ; x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( x , CONST0_RTX ( SImode ) ) ) ; return gen_lowpart ( mode , x ) ; } </s>

Errors in the source file can cause expand_expr to return const0_rtx where we expect a vector . To avoid crashing , use one of the vector clear instructions .


<s> void reset ( ) { TentativelyCommuting = false ; Declined = false ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> rtx aarch64_simd_gen_const_vector_dup ( machine_mode mode , HOST_WIDE_INT val ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits ) ; int i ; rtx cache = GEN_INT ( val ) ; for ( i = 0 ; i < nunits ; i ++ ) RTVEC_ELT ( v , i ) = cache ; return gen_rtx_CONST_VECTOR ( mode , v ) ; } </s>


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( ConstantSDNode * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { uint64_t Bytes = CSize -> getZExtValue ( ) ; if ( Bytes >= 1 && Bytes <= 0x100 ) { return DAG . getNode ( SystemZISD :: MVC , DL , MVT :: Other , Chain , Dst , Src , Size ) ; } } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ 1 0x100 SystemZISD::MVC MVT::Other


<s> bool mips_split_move_p ( rtx dest , rtx src , enum mips_split_type split_type ) { if ( mips_mult_move_p ( dest , src , split_type ) ) return false ; unsigned int size = GET_MODE_SIZE ( GET_MODE ( dest ) ) ; if ( size == 8 && FP_REG_RTX_P ( src ) && FP_REG_RTX_P ( dest ) ) return false ; if ( size == 8 && ISA_HAS_LDC1_SDC1 ) { if ( FP_REG_RTX_P ( dest ) && MEM_P ( src ) ) return false ; if ( FP_REG_RTX_P ( src ) && MEM_P ( dest ) ) return false ; } if ( MSA_SUPPORTED_MODE_P ( GET_MODE ( dest ) ) ) return mips_split_128bit_move_p ( dest , src ) ; return size > UNITS_PER_WORD ; } </s>

Return true if a move from SRC to DEST should be split into two . SPLIT_TYPE describes the split condition .


<s> bool error ( const StringRef & Msg , const AsmToken & Tok ) { return Parser . Error ( Tok . getLoc ( ) , Msg + Tok . getString ( ) ) ; } </s>

Convenience method for printing `` error : `` to the given stream .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
StringRef
RISCVMCExpr
::
getVariantKindName
(
VariantKind
Kind
)
{
switch
(
Kind
)
{
case
VK_RISCV_Invalid
:
case
VK_RISCV_None
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
case
VK_RISCV_LO
:
return
"lo"
;
case
VK_RISCV_HI
:
return
"hi"
;
case
VK_RISCV_PCREL_LO
:
return
"pcrel_lo"
;
case
VK_RISCV_PCREL_HI
:
return
"pcrel_hi"
;
case
VK_RISCV_GOT_HI
:
return
"got_pcrel_hi"
;
case
VK_RISCV_TPREL_LO
:
return
"tprel_lo"
;
case
VK_RISCV_TPREL_HI
:
return
"tprel_hi"
;
case
VK_RISCV_TPREL_ADD
:
return
"tprel_add"
;
case
VK_RISCV_TLS_GOT_HI
:
return
"tls_ie_pcrel_hi"
;
case
VK_RISCV_TLS_GD_HI
:
return
"tls_gd_pcrel_hi"
;
case
VK_RISCV_CAPTAB_PCREL_HI
:
return
"captab_pcrel_hi"
;
case
VK_RISCV_TPREL_CINCOFFSET
:
return
"tprel_cincoffset"
;
case
VK_RISCV_TLS_IE_CAPTAB_PCREL_HI
:
return
"tls_ie_captab_pcrel_hi"
;
case
VK_RISCV_TLS_GD_CAPTAB_PCREL_HI
:
return
"tls_gd_captab_pcrel_hi"
;
case
VK_RISCV_CALL
:
return
"call"
;
case
VK_RISCV_CALL_PLT
:
return
"call_plt"
;
case
VK_RISCV_CCALL
:
return
"ccall"
;
case
VK_RISCV_32_PCREL
:
return
"32_pcrel"
;
}
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .

RISCV
RISCV
RISCV
RISCV
"Invalid ELF symbol kind"
RISCV
"lo"
RISCV
"hi"
RISCV
"pcrel_lo"
RISCV
"pcrel_hi"
RISCV
"got_pcrel_hi"
RISCV
"tprel_lo"
RISCV
"tprel_hi"
RISCV
"tprel_add"
RISCV
"tls_ie_pcrel_hi"
RISCV
"tls_gd_pcrel_hi"
RISCV
"captab_pcrel_hi"
RISCV
"tprel_cincoffset"
RISCV
"tls_ie_captab_pcrel_hi"
RISCV
"tls_gd_captab_pcrel_hi"
RISCV
"call"
RISCV
"call_plt"
RISCV
"ccall"
RISCV
"32_pcrel"
"Invalid ELF symbol kind"


<s> void MSP430RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = 0 ; if ( Old -> getOpcode ( ) == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"X86 AT&T-Style Assembly Printer"
;
}
</s>


<s> const char * VideoCore4TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case VideoCore4ISD :: RET_FLAG : return "VideoCore4ISD::RET_FLAG" ; case VideoCore4ISD :: CALL : return "VideoCore4ISD::CALL" ; case VideoCore4ISD :: GLOBAL : return "VideoCore4ISD::GLOBAL" ; case VideoCore4ISD :: BR_JT : return "VideoCore4ISD::BR_JT" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const PatmosRegisterInfo * getRegisterInfo ( ) const override { return ( const PatmosRegisterInfo * ) & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Mips ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
getParser
(
)
.
setParsingInlineAsm
(
false
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
getParser
(
)
.
setParsingInlineAsm
(
true
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_proc"
)
return
parseDirectiveFPOProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_setframe"
)
return
parseDirectiveFPOSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_pushreg"
)
return
parseDirectiveFPOPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalloc"
)
return
parseDirectiveFPOStackAlloc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endprologue"
)
return
parseDirectiveFPOEndPrologue
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endproc"
)
return
parseDirectiveFPOEndProc
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static int c6x_issue_rate ( void ) { return 8 ; } </s>

Implement the TARGET_SCHED_ISSUE_RATE hook .


<s>
void
BT
::
run
(
)
{
reset
(
)
;
assert
(
FlowQ
.
empty
(
)
)
;
typedef
GraphTraits
<
const
MachineFunction
*
>
MachineFlowGraphTraits
;
const
MachineBasicBlock
*
Entry
=
MachineFlowGraphTraits
::
getEntryNode
(
&
MF
)
;
unsigned
MaxBN
=
0
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
assert
(
I
->
getNumber
(
)
>=
0
&&
"Disconnected block"
)
;
unsigned
BN
=
I
->
getNumber
(
)
;
if
(
BN
>
MaxBN
)
MaxBN
=
BN
;
}
BitVector
BlockScanned
(
MaxBN
+
1
)
;
int
EntryN
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
1
,
EntryN
)
)
;
while
(
!
FlowQ
.
empty
(
)
)
{
CFGEdge
Edge
=
FlowQ
.
front
(
)
;
FlowQ
.
pop
(
)
;
if
(
EdgeExec
.
count
(
Edge
)
)
continue
;
EdgeExec
.
insert
(
Edge
)
;
ReachedBB
.
insert
(
Edge
.
second
)
;
const
MachineBasicBlock
&
B
=
*
MF
.
getBlockNumbered
(
Edge
.
second
)
;
MachineBasicBlock
::
const_iterator
It
=
B
.
begin
(
)
,
End
=
B
.
end
(
)
;
while
(
It
!=
End
&&
It
->
isPHI
(
)
)
{
const
MachineInstr
&
PI
=
*
It
++
;
InstrExec
.
insert
(
&
PI
)
;
visitPHI
(
PI
)
;
}
if
(
BlockScanned
[
Edge
.
second
]
)
continue
;
BlockScanned
[
Edge
.
second
]
=
true
;
while
(
It
!=
End
&&
!
It
->
isBranch
(
)
)
{
const
MachineInstr
&
MI
=
*
It
++
;
InstrExec
.
insert
(
&
MI
)
;
visitNonBranch
(
MI
)
;
}
if
(
It
==
End
)
{
MachineFunction
::
const_iterator
BIt
=
B
.
getIterator
(
)
;
MachineFunction
::
const_iterator
Next
=
std
::
next
(
BIt
)
;
if
(
Next
!=
MF
.
end
(
)
&&
B
.
isSuccessor
(
&
*
Next
)
)
{
int
ThisN
=
B
.
getNumber
(
)
;
int
NextN
=
Next
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
ThisN
,
NextN
)
)
;
}
}
else
{
visitBranchesFrom
(
*
It
)
;
}
}
if
(
Trace
)
print_cells
(
dbgs
(
)
<<
"Cells after propagation:\n"
)
;
}
</s>

Run the analysis pass over a function and produce a dominator tree .


<s> void RISCVTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_4 ) ; else emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_16 ) ; std :: string Arch = "rv32" ; if ( STI . hasFeature ( RISCV :: Feature64Bit ) ) Arch = "rv64" ; if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) Arch += "e1p9" ; else Arch += "i2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtM ) ) Arch += "_m2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtA ) ) Arch += "_a2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtF ) ) Arch += "_f2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtD ) ) Arch += "_d2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtC ) ) Arch += "_c2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtV ) ) Arch += "_v0p10" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZfh ) ) Arch += "_zfh0p1" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZba ) ) Arch += "_zba0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbb ) ) Arch += "_zbb0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbc ) ) Arch += "_zbc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbe ) ) Arch += "_zbe0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbf ) ) Arch += "_zbf0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbm ) ) Arch += "_zbm0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbp ) ) Arch += "_zbp0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbr ) ) Arch += "_zbr0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbs ) ) Arch += "_zbs0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZbt ) ) Arch += "_zbt0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZvamo ) ) Arch += "_zvamo0p10" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZvlsseg ) ) Arch += "_zvlsseg0p10" ; emitTextAttribute ( RISCVAttrs :: ARCH , Arch ) ; } </s>

Emit the build attributes that only depend on the hardware that we expect .


<s> const X86Subtarget * X86TargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . hasFnAttribute ( "use-soft-float" ) && F . getFnAttribute ( "use-soft-float" ) . getValueAsString ( ) == "true" ; if ( SoftFloat ) FS += FS . empty ( ) ? "+soft-float" : ",+soft-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < X86Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static void mips_sim_record_set ( rtx x , const_rtx pat ATTRIBUTE_UNUSED , void * data ) { struct mips_sim * state ; state = ( struct mips_sim * ) data ; if ( REG_P ( x ) ) { unsigned int regno , end_regno ; end_regno = END_REGNO ( x ) ; for ( regno = REGNO ( x ) ; regno < end_regno ; regno ++ ) { state -> last_set [ regno ] . insn = mips_sim_insn ; state -> last_set [ regno ] . time = state -> time ; } } } </s>

mips_sim_insn has just set X. Update the LAST_SET array in simulation state DATA .


<s> static bool ft32_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { if ( arg . aggregate_type_p ( ) ) return true ; unsigned HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; return size > 4 * 6 ; } </s>

Return non-zero if the function argument described by TYPE is to be passed by reference .


<s> TargetLowering :: ConstraintType HexagonTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'q' : case 'v' : if ( Subtarget . useHVXOps ( ) ) return C_RegisterClass ; break ; case 'a' : return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool RISCVTargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { if ( VT . isScalarInteger ( ) ) { if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) > Subtarget . getXLen ( ) ) return false ; if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) { const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + 1 ) . isPowerOf2 ( ) || ( Imm - 1 ) . isPowerOf2 ( ) || ( 1 - Imm ) . isPowerOf2 ( ) || ( - 1 - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtZba ( ) && ! Imm . isSignedIntN ( 12 ) && ( ( Imm - 2 ) . isPowerOf2 ( ) || ( Imm - 4 ) . isPowerOf2 ( ) || ( Imm - 8 ) . isPowerOf2 ( ) ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( 12 ) && Imm . countTrailingZeros ( ) < 12 ) { APInt ImmS = Imm . ashr ( Imm . countTrailingZeros ( ) ) ; if ( ( ImmS + 1 ) . isPowerOf2 ( ) || ( ImmS - 1 ) . isPowerOf2 ( ) || ( 1 - ImmS ) . isPowerOf2 ( ) ) return true ; } } } return false ; } </s>

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> void XCoreTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case XCoreISD :: LADD : case XCoreISD :: LSUB : if ( Op . getResNo ( ) == 1 ) { KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - 1 ) ; } break ; case ISD :: INTRINSIC_W_CHAIN : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) -> getZExtValue ( ) ; switch ( IntNo ) { case Intrinsic :: xcore_getts : KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - 16 ) ; break ; case Intrinsic :: xcore_int : case Intrinsic :: xcore_inct : KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - 8 ) ; break ; case Intrinsic :: xcore_testct : KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - 1 ) ; break ; case Intrinsic :: xcore_testwct : KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - 3 ) ; break ; } } break ; } } </s>


<s> const SparcInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


"LR & FP are always handled in emitEpilogue"

"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> virtual const BlackfinSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>