<s> rtx msp430_subreg ( machine_mode mode , rtx r , machine_mode omode , int byte ) { rtx rv ; gcc_assert ( mode == HImode ) ; if ( GET_CODE ( r ) == SUBREG && SUBREG_BYTE ( r ) == 0 ) { rtx ireg = SUBREG_REG ( r ) ; machine_mode imode = GET_MODE ( ireg ) ; if ( imode == PSImode && mode == HImode && byte == 0 ) rv = gen_rtx_SUBREG ( mode , ireg , byte ) ; else rv = simplify_gen_subreg ( mode , ireg , imode , byte ) ; } else if ( GET_CODE ( r ) == MEM ) { if ( GET_CODE ( XEXP ( r , 0 ) ) == POST_INC && byte == 2 ) byte = 0 ; rv = adjust_address ( r , mode , byte ) ; } else if ( GET_CODE ( r ) == SYMBOL_REF && ( byte == 0 || byte == 2 ) && mode == HImode ) { rv = gen_rtx_ZERO_EXTRACT ( HImode , r , GEN_INT ( 16 ) , GEN_INT ( 8 * byte ) ) ; rv = gen_rtx_CONST ( HImode , r ) ; } else rv = simplify_gen_subreg ( mode , r , omode , byte ) ; if ( ! rv ) gcc_unreachable ( ) ; return rv ; } </s>

Simplify_gen_subreg ( ) does n't handle memory references the way we need it to below , so we use this function for when we must get a valid subreg in a `` natural '' state .


"TargetInstrInfo::findCommutedOpIndices() can't handle bundles"

Returns true iff the routine could find two commutable operands in the given machine instruction .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> static rtx nds32_delegitimize_address ( rtx x ) { x = delegitimize_mem_from_attrs ( x ) ; if ( GET_CODE ( x ) == CONST ) { rtx inner = XEXP ( x , 0 ) ; if ( GET_CODE ( inner ) == PLUS ) inner = XEXP ( inner , 0 ) ; if ( GET_CODE ( inner ) == UNSPEC ) { switch ( XINT ( inner , 1 ) ) { case UNSPEC_GOTINIT : case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLT : case UNSPEC_TLSGD : case UNSPEC_TLSLD : case UNSPEC_TLSIE : case UNSPEC_TLSLE : case UNSPEC_ICT : x = XVECEXP ( inner , 0 , 0 ) ; break ; default : break ; } } } return x ; } </s>

Reorgnize the UNSPEC CONST and return its direct symbol .


<s> void M68kRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const M68kFrameLowering * TFI = getFrameLowering ( MF ) ; MachineOperand & Disp = MI . getOperand ( FIOperandNum - 1 ) ; MachineOperand & Base = MI . getOperand ( FIOperandNum ) ; int Imm = ( int ) ( Disp . getImm ( ) ) ; int FIndex = ( int ) ( Base . getIndex ( ) ) ; bool AfterFPPop = false ; unsigned BasePtr ; if ( hasBasePointer ( MF ) ) BasePtr = ( FIndex < 0 ? FramePtr : getBaseRegister ( ) ) ; else if ( hasStackRealignment ( MF ) ) BasePtr = ( FIndex < 0 ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; Base . ChangeToRegister ( BasePtr , false ) ; int64_t FIOffset ; Register IgnoredFrameReg ; if ( AfterFPPop ) { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FIOffset = MFI . getObjectOffset ( FIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else { FIOffset = TFI -> getFrameIndexReference ( MF , FIndex , IgnoredFrameReg ) . getFixed ( ) ; } if ( BasePtr == StackPtr ) FIOffset += SPAdj ; Disp . ChangeToImmediate ( FIOffset + Imm ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { if ( Subtarget -> allowMixed16_32 ( ) ) const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> MCFragment * MINA32MCExpr :: findAssociatedFragment ( ) const { return Expr -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> bool ScheduleDAGPostRA :: addEdge ( SUnit * SuccSU , const SDep & PredDep ) { if ( SuccSU != & ExitSU ) { if ( Topo . IsReachable ( PredDep . getSUnit ( ) , SuccSU ) ) return false ; Topo . AddPred ( SuccSU , PredDep . getSUnit ( ) ) ; } SuccSU -> addPred ( PredDep , ! PredDep . isArtificial ( ) ) ; return true ; } </s>

Add a DAG edge to the given SU with the given predecessor dependence data .


<s> SDValue WebAssemblyTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : return SDValue ( ) ; case ISD :: VECTOR_SHUFFLE : return performVECTOR_SHUFFLECombine ( N , DCI ) ; } } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> bool HexagonTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_Hexagon ) ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .

Hexagon Hexagon ISD::OutputArg 16 Hexagon


<s> bool enableSubRegLiveness ( ) const override { return true ; } </s>

Enable tracking of subregister liveness in register allocator .


<s> unsigned getExplicitKernelArgOffset ( ) const { return isAmdHsaOS ( ) ? 0 : 36 ; } </s>

Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument .


<s> static rtx alignment_with_canonical_addr ( rtx align ) { rtx canon ; rtx addr = XEXP ( align , 0 ) ; if ( REG_P ( addr ) ) canon = addr ; else if ( GET_CODE ( addr ) == PLUS ) { rtx addrop0 = XEXP ( addr , 0 ) ; rtx addrop1 = XEXP ( addr , 1 ) ; if ( ! REG_P ( addrop0 ) ) addrop0 = force_reg ( GET_MODE ( addrop0 ) , addrop0 ) ; if ( ! REG_P ( addrop1 ) ) addrop1 = force_reg ( GET_MODE ( addrop1 ) , addrop1 ) ; canon = gen_rtx_PLUS ( GET_MODE ( addr ) , addrop0 , addrop1 ) ; } else canon = force_reg ( GET_MODE ( addr ) , addr ) ; return gen_rtx_AND ( GET_MODE ( align ) , canon , GEN_INT ( - 16 ) ) ; } </s>

Return RTX with its address canonicalized to ( reg ) or ( + reg reg ) . Here RTX is an ( & addr ( const_int -16 ) ) . Always return a new copy to avoid problems with combine .


<s>
void
GCNIterativeScheduler
::
schedule
(
)
{
LLVM_DEBUG
(
printLivenessInfo
(
dbgs
(
)
,
RegionBegin
,
RegionEnd
,
LIS
)
;
if
(
!
Regions
.
empty
(
)
&&
Regions
.
back
(
)
->
Begin
==
RegionBegin
)
{
dbgs
(
)
<<
"Max RP: "
;
Regions
.
back
(
)
->
MaxPressure
.
print
(
dbgs
(
)
,
&
MF
.
getSubtarget
<
SISubtarget
>
(
)
)
;
}
dbgs
(
)
<<
'\n'
;
)
;
}
</s>

Schedule - This is called back from ScheduleDAGInstrs : :Run ( ) when it 's time to do some work .


"List of x86 specific tuning parameter names:\n"

Helper function to set ix86_tune_features . IX86_TUNE is the processor type .


<s> bool AArch64TargetMachine :: parseMachineFunctionInfo ( const yaml :: MachineFunctionInfo & MFI , PerFunctionMIParsingState & PFS , SMDiagnostic & Error , SMRange & SourceRange ) const { const auto & YamlMFI = reinterpret_cast < const yaml :: AArch64FunctionInfo & > ( MFI ) ; MachineFunction & MF = PFS . MF ; MF . getInfo < AArch64FunctionInfo > ( ) -> initializeBaseYamlFields ( YamlMFI ) ; return false ; } </s>

Parse out the target 's MachineFunctionInfo from the YAML reprsentation .


<s> bool R600InstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( MI . getOpcode ( ) == AMDGPU :: KILLGT ) { return false ; } else if ( MI . getOpcode ( ) == AMDGPU :: CF_ALU ) { if ( MI . getParent ( ) -> begin ( ) != MachineBasicBlock :: const_iterator ( MI ) ) return false ; return MI . getOperand ( 3 ) . getImm ( ) == 0 && MI . getOperand ( 4 ) . getImm ( ) == 0 ; } else if ( isVector ( MI ) ) { return false ; } else { return AMDGPUInstrInfo :: isPredicable ( MI ) ; } } </s>

Return true if the specified instruction can be predicated .


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == bool_char_type_node ) return "U6__boolc" ; if ( type == bool_short_type_node ) return "U6__bools" ; if ( type == pixel_type_node ) return "u7__pixel" ; if ( type == bool_int_type_node ) return "U6__booli" ; if ( type == bool_long_type_node ) return "U6__booll" ; if ( TARGET_FLOAT128_TYPE ) { if ( type == ieee128_float_type_node ) return "U10__float128" ; if ( type == ibm128_float_type_node ) return "g" ; if ( type == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return ( TARGET_IEEEQUAD ) ? "U10__float128" : "g" ; } if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_ELF && TARGET_LONG_DOUBLE_128 && ! TARGET_IEEEQUAD ) return "g" ; return NULL ; } </s>

AltiVec defines five built-in scalar types that serve as vector elements ; we must teach the compiler how to mangle them . The 128-bit floating point mangling is target-specific as well . MMA defines two built-in types to be used as opaque vector types .


<s> static inline int multcosts ( rtx x ATTRIBUTE_UNUSED ) { if ( sh_multcost >= 0 ) return sh_multcost ; if ( TARGET_SHMEDIA ) return optimize_size ? 2 : 3 ; if ( TARGET_SH2 ) { if ( optimize_size ) return 2 ; return 3 ; } if ( optimize_size ) return 5 ; return 20 ; } </s>


<s> int rl78_force_nonfar_2 ( rtx * operands , rtx ( * gen ) ( rtx , rtx ) ) { int did = 0 ; rtx temp_reg = NULL ; if ( rl78_far_p ( operands [ 0 ] ) ) { temp_reg = operands [ 0 ] ; operands [ 0 ] = gen_reg_rtx ( GET_MODE ( operands [ 0 ] ) ) ; did = 1 ; } if ( ! did ) return 0 ; emit_insn ( gen ( operands [ 0 ] , operands [ 1 ] ) ) ; if ( temp_reg ) emit_move_insn ( temp_reg , operands [ 0 ] ) ; return 1 ; } </s>

Used by various two-operand expanders which can not accept all operands in the `` far '' namespace . Force some such operands into registers so that each pattern has at most one far operand .


<s>
void
HexagonFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
bool
HasAlloca
=
MFI
->
hasVarSizedObjects
(
)
;
bool
HasAligna
=
(
MFI
->
getMaxAlignment
(
)
>
getStackAlignment
(
)
)
;
if
(
!
HasAlloca
||
!
HasAligna
)
return
;
unsigned
LFS
=
MFI
->
getLocalFrameSize
(
)
;
int
Offset
=
LFS
;
for
(
int
i
=
0
,
e
=
MFI
->
getObjectIndexEnd
(
)
;
i
!=
e
;
++
i
)
{
if
(
!
MFI
->
isSpillSlotObjectIndex
(
i
)
||
MFI
->
isDeadObjectIndex
(
i
)
)
continue
;
int
S
=
MFI
->
getObjectSize
(
i
)
;
LFS
+=
S
;
Offset
-=
S
;
MFI
->
mapLocalFrameObject
(
i
,
Offset
)
;
}
MFI
->
setLocalFrameSize
(
LFS
)
;
unsigned
A
=
MFI
->
getLocalFrameMaxAlign
(
)
;
assert
(
A
<=
8
&&
"Unexpected local frame alignment"
)
;
if
(
A
==
0
)
MFI
->
setLocalFrameMaxAlign
(
8
)
;
MFI
->
setUseLocalStackAllocationBlock
(
true
)
;
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool AZPRFrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool check_use_sfunc_addr ( rtx_insn * insn , rtx reg ) { while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( LABEL_P ( insn ) || JUMP_P ( insn ) ) break ; if ( ! INSN_P ( insn ) ) continue ; if ( rtx_sequence * seq = dyn_cast < rtx_sequence * > ( PATTERN ( insn ) ) ) insn = seq -> insn ( 0 ) ; if ( GET_CODE ( PATTERN ( insn ) ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) continue ; return rtx_equal_p ( extract_sfunc_addr ( insn ) , reg ) ; } gcc_unreachable ( ) ; } </s>

Verify that the register in use_sfunc_addr still agrees with the address used in the sfunc . This prevents fill_slots_from_thread from changing use_sfunc_addr . INSN is the use_sfunc_addr instruction , and REG is the register it guards .


<s> static void ix86_init_large_pic_reg ( unsigned int tmp_regno ) { rtx_code_label * label ; rtx tmp_reg ; gcc_assert ( Pmode == DImode ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; LABEL_PRESERVE_P ( label ) = 1 ; tmp_reg = gen_rtx_REG ( Pmode , tmp_regno ) ; gcc_assert ( REGNO ( pic_offset_table_rtx ) != tmp_regno ) ; emit_insn ( gen_set_rip_rex64 ( pic_offset_table_rtx , label ) ) ; emit_insn ( gen_set_got_offset_rex64 ( tmp_reg , label ) ) ; emit_insn ( gen_add2_insn ( pic_offset_table_rtx , tmp_reg ) ) ; const char * name = LABEL_NAME ( label ) ; PUT_CODE ( label , NOTE ) ; NOTE_KIND ( label ) = NOTE_INSN_DELETED_LABEL ; NOTE_DELETED_LABEL_NAME ( label ) = name ; } </s>


<s> unsigned HexagonTTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , Value * Ptr , bool VariableMask , unsigned Alignment ) { return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment ) ; } </s>

Calculate the cost of Gather / Scatter operation .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> int MINA32FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MINA32Subtarget & Subtarget = MF . getSubtarget < MINA32Subtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MINA32RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; FrameReg = RegInfo -> getFrameRegister ( MF ) ; int64_t FrameOffset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ; FrameOffset -= getOffsetOfLocalArea ( ) ; FrameOffset += MFI . getStackSize ( ) ; return FrameOffset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool ia64_extra_constraint ( rtx value , char c ) { switch ( c ) { case 'Q' : return memory_operand ( value , VOIDmode ) && ! MEM_VOLATILE_P ( value ) ; case 'R' : return ( GET_CODE ( value ) == CONST_INT && INTVAL ( value ) >= 1 && INTVAL ( value ) <= 4 ) ; case 'S' : return ( GET_CODE ( value ) == MEM && GET_RTX_CLASS ( GET_CODE ( XEXP ( value , 0 ) ) ) != RTX_AUTOINC && ( reload_in_progress || memory_operand ( value , VOIDmode ) ) ) ; case 'T' : return small_addr_symbolic_operand ( value , VOIDmode ) ; case 'U' : return value == CONST0_RTX ( GET_MODE ( value ) ) ; case 'W' : if ( GET_CODE ( value ) == CONST_VECTOR && GET_MODE_CLASS ( GET_MODE ( value ) ) == MODE_VECTOR_INT ) { value = simplify_subreg ( DImode , value , GET_MODE ( value ) , 0 ) ; return ia64_const_ok_for_letter_p ( INTVAL ( value ) , 'J' ) ; } return false ; case 'Y' : return ( GET_CODE ( value ) == CONST_VECTOR && GET_MODE ( value ) == V2SFmode && ia64_const_double_ok_for_letter_p ( XVECEXP ( value , 0 , 0 ) , 'G' ) && ia64_const_double_ok_for_letter_p ( XVECEXP ( value , 0 , 1 ) , 'G' ) ) ; default : return false ; } } </s>


<s> void BTFDebug :: endModule ( ) { if ( MapDefNotCollected ) { processGlobals ( true ) ; MapDefNotCollected = false ; } processGlobals ( false ) ; processFuncPrototypes ( ) ; for ( auto & DataSec : DataSecEntries ) addType ( std :: move ( DataSec . second ) ) ; for ( auto & Fixup : FixupDerivedTypes ) { StringRef TypeName = Fixup . first ; bool IsUnion = Fixup . second . first ; uint32_t StructTypeId = 0 ; for ( const auto & StructType : StructTypes ) { if ( StructType -> getName ( ) == TypeName ) { StructTypeId = StructType -> getId ( ) ; break ; } } if ( StructTypeId == 0 ) { auto FwdTypeEntry = std :: make_unique < BTFTypeFwd > ( TypeName , IsUnion ) ; StructTypeId = addType ( std :: move ( FwdTypeEntry ) ) ; } for ( auto & DType : Fixup . second . second ) { DType -> setPointeeType ( StructTypeId ) ; } } for ( const auto & TypeEntry : TypeEntries ) TypeEntry -> completeType ( * this ) ; emitBTFSection ( ) ; emitBTFExtSection ( ) ; } </s>

Emit all exception information that should come after the content .


<s> SDValue AMDGPUTargetLowering :: LowerFREM ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue X = Op . getOperand ( 0 ) ; SDValue Y = Op . getOperand ( 1 ) ; SDValue Div = DAG . getNode ( ISD :: FDIV , SL , VT , X , Y ) ; SDValue Floor = DAG . getNode ( ISD :: FTRUNC , SL , VT , Div ) ; SDValue Mul = DAG . getNode ( ISD :: FMUL , SL , VT , Floor , Y ) ; return DAG . getNode ( ISD :: FSUB , SL , VT , X , Mul ) ; } </s>

Split a vector store into multiple scalar stores .

AMDGPU AMDGPU 0 1 ISD::FDIV ISD::FTRUNC ISD::FMUL ISD::FSUB


<s> const RegisterBank & AMDGPURegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC , LLT Ty ) const { if ( & RC == & AMDGPU :: SReg_1RegClass ) return AMDGPU :: VCCRegBank ; if ( TRI -> isSGPRClass ( & RC ) ) { if ( ! Ty . isValid ( ) ) return AMDGPU :: SGPRRegBank ; return Ty == LLT :: scalar ( 1 ) ? AMDGPU :: VCCRegBank : AMDGPU :: SGPRRegBank ; } return TRI -> isAGPRClass ( & RC ) ? AMDGPU :: AGPRRegBank : AMDGPU :: VGPRRegBank ; } </s>

AMDGPU AMDGPU AMDGPU::SReg_1RegClass AMDGPU::VCCRegBank AMDGPU::SGPRRegBank 1 AMDGPU::VCCRegBank AMDGPU::SGPRRegBank AMDGPU::AGPRRegBank AMDGPU::VGPRRegBank


<s> rtx z8k_function_arg ( cumulative_args_t cum_v , enum machine_mode mode , const_tree type , bool named ) { int nregs ; int rn ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; enum machine_mode rmode = ( ( mode == BLKmode ) ? TYPE_MODE ( type ) : mode ) ; if ( mode == BLKmode || mode == VOIDmode ) return 0 ; else nregs = ( GET_MODE_SIZE ( mode ) + 1 ) / 2 ; if ( ! TARGET_REGPARMS ) { return 0 ; } if ( ! named ) { return 0 ; } rn = * cum - ( nregs - 1 ) ; while ( rn >= 2 && ! HARD_REGNO_MODE_OK ( rn , rmode ) ) { rn -- ; } if ( rn < 2 || rn > 7 ) return 0 ; return gen_rtx_REG ( rmode , rn ) ; } </s>

Offset from the stack pointer register to the first location at which outgoing arguments are placed . If not specified , the default value of zero is used . This is the proper value for most machines .


<s> MachineInstr * AMDGPUInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , MachineInstr * LoadMI ) const { return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s>
bool
processBlock
(
MachineBasicBlock
&
MBB
)
{
bool
Changed
=
false
;
MachineRegisterInfo
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
for
(
MachineInstr
&
MI
:
MBB
)
{
if
(
!
MI
.
isFullCopy
(
)
)
continue
;
MachineOperand
&
DstMO
=
MI
.
getOperand
(
0
)
;
MachineOperand
&
SrcMO
=
MI
.
getOperand
(
1
)
;
if
(
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
!
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
SrcRC
=
IsVRReg
(
SrcMO
.
getReg
(
)
,
MRI
)
&
PPC
::
VSHRCRegClass
:
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVRReg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown source for a VSX copy"
)
;
unsigned
NewVReg
=
MRI
.
createVirtualRegister
(
SrcRC
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
SUBREG_TO_REG
)
,
NewVReg
)
.
addImm
(
1
)
.
addOperand
(
SrcMO
)
.
addImm
(
IsVRReg
(
SrcMO
.
getReg
(
)
,
MRI
)
PPC
::
sub_128
:
PPC
::
sub_64
)
;
SrcMO
.
setReg
(
NewVReg
)
;
}
else
if
(
!
IsVSReg
(
DstMO
.
getReg
(
)
,
MRI
)
&&
IsVSReg
(
SrcMO
.
getReg
(
)
,
MRI
)
)
{
Changed
=
true
;
const
TargetRegisterClass
*
DstRC
=
IsVRReg
(
DstMO
.
getReg
(
)
,
MRI
)
&
PPC
::
VSHRCRegClass
:
&
PPC
::
VSLRCRegClass
;
assert
(
(
IsF8Reg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSFReg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVSSReg
(
DstMO
.
getReg
(
)
,
MRI
)
||
IsVRReg
(
DstMO
.
getReg
(
)
,
MRI
)
)
&&
"Unknown destination for a VSX copy"
)
;
unsigned
NewVReg
=
MRI
.
createVirtualRegister
(
DstRC
)
;
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
TII
->
get
(
TargetOpcode
::
COPY
)
,
NewVReg
)
.
addOperand
(
SrcMO
)
;
SrcMO
.
setReg
(
NewVReg
)
;
SrcMO
.
setSubReg
(
IsVRReg
(
DstMO
.
getReg
(
)
,
MRI
)
PPC
::
sub_128
:
PPC
::
sub_64
)
;
}
}
return
Changed
;
}
</s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .


<s> const uint16_t * GBZ80RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { GBZ80 :: BC , GBZ80 :: DE , 0 } ; return CalleeSavedRegs ; } </s>


<s> static rtx loongarch_emit_set ( rtx target , rtx src ) { emit_insn ( gen_rtx_SET ( target , src ) ) ; return target ; } </s>

Emit an instruction of the form ( set TARGET SRC ) .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Fix SGPR live ranges"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
bool
AMDGPUAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MF
.
setAlignment
(
8
)
;
SetupMachineFunction
(
MF
)
;
MCContext
&
Context
=
getObjFileLowering
(
)
.
getContext
(
)
;
const
MCSectionELF
*
ConfigSection
=
Context
.
getELFSection
(
".AMDGPU.config"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
.
SwitchSection
(
ConfigSection
)
;
const
AMDGPUSubtarget
&
STM
=
MF
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
SIProgramInfo
KernelInfo
;
if
(
STM
.
isAmdHsaOS
(
)
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitAmdKernelCodeT
(
MF
,
KernelInfo
)
;
OutStreamer
.
EmitCodeAlignment
(
2
<<
(
MF
.
getAlignment
(
)
1
)
)
;
}
else
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
getSIProgramInfo
(
KernelInfo
,
MF
)
;
EmitProgramInfoSI
(
MF
,
KernelInfo
)
;
}
else
{
EmitProgramInfoR600
(
MF
)
;
}
DisasmLines
.
clear
(
)
;
HexLines
.
clear
(
)
;
DisasmLineMaxLen
=
0
;
EmitFunctionBody
(
)
;
if
(
isVerbose
(
)
)
{
const
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
".AMDGPU.csdata"
,
ELF
::
SHT_PROGBITS
,
0
)
;
OutStreamer
.
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
.
emitRawComment
(
" Kernel info:"
,
false
)
;
OutStreamer
.
emitRawComment
(
" codeLenInByte = "
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumSgprs: "
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" NumVgprs: "
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" FloatMode: "
+
Twine
(
KernelInfo
.
FloatMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" IeeeMode: "
+
Twine
(
KernelInfo
.
IEEEMode
)
,
false
)
;
OutStreamer
.
emitRawComment
(
" ScratchSize: "
+
Twine
(
KernelInfo
.
ScratchSize
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
.
emitRawComment
(
Twine
(
"SQ_PGM_RESOURCES:STACK_SIZE = "
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
".AMDGPU.disasm"
,
ELF
::
SHT_NOTE
,
0
)
)
;
for
(
size_t
i
=
0
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;
Comment
+=
" ; "
+
HexLines
[
i
]
+
"\n"
;
OutStreamer
.
EmitBytes
(
StringRef
(
DisasmLines
[
i
]
)
)
;
OutStreamer
.
EmitBytes
(
StringRef
(
Comment
)
)
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> int fsmbi_const_p ( rtx x ) { if ( CONSTANT_P ( x ) ) { enum immediate_class c = classify_immediate ( x , TImode ) ; return c == IC_FSMBI || ( ! epilogue_completed && c == IC_FSMBI2 ) ; } return 0 ; } </s>

Return TRUE if x is a CONST_INT , CONST_DOUBLE or CONST_VECTOR that can be generated using the fsmbi instruction .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SELECT_CC : return LowerSELECT_CC ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return LowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return LowerEH_RETURN ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return LowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return LowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return LowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return LowerLOAD ( Op , DAG ) ; case ISD :: STORE : return LowerSTORE ( Op , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: ADD : return LowerADD ( Op , DAG ) ; case ISD :: NACL_TP_TLS_OFFSET : return LowerNaClTpTlsOffset ( Op , DAG ) ; case ISD :: NACL_TP_TDB_OFFSET : return LowerNaClTpTdbOffset ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> static int get_arc_condition_code ( rtx comparison ) { switch ( GET_CODE ( comparison ) ) { case EQ : return 2 ; case NE : return 3 ; case GT : return 10 ; case LE : return 11 ; case GE : return 12 ; case LT : return 13 ; case GTU : return 14 ; case LEU : return 15 ; case LTU : return 6 ; case GEU : return 7 ; default : gcc_unreachable ( ) ; } return ( 42 ) ; } </s>

Returns the index of the ARC condition code string in ` arc_condition_codes ' . COMPARISON should be an rtx like ` ( eq ( ... ) ( ... ) ) ' .


"%qE attribute only applies to functions"

"cannot apply both %<longcall%> and %<shortcall%> attributes "

Handle a `` longcall '' or `` shortcall '' attribute ; arguments as in struct attribute_spec.handler .


<s>
void
SparcMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
unsigned
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
if
(
Ctx
.
getAsmInfo
(
)
->
isLittleEndian
(
)
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
unsigned
tlsOpNo
=
0
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
SP
::
TLS_CALL
:
tlsOpNo
=
1
;
break
;
case
SP
::
TLS_ADDrr
:
case
SP
::
TLS_ADDXrr
:
case
SP
::
TLS_LDrr
:
case
SP
::
TLS_LDXrr
:
tlsOpNo
=
3
;
break
;
}
if
(
tlsOpNo
!=
0
)
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
tlsOpNo
)
;
uint64_t
op
=
getMachineOpValue
(
MI
,
MO
,
Fixups
,
STI
)
;
assert
(
op
==
0
&&
"Unexpected operand value!"
)
;
(
void
)
op
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> static Mnode * add_minipool_forward_ref ( Mfix * fix ) { Mnode * max_mp = NULL ; HOST_WIDE_INT max_address = fix -> address + fix -> forwards - minipool_pad ; Mnode * mp ; if ( minipool_vector_head && ( fix -> address + get_attr_length ( fix -> insn ) >= minipool_vector_head -> max_address - fix -> fix_size ) ) return NULL ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { if ( GET_CODE ( fix -> value ) == GET_CODE ( mp -> value ) && fix -> mode == mp -> mode && ( ! LABEL_P ( fix -> value ) || ( CODE_LABEL_NUMBER ( fix -> value ) == CODE_LABEL_NUMBER ( mp -> value ) ) ) && rtx_equal_p ( fix -> value , mp -> value ) ) { mp -> refcount ++ ; return move_minipool_fix_forward_ref ( mp , max_mp , max_address ) ; } if ( max_mp == NULL && mp -> max_address > max_address ) max_mp = mp ; if ( ARM_DOUBLEWORD_ALIGN && max_mp == NULL && fix -> fix_size >= 8 && mp -> fix_size < 8 ) { max_mp = mp ; max_address = mp -> max_address ; } } mp = XNEW ( Mnode ) ; mp -> fix_size = fix -> fix_size ; mp -> mode = fix -> mode ; mp -> value = fix -> value ; mp -> refcount = 1 ; mp -> min_address = - 65536 ; if ( max_mp == NULL ) { mp -> max_address = max_address ; mp -> next = NULL ; mp -> prev = minipool_vector_tail ; if ( mp -> prev == NULL ) { minipool_vector_head = mp ; minipool_vector_label = gen_label_rtx ( ) ; } else mp -> prev -> next = mp ; minipool_vector_tail = mp ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ; else minipool_vector_head = mp ; } max_mp = mp ; while ( mp -> prev != NULL && mp -> prev -> max_address > mp -> max_address - mp -> prev -> fix_size ) { mp -> prev -> max_address = mp -> max_address - mp -> prev -> fix_size ; mp = mp -> prev ; } return max_mp ; } </s>

Add a constant to the minipool for a forward reference . Returns the node added or NULL if the constant will not fit in this pool .


<s> static int nonindexed_address_p ( rtx x , int strict ) { rtx xfoo0 ; if ( GET_CODE ( x ) == REG ) { extern rtx * reg_equiv_mem ; if ( ! reload_in_progress || reg_equiv_mem [ REGNO ( x ) ] == 0 || indirectable_address_p ( reg_equiv_mem [ REGNO ( x ) ] , strict ) ) return 1 ; } if ( indirectable_constant_address_p ( x ) ) return 1 ; if ( indirectable_address_p ( x , strict ) ) return 1 ; xfoo0 = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == MEM && indirectable_address_p ( xfoo0 , strict ) ) return 1 ; if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == POST_INC ) && BASE_REGISTER_P ( xfoo0 , strict ) ) return 1 ; return 0 ; } </s>

Return 1 if x is a valid address not using indexing . ( This much is the easy part . )


<s>
bool
AArch64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"***** AArch64AdvSIMDScalar *****\n"
)
;
if
(
skipFunction
(
mf
.
getFunction
(
)
)
)
return
false
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
mf
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
&
*
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>


<s> void RISCVMCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { unsigned Opcode = MI -> getOpcode ( ) ; if ( ! AsmPrinter . OutStreamer -> hasRawTextSupport ( ) ) Opcode = getShortenedInstr ( Opcode ) ; OutMI . setOpcode ( Opcode ) ; for ( unsigned I = 0 , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; MCOperand MCOp = lowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ; } } </s>


Return zero if TYPE1 and TYPE are incompatible , one if they are compatible , and two if they are nearly compatible ( which causes a warning to be generated ) .


"Unexpected instruction for custom inserter!"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> bool AArch64PassConfig :: addPreSched2 ( ) { addPass ( createAArch64ExpandPseudoPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableLoadStoreOpt ) addPass ( createAArch64LoadStoreOptimizationPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s>
bool
WaitcntBrackets
::
merge
(
const
WaitcntBrackets
&
Other
)
{
bool
StrictDom
=
false
;
for
(
auto
T
:
inst_counter_types
(
)
)
{
const
bool
OldOutOfOrder
=
counterOutOfOrder
(
T
)
;
const
uint32_t
OldEvents
=
PendingEvents
&
WaitEventMaskForInst
[
T
]
;
const
uint32_t
OtherEvents
=
Other
.
PendingEvents
&
WaitEventMaskForInst
[
T
]
;
if
(
OtherEvents
&
~
OldEvents
)
StrictDom
=
true
;
if
(
Other
.
MixedPendingEvents
[
T
]
||
(
OldEvents
&&
OtherEvents
&&
OldEvents
!=
OtherEvents
)
)
MixedPendingEvents
[
T
]
=
true
;
PendingEvents
|=
OtherEvents
;
const
uint32_t
MyPending
=
ScoreUBs
[
T
]
ScoreLBs
[
T
]
;
const
uint32_t
OtherPending
=
Other
.
ScoreUBs
[
T
]
Other
.
ScoreLBs
[
T
]
;
MergeInfo
M
;
M
.
OldLB
=
ScoreLBs
[
T
]
;
M
.
OtherLB
=
Other
.
ScoreLBs
[
T
]
;
M
.
MyShift
=
OtherPending
>
MyPending
OtherPending
MyPending
:
0
;
M
.
OtherShift
=
ScoreUBs
[
T
]
Other
.
ScoreUBs
[
T
]
+
M
.
MyShift
;
const
uint32_t
NewUB
=
ScoreUBs
[
T
]
+
M
.
MyShift
;
if
(
NewUB
<
ScoreUBs
[
T
]
)
report_fatal_error
(
"waitcnt score overflow"
)
;
ScoreUBs
[
T
]
=
NewUB
;
ScoreLBs
[
T
]
=
std
::
min
(
M
.
OldLB
+
M
.
MyShift
,
M
.
OtherLB
+
M
.
OtherShift
)
;
StrictDom
|=
mergeScore
(
M
,
LastFlat
[
T
]
,
Other
.
LastFlat
[
T
]
)
;
bool
RegStrictDom
=
false
;
for
(
int
J
=
0
,
E
=
std
::
max
(
getMaxVGPR
(
)
,
Other
.
getMaxVGPR
(
)
)
+
1
;
J
!=
E
;
J
++
)
{
RegStrictDom
|=
mergeScore
(
M
,
VgprScores
[
T
]
[
J
]
,
Other
.
VgprScores
[
T
]
[
J
]
)
;
}
if
(
T
==
LGKM_CNT
)
{
for
(
int
J
=
0
,
E
=
std
::
max
(
getMaxSGPR
(
)
,
Other
.
getMaxSGPR
(
)
)
+
1
;
J
!=
E
;
J
++
)
{
RegStrictDom
|=
mergeScore
(
M
,
SgprScores
[
J
]
,
Other
.
SgprScores
[
J
]
)
;
}
}
if
(
RegStrictDom
&&
!
OldOutOfOrder
)
StrictDom
=
true
;
}
VgprUB
=
std
::
max
(
getMaxVGPR
(
)
,
Other
.
getMaxVGPR
(
)
)
;
SgprUB
=
std
::
max
(
getMaxSGPR
(
)
,
Other
.
getMaxSGPR
(
)
)
;
return
StrictDom
;
}
</s>


<s>
void
HexagonFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
std
::
prev
(
MBB
.
end
(
)
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
if
(
hasFP
(
MF
)
||
MF
.
getTarget
(
)
.
getOptLevel
(
)
==
CodeGenOpt
::
)
{
MachineBasicBlock
::
iterator
MBBI
=
std
::
prev
(
MBB
.
end
(
)
)
;
MachineBasicBlock
::
iterator
MBBI_end
=
MBB
.
end
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
if
(
MBBI
->
getOpcode
(
)
==
Hexagon
::
EH_RETURN_JMPR
)
{
assert
(
MBBI
->
getOperand
(
0
)
.
isReg
(
)
&&
"Offset should be in register!"
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
L2_deallocframe
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
A2_add
)
,
Hexagon
::
R29
)
.
addReg
(
Hexagon
::
R29
)
.
addReg
(
Hexagon
::
R28
)
;
return
;
}
if
(
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
hasV4TOps
(
)
&&
MBBI
->
getOpcode
(
)
==
Hexagon
::
JMPret
&&
!
DisableDeallocRet
)
{
MachineBasicBlock
::
iterator
BeforeJMPR
=
MBB
.
begin
(
)
==
MBBI
MBBI
:
std
::
prev
(
MBBI
)
;
if
(
BeforeJMPR
!=
MBBI
&&
BeforeJMPR
->
getOpcode
(
)
==
Hexagon
::
RESTORE_DEALLOC_RET_JMP_V4
)
{
MBB
.
erase
(
MBBI
)
;
return
;
}
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI_end
,
dl
,
TII
.
get
(
Hexagon
::
L4_return
)
)
;
MIB
->
copyImplicitOps
(
*
MBB
.
getParent
(
)
,
&
*
MBBI
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
MachineBasicBlock
::
iterator
Term
=
MBB
.
getFirstTerminator
(
)
;
MachineBasicBlock
::
iterator
I
=
Term
==
MBB
.
begin
(
)
MBB
.
end
(
)
:
std
::
prev
(
Term
)
;
if
(
I
!=
MBB
.
end
(
)
&&
I
->
getOpcode
(
)
==
Hexagon
::
RESTORE_DEALLOC_BEFORE_TAILCALL_V4
)
return
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
L2_deallocframe
)
)
;
}
}
}
</s>


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < SparcSubtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> static bool mips_global_symbol_p ( const_rtx x ) { const_tree decl = SYMBOL_REF_DECL ( x ) ; if ( ! decl ) return ! SYMBOL_REF_LOCAL_P ( x ) || SYMBOL_REF_EXTERNAL_P ( x ) ; return DECL_P ( decl ) && ( TREE_PUBLIC ( decl ) || DECL_WEAK ( decl ) ) ; } </s>

Return true if SYMBOL_REF X is associated with a global symbol ( in the STB_GLOBAL sense ) .


"Warning: Illegal instruction detected: "

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool DCPU16AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static rtx emit_insxl ( machine_mode mode , rtx op1 , rtx op2 ) { rtx ret = gen_reg_rtx ( DImode ) ; rtx ( * fn ) ( rtx , rtx , rtx ) ; switch ( mode ) { case E_QImode : fn = gen_insbl ; break ; case E_HImode : fn = gen_inswl ; break ; case E_SImode : fn = gen_insll ; break ; case E_DImode : fn = gen_insql ; break ; default : gcc_unreachable ( ) ; } op1 = force_reg ( mode , op1 ) ; emit_insn ( fn ( ret , op1 , op2 ) ) ; return ret ; } </s>

A subroutine of the atomic operation splitters . Emit an insxl instruction in MODE .


<s> Align getStackAlignment ( ) const { return stackAlignment ; } </s>

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget .


<s> static void moxie_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regno ; int regs = 8 - * cum ; * pretend_size = regs < 0 ? 0 : GET_MODE_SIZE ( SImode ) * regs ; if ( no_rtl ) return ; for ( regno = * cum ; regno < 8 ; regno ++ ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx slot = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( SImode , ARG_POINTER_REGNUM ) , GEN_INT ( UNITS_PER_WORD * ( 3 + ( regno - 2 ) ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , slot ) , reg ) ; } } </s>

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> EVT RISCVTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( Subtarget . hasVInstructions ( ) && ( VT . isScalableVector ( ) || Subtarget . useRVVForFixedLengthVectors ( ) ) ) return EVT :: getVectorVT ( Context , MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
unsigned
HexagonInstrInfo
::
reduceLoopCount
(
MachineBasicBlock
&
MBB
,
MachineInstr
*
IndVar
,
MachineInstr
*
Cmp
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
SmallVectorImpl
<
MachineInstr
*
>
&
PrevInsts
,
unsigned
Iter
,
unsigned
MaxIter
)
const
{
assert
(
(
!
IndVar
)
&&
isEndLoopN
(
Cmp
->
getOpcode
(
)
)
&&
"Expecting a hardware loop"
)
;
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
DebugLoc
DL
=
Cmp
->
getDebugLoc
(
)
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
VisitedBBs
;
MachineInstr
*
Loop
=
findLoopInstr
(
&
MBB
,
Cmp
->
getOpcode
(
)
,
VisitedBBs
)
;
if
(
!
Loop
)
return
0
;
if
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0i
||
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop1i
)
{
int64_t
Offset
=
Loop
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
Offset
<=
1
)
Loop
->
eraseFromParent
(
)
;
else
Loop
->
getOperand
(
1
)
.
setImm
(
Offset
1
)
;
return
Offset
1
;
}
assert
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0r
&&
"Unexpected instruction"
)
;
unsigned
LoopCount
=
Loop
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
LoopEnd
=
createVR
(
MF
,
MVT
::
i1
)
;
MachineInstr
*
NewCmp
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
C2_cmpgtui
)
,
LoopEnd
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
unsigned
NewLoopCount
=
createVR
(
MF
,
MVT
::
i32
)
;
MachineInstr
*
NewAdd
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
A2_addi
)
,
NewLoopCount
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
for
(
SmallVectorImpl
<
MachineInstr
*
>
::
iterator
I
=
PrevInsts
.
begin
(
)
,
E
=
PrevInsts
.
end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
substituteRegister
(
LoopCount
,
NewLoopCount
,
0
,
getRegisterInfo
(
)
)
;
PrevInsts
.
clear
(
)
;
PrevInsts
.
push_back
(
NewCmp
)
;
PrevInsts
.
push_back
(
NewAdd
)
;
if
(
Iter
==
MaxIter
)
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
J2_loop0r
)
)
.
addMBB
(
Loop
->
getOperand
(
0
)
.
getMBB
(
)
)
.
addReg
(
NewLoopCount
)
;
if
(
Iter
==
0
)
Loop
->
eraseFromParent
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Hexagon
::
J2_jumpf
)
)
;
Cond
.
push_back
(
NewCmp
->
getOperand
(
0
)
)
;
return
NewLoopCount
;
}
</s>

Generate code to reduce the loop iteration by one and check if the loop is finished .


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { rtx x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; rtx_insn * insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , x ) ) ; add_reg_br_prob_note ( insn , profile_probability :: very_unlikely ( ) ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> unsigned getNumFixupKinds ( ) const { return Cpu0 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


"There are no defined alternate asm variants"

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> static bool loongarch_mode_ok_for_mov_fmt_p ( machine_mode mode ) { switch ( mode ) { case E_FCCmode : case E_SFmode : return TARGET_HARD_FLOAT ; case E_DFmode : return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT ; default : return 0 ; } } </s>

Return true if moves in mode MODE can use the FPU 's fmov.fmt instruction ,


<s> void X86InstrInfo :: breakPartialRegDependency ( MachineInstr & MI , unsigned OpNum , const TargetRegisterInfo * TRI ) const { Register Reg = MI . getOperand ( OpNum ) . getReg ( ) ; if ( MI . killsRegister ( Reg , TRI ) ) return ; if ( X86 :: VR128RegClass . contains ( Reg ) ) { unsigned Opc = Subtarget . hasAVX ( ) ? X86 :: VXORPSrr : X86 :: XORPSrr ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( Opc ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: VR256RegClass . contains ( Reg ) ) { Register XReg = TRI -> getSubReg ( Reg , X86 :: sub_xmm ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( X86 :: VXORPSrr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: GR64RegClass . contains ( Reg ) ) { Register XReg = TRI -> getSubReg ( Reg , X86 :: sub_32bit ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( X86 :: XOR32rr ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } else if ( X86 :: GR32RegClass . contains ( Reg ) ) { BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( X86 :: XOR32rr ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MI . addRegisterKilled ( Reg , TRI , true ) ; } } </s>

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum .


<s>
void
SIFrameLowering
::
processFunctionBeforeFrameFinalized
(
MachineFunction
&
MF
,
RegScavenger
*
RS
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
!
MFI
->
hasStackObjects
(
)
)
return
;
bool
MayNeedScavengingEmergencySlot
=
MFI
->
hasStackObjects
(
)
;
assert
(
(
RS
||
!
MayNeedScavengingEmergencySlot
)
&&
"RegScavenger required if spilling"
)
;
if
(
MayNeedScavengingEmergencySlot
)
{
int
ScavengeFI
=
MFI
->
CreateSpillStackObject
(
AMDGPU
::
SGPR_32RegClass
.
getSize
(
)
,
AMDGPU
::
SGPR_32RegClass
.
getAlignment
(
)
)
;
RS
->
addScavengingFrameIndex
(
ScavengeFI
)
;
}
}
</s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool csky_emit_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { bool invert ; rtx cc_reg = gen_rtx_REG ( CCmode , CSKY_CC_REGNUM ) ; if ( GET_MODE_CLASS ( GET_MODE ( op0 ) ) == MODE_FLOAT ) return csky_emit_compare_float ( code , op0 , op1 ) ; if ( GET_CODE ( op1 ) == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( op1 ) ; switch ( code ) { case GTU : if ( val == 0 ) code = NE ; else if ( TARGET_MINI_REGISTERS ? CSKY_CONST_OK_FOR_J ( val + 1 ) : CSKY_CONST_OK_FOR_Uk ( val + 1 ) ) { op1 = GEN_INT ( val + 1 ) ; code = GEU ; } break ; case GT : case LE : if ( TARGET_MINI_REGISTERS ? CSKY_CONST_OK_FOR_J ( val + 1 ) : CSKY_CONST_OK_FOR_Uk ( val + 1 ) ) { op1 = GEN_INT ( val + 1 ) ; code = code == LE ? LT : GE ; } break ; default : break ; } } if ( CONSTANT_P ( op1 ) && GET_CODE ( op1 ) != CONST_INT ) op1 = force_reg ( GET_MODE ( op1 ) , op1 ) ; invert = false ; switch ( code ) { case EQ : code = NE ; invert = true ; case NE : if ( GET_CODE ( op1 ) == CONST_INT && ( TARGET_MINI_REGISTERS ? ! csky_literal_K_operand ( op1 , SImode ) : ! csky_literal_I_operand ( op1 , SImode ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : code = GT ; invert = true ; case GT : if ( GET_CODE ( op1 ) == CONST_INT ) op1 = force_reg ( SImode , op1 ) ; break ; case GE : code = LT ; invert = true ; case LT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 && ( TARGET_MINI_REGISTERS ? ! csky_literal_J_operand ( op1 , SImode ) : ! csky_literal_Uk_operand ( op1 , SImode ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case GTU : gcc_assert ( GET_CODE ( op1 ) != CONST_INT || INTVAL ( op1 ) != 0 ) ; code = LEU ; invert = true ; case LEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 ) op1 = force_reg ( SImode , op1 ) ; break ; case LTU : code = GEU ; invert = true ; case GEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 && ( TARGET_MINI_REGISTERS ? ! csky_literal_J_operand ( op1 , SImode ) : ! csky_literal_Uk_operand ( op1 , SImode ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; default : break ; } emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_fmt_ee ( code , CCmode , op0 , op1 ) ) ) ; return invert ; } </s>

Emit a comparison instruction . Return true if an inverted comparison is generated .


<s> unsigned WebAssemblyFastISel :: fastMaterializeAlloca ( const AllocaInst * AI ) { DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & WebAssembly :: I64RegClass : & WebAssembly :: I32RegClass ) ; unsigned Opc = Subtarget -> hasAddr64 ( ) ? WebAssembly :: COPY_LOCAL_I64 : WebAssembly :: COPY_LOCAL_I32 ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( SI -> second ) ; return ResultReg ; } return 0 ; } </s>

Emit an alloca address in a register using target-specific logic .


<s> void GCNMaxOccupancySchedStrategy :: initialize ( ScheduleDAGMI * DAG ) { GenericScheduler :: initialize ( DAG ) ; const SIRegisterInfo * SRI = static_cast < const SIRegisterInfo * > ( TRI ) ; MF = & DAG -> MF ; const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; const int ErrorMargin = 3 ; SGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & AMDGPU :: SGPR_32RegClass ) - ErrorMargin ; VGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & AMDGPU :: VGPR_32RegClass ) - ErrorMargin ; if ( TargetOccupancy ) { SGPRCriticalLimit = ST . getMaxNumSGPRs ( TargetOccupancy , true ) ; VGPRCriticalLimit = ST . getMaxNumVGPRs ( TargetOccupancy ) ; } else { SGPRCriticalLimit = SRI -> getRegPressureSetLimit ( DAG -> MF , AMDGPU :: RegisterPressureSets :: SReg_32 ) ; VGPRCriticalLimit = SRI -> getRegPressureSetLimit ( DAG -> MF , AMDGPU :: RegisterPressureSets :: VGPR_32 ) ; } SGPRCriticalLimit -= ErrorMargin ; VGPRCriticalLimit -= ErrorMargin ; } </s>

Initialize the strategy after building the DAG for a new region .


": unsupported initializer for address space"

Emit the specified global variable to the .s file .


<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; } return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static bool c6x_function_value_regno_p ( const unsigned int regno ) { return regno == REG_A4 ; } </s>


<s> const P2InstrInfo * getInstrInfo ( ) const { return subtarget . getInstrInfo ( ) ; } </s>


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getFunction ( ) -> getCallingConv ( ) != CallingConv :: AMDGPU_PS ) return false ; Instructions . clear ( ) ; Blocks . clear ( ) ; ExecExports . clear ( ) ; LiveMaskQueries . clear ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; LIS = & getAnalysis < LiveIntervals > ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( AMDGPU :: EXEC ) ; return ! LiveMaskQueries . empty ( ) ; } unsigned LiveMaskReg = 0 ; { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( AMDGPU :: EXEC ) ; } if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; lowerLiveMaskQueries ( LiveMaskReg ) ; return true ; } } lowerLiveMaskQueries ( LiveMaskReg ) ; for ( auto BII : Blocks ) processBlock ( * BII . first , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI AMDGPU SI SI AMDGPU::EXEC 0 AMDGPU::SReg_64RegClass AMDGPU::COPY AMDGPU::EXEC AMDGPU::S_WQM_B64 AMDGPU::EXEC AMDGPU::EXEC


<s> std :: pair < unsigned , unsigned > AMDGPUSubtarget :: getWavesPerEU ( const Function & F , std :: pair < unsigned , unsigned > FlatWorkGroupSizes ) const { std :: pair < unsigned , unsigned > Default ( 1 , getMaxWavesPerEU ( ) ) ; unsigned MinImpliedByFlatWorkGroupSize = getWavesPerEUForWorkGroup ( FlatWorkGroupSizes . second ) ; Default . first = MinImpliedByFlatWorkGroupSize ; bool RequestedFlatWorkGroupSize = F . hasFnAttribute ( "amdgpu-flat-work-group-size" ) ; std :: pair < unsigned , unsigned > Requested = AMDGPU :: getIntegerPairAttribute ( F , "amdgpu-waves-per-eu" , Default , true ) ; if ( Requested . second && Requested . first > Requested . second ) return Default ; if ( Requested . first < getMinWavesPerEU ( ) || Requested . second > getMaxWavesPerEU ( ) ) return Default ; if ( RequestedFlatWorkGroupSize && Requested . first < MinImpliedByFlatWorkGroupSize ) return Default ; return Requested ; } </s>

Overload which uses the specified values for the flat work group sizes , rather than querying the function itself .

AMDGPU AMDGPU 1 "amdgpu-flat-work-group-size" AMDGPU::getIntegerPairAttribute "amdgpu-waves-per-eu"


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s>
SDValue
XCoreTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

XCore
XCore
ISD::InputArg
"Unsupported calling convention"


<s> static void build_all ( function_builder & b , const function_group_info & group ) { for ( unsigned int pred_idx = 0 ; group . preds [ pred_idx ] != NUM_PRED_TYPES ; ++ pred_idx ) for ( unsigned int vec_type_idx = 0 ; group . ops_infos . types [ vec_type_idx ] . index != NUM_VECTOR_TYPES ; ++ vec_type_idx ) build_one ( b , group , pred_idx , vec_type_idx ) ; } </s>

Add a function instance for every operand & & predicate & & args combination in GROUP . Take the function base name from GROUP & & operand suffix from operand_suffixes & & mode suffix from type_suffixes & & predication suffix from predication_suffixes . Use apply_predication to add in the predicate .


<s> static bool mips_hard_regno_call_part_clobbered ( unsigned int , unsigned int regno , machine_mode mode ) { if ( TARGET_FLOATXX && hard_regno_nregs ( regno , mode ) == 1 && FP_REG_P ( regno ) && ( regno & 1 ) != 0 ) return true ; if ( ISA_HAS_MSA && FP_REG_P ( regno ) && GET_MODE_SIZE ( mode ) > 8 ) return true ; return false ; } </s>

Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED . Odd-numbered single-precision registers are not considered callee-saved for o32 FPXX as they will be clobbered when run on an FR=1 FPU . MSA vector registers with MODE > 64 bits are part clobbered too .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
bool
isDarwin
=
TM
.
getSubtarget
<
PPCSubtarget
>
(
)
.
isDarwin
(
)
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
)
{
if
(
isDarwin
)
Suffix
=
"$stub"
;
}
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_PLT_OR_STUB
&&
isDarwin
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> bool XCoreTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( Ty -> getTypeID ( ) == Type :: VoidTyID ) return AM . Scale == 0 && isImmUs ( AM . BaseOffs ) && isImmUs4 ( AM . BaseOffs ) ; unsigned Size = DL . getTypeAllocSize ( Ty ) ; if ( AM . BaseGV ) { return Size >= 4 && ! AM . HasBaseReg && AM . Scale == 0 && AM . BaseOffs % 4 == 0 ; } switch ( Size ) { case 1 : if ( AM . Scale == 0 ) { return isImmUs ( AM . BaseOffs ) ; } return AM . Scale == 1 && AM . BaseOffs == 0 ; case 2 : case 3 : if ( AM . Scale == 0 ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == 2 && AM . BaseOffs == 0 ; default : if ( AM . Scale == 0 ) { return isImmUs4 ( AM . BaseOffs ) ; } return AM . Scale == 4 && AM . BaseOffs == 0 ; } } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


"Can only put epilog before 'retl' instruction!"


<s> int s390_extra_constraint_str ( rtx op , int c , const char * str ) { struct s390_address addr ; gcc_assert ( c == str [ 0 ] ) ; if ( c == 'A' ) { if ( ! MEM_P ( op ) || MEM_VOLATILE_P ( op ) ) return 0 ; if ( ( reload_completed || reload_in_progress ) ? ! offsettable_memref_p ( op ) : ! offsettable_nonstrict_memref_p ( op ) ) return 0 ; c = str [ 1 ] ; } else if ( c == 'B' ) { if ( GET_CODE ( op ) != MEM ) return 0 ; if ( ! s390_decompose_address ( XEXP ( op , 0 ) , & addr ) ) return 0 ; if ( addr . literal_pool ) return 0 ; c = str [ 1 ] ; } switch ( c ) { case 'Q' : if ( GET_CODE ( op ) != MEM ) return 0 ; if ( ! s390_decompose_address ( XEXP ( op , 0 ) , & addr ) ) return 0 ; if ( addr . indx ) return 0 ; if ( TARGET_LONG_DISPLACEMENT ) { if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; } break ; case 'R' : if ( GET_CODE ( op ) != MEM ) return 0 ; if ( TARGET_LONG_DISPLACEMENT ) { if ( ! s390_decompose_address ( XEXP ( op , 0 ) , & addr ) ) return 0 ; if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; } break ; case 'S' : if ( ! TARGET_LONG_DISPLACEMENT ) return 0 ; if ( GET_CODE ( op ) != MEM ) return 0 ; if ( ! s390_decompose_address ( XEXP ( op , 0 ) , & addr ) ) return 0 ; if ( addr . indx ) return 0 ; if ( s390_short_displacement ( addr . disp ) ) return 0 ; break ; case 'T' : if ( ! TARGET_LONG_DISPLACEMENT ) return 0 ; if ( GET_CODE ( op ) != MEM ) return 0 ; if ( s390_decompose_address ( XEXP ( op , 0 ) , & addr ) && s390_short_displacement ( addr . disp ) ) return 0 ; break ; case 'U' : if ( TARGET_LONG_DISPLACEMENT ) { if ( ! s390_decompose_address ( op , & addr ) ) return 0 ; if ( ! s390_short_displacement ( addr . disp ) ) return 0 ; } break ; case 'W' : if ( ! TARGET_LONG_DISPLACEMENT ) return 0 ; if ( s390_decompose_address ( op , & addr ) && s390_short_displacement ( addr . disp ) ) return 0 ; break ; case 'Y' : if ( ! s390_decompose_shift_count ( op , NULL , NULL ) ) return 0 ; break ; default : return 0 ; } return 1 ; } </s>

Return 1 if OP is a valid operand for a C constraint , 0 else .


<s> rtx function_value ( tree type , enum machine_mode mode , int incoming_p ) { int regbase = ( incoming_p ? SPARC_OUTGOING_INT_ARG_FIRST : SPARC_INCOMING_INT_ARG_FIRST ) ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; int regno ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( ( TARGET_ARCH32 && size <= 8 ) || ( TARGET_ARCH64 && size <= 32 ) ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , TYPE_MODE ( TREE_TYPE ( type ) ) , SPARC_FP_ARG_FIRST ) ; else mclass = MODE_FLOAT ; } else if ( type && TARGET_ARCH64 ) { if ( TREE_CODE ( type ) == RECORD_TYPE ) { gcc_assert ( int_size_in_bytes ( type ) <= 32 ) ; return function_arg_record_value ( type , mode , 0 , 1 , regbase ) ; } else if ( TREE_CODE ( type ) == UNION_TYPE ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; gcc_assert ( size <= 32 ) ; return function_arg_union_value ( size , mode , 0 , regbase ) ; } else if ( AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT bytes = int_size_in_bytes ( type ) ; gcc_assert ( bytes <= 32 ) ; mode = mode_for_size ( bytes * BITS_PER_UNIT , MODE_INT , 0 ) ; if ( mode == BLKmode ) return function_arg_union_value ( bytes , mode , 0 , regbase ) ; else mclass = MODE_INT ; } else if ( mclass == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) mode = word_mode ; } if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && TARGET_FPU ) regno = SPARC_FP_ARG_FIRST ; else regno = regbase ; return gen_rtx_REG ( mode , regno ) ; } </s>

Handle FUNCTION_VALUE , FUNCTION_OUTGOING_VALUE , and LIBCALL_VALUE macros . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .


<s> unsigned AArch64TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo ) { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ISD == ISD :: SDIV && Opd2Info == TargetTransformInfo :: OK_UniformConstantValue && Opd2PropInfo == TargetTransformInfo :: OP_PowerOf2 ) { unsigned Cost = getArithmeticInstrCost ( Instruction :: Add , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Sub , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: Select , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; Cost += getArithmeticInstrCost ( Instruction :: AShr , Ty , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return Cost ; } switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: ADD : case ISD :: MUL : case ISD :: XOR : case ISD :: OR : case ISD :: AND : return 1 * LT . first ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

AArch64 AArch64 ISD::SDIV ISD::ADD ISD::MUL ISD::XOR ISD::OR ISD::AND 1


"There are no defined alternate asm variants"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> bool arc_epilogue_uses ( int regno ) { if ( reload_completed ) { if ( ARC_INTERRUPT_P ( cfun -> machine -> fn_type ) ) { if ( ! fixed_regs [ regno ] ) return true ; return regno == arc_return_address_regs [ cfun -> machine -> fn_type ] ; } else return regno == RETURN_ADDR_REGNUM ; } else return regno == arc_return_address_regs [ arc_compute_function_type ( cfun ) ] ; } </s>

Implement EPILOGUE__USES . Return true if REGNO should be added to the deemed uses of the epilogue . We use the return address arc_return_address_regs [ arc_compute_function_type ( cfun ) ] . But also , we have to make sure all the register restore instructions are known to be live in interrupt functions , plus the blink register if it is clobbered by the isr .


<s>
MachineBasicBlock
*
XCoreTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
Subtarget
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
XCore
::
SELECT_CC
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
sinkMBB
->
splice
(
sinkMBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
sinkMBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
XCore
::
BRFT_lru6
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
XCore
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
3
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>


<s> unsigned SITargetLowering :: getVectorTypeBreakdownForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT , EVT & IntermediateVT , unsigned & NumIntermediates , MVT & RegisterVT ) const { if ( CC != CallingConv :: AMDGPU_KERNEL && VT . isVector ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; unsigned Size = ScalarVT . getSizeInBits ( ) ; if ( Size == 32 ) { RegisterVT = ScalarVT . getSimpleVT ( ) ; IntermediateVT = RegisterVT ; NumIntermediates = NumElts ; return NumIntermediates ; } if ( Size == 64 ) { RegisterVT = MVT :: i32 ; IntermediateVT = RegisterVT ; NumIntermediates = 2 * NumElts ; return NumIntermediates ; } if ( Size == 16 && Subtarget -> has16BitInsts ( ) && isPowerOf2_32 ( NumElts ) ) { RegisterVT = VT . isInteger ( ) ? MVT :: v2i16 : MVT :: v2f16 ; IntermediateVT = RegisterVT ; NumIntermediates = NumElts / 2 ; return NumIntermediates ; } } return TargetLowering :: getVectorTypeBreakdownForCallingConv ( Context , CC , VT , IntermediateVT , NumIntermediates , RegisterVT ) ; } </s>

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts .


<s> bool PPCPassConfig :: addPreSched2 ( ) { addPass ( createPPCVSXCopyCleanupPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> int msp430_check_env_var_for_devices ( char * * local_devices_csv_loc ) { const int num_vars = 3 ; const char dirsep [ 2 ] = { DIR_SEPARATOR , 0 } ; const char * env_vars [ num_vars ] = { "MSP430_GCC_INCLUDE_DIR" , "GCC_EXEC_PREFIX" , "COLLECT_GCC" } ; enum msp430_include_vars { MSP430_GCC_INCLUDE_DIR , GCC_EXEC_PREFIX , COLLECT_GCC } ; FILE * devices_csv_file = NULL ; int i ; for ( i = MSP430_GCC_INCLUDE_DIR ; i <= COLLECT_GCC ; i ++ ) { char * t_devices_loc ; char * val = getenv ( env_vars [ i ] ) ; if ( val == NULL ) continue ; t_devices_loc = xstrdup ( val ) ; if ( i == MSP430_GCC_INCLUDE_DIR ) { if ( ! IS_DIR_SEPARATOR ( t_devices_loc [ strlen ( t_devices_loc ) - 1 ] ) ) t_devices_loc = concat ( t_devices_loc , dirsep , NULL ) ; } else if ( i == GCC_EXEC_PREFIX ) extract_devices_dir_from_exec_prefix ( & t_devices_loc ) ; else if ( i == COLLECT_GCC ) extract_devices_dir_from_collect_gcc ( & t_devices_loc ) ; t_devices_loc = concat ( t_devices_loc , "devices.csv" , NULL ) ; devices_csv_file = fopen ( t_devices_loc , "r" ) ; if ( devices_csv_file != NULL ) { fclose ( devices_csv_file ) ; * local_devices_csv_loc = t_devices_loc ; canonicalize_path_dirsep ( local_devices_csv_loc ) ; return 0 ; } } return 1 ; } </s>

The path to the MSP430-GCC support files can be specified with the environment variable `` MSP430_GCC_INCLUDE_DIR '' , or installed into the toolchain in the msp430-elf/include/devices subdirectory . We use the GCC_EXEC_PREFIX or COLLECT_GCC environment variables as a starting point for the location of the toolchain , and work out the path to the installed device data from there . Return 0 and set LOCAL_DEVICES_CSV_LOC if we find devices.csv . Return 1 if devices.csv was n't found .


<s> static void frv_init_libfuncs ( void ) { set_optab_libfunc ( smod_optab , SImode , "__modi" ) ; set_optab_libfunc ( umod_optab , SImode , "__umodi" ) ; set_optab_libfunc ( add_optab , DImode , "__addll" ) ; set_optab_libfunc ( sub_optab , DImode , "__subll" ) ; set_optab_libfunc ( smul_optab , DImode , "__mulll" ) ; set_optab_libfunc ( sdiv_optab , DImode , "__divll" ) ; set_optab_libfunc ( smod_optab , DImode , "__modll" ) ; set_optab_libfunc ( umod_optab , DImode , "__umodll" ) ; set_optab_libfunc ( and_optab , DImode , "__andll" ) ; set_optab_libfunc ( ior_optab , DImode , "__orll" ) ; set_optab_libfunc ( xor_optab , DImode , "__xorll" ) ; set_optab_libfunc ( one_cmpl_optab , DImode , "__notll" ) ; set_optab_libfunc ( add_optab , SFmode , "__addf" ) ; set_optab_libfunc ( sub_optab , SFmode , "__subf" ) ; set_optab_libfunc ( smul_optab , SFmode , "__mulf" ) ; set_optab_libfunc ( sdiv_optab , SFmode , "__divf" ) ; set_optab_libfunc ( add_optab , DFmode , "__addd" ) ; set_optab_libfunc ( sub_optab , DFmode , "__subd" ) ; set_optab_libfunc ( smul_optab , DFmode , "__muld" ) ; set_optab_libfunc ( sdiv_optab , DFmode , "__divd" ) ; set_conv_libfunc ( sext_optab , DFmode , SFmode , "__ftod" ) ; set_conv_libfunc ( trunc_optab , SFmode , DFmode , "__dtof" ) ; set_conv_libfunc ( sfix_optab , SImode , SFmode , "__ftoi" ) ; set_conv_libfunc ( sfix_optab , DImode , SFmode , "__ftoll" ) ; set_conv_libfunc ( sfix_optab , SImode , DFmode , "__dtoi" ) ; set_conv_libfunc ( sfix_optab , DImode , DFmode , "__dtoll" ) ; set_conv_libfunc ( ufix_optab , SImode , SFmode , "__ftoui" ) ; set_conv_libfunc ( ufix_optab , DImode , SFmode , "__ftoull" ) ; set_conv_libfunc ( ufix_optab , SImode , DFmode , "__dtoui" ) ; set_conv_libfunc ( ufix_optab , DImode , DFmode , "__dtoull" ) ; set_conv_libfunc ( sfloat_optab , SFmode , SImode , "__itof" ) ; set_conv_libfunc ( sfloat_optab , SFmode , DImode , "__lltof" ) ; set_conv_libfunc ( sfloat_optab , DFmode , SImode , "__itod" ) ; set_conv_libfunc ( sfloat_optab , DFmode , DImode , "__lltod" ) ; } </s>

Set the names for various arithmetic operations according to the FRV ABI .


<s> bool cris_valid_pic_const ( rtx x ) { gcc_assert ( flag_pic ) ; switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : return true ; default : ; } if ( GET_CODE ( x ) != CONST ) return false ; x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == UNSPEC && XINT ( XEXP ( x , 0 ) , 1 ) == CRIS_UNSPEC_GOTREL && GET_CODE ( XEXP ( x , 1 ) ) == CONST_INT ) x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case CRIS_UNSPEC_PLT : case CRIS_UNSPEC_PLTGOTREAD : case CRIS_UNSPEC_GOTREAD : case CRIS_UNSPEC_GOTREL : return true ; default : gcc_unreachable ( ) ; } return cris_pic_symbol_type_of ( x ) == cris_no_symbol ; } </s>

Return TRUE iff X is a CONST valid for e.g . indexing .


<s> bool isImm ( ) const { return Kind == Immediate || Kind == Expression ; } </s>


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM MLA / MLS expansion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void xtensa_va_start ( tree valist , rtx nextarg ATTRIBUTE_UNUSED ) { tree f_stk , stk ; tree f_reg , reg ; tree f_ndx , ndx ; tree t , u ; int arg_words ; arg_words = crtl -> args . info . arg_words ; f_stk = TYPE_FIELDS ( va_list_type_node ) ; f_reg = DECL_CHAIN ( f_stk ) ; f_ndx = DECL_CHAIN ( f_reg ) ; stk = build3 ( COMPONENT_REF , TREE_TYPE ( f_stk ) , valist , f_stk , NULL_TREE ) ; reg = build3 ( COMPONENT_REF , TREE_TYPE ( f_reg ) , unshare_expr ( valist ) , f_reg , NULL_TREE ) ; ndx = build3 ( COMPONENT_REF , TREE_TYPE ( f_ndx ) , unshare_expr ( valist ) , f_ndx , NULL_TREE ) ; u = make_tree ( sizetype , expand_builtin_saveregs ( ) ) ; u = fold_convert ( ptr_type_node , u ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , reg , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = make_tree ( ptr_type_node , virtual_incoming_args_rtx ) ; u = fold_build_pointer_plus_hwi ( u , - 32 ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , stk , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; if ( arg_words >= MAX_ARGS_IN_REGISTERS ) arg_words += 2 ; t = build2 ( MODIFY_EXPR , integer_type_node , ndx , build_int_cst ( integer_type_node , arg_words * UNITS_PER_WORD ) ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>

Implement ` va_start ' for varargs and stdarg . We look at the current function to fill in an initial va_list .


<s> static void thumb1_reorg ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx dest , src ; rtx cmp , op0 , op1 , set = NULL ; rtx_insn * prev , * insn = BB_END ( bb ) ; bool insn_clobbered = false ; while ( insn != BB_HEAD ( bb ) && ! NONDEBUG_INSN_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( insn == BB_HEAD ( bb ) || INSN_CODE ( insn ) != CODE_FOR_cbranchsi4_insn ) continue ; cmp = XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ; op0 = XEXP ( cmp , 0 ) ; op1 = XEXP ( cmp , 1 ) ; if ( ! CONST_INT_P ( op1 ) || INTVAL ( op1 ) != 0 ) continue ; gcc_assert ( insn != BB_HEAD ( bb ) ) ; for ( prev = PREV_INSN ( insn ) ; ( ! insn_clobbered && prev != BB_HEAD ( bb ) && ( NOTE_P ( prev ) || DEBUG_INSN_P ( prev ) || ( ( set = single_set ( prev ) ) != NULL && get_attr_conds ( prev ) == CONDS_NOCOND ) ) ) ; prev = PREV_INSN ( prev ) ) { if ( reg_set_p ( op0 , prev ) ) insn_clobbered = true ; } if ( insn_clobbered ) continue ; if ( ! set ) continue ; dest = SET_DEST ( set ) ; src = SET_SRC ( set ) ; if ( ! low_register_operand ( dest , SImode ) || ! low_register_operand ( src , SImode ) ) continue ; if ( REGNO ( op0 ) == REGNO ( src ) || REGNO ( op0 ) == REGNO ( dest ) ) { dest = copy_rtx ( dest ) ; src = copy_rtx ( src ) ; src = gen_rtx_MINUS ( SImode , src , const0_rtx ) ; PATTERN ( prev ) = gen_rtx_SET ( dest , src ) ; INSN_CODE ( prev ) = - 1 ; XEXP ( cmp , 0 ) = copy_rtx ( dest ) ; INSN_CODE ( insn ) = - 1 ; } } } </s>

Rewrite move insn into subtract of 0 if the condition codes will be useful in next conditional jump insn .


<s> unsigned TeakInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = 0 ; if ( MBB . empty ( ) ) return 0 ; unsigned NumRemoved = 0 ; auto I = MBB . end ( ) ; do { -- I ; unsigned Opc = I -> getOpcode ( ) ; if ( Opc == Teak :: BRR_rel7 || Opc == Teak :: BRRCond_rel7 || Opc == Teak :: BR_imm18 ) { auto ToDelete = I ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * ToDelete ) ; ++ I ; MBB . erase ( ToDelete ) ; NumRemoved ++ ; } } while ( I != MBB . begin ( ) ) ; return NumRemoved ; } </s>

Remove the branching code at the end of the specific MBB .


<s>
bool
P2FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
unsigned
CalleeFrameSize
=
0
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
P2Subtarget
&
STI
=
MF
.
getSubtarget
<
P2Subtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
P2FunctionInfo
*
P2FI
=
MF
.
getInfo
<
P2FunctionInfo
>
(
)
;
LLVM_DEBUG
(
errs
(
)
<<
"=== Function: "
<<
MF
.
getName
(
)
<<
" ===\n"
)
;
LLVM_DEBUG
(
errs
(
)
<<
"Spilling callee saves\n"
)
;
for
(
unsigned
i
=
0
;
i
<
CSI
.
size
(
)
;
i
++
)
{
unsigned
Reg
=
CSI
[
i
]
.
getReg
(
)
;
bool
IsNotLiveIn
=
!
MBB
.
isLiveIn
(
Reg
)
;
if
(
IsNotLiveIn
)
{
MBB
.
addLiveIn
(
Reg
)
;
}
const
TargetRegisterClass
*
RC
=
TRI
->
getMinimalPhysRegClass
(
Reg
)
;
TII
.
storeRegToStackSlot
(
MBB
,
MI
,
Reg
,
false
,
CSI
[
i
]
.
getFrameIdx
(
)
,
RC
,
TRI
)
;
CalleeFrameSize
+=
4
;
LLVM_DEBUG
(
errs
(
)
<<
"--- spilling "
<<
Reg
<<
" to index "
<<
CSI
[
i
]
.
getFrameIdx
(
)
<<
"\n"
)
;
}
P2FI
->
setCalleeSavedFrameSize
(
CalleeFrameSize
)
;
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> inline bool function_base :: use_mask_predication_p ( ) const { return true ; } </s>

We choose to return true by default since most of the intrinsics use mask predication .


<s> bool rs6000_move_128bit_ok_p ( rtx operands [ ] ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; return ( gpc_reg_operand ( operands [ 0 ] , mode ) || gpc_reg_operand ( operands [ 1 ] , mode ) ) ; } </s>


<s> bool SPIRVLegalizerInfo :: legalizeCustom ( LegalizerHelper & Helper , MachineInstr & MI ) const { auto Opc = MI . getOpcode ( ) ; MachineRegisterInfo & MRI = MI . getMF ( ) -> getRegInfo ( ) ; if ( ! isTypeFoldingSupported ( Opc ) ) { assert ( Opc == TargetOpcode :: G_ICMP ) ; assert ( GR -> getSPIRVTypeForVReg ( MI . getOperand ( 0 ) . getReg ( ) ) ) ; auto & Op0 = MI . getOperand ( 2 ) ; auto & Op1 = MI . getOperand ( 3 ) ; Register Reg0 = Op0 . getReg ( ) ; Register Reg1 = Op1 . getReg ( ) ; CmpInst :: Predicate Cond = static_cast < CmpInst :: Predicate > ( MI . getOperand ( 1 ) . getPredicate ( ) ) ; if ( ( ! ST -> canDirectlyComparePointers ( ) || ( Cond != CmpInst :: ICMP_EQ && Cond != CmpInst :: ICMP_NE ) ) && MRI . getType ( Reg0 ) . isPointer ( ) && MRI . getType ( Reg1 ) . isPointer ( ) ) { LLT ConvT = LLT :: scalar ( ST -> getPointerSize ( ) ) ; Type * LLVMTy = IntegerType :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , ST -> getPointerSize ( ) ) ; SPIRVType * SpirvTy = GR -> getOrCreateSPIRVType ( LLVMTy , Helper . MIRBuilder ) ; Op0 . setReg ( convertPtrToInt ( Reg0 , ConvT , SpirvTy , Helper , MRI , GR ) ) ; Op1 . setReg ( convertPtrToInt ( Reg1 , ConvT , SpirvTy , Helper , MRI , GR ) ) ; } return true ; } return true ; } </s>

Called for instructions with the Custom LegalizationAction .


<s> static BasicBlock :: iterator getInsertPt ( BasicBlock & BB ) { BasicBlock :: iterator InsPt = BB . getFirstInsertionPt ( ) ; for ( BasicBlock :: iterator E = BB . end ( ) ; InsPt != E ; ++ InsPt ) { AllocaInst * AI = dyn_cast < AllocaInst > ( & * InsPt ) ; if ( ! AI || ! AI -> isStaticAlloca ( ) ) break ; } return InsPt ; } </s>

Current insertion point for new instructions .


<s> static void s390_add_constant ( struct constant_pool * pool , rtx val , machine_mode mode ) { struct constant * c ; size_t i ; for ( i = 0 ; i < NR_C_MODES ; i ++ ) if ( constant_modes [ i ] == mode ) break ; gcc_assert ( i != NR_C_MODES ) ; for ( c = pool -> constants [ i ] ; c != NULL ; c = c -> next ) if ( rtx_equal_p ( val , c -> value ) ) break ; if ( c == NULL ) { c = ( struct constant * ) xmalloc ( sizeof * c ) ; c -> value = val ; c -> label = gen_label_rtx ( ) ; c -> next = pool -> constants [ i ] ; pool -> constants [ i ] = c ; pool -> size += GET_MODE_SIZE ( mode ) ; } } </s>

Add constant VAL of mode MODE to the constant pool POOL .


<s> unsigned IA64RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ? IA64 :: r5 : IA64 :: r12 ; } </s>


<s> void TL45InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void ARMRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; DebugLoc dl = Old -> getDebugLoc ( ) ; unsigned Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; unsigned Opc = Old -> getOpcode ( ) ; bool isThumb = AFI -> isThumbFunction ( ) ; ARMCC :: CondCodes Pred = isThumb ? ARMCC :: AL : ( ARMCC :: CondCodes ) Old -> getOperand ( 1 ) . getImm ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { unsigned PredReg = isThumb ? 0 : Old -> getOperand ( 2 ) . getReg ( ) ; emitSPUpdate ( MBB , I , - Amount , Pred , PredReg , isThumb , TII , * this , dl ) ; } else { unsigned PredReg = isThumb ? 0 : Old -> getOperand ( 3 ) . getReg ( ) ; assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitSPUpdate ( MBB , I , Amount , Pred , PredReg , isThumb , TII , * this , dl ) ; } } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> BitVector XCoreRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; Reserved . set ( XCore :: CP ) ; Reserved . set ( XCore :: DP ) ; Reserved . set ( XCore :: SP ) ; Reserved . set ( XCore :: LR ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( XCore :: R10 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

XCore XCore XCore::CP XCore::DP XCore::SP XCore::LR XCore::R10


<s> TargetPassConfig * XtensaTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new XtensaPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> const MipsInstrInfo * MipsInstrInfo :: create ( MipsTargetMachine & TM ) { if ( TM . getSubtargetImpl ( ) -> inMips16Mode ( ) ) return llvm :: createMips16InstrInfo ( TM ) ; return llvm :: createMipsSEInstrInfo ( TM ) ; } </s>


"OpFunction is not in the front MBB of MF"

Targets should implement this to emit instructions .


<s> bool equals ( const ARMConstantPoolMBB * A ) const { return MBB == A -> MBB && ARMConstantPoolValue :: equals ( A ) ; } </s>

equals - Check for string equality , this is more efficient than compare ( ) when the relative ordering of inequal strings is n't needed .


<s> void eco32_print_operand_address ( FILE * file , rtx x ) { switch ( GET_CODE ( x ) ) { case REG : fprintf ( file , "%s,0" , reg_names [ REGNO ( x ) ] ) ; break ; case PLUS : switch ( GET_CODE ( XEXP ( x , 1 ) ) ) { case CONST_INT : fprintf ( file , "%s,%ld" , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] , INTVAL ( XEXP ( x , 1 ) ) ) ; break ; case SYMBOL_REF : fprintf ( file , "%s," , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; output_addr_const ( file , XEXP ( x , 1 ) ) ; break ; case CONST : { rtx plus = XEXP ( XEXP ( x , 1 ) , 0 ) ; if ( GET_CODE ( XEXP ( plus , 0 ) ) == SYMBOL_REF && CONST_INT_P ( XEXP ( plus , 1 ) ) ) { fprintf ( file , "%s," , reg_names [ REGNO ( XEXP ( x , 0 ) ) ] ) ; output_addr_const ( file , plus ) ; } else abort ( ) ; } break ; default : abort ( ) ; } break ; default : output_addr_const ( file , x ) ; break ; } } </s>


<s>
const
char
*
output_mov_long_double_fpa_from_arm
(
rtx
*
operands
)
{
int
arm_reg0
=
REGNO
(
operands
[
1
]
)
;
rtx
ops
[
3
]
;
gcc_assert
(
arm_reg0
!=
IP_REGNUM
)
;
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
arm_reg0
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
1
+
arm_reg0
)
;
ops
[
2
]
=
gen_rtx_REG
(
SImode
,
2
+
arm_reg0
)
;
output_asm_insn
(
"stm%?fd\t%|sp!, {%0, %1, %2}"
,
ops
)
;
output_asm_insn
(
"ldf%?e\t%0, [%|sp], #12"
,
operands
)
;
return
""
;
}
</s>

Output a move from arm registers to an fpa registers . OPERANDS [ 0 ] is an fpa register . OPERANDS [ 1 ] is the first registers of an arm register pair .


<s> DecodeStatus SparcDisassembler :: getInstruction ( MCInst & instr , uint64_t & Size , const MemoryObject & Region , uint64_t Address , raw_ostream & vStream , raw_ostream & cStream ) const { uint32_t Insn ; DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableSparc32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> void HexagonTargetMachine :: registerPassBuilderCallbacks ( PassBuilder & PB , bool DebugPassManager ) { PB . registerOptimizerLastEPCallback ( [ = ] ( ModulePassManager & MPM , PassBuilder :: OptimizationLevel Level ) { LoopPassManager LPM ( DebugPassManager ) ; FunctionPassManager FPM ( DebugPassManager ) ; LPM . addPass ( HexagonVectorLoopCarriedReusePass ( ) ) ; FPM . addPass ( createFunctionToLoopPassAdaptor ( std :: move ( LPM ) ) ) ; MPM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ; } ) ; } </s>

Invoke the PassBuilder callback registration .


<s> unsigned int call_properties ( const function_instance & ) const override { return CP_WRITE_MEMORY ; } </s>

Default implementation of function_base : :call_properties , with conservatively correct behavior for floating-point instructions .


<s> static void ix86_encode_section_info ( tree decl , rtx rtl , int first ) { default_encode_section_info ( decl , rtl , first ) ; if ( TREE_CODE ( decl ) == VAR_DECL && ( TREE_STATIC ( decl ) || DECL_EXTERNAL ( decl ) ) && ix86_in_large_data_p ( decl ) ) SYMBOL_REF_FLAGS ( XEXP ( rtl , 0 ) ) |= SYMBOL_FLAG_FAR_ADDR ; } </s>

Implements target vector targetm.asm.encode_section_info .


<s> static void visium_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx addr = XEXP ( m_tramp , 0 ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 0 ) ) , plus_constant ( SImode , expand_shift ( RSHIFT_EXPR , SImode , fnaddr , 16 , NULL_RTX , 1 ) , 0x04a90000 ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 4 ) ) , plus_constant ( SImode , expand_and ( SImode , fnaddr , GEN_INT ( 0xffff ) , NULL_RTX ) , 0x04890000 ) ) ; if ( visium_cpu == PROCESSOR_GR6 ) { gcc_assert ( TRAMPOLINE_ALIGNMENT >= 64 ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 12 ) ) , gen_int_mode ( 0 , SImode ) ) ; } emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 8 ) ) , plus_constant ( SImode , expand_shift ( RSHIFT_EXPR , SImode , static_chain , 16 , NULL_RTX , 1 ) , 0x04b40000 ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 12 ) ) , gen_int_mode ( 0xff892404 , SImode ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , plus_constant ( Pmode , addr , 16 ) ) , plus_constant ( SImode , expand_and ( SImode , static_chain , GEN_INT ( 0xffff ) , NULL_RTX ) , 0x04940000 ) ) ; emit_library_call ( set_trampoline_parity_libfunc , LCT_NORMAL , VOIDmode , addr , SImode ) ; } </s>

Initialize a trampoline . M_TRAMP is an RTX for the memory block for the trampoline , FNDECL is the FUNCTION_DECL for the nested function and STATIC_CHAIN is an RTX for the static chain value that should be passed to the function when it is called .


"%qE attribute only applies to functions"

"an interrupt handler cannot be compiled with %<-muser-mode%>"

Handle an `` interrupt_handler '' attribute ; arguments as in struct attribute_spec.handler .


Output assembly code for a specific branch instruction , appending the branch prediction flag to the opcode if appropriate .


<s> static rtx_insn * emit_frame_save ( rtx frame_reg , machine_mode mode , unsigned int regno , int offset , HOST_WIDE_INT frame_reg_to_sp ) { rtx reg ; gcc_checking_assert ( ! ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) ) ; reg = gen_rtx_REG ( mode , regno ) ; rtx_insn * insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ; return rs6000_frame_related ( insn , frame_reg , frame_reg_to_sp , NULL_RTX , NULL_RTX ) ; } </s>

Save a register into the frame , and emit RTX_FRAME_RELATED_P notes . Save REGNO into [ FRAME_REG + OFFSET ] in mode MODE .


"  Copied r%d to a vector register r%d for insn %d\n"

Make vector copies for all register REGNO definitions and replace its uses in a chain .


<s> static bool ix86_lea_outperforms ( rtx_insn * insn , unsigned int regno0 , unsigned int regno1 , unsigned int regno2 , int split_cost , bool has_scale ) { int dist_define , dist_use ; if ( ! TARGET_CPU_P ( BONNELL ) ) { if ( has_scale ) return true ; if ( split_cost < 1 ) return false ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; return true ; } struct recog_data_d recog_data_save = recog_data ; dist_define = distance_non_agu_define ( regno1 , regno2 , insn ) ; dist_use = distance_agu_use ( regno0 , insn ) ; recog_data = recog_data_save ; if ( dist_define < 0 || dist_define >= LEA_MAX_STALL ) { if ( dist_use < 0 && split_cost == 0 ) return TARGET_64BIT || IX86_LEA_PRIORITY ; else return true ; } dist_define += split_cost + IX86_LEA_PRIORITY ; if ( dist_use < 0 ) return dist_define > LEA_MAX_STALL ; return dist_define >= dist_use ; } </s>

Return true if usage of lea INSN has performance advantage over a sequence of instructions . Instructions sequence has SPLIT_COST cycles higher latency than lea latency .


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned Alignment , MachineMemOperand :: Flags , bool * Fast ) const { if ( ! VT . isSimple ( ) ) return false ; bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; auto Ty = VT . getSimpleVT ( ) . SimpleTy ; if ( Ty == MVT :: i8 || Ty == MVT :: i16 || Ty == MVT :: i32 ) { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } } if ( Ty == MVT :: f64 || Ty == MVT :: v2f64 ) { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } } if ( ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Ty != MVT :: v16i8 && Ty != MVT :: v8i16 && Ty != MVT :: v8f16 && Ty != MVT :: v4i32 && Ty != MVT :: v4f32 && Ty != MVT :: v2i64 && Ty != MVT :: v2f64 && Ty != MVT :: v4i8 && Ty != MVT :: v8i8 && Ty != MVT :: v4i16 ) return false ; if ( Subtarget -> isLittle ( ) ) { if ( Fast ) * Fast = true ; return true ; } else { if ( Ty == MVT :: v16i8 || ( ( Ty == MVT :: v8i16 || Ty == MVT :: v8f16 ) && Alignment >= 2 ) || ( ( Ty == MVT :: v4i32 || Ty == MVT :: v4f32 ) && Alignment >= 4 ) ) { if ( Fast ) * Fast = true ; return true ; } } return false ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> void ia64_emit_cond_move ( rtx op0 , rtx op1 , rtx cond ) { rtx insn , first = get_last_insn ( ) ; emit_move_insn ( op0 , op1 ) ; for ( insn = get_last_insn ( ) ; insn != first ; insn = PREV_INSN ( insn ) ) if ( INSN_P ( insn ) ) PATTERN ( insn ) = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( cond ) , PATTERN ( insn ) ) ; } </s>

Split a move from OP1 to OP0 conditional on COND .


<s> void HCE :: collect ( MachineFunction & MF ) { Extenders . clear ( ) ; for ( MachineBasicBlock & MBB : MF ) { if ( MBB . getNumber ( ) == - 1 ) continue ; for ( MachineInstr & MI : MBB ) collectInstr ( MI ) ; } } </s>

Analyze the given instruction MI and fill in the Uses , Defs and DeadDefs list based on the MachineOperand flags .


"mt_function_arg_advance: words = %2d, mode = %4s, named = %d, size = %3d\n"


<s> StackOffset VEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const VERegisterInfo * RegInfo = STI . getRegisterInfo ( ) ; const VEMachineFunctionInfo * FuncInfo = MF . getInfo < VEMachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; if ( FuncInfo -> isLeafProc ( ) ) { FrameReg = VE :: SX11 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } if ( RegInfo -> needsStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = VE :: SX17 ; else FrameReg = VE :: SX11 ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s>
bool
AMDGPUAsmParser
::
isInlineConstant
(
const
MCInst
&
Inst
,
unsigned
OpIdx
)
const
{
const
MCInstrDesc
&
Desc
=
MII
.
get
(
Inst
.
getOpcode
(
)
)
;
if
(
!
AMDGPU
::
isSISrcOperand
(
Desc
,
OpIdx
)
)
{
return
false
;
}
const
MCOperand
&
MO
=
Inst
.
getOperand
(
OpIdx
)
;
int64_t
Val
=
MO
.
getImm
(
)
;
auto
OpSize
=
AMDGPU
::
getOperandSize
(
Desc
,
OpIdx
)
;
switch
(
OpSize
)
{
case
8
:
return
AMDGPU
::
isInlinableLiteral64
(
Val
,
hasInv2PiInlineImm
(
)
)
;
case
4
:
return
AMDGPU
::
isInlinableLiteral32
(
Val
,
hasInv2PiInlineImm
(
)
)
;
case
2
:
{
const
unsigned
OperandType
=
Desc
.
OpInfo
[
OpIdx
]
.
OperandType
;
if
(
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
||
OperandType
==
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
||
OperandType
==
AMDGPU
::
OPERAND_REG_IMM_V2INT16
||
OperandType
==
AMDGPU
::
OPERAND_REG_IMM_V2FP16
)
{
return
AMDGPU
::
isInlinableLiteralV216
(
Val
,
hasInv2PiInlineImm
(
)
)
;
}
else
{
return
AMDGPU
::
isInlinableLiteral16
(
Val
,
hasInv2PiInlineImm
(
)
)
;
}
}
default
:
llvm_unreachable
(
"invalid operand size"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> SDValue SparcTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( Subtarget -> is64Bit ( ) ) return LowerFormalArguments_64 ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ; return LowerFormalArguments_32 ( Chain , CallConv , IsVarArg , Ins , DL , DAG , InVals ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> void R600SchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DAG = dag ; TII = static_cast < const R600InstrInfo * > ( DAG -> TII ) ; TRI = static_cast < const R600RegisterInfo * > ( DAG -> TRI ) ; MRI = & DAG -> MRI ; CurInstKind = IDOther ; CurEmitted = 0 ; OccupedSlotsMask = 31 ; InstKindLimit [ IDAlu ] = TII -> getMaxAlusPerClause ( ) ; InstKindLimit [ IDOther ] = 32 ; const AMDGPUSubtarget & ST = DAG -> TM . getSubtarget < AMDGPUSubtarget > ( ) ; InstKindLimit [ IDFetch ] = ST . getTexVTXClauseSize ( ) ; AluInstCount = 0 ; FetchInstCount = 0 ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> void AArch64InstrInfo :: suppressLdStPair ( MachineInstr & MI ) const { if ( MI . memoperands_empty ( ) ) return ; ( * MI . memoperands_begin ( ) ) -> setFlags ( MOSuppressPair ) ; } </s>

Hint that pairing the given load or store is unprofitable .


<s> bool MemSelOpt :: processInstruction ( MachineInstr * MI ) { bool Changed = false ; unsigned NumOperands = MI -> getNumOperands ( ) ; if ( NumOperands == 0 ) return false ; const TargetInstrDesc & TID = TII -> get ( MI -> getOpcode ( ) ) ; if ( ! ( TID . isCall ( ) || TID . mayLoad ( ) || TID . mayStore ( ) ) ) return false ; int MemOpPos = - 1 ; for ( unsigned i = 0 ; i < NumOperands ; i ++ ) { MachineOperand Op = MI -> getOperand ( i ) ; if ( Op . getType ( ) == MachineOperand :: MO_GlobalAddress || Op . getType ( ) == MachineOperand :: MO_ExternalSymbol ) { MemOpPos = i ; break ; } } if ( MemOpPos == - 1 ) return Changed ; MachineOperand & Op = MI -> getOperand ( MemOpPos ) ; if ( MI -> getOpcode ( ) == PIC16 :: CALL ) { DebugLoc dl = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , dl , TII -> get ( PIC16 :: pagesel ) ) . addOperand ( Op ) ; return true ; } std :: string NewBank = CurBank ; if ( Op . getType ( ) == MachineOperand :: MO_GlobalAddress && Op . getGlobal ( ) -> getType ( ) -> getAddressSpace ( ) == PIC16ISD :: RAM_SPACE ) { NewBank = Op . getGlobal ( ) -> getSection ( ) ; } else if ( Op . getType ( ) == MachineOperand :: MO_ExternalSymbol ) { std :: string Sym = Op . getSymbolName ( ) ; NewBank = PAN :: getSectionNameForSym ( Sym ) ; } if ( NewBank . compare ( CurBank ) != 0 ) { DebugLoc dl = MI -> getDebugLoc ( ) ; BuildMI ( * MBB , MI , dl , TII -> get ( PIC16 :: banksel ) ) . addOperand ( Op ) ; Changed = true ; CurBank = NewBank ; } return Changed ; } </s>

Process a single instruction and collect debug info anchors .


<s> bool SystemZDAGToDAGISel :: IsProfitableToFold ( SDValue N , SDNode * U , SDNode * Root ) const { if ( N . getOpcode ( ) == ISD :: LOAD && U -> getOpcode ( ) == SystemZISD :: ICMP ) { if ( ! N . hasOneUse ( ) || ! U -> hasOneUse ( ) ) return false ; SDNode * CCUser = * U -> use_begin ( ) ; SDNode * CCRegUser = nullptr ; if ( CCUser -> getOpcode ( ) == ISD :: CopyToReg || cast < RegisterSDNode > ( CCUser -> getOperand ( 1 ) ) -> getReg ( ) == SystemZ :: CC ) { for ( auto * U : CCUser -> uses ( ) ) { if ( CCRegUser == nullptr ) CCRegUser = U ; else if ( CCRegUser != U ) return false ; } } if ( CCRegUser == nullptr ) return false ; if ( CCRegUser -> isMachineOpcode ( ) && CCRegUser -> getMachineOpcode ( ) == SystemZ :: BRC ) return ! N -> isPredecessorOf ( CCUser -> getOperand ( 0 ) . getNode ( ) ) ; if ( ! IsLegalToFold ( N , U , CCRegUser , OptLevel , false ) ) return false ; } return true ; } </s>

IsProfitableToFold - Returns true if it 's profitable to fold the specific operand node N of U during instruction selection that starts at Root .

SystemZ SystemZ ISD::LOAD SystemZISD::ICMP ISD::CopyToReg 1 SystemZ::CC SystemZ::BRC 0


<s> const AMDGPUIntrinsicInfo * getIntrinsicInfo ( ) const override { return & IntrinsicInfo ; } </s>

If intrinsic information is available , return it . If not , return null .