<s> static void restore_saved_cr ( rtx reg , bool using_mfcr_multiple , bool exit_func ) { int count = 0 ; int i ; if ( using_mfcr_multiple ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) count ++ ; gcc_assert ( count ) ; } if ( using_mfcr_multiple && count > 1 ) { rtx_insn * insn ; rtvec p ; int ndx ; p = rtvec_alloc ( count ) ; ndx = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = reg ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - i ) ) ; RTVEC_ELT ( p , ndx ) = gen_rtx_SET ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , gen_rtx_UNSPEC ( CCmode , r , UNSPEC_MOVESI_TO_CR ) ) ; ndx ++ ; } insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; gcc_assert ( ndx == count ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } else for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) { rtx insn = emit_insn ( gen_movsi_to_cr_one ( gen_rtx_REG ( CCmode , CR0_REGNO + i ) , reg ) ) ; if ( ! exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap ) { add_reg_note ( insn , REG_CFA_RESTORE , gen_rtx_REG ( SImode , CR0_REGNO + i ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } if ( ! exit_func && DEFAULT_ABI != ABI_ELFv2 && ( DEFAULT_ABI == ABI_V4 || flag_shrink_wrap ) ) { rtx_insn * insn = get_last_insn ( ) ; rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; add_reg_note ( insn , REG_CFA_RESTORE , cr ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>


"Don't replace SQRT with RSQRT for half type"

Hooks for building estimates in place of slower divisions and square roots .


<s> static ds_t ia64_get_insn_checked_ds ( rtx_insn * insn ) { int code = get_insn_spec_code ( insn ) ; switch ( code ) { case UNSPEC_LDA : return BEGIN_DATA | BEGIN_CONTROL ; case UNSPEC_LDS : return BEGIN_CONTROL ; case UNSPEC_LDS_A : case UNSPEC_LDSA : return BEGIN_DATA | BEGIN_CONTROL ; default : return 0 ; } } </s>

If INSN is a speculative load return a ds with the speculation types that will be checked . Otherwise [ if INSN is a normal instruction ] return 0 .


<s> OperandMatchResultTy RISCVAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; RegNo = 0 ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( isRV32E ( ) , ( Register & ) RegNo , Name ) ) return MatchOperand_NoMatch ; getParser ( ) . Lex ( ) ; return MatchOperand_Success ; } </s>

tryParseRegister - parse one register if possible


<s> bool AArch64PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s>
bool
SIPreAllocateWWMRegs
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"SIPreAllocateWWMRegs: function "
<<
MF
.
getName
(
)
<<
"\n"
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
TII
=
ST
.
getInstrInfo
(
)
;
TRI
=
&
TII
->
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
LIS
=
&
getAnalysis
<
LiveIntervals
>
(
)
;
Matrix
=
&
getAnalysis
<
LiveRegMatrix
>
(
)
;
VRM
=
&
getAnalysis
<
VirtRegMap
>
(
)
;
RegClassInfo
.
runOnMachineFunction
(
MF
)
;
bool
RegsAssigned
=
false
;
ReversePostOrderTraversal
<
MachineFunction
*
>
RPOT
(
&
MF
)
;
for
(
MachineBasicBlock
*
MBB
:
RPOT
)
{
bool
InWWM
=
false
;
for
(
MachineInstr
&
MI
:
*
MBB
)
{
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
V_SET_INACTIVE_B32
||
MI
.
getOpcode
(
)
==
AMDGPU
::
V_SET_INACTIVE_B64
)
RegsAssigned
|=
processDef
(
MI
.
getOperand
(
0
)
)
;
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
ENTER_WWM
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"entering WWM region: "
<<
MI
<<
"\n"
)
;
InWWM
=
true
;
continue
;
}
if
(
MI
.
getOpcode
(
)
==
AMDGPU
::
EXIT_WWM
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"exiting WWM region: "
<<
MI
<<
"\n"
)
;
InWWM
=
false
;
}
if
(
!
InWWM
)
continue
;
LLVM_DEBUG
(
dbgs
(
)
<<
"processing "
<<
MI
<<
"\n"
)
;
for
(
MachineOperand
&
DefOpnd
:
MI
.
defs
(
)
)
{
RegsAssigned
|=
processDef
(
DefOpnd
)
;
}
}
}
if
(
!
RegsAssigned
)
return
false
;
rewriteRegs
(
MF
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .

AMDGPU
SI
"SIPreAllocateWWMRegs: function "
"\n"
AMDGPU::V_SET_INACTIVE_B32
AMDGPU::V_SET_INACTIVE_B64
0
AMDGPU::ENTER_WWM
"entering WWM region: "
"\n"
AMDGPU::EXIT_WWM
"exiting WWM region: "
"\n"
"processing "
"\n"


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_i32
:
case
WebAssembly
::
ARGUMENT_i32_S
:
case
WebAssembly
::
ARGUMENT_i64
:
case
WebAssembly
::
ARGUMENT_i64_S
:
case
WebAssembly
::
ARGUMENT_f32
:
case
WebAssembly
::
ARGUMENT_f32_S
:
case
WebAssembly
::
ARGUMENT_f64
:
case
WebAssembly
::
ARGUMENT_f64_S
:
case
WebAssembly
::
ARGUMENT_v16i8
:
case
WebAssembly
::
ARGUMENT_v16i8_S
:
case
WebAssembly
::
ARGUMENT_v8i16
:
case
WebAssembly
::
ARGUMENT_v8i16_S
:
case
WebAssembly
::
ARGUMENT_v4i32
:
case
WebAssembly
::
ARGUMENT_v4i32_S
:
case
WebAssembly
::
ARGUMENT_v2i64
:
case
WebAssembly
::
ARGUMENT_v2i64_S
:
case
WebAssembly
::
ARGUMENT_v4f32
:
case
WebAssembly
::
ARGUMENT_v4f32_S
:
case
WebAssembly
::
ARGUMENT_v2f64
:
case
WebAssembly
::
ARGUMENT_v2f64_S
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN_I32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2i64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2i64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2f64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2f64_S
:
{
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return-value"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID
:
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID_S
:
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return-void"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


getPassName - Return a nice clean name for a pass .


<s> static int rs6000_reassociation_width ( unsigned int opc ATTRIBUTE_UNUSED , machine_mode mode ) { switch ( rs6000_tune ) { case PROCESSOR_POWER8 : case PROCESSOR_POWER9 : if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return 1 ; if ( VECTOR_MODE_P ( mode ) ) return 4 ; if ( INTEGRAL_MODE_P ( mode ) ) return 1 ; if ( FLOAT_MODE_P ( mode ) ) return 4 ; break ; default : break ; } return 1 ; } </s>

Determine the reassociation width to be used in reassociate_bb . This takes into account how many parallel operations we can actually do of a given type , and also the latency . P8 : int add/sub 6/cycle mul 2/cycle vect add/sub/mul 2/cycle fp add/sub/mul 2/cycle dfp 1/cycle


<s> static bool s390_function_arg_float ( machine_mode mode , const_tree type ) { if ( s390_function_arg_size ( mode , type ) > 8 ) return false ; if ( TARGET_SOFT_FLOAT ) return false ; if ( ! type ) return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode ; if ( ! s390_single_field_struct_p ( REAL_TYPE , type , false ) ) return false ; return true ; } </s>

Return true if a function argument of type TYPE and mode MODE is to be passed in a floating-point register , if available .


<s> bool SITargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( VT == MVT :: Other || ( VT != MVT :: Other && VT . getSizeInBits ( ) > 1024 && VT . getStoreSize ( ) > 16 ) ) { return false ; } return allowsMisalignedMemoryAccessesImpl ( VT . getSizeInBits ( ) , AddrSpace , Alignment , Flags , IsFast ) ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> static rtx pa_trampoline_adjust_address ( rtx addr ) { if ( ! TARGET_64BIT ) addr = memory_address ( Pmode , plus_constant ( Pmode , addr , 46 ) ) ; return addr ; } </s>

Perform any machine-specific adjustment in the address of the trampoline . ADDR contains the address that was passed to pa_trampoline_init . Adjust the trampoline address to point to the plabel at offset 44 .


<s> rtx ix86_build_const_vector ( machine_mode mode , bool vect , rtx value ) { int i , n_elt ; rtvec v ; machine_mode scalar_mode ; switch ( mode ) { case E_V64QImode : case E_V32QImode : case E_V16QImode : case E_V32HImode : case E_V16HImode : case E_V8HImode : case E_V16SImode : case E_V8SImode : case E_V4SImode : case E_V2SImode : case E_V8DImode : case E_V4DImode : case E_V2DImode : gcc_assert ( vect ) ; case E_V8HFmode : case E_V16HFmode : case E_V32HFmode : case E_V16SFmode : case E_V8SFmode : case E_V4SFmode : case E_V2SFmode : case E_V8DFmode : case E_V4DFmode : case E_V2DFmode : n_elt = GET_MODE_NUNITS ( mode ) ; v = rtvec_alloc ( n_elt ) ; scalar_mode = GET_MODE_INNER ( mode ) ; RTVEC_ELT ( v , 0 ) = value ; for ( i = 1 ; i < n_elt ; ++ i ) RTVEC_ELT ( v , i ) = vect ? value : CONST0_RTX ( scalar_mode ) ; return gen_rtx_CONST_VECTOR ( mode , v ) ; default : gcc_unreachable ( ) ; } } </s>

A subroutine of ix86_build_signbit_mask . If VECT is true , then replicate the value for all elements of the vector register .


<s> void AnalyzeFormalArguments ( const SmallVectorImpl < ISD :: InputArg > & Ins , CCAssignFn Fn ) { PreAnalyzeFormalArgumentsForF128 ( Ins ) ; CCState :: AnalyzeFormalArguments ( Ins , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; } </s>

AnalyzeFormalArguments - Analyze an array of argument values , incorporating info about the formals into this state .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 pseudo instruction expansion pass"
;
}
</s>


<s> const LEGRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool Z80InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AliasAnalysis * AA ) const { switch ( MI . getOpcode ( ) ) { case Z80 :: LD8r0 : case Z80 :: LD24r0 : case Z80 :: LD24r_1 : return true ; } return false ; } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> bool AArch64FastISel :: fastSelectInstruction ( const Instruction * I ) { switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Add : case Instruction :: Sub : return selectAddSub ( I ) ; case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , ISD :: SREM ) ) return selectRem ( I , ISD :: SREM ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , ISD :: UREM ) ) return selectRem ( I , ISD :: UREM ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , ISD :: FP_TO_SINT ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , ISD :: TRUNCATE ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , ISD :: SINT_TO_FP ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; case Instruction :: GetElementPtr : return selectGetElementPtr ( I ) ; case Instruction :: AtomicCmpXchg : return selectAtomicCmpXchg ( cast < AtomicCmpXchgInst > ( I ) ) ; } return selectOperator ( I , I -> getOpcode ( ) ) ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> void X86CallLowering :: splitToValueTypes ( const ArgInfo & OrigArg , SmallVectorImpl < ArgInfo > & SplitArgs , const DataLayout & DL , MachineRegisterInfo & MRI , SplitArgTy PerformArgSplit ) const { const X86TargetLowering & TLI = * getTLI < X86TargetLowering > ( ) ; LLVMContext & Context = OrigArg . Ty -> getContext ( ) ; EVT VT = TLI . getValueType ( DL , OrigArg . Ty ) ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == 1 ) { SplitArgs . emplace_back ( OrigArg . Reg , VT . getTypeForEVT ( Context ) , OrigArg . Flags , OrigArg . IsFixed ) ; return ; } SmallVector < uint64_t , 4 > BitOffsets ; SmallVector < unsigned , 8 > SplitRegs ; EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = 0 ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * PartTy , DL ) ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; PerformArgSplit ( Info . Reg , PartVT . getSizeInBits ( ) * i ) ; } } </s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


<s> bool EnqueueExitsPass :: runOnMachineFunction ( MachineFunction & Func ) { Func . enqueueExitBlock ( ) ; return true ; } </s>


<s> static bool nios2_large_offset_p ( int unspec ) { gcc_assert ( nios2_unspec_reloc_name ( unspec ) != NULL ) ; if ( flag_pic == 2 && ( unspec == UNSPEC_PIC_SYM || unspec == UNSPEC_PIC_CALL_SYM ) ) return true ; if ( unspec == UNSPEC_PIC_GOTOFF_SYM ) return true ; return false ; } </s>

Return true for large offsets requiring hiadj/lo relocation pairs .


<s>
const
AArch64GOT
&
AArch64GNULDBackend
::
getGOT
(
)
const
{
assert
(
m_pGOT
!=
&&
"GOT section not exist"
)
;
return
*
m_pGOT
;
}
</s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Dead register definitions"
;
}
</s>


<s> bool sh_cfun_trap_exit_p ( void ) { return lookup_attribute ( "trap_exit" , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ; } </s>

Returns true if the current function has a `` trap_exit '' attribute set .


<s> void arc_set_default_type_attributes ( tree type ATTRIBUTE_UNUSED ) { gcc_unreachable ( ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos YAML/PML Module Export"
;
}
</s>


<s>
bool
AArch64AdvSIMDScalar
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
bool
Changed
=
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64AdvSIMDScalar *****\n"
)
;
const
TargetMachine
&
TM
=
mf
.
getTarget
(
)
;
MRI
=
&
mf
.
getRegInfo
(
)
;
TII
=
static_cast
<
const
AArch64InstrInfo
*
>
(
TM
.
getInstrInfo
(
)
)
;
for
(
MachineFunction
::
iterator
I
=
mf
.
begin
(
)
,
E
=
mf
.
end
(
)
;
I
!=
E
;
++
I
)
if
(
processMachineBasicBlock
(
I
)
)
Changed
=
true
;
return
Changed
;
}
</s>


<s> static bool nds32_have_prologue_p ( void ) { int i ; for ( i = 0 ; i < 28 ; i ++ ) if ( NDS32_REQUIRED_CALLEE_SAVED_P ( i ) ) return true ; return ( flag_pic || NDS32_REQUIRED_CALLEE_SAVED_P ( FP_REGNUM ) || NDS32_REQUIRED_CALLEE_SAVED_P ( LP_REGNUM ) ) ; } </s>

A helper function to check if this function should contain prologue .


<s> bool BPFAsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return SystemZ :: R7D ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
MIRBuilder
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
MIRBuilder
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeSmallCMGlobalValue
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_TRUNC
:
return
legalizeVectorTrunc
(
MI
,
Helper
)
;
case
TargetOpcode
::
G_SBFX
:
case
TargetOpcode
::
G_UBFX
:
return
legalizeBitfieldExtract
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ROTR
:
return
legalizeRotate
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTPOP
:
return
legalizeCTPOP
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpxchg128
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTTZ
:
return
legalizeCTTZ
(
MI
,
Helper
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> bool allowPositionIndependentMovt ( ) const { return isROPI ( ) || ! isTargetELF ( ) ; } </s>

Allow movt+movw for PIC global address calculation .


"-mfdpic is not supported, please use a bfin-linux-uclibc target"

"-mshared-library-id= specified without -mid-shared-library"

"-fstack-limit- options are ignored with -mfdpic; use -mstack-check-l1"

"can%'t use multiple stack checking methods together"

"ID shared libraries and FD-PIC mode can%'t be used together"

"cannot specify both -msep-data and -mid-shared-library"

"-mmulticore can only be used with BF561"

"-mcorea should be used with -mmulticore"

"-mcoreb should be used with -mmulticore"

"-mcorea and -mcoreb can%'t be used together"

Implement the TARGET_OPTION_OVERRIDE hook .


<s> void loongarch_expand_conditional_branch ( rtx * operands ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; rtx op0 = operands [ 1 ] ; rtx op1 = operands [ 2 ] ; rtx condition ; if ( FLOAT_MODE_P ( GET_MODE ( op1 ) ) ) loongarch_emit_float_compare ( & code , & op0 , & op1 ) ; else loongarch_emit_int_compare ( & code , & op0 , & op1 ) ; condition = gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ; emit_jump_insn ( gen_condjump ( condition , operands [ 3 ] ) ) ; } </s>

Compare OPERANDS [ 1 ] with OPERANDS [ 2 ] using comparison code CODE and jump to OPERANDS [ 3 ] if the condition holds .


<s> void P2AsmPrinter :: emitStartOfAsmFile ( Module & M ) { } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> void BPFAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { if ( Fixup . getKind ( ) == FK_SecRel_4 || Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value == 0 ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 ) { support :: endian :: write < uint32_t > ( & Data [ Fixup . getOffset ( ) ] , Value , Endian ) ; } else if ( Fixup . getKind ( ) == FK_Data_8 ) { support :: endian :: write < uint64_t > ( & Data [ Fixup . getOffset ( ) ] , Value , Endian ) ; } else if ( Fixup . getKind ( ) == FK_PCRel_4 ) { Value = ( uint32_t ) ( ( Value - 8 ) / 8 ) ; if ( Endian == support :: little ) { Data [ Fixup . getOffset ( ) + 1 ] = 0x10 ; support :: endian :: write32le ( & Data [ Fixup . getOffset ( ) + 4 ] , Value ) ; } else { Data [ Fixup . getOffset ( ) + 1 ] = 0x1 ; support :: endian :: write32be ( & Data [ Fixup . getOffset ( ) + 4 ] , Value ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - 8 ) / 8 ) ; support :: endian :: write < uint16_t > ( & Data [ Fixup . getOffset ( ) + 2 ] , Value , Endian ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

ARM ARM ARM::SP ARM::PC ARM::FPSCR ARM::R9


<s> bool hasReservedCallFrame ( MachineFunction & MF ) const { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


"mnop-mcount only supported with fentry-call"

"mrecord-mcount only supported with fentry-call"

runOnMachineFunction - Emit the function body .


<s>
void
XCoreTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
{
switch
(
N
->
getOpcode
(
)
)
{
default
:
assert
(
0
&&
"Don't know how to custom expand this!"
)
;
return
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
Results
.
push_back
(
ExpandADDSUB
(
N
,
DAG
)
)
;
return
;
}
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

XCore
XCore
0
"Don't know how to custom expand this!"
ISD::ADD
ISD::SUB


<s> void SparcTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( 0 , 0 ) ; if ( Constraint . length ( ) > 1 ) return ; char ConstraintLetter = Constraint [ 0 ] ; switch ( ConstraintLetter ) { default : break ; case 'I' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , Op . getValueType ( ) ) ; break ; } return ; } } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; } TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; } </s>

Lower the specified operand into the Ops vector .


<s>
bool
RISCVInsertVSETVLI
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
const
RISCVSubtarget
&
ST
=
MF
.
getSubtarget
<
RISCVSubtarget
>
(
)
;
if
(
!
ST
.
hasVInstructions
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Entering InsertVSETVLI for "
<<
MF
.
getName
(
)
<<
"\n"
)
;
TII
=
ST
.
getInstrInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
assert
(
BlockInfo
.
empty
(
)
&&
"Expect empty block infos"
)
;
BlockInfo
.
resize
(
MF
.
getNumBlockIDs
(
)
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
doLocalPrepass
(
MBB
)
;
bool
HaveVectorOp
=
false
;
for
(
const
MachineBasicBlock
&
MBB
:
MF
)
{
HaveVectorOp
|=
computeVLVTYPEChanges
(
MBB
)
;
BlockData
&
BBInfo
=
BlockInfo
[
MBB
.
getNumber
(
)
]
;
BBInfo
.
Exit
=
BBInfo
.
Change
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Initial exit state of "
<<
printMBBReference
(
MBB
)
<<
" is "
<<
BBInfo
.
Exit
<<
"\n"
)
;
}
if
(
!
HaveVectorOp
)
{
BlockInfo
.
clear
(
)
;
return
false
;
}
for
(
const
MachineBasicBlock
&
MBB
:
MF
)
{
WorkList
.
push
(
&
MBB
)
;
BlockInfo
[
MBB
.
getNumber
(
)
]
.
InQueue
=
true
;
}
while
(
!
WorkList
.
empty
(
)
)
{
const
MachineBasicBlock
&
MBB
=
*
WorkList
.
front
(
)
;
WorkList
.
pop
(
)
;
computeIncomingVLVTYPE
(
MBB
)
;
}
for
(
MachineBasicBlock
&
MBB
:
MF
)
doPRE
(
MBB
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
emitVSETVLIs
(
MBB
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
doLocalPostpass
(
MBB
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
if
(
MI
.
getOpcode
(
)
==
RISCV
::
PseudoVSETVLI
||
MI
.
getOpcode
(
)
==
RISCV
::
PseudoVSETIVLI
)
{
Register
VRegDef
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
VRegDef
!=
RISCV
::
X0
&&
MRI
->
use_nodbg_empty
(
VRegDef
)
)
MI
.
getOperand
(
0
)
.
setReg
(
RISCV
::
X0
)
;
}
}
}
BlockInfo
.
clear
(
)
;
return
HaveVectorOp
;
}
</s>

RISCV
RISCV
RISCV
RISCV
"Entering InsertVSETVLI for "
"\n"
"Expect empty block infos"
"Initial exit state of "
" is "
"\n"
RISCV::PseudoVSETVLI
RISCV::PseudoVSETIVLI
0
RISCV::X0
0
RISCV::X0


<s> SDValue MipsSETargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: SMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Mult , true , true , DAG ) ; case ISD :: UMUL_LOHI : return lowerMulDiv ( Op , MipsISD :: Multu , true , true , DAG ) ; case ISD :: MULHS : return lowerMulDiv ( Op , MipsISD :: Mult , false , true , DAG ) ; case ISD :: MULHU : return lowerMulDiv ( Op , MipsISD :: Multu , false , true , DAG ) ; case ISD :: MUL : return lowerMulDiv ( Op , MipsISD :: Mult , true , false , DAG ) ; case ISD :: SDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRem , true , true , DAG ) ; case ISD :: UDIVREM : return lowerMulDiv ( Op , MipsISD :: DivRemU , true , true , DAG ) ; case ISD :: INTRINSIC_WO_CHAIN : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return lowerINTRINSIC_W_CHAIN ( Op , DAG ) ; case ISD :: INTRINSIC_VOID : return lowerINTRINSIC_VOID ( Op , DAG ) ; case ISD :: EXTRACT_VECTOR_ELT : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case ISD :: BUILD_VECTOR : return lowerBUILD_VECTOR ( Op , DAG ) ; case ISD :: VECTOR_SHUFFLE : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: BITCAST : return lowerBITCAST ( Op , DAG ) ; } return MipsTargetLowering :: LowerOperation ( Op , DAG ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::LOAD ISD::STORE ISD::SMUL_LOHI MipsISD::Mult ISD::UMUL_LOHI MipsISD::Multu ISD::MULHS MipsISD::Mult ISD::MULHU MipsISD::Multu ISD::MUL MipsISD::Mult ISD::SDIVREM MipsISD::DivRem ISD::UDIVREM MipsISD::DivRemU ISD::INTRINSIC_WO_CHAIN ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_VOID ISD::EXTRACT_VECTOR_ELT ISD::BUILD_VECTOR ISD::VECTOR_SHUFFLE ISD::SELECT ISD::BITCAST Mips


<s> static std :: unique_ptr < AArch64Operand > CreateReg ( unsigned RegNum , RegKind Kind , SMLoc S , SMLoc E , MCContext & Ctx , RegConstraintEqualityTy EqTy = RegConstraintEqualityTy :: EqualsReg , AArch64_AM :: ShiftExtendType ExtTy = AArch64_AM :: LSL , unsigned ShiftAmount = 0 , unsigned HasExplicitAmount = false ) { auto Op = std :: make_unique < AArch64Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = Kind ; Op -> Reg . ElementWidth = 0 ; Op -> Reg . EqualityTy = EqTy ; Op -> Reg . ShiftExtend . Type = ExtTy ; Op -> Reg . ShiftExtend . Amount = ShiftAmount ; Op -> Reg . ShiftExtend . HasExplicitAmount = HasExplicitAmount ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static struct machine_function * tilegx_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Functions to save and restore machine-specific function data .


<s> int CAHPFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( ( FI >= MinCSFI && FI <= MaxCSFI ) || ! hasFP ( MF ) ) { FrameReg = CAHP :: X1 ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


"Nested function trampolines not supported on CK801."

Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE . Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts . Note that STATIC_CHAIN_REGNUM is t1 ( aka r12 ) on ck801 and t1 ( r13 ) otherwise .


<s> bool SIInstrInfo :: hasVALU32BitEncoding ( unsigned Opcode ) const { return AMDGPU :: getVOPe32 ( Opcode ) != - 1 ; } </s>

Return true if this 64-bit VALU instruction has a 32-bit encoding .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s> const CJGInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> bool bfin_expand_strmov ( rtx dst , rtx src , rtx count_exp , rtx align_exp ) { rtx srcreg , destreg , countreg ; HOST_WIDE_INT align = 0 ; unsigned HOST_WIDE_INT count = 0 ; if ( GET_CODE ( align_exp ) == CONST_INT ) align = INTVAL ( align_exp ) ; if ( GET_CODE ( count_exp ) == CONST_INT ) { count = INTVAL ( count_exp ) ; if ( ! TARGET_INLINE_ALL_STRINGOPS && count > 64 ) return false ; } if ( optimize_size ) { if ( count == 2 && align < 2 ) return false ; if ( count == 4 && align < 4 ) return false ; if ( count != 1 && count != 2 && count != 4 ) return false ; } if ( align < 2 && count != 1 ) return false ; destreg = copy_to_mode_reg ( Pmode , XEXP ( dst , 0 ) ) ; if ( destreg != XEXP ( dst , 0 ) ) dst = replace_equiv_address_nv ( dst , destreg ) ; srcreg = copy_to_mode_reg ( Pmode , XEXP ( src , 0 ) ) ; if ( srcreg != XEXP ( src , 0 ) ) src = replace_equiv_address_nv ( src , srcreg ) ; if ( count != 0 && align >= 2 ) { unsigned HOST_WIDE_INT offset = 0 ; if ( align >= 4 ) { if ( ( count & ~ 3 ) == 4 ) { single_move_for_strmov ( dst , src , SImode , offset ) ; offset = 4 ; } else if ( count & ~ 3 ) { HOST_WIDE_INT new_count = ( ( count >> 2 ) & 0x3fffffff ) - 1 ; countreg = copy_to_mode_reg ( Pmode , GEN_INT ( new_count ) ) ; emit_insn ( gen_rep_movsi ( destreg , srcreg , countreg , destreg , srcreg ) ) ; } if ( count & 2 ) { single_move_for_strmov ( dst , src , HImode , offset ) ; offset += 2 ; } } else { if ( ( count & ~ 1 ) == 2 ) { single_move_for_strmov ( dst , src , HImode , offset ) ; offset = 2 ; } else if ( count & ~ 1 ) { HOST_WIDE_INT new_count = ( ( count >> 1 ) & 0x7fffffff ) - 1 ; countreg = copy_to_mode_reg ( Pmode , GEN_INT ( new_count ) ) ; emit_insn ( gen_rep_movhi ( destreg , srcreg , countreg , destreg , srcreg ) ) ; } } if ( count & 1 ) { single_move_for_strmov ( dst , src , QImode , offset ) ; } return true ; } return false ; } </s>

Expand a string move operation of COUNT_EXP bytes from SRC to DST , with alignment ALIGN_EXP . Return true if successful , false if we should fall back on a different method .


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) return true ; switch ( I . getOpcode ( ) ) { default : break ; case TargetOpcode :: G_FPTOUI : case TargetOpcode :: G_OR : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_LOAD : return selectG_LOAD ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> RISCVTargetLowering :: ConstraintType RISCVTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'f' : return C_RegisterClass ; case 'I' : case 'J' : case 'K' : return C_Immediate ; case 'A' : return C_Memory ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> bool X86TTIImpl :: isLegalBroadcastLoad ( Type * ElementTy , unsigned NumElements ) const { return ST -> hasSSE3 ( ) && NumElements == 2 && ElementTy == Type :: getDoubleTy ( ElementTy -> getContext ( ) ) ; } </s>

\Returns true if the target supports broadcasting a load to a vector of type < NumElements x ElementTy > .


<s> const NyuziInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s>
static
int
s390_fn_types_compatible
(
enum
s390_builtin_ov_type_index
typeindex
,
vec
<
tree
,
va_gc
>
*
arglist
)
{
unsigned
int
i
;
int
match_type
=
0
;
for
(
i
=
0
;
i
<
vec_safe_length
(
arglist
)
;
i
++
)
{
tree
b_arg_type
=
s390_builtin_types
[
s390_builtin_ov_types
[
typeindex
]
[
i
+
1
]
]
;
tree
in_arg
=
(
*
arglist
)
[
i
]
;
tree
in_type
=
TREE_TYPE
(
in_arg
)
;
if
(
TREE_CODE
(
b_arg_type
)
==
VECTOR_TYPE
)
{
if
(
b_arg_type
!=
in_type
&&
TYPE_MAIN_VARIANT
(
b_arg_type
)
!=
TYPE_MAIN_VARIANT
(
in_type
)
)
goto
mismatch
;
}
if
(
lang_hooks
.
types_compatible_p
(
in_type
,
b_arg_type
)
)
continue
;
if
(
lang_hooks
.
types_compatible_p
(
lang_hooks
.
types
.
type_promotes_to
(
in_type
)
,
lang_hooks
.
types
.
type_promotes_to
(
b_arg_type
)
)
)
{
match_type
++
;
continue
;
}
if
(
TREE_CODE
(
b_arg_type
)
==
INTEGER_TYPE
&&
TREE_CODE
(
in_type
)
==
INTEGER_TYPE
)
{
match_type
++
;
continue
;
}
if
(
POINTER_TYPE_P
(
b_arg_type
)
&&
POINTER_TYPE_P
(
in_type
)
&&
!
(
TYPE_QUALS
(
TREE_TYPE
(
in_type
)
)
&
~
TYPE_QUALS
(
TREE_TYPE
(
b_arg_type
)
)
)
&&
(
TYPE_QUALS
(
TREE_TYPE
(
b_arg_type
)
)
&
~
TYPE_QUALS
(
TREE_TYPE
(
in_type
)
)
)
)
{
tree
qual_in_type
=
build_qualified_type
(
TREE_TYPE
(
in_type
)
,
TYPE_QUALS
(
TREE_TYPE
(
b_arg_type
)
)
)
;
if
(
lang_hooks
.
types_compatible_p
(
qual_in_type
,
TREE_TYPE
(
b_arg_type
)
)
)
{
match_type
++
;
continue
;
}
}
mismatch
:
if
(
TARGET_DEBUG_ARG
)
{
fprintf
(
stderr
,
" mismatch in operand: %d incoming: "
,
i
+
1
)
;
print_generic_expr
(
stderr
,
in_type
,
TDF_VOPS
|
TDF_MEMSYMS
)
;
fprintf
(
stderr
,
" expected: "
)
;
print_generic_expr
(
stderr
,
b_arg_type
,
TDF_VOPS
|
TDF_MEMSYMS
)
;
fprintf
(
stderr
,
"\n"
)
;
}
return
INT_MAX
;
}
return
match_type
;
}
</s>

Check whether the arguments in ARGLIST match the function type DEF_TYPE . Return the number of argument types which required conversion/promotion in order to make it match . 0 stands for a perfect match - all operand types match without changes INT_MAX stands for a mismatch .


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; const MipsSubtarget & ST = MF . getTarget ( ) . getSubtarget < MipsSubtarget > ( ) ; const TargetRegisterClass * RC = ST . inMips16Mode ( ) ? & Mips :: CPU16RegsRegClass : ST . isABI_N64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> int bfin_hard_regno_rename_ok ( unsigned int old_reg ATTRIBUTE_UNUSED , unsigned int new_reg ) { if ( funkind ( TREE_TYPE ( current_function_decl ) ) != SUBROUTINE && ! regs_ever_live [ new_reg ] ) return 0 ; return 1 ; } </s>

Return nonzero if register OLD_REG can be renamed to register NEW_REG .


<s> int vfp3_const_double_for_bits ( rtx x ) { const REAL_VALUE_TYPE * r ; if ( ! CONST_DOUBLE_P ( x ) ) return - 1 ; r = CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_NEGATIVE ( * r ) || REAL_VALUE_ISNAN ( * r ) || REAL_VALUE_ISINF ( * r ) || ! real_isinteger ( r , SFmode ) ) return - 1 ; HOST_WIDE_INT hwint = exact_log2 ( real_to_integer ( r ) ) ; if ( ! IN_RANGE ( hwint , 1 , 32 ) ) return - 1 ; return hwint ; } </s>

If X is a CONST_DOUBLE with a value that is a power of 2 whose log2 is in [ 1 , 32 ] , return that log2 . Otherwise return -1 . This is used in the patterns for vcvt.s32.f32 floating-point to fixed-point conversions .


<s> void Initialize ( MCContext & ctx , const TargetMachine & TM ) override { TargetLoweringObjectFile :: Initialize ( ctx , TM ) ; } </s>

This method must be called before any actual lowering is done .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetInstrInfo & TII , DebugLoc dl , const Thumb1RegisterInfo & MRI , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags ) { emitThumbRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , TII , MRI , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s>
unsigned
HexagonInstrInfo
::
reduceLoopCount
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
&
PreHeader
,
MachineInstr
*
IndVar
,
MachineInstr
&
Cmp
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
SmallVectorImpl
<
MachineInstr
*
>
&
PrevInsts
,
unsigned
Iter
,
unsigned
MaxIter
)
const
{
assert
(
(
!
IndVar
)
&&
isEndLoopN
(
Cmp
.
getOpcode
(
)
)
&&
"Expecting a hardware loop"
)
;
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
DebugLoc
DL
=
Cmp
.
getDebugLoc
(
)
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
VisitedBBs
;
MachineInstr
*
Loop
=
findLoopInstr
(
&
MBB
,
Cmp
.
getOpcode
(
)
,
Cmp
.
getOperand
(
0
)
.
getMBB
(
)
,
VisitedBBs
)
;
if
(
!
Loop
)
return
0
;
if
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0i
||
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop1i
)
{
int64_t
Offset
=
Loop
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
Offset
<=
1
)
Loop
->
eraseFromParent
(
)
;
else
Loop
->
getOperand
(
1
)
.
setImm
(
Offset
1
)
;
return
Offset
1
;
}
assert
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0r
&&
"Unexpected instruction"
)
;
unsigned
LoopCount
=
Loop
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
LoopEnd
=
createVR
(
MF
,
MVT
::
i1
)
;
MachineInstr
*
NewCmp
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
C2_cmpgtui
)
,
LoopEnd
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
unsigned
NewLoopCount
=
createVR
(
MF
,
MVT
::
i32
)
;
MachineInstr
*
NewAdd
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
A2_addi
)
,
NewLoopCount
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
const
HexagonRegisterInfo
&
HRI
=
*
Subtarget
.
getRegisterInfo
(
)
;
for
(
SmallVectorImpl
<
MachineInstr
*
>
::
iterator
I
=
PrevInsts
.
begin
(
)
,
E
=
PrevInsts
.
end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
substituteRegister
(
LoopCount
,
NewLoopCount
,
0
,
HRI
)
;
PrevInsts
.
clear
(
)
;
PrevInsts
.
push_back
(
NewCmp
)
;
PrevInsts
.
push_back
(
NewAdd
)
;
if
(
Iter
==
MaxIter
)
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
J2_loop0r
)
)
.
addMBB
(
Loop
->
getOperand
(
0
)
.
getMBB
(
)
)
.
addReg
(
NewLoopCount
)
;
if
(
Iter
==
0
)
Loop
->
eraseFromParent
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Hexagon
::
J2_jumpf
)
)
;
Cond
.
push_back
(
NewCmp
->
getOperand
(
0
)
)
;
return
NewLoopCount
;
}
</s>

Generate code to reduce the loop iteration by one and check if the loop is finished .


<s>
static
void
make_type_sizeless
(
tree
type
)
{
TYPE_ATTRIBUTES
(
type
)
=
tree_cons
(
get_identifier
(
"RVV sizeless type"
)
,
NULL_TREE
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>


"  num_insn = %d, num_uops = %d, window_size = %d\n"

"  num_imm = %d, num_imm_32 = %d, num_imm_64 = %d, imm_size = %d\n"

"    group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n"

Print the dispatch window , WINDOW_NUM , to FILE .


<s> static void increment_stack ( signed int amount , bool in_prologue ) { rtx inc ; if ( amount == 0 ) return ; inc = GEN_INT ( amount ) ; if ( ! CONST_OK_FOR_K ( amount ) ) { rtx reg = gen_rtx_REG ( Pmode , 12 ) ; inc = emit_move_insn ( reg , inc ) ; if ( in_prologue ) F ( inc ) ; inc = reg ; } inc = emit_insn ( gen_addsi3_clobber_flags ( stack_pointer_rtx , stack_pointer_rtx , inc ) ) ; if ( in_prologue ) F ( inc ) ; } </s>

Common code to change the stack pointer .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGlobalMergePass ( TM , 127 ) ) ; return false ; } </s>


<s>
SDValue
BlackfinTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Blackfin
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Opi
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
Opi
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
ZExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
AExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Opi
,
SDValue
(
)
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
}
else
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
void
SparcMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
unsigned
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
if
(
Ctx
.
getAsmInfo
(
)
->
isLittleEndian
(
)
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
unsigned
tlsOpNo
=
0
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
SP
::
TLS_CALL
:
tlsOpNo
=
1
;
break
;
case
SP
::
TLS_ADDrr
:
case
SP
::
TLS_ADDXrr
:
case
SP
::
TLS_LDrr
:
case
SP
::
TLS_LDXrr
:
tlsOpNo
=
3
;
break
;
}
if
(
tlsOpNo
!=
0
)
{
const
MCOperand
&
MO
=
MI
.
getOperand
(
tlsOpNo
)
;
uint64_t
op
=
getMachineOpValue
(
MI
,
MO
,
Fixups
,
STI
)
;
assert
(
op
==
0
&&
"Unexpected operand value!"
)
;
(
void
)
op
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr & MI , SDNode * Node ) const { const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( TII -> isVOP3 ( MI . getOpcode ( ) ) ) { TII -> legalizeOperandsVOP3 ( MRI , MI ) ; if ( const MCOperandInfo * OpInfo = MI . getDesc ( ) . OpInfo ) { unsigned Opc = MI . getOpcode ( ) ; const SIRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; for ( auto I : { AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) , AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) } ) { if ( I == - 1 ) break ; MachineOperand & Op = MI . getOperand ( I ) ; if ( ( OpInfo [ I ] . RegClass != llvm :: AMDGPU :: AV_64RegClassID && OpInfo [ I ] . RegClass != llvm :: AMDGPU :: AV_32RegClassID ) || ! Op . getReg ( ) . isVirtual ( ) || ! TRI -> isAGPR ( MRI , Op . getReg ( ) ) ) continue ; auto * Src = MRI . getUniqueVRegDef ( Op . getReg ( ) ) ; if ( ! Src || ! Src -> isCopy ( ) || ! TRI -> isSGPRReg ( MRI , Src -> getOperand ( 1 ) . getReg ( ) ) ) continue ; auto * RC = TRI -> getRegClassForReg ( MRI , Op . getReg ( ) ) ; auto * NewRC = TRI -> getEquivalentVGPRClass ( RC ) ; MRI . setRegClass ( Op . getReg ( ) , NewRC ) ; } } return ; } int NoRetAtomicOp = AMDGPU :: getAtomicNoRetOp ( MI . getOpcode ( ) ) ; if ( NoRetAtomicOp != - 1 ) { if ( ! Node -> hasAnyUseOfValue ( 0 ) ) { MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; return ; } if ( ( Node -> hasNUsesOfValue ( 1 , 0 ) && Node -> use_begin ( ) -> isMachineOpcode ( ) && Node -> use_begin ( ) -> getMachineOpcode ( ) == AMDGPU :: EXTRACT_SUBREG && ! Node -> use_begin ( ) -> hasAnyUseOfValue ( 0 ) ) ) { Register Def = MI . getOperand ( 0 ) . getReg ( ) ; MI . setDesc ( TII -> get ( NoRetAtomicOp ) ) ; MI . RemoveOperand ( 0 ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: IMPLICIT_DEF ) , Def ) ; } return ; } } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> virtual const MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM ) const { return DataSection ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s>
void
MipsRegisterBankInfo
::
applyMappingImpl
(
const
OperandsMapper
&
OpdMapper
)
const
{
MachineInstr
&
MI
=
OpdMapper
.
getMI
(
)
;
InstListTy
NewInstrs
;
MachineIRBuilder
B
(
MI
)
;
MachineFunction
*
MF
=
MI
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
OpdMapper
.
getMRI
(
)
;
InstManager
NewInstrObserver
(
NewInstrs
)
;
GISelObserverWrapper
WrapperObserver
(
&
NewInstrObserver
)
;
LegalizerHelper
Helper
(
*
MF
,
WrapperObserver
,
B
)
;
LegalizationArtifactCombiner
ArtCombiner
(
B
,
MF
->
getRegInfo
(
)
,
*
MF
->
getSubtarget
(
)
.
getLegalizerInfo
(
)
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
case
TargetOpcode
::
G_PHI
:
case
TargetOpcode
::
G_SELECT
:
case
TargetOpcode
::
G_IMPLICIT_DEF
:
{
Helper
.
narrowScalar
(
MI
,
0
,
LLT
::
scalar
(
32
)
)
;
while
(
!
NewInstrs
.
empty
(
)
)
{
MachineInstr
*
NewMI
=
NewInstrs
.
pop_back_val
(
)
;
if
(
NewMI
->
getOpcode
(
)
==
TargetOpcode
::
G_UNMERGE_VALUES
)
{
SmallVector
<
MachineInstr
*
,
2
>
DeadInstrs
;
ArtCombiner
.
tryCombineMerges
(
*
NewMI
,
DeadInstrs
)
;
for
(
MachineInstr
*
DeadMI
:
DeadInstrs
)
DeadMI
->
eraseFromParent
(
)
;
}
else
if
(
NewMI
->
getOpcode
(
)
==
TargetOpcode
::
G_MERGE_VALUES
)
continue
;
else
for
(
auto
Op
:
NewMI
->
operands
(
)
)
{
if
(
Op
.
isReg
(
)
)
{
assert
(
MRI
.
getType
(
Op
.
getReg
(
)
)
.
getSizeInBits
(
)
==
32
&&
"Only 32 bit gprb is handled here.\n"
)
;
MRI
.
setRegBank
(
Op
.
getReg
(
)
,
getRegBank
(
Mips
::
GPRBRegBankID
)
)
;
}
}
}
return
;
}
case
TargetOpcode
::
G_UNMERGE_VALUES
:
{
SmallVector
<
MachineInstr
*
,
2
>
DeadInstrs
;
ArtCombiner
.
tryCombineMerges
(
MI
,
DeadInstrs
)
;
for
(
MachineInstr
*
DeadMI
:
DeadInstrs
)
DeadMI
->
eraseFromParent
(
)
;
return
;
}
default
:
break
;
}
return
applyDefaultMapping
(
OpdMapper
)
;
}
</s>


<s> static int ix86_compare_version_priority ( tree decl1 , tree decl2 ) { unsigned int priority1 = get_builtin_code_for_version ( decl1 , NULL ) ; unsigned int priority2 = get_builtin_code_for_version ( decl2 , NULL ) ; return ( int ) priority1 - ( int ) priority2 ; } </s>

This compares the priority of target features in function DECL1 and DECL2 . It returns positive value if DECL1 is higher priority , negative value if DECL2 is higher priority and 0 if they are the same .


<s> unsigned getNumberOfRegisters ( bool Vector ) const { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 32 ; return 0 ; } return 32 ; } </s>


"SystemZ does do not have assembler relaxation"

Relax the instruction in the given fragment to the next wider instruction .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


<s> const unsigned * MSP430RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { MSP430 :: FPW , MSP430 :: R5W , MSP430 :: R6W , MSP430 :: R7W , MSP430 :: R8W , MSP430 :: R9W , MSP430 :: R10W , MSP430 :: R11W , 0 } ; return CalleeSavedRegs ; } </s>


<s> unsigned PPCInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == PPC :: INLINEASM ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { return MI . getOperand ( 1 ) . getImm ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) { PatchPointOpers Opers ( & MI ) ; return Opers . getMetaOper ( PatchPointOpers :: NBytesPos ) . getImm ( ) ; } else { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> const TargetRegisterClass * OpenRISCRegisterInfo :: getPointerRegClass ( unsigned Kind ) const { assert ( 0 && "Unimplemented" ) ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> const char * WebAssemblyTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( static_cast < WebAssemblyISD :: NodeType > ( Opcode ) ) { case WebAssemblyISD :: FIRST_NUMBER : break ; case WebAssemblyISD :: NODE : \ return "WebAssemblyISD::" # NODE ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

WebAssembly WebAssembly WebAssemblyISD::NodeType WebAssemblyISD::FIRST_NUMBER WebAssemblyISD::NODE "WebAssemblyISD::"


<s> virtual unsigned int execute ( function * ) { func_fma_steering * fma_steering = new func_fma_steering ; fma_steering -> execute_fma_steering ( ) ; delete fma_steering ; return 0 ; } </s>


<s> static unsigned arm_size_return_regs ( void ) { machine_mode mode ; if ( crtl -> return_rtx != 0 ) mode = GET_MODE ( crtl -> return_rtx ) ; else mode = DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ; return GET_MODE_SIZE ( mode ) ; } </s>

Calculate the size of the return value that is passed in registers .


<s> bool RISCVGatherScatterLowering :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < RISCVTargetMachine > ( ) ; ST = & TM . getSubtarget < RISCVSubtarget > ( F ) ; if ( ! ST -> hasVInstructions ( ) || ! ST -> useRVVForFixedLengthVectors ( ) ) return false ; TLI = ST -> getTargetLowering ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; StridedAddrs . clear ( ) ; SmallVector < IntrinsicInst * , 4 > Gathers ; SmallVector < IntrinsicInst * , 4 > Scatters ; bool Changed = false ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { IntrinsicInst * II = dyn_cast < IntrinsicInst > ( & I ) ; if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_gather && isa < FixedVectorType > ( II -> getType ( ) ) ) { Gathers . push_back ( II ) ; } else if ( II && II -> getIntrinsicID ( ) == Intrinsic :: masked_scatter && isa < FixedVectorType > ( II -> getArgOperand ( 0 ) -> getType ( ) ) ) { Scatters . push_back ( II ) ; } } } for ( auto * II : Gathers ) Changed |= tryCreateStridedLoadStore ( II , II -> getType ( ) , II -> getArgOperand ( 0 ) , II -> getArgOperand ( 1 ) ) ; for ( auto * II : Scatters ) Changed |= tryCreateStridedLoadStore ( II , II -> getArgOperand ( 0 ) -> getType ( ) , II -> getArgOperand ( 1 ) , II -> getArgOperand ( 2 ) ) ; while ( ! MaybeDeadPHIs . empty ( ) ) { if ( auto * Phi = dyn_cast_or_null < PHINode > ( MaybeDeadPHIs . pop_back_val ( ) ) ) RecursivelyDeleteDeadPHINode ( Phi ) ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool ix86_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const machine_mode mode = type_natural_mode ( type , NULL , true ) ; HOST_WIDE_INT size ; if ( TARGET_64BIT ) { if ( ix86_function_type_abi ( fntype ) == MS_ABI ) { size = int_size_in_bytes ( type ) ; if ( ( ! type || VECTOR_INTEGER_TYPE_P ( type ) || INTEGRAL_TYPE_P ( type ) || VECTOR_FLOAT_TYPE_P ( type ) ) && ( SCALAR_INT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ) && ! COMPLEX_MODE_P ( mode ) && ( GET_MODE_SIZE ( mode ) == 16 || size == 16 ) ) return false ; return size != 1 && size != 2 && size != 4 && size != 8 ; } else { int needed_intregs , needed_sseregs ; return examine_argument ( mode , type , 1 , & needed_intregs , & needed_sseregs ) ; } } else { size = int_size_in_bytes ( type ) ; if ( TARGET_IAMCU ) return VECTOR_MODE_P ( mode ) || size < 0 || size > 8 ; if ( mode == BLKmode ) return true ; if ( MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P ( type ) && size <= 8 ) return false ; if ( VECTOR_MODE_P ( mode ) || mode == TImode ) { if ( size < 8 ) return false ; if ( size == 8 ) return TARGET_VECT8_RETURNS || ! TARGET_MMX ; if ( size == 16 ) return ! TARGET_SSE ; if ( size == 32 ) return ! TARGET_AVX ; if ( size == 64 ) return ! TARGET_AVX512F ; } if ( mode == XFmode ) return false ; if ( size > 12 ) return true ; gcc_assert ( mode != OImode ) ; return false ; } } </s>

Return false iff type is returned in memory .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"SI Whole Quad Mode"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static int arm_barrier_cost ( rtx insn ) { int base_cost = 50 ; rtx next = next_nonnote_insn ( insn ) ; if ( next != NULL && GET_CODE ( next ) == CODE_LABEL ) base_cost -= 20 ; switch ( GET_CODE ( insn ) ) { case CODE_LABEL : return 50 ; case INSN : case CALL_INSN : return base_cost ; case JUMP_INSN : return base_cost - 10 ; default : return base_cost + 10 ; } } </s>

Return the cost of forcibly inserting a barrier after INSN .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> void RISCVInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( NoAliases || ! printAliasInstr ( NewMI , STI , O ) ) printInstruction ( NewMI , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static int rs6000_use_sched_lookahead ( void ) { switch ( rs6000_cpu_attr ) { case CPU_PPC8540 : case CPU_PPC8548 : return 4 ; case CPU_CELL : return ( reload_completed ? 8 : 0 ) ; default : return 0 ; } } </s>

Return how many instructions to look ahead for better insn scheduling .


<s> static int find_gr_spill ( enum ia64_frame_regs r , int try_locals ) { int regno ; if ( emitted_frame_related_regs [ r ] != 0 ) { regno = emitted_frame_related_regs [ r ] ; if ( regno >= LOC_REG ( 0 ) && regno < LOC_REG ( 80 - frame_pointer_needed ) && current_frame_info . n_local_regs < regno - LOC_REG ( 0 ) + 1 ) current_frame_info . n_local_regs = regno - LOC_REG ( 0 ) + 1 ; else if ( crtl -> is_leaf && regno >= GR_REG ( 1 ) && regno <= GR_REG ( 31 ) ) current_frame_info . gr_used_mask |= 1 << regno ; return regno ; } if ( crtl -> is_leaf ) { for ( regno = GR_REG ( 1 ) ; regno <= GR_REG ( 31 ) ; regno ++ ) if ( ! df_regs_ever_live_p ( regno ) && call_used_regs [ regno ] && ! fixed_regs [ regno ] && ! global_regs [ regno ] && ( ( current_frame_info . gr_used_mask >> regno ) & 1 ) == 0 && ! is_emitted ( regno ) ) { current_frame_info . gr_used_mask |= 1 << regno ; return regno ; } } if ( try_locals ) { regno = current_frame_info . n_local_regs ; while ( regno < ( 80 - frame_pointer_needed ) ) if ( ! is_emitted ( LOC_REG ( regno ++ ) ) ) { current_frame_info . n_local_regs = regno ; return LOC_REG ( regno - 1 ) ; } } return 0 ; } </s>

Helper function for ia64_compute_frame_size : find an appropriate general register to spill some special register to . SPECIAL_SPILL_MASK contains bits in GR0 to GR31 that have already been allocated by this routine . TRY_LOCALS is true if we should attempt to locate a local regnum .


<s> void AArch64AsmPrinter :: emitStartOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( "@feat.00" ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> emitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> emitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = 0 ; if ( M . getModuleFlag ( "cfguard" ) ) { Feat00Flags |= 0x800 ; } if ( M . getModuleFlag ( "ehcontguard" ) ) { Feat00Flags |= 0x4000 ; } OutStreamer -> emitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer -> emitAssignment ( S , MCConstantExpr :: create ( Feat00Flags , MMI -> getContext ( ) ) ) ; } if ( ! TT . isOSBinFormatELF ( ) ) return ; unsigned Flags = 0 ; if ( const auto * BTE = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "branch-target-enforcement" ) ) ) if ( BTE -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_BTI ; if ( const auto * Sign = mdconst :: extract_or_null < ConstantInt > ( M . getModuleFlag ( "sign-return-address" ) ) ) if ( Sign -> getZExtValue ( ) ) Flags |= ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_PAC ; if ( Flags == 0 ) return ; if ( auto * TS = static_cast < AArch64TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) TS -> emitNoteSection ( Flags ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> SDNode * PTXDAGToDAGISel :: Select ( SDNode * Node ) { return SelectCode ( Node ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: TlsGd : return "MipsISD::TlsGd" ; case MipsISD :: TprelHi : return "MipsISD::TprelHi" ; case MipsISD :: TprelLo : return "MipsISD::TprelLo" ; case MipsISD :: ThreadPointer : return "MipsISD::ThreadPointer" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; case MipsISD :: CMovFP_T : return "MipsISD::CMovFP_T" ; case MipsISD :: CMovFP_F : return "MipsISD::CMovFP_F" ; case MipsISD :: FPRound : return "MipsISD::FPRound" ; case MipsISD :: MAdd : return "MipsISD::MAdd" ; case MipsISD :: MAddu : return "MipsISD::MAddu" ; case MipsISD :: MSub : return "MipsISD::MSub" ; case MipsISD :: MSubu : return "MipsISD::MSubu" ; case MipsISD :: DivRem : return "MipsISD::DivRem" ; case MipsISD :: DivRemU : return "MipsISD::DivRemU" ; case MipsISD :: BuildPairF64 : return "MipsISD::BuildPairF64" ; case MipsISD :: ExtractElementF64 : return "MipsISD::ExtractElementF64" ; case MipsISD :: WrapperPIC : return "MipsISD::WrapperPIC" ; case MipsISD :: DynAlloc : return "MipsISD::DynAlloc" ; case MipsISD :: Sync : return "MipsISD::Sync" ; case MipsISD :: Ext : return "MipsISD::Ext" ; case MipsISD :: Ins : return "MipsISD::Ins" ; default : return NULL ; } } </s>

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::TlsGd "MipsISD::TlsGd" MipsISD::TprelHi "MipsISD::TprelHi" MipsISD::TprelLo "MipsISD::TprelLo" MipsISD::ThreadPointer "MipsISD::ThreadPointer" MipsISD::Ret "MipsISD::Ret" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp" MipsISD::CMovFP_T "MipsISD::CMovFP_T" MipsISD::CMovFP_F "MipsISD::CMovFP_F" MipsISD::FPRound "MipsISD::FPRound" MipsISD::MAdd "MipsISD::MAdd" MipsISD::MAddu "MipsISD::MAddu" MipsISD::MSub "MipsISD::MSub" MipsISD::MSubu "MipsISD::MSubu" MipsISD::DivRem "MipsISD::DivRem" MipsISD::DivRemU "MipsISD::DivRemU" MipsISD::BuildPairF64 "MipsISD::BuildPairF64" MipsISD::ExtractElementF64 "MipsISD::ExtractElementF64" MipsISD::WrapperPIC "MipsISD::WrapperPIC" MipsISD::DynAlloc "MipsISD::DynAlloc" MipsISD::Sync "MipsISD::Sync" MipsISD::Ext "MipsISD::Ext" MipsISD::Ins "MipsISD::Ins"


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RI = TM . getRegisterInfo ( ) ; return ( DisableFramePointerElim ( MF ) || RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void sh_emit_scc_to_t ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx t_reg = get_t_reg_rtx ( ) ; enum rtx_code oldcode = code ; machine_mode mode ; switch ( code ) { case NE : gcc_unreachable ( ) ; case LT : code = GT ; break ; case LE : code = GE ; break ; case LTU : code = GTU ; break ; case LEU : code = GEU ; break ; default : break ; } if ( code != oldcode ) std :: swap ( op0 , op1 ) ; mode = GET_MODE ( op0 ) ; if ( mode == VOIDmode ) mode = GET_MODE ( op1 ) ; op0 = force_reg ( mode , op0 ) ; if ( ( code != EQ && code != NE && ( op1 != const0_rtx || code == GTU || code == GEU || code == LTU || code == LEU ) ) || ( mode == DImode && op1 != const0_rtx ) || ( TARGET_SH2E && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) ) op1 = force_reg ( mode , op1 ) ; sh_emit_set_t_insn ( gen_rtx_SET ( t_reg , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) , mode ) ; } </s>

Prepare the operands for an scc instruction ; make sure that the compare has been done and the result is in T_REG .


<s> void setupMF ( MachineFunction & MF , GISelKnownBits & KB , CodeGenCoverage & CoverageInfo ) override { InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ; ProduceNonFlagSettingCondBr = ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: SpeculativeLoadHardening ) ; MFReturnAddr = Register ( ) ; processPHIs ( MF ) ; } </s>


<s>
void
NVPTXTargetStreamer
::
changeSection
(
const
MCSection
*
CurSection
,
MCSection
*
Section
,
const
MCExpr
*
SubSection
,
raw_ostream
&
OS
)
{
assert
(
!
SubSection
&&
"SubSection is not null!"
)
;
const
MCObjectFileInfo
*
FI
=
getStreamer
(
)
.
getContext
(
)
.
getObjectFileInfo
(
)
;
if
(
isDwarfSection
(
FI
,
CurSection
)
)
OS
<<
"//\t}\n"
;
if
(
isDwarfSection
(
FI
,
Section
)
)
{
outputDwarfFileDirectives
(
)
;
OS
<<
"//\t.section"
;
Section
->
PrintSwitchToSection
(
*
getStreamer
(
)
.
getContext
(
)
.
getAsmInfo
(
)
,
FI
->
getTargetTriple
(
)
,
OS
,
SubSection
)
;
OS
<<
"//\t{\n"
;
}
}
</s>

Update streamer for a new active section .

NVPTX
NVPTX
"SubSection is not null!"
"//\t}\n"
"//\t.section"
"//\t{\n"


<s> SDValue MandarinTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; AnalyzeReturnValues ( CCInfo , RVLocs , Ins ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> static tree cygwin_d_handle_target_object_format ( void ) { const char * objfmt = "coff" ; return build_string_literal ( strlen ( objfmt ) + 1 , objfmt ) ; } </s>

Handle a call to ` __traits ( getTargetInfo , `` objectFormat '' ) ' .


<s> void arm_encode_call_attribute ( tree decl , int flag ) { const char * str = XSTR ( XEXP ( DECL_RTL ( decl ) , 0 ) , 0 ) ; int len = strlen ( str ) ; char * newstr ; if ( DECL_WEAK ( decl ) && flag == SHORT_CALL_FLAG_CHAR ) return ; newstr = alloca ( len + 2 ) ; newstr [ 0 ] = flag ; strcpy ( newstr + 1 , str ) ; newstr = ( char * ) ggc_alloc_string ( newstr , len + 1 ) ; XSTR ( XEXP ( DECL_RTL ( decl ) , 0 ) , 0 ) = newstr ; } </s>

Encode long_call or short_call attribute by prefixing symbol name in DECL with a special character FLAG .


<s>
static
void
cris_asm_output_mi_thunk
(
FILE
*
stream
,
tree
thunkdecl
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
ATTRIBUTE_UNUSED
,
tree
funcdecl
)
{
if
(
delta
>
0
)
fprintf
(
stream
,
"\tadd%s "
HOST_WIDE_INT_PRINT_DEC
",$%s\n"
,
ADDITIVE_SIZE_MODIFIER
(
delta
)
,
delta
,
reg_names
[
CRIS_FIRST_ARG_REG
]
)
;
else
if
(
delta
<
0
)
fprintf
(
stream
,
"\tsub%s "
HOST_WIDE_INT_PRINT_DEC
",$%s\n"
,
ADDITIVE_SIZE_MODIFIER
(
delta
)
,
delta
,
reg_names
[
CRIS_FIRST_ARG_REG
]
)
;
if
(
flag_pic
)
{
const
char
*
name
=
XSTR
(
XEXP
(
DECL_RTL
(
funcdecl
)
,
0
)
,
0
)
;
name
=
(
*
targetm
.
strip_name_encoding
)
(
name
)
;
fprintf
(
stream
,
"add.d "
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"%s,$pc\n"
,
CRIS_PLT_PCOFFSET_SUFFIX
)
;
}
else
{
fprintf
(
stream
,
"jump "
)
;
assemble_name
(
stream
,
XSTR
(
XEXP
(
DECL_RTL
(
funcdecl
)
,
0
)
,
0
)
)
;
fprintf
(
stream
,
"\n"
)
;
}
}
</s>


<s> unsigned AArch64AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { AArch64Operand & Op = static_cast < AArch64Operand & > ( AsmOp ) ; int64_t ExpectedVal ; switch ( Kind ) { default : return Match_InvalidOperand ; case MCK__35_0 : ExpectedVal = 0 ; break ; case MCK__35_1 : ExpectedVal = 1 ; break ; case MCK__35_12 : ExpectedVal = 12 ; break ; case MCK__35_16 : ExpectedVal = 16 ; break ; case MCK__35_2 : ExpectedVal = 2 ; break ; case MCK__35_24 : ExpectedVal = 24 ; break ; case MCK__35_3 : ExpectedVal = 3 ; break ; case MCK__35_32 : ExpectedVal = 32 ; break ; case MCK__35_4 : ExpectedVal = 4 ; break ; case MCK__35_48 : ExpectedVal = 48 ; break ; case MCK__35_6 : ExpectedVal = 6 ; break ; case MCK__35_64 : ExpectedVal = 64 ; break ; case MCK__35_8 : ExpectedVal = 8 ; break ; } if ( ! Op . isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; machine_mode reg_mode = Pmode ; int reg_size = TARGET_32BIT ? 4 : 8 ; machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode ; int fp_reg_size = 8 ; int offset = info -> fp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_fp_reg_save ; i < 64 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( fp_reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += fp_reg_size ; } offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( reg_mode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , 0 ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( reg_mode , 0 ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; } } </s>


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static bool pa_legitimate_constant_p ( machine_mode mode , rtx x ) { if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && x != CONST0_RTX ( mode ) ) return false ; if ( ! NEW_HP_ASSEMBLER && ! TARGET_GAS && GET_CODE ( x ) == LABEL_REF ) return false ; if ( tls_referenced_p ( x ) ) return false ; if ( TARGET_64BIT && GET_CODE ( x ) == CONST_DOUBLE ) return false ; if ( TARGET_64BIT && HOST_BITS_PER_WIDE_INT > 32 && GET_CODE ( x ) == CONST_INT && ! reload_in_progress && ! reload_completed && ! LEGITIMATE_64BIT_CONST_INT_P ( INTVAL ( x ) ) && ! pa_cint_ok_for_move ( UINTVAL ( x ) ) ) return false ; if ( function_label_operand ( x , mode ) ) return false ; return true ; } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . In 64-bit mode , we reject CONST_DOUBLES . We also reject CONST_INTS that need more than three instructions to load prior to reload . This limit is somewhat arbitrary . It takes three instructions to load a CONST_INT from memory but two are memory accesses . It may be better to increase the allowed range for CONST_INTS . We may also be able to handle CONST_DOUBLES .


<s>
const
char
*
output_return
(
rtx_insn
*
insn
)
{
if
(
crtl
->
calls_eh_return
)
{
gcc_assert
(
!
final_sequence
)
;
if
(
flag_delayed_branch
)
{
if
(
!
TARGET_FLAT
&&
TARGET_V9
)
fputs
(
"\treturn\t%i7+8\n"
,
asm_out_file
)
;
else
{
if
(
!
TARGET_FLAT
)
fputs
(
"\trestore\n"
,
asm_out_file
)
;
fputs
(
"\tjmp\t%o7+8\n"
,
asm_out_file
)
;
}
fputs
(
"\t add\t%sp, %g1, %sp\n"
,
asm_out_file
)
;
}
else
{
if
(
!
TARGET_FLAT
)
fputs
(
"\trestore\n"
,
asm_out_file
)
;
fputs
(
"\tadd\t%sp, %g1, %sp\n"
,
asm_out_file
)
;
fputs
(
"\tjmp\t%o7+8\n\t nop\n"
,
asm_out_file
)
;
}
}
else
if
(
sparc_leaf_function_p
||
TARGET_FLAT
)
{
return
"jmp\t%%o7+%)%#"
;
}
else
{
if
(
final_sequence
)
{
rtx_insn
*
delay
;
rtx
pat
;
delay
=
NEXT_INSN
(
insn
)
;
gcc_assert
(
delay
)
;
pat
=
PATTERN
(
delay
)
;
if
(
TARGET_V9
&&
!
epilogue_renumber
(
&
pat
,
1
)
)
{
epilogue_renumber
(
&
pat
,
0
)
;
return
"return\t%%i7+%)%#"
;
}
else
{
output_asm_insn
(
"jmp\t%%i7+%)"
,
)
;
PATTERN
(
delay
)
=
gen_blockage
(
)
;
INSN_CODE
(
delay
)
=
1
;
final_scan_insn
(
delay
,
asm_out_file
,
optimize
,
0
,
)
;
INSN_LOCATION
(
delay
)
=
UNKNOWN_LOCATION
;
output_restore
(
pat
)
;
}
}
else
{
if
(
TARGET_V9
)
return
"return\t%%i7+%)\n\t nop"
;
else
if
(
flag_delayed_branch
)
return
"jmp\t%%i7+%)\n\t restore"
;
else
return
"restore\n\tjmp\t%%o7+%)\n\t nop"
;
}
}
return
""
;
}
</s>


<s> void R600InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( AMDGPU :: R600_Reg128RegClass . contains ( DestReg ) && AMDGPU :: R600_Reg128RegClass . contains ( SrcReg ) ) { for ( unsigned I = 0 ; I < 4 ; I ++ ) { unsigned SubRegIndex = RI . getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { assert ( ! AMDGPU :: R600_Reg128RegClass . contains ( DestReg ) && ! AMDGPU :: R600_Reg128RegClass . contains ( SrcReg ) ) ; MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , DestReg , SrcReg ) ; NewMI -> getOperand ( getOperandIdx ( * NewMI , R600Operands :: SRC0 ) ) . setIsKill ( KillSrc ) ; } } </s>


<s> void SparcTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { KnownBits Known2 ; Known . resetAll ( ) ; switch ( Op . getOpcode ( ) ) { default : break ; case SPISD :: SELECT_ICC : case SPISD :: SELECT_XCC : case SPISD :: SELECT_FCC : DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known , Depth + 1 ) ; DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known2 , Depth + 1 ) ; Known . One &= Known2 . One ; Known . Zero &= Known2 . Zero ; break ; } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> static int sequent_regs_live ( void ) { int live_seq = 0 ; int cur_seq = 0 ; for ( int reg = 0 ; reg <= LAST_CALLEE_SAVED_REG ; ++ reg ) { if ( fixed_regs [ reg ] ) { if ( live_seq != 0 ) return 0 ; else continue ; } if ( ! call_used_regs [ reg ] ) { if ( df_regs_ever_live_p ( reg ) ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; } } if ( ! frame_pointer_needed ) { if ( df_regs_ever_live_p ( REG_Y ) ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; if ( df_regs_ever_live_p ( REG_Y + 1 ) ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = 0 ; } else { cur_seq += 2 ; live_seq += 2 ; } return ( cur_seq == live_seq ) ? live_seq : 0 ; } </s>

This function checks sequence of live registers


<s> bool M68kCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; const M68kTargetLowering & TLI = * getTLI < M68kTargetLowering > ( ) ; const M68kSubtarget & STI = MF . getSubtarget < M68kSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const M68kRegisterInfo * TRI = STI . getRegisterInfo ( ) ; SmallVector < ArgInfo , 8 > OutArgs ; for ( auto & OrigArg : Info . OrigArgs ) splitToValueTypes ( OrigArg , OutArgs , DL , Info . CallConv ) ; SmallVector < ArgInfo , 8 > InArgs ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) splitToValueTypes ( Info . OrigRet , InArgs , DL , Info . CallConv ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; auto CallSeqStart = MIRBuilder . buildInstr ( AdjStackDown ) ; unsigned Opc = TLI . getTargetMachine ( ) . isPositionIndependent ( ) ? M68k :: CALLq : Info . Callee . isReg ( ) ? M68k :: CALLj : M68k :: CALLb ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) . add ( Info . Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; CCAssignFn * AssignFn = TLI . getCCAssignFn ( Info . CallConv , false , Info . IsVarArg ) ; OutgoingValueAssigner Assigner ( AssignFn ) ; M68kOutgoingArgHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , OutArgs , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; if ( Info . Callee . isReg ( ) ) constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , 0 ) ; MIRBuilder . insertInstr ( MIB ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { CCAssignFn * RetAssignFn = TLI . getCCAssignFn ( Info . CallConv , true , Info . IsVarArg ) ; OutgoingValueAssigner Assigner ( RetAssignFn , RetAssignFn ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , InArgs , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; } CallSeqStart . addImm ( Assigner . StackOffset ) . addImm ( 0 ) ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; MIRBuilder . buildInstr ( AdjStackUp ) . addImm ( Assigner . StackOffset ) . addImm ( 0 ) ; return true ; } </s>

This hook must be implemented to lower the given call instruction , including argument and return value marshalling .


<s> bool AArch64FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ! ( hasFP ( MF ) && MFI -> hasVarSizedObjects ( ) ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> SDValue PPCTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { if ( PPCSubTarget . isSVR4ABI ( ) ) { if ( PPCSubTarget . isPPC64 ( ) ) return LowerFormalArguments_64SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; else return LowerFormalArguments_32SVR4 ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } else { return LowerFormalArguments_Darwin ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; } } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> BitVector ARMBaseRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const TargetFrameLowering * TFI = STI . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM :: SP ) ; Reserved . set ( ARM :: PC ) ; Reserved . set ( ARM :: FPSCR ) ; Reserved . set ( ARM :: APSR_NZCV ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( ARM :: R9 ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { assert ( ARM :: D31 == ARM :: D16 + 15 ) ; for ( unsigned i = 0 ; i != 16 ; ++ i ) Reserved . set ( ARM :: D16 + i ) ; } const TargetRegisterClass * RC = & ARM :: GPRPairRegClass ; for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) for ( MCSubRegIterator SI ( * I , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) Reserved . set ( * I ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool GCNPassConfig :: addRegBankSelect ( ) { return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> bool MOSPostRAScavenging :: runOnMachineFunction ( MachineFunction & MF ) { const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: NoVRegs ) ) return false ; for ( MachineBasicBlock & MBB : MF ) for ( MachineInstr & MI : MBB ) if ( MI . definesRegister ( MOS :: NZ ) ) { auto Succ = ++ MachineBasicBlock :: iterator ( MI ) ; if ( Succ != MBB . end ( ) && Succ -> readsRegister ( MOS :: NZ , & TRI ) ) { MI . bundleWithSucc ( ) ; for ( MachineOperand & MO : Succ -> operands ( ) ) if ( MO . isReg ( ) && ( MO . getReg ( ) == MOS :: N || MO . getReg ( ) == MOS :: Z ) ) MO . setIsInternalRead ( ) ; } } RegScavenger RS ; scavengeFrameVirtualRegs ( MF , RS ) ; for ( MachineBasicBlock & MBB : MF ) for ( MachineInstr & MI : MBB . instrs ( ) ) if ( MI . isBundledWithPred ( ) ) { MI . unbundleFromPred ( ) ; for ( MachineOperand & MO : MI . operands ( ) ) if ( MO . isReg ( ) && MO . isInternalRead ( ) ) MO . setIsInternalRead ( false ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> rtx pru_get_return_address ( int count ) { if ( count != 0 ) return NULL_RTX ; return get_hard_reg_initial_val ( HImode , RA_REGNUM ) ; } </s>

Implement RETURN_ADDR_RTX . Note , we do not support moving back to a previous frame .


<s> void rs6000_xcoff_declare_object_name ( FILE * file , const char * name , tree decl ) { struct declare_alias_data data = { file , false } ; ASM_OUTPUT_LABEL ( file , name ) ; symtab_node :: get_create ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; } </s>

This macro produces the initial definition of a object ( variable ) name . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s>
void
fma_root_node
::
dump_info
(
fma_forest
*
forest
)
{
gcc_assert
(
dump_file
)
;
if
(
this
==
forest
->
get_roots
(
)
->
front
(
)
)
fprintf
(
dump_file
,
"Instruction(s) at root of forest #%d:"
,
forest
->
get_id
(
)
)
;
fprintf
(
dump_file
,
" %d"
,
INSN_UID
(
this
->
m_insn
)
)
;
if
(
this
==
forest
->
get_roots
(
)
->
back
(
)
)
fprintf
(
dump_file
,
"\n"
)
;
}
</s>

Dump information about the roots of forest FOREST .

aarch64
"Instruction(s) at root of forest #%d:"
" %d"
"\n"


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: TSTBIT : return "HexagonISD::TSTBIT" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VASL : return "HexagonISD::VASL" ; case HexagonISD :: VASR : return "HexagonISD::VASR" ; case HexagonISD :: VLSR : return "HexagonISD::VLSR" ; case HexagonISD :: VSPLAT : return "HexagonISD::VSPLAT" ; case HexagonISD :: VEXTRACTW : return "HexagonISD::VEXTRACTW" ; case HexagonISD :: VINSERTW0 : return "HexagonISD::VINSERTW0" ; case HexagonISD :: VROR : return "HexagonISD::VROR" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: VZERO : return "HexagonISD::VZERO" ; case HexagonISD :: D2P : return "HexagonISD::D2P" ; case HexagonISD :: P2D : return "HexagonISD::P2D" ; case HexagonISD :: V2Q : return "HexagonISD::V2Q" ; case HexagonISD :: Q2V : return "HexagonISD::Q2V" ; case HexagonISD :: QCAT : return "HexagonISD::QCAT" ; case HexagonISD :: QTRUE : return "HexagonISD::QTRUE" ; case HexagonISD :: QFALSE : return "HexagonISD::QFALSE" ; case HexagonISD :: TYPECAST : return "HexagonISD::TYPECAST" ; case HexagonISD :: VALIGNADDR : return "HexagonISD::VALIGNADDR" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::TSTBIT "HexagonISD::TSTBIT" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::JT "HexagonISD::JT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VASL "HexagonISD::VASL" HexagonISD::VASR "HexagonISD::VASR" HexagonISD::VLSR "HexagonISD::VLSR" HexagonISD::VSPLAT "HexagonISD::VSPLAT" HexagonISD::VEXTRACTW "HexagonISD::VEXTRACTW" HexagonISD::VINSERTW0 "HexagonISD::VINSERTW0" HexagonISD::VROR "HexagonISD::VROR" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::VZERO "HexagonISD::VZERO" HexagonISD::D2P "HexagonISD::D2P" HexagonISD::P2D "HexagonISD::P2D" HexagonISD::V2Q "HexagonISD::V2Q" HexagonISD::Q2V "HexagonISD::Q2V" HexagonISD::QCAT "HexagonISD::QCAT" HexagonISD::QTRUE "HexagonISD::QTRUE" HexagonISD::QFALSE "HexagonISD::QFALSE" HexagonISD::TYPECAST "HexagonISD::TYPECAST" HexagonISD::VALIGNADDR "HexagonISD::VALIGNADDR" HexagonISD::OP_END


<s> static int tilegx_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { if ( CALL_P ( insn ) && REG_NOTE_KIND ( link ) == REG_DEP_TRUE ) { rtx target = get_jump_target ( insn ) ; if ( ! REG_P ( target ) || ! set_of ( target , dep_insn ) ) return 0 ; } return cost ; } </s>


<s> bool nds32_long_call_p ( rtx symbol ) { if ( nds32_indirect_call_referenced_p ( symbol ) ) return TARGET_ICT_MODEL_LARGE ; else return TARGET_CMODEL_LARGE ; } </s>


<s> bool PTXDAGToDAGISel :: isImm ( const SDValue & operand ) { return ConstantSDNode :: classof ( operand . getNode ( ) ) ; } </s>


<s> void XCoreInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugValue ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: LDWFI ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
SDValue
XCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
return
ExpandADDSUB
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

XCore
XCore
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::ConstantPool
ISD::JumpTable
ISD::LOAD
ISD::STORE
ISD::SELECT_CC
ISD::VAARG
ISD::VASTART
ISD::ADD
ISD::SUB
ISD::FRAMEADDR
"unimplemented operand"


<s> void PPCPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { initializePPCVSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & PPCVSXFMAMutateID ) ; } if ( getPPCTargetMachine ( ) . isPositionIndependent ( ) ) { addPass ( & LiveVariablesID , false ) ; addPass ( createPPCTLSDynamicCallPass ( ) ) ; } if ( EnableExtraTOCRegDeps ) addPass ( createPPCTOCRegDepsPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & MachinePipelinerID ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> bool MipsRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MipsSubtarget & Subtarget = MF . getSubtarget < MipsSubtarget > ( ) ; unsigned FP = Subtarget . isGP32bit ( ) ? Mips :: FP : Mips :: FP_64 ; unsigned BP = Subtarget . isGP32bit ( ) ? Mips :: S7 : Mips :: S7_64 ; if ( Subtarget . inMips16Mode ( ) ) return false ; if ( ! MF . getRegInfo ( ) . canReserveReg ( FP ) ) return false ; if ( Subtarget . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MF . getRegInfo ( ) . canReserveReg ( BP ) ; } </s>

True if the stack can be realigned for the target .

Mips Mips Mips Mips Mips::FP Mips::FP_64 Mips::S7 Mips::S7_64 Mips


<s> rtx legitimize_reload_address ( rtx ad , machine_mode mode ATTRIBUTE_UNUSED , int opnum , int type ) { if ( ! optimize || TARGET_LONG_DISPLACEMENT ) return NULL_RTX ; if ( GET_CODE ( ad ) == PLUS ) { rtx tem = simplify_binary_operation ( PLUS , Pmode , XEXP ( ad , 0 ) , XEXP ( ad , 1 ) ) ; if ( tem ) ad = tem ; } if ( GET_CODE ( ad ) == PLUS && GET_CODE ( XEXP ( ad , 0 ) ) == REG && GET_CODE ( XEXP ( ad , 1 ) ) == CONST_INT && ! DISP_IN_RANGE ( INTVAL ( XEXP ( ad , 1 ) ) ) ) { HOST_WIDE_INT lower = INTVAL ( XEXP ( ad , 1 ) ) & 0xfff ; HOST_WIDE_INT upper = INTVAL ( XEXP ( ad , 1 ) ) ^ lower ; rtx cst , tem , new_rtx ; cst = GEN_INT ( upper ) ; if ( ! legitimate_reload_constant_p ( cst ) ) cst = force_const_mem ( Pmode , cst ) ; tem = gen_rtx_PLUS ( Pmode , XEXP ( ad , 0 ) , cst ) ; new_rtx = gen_rtx_PLUS ( Pmode , tem , GEN_INT ( lower ) ) ; push_reload ( XEXP ( tem , 1 ) , 0 , & XEXP ( tem , 1 ) , 0 , BASE_REG_CLASS , Pmode , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; return new_rtx ; } return NULL_RTX ; } </s>

Try a machine-dependent way of reloading an illegitimate address AD operand . If we find one , push the reload and and return the new address . MODE is the mode of the enclosing MEM . OPNUM is the operand number and TYPE is the reload type of the current reload .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
if
(
Subtarget
.
hasVector
(
)
)
VerifyVectorTypes
(
Outs
)
;
SmallVector
<
CCValAssign
,
16
>
RetLocs
;
CCState
RetCCInfo
(
CallConv
,
IsVarArg
,
MF
,
RetLocs
,
*
DAG
.
getContext
(
)
)
;
RetCCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
RetLocs
.
empty
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
Chain
)
;
SDValue
Glue
;
SmallVector
<
SDValue
,
4
>
RetOps
;
RetOps
.
push_back
(
Chain
)
;
for
(
unsigned
I
=
0
,
E
=
RetLocs
.
size
(
)
;
I
!=
E
;
++
I
)
{
CCValAssign
&
VA
=
RetLocs
[
I
]
;
SDValue
RetValue
=
OutVals
[
I
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
RetValue
=
convertValVTToLocVT
(
DAG
,
DL
,
VA
,
RetValue
)
;
unsigned
Reg
=
VA
.
getLocReg
(
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
Reg
,
RetValue
,
Glue
)
;
Glue
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
Reg
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Glue
.
getNode
(
)
)
RetOps
.
push_back
(
Glue
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> bool SITargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & , EVT ) const { return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static void vr4130_avoid_branch_rt_conflict ( rtx_insn * insn ) { rtx_insn * first , * second ; first = SEQ_BEGIN ( insn ) ; second = SEQ_END ( insn ) ; if ( JUMP_P ( first ) && NONJUMP_INSN_P ( second ) && GET_CODE ( PATTERN ( first ) ) == SET && GET_CODE ( SET_DEST ( PATTERN ( first ) ) ) == PC && GET_CODE ( SET_SRC ( PATTERN ( first ) ) ) == IF_THEN_ELSE ) { rtx cond = XEXP ( SET_SRC ( PATTERN ( first ) ) , 0 ) ; if ( ( GET_CODE ( cond ) == EQ || GET_CODE ( cond ) == NE ) && REG_P ( XEXP ( cond , 0 ) ) && REG_P ( XEXP ( cond , 1 ) ) && reg_referenced_p ( XEXP ( cond , 1 ) , PATTERN ( second ) ) && ! reg_referenced_p ( XEXP ( cond , 0 ) , PATTERN ( second ) ) ) { rtx tmp = XEXP ( cond , 0 ) ; XEXP ( cond , 0 ) = XEXP ( cond , 1 ) ; XEXP ( cond , 1 ) = tmp ; } } } </s>

The VR4130 pipeline issues aligned pairs of instructions together , but it stalls the second instruction if it depends on the first . In order to cut down the amount of logic required , this dependence check is not based on a full instruction decode . Instead , any non-SPECIAL instruction is assumed to modify the register specified by bits 20-16 ( which is usually the `` rt '' field ) . In beq , beql , bne and bnel instructions , the rt field is actually an input , so we can end up with a false dependence between the branch and its delay slot . If this situation occurs in instruction INSN , try to avoid it by swapping rs and rt .


<s> void print_address_operand ( FILE * file , rtx x ) { switch ( GET_CODE ( x ) ) { case PLUS : output_address ( VOIDmode , XEXP ( x , 0 ) ) ; fprintf ( file , "+" ) ; output_address ( VOIDmode , XEXP ( x , 1 ) ) ; break ; case PRE_DEC : fprintf ( file , "--" ) ; output_address ( VOIDmode , XEXP ( x , 0 ) ) ; break ; case POST_INC : output_address ( VOIDmode , XEXP ( x , 0 ) ) ; fprintf ( file , "++" ) ; break ; case POST_DEC : output_address ( VOIDmode , XEXP ( x , 0 ) ) ; fprintf ( file , "--" ) ; break ; default : gcc_assert ( GET_CODE ( x ) != MEM ) ; print_operand ( file , x , 0 ) ; break ; } } </s>

Subroutine of print_operand ; used to print a memory reference X to FILE .


"if conversion tried to stop defining used CPSR"

Convert the instruction into a predicated instruction .


<s> int arm_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( TARGET_32BIT ) { if ( ( IS_VFP_CLASS ( from ) && ! IS_VFP_CLASS ( to ) ) || ( ! IS_VFP_CLASS ( from ) && IS_VFP_CLASS ( to ) ) ) return 15 ; else if ( ( from == IWMMXT_REGS && to != IWMMXT_REGS ) || ( from != IWMMXT_REGS && to == IWMMXT_REGS ) ) return 4 ; else if ( from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS ) return 20 ; else return 2 ; } else { if ( from == HI_REGS || to == HI_REGS ) return 4 ; else return 2 ; } } </s>

Implement TARGET_REGISTER_MOVE_COST . Moves between VFP_REGS and GENERAL_REGS are a single insn , but it is typically more expensive than a single memory access . We set the cost to less than two memory accesses so that floating point to integer conversion does not go through memory .


<s>
static
void
rs6000_darwin_file_start
(
void
)
{
static
const
struct
{
const
char
*
arg
;
const
char
*
name
;
HOST_WIDE_INT
if_set
;
}
mapping
[
]
=
{
{
"ppc64"
,
"ppc64"
,
MASK_64BIT
}
,
{
"970"
,
"ppc970"
,
MASK_PPC_GPOPT
|
MASK_MFCRF
|
MASK_POWERPC64
}
,
{
"power4"
,
"ppc970"
,
0
}
,
{
"G5"
,
"ppc970"
,
0
}
,
{
"7450"
,
"ppc7450"
,
0
}
,
{
"7400"
,
"ppc7400"
,
MASK_ALTIVEC
}
,
{
"G4"
,
"ppc7400"
,
0
}
,
{
"750"
,
"ppc750"
,
0
}
,
{
"740"
,
"ppc750"
,
0
}
,
{
"G3"
,
"ppc750"
,
0
}
,
{
"604e"
,
"ppc604e"
,
0
}
,
{
"604"
,
"ppc604"
,
0
}
,
{
"603e"
,
"ppc603"
,
0
}
,
{
"603"
,
"ppc603"
,
0
}
,
{
"601"
,
"ppc601"
,
0
}
,
{
,
"ppc"
,
0
}
}
;
const
char
*
cpu_id
=
""
;
size_t
i
;
rs6000_file_start
(
)
;
darwin_file_start
(
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
cpu_id
=
rs6000_default_cpu
;
if
(
OPTION_SET_P
(
rs6000_cpu_index
)
)
cpu_id
=
processor_target_table
[
rs6000_cpu_index
]
.
name
;
i
=
0
;
while
(
mapping
[
i
]
.
arg
!=
&&
strcmp
(
mapping
[
i
]
.
arg
,
cpu_id
)
!=
0
&&
(
mapping
[
i
]
.
if_set
&
rs6000_isa_flags
)
==
0
)
i
++
;
fprintf
(
asm_out_file
,
"\t.machine %s\n"
,
mapping
[
i
]
.
name
)
;
}
</s>

Output a .machine directive for the Darwin assembler , and call the generic start_file routine .