<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , unsigned StackAlignOverride , unsigned PreferVectorWidthOverride ) : X86GenSubtargetInfo ( TT , CPU , FS ) , X86ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , PreferVectorWidthOverride ( PreferVectorWidthOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void i386_pe_seh_unwind_emit ( FILE * asm_out_file , rtx_insn * insn ) { rtx note , pat ; bool handled_one = false ; struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; seh = cfun -> machine -> seh ; if ( seh == NULL ) return ; if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , 1 ) ) { switch ( REG_NOTE_KIND ( note ) ) { case REG_FRAME_RELATED_EXPR : pat = XEXP ( note , 0 ) ; goto found ; case REG_CFA_DEF_CFA : case REG_CFA_EXPRESSION : gcc_unreachable ( ) ; break ; case REG_CFA_REGISTER : gcc_unreachable ( ) ; case REG_CFA_ADJUST_CFA : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) { pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , 0 , 0 ) ; } seh_cfa_adjust_cfa ( asm_out_file , seh , pat ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , 0 ) ; if ( pat == NULL ) pat = single_set ( insn ) ; seh_cfa_offset ( asm_out_file , seh , pat ) ; handled_one = true ; break ; default : break ; } } if ( handled_one ) return ; pat = PATTERN ( insn ) ; found : seh_frame_related_expr ( asm_out_file , seh , pat ) ; } </s>

This function looks at a single insn and emits any SEH directives required for unwind of this insn .


<s> bool isImm ( ) const { return Kind == CV_Immediate ; } </s>


<s> int z8k_address_cost ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { if ( GET_CODE ( op ) == PLUS ) { rtx lhs = XEXP ( op , 0 ) ; rtx rhs = XEXP ( op , 1 ) ; if ( GET_CODE ( lhs ) == REG && GET_CODE ( rhs ) == CONST_INT ) return 10 ; if ( GET_CODE ( lhs ) == MEM ) return 40 ; } return 1 ; } </s>

For z8k , it is better to use a complex address than let gcc copy the address into a reg and make a new pseudo . But not if the address requires to two regs - that would mean more pseudos with longer lifetimes .


<s> void BTFTypeFunc :: emitType ( MCStreamer & OS ) { BTFTypeBase :: emitType ( OS ) ; } </s>


<s> static void vr4130_reorder ( rtx_insn * * ready , int nready ) { if ( vr4130_swap_insns_p ( ready [ nready - 1 ] , ready [ nready - 2 ] ) ) mips_promote_ready ( ready , nready - 2 , nready - 1 ) ; } </s>

A TUNE_MIPS4130 helper function . ( READY , NREADY ) describes a ready queue with at least two instructions . Swap the first two if vr4130_swap_insns_p says that it could be worthwhile .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> bool needAddressOf ( ) const { return AddressOf ; } </s>

needAddressOf - Do we need to emit code to get the address of the variable/label ? Only valid when parsing MS-style inline assembly .


<s> static bool const_load_sequence_p ( swap_web_entry * insn_entry , rtx insn ) { unsigned uid = INSN_UID ( insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load ) return false ; const_rtx tocrel_base ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || ! ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) || ! MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , 0 ) ; rtx base_reg = XEXP ( mem , 0 ) ; if ( ! REG_P ( base_reg ) ) return false ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ; FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ; if ( MEM_P ( tocrel_expr ) ) tocrel_expr = XEXP ( tocrel_expr , 0 ) ; if ( ! toc_relative_expr_p ( tocrel_expr , false , & tocrel_base , NULL ) ) return false ; split_const ( XVECEXP ( tocrel_base , 0 , 0 ) , & base , & offset ) ; if ( ! SYMBOL_REF_P ( base ) || ! CONSTANT_POOL_ADDRESS_P ( base ) ) return false ; else { rtx const_vector = get_pool_constant ( base ) ; if ( SYMBOL_REF_P ( const_vector ) && CONSTANT_POOL_ADDRESS_P ( const_vector ) ) const_vector = get_pool_constant ( const_vector ) ; if ( GET_CODE ( const_vector ) != CONST_VECTOR ) return false ; } } } return true ; } </s>

Return TRUE if insn is a swap fed by a load from the constant pool .


<s> bool sh_dynamicalize_shift_p ( rtx count ) { gcc_assert ( CONST_INT_P ( count ) ) ; const int shift_amount_i = INTVAL ( count ) & 31 ; int insn_count ; if ( shift_amount_i == 31 ) insn_count = 2 ; else insn_count = ashl_lshr_seq [ shift_amount_i ] . insn_count ; return TARGET_DYNSHIFT && ( insn_count > 1 + SH_DYNAMIC_SHIFT_COST ) ; } </s>

Return true if it is potentially beneficial to use a dynamic shift instruction ( shad / shar ) instead of a combination of 1/2/8/16 shift instructions for the specified shift count . If dynamic shifts are not available , always return false .


<s> static bool vector_config_insn_p ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= 0 && get_attr_type ( rinsn ) == TYPE_VSETVL ; } </s>

Return true if it is a vsetvl instruction .


<s> unsigned getBaseReg ( ) const { return BaseReg ; } </s>

Get the base register of the pointer value .


<s> static rtx frv_expand_mclracc_builtin ( tree arglist ) { enum insn_code icode = CODE_FOR_mclracc ; rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ; op0 = frv_int_to_acc ( icode , 0 , op0 ) ; if ( ! op0 ) return NULL_RTX ; pat = GEN_FCN ( icode ) ( op0 ) ; if ( pat ) emit_insn ( pat ) ; return NULL_RTX ; } </s>

Expand the MCLRACC builtin . This builtin takes a single accumulator number as argument .


<s> bool WebAssemblyTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ; return ( CallerBits & CalleeBits ) == CalleeBits ; } </s>

Determine whether a callee with the given TLI can be inlined into caller with this TLI , based on 'nobuiltin ' attributes .


<s> void X86AsmInstrumentation :: EmitInstruction ( MCStreamer & Out , const MCInst & Inst , bool PrintSchedInfoEnabled ) { Out . EmitInstruction ( Inst , * STI , PrintSchedInfoEnabled ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
DecodeStatus
AArch64Disassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes
,
uint64_t
Address
,
raw_ostream
&
CS
)
const
{
CommentStream
=
&
CS
;
Size
=
0
;
if
(
Bytes
.
size
(
)
<
4
)
return
Fail
;
Size
=
4
;
uint32_t
Insn
=
(
Bytes
[
3
]
<<
24
)
|
(
Bytes
[
2
]
<<
16
)
|
(
Bytes
[
1
]
<<
8
)
|
(
Bytes
[
0
]
<<
0
)
;
const
uint8_t
*
Tables
[
]
=
{
DecoderTable32
,
DecoderTableFallback32
}
;
for
(
auto
Table
:
Tables
)
{
DecodeStatus
Result
=
decodeInstruction
(
Table
,
MI
,
Insn
,
Address
,
this
,
STI
)
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
AArch64
::
LDR_ZA
:
case
AArch64
::
STR_ZA
:
{
MI
.
insert
(
MI
.
begin
(
)
,
MCOperand
::
createReg
(
AArch64
::
ZA
)
)
;
const
MCOperand
&
Imm4Op
=
MI
.
getOperand
(
2
)
;
assert
(
Imm4Op
.
isImm
(
)
&&
"Unexpected operand type!"
)
;
MI
.
addOperand
(
Imm4Op
)
;
break
;
}
case
AArch64
::
LD1_MXIPXX_H_B
:
case
AArch64
::
LD1_MXIPXX_V_B
:
case
AArch64
::
ST1_MXIPXX_H_B
:
case
AArch64
::
ST1_MXIPXX_V_B
:
case
AArch64
::
INSERT_MXIPZ_H_B
:
case
AArch64
::
INSERT_MXIPZ_V_B
:
MI
.
insert
(
MI
.
begin
(
)
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
case
AArch64
::
EXTRACT_ZPMXI_H_B
:
case
AArch64
::
EXTRACT_ZPMXI_V_B
:
MI
.
insert
(
MI
.
begin
(
)
+
2
,
MCOperand
::
createReg
(
AArch64
::
ZAB0
)
)
;
break
;
case
AArch64
::
SMOVvi8to32_idx0
:
case
AArch64
::
SMOVvi8to64_idx0
:
case
AArch64
::
SMOVvi16to32_idx0
:
case
AArch64
::
SMOVvi16to64_idx0
:
case
AArch64
::
SMOVvi32to64_idx0
:
case
AArch64
::
UMOVvi8_idx0
:
case
AArch64
::
UMOVvi16_idx0
:
case
AArch64
::
UMOVvi32_idx0
:
case
AArch64
::
UMOVvi64_idx0
:
MI
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
break
;
}
if
(
Result
!=
MCDisassembler
::
Fail
)
return
Result
;
}
return
MCDisassembler
::
Fail
;
}
</s>

Returns the disassembly of a single instruction .


<s> static bool has_constraint ( unsigned int opnum , enum constraint_num constraint ) { const char * p = recog_data . constraints [ opnum ] ; if ( p == NULL || * p == 0 || * p == ',' ) return true ; do { char c ; unsigned int len ; c = * p ; len = CONSTRAINT_LEN ( c , p ) ; gcc_assert ( len > 0 ) ; switch ( c ) { case 0 : case ',' : return false ; default : if ( lookup_constraint ( p ) == constraint ) return true ; } p += len ; } while ( 1 ) ; } </s>

Returns true if operand OPNUM contains a constraint of type CONSTRAINT . Assumes that the current insn has already been recognised and hence the constraint data has been filled in .


<s> const RegisterBank & AMDGPURegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC ) const { if ( & RC == & AMDGPU :: SReg_1RegClass ) return AMDGPU :: VCCRegBank ; return TRI -> isSGPRClass ( & RC ) ? AMDGPU :: SGPRRegBank : AMDGPU :: VGPRRegBank ; } </s>

AMDGPU AMDGPU AMDGPU::SReg_1RegClass AMDGPU::VCCRegBank AMDGPU::SGPRRegBank AMDGPU::VGPRRegBank


<s> void ARMBaseInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerThunk ) { MachineInstr * Call = & * -- MBB . instr_end ( ) ; bool isThumb = Subtarget . isThumb ( ) ; unsigned FuncOp = isThumb ? 2 : 0 ; unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? ARM :: tTAILJMPr : ARM :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? ARM :: tTAILJMPd : ARM :: tTAILJMPdND : ARM :: TAILJMPd ; MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; if ( isThumb && ! Call -> getOperand ( FuncOp ) . isReg ( ) ) MIB . add ( predOps ( ARMCC :: AL ) ) ; Call -> eraseFromParent ( ) ; } } </s>

Insert a custom frame for outlined functions .

ARM ARM 2 0 ARM::tTAILJMPr ARM::TAILJMPr ARM::tTAILJMPd ARM::tTAILJMPdND ARM::TAILJMPd ARMCC::AL


<s> static bool save_local_or_in_reg_p ( unsigned int regno , int leaf_function ) { if ( ! call_used_or_fixed_reg_p ( regno ) && df_regs_ever_live_p ( regno ) ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ; if ( got_register_rtx && regno == REGNO ( got_register_rtx ) ) return true ; if ( crtl -> accesses_prior_frames && ( regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM ) ) return true ; return false ; } </s>

Return whether REGNO , a local or in register , must be saved/restored .


"value of -mfixed-range must have form REG1-REG2"

Parse the -mfixed-range= option string .


<s> uint32_t BTFDebug :: addType ( std :: unique_ptr < BTFTypeBase > TypeEntry ) { TypeEntry -> setId ( TypeEntries . size ( ) + 1 ) ; uint32_t Id = TypeEntry -> getId ( ) ; TypeEntries . push_back ( std :: move ( TypeEntry ) ) ; return Id ; } </s>

Add a new type attribute to the specified entity .


<s> bool X86FrameInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; bool isWin64 = STI . isTargetWin64 ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == FPReg ) continue ; if ( ! X86 :: VR128RegClass . contains ( Reg ) && ! isWin64 ) { BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , OperandVector & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentInstruction ( Inst , Operands , getContext ( ) , MII , Out ) ; Out . EmitInstruction ( Inst , STI ) ; } </s>


<s> static void rl78_alloc_physical_registers_cmp ( rtx_insn * insn ) { int tmp_id ; rtx saved_op1 ; rtx prev = prev_nonnote_nondebug_insn ( insn ) ; rtx first ; OP ( 1 ) = transcode_memory_rtx ( OP ( 1 ) , DE , insn ) ; OP ( 2 ) = transcode_memory_rtx ( OP ( 2 ) , HL , insn ) ; MAYBE_OK ( insn ) ; if ( REG_P ( OP ( 1 ) ) && REGNO ( OP ( 1 ) ) != AX_REG && GET_MODE ( OP ( 1 ) ) == HImode && MEM_P ( OP ( 2 ) ) ) { rtx cmp = XEXP ( SET_SRC ( PATTERN ( insn ) ) , 0 ) ; OP ( 2 ) = move_to_acc ( 2 , insn ) ; switch ( GET_CODE ( cmp ) ) { case EQ : case NE : break ; case LTU : cmp = gen_rtx_GTU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case GTU : cmp = gen_rtx_LTU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case LEU : cmp = gen_rtx_GEU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case GEU : cmp = gen_rtx_LEU ( HImode , OP ( 2 ) , OP ( 1 ) ) ; break ; case LT : case GT : case LE : case GE : debug_rtx ( insn ) ; default : gcc_unreachable ( ) ; } if ( GET_CODE ( cmp ) == EQ || GET_CODE ( cmp ) == NE ) PATTERN ( insn ) = gen_cbranchhi4_real ( cmp , OP ( 2 ) , OP ( 1 ) , OP ( 3 ) ) ; else PATTERN ( insn ) = gen_cbranchhi4_real_inverted ( cmp , OP ( 2 ) , OP ( 1 ) , OP ( 3 ) ) ; MUST_BE_OK ( insn ) ; } if ( rtx_equal_p ( OP ( 1 ) , OP ( 2 ) ) ) { OP ( 1 ) = OP ( 2 ) = BC ; MUST_BE_OK ( insn ) ; } tmp_id = get_max_insn_count ( ) ; saved_op1 = OP ( 1 ) ; OP ( 1 ) = move_to_acc ( 1 , insn ) ; MAYBE_OK ( insn ) ; if ( tmp_id == get_max_insn_count ( ) ) force_into_acc ( saved_op1 , insn ) ; if ( prev ) first = next_nonnote_nondebug_insn ( prev ) ; else for ( first = insn ; prev_nonnote_nondebug_insn ( first ) ; first = prev_nonnote_nondebug_insn ( first ) ) ; OP ( 2 ) = move_to_hl ( 2 , first ) ; MUST_BE_OK ( insn ) ; } </s>


<s> BitVector X86RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( X86 :: RSP ) ; Reserved . set ( X86 :: ESP ) ; Reserved . set ( X86 :: SP ) ; Reserved . set ( X86 :: SPL ) ; Reserved . set ( X86 :: RIP ) ; Reserved . set ( X86 :: EIP ) ; Reserved . set ( X86 :: IP ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( X86 :: RBP ) ; Reserved . set ( X86 :: EBP ) ; Reserved . set ( X86 :: BP ) ; Reserved . set ( X86 :: BPL ) ; } Reserved . set ( X86 :: ST0 ) ; Reserved . set ( X86 :: ST1 ) ; Reserved . set ( X86 :: ST2 ) ; Reserved . set ( X86 :: ST3 ) ; Reserved . set ( X86 :: ST4 ) ; Reserved . set ( X86 :: ST5 ) ; Reserved . set ( X86 :: ST6 ) ; Reserved . set ( X86 :: ST7 ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
SDValue
SystemZTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
lowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
lowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
lowerGlobalAddress
(
cast
<
GlobalAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
lowerGlobalTLSAddress
(
cast
<
GlobalAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
lowerBlockAddress
(
cast
<
BlockAddressSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
JumpTable
:
return
lowerJumpTable
(
cast
<
JumpTableSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
lowerConstantPool
(
cast
<
ConstantPoolSDNode
>
(
Op
)
,
DAG
)
;
case
ISD
::
BITCAST
:
return
lowerBITCAST
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
lowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
lowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
DYNAMIC_STACKALLOC
:
return
lowerDYNAMIC_STACKALLOC
(
Op
,
DAG
)
;
case
ISD
::
SMUL_LOHI
:
return
lowerSMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
UMUL_LOHI
:
return
lowerUMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
SDIVREM
:
return
lowerSDIVREM
(
Op
,
DAG
)
;
case
ISD
::
UDIVREM
:
return
lowerUDIVREM
(
Op
,
DAG
)
;
case
ISD
::
OR
:
return
lowerOR
(
Op
,
DAG
)
;
case
ISD
::
ATOMIC_SWAP
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_SWAPW
)
;
case
ISD
::
ATOMIC_LOAD_ADD
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_ADD
)
;
case
ISD
::
ATOMIC_LOAD_SUB
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_SUB
)
;
case
ISD
::
ATOMIC_LOAD_AND
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_AND
)
;
case
ISD
::
ATOMIC_LOAD_OR
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_OR
)
;
case
ISD
::
ATOMIC_LOAD_XOR
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_XOR
)
;
case
ISD
::
ATOMIC_LOAD_NAND
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_NAND
)
;
case
ISD
::
ATOMIC_LOAD_MIN
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_MIN
)
;
case
ISD
::
ATOMIC_LOAD_MAX
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_MAX
)
;
case
ISD
::
ATOMIC_LOAD_UMIN
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_UMIN
)
;
case
ISD
::
ATOMIC_LOAD_UMAX
:
return
lowerATOMIC_LOAD
(
Op
,
DAG
,
SystemZISD
::
ATOMIC_LOADW_UMAX
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
return
lowerATOMIC_CMP_SWAP
(
Op
,
DAG
)
;
case
ISD
::
STACKSAVE
:
return
lowerSTACKSAVE
(
Op
,
DAG
)
;
case
ISD
::
STACKRESTORE
:
return
lowerSTACKRESTORE
(
Op
,
DAG
)
;
case
ISD
::
PREFETCH
:
return
lowerPREFETCH
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"Unexpected node to lower"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool X86DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , Op2 , Op3 ; switch ( ConstraintCode ) { case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op , Op0 , Op1 , Op2 , Op3 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> Optional < MCFixupKind > MipsAsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "R_MIPS_NONE" , ( MCFixupKind ) Mips :: fixup_Mips_NONE ) . Case ( "R_MIPS_32" , FK_Data_4 ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_CALL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_HI16 ) . Case ( "R_MIPS_CALL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_LO16 ) . Case ( "R_MIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL16 ) . Case ( "R_MIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_OFST ) . Case ( "R_MIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_DISP ) . Case ( "R_MIPS_GOT_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_HI16 ) . Case ( "R_MIPS_GOT_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_LO16 ) . Case ( "R_MIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_Mips_GOTTPREL ) . Case ( "R_MIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_HI ) . Case ( "R_MIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_LO ) . Case ( "R_MIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_Mips_TLSGD ) . Case ( "R_MIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_Mips_TLSLDM ) . Case ( "R_MIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_HI ) . Case ( "R_MIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_LO ) . Case ( "R_MICROMIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_CALL16 ) . Case ( "R_MICROMIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_DISP ) . Case ( "R_MICROMIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_PAGE ) . Case ( "R_MICROMIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_OFST ) . Case ( "R_MICROMIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT16 ) . Case ( "R_MICROMIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOTTPREL ) . Case ( "R_MICROMIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 ) . Case ( "R_MICROMIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_GD ) . Case ( "R_MICROMIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_LDM ) . Case ( "R_MICROMIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 ) . Case ( "R_MIPS_JALR" , ( MCFixupKind ) Mips :: fixup_Mips_JALR ) . Case ( "R_MICROMIPS_JALR" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_JALR ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> void x86_emit_floatuns ( rtx operands [ 2 ] ) { rtx_code_label * neglab , * donelab ; rtx i0 , i1 , f0 , in , out ; machine_mode mode , inmode ; inmode = GET_MODE ( operands [ 1 ] ) ; gcc_assert ( inmode == SImode || inmode == DImode ) ; out = operands [ 0 ] ; in = force_reg ( inmode , operands [ 1 ] ) ; mode = GET_MODE ( out ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; f0 = gen_reg_rtx ( mode ) ; emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , inmode , 0 , neglab ) ; expand_float ( out , in , 0 ) ; emit_jump_insn ( gen_jump ( donelab ) ) ; emit_barrier ( ) ; emit_label ( neglab ) ; i0 = expand_simple_binop ( inmode , LSHIFTRT , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i1 = expand_simple_binop ( inmode , AND , in , const1_rtx , NULL , 1 , OPTAB_DIRECT ) ; i0 = expand_simple_binop ( inmode , IOR , i0 , i1 , i0 , 1 , OPTAB_DIRECT ) ; expand_float ( f0 , i0 , 0 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , out , gen_rtx_PLUS ( mode , f0 , f0 ) ) ) ; emit_label ( donelab ) ; } </s>

Generate an unsigned DImode/SImode to FP conversion . This is the same code optabs would emit if we did n't have TFmode patterns .


Return an array that contains the direct target flag values and their names .

Lanai Lanai Lanai "lanai-hi" "lanai-lo" "lanai-nf"


<s> static rtx alignment_mask ( rtx_insn * insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != AND || ! REG_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return 0 ; rtx mask = XEXP ( SET_SRC ( body ) , 1 ) ; if ( GET_CODE ( mask ) == CONST_INT ) { if ( INTVAL ( mask ) == - 16 ) return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; else return 0 ; } if ( ! REG_P ( mask ) ) return 0 ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; rtx real_mask = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( use ) , mask ) ) continue ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return 0 ; rtx_insn * const_insn = DF_REF_INSN ( def_link -> ref ) ; rtx const_body = PATTERN ( const_insn ) ; if ( GET_CODE ( const_body ) != SET ) return 0 ; real_mask = SET_SRC ( const_body ) ; if ( GET_CODE ( real_mask ) != CONST_INT || INTVAL ( real_mask ) != - 16 ) return 0 ; } if ( real_mask == 0 ) return 0 ; return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; } </s>

Check whether an rtx is an alignment mask , and if so , return a fully-expanded rtx for the masking operation .


<s>
const
char
*
pa_output_64bit_ior
(
rtx
*
operands
)
{
unsigned
HOST_WIDE_INT
mask
=
INTVAL
(
operands
[
2
]
)
;
int
bs0
,
bs1
,
p
,
len
;
if
(
INTVAL
(
operands
[
2
]
)
==
0
)
return
"copy %1,%0"
;
for
(
bs0
=
0
;
bs0
<
HOST_BITS_PER_WIDE_INT
;
bs0
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
bs0
)
)
!=
0
)
break
;
for
(
bs1
=
bs0
;
bs1
<
HOST_BITS_PER_WIDE_INT
;
bs1
++
)
if
(
(
mask
&
(
(
unsigned
HOST_WIDE_INT
)
1
<<
bs1
)
)
==
0
)
break
;
gcc_assert
(
bs1
==
HOST_BITS_PER_WIDE_INT
||
(
(
unsigned
HOST_WIDE_INT
)
1
<<
bs1
)
>
mask
)
;
p
=
63
bs0
;
len
=
bs1
bs0
;
operands
[
2
]
=
GEN_INT
(
p
)
;
operands
[
3
]
=
GEN_INT
(
len
)
;
return
"depdi -1,%2,%3,%0"
;
}
</s>

Return a string to perform a bitwise-and of operands [ 1 ] with operands [ 2 ] storing the result in operands [ 0 ] .


<s> bool RISCVAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == ".option" ) return parseDirectiveOption ( ) ; if ( IDVal == ".attribute" ) return parseDirectiveAttribute ( ) ; if ( IDVal == ".insn" ) return parseDirectiveInsn ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> static int rs6000_hard_regno_mode_ok_uncached ( int regno , machine_mode mode ) { int last_regno = regno + rs6000_hard_regno_nregs [ mode ] [ regno ] - 1 ; if ( COMPLEX_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( mode == PTImode ) return ( IN_RANGE ( regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && IN_RANGE ( last_regno , FIRST_GPR_REGNO , LAST_GPR_REGNO ) && ( ( regno & 1 ) == 0 ) ) ; if ( TARGET_VSX && VSX_REGNO_P ( regno ) && ( VECTOR_MEM_VSX_P ( mode ) || FLOAT128_VECTOR_P ( mode ) || reg_addr [ mode ] . scalar_in_vmx_p || ( TARGET_VSX_TIMODE && mode == TImode ) || ( TARGET_VADDUQM && mode == V1TImode ) ) ) { if ( FP_REGNO_P ( regno ) ) return FP_REGNO_P ( last_regno ) ; if ( ALTIVEC_REGNO_P ( regno ) ) { if ( GET_MODE_SIZE ( mode ) != 16 && ! reg_addr [ mode ] . scalar_in_vmx_p ) return 0 ; return ALTIVEC_REGNO_P ( last_regno ) ; } } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( FLOAT128_VECTOR_P ( mode ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % 2 ) == 0 ) && FP_REGNO_P ( last_regno ) ) return 1 ; if ( GET_MODE_CLASS ( mode ) == MODE_INT ) { if ( GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return 1 ; if ( TARGET_VSX_SMALL_INTEGER ) { if ( mode == SImode ) return 1 ; if ( TARGET_P9_VECTOR && ( mode == HImode || mode == QImode ) ) return 1 ; } } if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return 1 ; return 0 ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return 1 ; return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ; } </s>

Value is 1 if hard register REGNO can hold a value of machine-mode MODE .


<s> static void aarch64_simd_clone_adjust ( struct cgraph_node * node ) { tree t = TREE_TYPE ( node -> decl ) ; TYPE_ATTRIBUTES ( t ) = make_attribute ( "aarch64_vector_pcs" , "default" , TYPE_ATTRIBUTES ( t ) ) ; } </s>


<s> bool X86TargetLowering :: isSafeMemOpType ( MVT VT ) const { if ( VT == MVT :: f32 ) return X86ScalarSSEf32 ; if ( VT == MVT :: f64 ) return X86ScalarSSEf64 ; return true ; } </s>

Returns true if it 's safe to use load / store of the specified type to expand memcpy / memset inline .


<s> Register SIRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SIFrameLowering * TFI = MF . getSubtarget < GCNSubtarget > ( ) . getFrameLowering ( ) ; const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) { return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : Register ( ) ; } return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : FuncInfo -> getStackPtrOffsetReg ( ) ; } </s>


<s> bool isTarget64BitILP32 ( ) const { return Is64Bit && ( TargetTriple . isX32 ( ) || TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the ILP32 programming model ( x32 ABI ) ?


<s> void clear ( ) { memset ( ScoreLBs , 0 , sizeof ( ScoreLBs ) ) ; memset ( ScoreUBs , 0 , sizeof ( ScoreUBs ) ) ; memset ( EventUBs , 0 , sizeof ( EventUBs ) ) ; for ( enum InstCounterType T = VM_CNT ; T < NUM_INST_CNTS ; T = ( enum InstCounterType ) ( T + 1 ) ) { memset ( VgprScores [ T ] , 0 , sizeof ( VgprScores [ T ] ) ) ; } memset ( SgprScores , 0 , sizeof ( SgprScores ) ) ; } </s>


<s> static bool alpha_cannot_force_const_mem ( rtx x ) { enum rtx_code code = GET_CODE ( x ) ; return code == SYMBOL_REF || code == LABEL_REF || code == CONST ; } </s>

Primarily this is required for TLS symbols , but given that our move patterns * ought * to be able to handle any symbol at any time , we should never be spilling symbolic operands to the constant pool , ever .


<s> void AArch64PassConfig :: addPostRegAlloc ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( createAArch64DeadRegisterDefinitions ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && ( TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA53 ( ) || TM -> getSubtarget < AArch64Subtarget > ( ) . isCortexA57 ( ) ) && usingDefaultRegAlloc ( ) ) addPass ( createAArch64A57FPLoadBalancing ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> bool run ( ) { return runOnNode ( MDT . getRootNode ( ) ) ; } </s>

Run the analysis pass over a function and produce a dominator tree .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } if ( isOSWindows ( ) ) return X86II :: MO_NO_FLAG ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } if ( TM . getRelocationModel ( ) == Reloc :: Static ) return X86II :: MO_NO_FLAG ; return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


"missing name in %<target(\"arch=\")%> pragma or attribute"

"invalid name (\"%s\") in %<target(\"arch=\")%> pragma or attribute"

"invalid value (\"%s\") in %<target()%> pragma or attribute"

Handle the ARCH_STR argument to the arch= target attribute . PRAGMA_OR_ATTR is used in potential error messages .


<s> static bool mips_relational_operand_ok_p ( enum rtx_code code , rtx cmp1 ) { switch ( code ) { case GT : case GTU : return reg_or_0_operand ( cmp1 , VOIDmode ) ; case GE : case GEU : return ! TARGET_MIPS16 && cmp1 == const1_rtx ; case LT : case LTU : return arith_operand ( cmp1 , VOIDmode ) ; case LE : return sle_operand ( cmp1 , VOIDmode ) ; case LEU : return sleu_operand ( cmp1 , VOIDmode ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if CMP1 is a suitable second operand for relational operator CODE . See also the * sCC patterns in mips.md .


<s> ScheduleDAGInstrs * GCNPassConfig :: createMachineScheduler ( MachineSchedContext * C ) const { const SISubtarget & ST = C -> MF -> getSubtarget < SISubtarget > ( ) ; if ( ST . enableSIScheduler ( ) ) return createSIMachineScheduler ( C ) ; return nullptr ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


"  Skipping pass: no machine model present.\n"

runOnMachineFunction - Emit the function body .


<s> void sh_mark_label ( rtx address , int nuses ) { if ( GOTOFF_P ( address ) ) { address = XEXP ( address , 0 ) ; if ( GET_CODE ( address ) == PLUS ) address = XEXP ( address , 0 ) ; address = XVECEXP ( address , 0 , 0 ) ; } if ( GET_CODE ( address ) == LABEL_REF && LABEL_P ( XEXP ( address , 0 ) ) ) LABEL_NUSES ( XEXP ( address , 0 ) ) += nuses ; } </s>

If ADDRESS refers to a CODE_LABEL , add NUSES to the number of times that label is used .


<s> static machine_mode aarch64_simd_container_mode ( machine_mode mode , unsigned width ) { gcc_assert ( width == 64 || width == 128 ) ; if ( TARGET_SIMD ) { if ( width == 128 ) switch ( mode ) { case DFmode : return V2DFmode ; case SFmode : return V4SFmode ; case SImode : return V4SImode ; case HImode : return V8HImode ; case QImode : return V16QImode ; case DImode : return V2DImode ; default : break ; } else switch ( mode ) { case SFmode : return V2SFmode ; case SImode : return V2SImode ; case HImode : return V4HImode ; case QImode : return V8QImode ; default : break ; } } return word_mode ; } </s>

Return appropriate SIMD container for MODE within a vector of WIDTH bits .


<s>
void
LatticeCell
::
print
(
raw_ostream
&
os
)
const
{
if
(
isProperty
(
)
)
{
os
<<
"{ "
;
uint32_t
Ps
=
properties
(
)
;
if
(
Ps
&
ConstantProperties
::
Zero
)
os
<<
"zero "
;
if
(
Ps
&
ConstantProperties
::
NonZero
)
os
<<
"nonzero "
;
if
(
Ps
&
ConstantProperties
::
Finite
)
os
<<
"finite "
;
if
(
Ps
&
ConstantProperties
::
Infinity
)
os
<<
"infinity "
;
if
(
Ps
&
ConstantProperties
::
)
os
<<
"nan "
;
if
(
Ps
&
ConstantProperties
::
PosOrZero
)
os
<<
"poz "
;
if
(
Ps
&
ConstantProperties
::
NegOrZero
)
os
<<
"nez "
;
os
<<
'}'
;
return
;
}
os
<<
"{ "
;
if
(
isBottom
(
)
)
{
os
<<
"bottom"
;
}
else
if
(
isTop
(
)
)
{
os
<<
"top"
;
}
else
{
for
(
unsigned
i
=
0
;
i
<
size
(
)
;
++
i
)
{
const
Constant
*
C
=
Values
[
i
]
;
if
(
i
!=
0
)
os
<<
", "
;
C
->
print
(
os
)
;
}
}
os
<<
" }"
;
}
</s>

print - Print a debug representation of the operand to the given stream .

Hexagon
"{ "
"zero "
"nonzero "
"finite "
"infinity "
"nan "
"poz "
"nez "
"{ "
"bottom"
"top"
0
0
", "
" }"


<s> void emit_v9_brxx_insn ( enum rtx_code code , rtx op0 , rtx label ) { gcc_assert ( sparc_compare_emitted == NULL_RTX ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ; } </s>

Emit a conditional jump insn for the v9 architecture using comparison code CODE and jump target LABEL . This function exists to take advantage of the v9 brxx insns .


<s> bool PPCAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; O << "0(" ; printOperand ( MI , OpNo ) ; O << ")" ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> const uint32_t * AArch64RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { if ( CC == CallingConv :: AnyReg ) return CSR_AArch64_AllRegs_RegMask ; else return CSR_AArch64_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool RISCVTargetLowering :: shouldExtendTypeInLibCall ( EVT Type ) const { RISCVABI :: ABI ABI = Subtarget . getTargetABI ( ) ; if ( ABI == RISCVABI :: ABI_LP64 && ( Type == MVT :: f32 ) ) return false ; return true ; } </s>

Returns true if arguments should be extended in lib calls .


<s> static HOST_WIDE_INT rs6000_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST && ( STRICT_ALIGNMENT || ! optimize_size ) ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> bool RISCVAsmParser :: processInstruction ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { Inst . setLoc ( IDLoc ) ; if ( Inst . getOpcode ( ) == RISCV :: PseudoLI ) { auto Reg = Inst . getOperand ( 0 ) . getReg ( ) ; int64_t Imm = Inst . getOperand ( 1 ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < 32 > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } else if ( Inst . getOpcode ( ) == RISCV :: PseudoLLA ) { emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; } emitToStreamer ( Out , Inst ) ; return false ; } </s>

Process a single instruction and collect debug info anchors .


<s> const MCPhysReg * SparcRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_SaveList ; } </s>


<s> static void msp430_print_operand_addr ( FILE * file , machine_mode , rtx addr ) { switch ( GET_CODE ( addr ) ) { case PLUS : msp430_print_operand_raw ( file , XEXP ( addr , 1 ) ) ; gcc_assert ( REG_P ( XEXP ( addr , 0 ) ) ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; return ; case REG : fprintf ( file , "@" ) ; break ; case POST_INC : fprintf ( file , "@%s+" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; return ; case CONST : case CONST_INT : case SYMBOL_REF : case LABEL_REF : fprintf ( file , "&" ) ; break ; default : break ; } msp430_print_operand_raw ( file , addr ) ; } </s>

Output to stdio stream FILE the assembler syntax for an instruction operand that is a memory reference whose address is ADDR .


<s>
void
SIInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
Size
=
FrameInfo
.
getObjectSize
(
FrameIndex
)
;
unsigned
Align
=
FrameInfo
.
getObjectAlignment
(
FrameIndex
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOStore
,
Size
,
Align
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
SrcReg
!=
AMDGPU
::
M0
&&
"m0 should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillSaveOpcode
(
SpillSize
)
)
;
if
(
Register
::
isVirtualRegister
(
SrcReg
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
SrcReg
,
&
AMDGPU
::
SReg_32_XM0RegClass
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
,
RegState
::
Implicit
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillSaveOpcode
(
SpillSize
)
:
getVGPRSpillSaveOpcode
(
SpillSize
)
;
MFI
->
setHasSpilledVGPRs
(
)
;
auto
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
)
;
if
(
RI
.
hasAGPRs
(
RC
)
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
Register
Tmp
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
VGPR_32RegClass
)
;
MIB
.
addReg
(
Tmp
,
RegState
::
Define
)
;
}
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getScratchRSrcReg
(
)
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
unsigned
HexagonInstrInfo
::
reduceLoopCount
(
MachineBasicBlock
&
MBB
,
MachineInstr
*
IndVar
,
MachineInstr
&
Cmp
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
SmallVectorImpl
<
MachineInstr
*
>
&
PrevInsts
,
unsigned
Iter
,
unsigned
MaxIter
)
const
{
assert
(
(
!
IndVar
)
&&
isEndLoopN
(
Cmp
.
getOpcode
(
)
)
&&
"Expecting a hardware loop"
)
;
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
DebugLoc
DL
=
Cmp
.
getDebugLoc
(
)
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
VisitedBBs
;
MachineInstr
*
Loop
=
findLoopInstr
(
&
MBB
,
Cmp
.
getOpcode
(
)
,
Cmp
.
getOperand
(
0
)
.
getMBB
(
)
,
VisitedBBs
)
;
if
(
!
Loop
)
return
0
;
if
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0i
||
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop1i
)
{
int64_t
Offset
=
Loop
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
Offset
<=
1
)
Loop
->
eraseFromParent
(
)
;
else
Loop
->
getOperand
(
1
)
.
setImm
(
Offset
1
)
;
return
Offset
1
;
}
assert
(
Loop
->
getOpcode
(
)
==
Hexagon
::
J2_loop0r
&&
"Unexpected instruction"
)
;
unsigned
LoopCount
=
Loop
->
getOperand
(
1
)
.
getReg
(
)
;
unsigned
LoopEnd
=
createVR
(
MF
,
MVT
::
i1
)
;
MachineInstr
*
NewCmp
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
C2_cmpgtui
)
,
LoopEnd
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
unsigned
NewLoopCount
=
createVR
(
MF
,
MVT
::
i32
)
;
MachineInstr
*
NewAdd
=
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
A2_addi
)
,
NewLoopCount
)
.
addReg
(
LoopCount
)
.
addImm
(
1
)
;
for
(
SmallVectorImpl
<
MachineInstr
*
>
::
iterator
I
=
PrevInsts
.
begin
(
)
,
E
=
PrevInsts
.
end
(
)
;
I
!=
E
;
++
I
)
(
*
I
)
->
substituteRegister
(
LoopCount
,
NewLoopCount
,
0
,
getRegisterInfo
(
)
)
;
PrevInsts
.
clear
(
)
;
PrevInsts
.
push_back
(
NewCmp
)
;
PrevInsts
.
push_back
(
NewAdd
)
;
if
(
Iter
==
MaxIter
)
BuildMI
(
&
MBB
,
DL
,
get
(
Hexagon
::
J2_loop0r
)
)
.
addMBB
(
Loop
->
getOperand
(
0
)
.
getMBB
(
)
)
.
addReg
(
NewLoopCount
)
;
if
(
Iter
==
0
)
Loop
->
eraseFromParent
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
Hexagon
::
J2_jumpf
)
)
;
Cond
.
push_back
(
NewCmp
->
getOperand
(
0
)
)
;
return
NewLoopCount
;
}
</s>

Generate code to reduce the loop iteration by one and check if the loop is finished .


<s>
unsigned
PPCTTI
::
getArithmeticInstrCost
(
unsigned
Opcode
,
Type
*
Ty
,
OperandValueKind
Op1Info
,
OperandValueKind
Op2Info
)
const
{
assert
(
TLI
->
InstructionOpcodeToISD
(
Opcode
)
&&
"Invalid opcode"
)
;
return
TargetTransformInfo
::
getArithmeticInstrCost
(
Opcode
,
Ty
,
Op1Info
,
Op2Info
)
;
}
</s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> bool isMem ( ) const { return Kind == k_Memory ; } </s>


<s> bool NVPTXTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseGV ) { if ( AM . BaseOffs || AM . HasBaseReg || AM . Scale ) return false ; return true ; } switch ( AM . Scale ) { case 0 : break ; case 1 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool cris_reload_address_legitimized ( rtx x , enum machine_mode mode ATTRIBUTE_UNUSED , int opnum ATTRIBUTE_UNUSED , int itype , int ind_levels ATTRIBUTE_UNUSED ) { enum reload_type type = itype ; rtx op0 , op1 ; rtx * op0p ; rtx * op1p ; if ( GET_CODE ( x ) != PLUS ) return false ; op0 = XEXP ( x , 0 ) ; op0p = & XEXP ( x , 0 ) ; op1 = XEXP ( x , 1 ) ; op1p = & XEXP ( x , 1 ) ; if ( ! REG_P ( op1 ) ) return false ; if ( GET_CODE ( op0 ) == SIGN_EXTEND && GET_CODE ( XEXP ( op0 , 0 ) ) == MEM ) { rtx op00 = XEXP ( op0 , 0 ) ; rtx op000 = XEXP ( op00 , 0 ) ; rtx * op000p = & XEXP ( op00 , 0 ) ; if ( ( GET_MODE ( op00 ) == HImode || GET_MODE ( op00 ) == QImode ) && ( REG_P ( op000 ) || ( GET_CODE ( op000 ) == POST_INC && REG_P ( XEXP ( op000 , 0 ) ) ) ) ) { bool something_reloaded = false ; if ( GET_CODE ( op000 ) == POST_INC && REG_P ( XEXP ( op000 , 0 ) ) && REGNO ( XEXP ( op000 , 0 ) ) > CRIS_LAST_GENERAL_REGISTER ) return false ; if ( ( REG_P ( op000 ) && REGNO ( op000 ) > CRIS_LAST_GENERAL_REGISTER ) ) { push_reload ( op000 , NULL_RTX , op000p , NULL , GENERAL_REGS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , type ) ; something_reloaded = true ; } if ( REGNO ( op1 ) > CRIS_LAST_GENERAL_REGISTER ) { push_reload ( op1 , NULL_RTX , op1p , NULL , GENERAL_REGS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , type ) ; something_reloaded = true ; } gcc_assert ( something_reloaded ) ; return true ; } } return false ; } </s>

Worker function for LEGITIMIZE_RELOAD_ADDRESS .


<s> static void mips_emit_int_relational ( enum rtx_code code , bool * invert_ptr , rtx target , rtx cmp0 , rtx cmp1 ) { if ( mips_relational_operand_ok_p ( code , cmp1 ) ) mips_emit_binary ( code , target , cmp0 , cmp1 ) ; else if ( mips_canonicalize_comparison ( & code , & cmp1 , GET_MODE ( target ) ) ) mips_emit_binary ( code , target , cmp0 , cmp1 ) ; else { enum rtx_code inv_code = reverse_condition ( code ) ; if ( ! mips_relational_operand_ok_p ( inv_code , cmp1 ) ) { cmp1 = force_reg ( GET_MODE ( cmp0 ) , cmp1 ) ; mips_emit_int_relational ( code , invert_ptr , target , cmp0 , cmp1 ) ; } else if ( invert_ptr == 0 ) { rtx inv_target = gen_reg_rtx ( GET_MODE ( target ) ) ; mips_emit_binary ( inv_code , inv_target , cmp0 , cmp1 ) ; mips_emit_binary ( XOR , target , inv_target , const1_rtx ) ; } else { * invert_ptr = ! * invert_ptr ; mips_emit_binary ( inv_code , target , cmp0 , cmp1 ) ; } } } </s>

Compare CMP0 and CMP1 using relational operator CODE and store the result in TARGET . CMP0 and TARGET are register_operands that have the same integer mode . If INVERT_PTR is nonnull , it 's OK to set TARGET to the inverse of the result and flip * INVERT_PTR instead .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool NEONMoveFixPass :: runOnMachineFunction ( MachineFunction & Fn ) { ARMFunctionInfo * AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; const TargetMachine & TM = Fn . getTarget ( ) ; if ( AFI -> isThumbFunction ( ) ) return false ; TRI = TM . getRegisterInfo ( ) ; TII = static_cast < const ARMBaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= InsertMoves ( MBB ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addRequired < WebAssemblyExceptionInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool MipsCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) { return false ; } for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( Arg . getType ( ) ) ) return false ; } MachineFunction & MF = MIRBuilder . getMF ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const MipsTargetLowering & TLI = * getTLI < MipsTargetLowering > ( ) ; SmallVector < ArgInfo , 8 > ArgInfos ; SmallVector < unsigned , 8 > OrigArgIndices ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { ArgInfo AInfo ( VRegs [ i ] , Arg . getType ( ) ) ; setArgFlags ( AInfo , i + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( AInfo , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < ISD :: InputArg , 8 > Ins ; subTargetRegTypeForCallingConv ( F , ArgInfos , OrigArgIndices , Ins ) ; SmallVector < CCValAssign , 16 > ArgLocs ; MipsCCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const MipsTargetMachine & TM = static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) ; const MipsABIInfo & ABI = TM . getABI ( ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( F . getCallingConv ( ) ) , 1 ) ; CCInfo . AnalyzeFormalArguments ( Ins , TLI . CCAssignFnForCall ( ) ) ; setLocInfo ( ArgLocs , Ins ) ; IncomingValueHandler Handler ( MIRBuilder , MF . getRegInfo ( ) ) ; if ( ! Handler . handle ( ArgLocs , ArgInfos ) ) return false ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static bool aarch64_pragma_target_parse ( tree args , tree pop_target ) { if ( args ) { if ( ! aarch64_process_target_attr ( args , "pragma" ) ) return false ; aarch64_override_options_internal ( & global_options ) ; } else { pop_target = pop_target ? pop_target : target_option_default_node ; cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( pop_target ) ) ; } target_option_current_node = build_target_option_node ( & global_options ) ; aarch64_reset_previous_fndecl ( ) ; cpp_options * cpp_opts = cpp_get_options ( parse_in ) ; unsigned char saved_warn_unused_macros = cpp_opts -> warn_unused_macros ; cpp_opts -> warn_unused_macros = 0 ; aarch64_update_cpp_builtins ( parse_in ) ; cpp_opts -> warn_unused_macros = saved_warn_unused_macros ; if ( pop_target ) aarch64_save_restore_target_globals ( pop_target ) ; if ( TARGET_SIMD ) { tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL ; aarch64_init_simd_builtins ( ) ; current_target_pragma = saved_current_target_pragma ; } return true ; } </s>

Hook to validate the current # pragma GCC target and set the state , and update the macros based on what was changed . If ARGS is NULL , then POP_TARGET is used to reset the options .


<s>
void
XCoreInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
bool
GRDest
=
XCore
::
GRRegsRegClass
.
contains
(
DestReg
)
;
bool
GRSrc
=
XCore
::
GRRegsRegClass
.
contains
(
SrcReg
)
;
if
(
GRDest
&&
GRSrc
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
XCore
::
ADD_2rus
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
if
(
GRDest
&&
SrcReg
==
XCore
::
SP
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
XCore
::
LDAWSP_ru6
)
,
DestReg
)
.
addImm
(
0
)
;
return
;
}
if
(
DestReg
==
XCore
::
SP
&&
GRSrc
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
XCore
::
SETSP_1r
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> void or1k_profile_hook ( void ) { rtx a1 = gen_rtx_REG ( Pmode , 3 ) ; rtx ra = get_hard_reg_initial_val ( Pmode , LR_REGNUM ) ; rtx fun = gen_rtx_SYMBOL_REF ( Pmode , "_mcount" ) ; cfun -> machine -> set_mcount_arg_insn = emit_move_insn ( a1 , ra ) ; emit_library_call ( fun , LCT_NORMAL , VOIDmode , a1 , Pmode ) ; } </s>

Worker for PROFILE_HOOK . The OpenRISC profile hook uses the link register which will get clobbered by the GOT setup RTX . This sets up a placeholder to allow injecting of the GOT setup RTX to avoid clobbering .


<s> void AMDGPUPassConfig :: addIRPasses ( ) { disablePass ( & StackMapLivenessID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerLegacyPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; addPass ( createAMDGPUOpenCLImageTypeLoweringPass ( ) ) ; const AMDGPUTargetMachine & TM = getAMDGPUTargetMachine ( ) ; if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) { addPass ( createAMDGPUPromoteAlloca ( & TM ) ) ; if ( EnableSROA ) addPass ( createSROAPass ( ) ) ; addStraightLineScalarOptimizationPasses ( ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> void ARMInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << markup ( "<reg:" ) << getRegisterName ( RegNo , DefaultAltIdx ) << markup ( ">" ) ; } </s>


<s> int crx_initial_elimination_offset ( int from , int to ) { crx_compute_save_regs ( ) ; crx_compute_frame ( ) ; if ( ( from ) == FRAME_POINTER_REGNUM && ( to ) == STACK_POINTER_REGNUM ) return ( ACCUMULATE_OUTGOING_ARGS ? current_function_outgoing_args_size : 0 ) ; else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == FRAME_POINTER_REGNUM ) return ( sum_regs + local_vars_size ) ; else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == STACK_POINTER_REGNUM ) return ( sum_regs + local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? current_function_outgoing_args_size : 0 ) ) ; else abort ( ) ; } </s>

Implements the macro INITIAL_ELIMINATION_OFFSET , return the OFFSET .


<s> static int mergeSPUpdates ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , bool doMergeWithPrevious ) { if ( ( doMergeWithPrevious && MBBI == MBB . begin ( ) ) || ( ! doMergeWithPrevious && MBBI == MBB . end ( ) ) ) return 0 ; int Offset = 0 ; MachineBasicBlock :: iterator PI = doMergeWithPrevious ? prior ( MBBI ) : MBBI ; MachineBasicBlock :: iterator NI = doMergeWithPrevious ? 0 : next ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( ( Opc == X86 :: ADD64ri32 || Opc == X86 :: ADD64ri8 || Opc == X86 :: ADD32ri || Opc == X86 :: ADD32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == X86 :: SUB64ri32 || Opc == X86 :: SUB64ri8 || Opc == X86 :: SUB32ri || Opc == X86 :: SUB32ri8 ) && PI -> getOperand ( 0 ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( 2 ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ; } </s>

Check the instruction before/after the passed instruction .


<s> const ELFAttributeValue * ARMELFAttributeData :: getAttributeValue ( TagType pTag ) const { if ( pTag <= Tag_Max ) { const ELFAttributeValue & attr_value = m_Attrs [ pTag ] ; if ( attr_value . isInitialized ( ) ) { return & attr_value ; } else { return NULL ; } } else { UnknownAttrsMap :: const_iterator attr_it = m_UnknownAttrs . find ( pTag ) ; if ( attr_it == m_UnknownAttrs . end ( ) ) { return NULL ; } else { return & attr_it -> second ; } } } </s>

Extract a DWARF form value from a DIE specified by DIE offset .


<s> static rtx altivec_expand_ld_builtin ( tree exp , rtx target , bool * expandedp ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 ; machine_mode tmode , mode0 ; rtx pat , op0 ; enum insn_code icode ; switch ( fcode ) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi : icode = CODE_FOR_vector_altivec_load_v16qi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi : icode = CODE_FOR_vector_altivec_load_v8hi ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4si : icode = CODE_FOR_vector_altivec_load_v4si ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_4sf : icode = CODE_FOR_vector_altivec_load_v4sf ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2df : icode = CODE_FOR_vector_altivec_load_v2df ; break ; case ALTIVEC_BUILTIN_LD_INTERNAL_2di : icode = CODE_FOR_vector_altivec_load_v2di ; case ALTIVEC_BUILTIN_LD_INTERNAL_1ti : icode = CODE_FOR_vector_altivec_load_v1ti ; break ; default : * expandedp = false ; return NULL_RTX ; } * expandedp = true ; arg0 = CALL_EXPR_ARG ( exp , 0 ) ; op0 = expand_normal ( arg0 ) ; tmode = insn_data [ icode ] . operand [ 0 ] . mode ; mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( target == 0 || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>


<s> bool SPUTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> bool GCNDPPCombine :: runOnMachineFunction ( MachineFunction & MF ) { ST = & MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST -> hasDPP ( ) || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = ST -> getInstrInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { for ( auto I = MBB . rbegin ( ) , E = MBB . rend ( ) ; I != E ; ) { auto & MI = * I ++ ; if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_B32_dpp && combineDPPMov ( MI ) ) { Changed = true ; ++ NumDPPMovsCombined ; } else if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_B64_DPP_PSEUDO ) { if ( ST -> has64BitDPP ( ) && combineDPPMov ( MI ) ) { Changed = true ; ++ NumDPPMovsCombined ; } else { auto Split = TII -> expandMovDPP64 ( MI ) ; for ( auto M : { Split . first , Split . second } ) { if ( M && combineDPPMov ( * M ) ) ++ NumDPPMovsCombined ; } Changed = true ; } } } } return Changed ; } </s>


<s> bool AMDGPULowerIntrinsics :: runOnModule ( Module & M ) { bool Changed = false ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case Intrinsic :: memcpy : case Intrinsic :: memmove : case Intrinsic :: memset : if ( expandMemIntrinsicUses ( F ) ) Changed = true ; break ; default : break ; } } return Changed ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .

AMDGPU AMDGPU Intrinsic::memcpy Intrinsic::memmove Intrinsic::memset


<s> int mask_one_bit_p ( HOST_WIDE_INT mask ) { int i ; unsigned HOST_WIDE_INT n = mask ; for ( i = 0 ; i < 32 ; ++ i ) { if ( n & 0x80000000L ) { if ( n & 0x7fffffffL ) return 0 ; else return 32 - i ; } n <<= 1 ; } return 0 ; } </s>

Returns nonzero if the number MASK has only one bit set .


<s> void m68k_emit_move_double ( rtx operands [ 2 ] ) { handle_move_double ( operands , emit_reg_adjust , emit_movsi , emit_movsi ) ; } </s>

Output rtl code to perform a doubleword move insn with operands OPERANDS .


Implement the TARGET_CPU_CPP_BUILTINS macro


<s> static bool c6x_function_ok_for_sibcall ( tree decl , tree exp ) { if ( c6x_call_saved_register_used ( exp ) ) return false ; if ( ! flag_pic ) return true ; if ( TARGET_DSBT ) { if ( ! decl ) return false ; cgraph_node * this_func = cgraph_node :: local_info_node ( current_function_decl ) ; return this_func -> local ; } return true ; } </s>

Decide whether we can make a sibling call to a function . DECL is the declaration of the function being targeted by the call and EXP is the CALL_EXPR representing the call .


<s> WebAssemblySubtarget & WebAssemblySubtarget :: initializeSubtargetDependencies ( StringRef FS ) { if ( CPUString . empty ( ) ) CPUString = "generic" ; ParseSubtargetFeatures ( CPUString , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

WebAssembly WebAssembly WebAssembly "generic"


<s> const char * thumb1_output_casesi ( rtx * operands ) { rtx diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ 0 ] ) ) ) ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; switch ( GET_MODE ( diff_vec ) ) { case E_QImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi" ) ; case E_HImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi" ) ; case E_SImode : return "bl\t%___gnu_thumb1_case_si" ; default : gcc_unreachable ( ) ; } } </s>

Output a Thumb-1 casesi dispatch sequence .


<s> void AArch64PassConfig :: addPreEmitPass2 ( ) { addPass ( createUnpackMachineBundles ( nullptr ) ) ; } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s>
static
const
char
*
avr_out_lpm_no_lpmx
(
rtx_insn
*
insn
,
rtx
*
xop
,
int
*
plen
)
{
rtx
dest
=
xop
[
0
]
;
rtx
addr
=
xop
[
1
]
;
int
n_bytes
=
GET_MODE_SIZE
(
GET_MODE
(
dest
)
)
;
int
regno_dest
;
regno_dest
=
REGNO
(
dest
)
;
xop
[
3
]
=
lpm_reg_rtx
;
switch
(
GET_CODE
(
addr
)
)
{
default
:
gcc_unreachable
(
)
;
case
REG
:
gcc_assert
(
REG_Z
==
REGNO
(
addr
)
)
;
switch
(
n_bytes
)
{
default
:
gcc_unreachable
(
)
;
case
1
:
avr_asm_len
(
"%4lpm"
,
xop
,
plen
,
1
)
;
if
(
regno_dest
!=
LPM_REGNO
)
avr_asm_len
(
"mov %0,%3"
,
xop
,
plen
,
1
)
;
return
""
;
case
2
:
if
(
REGNO
(
dest
)
==
REG_Z
)
return
avr_asm_len
(
"%4lpm"
CR_TAB
"push %3"
CR_TAB
"adiw %2,1"
CR_TAB
"%4lpm"
CR_TAB
"mov %B0,%3"
CR_TAB
"pop %A0"
,
xop
,
plen
,
6
)
;
avr_asm_len
(
"%4lpm"
CR_TAB
"mov %A0,%3"
CR_TAB
"adiw %2,1"
CR_TAB
"%4lpm"
CR_TAB
"mov %B0,%3"
,
xop
,
plen
,
5
)
;
if
(
!
reg_unused_after
(
insn
,
addr
)
)
avr_asm_len
(
"sbiw %2,1"
,
xop
,
plen
,
1
)
;
break
;
}
break
;
case
POST_INC
:
gcc_assert
(
REG_Z
==
REGNO
(
XEXP
(
addr
,
0
)
)
&&
n_bytes
<=
4
)
;
if
(
regno_dest
==
LPM_REGNO
)
avr_asm_len
(
"%4lpm"
CR_TAB
"adiw %2,1"
,
xop
,
plen
,
2
)
;
else
avr_asm_len
(
"%4lpm"
CR_TAB
"mov %A0,%3"
CR_TAB
"adiw %2,1"
,
xop
,
plen
,
3
)
;
if
(
n_bytes
>=
2
)
avr_asm_len
(
"%4lpm"
CR_TAB
"mov %B0,%3"
CR_TAB
"adiw %2,1"
,
xop
,
plen
,
3
)
;
if
(
n_bytes
>=
3
)
avr_asm_len
(
"%4lpm"
CR_TAB
"mov %C0,%3"
CR_TAB
"adiw %2,1"
,
xop
,
plen
,
3
)
;
if
(
n_bytes
>=
4
)
avr_asm_len
(
"%4lpm"
CR_TAB
"mov %D0,%3"
CR_TAB
"adiw %2,1"
,
xop
,
plen
,
3
)
;
break
;
}
return
""
;
}
</s>

Helper function for the next function in the case where only restricted version of LPM instruction is available .


<s> const XtensaRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool GCNPassConfig :: addPreISel ( ) { AMDGPUPassConfig :: addPreISel ( ) ; addPass ( createAMDGPULateCodeGenPreparePass ( ) ) ; if ( EnableAtomicOptimizations ) { addPass ( createAMDGPUAtomicOptimizerPass ( ) ) ; } addPass ( & AMDGPUUnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) { if ( EnableStructurizerWorkarounds ) { addPass ( createFixIrreduciblePass ( ) ) ; addPass ( createUnifyLoopExitsPass ( ) ) ; } addPass ( createStructurizeCFGPass ( false ) ) ; } addPass ( createSinkingPass ( ) ) ; addPass ( createAMDGPUAnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( createSIAnnotateControlFlowPass ( ) ) ; } addPass ( createLCSSAPass ( ) ) ; return false ; } </s>

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU SI


<s> bool NVPTXDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_m : if ( SelectDirectAddr ( Op , Op0 ) ) { OutOps . push_back ( Op0 ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( 0 , SDLoc ( Op ) , MVT :: i32 ) ) ; return false ; } if ( SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ) { OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = TM . getDataLayout ( ) -> getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < const Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < const Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( 0 , isPPC64 ? 8 : 4 , 0 ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 , 0 ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> virtual ~ SystemZCallingConventionRegisters ( ) { } </s>


<s> void s390_expand_tbegin ( rtx dest , rtx tdb , rtx retry , bool clobber_fprs_p ) { rtx retry_plus_two = gen_reg_rtx ( SImode ) ; rtx retry_reg = gen_reg_rtx ( SImode ) ; rtx_code_label * retry_label = NULL ; if ( retry != NULL_RTX ) { emit_move_insn ( retry_reg , retry ) ; emit_insn ( gen_addsi3 ( retry_plus_two , retry_reg , const2_rtx ) ) ; emit_insn ( gen_addsi3 ( retry_reg , retry_reg , const1_rtx ) ) ; retry_label = gen_label_rtx ( ) ; emit_label ( retry_label ) ; } if ( clobber_fprs_p ) { if ( TARGET_VX ) emit_insn ( gen_tbegin_1_z13 ( gen_rtx_CONST_INT ( VOIDmode , TBEGIN_MASK ) , tdb ) ) ; else emit_insn ( gen_tbegin_1 ( gen_rtx_CONST_INT ( VOIDmode , TBEGIN_MASK ) , tdb ) ) ; } else emit_insn ( gen_tbegin_nofloat_1 ( gen_rtx_CONST_INT ( VOIDmode , TBEGIN_MASK ) , tdb ) ) ; emit_move_insn ( dest , gen_rtx_UNSPEC ( SImode , gen_rtvec ( 1 , gen_rtx_REG ( CCRAWmode , CC_REGNUM ) ) , UNSPEC_CC_TO_INT ) ) ; if ( retry != NULL_RTX ) { const int CC0 = 1 << 3 ; const int CC1 = 1 << 2 ; const int CC3 = 1 << 0 ; rtx jump ; rtx count = gen_reg_rtx ( SImode ) ; rtx_code_label * leave_label = gen_label_rtx ( ) ; jump = s390_emit_jump ( leave_label , gen_rtx_EQ ( VOIDmode , gen_rtx_REG ( CCRAWmode , CC_REGNUM ) , gen_rtx_CONST_INT ( VOIDmode , CC0 | CC1 | CC3 ) ) ) ; LABEL_NUSES ( leave_label ) = 1 ; emit_move_insn ( count , retry_plus_two ) ; emit_insn ( gen_subsi3 ( count , count , retry_reg ) ) ; emit_insn ( gen_tx_assist ( count ) ) ; jump = emit_jump_insn ( gen_doloop_si64 ( retry_label , retry_reg , retry_reg ) ) ; JUMP_LABEL ( jump ) = retry_label ; LABEL_NUSES ( retry_label ) = 1 ; emit_label ( leave_label ) ; } } </s>

Emit rtl for the tbegin or tbegin_retry ( RETRY ! = NULL_RTX ) expanders . DEST - Register location where CC will be stored . TDB - Pointer to a 256 byte area where to store the transaction . diagnostic block . NULL if TDB is not needed . RETRY - Retry count value . If non-NULL a retry loop for CC2 is emitted CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part of the tbegin instruction pattern .


<s>
MCSymbol
*
X86MCInstLower
::
GetSymbolFromOperand
(
const
MachineOperand
&
MO
)
const
{
const
DataLayout
&
DL
=
MF
.
getDataLayout
(
)
;
assert
(
(
MO
.
isGlobal
(
)
||
MO
.
isSymbol
(
)
||
MO
.
isMBB
(
)
)
&&
"Isn't a symbol reference"
)
;
MCSymbol
*
Sym
=
nullptr
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
switch
(
MO
.
getTargetFlags
(
)
)
{
case
X86II
::
MO_DLLIMPORT
:
Name
+=
"__imp_"
;
break
;
case
X86II
::
MO_COFFSTUB
:
Name
+=
".refptr."
;
break
;
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
Suffix
=
"$non_lazy_ptr"
;
break
;
}
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
.
getPrivateGlobalPrefix
(
)
;
if
(
MO
.
isGlobal
(
)
)
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
AsmPrinter
.
getNameWithPrefix
(
Name
,
GV
)
;
}
else
if
(
MO
.
isSymbol
(
)
)
{
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
if
(
MO
.
isMBB
(
)
)
{
assert
(
Suffix
.
empty
(
)
)
;
Sym
=
MO
.
getMBB
(
)
->
getSymbol
(
)
;
}
Name
+=
Suffix
;
if
(
!
Sym
)
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
break
;
case
X86II
::
MO_COFFSTUB
:
{
MachineModuleInfoCOFF
&
MMICOFF
=
MF
.
getMMI
(
)
.
getObjFileInfo
<
MachineModuleInfoCOFF
>
(
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
MMICOFF
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
true
)
;
}
break
;
}
case
X86II
::
MO_DARWIN_NONLAZY
:
case
X86II
::
MO_DARWIN_NONLAZY_PIC_BASE
:
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
)
.
getGVStubEntry
(
Sym
)
;
if
(
!
StubSym
.
getPointer
(
)
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AsmPrinter
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
break
;
}
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s>
unsigned
RV16KMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
Ctx
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
llvm_unreachable
(
"Unhandled expression!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void unicosmk_defer_case_vector ( rtx lab , rtx vec ) { struct machine_function * machine = cfun -> machine ; vec = gen_rtx_EXPR_LIST ( VOIDmode , lab , vec ) ; machine -> addr_list = gen_rtx_EXPR_LIST ( VOIDmode , vec , machine -> addr_list ) ; } </s>

Add a case vector to the current function 's list of deferred case vectors . Case vectors have to be put into a separate section because CAM does not allow data definitions in code sections .


<s> void X86FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const Function * Fn = MF . getFunction ( ) ; if ( ! STI . is64Bit ( ) || ! MF . getMMI ( ) . hasEHFunclets ( ) || classifyEHPersonality ( Fn -> getPersonalityFn ( ) ) != EHPersonality :: MSVC_CXX ) return ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; int64_t MinFixedObjOffset = - SlotSize ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I < 0 ; ++ I ) MinFixedObjOffset = std :: min ( MinFixedObjOffset , MFI -> getObjectOffset ( I ) ) ; for ( WinEHTryBlockMapEntry & TBME : EHInfo . TryBlockMap ) { for ( WinEHHandlerType & H : TBME . HandlerArray ) { int FrameIndex = H . CatchObj . FrameIndex ; if ( FrameIndex != INT_MAX ) { unsigned Align = MFI -> getObjectAlignment ( FrameIndex ) ; MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % Align ; MinFixedObjOffset -= MFI -> getObjectSize ( FrameIndex ) ; MFI -> setObjectOffset ( FrameIndex , MinFixedObjOffset ) ; } } } MinFixedObjOffset -= std :: abs ( MinFixedObjOffset ) % 8 ; int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize ; int UnwindHelpFI = MFI -> CreateFixedObject ( SlotSize , UnwindHelpOffset , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; addFrameReference ( BuildMI ( MBB , MBBI , DL , TII . get ( X86 :: MOV64mi32 ) ) , UnwindHelpFI ) . addImm ( - 2 ) ; } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s>
bool
TL45AsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
if
(
MatchInstructionImpl
(
Operands
,
Inst
,
ErrorInfo
,
MatchingInlineAsm
)
)
{
Out
.
EmitInstruction
(
Inst
,
this
->
STI
)
;
return
false
;
}
else
{
return
Error
(
IDLoc
,
"Error Parsing Instruction"
)
;
}
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> static int find_unused_clobbered_reg ( ) { int i ; for ( i = 0 ; i < 6 ; i ++ ) if ( ! regs_ever_live [ i ] ) return i ; return 0 ; } </s>

Find first call clobbered register unsused in a function . This could be used as base register in a leaf function or for holding the return address before epilogue .


<s> bool ix86_function_value_regno_p ( int regno ) { if ( regno == 0 || ( regno == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387 ) || ( regno == FIRST_SSE_REG && TARGET_SSE ) ) return true ; if ( ! TARGET_64BIT && ( regno == FIRST_MMX_REG && TARGET_MMX ) ) return true ; return false ; } </s>

Return true if N is a possible register number of function value .


<s> int m32c_function_arg_regno_p ( int r ) { if ( TARGET_A24 ) return ( r == R0_REGNO ) ; return ( r == R1_REGNO || r == R2_REGNO ) ; } </s>


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return ScalarizeVectorLoad ( Op , DAG ) ; LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT PtrVT = BasePtr . getValueType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; MachinePointerInfo SrcValue ( Load -> getMemOperand ( ) -> getValue ( ) ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; SDValue Ops [ ] = { DAG . getNode ( ISD :: CONCAT_VECTORS , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoLoad . getValue ( 1 ) , HiLoad . getValue ( 1 ) ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> static unsigned adjust_vectorization_cost ( enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info ) { if ( kind == scalar_stmt && stmt_info && stmt_info -> stmt && gimple_code ( stmt_info -> stmt ) == GIMPLE_ASSIGN ) { tree_code subcode = gimple_assign_rhs_code ( stmt_info -> stmt ) ; if ( subcode == COND_EXPR ) return 2 ; } return 0 ; } </s>

Adjust vectorization cost after calling rs6000_builtin_vectorization_cost . For some statement , we would like to further fine-grain tweak the cost on top of rs6000_builtin_vectorization_cost handling which does n't have any information on statement operation codes etc . One typical case here is COND_EXPR , it takes the same cost to simple FXU instruction when evaluating for scalar cost , but it should be priced more whatever transformed to either compare + branch or compare + isel instructions .


<s> bool HexagonDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Inp = Op , Res ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_v : case InlineAsm :: Constraint_m : if ( SelectAddrFI ( Inp , Res ) ) OutOps . push_back ( Res ) ; else OutOps . push_back ( Inp ) ; break ; } OutOps . push_back ( CurDAG -> getTargetConstant ( 0 , SDLoc ( Op ) , MVT :: i32 ) ) ; return false ; } </s>


<s> bool ARM64PassConfig :: addPostRegAlloc ( ) { if ( EnableDeadRegisterElimination ) addPass ( createARM64DeadRegisterDefinitions ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> void printPCRelImm ( const MCInst * MI , int opNum , raw_ostream & O ) { printOperand ( MI , opNum , O ) ; } </s>


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM::tRestore
0


<s> void m32c_register_pragmas ( void ) { c_register_pragma ( "GCC" , "memregs" , m32c_pragma_memregs ) ; } </s>


<s>
void
SIFrameLowering
::
determineCalleeSaves
(
MachineFunction
&
MF
,
BitVector
&
SavedVGPRs
,
RegScavenger
*
RS
)
const
{
TargetFrameLowering
::
determineCalleeSaves
(
MF
,
SavedVGPRs
,
RS
)
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
if
(
MFI
->
isEntryFunction
(
)
)
return
;
MachineFrameInfo
&
FrameInfo
=
MF
.
getFrameInfo
(
)
;
const
GCNSubtarget
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
SavedVGPRs
.
clearBitsNotInMask
(
TRI
->
getAllVectorRegMask
(
)
)
;
if
(
!
ST
.
hasGFX90AInsts
(
)
)
SavedVGPRs
.
clearBitsInMask
(
TRI
->
getAllAGPRRegMask
(
)
)
;
if
(
TRI
->
isCFISavedRegsSpillEnabled
(
)
)
{
allocateCFISave
(
MF
,
MFI
->
ReturnAddressSaveIndex
,
TRI
->
getReturnAddressReg
(
MF
)
)
;
allocateCFISave
(
MF
,
MFI
->
EXECSaveIndex
,
ST
.
isWave32
(
)
AMDGPU
::
EXEC_LO
:
AMDGPU
::
EXEC
)
;
}
const
bool
WillHaveFP
=
FrameInfo
.
hasCalls
(
)
&&
(
SavedVGPRs
.
any
(
)
||
!
allStackObjectsAreDead
(
MF
)
)
;
for
(
auto
SSpill
:
MFI
->
getSGPRSpillVGPRs
(
)
)
SavedVGPRs
.
reset
(
SSpill
.
VGPR
)
;
LivePhysRegs
LiveRegs
;
LiveRegs
.
init
(
*
TRI
)
;
if
(
WillHaveFP
||
hasFP
(
MF
)
)
{
assert
(
!
MFI
->
SGPRForFPSaveRestoreCopy
&&
!
MFI
->
FramePointerSaveIndex
&&
"Re-reserving spill slot for FP"
)
;
getVGPRSpillLaneOrTempRegister
(
MF
,
LiveRegs
,
MFI
->
SGPRForFPSaveRestoreCopy
,
MFI
->
FramePointerSaveIndex
,
true
)
;
}
if
(
TRI
->
hasBasePointer
(
MF
)
)
{
if
(
MFI
->
SGPRForFPSaveRestoreCopy
)
LiveRegs
.
addReg
(
MFI
->
SGPRForFPSaveRestoreCopy
)
;
assert
(
!
MFI
->
SGPRForBPSaveRestoreCopy
&&
!
MFI
->
BasePointerSaveIndex
&&
"Re-reserving spill slot for BP"
)
;
getVGPRSpillLaneOrTempRegister
(
MF
,
LiveRegs
,
MFI
->
SGPRForBPSaveRestoreCopy
,
MFI
->
BasePointerSaveIndex
,
false
)
;
}
}
</s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .

AMDGPU
SI
SI
SI
SI
AMDGPU::EXEC_LO
AMDGPU::EXEC
"Re-reserving spill slot for FP"
"Re-reserving spill slot for BP"


<s> bool sh_expand_strlen ( rtx * operands ) { rtx addr1 = operands [ 1 ] ; rtx current_addr = copy_addr_to_reg ( XEXP ( addr1 , 0 ) ) ; rtx start_addr = gen_reg_rtx ( Pmode ) ; rtx tmp0 = gen_reg_rtx ( SImode ) ; rtx tmp1 = gen_reg_rtx ( SImode ) ; rtx_code_label * L_return = gen_label_rtx ( ) ; rtx_code_label * L_loop_byte = gen_label_rtx ( ) ; rtx_insn * jump ; rtx_code_label * L_loop_long = gen_label_rtx ( ) ; rtx_code_label * L_end_loop_long = gen_label_rtx ( ) ; int align = INTVAL ( operands [ 3 ] ) ; emit_move_insn ( operands [ 0 ] , GEN_INT ( - 1 ) ) ; emit_move_insn ( start_addr , current_addr ) ; if ( align < 4 ) { emit_insn ( gen_tstsi_t ( current_addr , GEN_INT ( 3 ) ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_move_insn ( tmp0 , operands [ 2 ] ) ; addr1 = adjust_automodify_address ( addr1 , SImode , current_addr , 0 ) ; emit_label ( L_loop_long ) ; emit_move_insn ( tmp1 , addr1 ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 4 ) ) ; emit_insn ( gen_cmpstr_t ( tmp0 , tmp1 ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_long ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_end_loop_long ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , - 4 ) ) ; addr1 = adjust_address ( addr1 , QImode , 0 ) ; for ( int i = 0 ; i < 4 ; ++ i ) { emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 1 ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_true ( L_return ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; } emit_barrier_after ( jump ) ; emit_label ( L_loop_byte ) ; emit_insn ( gen_extendqisi2 ( tmp1 , addr1 ) ) ; emit_move_insn ( current_addr , plus_constant ( Pmode , current_addr , 1 ) ) ; emit_insn ( gen_cmpeqsi_t ( tmp1 , const0_rtx ) ) ; jump = emit_jump_insn ( gen_branch_false ( L_loop_byte ) ) ; add_int_reg_note ( jump , REG_BR_PROB , prob_likely ) ; emit_label ( L_return ) ; emit_insn ( gen_addsi3 ( start_addr , start_addr , GEN_INT ( 1 ) ) ) ; emit_insn ( gen_subsi3 ( operands [ 0 ] , current_addr , start_addr ) ) ; return true ; } </s>

Emit code to perform a strlen . OPERANDS [ 0 ] is the destination . OPERANDS [ 1 ] is the string . OPERANDS [ 2 ] is the char to search . OPERANDS [ 3 ] is the alignment .


"instruction use requires an option to be enabled"


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> static reg_class_t visium_secondary_reload ( bool in_p ATTRIBUTE_UNUSED , rtx x , reg_class_t rclass , machine_mode mode ATTRIBUTE_UNUSED , secondary_reload_info * sri ATTRIBUTE_UNUSED ) { int regno = true_regnum ( x ) ; if ( regno == - 1 && ( rclass == MDB || rclass == MDC || rclass == FP_REGS ) ) return GENERAL_REGS ; else if ( ( ( regno == R_MDB || regno == R_MDC ) && rclass == FP_REGS ) || ( FP_REGISTER_P ( regno ) && ( rclass == MDB || rclass == MDC ) ) ) return GENERAL_REGS ; else if ( ( regno == R_MDB && rclass == MDC ) || ( rclass == MDB && regno == R_MDC ) ) return GENERAL_REGS ; return NO_REGS ; } </s>

Return the register class required for an intermediate register used to copy a register of RCLASS from/to X . If no such intermediate register is required , return NO_REGS . If more than one such intermediate register is required , describe the one that is closest in the copy chain to the reload register .


"Expected SVE area to be calculated by this point"

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> unsigned HexagonTTIImpl :: getNumberOfRegisters ( bool vector ) const { return vector ? 0 : 32 ; } </s>


<s> BitVector rvexRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const uint16_t ReservedCPURegs [ ] = { rvex :: R0 , rvex :: R1 , rvex :: LR , rvex :: PC } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; if ( MF . getInfo < rvexFunctionInfo > ( ) -> globalBaseRegFixed ( ) ) { Reserved . set ( rvex :: R0 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
static
bool
class_can_hold_mode
(
reg_class_t
rclass
,
machine_mode
mode
)
{
static
char
results
[
LIM_REG_CLASSES
]
[
MAX_MACHINE_MODE
]
;
if
(
results
[
(
int
)
rclass
]
[
mode
]
==
0
)
{
int
r
;
results
[
rclass
]
[
mode
]
=
1
;
for
(
r
=
0
;
r
<
FIRST_PSEUDO_REGISTER
;
r
++
)
if
(
in_hard_reg_set_p
(
reg_class_contents
[
(
int
)
rclass
]
,
mode
,
r
)
&&
HARD_REGNO_MODE_OK
(
r
,
mode
)
)
{
results
[
rclass
]
[
mode
]
=
2
;
break
;
}
}
fprintf
(
stderr
,
"class %s can hold %s? %s\n"
,
class_names
[
(
int
)
rclass
]
,
mode_name
[
mode
]
,
(
results
[
rclass
]
[
mode
]
==
2
)
"yes"
:
"no"
)
;
return
results
[
(
int
)
rclass
]
[
mode
]
==
2
;
}
</s>

Used by m32c_register_move_cost to determine if a move is impossibly expensive .


<s>
bool
MCS51FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
ArrayRef
<
CalleeSavedInfo
>
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
unsigned
CalleeFrameSize
=
0
;
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
MCS51Subtarget
&
STI
=
MF
.
getSubtarget
<
MCS51Subtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
MCS51MachineFunctionInfo
*
MCS51FI
=
MF
.
getInfo
<
MCS51MachineFunctionInfo
>
(
)
;
for
(
unsigned
i
=
CSI
.
size
(
)
;
i
!=
0
;
i
)
{
unsigned
Reg
=
CSI
[
i
1
]
.
getReg
(
)
;
bool
IsNotLiveIn
=
!
MBB
.
isLiveIn
(
Reg
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
8
&&
"Invalid register size"
)
;
if
(
IsNotLiveIn
)
{
MBB
.
addLiveIn
(
Reg
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
MCS51
::
PUSHRr
)
)
.
addReg
(
Reg
,
getKillRegState
(
IsNotLiveIn
)
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
++
CalleeFrameSize
;
}
MCS51FI
->
setCalleeSavedFrameSize
(
CalleeFrameSize
)
;
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static int arm_legitimate_index_p ( enum machine_mode mode , rtx index , RTX_CODE outer , int strict_p ) { HOST_WIDE_INT range ; enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && ( TARGET_FPA || TARGET_MAVERICK ) && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || ( TARGET_MAVERICK && mode == DImode ) ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; if ( TARGET_LDRD ) return val > - 256 && val < 256 ; else return val > - 4096 && val < 4092 ; } return TARGET_LDRD && arm_address_register_rtx_p ( index , strict_p ) ; } if ( GET_MODE_SIZE ( mode ) <= 4 && ! ( arm_arch4 && ( mode == HImode || ( mode == QImode && outer == SIGN_EXTEND ) ) ) ) { if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && power_of_two_operand ( xiop1 , SImode ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && power_of_two_operand ( xiop0 , SImode ) ) ) ; } else if ( code == LSHIFTRT || code == ASHIFTRT || code == ASHIFT || code == ROTATERT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && GET_CODE ( op ) == CONST_INT && INTVAL ( op ) > 0 && INTVAL ( op ) <= 31 ) ; } } if ( arm_arch4 ) { if ( mode == HImode || ( outer == SIGN_EXTEND && mode == QImode ) ) range = 256 ; else range = 4096 ; } else range = ( mode == HImode ) ? 4095 : 4096 ; return ( code == CONST_INT && INTVAL ( index ) < range && INTVAL ( index ) > - range ) ; } </s>

Return nonzero if INDEX is valid for an address index operand in ARM state .


<s> void setName ( StringRef N ) { Impl -> setName ( N ) ; } </s>

Change the name of this type to the specified name , or to a name with a suffix if there is a collision .


<s> static void AnalyzeArguments ( CCState & State , SmallVectorImpl < CCValAssign > & ArgLocs , const SmallVectorImpl < ArgT > & Args ) { static const MCPhysReg RegList [ ] = { MSP430 :: R15 , MSP430 :: R14 , MSP430 :: R13 , MSP430 :: R12 } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; if ( State . isVarArg ( ) ) { AnalyzeVarArgs ( State , Args ) ; return ; } SmallVector < unsigned , 4 > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; ISD :: ArgFlagsTy ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( LocVT == MVT :: i8 ) { LocVT = MVT :: i16 ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 2 , 2 , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <= RegsLeft ) { unsigned FirstVal = ValNo ; for ( unsigned j = 0 ; j < Parts ; j ++ ) { unsigned Reg = State . AllocateReg ( RegList , NbRegs ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -- ; } SmallVectorImpl < CCValAssign > :: iterator B = ArgLocs . begin ( ) + FirstVal ; std :: reverse ( B , B + Parts ) ; } else { UseStack = true ; for ( unsigned j = 0 ; j < Parts ; j ++ ) CC_MSP430_AssignStack ( ValNo ++ , ArgVT , LocVT , LocInfo , ArgFlags , State ) ; } } } </s>

The function will invoke AnalyzeCallOperands .


<s> int arm_max_const_double_inline_cost ( ) { if ( arm_disable_literal_pool ) return 99 ; return ( ( optimize_size || arm_ld_sched ) ? 3 : 4 ) ; } </s>

Return maximum allowed cost of synthesizing a 64-bit constant VAL inline . Returns the number of insns needed , or 99 if we always want to synthesize the value .


<s>
SDValue
BPFTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
if
(
Ins
.
size
(
)
>=
2
)
{
fail
(
DL
,
DAG
,
"only small returns supported"
)
;
}
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_BPF64
)
;
for
(
auto
&
Val
:
RVLocs
)
{
Chain
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
Val
.
getLocReg
(
)
,
Val
.
getValVT
(
)
,
InFlag
)
.
getValue
(
1
)
;
InFlag
=
Chain
.
getValue
(
2
)
;
InVals
.
push_back
(
Chain
.
getValue
(
0
)
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
bool
JVMInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
MachineOperand
&
MO
=
Cond
[
0
]
;
unsigned
NewCond
;
switch
(
MO
.
getImm
(
)
)
{
default
:
llvm_unreachable
(
"Unhandled conditon"
)
;
case
JVM
::
IFICMPEQ
:
NewCond
=
JVM
::
IFICMPNE
;
break
;
case
JVM
::
IFICMPNE
:
NewCond
=
JVM
::
IFICMPEQ
;
break
;
case
JVM
::
IFICMPGT
:
NewCond
=
JVM
::
IFICMPLE
;
break
;
case
JVM
::
IFICMPGE
:
NewCond
=
JVM
::
IFICMPLT
;
break
;
case
JVM
::
IFICMPLT
:
NewCond
=
JVM
::
IFICMPGE
;
break
;
case
JVM
::
IFICMPLE
:
NewCond
=
JVM
::
IFICMPGT
;
break
;
case
JVM
::
IFEQ
:
NewCond
=
JVM
::
IFNE
;
break
;
case
JVM
::
IFGT
:
NewCond
=
JVM
::
IFLE
;
break
;
case
JVM
::
IFGE
:
NewCond
=
JVM
::
IFLT
;
break
;
case
JVM
::
IFLT
:
NewCond
=
JVM
::
IFGE
;
break
;
case
JVM
::
IFLE
:
NewCond
=
JVM
::
IFGT
;
break
;
case
JVM
::
IFNE
:
NewCond
=
JVM
::
IFEQ
;
break
;
}
Cond
[
0
]
.
setImm
(
NewCond
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .

JVM
JVM
0
"Unhandled conditon"
JVM::IFICMPEQ
JVM::IFICMPNE
JVM::IFICMPNE
JVM::IFICMPEQ
JVM::IFICMPGT
JVM::IFICMPLE
JVM::IFICMPGE
JVM::IFICMPLT
JVM::IFICMPLT
JVM::IFICMPGE
JVM::IFICMPLE
JVM::IFICMPGT
JVM::IFEQ
JVM::IFNE
JVM::IFGT
JVM::IFLE
JVM::IFGE
JVM::IFLT
JVM::IFLT
JVM::IFGE
JVM::IFLE
JVM::IFGT
JVM::IFNE
JVM::IFEQ
0


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isReleaseOrStronger ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall ( Strex , { Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> void AMDGPURegisterBankInfo :: split64BitValueForMapping ( MachineIRBuilder & B , SmallVector < unsigned , 2 > & Regs , LLT HalfTy , unsigned Reg ) const { assert ( HalfTy . getSizeInBits ( ) == 32 ) ; MachineRegisterInfo * MRI = B . getMRI ( ) ; unsigned LoLHS = MRI -> createGenericVirtualRegister ( HalfTy ) ; unsigned HiLHS = MRI -> createGenericVirtualRegister ( HalfTy ) ; const RegisterBank * Bank = getRegBank ( Reg , * MRI , * TRI ) ; MRI -> setRegBank ( LoLHS , * Bank ) ; MRI -> setRegBank ( HiLHS , * Bank ) ; Regs . push_back ( LoLHS ) ; Regs . push_back ( HiLHS ) ; B . buildInstr ( AMDGPU :: G_UNMERGE_VALUES ) . addDef ( LoLHS ) . addDef ( HiLHS ) . addUse ( Reg ) ; } </s>

Split 64-bit value Reg into two 32-bit halves and populate them into Regs .