<s> static void emit_soft_tfmode_libcall ( const char * func_name , int nargs , rtx * operands ) { rtx ret_slot = NULL , arg [ 3 ] , func_sym ; int i ; gcc_assert ( nargs == 2 || nargs == 3 ) ; for ( i = 0 ; i < nargs ; ++ i ) { rtx this_arg = operands [ i ] ; rtx this_slot ; if ( GET_MODE ( this_arg ) == TFmode ) { int force_stack_temp ; force_stack_temp = 0 ; if ( TARGET_BUGGY_QP_LIB && i == 0 ) force_stack_temp = 1 ; if ( GET_CODE ( this_arg ) == MEM && ! force_stack_temp ) this_arg = XEXP ( this_arg , 0 ) ; else if ( CONSTANT_P ( this_arg ) && ! force_stack_temp ) { this_slot = force_const_mem ( TFmode , this_arg ) ; this_arg = XEXP ( this_slot , 0 ) ; } else { this_slot = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) , 0 ) ; if ( i > 0 ) emit_move_insn ( this_slot , this_arg ) ; else ret_slot = this_slot ; this_arg = XEXP ( this_slot , 0 ) ; } } arg [ i ] = this_arg ; } func_sym = gen_rtx_SYMBOL_REF ( Pmode , func_name ) ; if ( GET_MODE ( operands [ 0 ] ) == TFmode ) { if ( nargs == 2 ) emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , 2 , arg [ 0 ] , GET_MODE ( arg [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) ) ; else emit_library_call ( func_sym , LCT_NORMAL , VOIDmode , 3 , arg [ 0 ] , GET_MODE ( arg [ 0 ] ) , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) , arg [ 2 ] , GET_MODE ( arg [ 2 ] ) ) ; if ( ret_slot ) emit_move_insn ( operands [ 0 ] , ret_slot ) ; } else { rtx ret ; gcc_assert ( nargs == 2 ) ; ret = emit_library_call_value ( func_sym , operands [ 0 ] , LCT_NORMAL , GET_MODE ( operands [ 0 ] ) , 1 , arg [ 1 ] , GET_MODE ( arg [ 1 ] ) ) ; if ( ret != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , ret ) ; } } </s>

Generate a call to FUNC with OPERANDS . Operand 0 is the return value . Unlike normal calls , TFmode operands are passed by reference . It is assumed that no more than 3 operands are required .


<s> static unsigned s390_loop_unroll_adjust ( unsigned nunroll , struct loop * loop ) { basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = 0 ; if ( s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196 && s390_tune != PROCESSOR_2827_ZEC12 ) return nunroll ; bbs = get_loop_body ( loop ) ; subrtx_iterator :: array_type array ; for ( i = 0 ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( INSN_P ( insn ) && INSN_CODE ( insn ) != - 1 ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( MEM_P ( * iter ) ) mem_count += 1 ; free ( bbs ) ; if ( mem_count == 0 ) return nunroll ; switch ( loop_depth ( loop ) ) { case 1 : return MIN ( nunroll , 28 / mem_count ) ; case 2 : return MIN ( nunroll , 22 / mem_count ) ; default : return MIN ( nunroll , 16 / mem_count ) ; } } </s>

This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates a new number struct loop * loop should be unrolled if tuned for cpus with a built-in stride prefetcher . The loop is analyzed for memory accesses by calling check_dpu for each rtx of the loop . Depending on the loop_depth and the amount of memory accesses a new number < =nunroll is returned to improve the behaviour of the hardware prefetch unit .


<s> int m68k_sched_indexed_address_bypass_p ( rtx_insn * pro , rtx_insn * con ) { gcc_assert ( sched_cfv4_bypass_data . pro == NULL && sched_cfv4_bypass_data . con == NULL && sched_cfv4_bypass_data . scale == 0 ) ; switch ( sched_get_indexed_address_scale ( pro , con ) ) { case 1 : sched_cfv4_bypass_data . pro = pro ; sched_cfv4_bypass_data . con = con ; sched_cfv4_bypass_data . scale = 1 ; return 0 ; case 2 : case 4 : return 1 ; default : return 0 ; } } </s>

Return non-zero if PRO modifies register used as index with scale 2 or 4 in CON .


"getRegForInlineAsmConstraint Unhandled data type"

Given a physical register constraint ( e.g .


<s> AArch64PLT1 * AArch64PLT :: create ( ) { AArch64PLT1 * plt1_entry = new ( std :: nothrow ) AArch64PLT1 ( * m_pSectionData ) ; if ( ! plt1_entry ) fatal ( diag :: fail_allocate_memory_plt ) ; return plt1_entry ; } </s>


<s> bool SystemZTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( UseSoftFloat || ( VT != MVT :: f32 && VT != MVT :: f64 ) ) return false ; return Imm . isZero ( ) || Imm . isNegZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> int m68hc11_small_indexed_indirect_p ( rtx operand , enum machine_mode mode ) { rtx base , offset ; int addr_mode ; if ( GET_CODE ( operand ) == REG && reload_in_progress && REGNO ( operand ) >= FIRST_PSEUDO_REGISTER && reg_equiv_memory_loc [ REGNO ( operand ) ] ) { operand = reg_equiv_memory_loc [ REGNO ( operand ) ] ; operand = eliminate_regs ( operand , 0 , NULL_RTX ) ; } if ( GET_CODE ( operand ) != MEM ) return 0 ; operand = XEXP ( operand , 0 ) ; if ( CONSTANT_ADDRESS_P ( operand ) ) return 1 ; if ( PUSH_POP_ADDRESS_P ( operand ) ) return 1 ; addr_mode = m68hc11_mov_addr_mode | ( reload_completed ? ADDR_STRICT : 0 ) ; if ( ! m68hc11_valid_addressing_p ( operand , mode , addr_mode ) ) return 0 ; if ( TARGET_M6812 && GET_CODE ( operand ) == PLUS && ( reload_completed | reload_in_progress ) ) { base = XEXP ( operand , 0 ) ; offset = XEXP ( operand , 1 ) ; if ( GET_CODE ( base ) != CONST_INT && GET_CODE ( offset ) != CONST_INT ) return 0 ; if ( GET_CODE ( base ) == CONST_INT ) offset = base ; switch ( GET_MODE_SIZE ( mode ) ) { case 8 : if ( INTVAL ( offset ) < - 16 + 6 || INTVAL ( offset ) > 15 - 6 ) return 0 ; break ; case 4 : if ( INTVAL ( offset ) < - 16 + 2 || INTVAL ( offset ) > 15 - 2 ) return 0 ; break ; default : if ( INTVAL ( offset ) < - 16 || INTVAL ( offset ) > 15 ) return 0 ; break ; } } return 1 ; } </s>

Returns 1 if the operand fits in a 68HC11 indirect mode or in a 68HC12 1-byte index addressing mode .


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
TSchedModel
.
init
(
STI
.
getSchedModel
(
)
,
&
STI
,
TII
)
;
if
(
ForceMemOperand
)
{
CmovGroups
AllCmovGroups
;
SmallVector
<
MachineBasicBlock
*
,
4
>
Blocks
;
for
(
auto
&
MBB
:
MF
)
Blocks
.
push_back
(
&
MBB
)
;
if
(
collectCmovCandidates
(
Blocks
,
AllCmovGroups
,
true
)
)
{
for
(
auto
&
Group
:
AllCmovGroups
)
{
if
(
!
llvm
::
any_of
(
Group
,
[
&
]
(
MachineInstr
*
I
)
{
return
I
->
mayLoad
(
)
;
}
)
)
continue
;
Changed
=
true
;
convertCmovInstsToBranches
(
Group
)
;
}
}
}
SmallVector
<
MachineLoop
*
,
4
>
Loops
(
MLI
.
begin
(
)
,
MLI
.
end
(
)
)
;
for
(
int
i
=
0
;
i
<
(
int
)
Loops
.
size
(
)
;
++
i
)
for
(
MachineLoop
*
Child
:
Loops
[
i
]
->
getSubLoops
(
)
)
Loops
.
push_back
(
Child
)
;
for
(
MachineLoop
*
CurrLoop
:
Loops
)
{
if
(
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
->
getBlocks
(
)
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


"value of %<-mfixed-range%> must have form REG1-REG2"

Parse the -mfixed-range= option string .


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::VASTART ISD::FCOPYSIGN ISD::FRAMEADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE


<s>
bool
MipsAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ParseInstruction\n"
)
;
getTargetStreamer
(
)
.
forbidModuleDirective
(
)
;
if
(
!
mnemonicIsValid
(
Name
,
0
)
)
{
return
Error
(
NameLoc
,
"unknown instruction"
)
;
}
Operands
.
push_back
(
MipsOperand
::
CreateToken
(
Name
,
NameLoc
,
*
this
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
&&
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
if
(
getLexer
(
)
.
is
(
AsmToken
::
LBrac
)
)
{
if
(
parseBracketSuffix
(
Name
,
Operands
)
)
return
true
;
}
else
if
(
getLexer
(
)
.
is
(
AsmToken
::
LParen
)
&&
parseParenSuffix
(
Name
,
Operands
)
)
return
true
;
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token in argument list"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

Mips
Mips
"ParseInstruction\n"
0
"unknown instruction"
MipsOperand::CreateToken
"unexpected token in argument list"
"unexpected token in argument list"
"unexpected token in argument list"


<s> void RISCVPassConfig :: addPreRegAlloc ( ) { addPass ( createRISCVMergeBaseOffsetOptPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


"extern const void *const __offload_funcs_end[];\n"

"extern const void *const __offload_vars_end[];\n\n"

"const void *const __offload_func_table[0]\n"

"__attribute__ ((__used__, visibility (\"hidden\"),\n"

"section (\".gnu.offload_funcs\"))) = { };\n\n"

"const void *const __offload_var_table[0]\n"

"section (\".gnu.offload_vars\"))) = { };\n\n"

"const void *const __OFFLOAD_TARGET_TABLE__[]\n"

"__attribute__ ((__used__, visibility (\"hidden\"))) = {\n"

"  &__offload_func_table, &__offload_funcs_end,\n"

"  &__offload_var_table, &__offload_vars_end\n"

"void target_register_lib (const void *);\n\n"

"  target_register_lib (__OFFLOAD_TARGET_TABLE__);\n"

Generates object file with the descriptor for the target library .


<s>
static
HOST_WIDE_INT
rs6000_disable_incompatible_switches
(
void
)
{
HOST_WIDE_INT
ignore_masks
=
rs6000_isa_flags_explicit
;
size_t
i
,
j
;
static
const
struct
{
const
HOST_WIDE_INT
no_flag
;
const
HOST_WIDE_INT
dep_flags
;
const
char
*
const
name
;
}
flags
[
]
=
{
{
OPTION_MASK_P9_VECTOR
,
OTHER_P9_VECTOR_MASKS
,
"power9-vector"
}
,
{
OPTION_MASK_P8_VECTOR
,
OTHER_P8_VECTOR_MASKS
,
"power8-vector"
}
,
{
OPTION_MASK_VSX
,
OTHER_VSX_VECTOR_MASKS
,
"vsx"
}
,
}
;
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
flags
)
;
i
++
)
{
HOST_WIDE_INT
no_flag
=
flags
[
i
]
.
no_flag
;
if
(
(
rs6000_isa_flags
&
no_flag
)
==
0
&&
(
rs6000_isa_flags_explicit
&
no_flag
)
!=
0
)
{
HOST_WIDE_INT
dep_flags
=
flags
[
i
]
.
dep_flags
;
HOST_WIDE_INT
set_flags
=
(
rs6000_isa_flags_explicit
&
rs6000_isa_flags
&
dep_flags
)
;
if
(
set_flags
)
{
for
(
j
=
0
;
j
<
ARRAY_SIZE
(
rs6000_opt_masks
)
;
j
++
)
if
(
(
set_flags
&
rs6000_opt_masks
[
j
]
.
mask
)
!=
0
)
{
set_flags
&=
~
rs6000_opt_masks
[
j
]
.
mask
;
error
(
"%<-mno-%s%> turns off %<-m%s%>"
,
flags
[
i
]
.
name
,
rs6000_opt_masks
[
j
]
.
name
)
;
}
gcc_assert
(
!
set_flags
)
;
}
rs6000_isa_flags
&=
~
dep_flags
;
ignore_masks
|=
no_flag
|
dep_flags
;
}
}
return
ignore_masks
;
}
</s>

If the user used -mno-vsx , we need turn off all of the implicit ISA 2.06 , 2.07 , and 3.0 options that relate to the vector unit ( -mdirect-move , -mupper-regs-df , etc. ) . If the user used -mno-power8-vector , we need to turn off all of the implicit ISA 2.07 and 3.0 options that relate to the vector unit . If the user used -mno-power9-vector , we need to turn off all of the implicit ISA 3.0 options that relate to the vector unit . This function does not handle explicit options such as the user specifying -mdirect-move . These are handled in rs6000_option_override_internal , and the appropriate error is given if needed . We return a mask of all of the implicit options that should not be enabled by default .


<s> bool X86InstrInfo :: canInsertSelect ( const MachineBasicBlock & MBB , ArrayRef < MachineOperand > Cond , Register DstReg , Register TrueReg , Register FalseReg , int & CondCycles , int & TrueCycles , int & FalseCycles ) const { if ( ! Subtarget . hasCMov ( ) ) return false ; if ( Cond . size ( ) != 1 ) return false ; if ( ( X86 :: CondCode ) Cond [ 0 ] . getImm ( ) > X86 :: LAST_VALID_COND ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( X86 :: GR16RegClass . hasSubClassEq ( RC ) || X86 :: GR32RegClass . hasSubClassEq ( RC ) || X86 :: GR64RegClass . hasSubClassEq ( RC ) ) { CondCycles = 2 ; TrueCycles = 2 ; FalseCycles = 2 ; return true ; } return false ; } </s>

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond .


<s> MCInst const & getDesc ( ) const { return * ID ; } </s>

Returns the target instruction descriptor of this MachineInstr .


<s> bool GBZ80InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AliasAnalysis * AI ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case GB :: LD_r_n : case GB :: LD_dd_nn : return true ; } } </s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> int first_reg_to_save ( void ) { int first_reg ; for ( first_reg = 13 ; first_reg <= 31 ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; if ( first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic != 0 ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) && df_regs_ever_live_p ( RS6000_PIC_OFFSET_TABLE_REGNUM ) ) first_reg = RS6000_PIC_OFFSET_TABLE_REGNUM ; if ( flag_pic && crtl -> uses_pic_offset_table && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM ) return RS6000_PIC_OFFSET_TABLE_REGNUM ; return first_reg ; } </s>

Return the first register that is required to be saved . 16 if none .


The guts of ix86_expand_vec_perm_const , also used by the ok hook . With all of the interface bits taken care of , perform the expansion in D and return true on success .


<s> static bool mips_save_reg_p ( unsigned int regno ) { if ( regno == GLOBAL_POINTER_REGNUM ) return ( TARGET_ABICALLS && TARGET_NEWABI && cfun -> machine -> global_pointer == regno ) ; if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == GP_REG_FIRST + 31 && regs_ever_live [ regno ] ) return true ; if ( TARGET_MIPS16 ) { tree return_type ; return_type = DECL_RESULT ( current_function_decl ) ; if ( regno == GP_REG_FIRST + 18 && regs_ever_live [ regno ] ) return true ; if ( regno == GP_REG_FIRST + 31 && mips16_hard_float && ! aggregate_value_p ( return_type , current_function_decl ) && GET_MODE_CLASS ( DECL_MODE ( return_type ) ) == MODE_FLOAT && GET_MODE_SIZE ( DECL_MODE ( return_type ) ) <= UNITS_PER_FPVALUE ) return true ; } return false ; } </s>

Return true if the current function must save REGNO .


<s> void X86FrameLowering :: orderFrameObjects ( const MachineFunction & MF , SmallVectorImpl < int > & ObjectsToAllocate ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ObjectsToAllocate . empty ( ) ) return ; std :: vector < X86FrameSortingObject > SortingObjects ( MFI . getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI . getObjectAlignment ( Obj ) ; int ObjectSize = MFI . getObjectSize ( Obj ) ; if ( ObjectSize == 0 ) SortingObjects [ Obj ] . ObjectSize = 4 ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugValue ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= 0 && Index < MFI . getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , X86FrameSortingComparator ( ) ) ; int i = 0 ; for ( auto & Obj : SortingObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } if ( ! TRI -> needsStackRealignment ( MF ) && hasFP ( MF ) ) std :: reverse ( ObjectsToAllocate . begin ( ) , ObjectsToAllocate . end ( ) ) ; } </s>


<s> static inline int avr_outgoing_args_size ( void ) { return ( ACCUMULATE_OUTGOING_ARGS ? ( HOST_WIDE_INT ) crtl -> outgoing_args_size : 0 ) ; } </s>

Report contribution of accumulated outgoing arguments to stack size .


<s> static machine_mode ix86_c_mode_for_suffix ( char suffix ) { if ( suffix == 'q' ) return TFmode ; if ( suffix == 'w' ) return XFmode ; return VOIDmode ; } </s>


<s> DecodeStatus XtensaDisassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { Size = 0 ; size_t MinInstructionSize = 2 ; if ( Bytes . size ( ) < MinInstructionSize ) return Fail ; uint8_t firstByte = reinterpret_cast < const uint8_t * > ( Bytes . data ( ) ) [ 0 ] ; if ( firstByte & 8 ) { Size = 2 ; } else { if ( Bytes . size ( ) < 3 ) return Fail ; Size = 3 ; } uint32_t Insn { 0 } ; Insn |= firstByte << 0 ; Insn |= reinterpret_cast < const uint8_t * > ( Bytes . data ( ) ) [ 1 ] << 8 ; if ( Size == 3 ) { Insn |= reinterpret_cast < const uint8_t * > ( Bytes . data ( ) ) [ 2 ] << 16 ; return decodeInstruction ( DecoderTableXtensa24 , Instr , Insn , Address , this , STI ) ; } else { return decodeInstruction ( DecoderTableXtensa16 , Instr , Insn , Address , this , STI ) ; } } </s>

Returns the disassembly of a single instruction .


<s>
void
dump
(
)
{
dbgs
(
)
<<
"X86ISelAddressMode "
<<
this
<<
'\n'
;
dbgs
(
)
<<
"Base_Reg "
;
if
(
Base_Reg
.
getNode
(
)
!=
0
)
Base_Reg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Base.FrameIndex "
<<
Base_FrameIndex
<<
'\n'
<<
" Scale"
<<
Scale
<<
'\n'
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
!=
0
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" Disp "
<<
Disp
<<
'\n'
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
'\n'
<<
"ES "
;
if
(
ES
)
dbgs
(
)
<<
ES
;
else
dbgs
(
)
<<
"nul"
;
dbgs
(
)
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

X86
"X86ISelAddressMode "
"Base_Reg "
0
"nul"
" Base.FrameIndex "
" Scale"
"IndexReg "
0
"nul"
" Disp "
"GV "
"nul"
" CP "
"nul"
"ES "
"nul"
" JT"
" Align"


<s> BitVector TL45RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const MCPhysReg ReservedGPR32 [ ] = { TL45 :: r0 , TL45 :: sp , TL45 :: bp , TL45 :: pc , TL45 :: eflags } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned short I : ReservedGPR32 ) { Reserved . set ( I ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> BitVector MipsRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { static const MCPhysReg ReservedGPR32 [ ] = { Mips :: ZERO , Mips :: K0 , Mips :: K1 , Mips :: SP } ; static const MCPhysReg ReservedGPR64 [ ] = { Mips :: ZERO_64 , Mips :: K0_64 , Mips :: K1_64 , Mips :: SP_64 } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = 0 ; I < array_lengthof ( ReservedGPR32 ) ; ++ I ) Reserved . set ( ReservedGPR32 [ I ] ) ; if ( Subtarget . isTargetNaCl ( ) ) { Reserved . set ( Mips :: T6 ) ; Reserved . set ( Mips :: T7 ) ; Reserved . set ( Mips :: T8 ) ; } for ( unsigned I = 0 ; I < array_lengthof ( ReservedGPR64 ) ; ++ I ) Reserved . set ( ReservedGPR64 [ I ] ) ; if ( ! Subtarget . isABICalls ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . inMips16Mode ( ) ) Reserved . set ( Mips :: S0 ) ; else { Reserved . set ( Mips :: FP ) ; Reserved . set ( Mips :: FP_64 ) ; } } Reserved . set ( Mips :: HWR29 ) ; Reserved . set ( Mips :: DSPPos ) ; Reserved . set ( Mips :: DSPSCount ) ; Reserved . set ( Mips :: DSPCarry ) ; Reserved . set ( Mips :: DSPEFI ) ; Reserved . set ( Mips :: DSPOutFlag ) ; if ( Subtarget . inMips16Mode ( ) ) { const MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; Reserved . set ( Mips :: RA ) ; Reserved . set ( Mips :: RA_64 ) ; Reserved . set ( Mips :: T0 ) ; Reserved . set ( Mips :: T1 ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( "saveS2" ) || MipsFI -> hasSaveS2 ( ) ) Reserved . set ( Mips :: S2 ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( Mips :: GP ) ; Reserved . set ( Mips :: GP_64 ) ; } return Reserved ; } </s>


<s> static bool ck807_ck810_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case MULT : if ( REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , 1 ) ) ; if ( val % 2 == 0 && val < 0xffffffff && val > 0 ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } } return false ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( 3 ) ; return true ; default : return false ; } } </s>

TARGET_RTX_COSTS helper for ck807/ck810 arches .


<s> bool HSAILInstrInfo :: verifyInstruction ( const MachineInstr * MI , StringRef & ErrInfo ) const { return true ; } </s>

Perform target-specific instruction verification .


<s> void HexagonSubtarget :: adjustSchedDependency ( SUnit * Src , SUnit * Dst , SDep & Dep ) const { MachineInstr * SrcInst = Src -> getInstr ( ) ; MachineInstr * DstInst = Dst -> getInstr ( ) ; if ( ! Src -> isInstr ( ) || ! Dst -> isInstr ( ) ) return ; const HexagonInstrInfo * QII = getInstrInfo ( ) ; SmallSet < SUnit * , 4 > ExclSrc ; SmallSet < SUnit * , 4 > ExclDst ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } if ( ! hasV60TOps ( ) ) return ; if ( DstInst -> isRegSequence ( ) && Dst -> NumSuccs == 1 ) { unsigned RSeqReg = DstInst -> getOperand ( 0 ) . getReg ( ) ; MachineInstr * RSeqDst = Dst -> Succs [ 0 ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - 1 ; for ( unsigned OpNum = 0 ; OpNum < RSeqDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = RSeqDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == RSeqReg ) { UseIdx = OpNum ; break ; } } unsigned RSeqLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , 0 , * RSeqDst , UseIdx ) ) ; Dep . setLatency ( RSeqLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } updateLatency ( * SrcInst , * DstInst , Dep ) ; } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s>
void
apply
(
ScheduleDAGInstrs
*
DAGInstrs
)
override
{
const
GCNSubtarget
&
ST
=
DAGInstrs
->
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
if
(
!
ST
.
hasMAIInsts
(
)
||
DisablePowerSched
)
return
;
DAG
=
static_cast
<
ScheduleDAGMI
*
>
(
DAGInstrs
)
;
const
TargetSchedModel
*
TSchedModel
=
DAGInstrs
->
getSchedModel
(
)
;
if
(
!
TSchedModel
||
DAG
->
SUnits
.
empty
(
)
)
return
;
auto
LastSALU
=
DAG
->
SUnits
.
begin
(
)
;
auto
E
=
DAG
->
SUnits
.
end
(
)
;
SmallPtrSet
<
SUnit
*
,
32
>
Visited
;
for
(
SUnit
&
SU
:
DAG
->
SUnits
)
{
MachineInstr
&
MAI
=
*
SU
.
getInstr
(
)
;
if
(
!
TII
->
isMAI
(
MAI
)
||
MAI
.
getOpcode
(
)
==
AMDGPU
::
V_ACCVGPR_WRITE_B32_e64
||
MAI
.
getOpcode
(
)
==
AMDGPU
::
V_ACCVGPR_READ_B32_e64
)
continue
;
unsigned
Lat
=
TSchedModel
->
computeInstrLatency
(
&
MAI
)
1
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Found MFMA: "
;
DAG
->
dumpNode
(
SU
)
;
dbgs
(
)
<<
"Need "
<<
Lat
<<
" instructions to cover latency.\n"
)
;
for
(
;
Lat
&&
LastSALU
!=
E
;
++
LastSALU
)
{
if
(
Visited
.
count
(
&
*
LastSALU
)
)
continue
;
if
(
!
isSALU
(
&
*
LastSALU
)
||
!
canAddEdge
(
&
*
LastSALU
,
&
SU
)
)
continue
;
Lat
-=
linkSALUChain
(
&
SU
,
&
*
LastSALU
,
Lat
,
Visited
)
;
}
}
}
</s>

Apply the profile inference algorithm for a given function .


<s>
void
mmix_output_register_setting
(
FILE
*
stream
,
int
regno
,
int64_t
value
,
int
do_begin_end
)
{
if
(
do_begin_end
)
fprintf
(
stream
,
"\t"
)
;
if
(
insn_const_int_ok_for_constraint
(
value
,
CONSTRAINT_K
)
)
fprintf
(
stream
,
"NEGU %s,0,%"
PRId64
,
reg_names
[
regno
]
,
value
)
;
else
if
(
mmix_shiftable_wyde_value
(
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
uint64_t
)
value
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
(
uint64_t
)
value
)
;
fprintf
(
stream
,
"\n\tNEGU %s,0,%s"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
if
(
mmix_shiftable_wyde_value
(
~
(
uint64_t
)
value
)
)
{
mmix_output_shiftvalue_op_from_str
(
stream
,
"SET"
,
~
(
uint64_t
)
value
)
;
fprintf
(
stream
,
" %s,"
,
reg_names
[
regno
]
)
;
mmix_output_shifted_value
(
stream
,
~
(
uint64_t
)
value
)
;
fprintf
(
stream
,
"\n\tNOR %s,%s,0"
,
reg_names
[
regno
]
,
reg_names
[
regno
]
)
;
}
else
{
static
const
char
*
const
higher_parts
[
]
=
{
"L"
,
"ML"
,
"MH"
,
"H"
}
;
const
char
*
op
=
"SET"
;
const
char
*
line_begin
=
""
;
int
insns
=
0
;
int
i
;
int64_t
tmpvalue
=
value
;
for
(
i
=
0
;
i
<
4
&&
tmpvalue
!=
0
;
i
++
)
{
if
(
tmpvalue
&
65535
)
insns
++
;
tmpvalue
>>=
16
;
}
if
(
TARGET_BASE_ADDRESSES
&&
insns
==
3
)
{
fprintf
(
stream
,
"LDA %s,"
,
reg_names
[
regno
]
)
;
mmix_output_octa
(
stream
,
value
,
0
)
;
}
else
{
for
(
i
=
0
;
i
<
4
&&
value
!=
0
;
i
++
)
{
if
(
value
&
65535
)
{
fprintf
(
stream
,
"%s%s%s %s,#%x"
,
line_begin
,
op
,
higher_parts
[
i
]
,
reg_names
[
regno
]
,
(
int
)
(
value
&
65535
)
)
;
op
=
"INC"
;
line_begin
=
"\n\t"
;
}
value
>>=
16
;
}
}
}
if
(
do_begin_end
)
fprintf
(
stream
,
"\n"
)
;
}
</s>

Output an optimal sequence for setting a register to a specific constant . Used in an alternative for const_ints in movdi , and when using large stack-frame offsets . Use do_begin_end to say if a line-starting TAB and newline before the first insn and after the last insn is wanted .


<s> bool ARMTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( ! Subtarget -> hasVFP3 ( ) ) return false ; if ( VT == MVT :: f16 && Subtarget -> hasFullFP16 ( ) ) return ARM_AM :: getFP16Imm ( Imm ) != - 1 ; if ( VT == MVT :: f32 ) return ARM_AM :: getFP32Imm ( Imm ) != - 1 ; if ( VT == MVT :: f64 && ! Subtarget -> isFPOnlySP ( ) ) return ARM_AM :: getFP64Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> static void predict_jump ( int prob ) { rtx_insn * insn = get_last_insn ( ) ; gcc_assert ( JUMP_P ( insn ) ) ; add_reg_br_prob_note ( insn , profile_probability :: from_reg_br_prob_base ( prob ) ) ; } </s>

Predict just emitted jump instruction to be taken with probability PROB .


<s> static void mips_df_reorg ( void ) { df_set_flags ( DF_EQ_NOTES ) ; df_chain_add_problem ( DF_UD_CHAIN ) ; df_analyze ( ) ; if ( TARGET_RELAX_PIC_CALLS ) mips_annotate_pic_calls ( ) ; if ( mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE ) r10k_insert_cache_barriers ( ) ; df_finish_pass ( false ) ; } </s>

Subroutine of mips_reorg to manage passes that require DF .


<s>
EVT
SNESTargetLowering
::
getSetCCResultType
(
const
DataLayout
&
DL
,
LLVMContext
&
,
EVT
VT
)
const
{
assert
(
!
VT
.
isVector
(
)
&&
"No SNES SetCC type for vectors!"
)
;
return
MVT
::
i8
;
}
</s>

Return the value type to use for ISD : :SETCC .

SNES
SNES
"No SNES SetCC type for vectors!"
MVT::i8


<s> int getStackPointerBias ( ) override final { return 0 ; } </s>

The 64-bit ABI uses biased stack and frame pointers , so the stack frame of the current function is the area from [ sp+BIAS ] to [ fp+BIAS ] .


<s> static void mips_swap_registers ( unsigned int i ) { int tmpi ; const char * tmps ; SWAP_INT ( fixed_regs [ i ] , fixed_regs [ i + 1 ] ) ; SWAP_INT ( call_used_regs [ i ] , call_used_regs [ i + 1 ] ) ; SWAP_INT ( call_really_used_regs [ i ] , call_really_used_regs [ i + 1 ] ) ; SWAP_STRING ( reg_names [ i ] , reg_names [ i + 1 ] ) ; } </s>

Swap the register information for registers I and I + 1 , which currently have the wrong endianness . Note that the registers ' fixedness and call-clobberedness might have been set on the command line .


Helper function for gcn_reduction_update . Insert code to lockfully update * PTR with * PTR OP VAR just before GSI . This is necessary for types larger than 64 bits , where there is no cmp & swap instruction to implement a lockless scheme . We use a lock variable in global memory . while ( cmp & swap ( & lock_var , 0 , 1 ) ) continue ; T accum = * ptr ; accum = accum OP var ; * ptr = accum ; cmp & swap ( & lock_var , 1 , 0 ) ; return accum ; A lock in global memory is necessary to force execution engine descheduling and avoid resource starvation that can occur if the lock is in shared memory .


<s>
void
dump
(
)
{
cerr
<<
"X86ISelAddressMode "
<<
this
<<
"\n"
;
cerr
<<
"Base.Reg "
;
if
(
Base
.
Reg
.
getNode
(
)
!=
0
)
Base
.
Reg
.
getNode
(
)
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
" Base.FrameIndex "
<<
Base
.
FrameIndex
<<
"\n"
;
cerr
<<
"isRIPRel "
<<
isRIPRel
<<
" Scale"
<<
Scale
<<
"\n"
;
cerr
<<
"IndexReg "
;
if
(
IndexReg
.
getNode
(
)
!=
0
)
IndexReg
.
getNode
(
)
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
" Disp "
<<
Disp
<<
"\n"
;
cerr
<<
"GV "
;
if
(
GV
)
GV
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
" CP "
;
if
(
CP
)
CP
->
dump
(
)
;
else
cerr
<<
"nul"
;
cerr
<<
"\n"
;
cerr
<<
"ES "
;
if
(
ES
)
cerr
<<
ES
;
else
cerr
<<
"nul"
;
cerr
<<
" JT"
<<
JT
<<
" Align"
<<
Align
<<
"\n"
;
}
</s>

X86
"X86ISelAddressMode "
"\n"
"Base.Reg "
0
"nul"
" Base.FrameIndex "
"\n"
"isRIPRel "
" Scale"
"\n"
"IndexReg "
0
"nul"
" Disp "
"\n"
"GV "
"nul"
" CP "
"nul"
"\n"
"ES "
"nul"
" JT"
" Align"
"\n"


<s> MachinePointerInfo MipsFunctionInfo :: callPtrInfo ( const GlobalValue * Val ) { const MipsCallEntry * & E = GlobalCallEntries [ Val ] ; if ( ! E ) E = new MipsCallEntry ( Val ) ; return MachinePointerInfo ( E ) ; } </s>

Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object representing a GOT entry for a global function .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Branch Relaxation"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void BTFTypeFunc :: completeType ( BTFDebug & BDebug ) { BTFType . NameOff = BDebug . addString ( Name ) ; } </s>

Complete BTF type generation after all related DebugInfo types have been visited so their BTF type id 's are available for cross referece .


<s>
void
RV16KMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
MI
.
getOpcode
(
)
==
RV16K
::
PseudoHLT
)
{
expandHalt
(
MI
,
OS
,
Fixups
,
STI
)
;
MCNumEmitted
+=
4
;
return
;
}
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
default
:
llvm_unreachable
(
"Unhandled encodeInstruction length!"
)
;
case
2
:
{
uint16_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
<
uint16_t
>
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
case
4
:
{
uint32_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
support
::
endian
::
write
(
OS
,
Bits
,
support
::
little
)
;
break
;
}
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .


<s> void SparcFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & MI = * I ; int Size = MI . getOperand ( 0 ) . getImm ( ) ; if ( MI . getOpcode ( ) == SP :: ADJCALLSTACKDOWN ) Size = - Size ; if ( Size ) emitSPAdjustment ( MF , MBB , I , Size , SP :: ADDrr , SP :: ADDri ) ; } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> unsigned int darwin_rs6000_special_round_type_align ( tree type , unsigned int computed , unsigned int specified ) { unsigned int align = MAX ( computed , specified ) ; if ( TYPE_PACKED ( type ) ) return align ; do { tree field = TYPE_FIELDS ( type ) ; while ( field != NULL && ( TREE_CODE ( field ) != FIELD_DECL || DECL_FIELD_ABI_IGNORED ( field ) ) ) field = DECL_CHAIN ( field ) ; if ( ! field ) break ; if ( DECL_PACKED ( field ) ) return align ; type = TREE_TYPE ( field ) ; while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; } while ( AGGREGATE_TYPE_P ( type ) ) ; if ( ! AGGREGATE_TYPE_P ( type ) && type != error_mark_node ) align = MAX ( align , TYPE_ALIGN ( type ) ) ; return align ; } </s>

Darwin increases record alignment to the natural alignment of the first field .


<s> bool CAHPDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : OutOps . push_back ( Op ) ; return false ; default : break ; } return true ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s>
bool
X86AsmPrinter
::
PrintAsmOperand
(
const
MachineInstr
*
MI
,
unsigned
OpNo
,
const
char
*
ExtraCode
,
raw_ostream
&
O
)
{
if
(
ExtraCode
&&
ExtraCode
[
0
]
)
{
if
(
ExtraCode
[
1
]
!=
0
)
return
true
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNo
)
;
switch
(
ExtraCode
[
0
]
)
{
default
:
return
AsmPrinter
::
PrintAsmOperand
(
MI
,
OpNo
,
ExtraCode
,
O
)
;
case
'a'
:
switch
(
MO
.
getType
(
)
)
{
default
:
return
true
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
return
false
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
PrintSymbolOperand
(
MO
,
O
)
;
if
(
Subtarget
->
isPICStyleRIPRel
(
)
)
O
<<
"(%rip)"
;
return
false
;
case
MachineOperand
::
MO_Register
:
O
<<
'('
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
O
<<
')'
;
return
false
;
}
case
'c'
:
switch
(
MO
.
getType
(
)
)
{
default
:
PrintOperand
(
MI
,
OpNo
,
O
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
O
<<
MO
.
getImm
(
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
case
MachineOperand
::
MO_JumpTableIndex
:
case
MachineOperand
::
MO_ExternalSymbol
:
llvm_unreachable
(
"unexpected operand type!"
)
;
case
MachineOperand
::
MO_GlobalAddress
:
PrintSymbolOperand
(
MO
,
O
)
;
break
;
}
return
false
;
case
'A'
:
if
(
MO
.
isReg
(
)
)
{
O
<<
'*'
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
return
true
;
case
'b'
:
case
'h'
:
case
'w'
:
case
'k'
:
case
'q'
:
case
'V'
:
if
(
MO
.
isReg
(
)
)
return
printAsmMRegister
(
*
this
,
MO
,
ExtraCode
[
0
]
,
O
)
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'x'
:
case
't'
:
case
'g'
:
if
(
MO
.
isReg
(
)
)
return
printAsmVRegister
(
MO
,
ExtraCode
[
0
]
,
O
)
;
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'P'
:
PrintPCRelImm
(
MI
,
OpNo
,
O
)
;
return
false
;
case
'n'
:
if
(
MO
.
isImm
(
)
)
{
O
<<
MO
.
getImm
(
)
;
return
false
;
}
O
<<
'-'
;
}
}
PrintOperand
(
MI
,
OpNo
,
O
)
;
return
false
;
}
</s>

PrintAsmOperand - Print out an operand for an inline asm expression .


"FramePointer is not implemented on AIX yet."

getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer .


<s>
const
LegalizerInfo
*
getLegalizerInfo
(
)
const
override
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getLegalizerInfo
(
)
;
}
</s>

Expose LegalizerInfo so the clients can re-use .

AMDGPU
"Access to GlobalISel APIs not set"


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned getAddressSpace ( ) const { return getSubclassData ( ) ; } </s>

Return the address space of the Pointer type .


<s> bool PPCRegisterInfo :: isCallerPreservedPhysReg ( unsigned PhysReg , const MachineFunction & MF ) const { assert ( Register :: isPhysicalRegister ( PhysReg ) ) ; const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! TM . isPPC64 ( ) ) return false ; if ( ! Subtarget . isSVR4ABI ( ) ) return false ; if ( PhysReg == PPC :: X2 ) return ( getReservedRegs ( MF ) . test ( PPC :: X2 ) ) ; if ( StackPtrConst && ( PhysReg == PPC :: X1 ) && ! MFI . hasVarSizedObjects ( ) && ! MFI . hasOpaqueSPAdjustment ( ) ) return true ; return false ; } </s>

Physical registers that may be modified within a function but are guaranteed to be restored before any uses .


<s> static rtx bfin_load_pic_reg ( rtx dest ) { struct cgraph_local_info * i = NULL ; rtx addr , insn ; if ( flag_unit_at_a_time ) i = cgraph_local_info ( current_function_decl ) ; if ( i && i -> local ) return pic_offset_table_rtx ; if ( bfin_lib_id_given ) addr = plus_constant ( pic_offset_table_rtx , - 4 - bfin_library_id * 4 ) ; else addr = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_LIBRARY_OFFSET ) ) ; insn = emit_insn ( gen_movsi ( dest , gen_rtx_MEM ( Pmode , addr ) ) ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_MAYBE_DEAD , const0_rtx , NULL ) ; return dest ; } </s>

Used while emitting the prologue to generate code to load the correct value into the PIC register , which is passed in DEST .


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( IsZeroVal && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) && Subtarget -> hasNEON ( ) ) { if ( memOpAlign ( SrcAlign , DstAlign , 16 ) && Size >= 16 ) { return MVT :: v4i32 ; } else if ( memOpAlign ( SrcAlign , DstAlign , 8 ) && Size >= 8 ) { return MVT :: v2i32 ; } } if ( Size >= 4 ) { return MVT :: i32 ; } else if ( Size >= 2 ) { return MVT :: i16 ; } return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
int
SparcSubtarget
::
getAdjustedFrameSize
(
int
frameSize
)
const
{
if
(
is64Bit
(
)
)
{
frameSize
+=
128
;
assert
(
frameSize
%
16
==
0
&&
"Stack size not 16-byte aligned"
)
;
}
else
{
frameSize
+=
92
;
frameSize
=
RoundUpToAlignment
(
frameSize
,
8
)
;
}
return
frameSize
;
}
</s>

Given a actual stack size as determined by FrameInfo , this function returns adjusted framesize which includes space for RSA , return address , and frame poitner .


<s> void visium_expand_prologue ( void ) { const int frame_size = visium_compute_frame_size ( get_frame_size ( ) ) ; const int save_area_size = current_frame_info . save_area_size ; const int reg_size1 = current_frame_info . reg_size1 ; const int max_reg1 = current_frame_info . max_reg1 ; const int reg_size2 = current_frame_info . reg_size2 ; const int var_size = current_frame_info . var_size ; const int save_fp = current_frame_info . save_fp ; const int save_lr = current_frame_info . save_lr ; const int lr_slot = current_frame_info . lr_slot ; const int local_frame_offset = ( save_fp + save_lr + lr_slot ) * UNITS_PER_WORD ; const int combine = current_frame_info . combine ; int reg_size ; int first_reg ; int fsize ; visium_frame_size = frame_size ; if ( flag_stack_usage_info ) current_function_static_stack_size = frame_size ; if ( reg_size2 ) { visium_save_regs ( reg_size1 + save_area_size , reg_size1 , 0 , max_reg1 ) ; reg_size = reg_size2 ; first_reg = max_reg1 + 1 ; fsize = local_frame_offset + var_size + reg_size2 ; } else { reg_size = reg_size1 ; first_reg = 0 ; fsize = local_frame_offset + var_size + reg_size1 + save_area_size ; } if ( reg_size && ! combine ) visium_save_regs ( fsize - local_frame_offset - var_size , reg_size , first_reg , FIRST_PSEUDO_REGISTER - 1 ) ; if ( reg_size && combine ) visium_save_regs ( fsize , local_frame_offset + var_size + reg_size , first_reg , FIRST_PSEUDO_REGISTER - 1 ) ; else if ( fsize ) { const int alloc_size = reg_size ? local_frame_offset + var_size : fsize ; if ( alloc_size > 65535 ) { rtx tmp = gen_rtx_REG ( SImode , PROLOGUE_TMP_REGNUM ) , insn ; emit_insn ( gen_movsi ( tmp , GEN_INT ( alloc_size ) ) ) ; insn = emit_frame_insn ( gen_subsi3_flags ( stack_pointer_rtx , stack_pointer_rtx , tmp ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - alloc_size ) ) ) ) ; } else emit_frame_insn ( gen_addsi3_flags ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - alloc_size ) ) ) ; } if ( save_fp ) emit_frame_insn ( gen_movsi ( gen_frame_mem ( SImode , stack_pointer_rtx ) , hard_frame_pointer_rtx ) ) ; if ( frame_pointer_needed ) emit_frame_insn ( gen_stack_save ( ) ) ; if ( save_lr ) { rtx base_rtx , mem ; if ( cfun -> machine -> frame_needed ) base_rtx = hard_frame_pointer_rtx ; else base_rtx = stack_pointer_rtx ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , base_rtx , save_fp * UNITS_PER_WORD ) ) ; emit_frame_insn ( gen_movsi ( mem , gen_rtx_REG ( SImode , LINK_REGNUM ) ) ) ; } } </s>

This function generates the code for function entry .


<s> bool rs6000_emit_set_const ( rtx dest , rtx source ) { machine_mode mode = GET_MODE ( dest ) ; rtx temp , set ; rtx_insn * insn ; HOST_WIDE_INT c ; gcc_checking_assert ( CONST_INT_P ( source ) ) ; c = INTVAL ( source ) ; switch ( mode ) { case QImode : case HImode : emit_insn ( gen_rtx_SET ( dest , source ) ) ; return true ; case SImode : temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( copy_rtx ( temp ) , GEN_INT ( c & ~ ( HOST_WIDE_INT ) 0xffff ) ) ) ; emit_insn ( gen_rtx_SET ( dest , gen_rtx_IOR ( SImode , copy_rtx ( temp ) , GEN_INT ( c & 0xffff ) ) ) ) ; break ; case DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == 0 , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != 0 , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> 32 ) ) ; c = ( ( c & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; emit_move_insn ( lo , GEN_INT ( c ) ) ; } else rs6000_emit_set_long_const ( dest , c ) ; break ; default : gcc_unreachable ( ) ; } insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( insn , REG_EQUAL , GEN_INT ( c ) ) ; return true ; } </s>

Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns . Do all computations in MODE . Returns the place where the output has been placed if it can be done and the insns have been emitted . If it would take more than N insns , zero is returned and no insns and emitted .


<s> static machine_mode aarch64_reg_save_mode ( tree fndecl , unsigned regno ) { return GP_REGNUM_P ( regno ) ? E_DImode : ( aarch64_simd_decl_p ( fndecl ) ? E_TFmode : E_DFmode ) ; } </s>

Return the mode a register save/restore should use . DImode for integer registers , DFmode for FP registers in non-SIMD functions ( they only save the bottom half of a 128 bit register ) , or TFmode for FP registers in SIMD functions .


<s> SDValue HexagonTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == MVT :: i1 ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , MVT :: i32 , InFlag ) ; unsigned PredR = MRI . createVirtualRegister ( & Hexagon :: PredRegsRegClass ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( 1 ) , dl , PredR , FR0 . getValue ( 0 ) , FR0 . getValue ( 2 ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( 0 ) , dl , PredR , MVT :: i1 , TPR . getValue ( 1 ) ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) ; } InVals . push_back ( RetVal . getValue ( 0 ) ) ; Chain = RetVal . getValue ( 1 ) ; InFlag = RetVal . getValue ( 2 ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
void
X86TargetLowering
::
emitBitTestAtomicRMWIntrinsic
(
AtomicRMWInst
*
AI
)
const
{
IRBuilder
<
>
Builder
(
AI
)
;
Intrinsic
::
ID
IID
=
Intrinsic
::
not_intrinsic
;
switch
(
AI
->
getOperation
(
)
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Or
:
IID
=
Intrinsic
::
x86_atomic_bts
;
break
;
case
AtomicRMWInst
::
Xor
:
IID
=
Intrinsic
::
x86_atomic_btc
;
break
;
case
AtomicRMWInst
::
And
:
IID
=
Intrinsic
::
x86_atomic_btr
;
break
;
}
Instruction
*
I
=
AI
->
user_back
(
)
;
LLVMContext
&
Ctx
=
AI
->
getContext
(
)
;
unsigned
Imm
=
countTrailingZeros
(
cast
<
ConstantInt
>
(
I
->
getOperand
(
1
)
)
->
getZExtValue
(
)
)
;
Function
*
BitTest
=
Intrinsic
::
getDeclaration
(
AI
->
getModule
(
)
,
IID
,
AI
->
getType
(
)
)
;
Value
*
Addr
=
Builder
.
CreatePointerCast
(
AI
->
getPointerOperand
(
)
,
Type
::
getInt8PtrTy
(
Ctx
)
)
;
Value
*
Result
=
Builder
.
CreateCall
(
BitTest
,
{
Addr
,
Builder
.
getInt8
(
Imm
)
}
)
;
I
->
replaceAllUsesWith
(
Result
)
;
I
->
eraseFromParent
(
)
;
AI
->
eraseFromParent
(
)
;
}
</s>

Perform a bit test atomicrmw using a target-specific intrinsic .


"Can only insert epilog into returning blocks"


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
bool
ARMAsmBackend
::
shouldForceRelocation
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
)
{
const
MCSymbolRefExpr
*
A
=
Target
.
getSymA
(
)
;
const
MCSymbol
*
Sym
=
A
&
A
->
getSymbol
(
)
:
nullptr
;
const
unsigned
FixupKind
=
Fixup
.
getKind
(
)
;
if
(
FixupKind
==
FK_NONE
)
return
true
;
if
(
FixupKind
==
ARM
::
fixup_arm_thumb_bl
)
{
assert
(
Sym
&&
"How did we resolve this?"
)
;
if
(
Sym
->
isExternal
(
)
)
return
true
;
}
if
(
Sym
&&
Sym
->
isELF
(
)
)
{
unsigned
Type
=
cast
<
MCSymbolELF
>
(
Sym
)
->
getType
(
)
;
if
(
(
Type
==
ELF
::
STT_FUNC
||
Type
==
ELF
::
STT_GNU_IFUNC
)
)
{
if
(
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_uncondbranch
)
)
return
true
;
if
(
!
Asm
.
isThumbFunc
(
Sym
)
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_br
||
FixupKind
==
ARM
::
fixup_arm_thumb_bl
||
FixupKind
==
ARM
::
fixup_t2_condbranch
||
FixupKind
==
ARM
::
fixup_t2_uncondbranch
)
)
return
true
;
}
}
if
(
A
&&
(
FixupKind
==
ARM
::
fixup_arm_thumb_blx
||
FixupKind
==
ARM
::
fixup_arm_blx
||
FixupKind
==
ARM
::
fixup_arm_uncondbl
||
FixupKind
==
ARM
::
fixup_arm_condbl
)
)
return
true
;
return
false
;
}
</s>

Hook to check if a relocation is needed for some target specific reason .


<s> static void rbt_left_rotate ( struct rbt_strings * t , struct rbt_string_node * node ) { struct rbt_string_node * right = node -> right ; assert ( right ) ; node -> right = right -> left ; if ( right -> left != t -> rbt_nil ) right -> left -> par = node ; right -> par = node -> par ; if ( node -> par == t -> rbt_nil ) t -> rbt_root = right ; else if ( node == node -> par -> left ) node -> par -> left = right ; else node -> par -> right = right ; right -> left = node ; node -> par = right ; } </s>

Perform a left-rotate operation on NODE in the red-black tree .


<s> void Thumb2RegisterInfo :: emitLoadConstPool ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , unsigned DestReg , unsigned SubIdx , int Val , ARMCC :: CondCodes Pred , unsigned PredReg ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , 4 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ARM :: t2LDRpci ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) ARMCC :: AL ) . addReg ( 0 ) ; } </s>

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate .


<s> static void nvptx_emit_joining ( unsigned mask , bool is_call ) { mask &= ( GOMP_DIM_MASK ( GOMP_DIM_WORKER ) | GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ; if ( mask ) { rtx op = GEN_INT ( mask | ( is_call << GOMP_DIM_MAX ) ) ; emit_insn ( gen_nvptx_joining ( op ) ) ; emit_insn ( gen_nvptx_join ( op ) ) ; } } </s>


<s> bool is ( unsigned T ) const { assert ( T == 0 || T == 1 ) ; return T == 0 ? Type == Zero : ( T == 1 ? Type == One : false ) ; } </s>


<s> static void msp430_print_operand_addr ( FILE * file , machine_mode , rtx addr ) { switch ( GET_CODE ( addr ) ) { case PLUS : msp430_print_operand_raw ( file , XEXP ( addr , 1 ) ) ; gcc_assert ( REG_P ( XEXP ( addr , 0 ) ) ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; return ; case REG : fprintf ( file , "@" ) ; break ; case CONST : case CONST_INT : case SYMBOL_REF : case LABEL_REF : fprintf ( file , "&" ) ; break ; default : break ; } msp430_print_operand_raw ( file , addr ) ; } </s>

Output to stdio stream FILE the assembler syntax for an instruction operand that is a memory reference whose address is ADDR .


<s> int ARMTargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) { if ( Subtarget -> hasFPAO ( ) ) return AM . Scale < 0 ? 1 : 0 ; return 0 ; } return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s> void RISCVInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { bool Changed = true ; while ( Changed ) { Changed = false ; auto I = MBB . begin ( ) ; auto E = MBB . end ( ) ; for ( ; I != E ; ++ I ) { if ( I -> isCFIInstruction ( ) ) { I -> removeFromParent ( ) ; Changed = true ; break ; } } } MBB . insert ( MBB . end ( ) , BuildMI ( MF , DebugLoc ( ) , get ( RISCV :: JALR ) ) . addReg ( RISCV :: X0 , RegState :: Define ) . addReg ( RISCV :: X5 ) . addImm ( 0 ) ) ; } </s>

Insert a custom frame for outlined functions .


<s> bool mprocAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
Patmos
::
NumTargetFixupKinds
]
=
{
{
"FK_Patmos_BO_7"
,
25
,
7
,
0
}
,
{
"FK_Patmos_SO_7"
,
25
,
7
,
0
}
,
{
"FK_Patmos_WO_7"
,
25
,
7
,
0
}
,
{
"FK_Patmos_abs_ALUi"
,
20
,
12
,
0
}
,
{
"FK_Patmos_abs_CFLi"
,
10
,
22
,
0
}
,
{
"FK_Patmos_abs_ALUl"
,
32
,
32
,
0
}
,
{
"FK_Patmos_stc"
,
14
,
18
,
0
}
,
{
"FK_Patmos_PCrel"
,
10
,
22
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s>
unsigned
MipsSEInstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BEQ
:
return
Mips
::
BNE
;
case
Mips
::
BEQ_MM
:
return
Mips
::
BNE_MM
;
case
Mips
::
BNE
:
return
Mips
::
BEQ
;
case
Mips
::
BNE_MM
:
return
Mips
::
BEQ_MM
;
case
Mips
::
BGTZ
:
return
Mips
::
BLEZ
;
case
Mips
::
BGEZ
:
return
Mips
::
BLTZ
;
case
Mips
::
BLTZ
:
return
Mips
::
BGEZ
;
case
Mips
::
BLEZ
:
return
Mips
::
BGTZ
;
case
Mips
::
BEQ64
:
return
Mips
::
BNE64
;
case
Mips
::
BNE64
:
return
Mips
::
BEQ64
;
case
Mips
::
BGTZ64
:
return
Mips
::
BLEZ64
;
case
Mips
::
BGEZ64
:
return
Mips
::
BLTZ64
;
case
Mips
::
BLTZ64
:
return
Mips
::
BGEZ64
;
case
Mips
::
BLEZ64
:
return
Mips
::
BGTZ64
;
case
Mips
::
BC1T
:
return
Mips
::
BC1F
;
case
Mips
::
BC1F
:
return
Mips
::
BC1T
;
case
Mips
::
BEQZC_MM
:
return
Mips
::
BNEZC_MM
;
case
Mips
::
BNEZC_MM
:
return
Mips
::
BEQZC_MM
;
case
Mips
::
BEQZC
:
return
Mips
::
BNEZC
;
case
Mips
::
BNEZC
:
return
Mips
::
BEQZC
;
case
Mips
::
BEQC
:
return
Mips
::
BNEC
;
case
Mips
::
BNEC
:
return
Mips
::
BEQC
;
case
Mips
::
BGTZC
:
return
Mips
::
BLEZC
;
case
Mips
::
BGEZC
:
return
Mips
::
BLTZC
;
case
Mips
::
BLTZC
:
return
Mips
::
BGEZC
;
case
Mips
::
BLEZC
:
return
Mips
::
BGTZC
;
case
Mips
::
BEQZC64
:
return
Mips
::
BNEZC64
;
case
Mips
::
BNEZC64
:
return
Mips
::
BEQZC64
;
case
Mips
::
BEQC64
:
return
Mips
::
BNEC64
;
case
Mips
::
BNEC64
:
return
Mips
::
BEQC64
;
case
Mips
::
BGEC64
:
return
Mips
::
BLTC64
;
case
Mips
::
BGEUC64
:
return
Mips
::
BLTUC64
;
case
Mips
::
BLTC64
:
return
Mips
::
BGEC64
;
case
Mips
::
BLTUC64
:
return
Mips
::
BGEUC64
;
case
Mips
::
BGTZC64
:
return
Mips
::
BLEZC64
;
case
Mips
::
BGEZC64
:
return
Mips
::
BLTZC64
;
case
Mips
::
BLTZC64
:
return
Mips
::
BGEZC64
;
case
Mips
::
BLEZC64
:
return
Mips
::
BGTZC64
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s> void HexagonPassConfig :: addPreSched2 ( ) { addPass ( createHexagonCopyToCombine ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ; addPass ( createHexagonSplitConst32AndConst64 ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


<s> static bool v850_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { return int_size_in_bytes ( type ) > 8 || TYPE_MODE ( type ) == BLKmode ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s>
void
WebAssemblyInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
auto
&
MRI
=
MBB
.
getParent
(
)
->
getRegInfo
(
)
;
const
TargetRegisterClass
*
RC
=
TargetRegisterInfo
::
isVirtualRegister
(
DestReg
)
MRI
.
getRegClass
(
DestReg
)
:
MRI
.
getTargetRegisterInfo
(
)
->
getMinimalPhysRegClass
(
DestReg
)
;
unsigned
CopyLocalOpcode
;
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_I32
;
else
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_I64
;
else
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_F32
;
else
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
CopyLocalOpcode
=
WebAssembly
::
COPY_LOCAL_F64
;
else
llvm_unreachable
(
"Unexpected register class"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
CopyLocalOpcode
)
,
DestReg
)
.
addReg
(
SrcReg
,
KillSrc
RegState
::
Kill
:
0
)
;
}
</s>


<s> unsigned VEInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == VE :: STrii || MI . getOpcode ( ) == VE :: STLrii || MI . getOpcode ( ) == VE :: STUrii || MI . getOpcode ( ) == VE :: STQrii ) { if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 3 ) . getReg ( ) ; } } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
bool
NeedShadowCallStackProlog
=
false
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
,
NeedShadowCallStackProlog
)
;
auto
EmitMI
=
[
&
]
(
const
RegPairInfo
&
RPI
)
{
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
;
if
(
ReverseCSRRestoreSeq
)
for
(
const
RegPairInfo
&
RPI
:
reverse
(
RegPairs
)
)
EmitMI
(
RPI
)
;
else
for
(
const
RegPairInfo
&
RPI
:
RegPairs
)
EmitMI
(
RPI
)
;
if
(
NeedShadowCallStackProlog
)
{
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
AArch64
::
LDRXpre
)
)
.
addReg
(
AArch64
::
X18
,
RegState
::
Define
)
.
addReg
(
AArch64
::
LR
,
RegState
::
Define
)
.
addReg
(
AArch64
::
X18
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> std :: pair < unsigned , const TargetRegisterClass * > AArch64TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: GPR64commonRegClass ) ; return std :: make_pair ( 0U , & AArch64 :: GPR32commonRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , & AArch64 :: FPR32RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return std :: make_pair ( 0U , & AArch64 :: FPR64RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128RegClass ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == 128 ) return std :: make_pair ( 0U , & AArch64 :: FPR128_loRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( AArch64 :: NZCV ) , & AArch64 :: CCRRegClass ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == 4 || Size == 5 ) && Constraint [ 0 ] == '{' && tolower ( Constraint [ 1 ] ) == 'v' && Constraint [ Size - 1 ] == '}' ) { const std :: string Reg = std :: string ( & Constraint [ 2 ] , & Constraint [ Size - 1 ] ) ; int RegNo = atoi ( Reg . c_str ( ) ) ; if ( RegNo >= 0 && RegNo <= 31 ) { Res . first = AArch64 :: FPR128RegClass . getRegister ( RegNo ) ; Res . second = & AArch64 :: FPR128RegClass ; } } } return Res ; } </s>

Given a physical register constraint ( e.g .


<s> void RISCVFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( hasFP ( MF ) ) { SavedRegs . set ( RISCV :: X1 ) ; SavedRegs . set ( RISCV :: X8 ) ; } if ( hasBP ( MF ) ) SavedRegs . set ( RISCVABI :: getBPReg ( ) ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { RISCV :: X1 , RISCV :: X5 , RISCV :: X6 , RISCV :: X7 , RISCV :: X10 , RISCV :: X11 , RISCV :: X12 , RISCV :: X13 , RISCV :: X14 , RISCV :: X15 , RISCV :: X16 , RISCV :: X17 , RISCV :: X28 , RISCV :: X29 , RISCV :: X30 , RISCV :: X31 , 0 } ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = 0 ; Regs [ i ] ; ++ i ) if ( RISCV :: FPR16RegClass . contains ( Regs [ i ] ) || RISCV :: FPR32RegClass . contains ( Regs [ i ] ) || RISCV :: FPR64RegClass . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> void RISCVFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; RISCVFunctionInfo * RISCVFI = MF . getInfo < RISCVFunctionInfo > ( ) ; const RISCVRegisterInfo * RegInfo = static_cast < const RISCVRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; const RISCVInstrInfo & TII = * static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; const RISCVSubtarget & STI = MF . getSubtarget < RISCVSubtarget > ( ) ; unsigned SP = STI . isRV64 ( ) ? RISCV :: sp_64 : RISCV :: sp ; unsigned FP = STI . isRV64 ( ) ? RISCV :: fp_64 : RISCV :: fp ; unsigned ZERO = STI . isRV64 ( ) ? RISCV :: zero_64 : RISCV :: zero ; unsigned ADDu = STI . isRV64 ( ) ? RISCV :: ADD64 : RISCV :: ADD ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , dl , TII . get ( ADDu ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( RISCVFI -> getCallsEhReturn ( ) ) { const TargetRegisterClass * RC = & RISCV :: GR32BitRegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI -> getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ehDataReg ( J ) , RISCVFI -> getEhDataRegFI ( J ) , RC , RegInfo ) ; } } uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>


"LOAD_STACK_GUARD currently supported only for MachO."

This function is called for all pseudo instructions that remain after register allocation .


<s> void assignValueToReg ( unsigned ValVReg , unsigned PhysReg , CCValAssign & VA ) override { MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg ) ; MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s>
void
SystemZTargetLowering
::
LowerOperationWrapper
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
switch
(
N
->
getOpcode
(
)
)
{
case
ISD
::
ATOMIC_LOAD
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Untyped
,
MVT
::
Other
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
N
->
getOperand
(
1
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_LOAD_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
Results
.
push_back
(
lowerGR128ToI128
(
DAG
,
Res
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
break
;
}
case
ISD
::
ATOMIC_STORE
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Other
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
2
)
)
,
N
->
getOperand
(
1
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_STORE_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
if
(
cast
<
AtomicSDNode
>
(
N
)
->
getOrdering
(
)
==
AtomicOrdering
::
SequentiallyConsistent
)
Res
=
SDValue
(
DAG
.
getMachineNode
(
SystemZ
::
Serialize
,
DL
,
MVT
::
Other
,
Res
)
,
0
)
;
Results
.
push_back
(
Res
)
;
break
;
}
case
ISD
::
ATOMIC_CMP_SWAP_WITH_SUCCESS
:
{
SDLoc
DL
(
N
)
;
SDVTList
Tys
=
DAG
.
getVTList
(
MVT
::
Untyped
,
MVT
::
Other
,
MVT
::
Glue
)
;
SDValue
Ops
[
]
=
{
N
->
getOperand
(
0
)
,
N
->
getOperand
(
1
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
2
)
)
,
lowerI128ToGR128
(
DAG
,
N
->
getOperand
(
3
)
)
}
;
MachineMemOperand
*
MMO
=
cast
<
AtomicSDNode
>
(
N
)
->
getMemOperand
(
)
;
SDValue
Res
=
DAG
.
getMemIntrinsicNode
(
SystemZISD
::
ATOMIC_CMP_SWAP_128
,
DL
,
Tys
,
Ops
,
MVT
::
i128
,
MMO
)
;
SDValue
Success
=
emitSETCC
(
DAG
,
DL
,
Res
.
getValue
(
2
)
,
SystemZ
::
CCMASK_CS
,
SystemZ
::
CCMASK_CS_EQ
)
;
Success
=
DAG
.
getZExtOrTrunc
(
Success
,
DL
,
N
->
getValueType
(
1
)
)
;
Results
.
push_back
(
lowerGR128ToI128
(
DAG
,
Res
)
)
;
Results
.
push_back
(
Success
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
break
;
}
default
:
llvm_unreachable
(
"Unexpected node to lower"
)
;
}
}
</s>

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types .


<s> static int arm_get_vfp_saved_size ( void ) { unsigned int regno ; int count ; int saved ; saved = 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) { count = 0 ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += 2 ) { if ( ( ! df_regs_ever_live_p ( regno ) || call_used_regs [ regno ] ) && ( ! df_regs_ever_live_p ( regno + 1 ) || call_used_regs [ regno + 1 ] ) ) { if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } count = 0 ; } else count ++ ; } if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } } return saved ; } </s>

Return the number of bytes required to save VFP registers .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = MF . getFunction ( ) -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer . EmitCOFFSymbolType ( Type ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ; return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> void MSP430RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const MSP430FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? MSP430 :: FP : MSP430 :: SP ) ; int Offset = MF . getFrameInfo ( ) . getObjectOffset ( FrameIndex ) ; Offset += 2 ; if ( ! TFI -> hasFP ( MF ) ) Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; else Offset += 2 ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( MI . getOpcode ( ) == MSP430 :: ADD16ri ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( MSP430 :: MOV16rr ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == 0 ) return ; unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( Offset < 0 ) BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: SUB16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( MSP430 :: ADD16ri ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> const uint32_t * TeakRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void assign_csky_minipool_offsets ( Mfix * barrier ) { HOST_WIDE_INT offset = 0 ; Mnode * mp ; minipool_barrier = barrier ; for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) { mp -> offset = offset ; if ( mp -> refcount > 0 ) offset += mp -> fix_size ; } } </s>

Fill in the offsets for minipool entries .


<s> static bool isConditionalBranch ( const MachineInstr & MI ) { return ( MI . getOpcode ( ) == TPC :: JMPR || MI . getOpcode ( ) == TPC :: JMPA ) && MI . getOperand ( 1 ) . getReg ( ) != TPC :: SP0 ; } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM pseudo instruction expansion pass"
;
}
</s>

getPassName - Return a nice clean name for a pass .

ARM
"ARM pseudo instruction expansion pass"


<s> bool SIInstrInfo :: isOperandLegal ( const MachineInstr * MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & InstDesc = get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - 1 ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI -> getOperand ( OpIdx ) ; if ( isVALU ( InstDesc . Opcode ) && usesConstantBus ( MRI , * MO , DefinedRC -> getSize ( ) ) ) { unsigned SGPRUsed = MO -> isReg ( ) ? MO -> getReg ( ) : ( unsigned ) AMDGPU :: NoRegister ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) != SGPRUsed && usesConstantBus ( MRI , Op , getOpSize ( * MI , i ) ) ) { return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; const TargetRegisterClass * RC = MRI . getRegClass ( MO -> getReg ( ) ) ; return RI . getCommonSubClass ( RC , RI . getRegClass ( OpInfo . RegClass ) ) == RC ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO ) ; } </s>

Check if MO is a legal operand if it was the OpIdx Operand for MI .


<s>
void
BlockWaitcntBrackets
::
print
(
raw_ostream
&
OS
)
{
OS
<<
'\n'
;
for
(
enum
InstCounterType
T
=
VM_CNT
;
T
<
NUM_INST_CNTS
;
T
=
(
enum
InstCounterType
)
(
T
+
1
)
)
{
int
LB
=
getScoreLB
(
T
)
;
int
UB
=
getScoreUB
(
T
)
;
switch
(
T
)
{
case
VM_CNT
:
OS
<<
"    VM_CNT("
<<
UB
LB
<<
"): "
;
break
;
case
LGKM_CNT
:
OS
<<
"    LGKM_CNT("
<<
UB
LB
<<
"): "
;
break
;
case
EXP_CNT
:
OS
<<
"    EXP_CNT("
<<
UB
LB
<<
"): "
;
break
;
default
:
OS
<<
"    UNKNOWN("
<<
UB
LB
<<
"): "
;
break
;
}
if
(
LB
<
UB
)
{
for
(
int
J
=
0
;
J
<=
getMaxVGPR
(
)
;
J
++
)
{
int
RegScore
=
getRegScore
(
J
,
T
)
;
if
(
RegScore
<=
LB
)
continue
;
int
RelScore
=
RegScore
LB
1
;
if
(
J
<
SQ_MAX_PGM_VGPRS
+
EXTRA_VGPR_LDS
)
{
OS
<<
RelScore
<<
":v"
<<
J
<<
" "
;
}
else
{
OS
<<
RelScore
<<
":ds "
;
}
}
if
(
T
==
LGKM_CNT
)
{
for
(
int
J
=
0
;
J
<=
getMaxSGPR
(
)
;
J
++
)
{
int
RegScore
=
getRegScore
(
J
+
NUM_ALL_VGPRS
,
LGKM_CNT
)
;
if
(
RegScore
<=
LB
)
continue
;
int
RelScore
=
RegScore
LB
1
;
OS
<<
RelScore
<<
":s"
<<
J
<<
" "
;
}
}
}
OS
<<
'\n'
;
}
OS
<<
'\n'
;
return
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> bool direct_move_p ( rtx op0 , rtx op1 ) { int regno0 , regno1 ; if ( ! REG_P ( op0 ) || ! REG_P ( op1 ) ) return false ; if ( ! TARGET_DIRECT_MOVE && ! TARGET_MFPGPR ) return false ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; if ( ! HARD_REGISTER_NUM_P ( regno0 ) || ! HARD_REGISTER_NUM_P ( regno1 ) ) return false ; if ( INT_REGNO_P ( regno0 ) ) return ( TARGET_DIRECT_MOVE ) ? VSX_REGNO_P ( regno1 ) : FP_REGNO_P ( regno1 ) ; else if ( INT_REGNO_P ( regno1 ) ) { if ( TARGET_MFPGPR && FP_REGNO_P ( regno0 ) ) return true ; else if ( TARGET_DIRECT_MOVE && VSX_REGNO_P ( regno0 ) ) return true ; } return false ; } </s>

Return true if this is a move direct operation between GPR registers and floating point/VSX registers .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static bool alpha_split_complex_arg ( tree type ) { return TYPE_MODE ( type ) != TCmode ; } </s>

TCmode complex values are passed by invisible reference . We should not split these values .


<s> void pru_expand_epilogue ( bool sibcall_p ) { int total_frame_size ; int sp_adjust , save_offset ; int regno_start ; if ( ! sibcall_p && pru_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } emit_insn ( gen_blockage ( ) ) ; total_frame_size = cfun -> machine -> total_size ; if ( frame_pointer_needed ) { pru_add3_frame_adjust ( stack_pointer_rtx , hard_frame_pointer_rtx , - cfun -> machine -> save_reg_size , REG_CFA_ADJUST_CFA ) ; save_offset = 0 ; sp_adjust = total_frame_size - cfun -> machine -> save_regs_offset ; } else if ( ! UBYTE_INT ( total_frame_size ) ) { pru_add_to_sp ( cfun -> machine -> save_regs_offset , REG_CFA_ADJUST_CFA ) ; save_offset = 0 ; sp_adjust = total_frame_size - cfun -> machine -> save_regs_offset ; } else { save_offset = cfun -> machine -> save_regs_offset ; sp_adjust = total_frame_size ; } regno_start = 0 ; do regno_start = xbbo_next_reg_cluster ( regno_start , & save_offset , false ) ; while ( regno_start >= 0 ) ; emit_insn ( gen_blockage ( ) ) ; if ( sp_adjust ) pru_add_to_sp ( sp_adjust , REG_CFA_ADJUST_CFA ) ; if ( ! sibcall_p ) emit_jump_insn ( gen_simple_return ( ) ) ; } </s>


<s> unsigned M680x0RegisterInfo :: getMatchingMegaReg ( unsigned Reg , const TargetRegisterClass * RC ) const { for ( MCSuperRegIterator Super ( Reg , this ) ; Super . isValid ( ) ; ++ Super ) if ( RC -> contains ( * Super ) ) return * Super ; return 0 ; } </s>

Return a mega-register of the specified register Reg so its sub-register of index SubIdx is Reg , its super ( or mega ) Reg .


"Can't return value from vararg function in memory"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const char * LoongArchTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( LoongArchISD :: NodeType ) Opcode ) { case LoongArchISD :: FIRST_NUMBER : break ; case LoongArchISD :: node : \ return "LoongArchISD::" # node ; NODE_NAME_CASE ( RET ) } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

LoongArch LoongArch LoongArchISD::NodeType LoongArchISD::FIRST_NUMBER LoongArchISD::node "LoongArchISD::"


<s> void s390_activate_target_options ( tree new_tree ) { cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; s390_previous_fndecl = NULL_TREE ; } </s>

Restore targets globals from NEW_TREE and invalidate s390_previous_fndecl cache .


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
DataLayout
&
DL
,
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
,
Instruction
*
I
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
if
(
AS
==
AMDGPUAS
::
GLOBAL_ADDRESS
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
AS
==
AMDGPUAS
::
CONSTANT_ADDRESS
||
AS
==
AMDGPUAS
::
CONSTANT_ADDRESS_32BIT
||
AS
==
AMDGPUAS
::
BUFFER_FAT_POINTER
)
{
if
(
AM
.
BaseOffs
%
4
!=
0
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
Ty
->
isSized
(
)
&&
DL
.
getTypeStoreSize
(
Ty
)
<
4
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
if
(
!
isUInt
<
8
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SEA_ISLANDS
)
{
if
(
!
isUInt
<
32
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
>=
AMDGPUSubtarget
::
VOLCANIC_ISLANDS
)
{
if
(
!
isUInt
<
20
>
(
AM
.
BaseOffs
)
)
return
false
;
}
else
llvm_unreachable
(
"unhandled generation"
)
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUAS
::
PRIVATE_ADDRESS
)
{
return
isLegalMUBUFAddressingMode
(
AM
)
;
}
else
if
(
AS
==
AMDGPUAS
::
LOCAL_ADDRESS
||
AS
==
AMDGPUAS
::
REGION_ADDRESS
)
{
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUAS
::
FLAT_ADDRESS
||
AS
==
AMDGPUAS
::
UNKNOWN_ADDRESS_SPACE
)
{
return
isLegalFlatAddressingMode
(
AM
)
;
}
return
isLegalGlobalAddressingMode
(
AM
)
;
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> bool X86TargetLowering :: useStackGuardXorFP ( ) const { return Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ; } </s>

If this function returns true , stack protection checks should XOR the frame pointer ( or whichever pointer is used to address locals ) into the stack guard value before checking it .


<s> void HexagonTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> MachineRegisterInfo & getRegInfo ( Block & MBB ) { return MBB . getParent ( ) -> getRegInfo ( ) ; } </s>

getRegInfo - Return information about the registers currently in use .


<s> bool isImm ( ) const override { return Kind == Immediate || Kind == Expression ; } </s>


<s>
void
tilegx_function_profiler
(
FILE
*
file
,
int
labelno
ATTRIBUTE_UNUSED
)
{
if
(
tilegx_in_bundle
)
{
fprintf
(
file
,
"\t}\n"
)
;
}
if
(
cfun
->
static_chain_decl
)
{
fprintf
(
file
,
"\t{\n"
"\taddi\tsp, sp, -16\n"
"\tst\tsp, r10\n"
"\t}\n"
)
;
}
if
(
flag_pic
)
{
fprintf
(
file
,
"\t{\n"
"\tmove\tr10, lr\n"
"\tjal\tplt(%s)\n"
"\t}\n"
,
MCOUNT_NAME
)
;
}
else
{
fprintf
(
file
,
"\t{\n"
"\tmove\tr10, lr\n"
"\tjal\t%s\n"
"\t}\n"
,
MCOUNT_NAME
)
;
}
if
(
cfun
->
static_chain_decl
)
{
fprintf
(
file
,
"\taddi\tsp, sp, 16\n"
"\tld\tr10, sp\n"
)
;
}
tilegx_in_bundle
=
false
;
}
</s>

Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry .


<s> void aarch64_init_fcmla_laneq_builtins ( void ) { unsigned int i = 0 ; for ( i = 0 ; i < ARRAY_SIZE ( aarch64_fcmla_lane_builtin_data ) ; ++ i ) { aarch64_fcmla_laneq_builtin_datum * d = & aarch64_fcmla_lane_builtin_data [ i ] ; tree argtype = aarch64_lookup_simd_builtin_type ( d -> mode , qualifier_none ) ; machine_mode quadmode = GET_MODE_2XWIDER_MODE ( d -> mode ) . require ( ) ; tree quadtype = aarch64_lookup_simd_builtin_type ( quadmode , qualifier_none ) ; tree lanetype = aarch64_simd_builtin_std_type ( SImode , qualifier_lane_pair_index ) ; tree ftype = build_function_type_list ( argtype , argtype , argtype , quadtype , lanetype , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_FP , d -> mode ) ; tree fndecl = aarch64_general_add_builtin ( d -> name , ftype , d -> fcode , attrs ) ; aarch64_builtin_decls [ d -> fcode ] = fndecl ; } } </s>

Due to the architecture not providing lane variant of the lane instructions for fcmla we ca n't use the standard simd builtin expansion code , but we still want the majority of the validation that would normally be done .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


"PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG."

"PRINT_OPERAND_ADDRESS, invalid insn #2"

"PRINT_OPERAND_ADDRESS, invalid insn #1"

A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory reference whose address is ADDR . ADDR is an RTL expression .


<s> static int dispatch_function_versions ( tree dispatch_decl , void * fndecls_p , basic_block * empty_bb ) { tree default_decl ; gimple * ifunc_cpu_init_stmt ; gimple_seq gseq ; int ix ; tree ele ; vec < tree > * fndecls ; unsigned int num_versions = 0 ; unsigned int actual_versions = 0 ; unsigned int i ; struct _function_version_info { tree version_decl ; tree predicate_chain ; unsigned int dispatch_priority ; } * function_version_info ; gcc_assert ( dispatch_decl != NULL && fndecls_p != NULL && empty_bb != NULL ) ; fndecls = static_cast < vec < tree > * > ( fndecls_p ) ; num_versions = fndecls -> length ( ) ; gcc_assert ( num_versions >= 2 ) ; function_version_info = ( struct _function_version_info * ) XNEWVEC ( struct _function_version_info , ( num_versions - 1 ) ) ; default_decl = ( * fndecls ) [ 0 ] ; push_cfun ( DECL_STRUCT_FUNCTION ( dispatch_decl ) ) ; gseq = bb_seq ( * empty_bb ) ; ifunc_cpu_init_stmt = gimple_build_call_vec ( get_ix86_builtin ( IX86_BUILTIN_CPU_INIT ) , vNULL ) ; gimple_seq_add_stmt ( & gseq , ifunc_cpu_init_stmt ) ; gimple_set_bb ( ifunc_cpu_init_stmt , * empty_bb ) ; set_bb_seq ( * empty_bb , gseq ) ; pop_cfun ( ) ; for ( ix = 1 ; fndecls -> iterate ( ix , & ele ) ; ++ ix ) { tree version_decl = ele ; tree predicate_chain = NULL_TREE ; unsigned int priority ; priority = get_builtin_code_for_version ( version_decl , & predicate_chain ) ; if ( predicate_chain == NULL_TREE ) continue ; function_version_info [ actual_versions ] . version_decl = version_decl ; function_version_info [ actual_versions ] . predicate_chain = predicate_chain ; function_version_info [ actual_versions ] . dispatch_priority = priority ; actual_versions ++ ; } qsort ( function_version_info , actual_versions , sizeof ( struct _function_version_info ) , feature_compare ) ; for ( i = 0 ; i < actual_versions ; ++ i ) * empty_bb = add_condition_to_bb ( dispatch_decl , function_version_info [ i ] . version_decl , function_version_info [ i ] . predicate_chain , * empty_bb ) ; * empty_bb = add_condition_to_bb ( dispatch_decl , default_decl , NULL , * empty_bb ) ; free ( function_version_info ) ; return 0 ; } </s>

This function generates the dispatch function for multi-versioned functions . DISPATCH_DECL is the function which will contain the dispatch logic . FNDECLS are the function choices for dispatch , and is a tree chain . EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch code is generated .


<s> bool X86InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; switch ( MI -> getOpcode ( ) ) { case X86 :: V_SET0 : return Expand2AddrUndef ( MI , get ( HasAVX ? X86 :: VPXORrr : X86 :: PXORrr ) ) ; case X86 :: TEST8ri_NOREX : MI -> setDesc ( get ( X86 :: TEST8ri ) ) ; return true ; } return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static void i386_solaris_elf_named_section ( const char * name , unsigned int flags , tree decl ) { if ( TARGET_64BIT && strcmp ( name , ".eh_frame" ) == 0 ) { fprintf ( asm_out_file , "\t.section\t%s,\"%s\",@unwind\n" , name , flags & SECTION_WRITE ? "aw" : "a" ) ; return ; } default_elf_asm_named_section ( name , flags , decl ) ; } </s>

Solaris named-section hook . Parameters are as for named_section_real .


<s> bool AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { if ( Subtarget -> hasLSE ( ) ) return false ; return getTargetMachine ( ) . getOptLevel ( ) != 0 ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> void MipsPassConfig :: addPreSched2 ( ) { addPass ( createMipsExpandPseudoPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


Hook to validate attribute ( ( target ( `` ... '' ) ) ) .


<s> bool PPCTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createPPCISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void AMDGPUSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , MachineInstr * begin , MachineInstr * end , unsigned NumRegionInstrs ) const { if ( getGeneration ( ) >= SOUTHERN_ISLANDS ) { Policy . ShouldTrackPressure = true ; Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; } } </s>

Override generic scheduling policy within a region .


<s> bool NVPTXAsmPrinter :: doInitialization ( Module & M ) { SmallString < 128 > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( OutContext , * TM . getTargetData ( ) ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( nvptxSubtarget . getDrvInterface ( ) == NVPTX :: CUDA ) recordAndEmitFilenames ( M ) ; SmallString < 128 > Str2 ; raw_svector_ostream OS2 ( Str2 ) ; emitDeclarations ( M , OS2 ) ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) printModuleLevelGV ( I , OS2 ) ; OS2 << '\n' ; OutStreamer . EmitRawText ( OS2 . str ( ) ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


"Missing init of reg %u inserted: insn %u\n"

Find uses of regs that are not defined on all incoming paths , and insert a corresponding def at function entry . Advantage : Simple . Disadvantage : Potentially creates long live ranges . May not catch all cases . F.i . a clobber cuts a live range in the compiler and may prevent entry_lr_in from being set for a reg , but the clobber does not translate to a ptx insn , so in ptx there still may be an uninitialized ptx reg . See f.i . gcc.c-torture/compile/20020926-1.c .


<s> Optional < MCFixupKind > ELFPPCAsmBackend :: getFixupKind ( StringRef Name ) const { if ( TT . isOSBinFormatELF ( ) ) { unsigned Type ; if ( TT . isPPC64 ( ) ) { Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_PPC64_NONE ) . Case ( "BFD_RELOC_16" , ELF :: R_PPC64_ADDR16 ) . Case ( "BFD_RELOC_32" , ELF :: R_PPC64_ADDR32 ) . Case ( "BFD_RELOC_64" , ELF :: R_PPC64_ADDR64 ) . Default ( - 1u ) ; } else { Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_PPC_NONE ) . Case ( "BFD_RELOC_16" , ELF :: R_PPC_ADDR16 ) . Case ( "BFD_RELOC_32" , ELF :: R_PPC_ADDR32 ) . Default ( - 1u ) ; } if ( Type != - 1u ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return None ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s>
SDValue
SystemZTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

SystemZ
SystemZ
ISD::InputArg
"Unsupported calling convention"


<s>
const
char
*
nds32_output_double
(
rtx
*
operands
,
bool
load_p
)
{
char
pattern
[
100
]
;
int
reg
=
load_p
0
:
1
;
int
mem
=
load_p
1
:
0
;
rtx
otherops
[
3
]
;
rtx
addr
=
XEXP
(
operands
[
mem
]
,
0
)
;
otherops
[
0
]
=
gen_rtx_REG
(
SImode
,
REGNO
(
operands
[
reg
]
)
)
;
otherops
[
1
]
=
gen_rtx_REG
(
SImode
,
REGNO
(
operands
[
reg
]
)
+
1
)
;
if
(
GET_CODE
(
addr
)
==
POST_INC
)
{
otherops
[
2
]
=
XEXP
(
addr
,
0
)
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"%cmw.bim\t%%0, [%%2], %%1, 0"
,
load_p
'l'
:
's'
)
;
}
else
{
otherops
[
2
]
=
addr
;
snprintf
(
pattern
,
sizeof
(
pattern
)
,
"%cmw.bi\t%%0, [%%2], %%1, 0"
,
load_p
'l'
:
's'
)
;
}
output_asm_insn
(
pattern
,
otherops
)
;
return
""
;
}
</s>

Using multiple load/store instruction to output doubleword instruction .


<s> unsigned SparcInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( MI -> getOpcode ( ) == SP :: LDri || MI -> getOpcode ( ) == SP :: LDFri || MI -> getOpcode ( ) == SP :: LDDFri ) { if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
SDValue
TLCS900TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
SHL
:
case
ISD
::
SRL
:
case
ISD
::
SRA
:
return
LowerShifts
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SIGN_EXTEND
:
return
LowerSIGN_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

TLCS900
TLCS900
ISD::SHL
ISD::SRL
ISD::SRA
ISD::GlobalAddress
ISD::BlockAddress
ISD::ExternalSymbol
ISD::SETCC
ISD::BR_CC
ISD::SELECT_CC
ISD::SIGN_EXTEND
ISD::RETURNADDR
ISD::FRAMEADDR
"unimplemented operand"


<s> void ix86_expand_unary_operator ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { bool matching_memory = false ; rtx src , dst , op , clob ; dst = operands [ 0 ] ; src = operands [ 1 ] ; if ( MEM_P ( dst ) ) { if ( rtx_equal_p ( dst , src ) ) matching_memory = true ; else dst = gen_reg_rtx ( mode ) ; } if ( MEM_P ( src ) && ! matching_memory ) src = force_reg ( mode , src ) ; op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_e ( code , mode , src ) ) ; if ( reload_in_progress || code == NOT ) { gcc_assert ( code == NOT ) ; emit_insn ( op ) ; } else { clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , FLAGS_REG ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; } if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , dst ) ; } </s>

Attempt to expand a unary operator . Make the expansion closer to the actual machine , then just general_operand , which will allow 2 separate memory references ( one output , one input ) in a single insn .


<s> bool M68kSubtarget :: isLegalToCallImmediateAddr ( ) const { return true ; } </s>

Return true if the subtarget allows calls to immediate address .


<s> void rs6000_emit_le_vsx_store ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_src , permute_tmp ; gcc_assert ( ! reload_in_progress && ! lra_in_progress && ! reload_completed ) ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = adjust_address ( dest , V2DImode , 0 ) ; source = gen_lowpart ( V2DImode , source ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( source ) : source ; permute_src = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_tmp = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( tmp , permute_src ) ) ; emit_insn ( gen_rtx_SET ( dest , permute_tmp ) ) ; } </s>

Emit a little-endian store to vector memory location DEST from VSX register SOURCE in mode MODE . The store is done with two permuting insn 's that represent an xxpermdi and an stxvd2x .