<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> int GCNTTIImpl :: getMinMaxReductionCost ( Type * Ty , Type * CondTy , bool IsPairwise , bool IsUnsigned ) { EVT OrigTy = TLI -> getValueType ( DL , Ty ) ; if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != 16 ) return BaseT :: getMinMaxReductionCost ( Ty , CondTy , IsPairwise , IsUnsigned ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; return LT . first * getHalfRateInstrCost ( ) ; } </s>

Try to calculate op costs for min/max reduction operations .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto DL = MF . getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned Idx = 0 ; for ( const auto & Arg : F . args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) || VRegs [ Idx ] . size ( ) > 1 ) return false ; ArgInfo OrigArg ( VRegs [ Idx ] , Arg . getType ( ) ) ; setArgFlags ( OrigArg , Idx + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; X86OutgoingValueAssigner Assigner ( CC_X86 ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> static bool arc_store_addr_hazard_internal_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx in_set , out_set ; rtx out_addr , in_addr ; if ( ! producer ) return false ; if ( ! consumer ) return false ; out_set = single_set ( producer ) ; if ( out_set ) { out_addr = SET_DEST ( out_set ) ; if ( ! out_addr ) return false ; if ( GET_CODE ( out_addr ) == ZERO_EXTEND || GET_CODE ( out_addr ) == SIGN_EXTEND ) out_addr = XEXP ( out_addr , 0 ) ; if ( ! MEM_P ( out_addr ) ) return false ; in_set = single_set ( consumer ) ; if ( in_set ) { in_addr = SET_SRC ( in_set ) ; if ( ! in_addr ) return false ; if ( GET_CODE ( in_addr ) == ZERO_EXTEND || GET_CODE ( in_addr ) == SIGN_EXTEND ) in_addr = XEXP ( in_addr , 0 ) ; if ( ! MEM_P ( in_addr ) ) return false ; in_addr = XEXP ( in_addr , 0 ) ; out_addr = XEXP ( out_addr , 0 ) ; return exp_equiv_p ( in_addr , out_addr , 0 , true ) ; } } return false ; } </s>

Return true if a load instruction ( CONSUMER ) uses the same address as a store instruction ( PRODUCER ) . This function is used to avoid st/ld address hazard in ARC700 cores .


<s>
bool
AArch64BranchRelaxation
::
runOnMachineFunction
(
MachineFunction
&
mf
)
{
MF
=
&
mf
;
if
(
!
BranchRelaxation
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"***** AArch64BranchRelaxation *****\n"
)
;
TII
=
(
const
AArch64InstrInfo
*
)
MF
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
MF
->
RenumberBlocks
(
)
;
scanFunction
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks before relaxation\n"
)
;
DEBUG
(
dumpBBs
(
)
)
;
bool
MadeChange
=
false
;
while
(
relaxBranchInstructions
(
)
)
MadeChange
=
true
;
verify
(
)
;
DEBUG
(
dbgs
(
)
<<
"  Basic blocks after relaxation\n"
)
;
DEBUG
(
dbgs
(
)
<<
'\n'
;
dumpBBs
(
)
)
;
BlockInfo
.
clear
(
)
;
return
MadeChange
;
}
</s>

runOnMachineFunction - Emit the function body .


<s>
void
SIRegisterInfo
::
resolveFrameIndex
(
MachineInstr
&
MI
,
Register
BaseReg
,
int64_t
Offset
)
const
{
const
SIInstrInfo
*
TII
=
ST
.
getInstrInfo
(
)
;
bool
IsFlat
=
TII
->
isFLATScratch
(
MI
)
;
bool
SeenFI
=
false
;
for
(
const
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
MO
.
isFI
(
)
)
{
if
(
SeenFI
)
llvm_unreachable
(
"should not see multiple frame indices"
)
;
SeenFI
=
true
;
}
}
MachineOperand
*
FIOp
=
TII
->
getNamedOperand
(
MI
,
IsFlat
AMDGPU
::
OpName
::
saddr
:
AMDGPU
::
OpName
::
vaddr
)
;
MachineOperand
*
OffsetOp
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
offset
)
;
int64_t
NewOffset
=
OffsetOp
->
getImm
(
)
+
Offset
;
assert
(
FIOp
&&
FIOp
->
isFI
(
)
&&
"frame index must be address operand"
)
;
assert
(
TII
->
isMUBUF
(
MI
)
||
TII
->
isFLATScratch
(
MI
)
)
;
if
(
IsFlat
)
{
assert
(
TII
->
isLegalFLATOffset
(
NewOffset
,
AMDGPUAS
::
PRIVATE_ADDRESS
,
SIInstrFlags
::
FlatScratch
)
&&
"offset should be legal"
)
;
FIOp
->
ChangeToRegister
(
BaseReg
,
false
)
;
OffsetOp
->
setImm
(
NewOffset
)
;
return
;
}
MachineOperand
*
SOffset
=
TII
->
getNamedOperand
(
MI
,
AMDGPU
::
OpName
::
soffset
)
;
assert
(
SOffset
->
isImm
(
)
&&
SOffset
->
getImm
(
)
==
0
)
;
assert
(
SIInstrInfo
::
isLegalMUBUFImmOffset
(
NewOffset
)
&&
"offset should be legal"
)
;
FIOp
->
ChangeToRegister
(
BaseReg
,
false
)
;
OffsetOp
->
setImm
(
NewOffset
)
;
}
</s>

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .

AMDGPU
SI
SI
"should not see multiple frame indices"
AMDGPU::OpName
AMDGPU::OpName
AMDGPU::OpName
"frame index must be address operand"
AMDGPU
SIInstrFlags::FlatScratch
"offset should be legal"
AMDGPU::OpName
0
SI
"offset should be legal"


<s> static const char * alpha_mangle_type ( const_tree type ) { if ( TYPE_MAIN_VARIANT ( type ) == long_double_type_node && TARGET_LONG_DOUBLE_128 ) return "g" ; return NULL ; } </s>


<s> void arc_asm_output_aligned_decl_local ( FILE * stream , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned HOST_WIDE_INT align , unsigned HOST_WIDE_INT globalize_p ) { int in_small_data = arc_in_small_data_p ( decl ) ; if ( in_small_data ) switch_to_section ( get_named_section ( NULL , ".sbss" , 0 ) ) ; else switch_to_section ( bss_section ) ; if ( globalize_p ) ( * targetm . asm_out . globalize_label ) ( stream , name ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( ( align ) / BITS_PER_UNIT ) ) ; ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , "object" ) ; ASM_OUTPUT_SIZE_DIRECTIVE ( stream , name , size ) ; ASM_OUTPUT_LABEL ( stream , name ) ; if ( size != 0 ) ASM_OUTPUT_SKIP ( stream , size ) ; } </s>


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> static bool ix86_push_argument ( unsigned int npush ) { return ( ( ! TARGET_SSE2 || npush < ( TARGET_64BIT ? 16 : 8 ) ) && TARGET_PUSH_ARGS && ! ACCUMULATE_OUTGOING_ARGS ) ; } </s>


<s> unsigned int compute_a_rotate_length ( rtx * operands ) { rtx src = operands [ 1 ] ; rtx amount_rtx = operands [ 2 ] ; enum machine_mode mode = GET_MODE ( src ) ; int amount ; unsigned int length = 0 ; gcc_assert ( GET_CODE ( amount_rtx ) == CONST_INT ) ; amount = INTVAL ( amount_rtx ) ; if ( amount < 0 ) amount = 0 ; if ( ( unsigned int ) amount > GET_MODE_BITSIZE ( mode ) ) amount = GET_MODE_BITSIZE ( mode ) ; if ( ( unsigned int ) amount > GET_MODE_BITSIZE ( mode ) / ( unsigned ) 2 ) amount = GET_MODE_BITSIZE ( mode ) - amount ; if ( ( mode == HImode && TARGET_H8300 && amount >= 5 ) || ( mode == HImode && TARGET_H8300H && amount >= 6 ) || ( mode == HImode && TARGET_H8300S && amount == 8 ) || ( mode == SImode && TARGET_H8300H && amount >= 10 ) || ( mode == SImode && TARGET_H8300S && amount >= 13 ) ) { amount = GET_MODE_BITSIZE ( mode ) / 2 - amount ; length += 6 ; } if ( TARGET_H8300S ) amount = amount / 2 + amount % 2 ; length += amount * ( ( TARGET_H8300 && mode == HImode ) ? 6 : 2 ) ; return length ; } </s>


<s>
bool
WinEHStatePass
::
runOnFunction
(
Function
&
F
)
{
if
(
!
F
.
hasPersonalityFn
(
)
)
return
false
;
PersonalityFn
=
dyn_cast
<
Function
>
(
F
.
getPersonalityFn
(
)
->
stripPointerCasts
(
)
)
;
if
(
!
PersonalityFn
)
return
false
;
Personality
=
classifyEHPersonality
(
PersonalityFn
)
;
if
(
!
isFuncletEHPersonality
(
Personality
)
)
return
false
;
bool
HasPads
=
false
;
for
(
BasicBlock
&
BB
:
F
)
{
if
(
BB
.
isEHPad
(
)
)
{
HasPads
=
true
;
break
;
}
}
if
(
!
HasPads
)
return
false
;
F
.
addFnAttr
(
"no-frame-pointer-elim"
,
"true"
)
;
emitExceptionRegistrationRecord
(
&
F
)
;
auto
*
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
std
::
unique_ptr
<
WinEHFuncInfo
>
FuncInfoPtr
;
if
(
!
MMI
)
FuncInfoPtr
.
reset
(
new
WinEHFuncInfo
(
)
)
;
WinEHFuncInfo
&
FuncInfo
=
*
(
MMI
&
MMI
->
getWinEHFuncInfo
(
&
F
)
:
FuncInfoPtr
.
get
(
)
)
;
FuncInfo
.
EHRegNode
=
RegNode
;
switch
(
Personality
)
{
default
:
llvm_unreachable
(
"unexpected personality function"
)
;
case
EHPersonality
::
MSVC_CXX
:
addCXXStateStores
(
F
,
FuncInfo
)
;
break
;
case
EHPersonality
::
MSVC_X86SEH
:
addSEHStateStores
(
F
,
FuncInfo
)
;
break
;
}
PersonalityFn
=
nullptr
;
Personality
=
EHPersonality
::
Unknown
;
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s>
MCSymbol
*
MSP430MCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
assert
(
0
&&
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .


<s> unsigned AlphaInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { case Alpha :: LDL : case Alpha :: LDQ : case Alpha :: LDBU : case Alpha :: LDWU : case Alpha :: LDS : case Alpha :: LDT : if ( MI -> getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .

Alpha Alpha Alpha::LDL Alpha::LDQ Alpha::LDBU Alpha::LDWU Alpha::LDS Alpha::LDT 1 1 0 0


<s> static bool use_helper_for_const_shift ( machine_mode mode , HOST_WIDE_INT amt ) { const int default_inline_shift = 4 ; int user_set_max_inline = ( msp430_max_inline_shift == 65 ? 0 : 1 ) ; int max_inline = ( user_set_max_inline ? msp430_max_inline_shift : default_inline_shift ) ; int max_inline_32 = max_inline / 2 ; if ( mode == E_DImode ) return true ; if ( ( mode == E_QImode || mode == E_HImode || mode == E_PSImode ) && ( msp430x || amt <= max_inline || ( ! user_set_max_inline && ( optimize >= 2 && ! optimize_size ) ) ) ) return false ; if ( mode == E_SImode && ( amt <= max_inline_32 || ( ! user_set_max_inline && ( optimize >= 2 && ! optimize_size ) && amt <= 15 ) ) ) return false ; return true ; } </s>

Return TRUE if the helper function should be used and FALSE if the shifts insns should be emitted inline .


<s> bool R600InstrInfo :: isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumCyles , BranchProbability Probability ) const { return true ; } </s>

Return true if it 's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion .


<s> enum reg_class ia64_secondary_reload_class ( enum reg_class rclass , machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { int regno = - 1 ; if ( GET_CODE ( x ) == REG || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; switch ( rclass ) { case BR_REGS : case AR_M_REGS : case AR_I_REGS : if ( regno >= 0 && ! GENERAL_REGNO_P ( regno ) ) return GR_REGS ; if ( GET_CODE ( x ) == MEM ) return GR_REGS ; break ; case FR_REGS : case FP_REGS : if ( regno >= 0 && ! ( FR_REGNO_P ( regno ) || GENERAL_REGNO_P ( regno ) ) ) return GR_REGS ; if ( GET_CODE ( x ) == MEM && ( GET_MODE ( x ) == SImode || GET_MODE ( x ) == HImode || GET_MODE ( x ) == QImode ) ) return GR_REGS ; if ( GET_CODE ( x ) == CONST_INT ) return GR_REGS ; if ( GET_CODE ( x ) == PLUS ) return GR_REGS ; break ; case PR_REGS : if ( GET_CODE ( x ) == MEM ) return GR_REGS ; if ( regno >= 0 && ! GENERAL_REGNO_P ( regno ) && ! PR_REGNO_P ( regno ) ) return GR_REGS ; break ; default : break ; } return NO_REGS ; } </s>

This function returns the register class required for a secondary register when copying between one of the registers in CLASS , and X , using MODE . A return value of NO_REGS means that no secondary register is required .


<s> static rtx arc_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int arg_num = * cum ; rtx ret ; const char * debstr ATTRIBUTE_UNUSED ; arg_num = ROUND_ADVANCE_CUM ( arg_num , mode , type ) ; if ( mode == VOIDmode ) { ret = const0_rtx ; debstr = "<0>" ; } else if ( GPR_REST_ARG_REGS ( arg_num ) > 0 ) { ret = gen_rtx_REG ( mode , arg_num ) ; debstr = reg_names [ arg_num ] ; } else { ret = NULL_RTX ; debstr = "memory" ; } return ret ; } </s>

On the ARC the first MAX_ARC_PARM_REGS args are normally in registers and the rest are pushed .


<s> int nds32_target_alignment ( rtx label ) { rtx_insn * insn ; if ( optimize_size ) return 0 ; insn = next_active_insn ( label ) ; if ( insn == 0 ) return 0 ; else if ( ( get_attr_length ( insn ) % 4 ) == 0 ) return 2 ; else return 0 ; } </s>

Return align 2 ( log base 2 ) if the next instruction of LABEL is 4 byte .


<s> tree gimple_folder :: load_store_cookie ( tree type ) { return build_int_cst ( build_pointer_type ( type ) , TYPE_ALIGN_UNIT ( type ) ) ; } </s>

Return the alignment and TBAA argument to an internal load or store function like IFN_MASK_LOAD or IFN_MASK_STORE , given that it accesses memory elements of type TYPE .


<s> bool HexagonFrameLowering :: hasTailCall ( MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; unsigned RetOpcode = MBBI -> getOpcode ( ) ; return RetOpcode == Hexagon :: TCRETURNi || RetOpcode == Hexagon :: TCRETURNr ; } </s>

Returns true if the function contains a tail call .

Hexagon Hexagon Hexagon::TCRETURNi Hexagon::TCRETURNr


<s> const CallLowering * getCallLowering ( ) const override { return CallLoweringInfo . get ( ) ; } </s>


<s> const RISCVRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
MachineBasicBlock
*
M680x0TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
M680x0
::
CMOV8d
:
case
M680x0
::
CMOV16d
:
case
M680x0
::
CMOV32r
:
return
EmitLoweredSelect
(
MI
,
BB
)
;
case
M680x0
::
SALLOCA
:
return
EmitLoweredSegAlloca
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> const TargetRegisterClass * TGSIRegisterInfo :: getCFGStructurizerRegClass ( MVT VT ) const { switch ( VT . SimpleTy ) { default : case MVT :: i32 : return & TGSI :: IRegsRegClass ; } } </s>

get the register class of the specified type to use in the CFGStructurizer


<s> StringRef getPassName ( ) const override { return "AMDGPURegBankCombiner" ; } </s>

getPassName - Return a nice clean name for a pass .


<s>
static
void
ix86_function_specific_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
char
*
target_string
=
ix86_target_string
(
ptr
->
x_ix86_isa_flags
,
ptr
->
x_ix86_isa_flags2
,
ptr
->
x_target_flags
,
ptr
->
x_ix86_target_flags
,
,
,
ptr
->
x_ix86_fpmath
,
false
)
;
gcc_assert
(
ptr
->
arch
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*sarch = %d (%s)\n"
,
indent
,
""
,
ptr
->
arch
,
processor_target_table
[
ptr
->
arch
]
.
name
)
;
gcc_assert
(
ptr
->
tune
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*stune = %d (%s)\n"
,
indent
,
""
,
ptr
->
tune
,
processor_target_table
[
ptr
->
tune
]
.
name
)
;
fprintf
(
file
,
"%*sbranch_cost = %d\n"
,
indent
,
""
,
ptr
->
branch_cost
)
;
if
(
target_string
)
{
fprintf
(
file
,
"%*s%s\n"
,
indent
,
""
,
target_string
)
;
free
(
target_string
)
;
}
}
</s>


<s> int expand_block_clear ( rtx operands [ ] ) { rtx orig_dest = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx align_rtx = operands [ 3 ] ; bool constp = CONST_INT_P ( bytes_rtx ) ; HOST_WIDE_INT align ; HOST_WIDE_INT bytes ; int offset ; int clear_bytes ; int clear_step ; if ( ! constp ) return 0 ; gcc_assert ( CONST_INT_P ( align_rtx ) ) ; align = INTVAL ( align_rtx ) * BITS_PER_UNIT ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= 0 ) return 1 ; if ( TARGET_ALTIVEC && ( align >= 128 || TARGET_EFFICIENT_UNALIGNED_VSX ) ) clear_step = 16 ; else if ( TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) clear_step = 8 ; else clear_step = 4 ; if ( optimize_size && bytes > 3 * clear_step ) return 0 ; if ( ! optimize_size && bytes > 8 * clear_step ) return 0 ; bool unaligned_vsx_ok = ( bytes >= 32 && TARGET_EFFICIENT_UNALIGNED_VSX ) ; for ( offset = 0 ; bytes > 0 ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( TARGET_ALTIVEC && ( bytes >= 16 && ( align >= 128 || unaligned_vsx_ok ) ) ) { clear_bytes = 16 ; mode = V4SImode ; } else if ( bytes >= 8 && TARGET_POWERPC64 && ( align >= 64 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 8 ; mode = DImode ; if ( offset == 0 && align < 64 ) { rtx addr ; addr = XEXP ( orig_dest , 0 ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , 1 ) ) && ( INTVAL ( XEXP ( addr , 1 ) ) & 3 ) != 0 ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } } else if ( bytes >= 4 && ( align >= 32 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 4 ; mode = SImode ; } else if ( bytes >= 2 && ( align >= 16 || ! STRICT_ALIGNMENT ) ) { clear_bytes = 2 ; mode = HImode ; } else { clear_bytes = 1 ; mode = QImode ; } dest = adjust_address ( orig_dest , mode , offset ) ; emit_move_insn ( dest , CONST0_RTX ( mode ) ) ; } return 1 ; } </s>

Expand a block clear operation , and return 1 if successful . Return 0 if we should let the compiler generate normal code . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 3 ] is the alignment


<s> unsigned getNumberOfRegisters ( bool Vector ) const override { if ( Vector ) { if ( ST -> hasNEON ( ) ) return 32 ; return 0 ; } return 31 ; } </s>


<s> bool AArch64TargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { return true ; } </s>

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass .


<s> static bool isReachable ( const MachineInstr * From , const MachineInstr * To , const MachineBasicBlock * CutOff , MachineDominatorTree & MDT ) { if ( MDT . dominates ( From , To ) ) return true ; const MachineBasicBlock * MBBFrom = From -> getParent ( ) ; const MachineBasicBlock * MBBTo = To -> getParent ( ) ; return searchPredecessors ( MBBTo , CutOff , [ MBBFrom ] ( const MachineBasicBlock * MBB ) { return MBB == MBBFrom ; } ) ; } </s>

Returns true if instruction is reachable from entry .


<s> const MCPhysReg * MipsRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_SaveList ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_SaveList ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_SaveList ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_SaveList ; return CSR_O32_SaveList ; } </s>


<s> bool HexagonInstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr & MIa , MachineInstr & MIb , AliasAnalysis * AA ) const { int OffsetA = 0 , OffsetB = 0 ; unsigned SizeA = 0 , SizeB = 0 ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; if ( MIa . mayLoad ( ) && ! isMemOp ( MIa ) && MIb . mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BaseRegA = getBaseAndOffset ( MIa , OffsetA , SizeA ) ; if ( ! BaseRegA || ! SizeA ) return false ; unsigned BaseRegB = getBaseAndOffset ( MIb , OffsetB , SizeB ) ; if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return ( SizeA <= offDiff ) ; } return false ; } </s>

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const MCExpr * AArch64TargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr ) { return ConstantPools -> addEntry ( Streamer , Expr ) ; } </s>

Add a new entry to the constant pool for the current section and return an MCExpr that can be used to refer to the constant pool location .


<s> static int get_mode_no_for_insn ( rtx_insn * insn ) { rtx reg , mem , mode_rtx ; int mode_no ; bool extend_p ; extract_insn_cached ( insn ) ; if ( recog_data . n_operands != 2 ) return - 1 ; reg = recog_data . operand [ 0 ] ; mem = recog_data . operand [ 1 ] ; if ( get_attr_speculable1 ( insn ) == SPECULABLE1_YES ) { if ( ! reload_completed ) { if ( ! REG_P ( reg ) || AR_REGNO_P ( REGNO ( reg ) ) ) return - 1 ; if ( ! MEM_P ( mem ) ) return - 1 ; { rtx mem_reg = XEXP ( mem , 0 ) ; if ( ! REG_P ( mem_reg ) ) return - 1 ; } mode_rtx = mem ; } else if ( get_attr_speculable2 ( insn ) == SPECULABLE2_YES ) { gcc_assert ( REG_P ( reg ) && MEM_P ( mem ) ) ; mode_rtx = mem ; } else return - 1 ; } else if ( get_attr_data_speculative ( insn ) == DATA_SPECULATIVE_YES || get_attr_control_speculative ( insn ) == CONTROL_SPECULATIVE_YES || get_attr_check_load ( insn ) == CHECK_LOAD_YES ) { gcc_assert ( REG_P ( reg ) && MEM_P ( mem ) ) ; mode_rtx = mem ; } else { enum attr_itanium_class attr_class = get_attr_itanium_class ( insn ) ; if ( attr_class == ITANIUM_CLASS_CHK_A || attr_class == ITANIUM_CLASS_CHK_S_I || attr_class == ITANIUM_CLASS_CHK_S_F ) mode_rtx = reg ; else return - 1 ; } mode_no = ia64_mode_to_int ( GET_MODE ( mode_rtx ) ) ; if ( mode_no == SPEC_MODE_INVALID ) return - 1 ; extend_p = ( GET_MODE ( reg ) != GET_MODE ( mode_rtx ) ) ; if ( extend_p ) { if ( ! ( SPEC_MODE_FOR_EXTEND_FIRST <= mode_no && mode_no <= SPEC_MODE_FOR_EXTEND_LAST ) ) return - 1 ; mode_no += SPEC_GEN_EXTEND_OFFSET ; } return mode_no ; } </s>

If INSN is an appropriate load return its mode . Return -1 otherwise .


<s> static bool get_default_ta ( ) { return ( bool ) ( get_prefer_tail_policy ( ) & 0x1 || ( get_prefer_tail_policy ( ) >> 1 & 0x1 ) ) ; } </s>


"Basic block should contain at least a RET but is empty"

runOnMachineFunction - Emit the function body .


"the ABI for passing parameters with %d-byte"

Gives the alignment boundary , in bits , of an argument with the specified mode and type .


<s> SDValue MipsTargetLowering :: getTargetNode ( ConstantPoolSDNode * N , EVT Ty , SelectionDAG & DAG , unsigned Flag ) const { return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flag ) ; } </s>

Retrieve the target node this edge connects to .


<s> std :: pair < unsigned , const TargetRegisterClass * > MipsTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , Mips :: CPURegsRegisterClass ) ; case 'f' : if ( VT == MVT :: f32 ) return std :: make_pair ( 0U , Mips :: FGR32RegisterClass ) ; if ( VT == MVT :: f64 ) if ( ( ! Subtarget -> isSingleFloat ( ) ) && ( ! Subtarget -> isFP64bit ( ) ) ) return std :: make_pair ( 0U , Mips :: AFGR64RegisterClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static int indirectable_constant_address_p ( rtx x ) { return CONSTANT_ADDRESS_P ( x ) ; } </s>

Re-definition of CONSTANT_ADDRESS_P , which is true only when there are no SYMBOL_REFs for external symbols present .


"Disqualifying LR because GPR0 is live "


<s>
bool
F2003fFiMalkrz
::
runOnMachineFunction
(
MachineFunction
&
F
)
{
const
F2003fInstrInfo
&
TII
=
*
static_cast
<
const
F2003fInstrInfo
*
>
(
F
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
for
(
auto
&
BB
:
F
)
{
for
(
MachineBasicBlock
::
iterator
I
=
BB
.
begin
(
)
;
I
!=
BB
.
end
(
)
;
)
{
MachineInstr
&
MI
=
*
I
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
Opc
=
MI
.
getOpcode
(
)
;
unsigned
FiOpc
=
TII
.
getFiFromFiMalkrz
(
Opc
)
;
if
(
FiOpc
!=
F2003f
::
INSTRUCTION_LIST_END
)
{
DEBUG
(
dbgs
(
)
<<
"Expand: "
)
;
DEBUG
(
MI
.
dump
(
)
)
;
MIBundleBuilder
Bundle
(
BB
,
I
)
;
unsigned
MalkrzOpc
=
TII
.
getMalkrzFromFiMalkrz
(
Opc
)
;
unsigned
MalkrzNumOperands
=
TII
.
get
(
MalkrzOpc
)
.
getNumOperands
(
)
;
MachineInstrBuilder
Malkrz
=
BuildMI
(
F
,
DL
,
TII
.
get
(
MalkrzOpc
)
)
;
for
(
unsigned
i
=
0
;
i
<
MalkrzNumOperands
;
i
++
)
{
Malkrz
.
add
(
MI
.
getOperand
(
i
)
)
;
}
Bundle
.
prepend
(
Malkrz
)
;
unsigned
FiNumOperands
=
TII
.
get
(
FiOpc
)
.
getNumOperands
(
)
;
MachineInstrBuilder
Fi
=
BuildMI
(
F
,
DL
,
TII
.
get
(
FiOpc
)
)
;
for
(
unsigned
i
=
0
;
i
<
FiNumOperands
;
i
++
)
{
Fi
.
add
(
MI
.
getOperand
(
i
+
MalkrzNumOperands
)
)
;
}
Bundle
.
prepend
(
Fi
)
;
I
=
BB
.
erase
(
MI
)
;
}
else
{
++
I
;
}
}
}
return
true
;
}
</s>


<s> virtual void Reset ( ) { ResourceAssignment :: Reset ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> unsigned getEUsPerCU ( ) const { return AMDGPU :: IsaInfo :: getEUsPerCU ( getFeatureBits ( ) ) ; } </s>

Number of SIMDs/EUs ( execution units ) per `` CU '' ( `` compute unit '' ) , where the `` CU '' is the unit onto which workgroups are mapped .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> rtx m32c_function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { enum machine_mode mode = TYPE_MODE ( valtype ) ; return m32c_libcall_value ( mode ) ; } </s>

Implements FUNCTION_VALUE . Functions and libcalls have the same conventions .


<s> bool m68k_legitimate_constant_p ( machine_mode mode , rtx x ) { return mode != XFmode && ! m68k_illegitimate_symbolic_constant_p ( x ) ; } </s>


<s> bool ARMBaseInstrInfo :: hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; unsigned UDomain = UseMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Subtarget . isCortexA8 ( ) && ( DDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainVFP ) ) return true ; int Latency = computeOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx , false ) ; if ( Latency < 0 ) Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency <= 3 ) return false ; return DDomain == ARMII :: DomainVFP || DDomain == ARMII :: DomainNEON || UDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainNEON ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .

ARM ARM ARMII::DomainMask ARMII::DomainMask ARMII::DomainVFP ARMII::DomainVFP 0 3 ARMII::DomainVFP ARMII::DomainNEON ARMII::DomainVFP ARMII::DomainNEON


<s> const LatticeCell & get ( Register R ) const { if ( ! R . isVirtual ( ) ) return Bottom ; MapType :: const_iterator F = Map . find ( R ) ; if ( F != Map . end ( ) ) return F -> second ; return Top ; } </s>

Get the generated Value for a given VPValue and given Part and Lane .


<s> bool arc_epilogue_uses ( int regno ) { unsigned int fn_type ; fn_type = arc_compute_function_type ( cfun ) ; if ( regno == arc_tp_regno ) return true ; if ( regno == RETURN_ADDR_REGNUM ) return true ; if ( regno == arc_return_address_register ( fn_type ) ) return true ; if ( epilogue_completed && ARC_INTERRUPT_P ( fn_type ) ) { if ( df_regs_ever_live_p ( regno ) || call_used_or_fixed_reg_p ( regno ) ) return true ; } return false ; } </s>

Implement EPILOGUE__USES . Return true if REGNO should be added to the deemed uses of the epilogue . We use the return address arc_return_address_regs [ arc_compute_function_type ( cfun ) ] . But also , we have to make sure all the register restore instructions are known to be live in interrupt functions , plus the blink register if it is clobbered by the isr .


<s> fma_node * func_fma_steering :: get_fma_node ( rtx_insn * insn ) { fma_node * * fma_slot ; fma_slot = this -> m_insn_fma_head_map -> get ( insn ) ; if ( fma_slot ) return * fma_slot ; return NULL ; } </s>

Return whether an fma_node object exists for instruction INSN and , if not , allocate one in * RET .


<s> void UnwindOpcodeAssembler :: EmitRegSave ( uint32_t RegSave ) { if ( RegSave == 0u ) return ; if ( RegSave & ( 1u << 4 ) ) { uint32_t Range = 0 ; uint32_t Mask = ( 1u << 4 ) ; for ( uint32_t Bit = ( 1u << 5 ) ; Bit < ( 1u << 12 ) ; Bit <<= 1 ) { if ( ( RegSave & Bit ) == 0u ) break ; ++ Range ; Mask |= Bit ; } uint32_t UnmaskedReg = RegSave & 0xfff0u & ( ~ Mask ) ; if ( UnmaskedReg == 0u ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4 | Range ) ; RegSave &= 0x000fu ; } else if ( UnmaskedReg == ( 1u << 14 ) ) { EmitInt8 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range ) ; RegSave &= 0x000fu ; } } if ( ( RegSave & 0xfff0u ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK_R4 | ( RegSave >> 4 ) ) ; if ( ( RegSave & 0x000fu ) != 0 ) EmitInt16 ( ARM :: EHABI :: UNWIND_OPCODE_POP_REG_MASK | ( RegSave & 0x000fu ) ) ; } </s>

Emit unwind opcodes for .save directives .


<s> bool OR1KAsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OW -> write32 ( 0x15000000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> bool SPUTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createSPUISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
bool
runOnMachineFunction
(
MachineFunction
&
MF
)
override
{
LLVM_DEBUG
(
dbgs
(
)
<<
"********** ISelDAGToDAG **********\n"
"********** Function: "
<<
MF
.
getName
(
)
<<
'\n'
)
;
checkForInvalidNodes
(
MF
.
getFunction
(
)
)
;
Subtarget
=
&
MF
.
getSubtarget
<
WebAssemblySubtarget
>
(
)
;
return
SelectionDAGISel
::
runOnMachineFunction
(
MF
)
;
}
</s>

runOnMachineFunction - Emit the function body .

WebAssembly
"********** ISelDAGToDAG **********\n"
"********** Function: "
WebAssembly


<s> static void aarch64_sched_fusion_priority ( rtx_insn * insn , int max_pri , int * fusion_pri , int * pri ) { int tmp , off_val ; rtx base , offset ; enum sched_fusion_type fusion ; gcc_assert ( INSN_P ( insn ) ) ; tmp = max_pri - 1 ; fusion = fusion_load_store ( insn , & base , & offset ) ; if ( fusion == SCHED_FUSION_NONE ) { * pri = tmp ; * fusion_pri = tmp ; return ; } * fusion_pri = tmp - fusion * FIRST_PSEUDO_REGISTER - REGNO ( base ) ; tmp /= 2 ; off_val = ( int ) ( INTVAL ( offset ) ) ; if ( off_val >= 0 ) tmp -= ( off_val & 0xfffff ) ; else tmp += ( ( - off_val ) & 0xfffff ) ; * pri = tmp ; return ; } </s>

Implement the TARGET_SCHED_FUSION_PRIORITY hook . Currently we only support to fuse ldr or str instructions , so FUSION_PRI and PRI are only calculated for these instructions . For other instruction , FUSION_PRI and PRI are simply set to MAX_PRI - 1 . In the future , other type instruction fusion can be added by returning different priorities . It 's important that irrelevant instructions get the largest FUSION_PRI .


<s> const uint16_t * X86RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool callsEHReturn = false ; bool ghcCall = false ; bool oclBiCall = false ; bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( MF ) { callsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; oclBiCall = ( F ? F -> getCallingConv ( ) == CallingConv :: Intel_OCL_BI : false ) ; } if ( ghcCall ) return CSR_NoRegs_SaveList ; if ( oclBiCall ) { if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; } if ( Is64Bit ) { if ( IsWin64 ) return CSR_Win64_SaveList ; if ( callsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; } if ( callsEHReturn ) return CSR_32EHRet_SaveList ; return CSR_32_SaveList ; } </s>


"%qE attribute only applies to functions"

"multiple interrupt attributes not allowed"

"%<interrupt_thread%> is available only on fido"

Handle an attribute requiring a FUNCTION_DECL ; arguments as in struct attribute_spec.handler .


<s> bool AArch64InstrInfo :: isPairableLdStInst ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : case AArch64 :: STRXui : case AArch64 :: STRWui : case AArch64 :: LDRSui : case AArch64 :: LDRDui : case AArch64 :: LDRQui : case AArch64 :: LDRXui : case AArch64 :: LDRWui : case AArch64 :: LDRSWui : case AArch64 :: STURSi : case AArch64 :: STURDi : case AArch64 :: STURQi : case AArch64 :: STURWi : case AArch64 :: STURXi : case AArch64 :: LDURSi : case AArch64 :: LDURDi : case AArch64 :: LDURQi : case AArch64 :: LDURWi : case AArch64 :: LDURXi : case AArch64 :: LDURSWi : return true ; } } </s>

Return true if pairing the given load or store may be paired with another .


<s>
void
Cpu0SEFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
Cpu0MachineFunctionInfo
*
Cpu0FI
=
MF
.
getInfo
<
Cpu0MachineFunctionInfo
>
(
)
;
const
Cpu0SEInstrInfo
&
TII
=
*
static_cast
<
const
Cpu0SEInstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
const
Cpu0RegisterInfo
&
RegInfo
=
*
static_cast
<
const
Cpu0RegisterInfo
*
>
(
STI
.
getRegisterInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
dl
=
MBBI
!=
MBB
.
end
(
)
MBBI
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
Cpu0ABIInfo
ABI
=
STI
.
getABI
(
)
;
unsigned
SP
=
Cpu0
::
SP
;
const
TargetRegisterClass
*
RC
=
&
Cpu0
::
GPROutRegClass
;
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
StackSize
==
0
&&
!
MFI
.
adjustsStack
(
)
)
return
;
MachineModuleInfo
&
MMI
=
MF
.
getMMI
(
)
;
const
MCRegisterInfo
*
MRI
=
MMI
.
getContext
(
)
.
getRegisterInfo
(
)
;
TII
.
adjustStackPtr
(
SP
,
StackSize
,
MBB
,
MBBI
)
;
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createDefCfaOffset
(
nullptr
,
StackSize
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
=
MFI
.
getCalleeSavedInfo
(
)
;
if
(
CSI
.
size
(
)
)
{
for
(
unsigned
i
=
0
;
i
<
CSI
.
size
(
)
;
++
i
)
++
MBBI
;
for
(
std
::
vector
<
CalleeSavedInfo
>
::
const_iterator
I
=
CSI
.
begin
(
)
,
E
=
CSI
.
end
(
)
;
I
!=
E
;
++
I
)
{
int64_t
Offset
=
MFI
.
getObjectOffset
(
I
->
getFrameIdx
(
)
)
;
unsigned
Reg
=
I
->
getReg
(
)
;
{
unsigned
CFIIndex
=
MF
.
addFrameInst
(
MCCFIInstruction
::
createOffset
(
nullptr
,
MRI
->
getDwarfRegNum
(
Reg
,
1
)
,
Offset
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
TargetOpcode
::
CFI_INSTRUCTION
)
)
.
addCFIIndex
(
CFIIndex
)
;
}
}
}
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static int unspec_fcmla ( int rot ) { switch ( rot ) { case 0 : return UNSPEC_FCMLA ; case 90 : return UNSPEC_FCMLA90 ; case 180 : return UNSPEC_FCMLA180 ; case 270 : return UNSPEC_FCMLA270 ; default : gcc_unreachable ( ) ; } } </s>

Return the UNSPEC_FCMLA * unspec for rotation amount ROT .


<s> static struct mips_multi_member * mips_multi_add ( void ) { mips_multi_member empty ; return mips_multi_members . safe_push ( empty ) ; } </s>

Add a new , uninitialized member to the current multi-insn sequence .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
*
Mang
=
AP
.
Mang
;
const
DataLayout
*
DL
=
TM
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
StringRef
Suffix
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
Suffix
=
"$stub"
;
else
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
Suffix
=
"$non_lazy_ptr"
;
if
(
!
Suffix
.
empty
(
)
)
Name
+=
DL
->
getPrivateGlobalPrefix
(
)
;
unsigned
PrefixLen
=
Name
.
size
(
)
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mang
->
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
*
Mang
)
;
}
unsigned
OrigLen
=
Name
.
size
(
)
PrefixLen
;
Name
+=
Suffix
;
MCSymbol
*
Sym
=
Ctx
.
GetOrCreateSymbol
(
Name
.
str
(
)
)
;
StringRef
OrigName
=
StringRef
(
Name
)
.
substr
(
PrefixLen
,
OrigLen
)
;
if
(
MO
.
getTargetFlags
(
)
==
PPCII
::
MO_DARWIN_STUB
)
{
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
getMachOMMI
(
AP
)
.
getFnStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
)
return
Sym
;
if
(
MO
.
isGlobal
(
)
)
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
else
{
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
Ctx
.
GetOrCreateSymbol
(
OrigName
)
,
false
)
;
}
return
Sym
;
}
if
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_FLAG
)
{
MachineModuleInfoMachO
&
MachO
=
getMachOMMI
(
AP
)
;
MachineModuleInfoImpl
::
StubValueTy
&
StubSym
=
(
MO
.
getTargetFlags
(
)
&
PPCII
::
MO_NLP_HIDDEN_FLAG
)
MachO
.
getHiddenGVStubEntry
(
Sym
)
:
MachO
.
getGVStubEntry
(
Sym
)
;
if
(
StubSym
.
getPointer
(
)
==
0
)
{
assert
(
MO
.
isGlobal
(
)
&&
"Extern symbol not handled yet"
)
;
StubSym
=
MachineModuleInfoImpl
::
StubValueTy
(
AP
.
getSymbol
(
MO
.
getGlobal
(
)
)
,
!
MO
.
getGlobal
(
)
->
hasInternalLinkage
(
)
)
;
}
return
Sym
;
}
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> static rtx arc_unspec_offset ( rtx loc , int unspec ) { return gen_rtx_CONST ( Pmode , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , loc ) , unspec ) ) ; } </s>


<s> bool SITargetLowering :: isFPExtFoldable ( unsigned Opcode , EVT DestVT , EVT SrcVT ) const { return ( ( Opcode == ISD :: FMAD && Subtarget -> hasMadMixInsts ( ) ) || ( Opcode == ISD :: FMA && Subtarget -> hasFmaMixInsts ( ) ) ) && DestVT . getScalarType ( ) == MVT :: f32 && ! Subtarget -> hasFP32Denormals ( ) && SrcVT . getScalarType ( ) == MVT :: f16 ; } </s>

Return true if an fpext operation input to an Opcode operation is free ( for instance , because half-precision floating-point numbers are implicitly extended to float-precision ) for an FMA instruction .

AMDGPU SI ISD::FMAD ISD::FMA MVT::f32 MVT::f16


<s> StringRef getPassName ( ) const override { return SNES_INSTRUMENT_FUNCTIONS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


<s> static void emitSPUpdate ( bool isARM , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const ARMBaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , ARMCC :: CondCodes Pred = ARMCC :: AL , unsigned PredReg = 0 ) { if ( isARM ) emitARMRegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , Pred , PredReg , TII , MIFlags ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , ARM :: SP , ARM :: SP , NumBytes , Pred , PredReg , TII , MIFlags ) ; } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .

ARM ARM ARM ARMCC::CondCodes ARMCC::AL 0 ARM ARM ARM::SP ARM::SP ARM::SP ARM::SP


"********** Fixing Irreducible Control Flow **********\n"


<s> bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) override { OutOps . push_back ( Op ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { rtx very_unlikely = GEN_INT ( REG_BR_PROB_BASE / 100 - 1 ) ; rtx x ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; x = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; REG_NOTES ( x ) = gen_rtx_EXPR_LIST ( REG_BR_PROB , very_unlikely , NULL_RTX ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> void TeeRISCInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool runOnFunction ( Function & F ) override { TargetMachine * TM = & getAnalysis < TargetPassConfig > ( ) . getTM < TargetMachine > ( ) ; bool C = false ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) { X86PreAMXConfig PCFG ( F ) ; C = PCFG . preTileConfig ( ) ; } return C ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void AArch64Subtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , MachineInstr * begin , MachineInstr * end , unsigned NumRegionInstrs ) const { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; Policy . DisableLatencyHeuristic = DisableLatencySchedHeuristic ; } </s>

Override generic scheduling policy within a region .


<s> static rtx cr16_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> last_parm_in_reg = 0 ; if ( type == void_type_node ) return NULL_RTX ; if ( targetm . calls . must_pass_in_stack ( mode , type ) || ( cum -> ints < 0 ) ) return NULL_RTX ; if ( mode == BLKmode ) { if ( enough_regs_for_param ( cum , type , mode ) != 0 ) { cum -> last_parm_in_reg = 1 ; return gen_rtx_REG ( mode , MIN_REG_FOR_PASSING_ARGS + cum -> ints ) ; } } if ( ( MIN_REG_FOR_PASSING_ARGS + cum -> ints ) > MAX_REG_FOR_PASSING_ARGS ) return NULL_RTX ; else { if ( enough_regs_for_param ( cum , type , mode ) != 0 ) { cum -> last_parm_in_reg = 1 ; return gen_rtx_REG ( mode , MIN_REG_FOR_PASSING_ARGS + cum -> ints ) ; } } return NULL_RTX ; } </s>

Implements the macro FUNCTION_ARG defined in cr16.h .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
if
(
skipFunction
(
Func
.
getFunction
(
)
)
)
return
false
;
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
bool
IsSlowLEA
=
ST
.
slowLEA
(
)
;
bool
IsSlow3OpsLEA
=
ST
.
slow3OpsLEA
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
.
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
IsSlowLEA
||
IsSlow3OpsLEA
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TSM
.
init
(
&
Func
.
getSubtarget
(
)
)
;
TII
=
ST
.
getInstrInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
,
IsSlowLEA
,
IsSlow3OpsLEA
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> void s390_d_target_versions ( void ) { if ( TARGET_ZARCH ) d_add_builtin_version ( "SystemZ" ) ; else if ( TARGET_64BIT ) d_add_builtin_version ( "S390X" ) ; else d_add_builtin_version ( "S390" ) ; if ( TARGET_SOFT_FLOAT ) d_add_builtin_version ( "D_SoftFloat" ) ; else if ( TARGET_HARD_FLOAT ) d_add_builtin_version ( "D_HardFloat" ) ; } </s>

Implement TARGET_D_CPU_VERSIONS for S/390 and zSeries targets .


<s> static void umips_output_load_store_pair_1 ( bool load_p , rtx reg , rtx mem ) { rtx ops [ ] = { reg , mem } ; if ( load_p ) output_asm_insn ( "lwp\t%0,%1" , ops ) ; else output_asm_insn ( "swp\t%0,%1" , ops ) ; } </s>

Return the assembly instruction for a microMIPS LWP or SWP in which the first register is REG and the first memory slot is MEM . LOAD_P is true for LWP .


<s> static rtx ix86_validate_address_register ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; if ( mode != SImode && mode != DImode ) return NULL_RTX ; if ( REG_P ( op ) ) return op ; else if ( SUBREG_P ( op ) ) { rtx reg = SUBREG_REG ( op ) ; if ( ! REG_P ( reg ) ) return NULL_RTX ; mode = GET_MODE ( reg ) ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return NULL_RTX ; if ( register_no_elim_operand ( reg , mode ) ) return reg ; } return NULL_RTX ; } </s>

Determine if op is suitable RTX for an address register . Return naked register if a register or a register subreg is found , otherwise return NULL_RTX .


<s> static unsigned char avr_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( rclass == CC_REG && mode == CCmode ) return 1 ; return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ; } </s>

Implement TARGET_CLASS_MAX_NREGS . Reasons described in comments for avr_hard_regno_nregs .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; return ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) || ( ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> void RISCVInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { bool Res = false ; const MCInst * NewMI = MI ; MCInst UncompressedMI ; if ( ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ; if ( NoAliases || ! printAliasInstr ( NewMI , Address , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ; printAnnotation ( O , Annot ) ; } </s>


<s> bool isScalable ( ) const { return Type == PPR || Type == ZPR ; } </s>

Returns true if the LLT is a scalable vector .


<s> static bool arm_output_ttype ( rtx x ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( ! CONST_INT_P ( x ) ) fputs ( "(TARGET2)" , asm_out_file ) ; fputc ( '\n' , asm_out_file ) ; return TRUE ; } </s>

Output a reference from a function exception table to the type_info object X . The EABI specifies that the symbol should be relocated by an R_ARM_TARGET2 relocation .


<s> static bool aarch64_short_vector_p ( const_tree type , machine_mode mode ) { poly_int64 size = - 1 ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) size = int_size_in_bytes ( type ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) size = GET_MODE_SIZE ( mode ) ; return known_eq ( size , 8 ) || known_eq ( size , 16 ) ; } </s>

Return TRUE if the type , as described by TYPE and MODE , is a short vector type as described in AAPCS64 \S 4.1.2 . See the comment above aarch64_composite_type_p for the notes on MODE .


<s> M68kSubtarget :: M68kSubtarget ( const Triple & TT , StringRef CPU , StringRef FS , const M68kTargetMachine & TM ) : M68kGenSubtargetInfo ( TT , CPU , CPU , FS ) , TM ( TM ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , TT , FS , TM ) ) , FrameLowering ( * this , this -> getStackAlignment ( ) ) , TLInfo ( TM , * this ) , TargetTriple ( TT ) { } </s>

This constructor initializes the data members to match that of the specified triple .


"\t# pre-label NOPs for hotpatch (%d halfwords)\n"

"\t# post-label NOPs for hotpatch (%d halfwords)\n"

Write the extra assembler code needed to declare a function properly .


<s> const uint32_t * MMIXRegisterInfo :: getCallPreservedMask ( const MachineFunction & , CallingConv :: ID ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
void
mmix_asm_output_aligned_local
(
FILE
*
stream
,
const
char
*
name
,
int
size
,
int
align
)
{
data_section
(
)
;
ASM_OUTPUT_ALIGN
(
stream
,
exact_log2
(
align
/
BITS_PER_UNIT
)
)
;
assemble_name
(
stream
,
name
)
;
fprintf
(
stream
,
"\tLOC @+%d\n"
,
size
)
;
}
</s>


<s> void function_builder :: append_sew ( int sew ) { switch ( sew ) { case 8 : append_name ( "8" ) ; break ; case 16 : append_name ( "16" ) ; break ; case 32 : append_name ( "32" ) ; break ; case 64 : append_name ( "64" ) ; break ; default : gcc_unreachable ( ) ; } } </s>


<s> static RTX_CODE compare_condition ( rtx insn ) { rtx next = next_real_insn ( insn ) ; RTX_CODE cond = UNKNOWN ; if ( next && GET_CODE ( next ) == JUMP_INSN ) { rtx pat = PATTERN ( next ) ; rtx src = SET_SRC ( pat ) ; rtx t = XEXP ( src , 0 ) ; cond = GET_CODE ( t ) ; } return cond ; } </s>

Returns the condition of compare insn INSN , or UNKNOWN .


<s> SDValue TMS320C64XLowering :: LowerOperation ( SDValue op , SelectionDAG & DAG ) const { switch ( op . getOpcode ( ) ) { case ISD :: GlobalAddress : return LowerGlobalAddress ( op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( op , DAG ) ; case ISD :: RETURNADDR : return LowerReturnAddr ( op , DAG ) ; case ISD :: BR_CC : return LowerBRCC ( op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( op , DAG ) ; case ISD :: LOAD : return LowerExtLoad ( op , DAG ) ; case ISD :: SELECT : return LowerSelect ( op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( op , DAG ) ; case ISD :: VAARG : return LowerVAARG ( op , DAG ) ; case ISD :: INTRINSIC_W_CHAIN : return LowerIntrinsic ( op , DAG ) ; default : llvm_unreachable ( op . getNode ( ) -> getOperationName ( ) . c_str ( ) ) ; } return op ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

TMS320C64X TMS320C64X ISD::GlobalAddress ISD::JumpTable ISD::RETURNADDR ISD::BR_CC ISD::SETCC ISD::LOAD ISD::SELECT ISD::VASTART ISD::VAARG ISD::INTRINSIC_W_CHAIN


<s> int arc_return_address_register ( unsigned int fn_type ) { int regno = 0 ; if ( ARC_INTERRUPT_P ( fn_type ) ) { if ( ( ( fn_type & ARC_FUNCTION_ILINK1 ) | ARC_FUNCTION_FIRQ ) != 0 ) regno = ILINK1_REGNUM ; else if ( ( fn_type & ARC_FUNCTION_ILINK2 ) != 0 ) regno = ILINK2_REGNUM ; else gcc_unreachable ( ) ; } else if ( ARC_NORMAL_P ( fn_type ) || ARC_NAKED_P ( fn_type ) ) regno = RETURN_ADDR_REGNUM ; gcc_assert ( regno != 0 ) ; return regno ; } </s>

Return the register number of the register holding the return address for a function of type TYPE .


<s>
MachineBasicBlock
*
MBlazeTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
MBB
)
const
{
switch
(
MI
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
MBlaze
::
ShiftRL
:
case
MBlaze
::
ShiftRA
:
case
MBlaze
::
ShiftL
:
return
EmitCustomShift
(
MI
,
MBB
)
;
case
MBlaze
::
Select_FCC
:
case
MBlaze
::
Select_CC
:
return
EmitCustomSelect
(
MI
,
MBB
)
;
case
MBlaze
::
CAS32
:
case
MBlaze
::
SWP32
:
case
MBlaze
::
LAA32
:
case
MBlaze
::
LAS32
:
case
MBlaze
::
LAD32
:
case
MBlaze
::
LAO32
:
case
MBlaze
::
LAX32
:
case
MBlaze
::
LAN32
:
return
EmitCustomAtomic
(
MI
,
MBB
)
;
case
MBlaze
::
MEMBARRIER
:
MI
->
eraseFromParent
(
)
;
return
MBB
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static void register_builtin_types ( ) { scalar_types [ VECTOR_TYPE_ ## ACLE_NAME ] = SCALAR_TYPE ; for ( unsigned int i = 0 ; i < NUM_VECTOR_TYPES ; ++ i ) { if ( vector_types [ i ] . requires_float && ! TARGET_HAVE_MVE_FLOAT ) continue ; tree eltype = scalar_types [ i ] ; tree vectype ; if ( eltype == boolean_type_node ) { vectype = get_typenode_from_name ( UINT16_TYPE ) ; gcc_assert ( GET_MODE_SIZE ( TYPE_MODE ( vectype ) ) == 2 ) ; } else { vectype = arm_mve_type_for_scalar_type ( eltype ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && GET_MODE_SIZE ( TYPE_MODE ( vectype ) ) == 16 ) ; } abi_vector_types [ i ] = vectype ; } } </s>

Register the built-in RVV ABI types , such as __rvv_int32m1_t .


<s> int pdp10_stack_dynamic_offset ( ) { return 1 ; } </s>

Called by the STACK_DYNAMIC_OFFSET macro .


<s> bool ARMGlobalMerge :: doInitialization ( Module & M ) { SmallVector < GlobalVariable * , 16 > Globals , ConstGlobals , BSSGlobals ; const TargetData * TD = TLI -> getTargetData ( ) ; unsigned MaxOffset = TLI -> getMaximalGlobalOffset ( ) ; bool Changed = false ; if ( TLI -> getTargetMachine ( ) . getSubtarget < ARMSubtarget > ( ) . isTargetDarwin ( ) ) return false ; for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) { if ( ! I -> hasLocalLinkage ( ) || I -> isThreadLocal ( ) || I -> hasSection ( ) ) continue ; if ( I -> getAlignment ( ) != 0 ) continue ; if ( I -> getName ( ) . startswith ( "llvm." ) || I -> getName ( ) . startswith ( ".llvm." ) ) continue ; if ( TD -> getTypeAllocSize ( I -> getType ( ) -> getElementType ( ) ) < MaxOffset ) { const TargetLoweringObjectFile & TLOF = TLI -> getObjFileLowering ( ) ; if ( TLOF . getKindForGlobal ( I , TLI -> getTargetMachine ( ) ) . isBSSLocal ( ) ) BSSGlobals . push_back ( I ) ; else if ( I -> isConstant ( ) ) ConstGlobals . push_back ( I ) ; else Globals . push_back ( I ) ; } } if ( Globals . size ( ) > 1 ) Changed |= doMerge ( Globals , M , false ) ; if ( BSSGlobals . size ( ) > 1 ) Changed |= doMerge ( BSSGlobals , M , false ) ; return Changed ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> EVT getSetCCResultType ( const DataLayout & , LLVMContext & C , EVT VT ) const override { if ( ! VT . isVector ( ) ) return MVT :: i1 ; else return EVT :: getVectorVT ( C , MVT :: i1 , VT . getVectorNumElements ( ) ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static void nvptx_emit_forking ( unsigned mask , bool is_call ) { mask &= ( GOMP_DIM_MASK ( GOMP_DIM_WORKER ) | GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ; if ( mask ) { rtx op = GEN_INT ( mask | ( is_call << GOMP_DIM_MAX ) ) ; emit_insn ( gen_nvptx_fork ( op ) ) ; emit_insn ( gen_nvptx_forked ( op ) ) ; } } </s>


<s>
static
void
ix86_function_specific_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
char
*
target_string
=
ix86_target_string
(
ptr
->
x_ix86_isa_flags
,
ptr
->
x_target_flags
,
,
,
ptr
->
x_ix86_fpmath
,
false
)
;
gcc_assert
(
ptr
->
arch
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*sarch = %d (%s)\n"
,
indent
,
""
,
ptr
->
arch
,
processor_target_table
[
ptr
->
arch
]
.
name
)
;
gcc_assert
(
ptr
->
tune
<
PROCESSOR_max
)
;
fprintf
(
file
,
"%*stune = %d (%s)\n"
,
indent
,
""
,
ptr
->
tune
,
processor_target_table
[
ptr
->
tune
]
.
name
)
;
fprintf
(
file
,
"%*sbranch_cost = %d\n"
,
indent
,
""
,
ptr
->
branch_cost
)
;
if
(
target_string
)
{
fprintf
(
file
,
"%*s%s\n"
,
indent
,
""
,
target_string
)
;
free
(
target_string
)
;
}
}
</s>


<s> static bool alpha_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { return ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) || ! reg_classes_intersect_p ( FLOAT_REGS , rclass ) ) ; } </s>


<s> bool loongarch_12bit_offset_address_p ( rtx x , machine_mode mode ) { struct loongarch_address_info addr ; return ( loongarch_classify_address ( & addr , x , mode , false ) && addr . type == ADDRESS_REG && CONST_INT_P ( addr . offset ) && LARCH_U12BIT_OFFSET_P ( INTVAL ( addr . offset ) ) ) ; } </s>

Return true if X is a legitimate address with a 12-bit offset or addr.type is ADDRESS_LO_SUM . MODE is the mode of the value being accessed .


<s>
static
unsigned
getRegClass
(
bool
IsVgpr
,
unsigned
RegWidth
)
{
if
(
IsVgpr
)
{
switch
(
RegWidth
)
{
default
:
llvm_unreachable
(
"Unknown register width"
)
;
case
1
:
return
AMDGPU
::
VGPR_32RegClassID
;
case
2
:
return
AMDGPU
::
VReg_64RegClassID
;
case
3
:
return
AMDGPU
::
VReg_96RegClassID
;
case
4
:
return
AMDGPU
::
VReg_128RegClassID
;
case
8
:
return
AMDGPU
::
VReg_256RegClassID
;
case
16
:
return
AMDGPU
::
VReg_512RegClassID
;
}
}
switch
(
RegWidth
)
{
default
:
llvm_unreachable
(
"Unknown register width"
)
;
case
1
:
return
AMDGPU
::
SGPR_32RegClassID
;
case
2
:
return
AMDGPU
::
SGPR_64RegClassID
;
case
4
:
return
AMDGPU
::
SReg_128RegClassID
;
case
8
:
return
AMDGPU
::
SReg_256RegClassID
;
case
16
:
return
AMDGPU
::
SReg_512RegClassID
;
}
}
</s>

Given a machine instruction descriptor , returns the register class constraint for OpNum , or NULL .


<s> explicit Entry ( const SortRegion * R ) : TheRegion ( R ) , NumBlocksLeft ( R -> getNumBlocks ( ) ) { } </s>


Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


"Code generation for MIPS-I is not implemented"

"Code generation for MIPS-V is not implemented"

"MSA requires a 64-bit FPU register file (FR=1 mode). "

"-mattr=+nooddspreg requires the O32 ABI."

"FPXX is not permitted for the N32/N64 ABI's."

"position-independent code requires '-mabicalls'"

"warning: cannot use small-data accesses for '-mabicalls'"


<s> static bool abi_v4_pass_in_fpr ( machine_mode mode ) { if ( ! TARGET_FPRS || ! TARGET_HARD_FLOAT ) return false ; if ( TARGET_SINGLE_FLOAT && mode == SFmode ) return true ; if ( TARGET_DOUBLE_FLOAT && mode == DFmode ) return true ; if ( is_complex_IBM_long_double ( mode ) ) return false ; if ( FLOAT128_2REG_P ( mode ) ) return true ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return true ; return false ; } </s>

Whether ABI_V4 passes MODE args to a function in floating point registers .


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr & MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp , LiveVariables * LV ) const { MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , 64 ) ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * Copy = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; if ( LV ) LV -> replaceKillInstruction ( SrcReg , MI , * Copy ) ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s> const char * pru_output_signed_cbranch ( rtx * operands , bool is_near ) { enum rtx_code code = GET_CODE ( operands [ 0 ] ) ; if ( code == LT || code == LE ) return pru_output_ltle_signed_cbranch ( operands , is_near ) ; else if ( code == GT || code == GE ) return pru_output_gtge_signed_cbranch ( operands , is_near ) ; else gcc_unreachable ( ) ; } </s>

Output asm code for a signed-compare conditional branch . If IS_NEAR is true , then QBBx instructions may be used for reaching the destination label . Otherwise JMP is used , at the expense of increased code size .


<s> bool HexagonMCChecker :: check ( bool FullCheck ) { bool chkP = checkPredicates ( ) ; bool chkNV = checkNewValues ( ) ; bool chkR = checkRegisters ( ) ; bool chkRRO = checkRegistersReadOnly ( ) ; checkRegisterCurDefs ( ) ; bool chkS = checkSolo ( ) ; bool chkSh = true ; if ( FullCheck ) chkSh = checkShuffle ( ) ; bool chkSl = true ; if ( FullCheck ) chkSl = checkSlots ( ) ; bool chkAXOK = checkAXOK ( ) ; bool chkCofMax1 = checkCOFMax1 ( ) ; bool chkHWLoop = checkHWLoop ( ) ; bool chkValidTmpDst = FullCheck ? checkValidTmpDst ( ) : true ; bool chkLegalVecRegPair = checkLegalVecRegPair ( ) ; bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl && chkAXOK && chkCofMax1 && chkHWLoop && chkValidTmpDst && chkLegalVecRegPair ; return chk ; } </s>

Check if the constraints are satisfiable .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .

PowerPC
PPC
"Unknown rematerializable operation!"
PPC::LI
PPC::LI8
PPC::LIS
PPC::LIS8
PPC::QVGPCI
PPC::ADDIStocHA
PPC::ADDItocL
PPC::LOAD_STACK_GUARD


<s> void timode_scalar_chain :: mark_dual_mode_def ( df_ref ) { gcc_unreachable ( ) ; } </s>

For DImode conversion , mark register defined by DEF as requiring conversion .


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


"rvex DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> static void arc_setup_incoming_varargs ( cumulative_args_t args_so_far , machine_mode mode , tree type , int * pretend_size , int no_rtl ) { int first_anon_arg ; CUMULATIVE_ARGS next_cum ; next_cum = * get_cumulative_args ( args_so_far ) ; arc_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , true ) ; first_anon_arg = next_cum ; if ( FUNCTION_ARG_REGNO_P ( first_anon_arg ) ) { int first_reg_offset = first_anon_arg ; if ( ! no_rtl ) { rtx regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( 0 ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , MAX_ARC_PARM_REGS - first_reg_offset ) ; } * pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ; } } </s>

Do any needed setup for a variadic function . For the ARC , we must create a register parameter block , and then copy any anonymous arguments in registers to memory . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> unsigned SIRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned Occupancy = ST . getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , * MF . getFunction ( ) ) ; switch ( RC -> getID ( ) ) { default : return AMDGPURegisterInfo :: getRegPressureLimit ( RC , MF ) ; case AMDGPU :: VGPR_32RegClassID : return std :: min ( ST . getMaxNumVGPRs ( Occupancy ) , ST . getMaxNumVGPRs ( MF ) ) ; case AMDGPU :: SGPR_32RegClassID : return std :: min ( ST . getMaxNumSGPRs ( Occupancy , true ) , ST . getMaxNumSGPRs ( MF ) ) ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .

AMDGPU SI SI SI SI SI AMDGPU AMDGPU::VGPR_32RegClassID AMDGPU::SGPR_32RegClassID


Hook to validate attribute ( ( target ( `` ... '' ) ) ) .


<s> unsigned getAlignment ( ) const { return Alignment ; } </s>

getAlignment - Return the alignment of the function .


<s> std :: pair < InstructionCost , MVT > SITargetLowering :: getTypeLegalizationCost ( const DataLayout & DL , Type * Ty ) const { std :: pair < InstructionCost , MVT > Cost = TargetLoweringBase :: getTypeLegalizationCost ( DL , Ty ) ; auto Size = DL . getTypeSizeInBits ( Ty ) ; if ( Size <= 256 ) return Cost ; Cost . first += ( Size + 255 ) / 256 ; return Cost ; } </s>

Estimate the cost of type-legalization and the legalized type .


<s>
void
Z80oldTargetLowering
::
AdjustInstrPostInstrSelection
(
MachineInstr
&
MI
,
SDNode
*
Node
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
case
Z80old
::
ADJCALLSTACKUP16
:
case
Z80old
::
ADJCALLSTACKDOWN16
:
return
AdjustAdjCallStack
(
MI
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DCI ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: SELECT_CC : return performSelectCCCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: CSEL : return performCONDCombine ( N , DCI , DAG , 2 , 3 ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static bool nios2_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { return ( int_size_in_bytes ( type ) > ( 2 * UNITS_PER_WORD ) || int_size_in_bytes ( type ) == - 1 ) ; } </s>


<s> virtual void Initialize ( MCContext & ctx , const TargetMachine & TM ) { TargetLoweringObjectFile :: Initialize ( ctx , TM ) ; TextSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getText ( ) ) ; DataSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getDataRel ( ) ) ; BSSSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getBSS ( ) ) ; ReadOnlySection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getReadOnly ( ) ) ; StaticCtorSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; StaticDtorSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; LSDASection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLocSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfARangesSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfRangesSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfMacroInfoSection = new Z80Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> enum reg_class aarch64_regno_regclass ( unsigned regno ) { if ( GP_REGNUM_P ( regno ) ) return GENERAL_REGS ; if ( regno == SP_REGNUM ) return STACK_REG ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return POINTER_REGS ; if ( FP_REGNUM_P ( regno ) ) return FP_LO_REGNUM_P ( regno ) ? FP_LO_REGS : FP_REGS ; return NO_REGS ; } </s>


"unimplemented opcode in encodeInstruction()"

"Pseudo opcode found in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s> bool AArch64RedundantCopyElimination :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; ClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= optimizeCopy ( & MBB ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool ARMTargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const { if ( ! Subtarget -> supportsTailCall ( ) ) return false ; if ( ! CI -> isTailCall ( ) || getTargetMachine ( ) . Options . DisableTailCalls ) return false ; return ! Subtarget -> isThumb1Only ( ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( STI . isTargetDarwin ( ) && STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_iOS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s>
bool
SystemZInstrInfo
::
PredicateInstruction
(
MachineInstr
*
MI
,
const
SmallVectorImpl
<
MachineOperand
>
&
Pred
)
const
{
assert
(
Pred
.
size
(
)
==
2
&&
"Invalid condition"
)
;
unsigned
CCValid
=
Pred
[
0
]
.
getImm
(
)
;
unsigned
CCMask
=
Pred
[
1
]
.
getImm
(
)
;
assert
(
CCMask
>
0
&&
CCMask
<
15
&&
"Invalid predicate"
)
;
unsigned
Opcode
=
MI
->
getOpcode
(
)
;
if
(
STI
.
hasLoadStoreOnCond
(
)
)
{
if
(
unsigned
CondOpcode
=
getConditionalMove
(
Opcode
)
)
{
MI
->
setDesc
(
get
(
CondOpcode
)
)
;
MachineInstrBuilder
(
*
MI
->
getParent
(
)
->
getParent
(
)
,
MI
)
.
addImm
(
CCValid
)
.
addImm
(
CCMask
)
.
addReg
(
SystemZ
::
CC
,
RegState
::
Implicit
)
;
return
true
;
}
}
return
false
;
}
</s>

Convert the instruction into a predicated instruction .


<s> int mmix_eh_return_data_regno ( int n ) { if ( n >= 0 && n < 4 ) return MMIX_EH_RETURN_DATA_REGNO_START + n ; return INVALID_REGNUM ; } </s>


"\nrs6000_legitimate_address_p: return = %s, mode = %s, "

Debug version of rs6000_legitimate_address_p .


<s>
void
WebAssemblyTargetAsmStreamer
::
emitTagType
(
const
MCSymbolWasm
*
Sym
)
{
assert
(
Sym
->
isTag
(
)
)
;
OS
<<
"\t.tagtype\t"
<<
Sym
->
getName
(
)
<<
" "
;
OS
<<
WebAssembly
::
typeListToString
(
Sym
->
getSignature
(
)
->
Params
)
;
OS
<<
"\n"
;
}
</s>

WebAssembly
WebAssembly
"\t.tagtype\t"
" "
WebAssembly::typeListToString
"\n"


<s> static void aarch64_destroy_cost_data ( void * data ) { delete static_cast < aarch64_vector_costs * > ( data ) ; } </s>


<s>
static
void
output_reg_adjust
(
rtx
reg
,
int
n
)
{
const
char
*
s
;
gcc_assert
(
GET_MODE
(
reg
)
==
SImode
&&
12
<=
n
&&
n
!=
0
&&
n
<=
12
)
;
switch
(
n
)
{
case
12
:
s
=
"add%.l #12,%0"
;
break
;
case
8
:
s
=
"addq%.l #8,%0"
;
break
;
case
4
:
s
=
"addq%.l #4,%0"
;
break
;
case
12
:
s
=
"sub%.l #12,%0"
;
break
;
case
8
:
s
=
"subq%.l #8,%0"
;
break
;
case
4
:
s
=
"subq%.l #4,%0"
;
break
;
default
:
gcc_unreachable
(
)
;
s
=
;
}
output_asm_insn
(
s
,
&
reg
)
;
}
</s>

Output assembler code to adjust REG by N .


<s> void function_expander :: add_input_operand ( insn_code icode , rtx x ) { unsigned int opno = m_ops . length ( ) ; const insn_operand_data & operand = insn_data [ icode ] . operand [ opno ] ; machine_mode mode = operand . mode ; if ( mode == VOIDmode ) { gcc_assert ( operand . predicate == aarch64_any_register_operand ) ; mode = GET_MODE ( x ) ; } else if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) && VECTOR_MODE_P ( mode ) ) x = expand_vector_broadcast ( mode , x ) ; else if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) { gcc_assert ( GET_MODE ( x ) == VNx16BImode ) ; x = gen_lowpart ( mode , x ) ; } m_ops . safe_grow ( m_ops . length ( ) + 1 ) ; create_input_operand ( & m_ops . last ( ) , x , mode ) ; } </s>

Create op and add it into M_OPS and increase OPNO .


<s> SDValue TGSITargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned VirtualRegister ; if ( ! MRI . isLiveIn ( Reg ) ) { VirtualRegister = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( Reg , VirtualRegister ) ; } else { VirtualRegister = MRI . getLiveInVirtReg ( Reg ) ; } return DAG . getRegister ( VirtualRegister , VT ) ; } </s>

Helper function that adds Reg to the LiveIn list of the DAG 's MachineFunction .


<s> TargetLowering :: ConstraintWeight SPUTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : case 'r' : case 'f' : case 'd' : case 'v' : case 'y' : weight = CW_Register ; break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> bool AMDGPUSymbolizer :: tryAddingSymbolicOperand ( MCInst & Inst , raw_ostream & , int64_t Value , uint64_t , bool IsBranch , uint64_t , uint64_t ) { if ( ! IsBranch ) { return false ; } auto * Symbols = static_cast < SectionSymbolsTy * > ( DisInfo ) ; if ( ! Symbols ) return false ; auto Result = llvm :: find_if ( * Symbols , [ Value ] ( const SymbolInfoTy & Val ) { return Val . Addr == static_cast < uint64_t > ( Value ) && Val . Type == ELF :: STT_NOTYPE ; } ) ; if ( Result != Symbols -> end ( ) ) { auto * Sym = Ctx . getOrCreateSymbol ( Result -> Name ) ; const auto * Add = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Inst . addOperand ( MCOperand :: createExpr ( Add ) ) ; return true ; } return false ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


"instruction requires a CPU feature not currently enabled"

"flag setting instruction only valid outside IT block"

"instruction only valid inside IT block"

"instruction variant requires ARMv6 or later"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> bool strict_low_part_peephole_ok ( enum machine_mode mode , rtx first_insn , rtx target ) { rtx p ; p = prev_nonnote_insn ( first_insn ) ; while ( p ) { if ( GET_CODE ( p ) != INSN ) return false ; if ( reg_set_p ( target , p ) ) { rtx set = single_set ( p ) ; rtx dest ; if ( ! set ) return false ; dest = SET_DEST ( set ) ; if ( rtx_equal_p ( dest , target ) && SET_SRC ( set ) == const0_rtx ) return true ; else if ( GET_CODE ( dest ) == STRICT_LOW_PART && GET_CODE ( XEXP ( dest , 0 ) ) == REG && REGNO ( XEXP ( dest , 0 ) ) == REGNO ( target ) && ( GET_MODE_SIZE ( GET_MODE ( XEXP ( dest , 0 ) ) ) <= GET_MODE_SIZE ( mode ) ) ) ; else return false ; } p = prev_nonnote_insn ( p ) ; } return false ; } </s>

Check for cases where a clr insns can be omitted from code using strict_low_part sets . For example , the second clrl here is not needed : clrl d0 ; movw a0 @ + , d0 ; use d0 ; clrl d0 ; movw a0 @ + ; use d0 ; ... MODE is the mode of this STRICT_LOW_PART set . FIRST_INSN is the clear insn we are checking for redundancy . TARGET is the register set by the clear insn .


<s> static rtx rl78_hi8 ( rtx addr ) { if ( GET_CODE ( addr ) == SYMBOL_REF || GET_CODE ( addr ) == CONST ) { rtx r = gen_rtx_ZERO_EXTRACT ( QImode , addr , GEN_INT ( 8 ) , GEN_INT ( 16 ) ) ; r = gen_rtx_CONST ( QImode , r ) ; return r ; } return rl78_subreg ( QImode , addr , SImode , 2 ) ; } </s>

Return a suitable RTX for the high half 's lower byte of a __far address .


<s> unsigned HexagonTTIImpl :: getScalarizationOverhead ( Type * Ty , bool Insert , bool Extract ) { return BaseT :: getScalarizationOverhead ( Ty , Insert , Extract ) ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> const PPCRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
MachineBasicBlock
*
MipsTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
,
DenseMap
<
MachineBasicBlock
*
,
MachineBasicBlock
*
>
*
EM
)
const
{
const
TargetInstrInfo
*
TII
=
getTargetMachine
(
)
.
getInstrInfo
(
)
;
bool
isFPCmp
=
false
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
switch
(
MI
->
getOpcode
(
)
)
{
default
:
assert
(
false
&&
"Unexpected instr type to insert"
)
;
case
Mips
::
Select_FCC
:
case
Mips
::
Select_FCC_S32
:
case
Mips
::
Select_FCC_D32
:
isFPCmp
=
true
;
case
Mips
::
Select_CC
:
case
Mips
::
Select_CC_S32
:
case
Mips
::
Select_CC_D32
:
{
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
It
=
BB
;
++
It
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
sinkMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
if
(
isFPCmp
)
{
Mips
::
CondCode
CC
=
(
Mips
::
CondCode
)
MI
->
getOperand
(
4
)
.
getImm
(
)
;
unsigned
Opc
=
FPBranchCodeToOpc
(
GetFPBranchCodeFromCond
(
CC
)
)
;
BuildMI
(
BB
,
dl
,
TII
->
get
(
Opc
)
)
.
addMBB
(
sinkMBB
)
;
}
else
BuildMI
(
BB
,
dl
,
TII
->
get
(
Mips
::
BNE
)
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addReg
(
Mips
::
ZERO
)
.
addMBB
(
sinkMBB
)
;
F
->
insert
(
It
,
copy0MBB
)
;
F
->
insert
(
It
,
sinkMBB
)
;
for
(
MachineBasicBlock
::
succ_iterator
i
=
BB
->
succ_begin
(
)
,
e
=
BB
->
succ_end
(
)
;
i
!=
e
;
++
i
)
{
EM
->
insert
(
std
::
make_pair
(
*
i
,
sinkMBB
)
)
;
sinkMBB
->
addSuccessor
(
*
i
)
;
}
while
(
!
BB
->
succ_empty
(
)
)
BB
->
removeSuccessor
(
BB
->
succ_begin
(
)
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
sinkMBB
)
;
BB
=
sinkMBB
;
BuildMI
(
BB
,
dl
,
TII
->
get
(
Mips
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
3
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void ARMTargetLowering :: finalizeLowering ( MachineFunction & MF ) const { MF . getFrameInfo ( ) . computeMaxCallFrameSize ( MF ) ; TargetLoweringBase :: finalizeLowering ( MF ) ; } </s>

Execute target specific actions to finalize target lowering .


<s> static rtx get_jump_target ( rtx branch ) { if ( CALL_P ( branch ) ) { rtx call ; call = PATTERN ( branch ) ; if ( GET_CODE ( call ) == PARALLEL ) call = XVECEXP ( call , 0 , 0 ) ; if ( GET_CODE ( call ) == SET ) call = SET_SRC ( call ) ; if ( GET_CODE ( call ) == CALL ) return XEXP ( XEXP ( call , 0 ) , 0 ) ; } return 0 ; } </s>


<s> const Cpu0RegisterInfo & Cpu0InstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>


<s> bool X86InstrInfo :: hasHighOperandLatency ( const TargetSchedModel & SchedModel , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { return isHighLatencyDef ( DefMI -> getOpcode ( ) ) ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool OptimizeLEAPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( DisableX86LEAOpt || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < X86Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < X86Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) { MemOpMap LEAs ; InstrPos . clear ( ) ; findLEAs ( MBB , LEAs ) ; if ( LEAs . empty ( ) ) continue ; Changed |= removeRedundantLEAs ( LEAs ) ; if ( MF . getFunction ( ) . optForSize ( ) ) Changed |= removeRedundantAddrCalc ( LEAs ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s>
SDValue
PPCTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_PPC
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Outs
[
i
]
.
Val
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
else
return
DAG
.
getNode
(
PPCISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> int h8300_can_use_return_insn_p ( void ) { return ( reload_completed && ! frame_pointer_needed && get_frame_size ( ) == 0 && compute_saved_regs ( ) == 0 ) ; } </s>

Return nonzero if we can use `` rts '' for the function currently being compiled .


<s> bool X86RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . RealignStack && ! MFI -> hasVarSizedObjects ( ) ) ; } </s>

True if the stack can be realigned for the target .


<s> bool AArch64TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return false ; int64_t Val = Imm . getSExtValue ( ) ; if ( Val == 0 || AArch64_AM :: isLogicalImmediate ( Val , BitSize ) ) return true ; if ( ( int64_t ) Val < 0 ) Val = ~ Val ; if ( BitSize == 32 ) Val &= ( 1LL << 32 ) - 1 ; unsigned LZ = countLeadingZeros ( ( uint64_t ) Val ) ; unsigned Shift = ( 63 - LZ ) / 16 ; return Shift < 3 ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> bool PIC16AsmPrinter :: doFinalization ( Module & M ) { O << "\t" << "END\n" ; bool Result = AsmPrinter :: doFinalization ( M ) ; return Result ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> static inline bool address_is_prefixed ( rtx addr , machine_mode mode , enum non_prefixed_form non_prefixed ) { enum insn_form iform = address_to_insn_form ( addr , mode , non_prefixed ) ; return ( iform == INSN_FORM_PREFIXED_NUMERIC || iform == INSN_FORM_PCREL_LOCAL ) ; } </s>

Return true if the address can be used for a prefixed load , store , or add immediate instructions that can not be used with a non-prefixed instruction . For example , using a numeric offset that is not valid for the non-prefixed instruction or a PC-relative reference to a local symbol would return true , but an address with an offset of 64 would not return true . References to external PC-relative symbols are n't allowed , because GCC has to load the address into a register and then issue a separate load or store .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
MachineInstr
&
MI
,
MachineRegisterInfo
&
MRI
,
MachineIRBuilder
&
MIRBuilder
,
GISelChangeObserver
&
Observer
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> static bool riscv_save_reg_p ( unsigned int regno ) { bool call_saved = ! global_regs [ regno ] && ! call_used_regs [ regno ] ; bool might_clobber = crtl -> saves_all_registers || df_regs_ever_live_p ( regno ) ; if ( call_saved && might_clobber ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && crtl -> calls_eh_return ) return true ; if ( cfun -> machine -> interrupt_handler_p ) { if ( regno == GP_REG_FIRST ) return false ; if ( regno == STACK_POINTER_REGNUM ) return false ; if ( regno == GP_REGNUM || regno == THREAD_POINTER_REGNUM ) return false ; if ( df_regs_ever_live_p ( regno ) || ( ! crtl -> is_leaf && call_used_regs [ regno ] ) ) return true ; } return false ; } </s>

Return true if the current function must save register REGNO .


<s> static tree mn10300_md_asm_clobbers ( tree outputs ATTRIBUTE_UNUSED , tree inputs ATTRIBUTE_UNUSED , tree clobbers ) { clobbers = tree_cons ( NULL_TREE , build_string ( 5 , "EPSW" ) , clobbers ) ; return clobbers ; } </s>

Worker function for TARGET_MD_ASM_CLOBBERS . We do this in the mn10300 backend to maintain source compatibility with the old cc0-based compiler .


<s>
ScheduleHazardRecognizer
::
HazardType
SPUHazardRecognizer
::
getHazardType
(
SUnit
*
SU
)
{
const
SDNode
*
Node
=
SU
->
getNode
(
)
->
getFlaggedMachineNode
(
)
;
ScheduleHazardRecognizer
::
HazardType
retval
=
NoHazard
;
bool
mustBeOdd
=
false
;
switch
(
Node
->
getOpcode
(
)
)
{
case
SPU
::
LQDv16i8
:
case
SPU
::
LQDv8i16
:
case
SPU
::
LQDv4i32
:
case
SPU
::
LQDv4f32
:
case
SPU
::
LQDv2f64
:
case
SPU
::
LQDr128
:
case
SPU
::
LQDr64
:
case
SPU
::
LQDr32
:
case
SPU
::
LQDr16
:
case
SPU
::
LQAv16i8
:
case
SPU
::
LQAv8i16
:
case
SPU
::
LQAv4i32
:
case
SPU
::
LQAv4f32
:
case
SPU
::
LQAv2f64
:
case
SPU
::
LQAr128
:
case
SPU
::
LQAr64
:
case
SPU
::
LQAr32
:
case
SPU
::
LQXv4i32
:
case
SPU
::
LQXr128
:
case
SPU
::
LQXr64
:
case
SPU
::
LQXr32
:
case
SPU
::
LQXr16
:
case
SPU
::
STQDv16i8
:
case
SPU
::
STQDv8i16
:
case
SPU
::
STQDv4i32
:
case
SPU
::
STQDv4f32
:
case
SPU
::
STQDv2f64
:
case
SPU
::
STQDr128
:
case
SPU
::
STQDr64
:
case
SPU
::
STQDr32
:
case
SPU
::
STQDr16
:
case
SPU
::
STQDr8
:
case
SPU
::
STQAv16i8
:
case
SPU
::
STQAv8i16
:
case
SPU
::
STQAv4i32
:
case
SPU
::
STQAv4f32
:
case
SPU
::
STQAv2f64
:
case
SPU
::
STQAr128
:
case
SPU
::
STQAr64
:
case
SPU
::
STQAr32
:
case
SPU
::
STQAr16
:
case
SPU
::
STQAr8
:
case
SPU
::
STQXv16i8
:
case
SPU
::
STQXv8i16
:
case
SPU
::
STQXv4i32
:
case
SPU
::
STQXv4f32
:
case
SPU
::
STQXv2f64
:
case
SPU
::
STQXr128
:
case
SPU
::
STQXr64
:
case
SPU
::
STQXr32
:
case
SPU
::
STQXr16
:
case
SPU
::
STQXr8
:
case
SPU
::
RET
:
mustBeOdd
=
true
;
break
;
default
:
break
;
}
if
(
mustBeOdd
&&
!
EvenOdd
)
retval
=
Hazard
;
DOUT
(
llvm
::
dbgs
(
)
<<
"SPUHazardRecognizer EvenOdd "
<<
EvenOdd
<<
" Hazard "
<<
retval
<<
"\n"
;
EvenOdd
^=
1
;
return
retval
;
return
NoHazard
;
}
</s>

getHazardType - Return the hazard type of emitting this node .


<s> outliner :: OutlinedFunction X86InstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { unsigned SequenceSize = std :: accumulate ( RepeatedSequenceLocs [ 0 ] . front ( ) , std :: next ( RepeatedSequenceLocs [ 0 ] . back ( ) ) , 0 , [ ] ( unsigned Sum , const MachineInstr & MI ) { if ( MI . isDebugInstr ( ) || MI . isKill ( ) ) return Sum ; return Sum + 1 ; } ) ; unsigned CFICount = 0 ; MachineBasicBlock :: iterator MBBI = RepeatedSequenceLocs [ 0 ] . front ( ) ; for ( unsigned Loc = RepeatedSequenceLocs [ 0 ] . getStartIdx ( ) ; Loc < RepeatedSequenceLocs [ 0 ] . getEndIdx ( ) + 1 ; Loc ++ ) { const std :: vector < MCCFIInstruction > & CFIInstructions = RepeatedSequenceLocs [ 0 ] . getMF ( ) -> getFrameInstructions ( ) ; if ( MBBI -> isCFIInstruction ( ) ) { unsigned CFIIndex = MBBI -> getOperand ( 0 ) . getCFIIndex ( ) ; MCCFIInstruction CFI = CFIInstructions [ CFIIndex ] ; CFICount ++ ; } MBBI ++ ; } for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { std :: vector < MCCFIInstruction > CFIInstructions = C . getMF ( ) -> getFrameInstructions ( ) ; if ( CFICount > 0 && CFICount != CFIInstructions . size ( ) ) return outliner :: OutlinedFunction ( ) ; } if ( RepeatedSequenceLocs [ 0 ] . back ( ) -> isTerminator ( ) ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerTailCall , 1 ) ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , 0 , MachineOutlinerTailCall ) ; } if ( CFICount > 0 ) return outliner :: OutlinedFunction ( ) ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerDefault , 1 ) ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , 1 , MachineOutlinerDefault ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


<s>
void
ARMAsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
,
MCContext
&
Ctx
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
IsPCRel
,
Ctx
,
IsLittleEndian
,
true
)
;
if
(
!
Value
)
return
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FullSizeBytes
;
if
(
!
IsLittleEndian
)
{
FullSizeBytes
=
getFixupKindContainerSizeBytes
(
Fixup
.
getKind
(
)
)
;
assert
(
(
Offset
+
FullSizeBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FullSizeBytes
&&
"Invalid fixup size!"
)
;
}
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
IsLittleEndian
i
:
(
FullSizeBytes
1
i
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static unsigned int ix86_autovectorize_vector_sizes ( void ) { return TARGET_AVX512F ? 64 | 32 | 16 : ( TARGET_AVX && ! TARGET_PREFER_AVX128 ) ? 32 | 16 : 0 ; } </s>

If AVX is enabled then try vectorizing with both 256bit and 128bit vectors . If AVX512F is enabled then try vectorizing with 512bit , 256bit and 128bit vectors .


<s> bool isValid ( ) const { return Valid ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s> virtual void EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> unsigned AGCRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return ~ 0u ; } </s>