"Multiply operation with an immediate and a register!"

"Divide operation with an immediate and a register!"

Produce a widened version of the select instruction .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
(
index
&
7
)
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
(
index
&
7
)
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
case
TYPE_MVSIBX
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MVSIBY
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_MVSIBZ
:
\
return
prefix
##
_ZMM0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> static void ix86_conditional_register_usage ( void ) { int i , c_mask ; if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } c_mask = ( TARGET_64BIT_MS_ABI ? ( 1 << 3 ) : TARGET_64BIT ? ( 1 << 2 ) : ( 1 << 1 ) ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > 1 ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; } if ( ! TARGET_MMX ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) MMX_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_SSE ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) SSE_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! ( TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ) ) for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) FLOAT_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; if ( ! TARGET_AVX512F ) { for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; for ( i = FIRST_MASK_REG ; i <= LAST_MASK_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } if ( ! TARGET_MPX ) for ( i = FIRST_BND_REG ; i <= LAST_BND_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = 1 , reg_names [ i ] = "" ; } </s>

Update register usage after having seen the compiler flags .


"Extending floating point arguments not supported yet"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static rtx_insn * mn10300_md_asm_adjust ( vec < rtx > & , vec < rtx > & , vec < machine_mode > & , vec < const char * > & , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , CC_REG ) ) ; SET_HARD_REG_BIT ( clobbered_regs , CC_REG ) ; return NULL ; } </s>

Worker function for TARGET_MD_ASM_ADJUST . We do this in the mn10300 backend to maintain source compatibility with the old cc0-based compiler .


<s> bool Cpu0SEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Cpu0 :: RetLR : expandRetLR ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> bool GCNPassConfig :: addInstSelector ( ) { AMDGPUPassConfig :: addInstSelector ( ) ; addPass ( createSILowerI1CopiesPass ( ) ) ; addPass ( & SIFixSGPRCopiesID ) ; addPass ( createSIFoldOperandsPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void bfin_expand_prologue ( void ) { rtx insn ; HOST_WIDE_INT frame_size = get_frame_size ( ) ; rtx spreg = gen_rtx_REG ( Pmode , REG_SP ) ; e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; rtx pic_reg_loaded = NULL_RTX ; if ( fkind != SUBROUTINE ) { expand_interrupt_handler_prologue ( spreg , fkind ) ; return ; } if ( current_function_limit_stack ) { HOST_WIDE_INT offset = bfin_initial_elimination_offset ( ARG_POINTER_REGNUM , STACK_POINTER_REGNUM ) ; rtx lim = stack_limit_rtx ; if ( GET_CODE ( lim ) == SYMBOL_REF ) { rtx p2reg = gen_rtx_REG ( Pmode , REG_P2 ) ; if ( TARGET_ID_SHARED_LIBRARY ) { rtx p1reg = gen_rtx_REG ( Pmode , REG_P1 ) ; rtx val ; pic_reg_loaded = bfin_load_pic_reg ( p2reg ) ; val = legitimize_pic_address ( stack_limit_rtx , p1reg , pic_reg_loaded ) ; emit_move_insn ( p1reg , val ) ; frame_related_constant_load ( p2reg , offset , FALSE ) ; emit_insn ( gen_addsi3 ( p2reg , p2reg , p1reg ) ) ; lim = p2reg ; } else { rtx limit = plus_constant ( stack_limit_rtx , offset ) ; emit_move_insn ( p2reg , limit ) ; lim = p2reg ; } } emit_insn ( gen_compare_lt ( bfin_cc_rtx , spreg , lim ) ) ; emit_insn ( gen_trapifcc ( ) ) ; } expand_prologue_reg_save ( spreg , 0 , false ) ; do_link ( spreg , frame_size , false ) ; if ( TARGET_ID_SHARED_LIBRARY && ( current_function_uses_pic_offset_table || ! current_function_is_leaf ) ) bfin_load_pic_reg ( pic_offset_table_rtx ) ; } </s>

Generate RTL for the prologue of the current function .


<s> bool X86TargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { int ShiftAmountOpNum = - 1 ; if ( I -> isShift ( ) ) ShiftAmountOpNum = 1 ; else if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { if ( II -> getIntrinsicID ( ) == Intrinsic :: fshl || II -> getIntrinsicID ( ) == Intrinsic :: fshr ) ShiftAmountOpNum = 2 ; } if ( ShiftAmountOpNum == - 1 ) return false ; auto * Shuf = dyn_cast < ShuffleVectorInst > ( I -> getOperand ( ShiftAmountOpNum ) ) ; if ( Shuf && getSplatIndex ( Shuf -> getShuffleMask ( ) ) >= 0 && isVectorShiftByScalarCheap ( I -> getType ( ) ) ) { Ops . push_back ( & I -> getOperandUse ( ShiftAmountOpNum ) ) ; return true ; } return false ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s> uint64_t MipsPLT :: emit ( MemoryRegion & pRegion ) { uint64_t result = 0x0 ; iterator it = begin ( ) ; unsigned char * buffer = pRegion . begin ( ) ; memcpy ( buffer , llvm :: cast < MipsPLT0 > ( ( * it ) ) . getValue ( ) , MipsPLT0 :: EntrySize ) ; result += MipsPLT0 :: EntrySize ; ++ it ; MipsPLTA * plta = 0 ; for ( iterator ie = end ( ) ; it != ie ; ++ it ) { plta = & ( llvm :: cast < MipsPLTA > ( * it ) ) ; memcpy ( buffer + result , plta -> getValue ( ) , MipsPLTA :: EntrySize ) ; result += MipsPLTA :: EntrySize ; } return result ; } </s>

Output the remark via the diagnostic handler and to the optimization record file .

Mips Mips 0x0 Mips Mips Mips Mips 0 Mips Mips Mips


<s> static void rs6000_emit_move_from_cr ( rtx reg ) { if ( DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF ) { int i , cr_reg [ 8 ] , count = 0 ; for ( i = 0 ; i < 8 ; i ++ ) if ( save_reg_p ( CR0_REGNO + i ) ) cr_reg [ count ++ ] = i ; if ( count == 1 ) { rtvec p = rtvec_alloc ( 1 ) ; rtvec r = rtvec_alloc ( 2 ) ; RTVEC_ELT ( r , 0 ) = gen_rtx_REG ( CCmode , CR0_REGNO + cr_reg [ 0 ] ) ; RTVEC_ELT ( r , 1 ) = GEN_INT ( 1 << ( 7 - cr_reg [ 0 ] ) ) ; RTVEC_ELT ( p , 0 ) = gen_rtx_SET ( VOIDmode , reg , gen_rtx_UNSPEC ( SImode , r , UNSPEC_MOVESI_FROM_CR ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; return ; } } emit_insn ( gen_movesi_from_cr ( reg ) ) ; } </s>

Emit code to store CR fields that need to be saved into REG .


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"Cannot store this register to stack slot!"

Store the specified register of the given register class to the specified stack frame index .


<s> static bool arc_cannot_substitute_mem_equiv_p ( rtx ) { return true ; } </s>

Return true if SUBST ca n't safely replace its equivalent during RA .


<s> static bool ix86_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( must_pass_in_stack_var_size_or_pad ( mode , type ) ) return true ; return ( ! TARGET_64BIT && mode == TImode && type && TREE_CODE ( type ) != VECTOR_TYPE ) ; } </s>

Return if we do not know how to pass TYPE solely in registers .


<s> int m32r_expand_block_move ( rtx operands [ ] ) { rtx orig_dst = operands [ 0 ] ; rtx orig_src = operands [ 1 ] ; rtx bytes_rtx = operands [ 2 ] ; rtx align_rtx = operands [ 3 ] ; int constp = CONST_INT_P ( bytes_rtx ) ; HOST_WIDE_INT bytes = constp ? INTVAL ( bytes_rtx ) : 0 ; int align = INTVAL ( align_rtx ) ; int leftover ; rtx src_reg ; rtx dst_reg ; if ( constp && bytes <= 0 ) return 1 ; dst_reg = copy_addr_to_reg ( XEXP ( orig_dst , 0 ) ) ; src_reg = copy_addr_to_reg ( XEXP ( orig_src , 0 ) ) ; if ( align > UNITS_PER_WORD ) align = UNITS_PER_WORD ; if ( optimize_size || ! constp || align != UNITS_PER_WORD ) { block_move_call ( dst_reg , src_reg , bytes_rtx ) ; return 0 ; } leftover = bytes % MAX_MOVE_BYTES ; bytes -= leftover ; if ( bytes ) { rtx_code_label * label = NULL ; rtx final_src = NULL_RTX ; rtx at_a_time = GEN_INT ( MAX_MOVE_BYTES ) ; rtx rounded_total = GEN_INT ( bytes ) ; rtx new_dst_reg = gen_reg_rtx ( SImode ) ; rtx new_src_reg = gen_reg_rtx ( SImode ) ; if ( bytes > MAX_MOVE_BYTES ) { final_src = gen_reg_rtx ( Pmode ) ; if ( INT16_P ( bytes ) ) emit_insn ( gen_addsi3 ( final_src , src_reg , rounded_total ) ) ; else { emit_insn ( gen_movsi ( final_src , rounded_total ) ) ; emit_insn ( gen_addsi3 ( final_src , final_src , src_reg ) ) ; } label = gen_label_rtx ( ) ; emit_label ( label ) ; } emit_insn ( gen_cpymemsi_internal ( dst_reg , src_reg , at_a_time , new_dst_reg , new_src_reg ) ) ; emit_move_insn ( dst_reg , new_dst_reg ) ; emit_move_insn ( src_reg , new_src_reg ) ; emit_insn ( gen_addsi3 ( dst_reg , dst_reg , GEN_INT ( 4 ) ) ) ; if ( bytes > MAX_MOVE_BYTES ) { rtx test = gen_rtx_NE ( VOIDmode , src_reg , final_src ) ; emit_jump_insn ( gen_cbranchsi4 ( test , src_reg , final_src , label ) ) ; } } if ( leftover ) emit_insn ( gen_cpymemsi_internal ( dst_reg , src_reg , GEN_INT ( leftover ) , gen_reg_rtx ( SImode ) , gen_reg_rtx ( SImode ) ) ) ; return 1 ; } </s>

Expand string/block move operations . operands [ 0 ] is the pointer to the destination . operands [ 1 ] is the pointer to the source . operands [ 2 ] is the number of bytes to move . operands [ 3 ] is the alignment .


<s> bool TeeRISCFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> static bool rs6000_use_blocks_for_decl_p ( const_tree decl ) { return ! DECL_THREAD_LOCAL_P ( decl ) ; } </s>

Do not place thread-local symbols refs in the object blocks .


<s> bool ARMPassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; bool MergeExternalByDefault = ! TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ; addPass ( createGlobalMergePass ( TM , 127 , OnlyOptimizeForSize , MergeExternalByDefault ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createHardwareLoopsPass ( ) ) ; addPass ( createMVETailPredicationPass ( ) ) ; } return false ; } </s>


<s> SDValue AArch64TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: SUB : return performAddSubLongCombine ( N , DCI , DAG ) ; case ISD :: XOR : return performXorCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: MUL : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : return performIntToFpCombine ( N , DAG ) ; case ISD :: OR : return performORCombine ( N , DCI , Subtarget ) ; case ISD :: INTRINSIC_WO_CHAIN : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case ISD :: ANY_EXTEND : case ISD :: ZERO_EXTEND : case ISD :: SIGN_EXTEND : return performExtendCombine ( N , DCI , DAG ) ; case ISD :: BITCAST : return performBitcastCombine ( N , DCI , DAG ) ; case ISD :: CONCAT_VECTORS : return performConcatVectorsCombine ( N , DCI , DAG ) ; case ISD :: SELECT : return performSelectCombine ( N , DAG ) ; case ISD :: VSELECT : return performVSelectCombine ( N , DCI . DAG ) ; case ISD :: STORE : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case AArch64ISD :: BRCOND : return performBRCONDCombine ( N , DCI , DAG ) ; case AArch64ISD :: CSEL : return performCONDCombine ( N , DCI , DAG , 2 , 3 ) ; case AArch64ISD :: DUP : return performPostLD1Combine ( N , DCI , false ) ; case ISD :: INSERT_VECTOR_ELT : return performPostLD1Combine ( N , DCI , true ) ; case ISD :: INTRINSIC_VOID : case ISD :: INTRINSIC_W_CHAIN : switch ( cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) ) { case Intrinsic :: aarch64_neon_ld2 : case Intrinsic :: aarch64_neon_ld3 : case Intrinsic :: aarch64_neon_ld4 : case Intrinsic :: aarch64_neon_ld1x2 : case Intrinsic :: aarch64_neon_ld1x3 : case Intrinsic :: aarch64_neon_ld1x4 : case Intrinsic :: aarch64_neon_ld2lane : case Intrinsic :: aarch64_neon_ld3lane : case Intrinsic :: aarch64_neon_ld4lane : case Intrinsic :: aarch64_neon_ld2r : case Intrinsic :: aarch64_neon_ld3r : case Intrinsic :: aarch64_neon_ld4r : case Intrinsic :: aarch64_neon_st2 : case Intrinsic :: aarch64_neon_st3 : case Intrinsic :: aarch64_neon_st4 : case Intrinsic :: aarch64_neon_st1x2 : case Intrinsic :: aarch64_neon_st1x3 : case Intrinsic :: aarch64_neon_st1x4 : case Intrinsic :: aarch64_neon_st2lane : case Intrinsic :: aarch64_neon_st3lane : case Intrinsic :: aarch64_neon_st4lane : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; default : break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s>
int
HexagonFrameLowering
::
getFrameIndexReference
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
)
const
{
auto
&
MFI
=
MF
.
getFrameInfo
(
)
;
auto
&
HRI
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
int
Offset
=
MFI
.
getObjectOffset
(
FI
)
;
bool
HasAlloca
=
MFI
.
hasVarSizedObjects
(
)
;
bool
HasExtraAlign
=
HRI
.
needsStackRealignment
(
MF
)
;
bool
NoOpt
=
MF
.
getTarget
(
)
.
getOptLevel
(
)
==
CodeGenOpt
::
;
unsigned
SP
=
HRI
.
getStackRegister
(
)
,
FP
=
HRI
.
getFrameRegister
(
)
;
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
unsigned
AP
=
HMFI
.
getStackAlignBasePhysReg
(
)
;
unsigned
FrameSize
=
MFI
.
getStackSize
(
)
;
bool
UseFP
=
false
,
UseAP
=
false
;
if
(
NoOpt
&&
!
HasExtraAlign
)
UseFP
=
true
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
||
MFI
.
isObjectPreAllocated
(
FI
)
)
{
UseFP
|=
(
HasAlloca
||
HasExtraAlign
)
;
}
else
{
if
(
HasAlloca
)
{
if
(
HasExtraAlign
)
UseAP
=
true
;
else
UseFP
=
true
;
}
}
bool
HasFP
=
hasFP
(
MF
)
;
assert
(
(
HasFP
||
!
UseFP
)
&&
"This function must have frame pointer"
)
;
if
(
Offset
>
0
&&
!
HasFP
)
Offset
-=
8
;
if
(
UseFP
)
FrameReg
=
FP
;
else
if
(
UseAP
)
FrameReg
=
AP
;
else
FrameReg
=
SP
;
int
RealOffset
=
Offset
;
if
(
!
UseFP
&&
!
UseAP
&&
HasFP
)
RealOffset
=
FrameSize
+
Offset
;
return
RealOffset
;
}
</s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .

Hexagon
Hexagon
Hexagon
Hexagon
"This function must have frame pointer"
0
8


<s> bool ARMBaseTargetMachine :: addPreEmitPass ( PassManagerBase & PM ) { if ( Subtarget . isThumb2 ( ) && ! Subtarget . prefers32BitThumb ( ) ) PM . add ( createThumb2SizeReductionPass ( ) ) ; PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> unsigned GCNSubtarget :: getOccupancyWithNumSGPRs ( unsigned SGPRs ) const { if ( getGeneration ( ) >= AMDGPUSubtarget :: GFX10 ) return 10 ; if ( getGeneration ( ) >= AMDGPUSubtarget :: VOLCANIC_ISLANDS ) { if ( SGPRs <= 80 ) return 10 ; if ( SGPRs <= 88 ) return 9 ; if ( SGPRs <= 100 ) return 8 ; return 7 ; } if ( SGPRs <= 48 ) return 10 ; if ( SGPRs <= 56 ) return 9 ; if ( SGPRs <= 64 ) return 8 ; if ( SGPRs <= 72 ) return 7 ; if ( SGPRs <= 80 ) return 6 ; return 5 ; } </s>

Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs .


<s> bool legitimate_constant_pool_address_p ( rtx x ) { return ( TARGET_TOC && GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , 0 ) ) == REG && ( TARGET_MINIMAL_TOC || REGNO ( XEXP ( x , 0 ) ) == TOC_REGISTER ) && constant_pool_expr_p ( XEXP ( x , 1 ) ) ) ; } </s>

Return true if X is a constant pool address , and also for cmodel=medium if X is a toc-relative address known to be offsettable within MODE .


<s> static int ix86_int_cmp_code_to_pcmp_immediate ( enum rtx_code code ) { switch ( code ) { case EQ : return 0 ; case LT : case LTU : return 1 ; case LE : case LEU : return 2 ; case NE : return 4 ; case GE : case GEU : return 5 ; case GT : case GTU : return 6 ; default : gcc_unreachable ( ) ; } } </s>

Helper for ix86_cmp_code_to_pcmp_immediate for int modes .


<s> bool PPCQPXLoadSplat :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; bool MadeChange = false ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; for ( auto MFI = MF . begin ( ) , MFIE = MF . end ( ) ; MFI != MFIE ; ++ MFI ) { MachineBasicBlock * MBB = & * MFI ; SmallVector < MachineInstr * , 4 > Splats ; for ( auto MBBI = MBB -> rbegin ( ) ; MBBI != MBB -> rend ( ) ; ++ MBBI ) { MachineInstr * MI = & * MBBI ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isCall ( ) ) { Splats . clear ( ) ; continue ; } for ( auto SI = Splats . begin ( ) ; SI != Splats . end ( ) ; ) { MachineInstr * SMI = * SI ; unsigned SplatReg = SMI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = SMI -> getOperand ( 1 ) . getReg ( ) ; if ( MI -> modifiesRegister ( SrcReg , TRI ) ) { switch ( MI -> getOpcode ( ) ) { default : SI = Splats . erase ( SI ) ; continue ; case PPC :: LFS : case PPC :: LFD : case PPC :: LFSU : case PPC :: LFDU : case PPC :: LFSUX : case PPC :: LFDUX : case PPC :: LFSX : case PPC :: LFDX : case PPC :: LFIWAX : case PPC :: LFIWZX : if ( SplatReg != SrcReg ) { unsigned SubRegIndex = TRI -> getSubRegIndex ( SrcReg , MI -> getOperand ( 0 ) . getReg ( ) ) ; unsigned SplatSubReg = TRI -> getSubReg ( SplatReg , SubRegIndex ) ; MI -> getOperand ( 0 ) . setReg ( SplatSubReg ) ; MI -> substituteRegister ( SrcReg , SplatReg , 0 , * TRI ) ; } SI = Splats . erase ( SI ) ; ++ MBBI ; SMI -> eraseFromParent ( ) ; -- MBBI ; ++ NumSimplified ; MadeChange = true ; continue ; } } if ( MI -> modifiesRegister ( SplatReg , TRI ) || ( SrcReg != SplatReg && MI -> readsRegister ( SplatReg , TRI ) ) ) { SI = Splats . erase ( SI ) ; continue ; } ++ SI ; } if ( MI -> getOpcode ( ) != PPC :: QVESPLATI && MI -> getOpcode ( ) != PPC :: QVESPLATIs && MI -> getOpcode ( ) != PPC :: QVESPLATIb ) continue ; if ( MI -> getOperand ( 2 ) . getImm ( ) != 0 ) continue ; if ( ! MI -> getOperand ( 1 ) . isKill ( ) ) continue ; Splats . push_back ( MI ) ; } } return MadeChange ; } </s>

runOnMachineFunction - Emit the function body .


<s> void emit_ap_optimizations ( ) { } </s>

Here after reloading , before the second scheduling pass .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> const char * DCPU16TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case DCPU16ISD :: RET_FLAG : return "DCPU16ISD::RET_FLAG" ; case DCPU16ISD :: RETI_FLAG : return "DCPU16ISD::RETI_FLAG" ; case DCPU16ISD :: CALL : return "DCPU16ISD::CALL" ; case DCPU16ISD :: Wrapper : return "DCPU16ISD::Wrapper" ; case DCPU16ISD :: BR_CC : return "DCPU16ISD::BR_CC" ; case DCPU16ISD :: SELECT_CC : return "DCPU16ISD::SELECT_CC" ; case DCPU16ISD :: SMUL : return "DCPU16ISD::SMUL" ; case DCPU16ISD :: UMUL : return "DCPU16ISD::UMUL" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool SIInsertWaits :: runOnMachineFunction ( MachineFunction & MF ) { bool Changes = false ; TII = static_cast < const SIInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = static_cast < const SIRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; MRI = & MF . getRegInfo ( ) ; WaitedOn = ZeroCounts ; LastIssued = ZeroCounts ; LastOpcodeType = OTHER ; LastInstWritesM0 = false ; memset ( & UsedRegs , 0 , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , 0 , sizeof ( DefinedRegs ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == AMDGPU :: S_BARRIER ) Changes |= insertWait ( MBB , I , LastIssued ) ; else Changes |= insertWait ( MBB , I , handleOperands ( * I ) ) ; pushInstruction ( MBB , I ) ; handleSendMsg ( MBB , I ) ; } Changes |= insertWait ( MBB , MBB . getFirstTerminator ( ) , LastIssued ) ; } return Changes ; } </s>


<s> void R600InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , MCRegister DestReg , MCRegister SrcReg , bool KillSrc ) const { unsigned VectorComponents = 0 ; if ( ( R600 :: R600_Reg128RegClass . contains ( DestReg ) || R600 :: R600_Reg128VerticalRegClass . contains ( DestReg ) ) && ( R600 :: R600_Reg128RegClass . contains ( SrcReg ) || R600 :: R600_Reg128VerticalRegClass . contains ( SrcReg ) ) ) { VectorComponents = 4 ; } else if ( ( R600 :: R600_Reg64RegClass . contains ( DestReg ) || R600 :: R600_Reg64VerticalRegClass . contains ( DestReg ) ) && ( R600 :: R600_Reg64RegClass . contains ( SrcReg ) || R600 :: R600_Reg64VerticalRegClass . contains ( SrcReg ) ) ) { VectorComponents = 2 ; } if ( VectorComponents > 0 ) { for ( unsigned I = 0 ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = R600RegisterInfo :: getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , R600 :: MOV , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , R600 :: MOV , DestReg , SrcReg ) ; NewMI -> getOperand ( getOperandIdx ( * NewMI , R600 :: OpName :: src0 ) ) . setIsKill ( KillSrc ) ; } } </s>


<s> int arm_coproc_mem_operand_no_writeback ( rtx op ) { return arm_coproc_mem_operand_wb ( op , 0 ) ; } </s>

Return TRUE if OP is a valid coprocessor memory address pattern in a context in which no writeback address modes are allowed .


<s> virtual const GBZ80InstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> bool MipsFastISel :: fastLowerCall ( CallLoweringInfo & CLI ) { CallingConv :: ID CC = CLI . CallConv ; bool IsTailCall = CLI . IsTailCall ; bool IsVarArg = CLI . IsVarArg ; const Value * Callee = CLI . Callee ; const char * SymName = CLI . SymName ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = MVT :: isVoid ; else if ( ! isTypeSupported ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , 16 > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == MVT :: i1 || VT == MVT :: i8 || VT == MVT :: i16 ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > 64 ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; if ( ! Addr . getGlobalValue ( ) ) return false ; unsigned DestAddress ; if ( SymName ) DestAddress = materializeExternalCallSym ( SymName ) ; else DestAddress = materializeGV ( Addr . getGlobalValue ( ) , MVT :: i32 ) ; emitInst ( TargetOpcode :: COPY , Mips :: T9 ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Mips :: JALR ) , Mips :: RA ) . addReg ( Mips :: T9 ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call = MIB ; return finishCall ( CLI , RetVT , NumBytes ) ; } </s>

This method is called by target-independent code to do target- specific call lowering .


<s> MipsTargetLowering :: ConstraintType MipsTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'd' : case 'y' : case 'f' : case 'c' : case 'l' : case 'x' : case 'C' : return C_RegisterClass ; case 'R' : return C_Memory ; } } if ( Constraint == "ZC" ) return C_Memory ; return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; if ( STI . hasMOPS ( ) ) { return EmitMOPS ( AArch64ISD :: MOPS_MEMSET , DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , MachinePointerInfo { } ) ; } ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const char * bzeroName = ( V && V -> isZero ( ) ) ? DAG . getTargetLoweringInfo ( ) . getLibcallName ( RTLIB :: BZERO ) : nullptr ; if ( bzeroName && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = Type :: getInt8PtrTy ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroName , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> static void mips_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; struct mips_arg_info info ; mips_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named ) ; if ( ! info . fpr_p ) cum -> gp_reg_found = true ; if ( cum -> arg_number < 2 && info . fpr_p ) cum -> fp_code += ( arg . mode == SFmode ? 1 : 2 ) << ( cum -> arg_number * 2 ) ; if ( mips_abi != ABI_EABI || ! info . fpr_p ) cum -> num_gprs = info . reg_offset + info . reg_words ; else if ( info . reg_words > 0 ) cum -> num_fprs += MAX_FPRS_PER_FMT ; if ( info . stack_words > 0 ) cum -> stack_words = info . stack_offset + info . stack_words ; cum -> arg_number ++ ; } </s>


"instruction use requires an option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> unsigned SIInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; const MCInstrDesc & Desc = getMCOpcodeFromPseudo ( Opc ) ; unsigned DescSize = Desc . getSize ( ) ; if ( isFixedSize ( MI ) ) return DescSize ; if ( isVALU ( MI ) || isSALU ( MI ) ) { int Src0Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src0 ) ; if ( Src0Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src0Idx ) , Desc . OpInfo [ Src0Idx ] ) ) return DescSize + 4 ; int Src1Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src1 ) ; if ( Src1Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src1Idx ) , Desc . OpInfo [ Src1Idx ] ) ) return DescSize + 4 ; int Src2Idx = AMDGPU :: getNamedOperandIdx ( Opc , AMDGPU :: OpName :: src2 ) ; if ( Src2Idx == - 1 ) return DescSize ; if ( isLiteralConstantLike ( MI . getOperand ( Src2Idx ) , Desc . OpInfo [ Src2Idx ] ) ) return DescSize + 4 ; return DescSize ; } switch ( Opc ) { case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : case TargetOpcode :: EH_LABEL : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleSize ( MI ) ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } default : return DescSize ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool TVMStackModel :: processInstruction ( MachineInstr & MI , Stack & TheStack ) { SlotIndex Index = LIS -> getInstructionIndex ( MI ) . getRegSlot ( ) ; MachineInstr * NewMI = optimizeReversible ( MI , TheStack ) ; MachineInstr & CurrentMI = NewMI ? * NewMI : MI ; auto * MBB = CurrentMI . getParent ( ) ; StackFixup :: InstructionGenerator InsertMIs ( TII , MFI , MBB , CurrentMI ) ; std :: string PreTermStackStr ; StackFixup Fix = prepareStackFor ( CurrentMI , TheStack , Index , & PreTermStackStr ) ; InsertMIs ( Fix ) ; Fix . apply ( TheStack ) ; modelInstructionExecution ( CurrentMI , TheStack ) ; rewriteToSForm ( CurrentMI , PreTermStackStr , TheStack ) ; return true ; } </s>

Process a single instruction and collect debug info anchors .


<s> int ia64_move_ok ( rtx dst , rtx src ) { if ( GET_CODE ( dst ) != MEM ) return 1 ; if ( GET_CODE ( src ) == MEM ) return 0 ; if ( register_operand ( src , VOIDmode ) ) return 1 ; if ( INTEGRAL_MODE_P ( GET_MODE ( dst ) ) ) return src == const0_rtx ; else return satisfies_constraint_G ( src ) ; } </s>

Return 1 if the operands of a move are ok .


<s>
Register
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
EVT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
MatchRegisterName
(
RegName
)
;
if
(
AArch64
::
X1
<=
Reg
&&
Reg
<=
AArch64
::
X28
)
{
const
MCRegisterInfo
*
MRI
=
Subtarget
->
getRegisterInfo
(
)
;
unsigned
DwarfRegNum
=
MRI
->
getDwarfRegNum
(
Reg
,
false
)
;
if
(
!
Subtarget
->
isXRegisterReserved
(
DwarfRegNum
)
)
Reg
=
0
;
}
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


<s> inline void function_expander :: add_output_operand ( machine_mode mode , rtx target ) { create_output_operand ( & m_ops [ opno ++ ] , target , mode ) ; } </s>

Create output and add it into M_OPS and increase OPNO .


<s> static rtx mips_force_binary ( machine_mode mode , enum rtx_code code , rtx op0 , rtx op1 ) { rtx reg ; reg = gen_reg_rtx ( mode ) ; mips_emit_binary ( code , reg , op0 , op1 ) ; return reg ; } </s>

Compute ( CODE OP0 OP1 ) and store the result in a new register of mode MODE . Return that new register .


<s> Value * X86TargetLowering :: getIRStackGuard ( IRBuilder < > & IRB ) const { if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x10 , getAddressSpace ( ) ) ; } else { unsigned AddressSpace = getAddressSpace ( ) ; Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; int Offset = M -> getStackProtectorGuardOffset ( ) ; if ( Offset == INT_MAX ) Offset = ( Subtarget . is64Bit ( ) ) ? 0x28 : 0x14 ; StringRef GuardReg = M -> getStackProtectorGuardReg ( ) ; if ( GuardReg == "fs" ) AddressSpace = X86AS :: FS ; else if ( GuardReg == "gs" ) AddressSpace = X86AS :: GS ; return SegmentOffset ( IRB , Offset , AddressSpace ) ; } } return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


"emitPrologue doesn't support framepointer-less functions"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> int frv_emit_cond_branch ( enum rtx_code test , rtx label ) { rtx test_rtx ; rtx label_ref ; rtx if_else ; rtx cc_reg = frv_emit_comparison ( test , frv_compare_op0 , frv_compare_op1 ) ; enum machine_mode cc_mode = GET_MODE ( cc_reg ) ; label_ref = gen_rtx_LABEL_REF ( VOIDmode , label ) ; test_rtx = gen_rtx_fmt_ee ( test , cc_mode , cc_reg , const0_rtx ) ; if_else = gen_rtx_IF_THEN_ELSE ( cc_mode , test_rtx , label_ref , pc_rtx ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , if_else ) ) ; return TRUE ; } </s>

Emit code for a conditional branch . The comparison operands were previously stored in frv_compare_op0 and frv_compare_op1 . XXX : I originally wanted to add a clobber of a CCR register to use in conditional execution , but that confuses the rest of the compiler .


<s> Register VEInstrInfo :: getGlobalBaseReg ( MachineFunction * MF ) const { VEMachineFunctionInfo * VEFI = MF -> getInfo < VEMachineFunctionInfo > ( ) ; Register GlobalBaseReg = VEFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; GlobalBaseReg = VE :: SX15 ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc dl ; BuildMI ( FirstMBB , MBBI , dl , get ( VE :: GETGOT ) , GlobalBaseReg ) ; VEFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .

VE VE VE VE VE VE 0 VE::SX15 VE::GETGOT VE


Return an array that contains the direct target flag values and their names .


<s> static bool aarch64_tls_symbol_p ( rtx x ) { if ( ! TARGET_HAVE_TLS ) return false ; x = strip_salt ( x ) ; if ( ! SYMBOL_REF_P ( x ) ) return false ; return SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return true if SYMBOL_REF X is thread local


<s> bool runOnFunction ( Function & F ) { PHINodeSet PromotablePHINodes = getPromotablePHINodes ( F ) ; B2IMap Bool2IntMap ; bool Changed = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { if ( ReturnInst * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( R -> getOperandUse ( 0 ) , PromotablePHINodes , Bool2IntMap ) ; if ( CallInst * CI = dyn_cast < CallInst > ( & I ) ) for ( auto & U : CI -> operands ( ) ) if ( U -> getType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( U , PromotablePHINodes , Bool2IntMap ) ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool HexagonVExtract :: runOnMachineFunction ( MachineFunction & MF ) { HST = & MF . getSubtarget < HexagonSubtarget > ( ) ; HII = HST -> getInstrInfo ( ) ; const auto & HRI = * HST -> getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; std :: map < unsigned , SmallVector < MachineInstr * , 4 >> VExtractMap ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { unsigned Opc = MI . getOpcode ( ) ; if ( Opc != Hexagon :: V6_extractw ) continue ; Register VecR = MI . getOperand ( 1 ) . getReg ( ) ; VExtractMap [ VecR ] . push_back ( & MI ) ; } } for ( auto & P : VExtractMap ) { unsigned VecR = P . first ; if ( P . second . size ( ) <= VExtractThreshold ) continue ; const auto & VecRC = * MRI . getRegClass ( VecR ) ; int FI = MFI . CreateSpillStackObject ( HRI . getSpillSize ( VecRC ) , HRI . getSpillAlignment ( VecRC ) ) ; MachineInstr * DefI = MRI . getVRegDef ( VecR ) ; MachineBasicBlock :: iterator At = std :: next ( DefI -> getIterator ( ) ) ; MachineBasicBlock & DefB = * DefI -> getParent ( ) ; unsigned StoreOpc = VecRC . getID ( ) == Hexagon :: HvxVRRegClassID ? Hexagon :: V6_vS32b_ai : Hexagon :: PS_vstorerw_ai ; BuildMI ( DefB , At , DefI -> getDebugLoc ( ) , HII -> get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( VecR ) ; unsigned VecSize = HRI . getRegSizeInBits ( VecRC ) / 8 ; for ( MachineInstr * ExtI : P . second ) { assert ( ExtI -> getOpcode ( ) == Hexagon :: V6_extractw ) ; unsigned SR = ExtI -> getOperand ( 1 ) . getSubReg ( ) ; assert ( ExtI -> getOperand ( 1 ) . getReg ( ) == VecR ) ; MachineBasicBlock & ExtB = * ExtI -> getParent ( ) ; DebugLoc DL = ExtI -> getDebugLoc ( ) ; Register BaseR = MRI . createVirtualRegister ( & Hexagon :: IntRegsRegClass ) ; BuildMI ( ExtB , ExtI , DL , HII -> get ( Hexagon :: PS_fi ) , BaseR ) . addFrameIndex ( FI ) . addImm ( SR == 0 ? 0 : VecSize / 2 ) ; unsigned ElemR = genElemLoad ( ExtI , BaseR , MRI ) ; Register ExtR = ExtI -> getOperand ( 0 ) . getReg ( ) ; MRI . replaceRegWith ( ExtR , ElemR ) ; ExtB . erase ( ExtI ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86Subtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_NONE ; CriticalPathRCs . clear ( ) ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> MVT MipsTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) { if ( Subtarget . isABI_O32 ( ) ) { return MVT :: i32 ; } else { return ( VT . getSizeInBits ( ) == 32 ) ? MVT :: i32 : MVT :: i64 ; } } return MipsTargetLowering :: getRegisterType ( Context , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> X86Subtarget :: X86Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const X86TargetMachine & TM , MaybeAlign StackAlignOverride , unsigned PreferVectorWidthOverride , unsigned RequiredVectorWidth ) : X86GenSubtargetInfo ( TT , CPU , FS ) , PICStyle ( PICStyles :: None ) , TM ( TM ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , PreferVectorWidthOverride ( PreferVectorWidthOverride ) , RequiredVectorWidth ( RequiredVectorWidth ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( * this , getStackAlignment ( ) ) { if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new X86CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new X86LegalizerInfo ( * this , TM ) ) ; auto * RBI = new X86RegisterBankInfo ( * getRegisterInfo ( ) ) ; RegBankInfo . reset ( RBI ) ; InstSelector . reset ( createX86InstructionSelector ( TM , * this , * RBI ) ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void ix86_expand_vector_convert_uns_vsivsf ( rtx target , rtx val ) { rtx tmp [ 8 ] ; REAL_VALUE_TYPE TWO16r ; machine_mode intmode = GET_MODE ( val ) ; machine_mode fltmode = GET_MODE ( target ) ; rtx ( * cvt ) ( rtx , rtx ) ; if ( intmode == V4SImode ) cvt = gen_floatv4siv4sf2 ; else cvt = gen_floatv8siv8sf2 ; tmp [ 0 ] = ix86_build_const_vector ( intmode , 1 , GEN_INT ( 0xffff ) ) ; tmp [ 0 ] = force_reg ( intmode , tmp [ 0 ] ) ; tmp [ 1 ] = expand_simple_binop ( intmode , AND , val , tmp [ 0 ] , NULL_RTX , 1 , OPTAB_DIRECT ) ; tmp [ 2 ] = expand_simple_binop ( intmode , LSHIFTRT , val , GEN_INT ( 16 ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; tmp [ 3 ] = gen_reg_rtx ( fltmode ) ; emit_insn ( cvt ( tmp [ 3 ] , tmp [ 1 ] ) ) ; tmp [ 4 ] = gen_reg_rtx ( fltmode ) ; emit_insn ( cvt ( tmp [ 4 ] , tmp [ 2 ] ) ) ; real_ldexp ( & TWO16r , & dconst1 , 16 ) ; tmp [ 5 ] = const_double_from_real_value ( TWO16r , SFmode ) ; tmp [ 5 ] = force_reg ( fltmode , ix86_build_const_vector ( fltmode , 1 , tmp [ 5 ] ) ) ; if ( TARGET_FMA ) { tmp [ 6 ] = gen_rtx_FMA ( fltmode , tmp [ 4 ] , tmp [ 5 ] , tmp [ 3 ] ) ; emit_move_insn ( target , tmp [ 6 ] ) ; } else { tmp [ 6 ] = expand_simple_binop ( fltmode , MULT , tmp [ 4 ] , tmp [ 5 ] , NULL_RTX , 1 , OPTAB_DIRECT ) ; tmp [ 7 ] = expand_simple_binop ( fltmode , PLUS , tmp [ 3 ] , tmp [ 6 ] , target , 1 , OPTAB_DIRECT ) ; if ( tmp [ 7 ] != target ) emit_move_insn ( target , tmp [ 7 ] ) ; } } </s>

floatunsv { 4,8 } siv { 4,8 } sf2 expander . Expand code to convert a vector of unsigned ints VAL to vector of floats TARGET .


<s> unsigned SIInstrInfo :: getAddressSpaceForPseudoSourceKind ( unsigned Kind ) const { switch ( Kind ) { case PseudoSourceValue :: Stack : case PseudoSourceValue :: FixedStack : return AMDGPUAS :: PRIVATE_ADDRESS ; case PseudoSourceValue :: ConstantPool : case PseudoSourceValue :: GOT : case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom : return AMDGPUAS :: CONSTANT_ADDRESS ; } return AMDGPUAS :: FLAT_ADDRESS ; } </s>

getAddressSpaceForPseudoSourceKind - Given the kind of memory ( e.g .


<s> void ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( & MachinePipelinerID ) ; addPass ( createMVETPAndVPTOptimisationsPass ( ) ) ; addPass ( createMLxExpansionPass ( ) ) ; if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( ! DisableA15SDOptimization ) addPass ( createA15SDOptimizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> const MCExpr * CSKYTargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr , SMLoc Loc , const MCExpr * AdjustExpr ) { auto ELFRefKind = CSKYMCExpr :: VK_CSKY_Invalid ; ConstantCounter ++ ; const MCExpr * OrigExpr = Expr ; if ( const CSKYMCExpr * CE = dyn_cast < CSKYMCExpr > ( Expr ) ) { Expr = CE -> getSubExpr ( ) ; ELFRefKind = CE -> getKind ( ) ; } if ( const MCSymbolRefExpr * SymExpr = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { const MCSymbol * Sym = & SymExpr -> getSymbol ( ) ; SymbolIndex Index = { Sym , ELFRefKind } ; if ( ConstantMap . find ( Index ) == ConstantMap . end ( ) ) { ConstantMap [ Index ] = ConstantPool -> addEntry ( getStreamer ( ) , OrigExpr , 4 , Loc , AdjustExpr ) ; } return ConstantMap [ Index ] ; } return ConstantPool -> addEntry ( getStreamer ( ) , Expr , 4 , Loc , AdjustExpr ) ; } </s>

Add a new entry to the constant pool for the current section and return an MCExpr that can be used to refer to the constant pool location .


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ; return createSparcELFObjectWriter ( OS , is64Bit ( ) , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void JVMTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; } </s>

This method must be called before any actual lowering is done .


<s> static machine_mode nvptx_promote_function_mode ( const_tree type , machine_mode mode , int * ARG_UNUSED ( punsignedp ) , const_tree funtype , int for_return ) { return promote_arg ( mode , for_return || ! type || TYPE_ARG_TYPES ( funtype ) ) ; } </s>


<s> static int mips_register_priority ( int hard_regno ) { if ( TARGET_MIPS16 && TEST_HARD_REG_BIT ( reg_class_contents [ M16_REGS ] , hard_regno ) ) return 1 ; return 0 ; } </s>


<s> void DLXTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> bool ARMBaseInstrInfo :: isPredicated ( const MachineInstr & MI ) const { if ( MI . isBundle ( ) ) { MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ; while ( ++ I != E && I -> isInsideBundle ( ) ) { int PIdx = I -> findFirstPredOperandIdx ( ) ; if ( PIdx != - 1 && I -> getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ) return true ; } return false ; } int PIdx = MI . findFirstPredOperandIdx ( ) ; return PIdx != - 1 && MI . getOperand ( PIdx ) . getImm ( ) != ARMCC :: AL ; } </s>

Returns true if the instruction is already predicated .


<s> bool llvm :: getAlign ( const CallInst & I , unsigned index , unsigned & align ) { if ( MDNode * alignNode = I . getMDNode ( "callalign" ) ) { for ( int i = 0 , n = alignNode -> getNumOperands ( ) ; i < n ; i ++ ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( alignNode -> getOperand ( i ) ) ) { unsigned v = CI -> getZExtValue ( ) ; if ( ( v >> 16 ) == index ) { align = v & 0xFFFF ; return true ; } if ( ( v >> 16 ) > index ) { return false ; } } } } return false ; } </s>

Return the minimum known alignment in bytes of the actual memory reference .


<s> static bool arm_fastmul_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB1 ) { * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = COSTS_N_INSNS ( 2 ) ; return false ; } if ( mode == DImode ) { * total = COSTS_N_INSNS ( 5 ) ; return false ; } if ( CONST_INT_P ( XEXP ( x , 1 ) ) ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 8 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; return false ; } if ( mode == SImode ) { * total = COSTS_N_INSNS ( 4 ) ; return false ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { if ( TARGET_HARD_FLOAT && ( mode == SFmode || ( mode == DFmode && ! TARGET_VFP_SINGLE ) ) ) { * total = COSTS_N_INSNS ( 1 ) ; return false ; } } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; } } </s>

RTX cost for cores with a fast multiply unit ( M variants ) .


<s> bool enableEarlyIfConversion ( ) const override { return true ; } </s>

Enable the use of the early if conversion pass .


<s> StringRef getVendorName ( ) const { return StringRef ( names , vendor_name_size - 1 ) ; } </s>

Get the vendor ( second ) component of the triple .


<s> static bool split_mem_address ( rtx addr , rtx * base_reg , rtx * offset ) { if ( REG_P ( addr ) ) { * base_reg = addr ; * offset = const0_rtx ; return true ; } else if ( GET_CODE ( addr ) == PLUS ) { * base_reg = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return true ; } return false ; } </s>

Utility function to break a memory address into base register + constant offset . Return false if something unexpected is seen .


"invalid feature modifier %qs in %<-march=%s%>"

Validate a command-line -march option . Parse the arch and extensions ( if any ) specified in STR and throw errors if appropriate . Put the results , if they are valid , in RES and ISA_FLAGS . Return whether the option is valid .


<s> int register_ok_for_ldd ( rtx reg ) { if ( ! REG_P ( reg ) ) return 0 ; if ( REGNO ( reg ) < FIRST_PSEUDO_REGISTER ) return ( REGNO ( reg ) % 2 == 0 ) ; return 1 ; } </s>

Return 1 if reg is a pseudo , or is the first register in a hard register pair . This makes it a candidate for use in ldd and std insns .


<s> bool systemSupportsUnalignedAccess ( unsigned AS = 0 ) const { return hasMips32r6 ( ) ; } </s>

Does the system support unaligned memory access .


"NVPTX optimize redundant cvta.to.local instruction"

getPassName - Return a nice clean name for a pass .


<s> virtual const PPCRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool nios2_legitimate_address_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx operand , bool strict_p ) { switch ( GET_CODE ( operand ) ) { case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( operand ) ) return false ; if ( nios2_symbol_ref_in_small_data_p ( operand ) ) return true ; case LABEL_REF : case CONST_INT : case CONST : case CONST_DOUBLE : return false ; case REG : return nios2_regno_ok_for_base_p ( REGNO ( operand ) , strict_p ) ; case PLUS : { rtx op0 = XEXP ( operand , 0 ) ; rtx op1 = XEXP ( operand , 1 ) ; return ( nios2_valid_addr_expr_p ( op0 , op1 , strict_p ) || nios2_valid_addr_expr_p ( op1 , op0 , strict_p ) ) ; } default : break ; } return false ; } </s>


<s> void BPFAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { customEmitInstruction ( I ++ ) ; } while ( ( I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> static int flow_dependent_p ( rtx insn , rtx dep_insn ) { rtx tmp = PATTERN ( insn ) ; note_stores ( PATTERN ( dep_insn ) , flow_dependent_p_1 , & tmp ) ; return tmp == NULL_RTX ; } </s>

Check if INSN is flow-dependent on DEP_INSN . Can also be used to check if DEP_INSN is anti-flow dependent on INSN .


<s> unsigned getNumFixupKinds ( ) const override { return LC3 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> static machine_mode s390_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_VXE ) switch ( mode ) { case E_SFmode : return V4SFmode ; default : ; } if ( TARGET_VX ) switch ( mode ) { case E_DFmode : return V2DFmode ; case E_DImode : return V2DImode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; default : ; } return word_mode ; } </s>

Return the vector mode to be used for inner mode MODE when doing vectorization .


<s> static void ia64_trampoline_init ( rtx m_tramp , tree fndecl , rtx static_chain ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx addr , addr_reg , tramp , eight = GEN_INT ( 8 ) ; if ( ! TARGET_GNU_AS ) { static bool declared_ia64_trampoline = false ; if ( ! declared_ia64_trampoline ) { declared_ia64_trampoline = true ; ( * targetm . asm_out . globalize_label ) ( asm_out_file , "__ia64_trampoline" ) ; } } addr = convert_memory_address ( Pmode , XEXP ( m_tramp , 0 ) ) ; fnaddr = convert_memory_address ( Pmode , fnaddr ) ; static_chain = convert_memory_address ( Pmode , static_chain ) ; addr_reg = copy_to_reg ( addr ) ; m_tramp = adjust_automodify_address ( m_tramp , Pmode , addr_reg , 0 ) ; tramp = gen_rtx_SYMBOL_REF ( Pmode , "__ia64_trampoline" ) ; if ( TARGET_ABI_OPEN_VMS ) { rtx reg = gen_reg_rtx ( Pmode ) ; SYMBOL_REF_FLAGS ( tramp ) |= SYMBOL_FLAG_FUNCTION ; emit_move_insn ( reg , tramp ) ; emit_move_insn ( reg , gen_rtx_MEM ( Pmode , reg ) ) ; tramp = reg ; } emit_move_insn ( m_tramp , tramp ) ; emit_insn ( gen_adddi3 ( addr_reg , addr_reg , eight ) ) ; m_tramp = adjust_automodify_address ( m_tramp , VOIDmode , NULL , 8 ) ; emit_move_insn ( m_tramp , force_reg ( Pmode , plus_constant ( Pmode , addr , 16 ) ) ) ; emit_insn ( gen_adddi3 ( addr_reg , addr_reg , eight ) ) ; m_tramp = adjust_automodify_address ( m_tramp , VOIDmode , NULL , 8 ) ; emit_move_insn ( m_tramp , force_reg ( Pmode , fnaddr ) ) ; emit_insn ( gen_adddi3 ( addr_reg , addr_reg , eight ) ) ; m_tramp = adjust_automodify_address ( m_tramp , VOIDmode , NULL , 8 ) ; emit_move_insn ( m_tramp , static_chain ) ; } </s>

Implement TARGET_TRAMPOLINE_INIT . The trampoline should set the static chain pointer to value placed into the trampoline and should branch to the specified routine . To make the normal indirect-subroutine calling convention work , the trampoline must look like a function descriptor ; the first word being the target address and the second being the target 's global pointer . We abuse the concept of a global pointer by arranging for it to point to the data we need to load . The complete trampoline has the following form : + -- -- -- -- -- -- -- -- -- -+ \ TRAMP : | __ia64_trampoline | | + -- -- -- -- -- -- -- -- -- -+ > fake function descriptor | TRAMP+16 | | + -- -- -- -- -- -- -- -- -- -+ / | target descriptor | + -- -- -- -- -- -- -- -- -- -+ | static link | + -- -- -- -- -- -- -- -- -- -+


<s> void setReg ( MCRegister PhysReg ) { Reg . RegNum = PhysReg ; } </s>

Assigns the associated register for this edge .


<s> bool spu_legitimate_constant_p ( machine_mode mode , rtx x ) { subrtx_iterator :: array_type array ; if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , 0 ) ; FOR_EACH_SUBRTX ( iter , array , x , ALL ) if ( ea_symbol_ref_p ( * iter ) ) return 0 ; if ( ! flag_pic && mode == V4SImode && ( GET_CODE ( CONST_VECTOR_ELT ( x , 0 ) ) == SYMBOL_REF || GET_CODE ( CONST_VECTOR_ELT ( x , 0 ) ) == LABEL_REF || GET_CODE ( CONST_VECTOR_ELT ( x , 0 ) ) == CONST ) ) return CONST_VECTOR_ELT ( x , 0 ) == CONST_VECTOR_ELT ( x , 1 ) && CONST_VECTOR_ELT ( x , 1 ) == CONST_VECTOR_ELT ( x , 2 ) && CONST_VECTOR_ELT ( x , 2 ) == CONST_VECTOR_ELT ( x , 3 ) ; if ( GET_CODE ( x ) == CONST_VECTOR && ! const_vector_immediate_p ( x ) ) return 0 ; return 1 ; } </s>

We accept : - any 32-bit constant ( SImode , SFmode ) - any constant that can be generated with fsmbi ( any mode ) - a 64-bit constant where the high and low bits are identical ( DImode , DFmode ) - a 128-bit constant where the four 32-bit words match .


<s> bool doInitialization ( Module & M ) override { if ( ! Triple ( M . getTargetTriple ( ) ) . isOSNaCl ( ) ) SMShadowTracker . reset ( 0 ) ; SM . reset ( ) ; return AsmPrinter :: doInitialization ( M ) ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SI Shrink Instructions"
;
}
</s>


<s> void finish ( ) override { for ( auto * Sym : UpdateOther ) if ( Sym -> isVariable ( ) ) copyLocalEntry ( Sym , Sym -> getVariableValue ( ) ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> int avr_vdump ( FILE * stream , const char * caller , ... ) { va_list ap ; if ( stream == NULL && dump_file ) stream = dump_file ; va_start ( ap , caller ) ; if ( stream ) avr_log_vadump ( stream , caller , ap ) ; va_end ( ap ) ; return 1 ; } </s>

Wrapper for avr_log_vadump . If STREAM is NULL we are called by avr_dump , i.e . output to dump_file if available . The 2nd argument is __FUNCTION__ . The 3rd argument is the format string .


runOnMachineFunction - Emit the function body .


<s> void HexagonCommonGEP :: removeDeadCode ( ) { ValueVect BO ; BO . push_back ( & Fn -> front ( ) ) ; for ( unsigned i = 0 ; i < BO . size ( ) ; ++ i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i ] ) ; for ( auto DTN : children < DomTreeNode * > ( DT -> getNode ( B ) ) ) BO . push_back ( DTN -> getBlock ( ) ) ; } for ( unsigned i = BO . size ( ) ; i > 0 ; -- i ) { BasicBlock * B = cast < BasicBlock > ( BO [ i - 1 ] ) ; BasicBlock :: InstListType & IL = B -> getInstList ( ) ; using reverse_iterator = BasicBlock :: InstListType :: reverse_iterator ; ValueVect Ins ; for ( reverse_iterator I = IL . rbegin ( ) , E = IL . rend ( ) ; I != E ; ++ I ) Ins . push_back ( & * I ) ; for ( ValueVect :: iterator I = Ins . begin ( ) , E = Ins . end ( ) ; I != E ; ++ I ) { Instruction * In = cast < Instruction > ( * I ) ; if ( isInstructionTriviallyDead ( In ) ) In -> eraseFromParent ( ) ; } } } </s>

Remove all dead instructions between the I and E .


<s> static bool nvptx_vpropagate ( bool is_call , basic_block block , rtx_insn * insn ) { return nvptx_propagate ( is_call , block , insn , PM_read_write , vprop_gen , 0 ) ; } </s>

Propagate state that is live at start of BLOCK across the vectors of a single warp . Propagation is inserted just after INSN . IS_CALL and return as for nvptx_propagate .


<s> static machine_mode rx_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { unsigned f ; if ( m1 == m2 ) return m1 ; f = flags_from_mode ( m1 ) | flags_from_mode ( m2 ) ; if ( f & CC_FLAG_FP ) return VOIDmode ; return mode_from_flags ( f ) ; } </s>

Return a CC_MODE of which both M1 and M2 are subsets .


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= 5 && Constraint [ 0 ] == '{' && * ( Constraint . end ( ) - 1 ) == '}' ) { StringRef name ( Constraint . data ( ) + 1 , Constraint . size ( ) - 2 ) ; uint64_t intVal = 0 ; if ( name . substr ( 0 , 1 ) . equals ( "r" ) && ! name . substr ( 1 ) . getAsInteger ( 10 , intVal ) && intVal <= 31 ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / 8 ] ; char regIdx = '0' + ( intVal % 8 ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , 0 } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint , VT ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreservedID ( LiveVariablesID ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> MachineInstr * AArch64InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , int FrameIndex ) const { if ( MI -> isCopy ( ) ) { unsigned DstReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; if ( SrcReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } if ( DstReg == AArch64 :: SP && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & AArch64 :: GPR64RegClass ) ; return nullptr ; } } return nullptr ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> static int mips_adjust_cost ( rtx insn ATTRIBUTE_UNUSED , rtx link , rtx dep ATTRIBUTE_UNUSED , int cost ) { if ( REG_NOTE_KIND ( link ) != 0 ) return 0 ; return cost ; } </s>

Implement TARGET_SCHED_ADJUST_COST . We assume that anti and output dependencies have no cost .


<s> static void s390_end_pool ( struct constant_pool * pool , rtx_insn * insn ) { rtx pool_size = GEN_INT ( pool -> size + 8 ) ; if ( ! insn ) insn = get_last_insn ( ) ; pool -> pool_insn = emit_insn_after ( gen_pool ( pool_size ) , insn ) ; INSN_ADDRESSES_NEW ( pool -> pool_insn , - 1 ) ; } </s>

End range of instructions covered by POOL at INSN and emit placeholder insn representing the pool .


<s> bool Z80oldFrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MF . getInfo < Z80oldMachineFunctionInfo > ( ) -> setCalleeSavedFrameSize ( ( CSI . size ( ) + hasFP ( MF ) ) * SlotSize ) ; return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return 1 ; switch ( rs6000_tune ) { case PROCESSOR_RS64A : case PROCESSOR_PPC601 : case PROCESSOR_PPC7450 : return 3 ; case PROCESSOR_PPC440 : case PROCESSOR_PPC603 : case PROCESSOR_PPC750 : case PROCESSOR_PPC7400 : case PROCESSOR_PPC8540 : case PROCESSOR_PPC8548 : case PROCESSOR_CELL : case PROCESSOR_PPCE300C2 : case PROCESSOR_PPCE300C3 : case PROCESSOR_PPCE500MC : case PROCESSOR_PPCE500MC64 : case PROCESSOR_PPCE5500 : case PROCESSOR_PPCE6500 : case PROCESSOR_TITAN : return 2 ; case PROCESSOR_PPC476 : case PROCESSOR_PPC604 : case PROCESSOR_PPC604e : case PROCESSOR_PPC620 : case PROCESSOR_PPC630 : return 4 ; case PROCESSOR_POWER4 : case PROCESSOR_POWER5 : case PROCESSOR_POWER6 : case PROCESSOR_POWER7 : return 5 ; case PROCESSOR_POWER8 : return 7 ; case PROCESSOR_POWER9 : return 6 ; case PROCESSOR_POWER10 : return 8 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
case
ISD
::
ABS
:
lowerABS
(
N
,
Results
,
DAG
)
;
return
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP
ISD::INTRINSIC_WO_CHAIN
ISD::ABS


<s> TargetPassConfig * TOYTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TOYPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool M68kAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { if ( Count % 2 != 0 ) return false ; uint64_t NumNops = Count / 2 ; for ( uint64_t i = 0 ; i != NumNops ; ++ i ) { OS << "\x4E\x71" ; } return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


Try to a expand constant multiply in SImode by looking it up in a precompiled table . OP0 is the result operand , OP1 is the source operand , and MULTIPLIER is the value of the constant . Return true if it succeeds .


<s> SDValue MSP430TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_MSP430 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> unsigned getMaxSupportedInterleaveFactor ( ) const override { return 4 ; } </s>

Get the maximum supported factor for interleaved memory accesses .


<s> void HexagonShuffler :: append ( MCInst const & ID , MCInst const * Extender , unsigned S ) { HexagonInstr PI ( MCII , STI , & ID , Extender , S ) ; Packet . push_back ( PI ) ; } </s>


<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
AMDGPU
::
OPERAND_SRC_FIRST
||
OperandType
>
AMDGPU
::
OPERAND_SRC_LAST
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
OperandType
)
{
case
AMDGPU
::
OPERAND_REG_IMM_INT32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT64
:
case
AMDGPU
::
OPERAND_REG_IMM_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP64
:
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
case
AMDGPU
::
OPERAND_REG_IMM_INT16
:
case
AMDGPU
::
OPERAND_REG_IMM_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
:
{
if
(
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
if
(
!
(
Imm
&
0xffff
)
)
{
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Imm
>>
16
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
uint32_t
Trunc
=
static_cast
<
uint32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteralV216
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> const TargetRegisterClass * ARMTargetLowering :: getRegClassFor ( MVT VT , bool isDivergent ) const { ( void ) isDivergent ; if ( Subtarget -> hasNEON ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: QQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: QQQQPRRegClass ; } if ( Subtarget -> hasMVEIntegerOps ( ) ) { if ( VT == MVT :: v4i64 ) return & ARM :: MQQPRRegClass ; if ( VT == MVT :: v8i64 ) return & ARM :: MQQQQPRRegClass ; } return TargetLowering :: getRegClassFor ( VT ) ; } </s>

Return the register class that should be used for the specified value type .


<s> bool isPPC64 ( ) const { const Triple & TT = getTargetTriple ( ) ; return ( TT . getArch ( ) == Triple :: ppc64 || TT . getArch ( ) == Triple :: ppc64le ) ; } </s>

Tests whether the target is 64-bit PowerPC ( little and big endian ) .


<s> bool RISCVTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == MVT :: f16 && ! Subtarget . hasStdExtZfh ( ) ) return false ; if ( VT == MVT :: f32 && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == MVT :: f64 && ! Subtarget . hasStdExtD ( ) ) return false ; if ( Imm . isNegZero ( ) ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s> const MCRegister ARMElfTargetObjectFile :: getStaticBase ( ) const { return ARM :: R9 ; } </s>

Returns the register used as static base in RWPI variants .


<s> bool TMS320C64XFrameLowering :: hasFP ( const MachineFunction & MF ) const { return true ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"function_arg_pass_by_reference: V4 IEEE 128-bit\n"

"non-standard ABI extension with no compatibility guarantee"

A C expression that indicates when an argument must be passed by reference . If nonzero for an argument , a copy of that argument is made in memory and a pointer to the argument is passed instead of the argument itself . The pointer is passed in whatever way is appropriate for passing a pointer to that type . Under V.4 , aggregates and long double are passed by reference . As an extension to all 32-bit ABIs , AltiVec vectors are passed by reference unless the AltiVec vector extension ABI is in force . As an extension to all ABIs , variable sized types are passed by reference .


<s> bool Z80oldRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , unsigned BaseReg , int64_t Offset ) const { return isInt < 8 > ( Offset ) ; } </s>

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"AMDGPU Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void sparc64_initialize_trampoline ( rtx m_tramp , rtx fnaddr , rtx cxt ) { emit_move_insn ( adjust_address ( m_tramp , SImode , 0 ) , GEN_INT ( trunc_int_for_mode ( 0x83414000 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 4 ) , GEN_INT ( trunc_int_for_mode ( 0xca586018 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 8 ) , GEN_INT ( trunc_int_for_mode ( 0x81c14000 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , SImode , 12 ) , GEN_INT ( trunc_int_for_mode ( 0xca586010 , SImode ) ) ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , 16 ) , cxt ) ; emit_move_insn ( adjust_address ( m_tramp , DImode , 24 ) , fnaddr ) ; emit_insn ( gen_flush ( DImode , validize_mem ( adjust_address ( m_tramp , DImode , 0 ) ) ) ) ; if ( sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA && sparc_cpu != PROCESSOR_NIAGARA2 && sparc_cpu != PROCESSOR_NIAGARA3 && sparc_cpu != PROCESSOR_NIAGARA4 && sparc_cpu != PROCESSOR_NIAGARA7 && sparc_cpu != PROCESSOR_M8 ) emit_insn ( gen_flush ( DImode , validize_mem ( adjust_address ( m_tramp , DImode , 8 ) ) ) ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__enable_execute_stack" ) , LCT_NORMAL , VOIDmode , XEXP ( m_tramp , 0 ) , Pmode ) ; } </s>

The 64 bit version is simpler because it makes more sense to load the values as `` immediate '' data out of the trampoline . It 's also easier since we can read the PC without clobbering a register .


<s> Value * RISCVTargetLowering :: emitMaskedAtomicCmpXchgIntrinsic ( IRBuilderBase & Builder , AtomicCmpXchgInst * CI , Value * AlignedAddr , Value * CmpVal , Value * NewVal , Value * Mask , AtomicOrdering Ord ) const { assert ( ! RISCVABI :: isCheriPureCapABI ( Subtarget . getTargetABI ( ) ) ) ; unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; Intrinsic :: ID CmpXchgIntrID = Intrinsic :: riscv_masked_cmpxchg_i32 ; if ( XLen == 64 ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = Intrinsic :: riscv_masked_cmpxchg_i64 ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = Intrinsic :: getDeclaration ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ; if ( XLen == 64 ) Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ; return Result ; } </s>

Perform a masked cmpxchg using a target-specific intrinsic .


<s> bool X86FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( MI ) ; if ( MBB . isEHFuncletEntry ( ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Opc = STI . is64Bit ( ) ? X86 :: PUSH64r : X86 :: PUSH32r ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; bool CanKill = ! isLiveIn ; if ( CanKill ) { for ( MCRegAliasIterator AReg ( Reg , TRI , false ) ; AReg . isValid ( ) ; ++ AReg ) { if ( MRI . isLiveIn ( * AReg ) ) { CanKill = false ; break ; } } } BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , getKillRegState ( CanKill ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - 1 ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> void ix86_expand_rounddf_32 ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xa2 , dxa , TWO52 , tmp , half , mhalf , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , 0 , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , 0 , OPTAB_DIRECT ) ; dxa = expand_simple_binop ( mode , MINUS , xa2 , xa , NULL_RTX , 0 , OPTAB_DIRECT ) ; half = force_reg ( mode , const_double_from_real_value ( dconsthalf , mode ) ) ; one = expand_simple_binop ( mode , PLUS , half , half , NULL_RTX , 0 , OPTAB_DIRECT ) ; mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = gen_reg_rtx ( mode ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , one , tmp ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , 0 , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa2 , force_reg ( mode , operand1 ) , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing round from OPERAND1 storing into OPERAND0 . Sequence that works without relying on DImode truncation via cvttsd2siq that is only available on 64bit targets .


<s> int vax_mode_dependent_address_p ( rtx x ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) return 1 ; if ( GET_CODE ( x ) != PLUS ) return 0 ; xfoo0 = XEXP ( x , 0 ) ; xfoo1 = XEXP ( x , 1 ) ; if ( CONSTANT_ADDRESS_P ( xfoo0 ) && GET_CODE ( xfoo1 ) == REG ) return 0 ; if ( CONSTANT_ADDRESS_P ( xfoo1 ) && GET_CODE ( xfoo0 ) == REG ) return 0 ; return 1 ; } </s>

Return 1 if x ( a legitimate address expression ) has an effect that depends on the machine mode it is used for . On the VAX , the predecrement and postincrement address depend thus ( the amount of decrement or increment being the length of the operand ) and all indexed address depend thus ( because the index scale factor is the length of the operand ) .


<s> unsigned MipsAsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> bool isMem ( ) const override { return false ; } </s>


<s> void aarch64_expand_subvti ( rtx op0 , rtx low_dest , rtx low_in1 , rtx low_in2 , rtx high_dest , rtx high_in1 , rtx high_in2 , bool unsigned_p ) { if ( low_in2 == const0_rtx ) { low_dest = low_in1 ; high_in2 = force_reg ( DImode , high_in2 ) ; if ( unsigned_p ) emit_insn ( gen_subdi3_compare1 ( high_dest , high_in1 , high_in2 ) ) ; else emit_insn ( gen_subvdi_insn ( high_dest , high_in1 , high_in2 ) ) ; } else { if ( aarch64_plus_immediate ( low_in2 , DImode ) ) emit_insn ( gen_subdi3_compare1_imm ( low_dest , low_in1 , low_in2 , GEN_INT ( - INTVAL ( low_in2 ) ) ) ) ; else { low_in2 = force_reg ( DImode , low_in2 ) ; emit_insn ( gen_subdi3_compare1 ( low_dest , low_in1 , low_in2 ) ) ; } high_in2 = force_reg ( DImode , high_in2 ) ; if ( unsigned_p ) emit_insn ( gen_usubdi3_carryinC ( high_dest , high_in1 , high_in2 ) ) ; else emit_insn ( gen_subdi3_carryinV ( high_dest , high_in1 , high_in2 ) ) ; } emit_move_insn ( gen_lowpart ( DImode , op0 ) , low_dest ) ; emit_move_insn ( gen_highpart ( DImode , op0 ) , high_dest ) ; } </s>

Generate RTL for 128-bit ( TImode ) subtraction with overflow . OP0 represents the TImode destination operand 0 LOW_DEST represents the low half ( DImode ) of TImode operand 0 LOW_IN1 represents the low half ( DImode ) of TImode operand 1 LOW_IN2 represents the low half ( DImode ) of TImode operand 2 HIGH_DEST represents the high half ( DImode ) of TImode operand 0 HIGH_IN1 represents the high half ( DImode ) of TImode operand 1 HIGH_IN2 represents the high half ( DImode ) of TImode operand 2 UNSIGNED_P is true if the operation is being performed on unsigned values .


<s> static int mips_arg_partial_bytes ( cumulative_args_t cum , const function_arg_info & arg ) { struct mips_arg_info info ; mips_get_arg_info ( & info , get_cumulative_args ( cum ) , arg . mode , arg . type , arg . named ) ; return info . stack_words > 0 ? info . reg_words * UNITS_PER_WORD : 0 ; } </s>


<s> static unsigned int bit_count ( unsigned int x ) { const unsigned int m1 = 0x55555555 ; const unsigned int m2 = 0x33333333 ; const unsigned int m4 = 0x0f0f0f0f ; x -= ( x >> 1 ) & m1 ; x = ( x & m2 ) + ( ( x >> 2 ) & m2 ) ; x = ( x + ( x >> 4 ) ) & m4 ; x += x >> 8 ; return ( x + ( x >> 16 ) ) & 0x3f ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - CHILD |ret | return address -- | | \ | | call saved | | registers | | / -- | | \ | | local | | variables frame pointer - > | | / -- | | \ | | outgoing | Decreasing | | arguments | addresses current stack pointer - > | | / | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V | |


<s> bool umips_load_store_pair_p ( bool load_p , rtx * operands ) { rtx reg1 , reg2 , mem1 , mem2 ; if ( load_p ) { reg1 = operands [ 0 ] ; reg2 = operands [ 2 ] ; mem1 = operands [ 1 ] ; mem2 = operands [ 3 ] ; } else { reg1 = operands [ 1 ] ; reg2 = operands [ 3 ] ; mem1 = operands [ 0 ] ; mem2 = operands [ 2 ] ; } if ( REGNO ( reg2 ) == REGNO ( reg1 ) + 1 ) return umips_load_store_pair_p_1 ( load_p , false , reg1 , mem1 , mem2 ) ; if ( REGNO ( reg1 ) == REGNO ( reg2 ) + 1 ) return umips_load_store_pair_p_1 ( load_p , true , reg2 , mem2 , mem1 ) ; return false ; } </s>

OPERANDS describes the operands to a pair of SETs , in the order dest1 , src1 , dest2 , src2 . Return true if the operands can be used in an LWP or SWP instruction ; LOAD_P says which .


" Declaring this symbol tells the CRT that it should"

"copy all variables from program memory to RAM on startup"

"clear the zeroed data section on startup"

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool AMDGPUMCAsmInfo :: shouldOmitSectionDirective ( StringRef SectionName ) const { return SectionName == ".hsatext" || MCAsmInfo :: shouldOmitSectionDirective ( SectionName ) ; } </s>

Return true if the .section directive should be omitted when emitting SectionName .


<s>
SDValue
SystemZTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_SystemZ
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
SDValue
ResValue
=
OutVals
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
AExt
)
ResValue
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
ResValue
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
ResValue
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
SystemZISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return X86II :: MO_NO_FLAG ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( shouldAssumeDSOLocal ( RM , TargetTriple , M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) return X86II :: MO_DLLIMPORT ; if ( is64Bit ( ) ) return X86II :: MO_GOTPCREL ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s>
void
NVPTXPassConfig
::
addOptimizedRegAlloc
(
FunctionPass
*
RegAllocPass
)
{
assert
(
!
RegAllocPass
&&
"NVPTX uses no regalloc!"
)
;
addPass
(
&
ProcessImplicitDefsID
)
;
addPass
(
&
LiveVariablesID
)
;
addPass
(
&
MachineLoopInfoID
)
;
addPass
(
&
PHIEliminationID
)
;
addPass
(
&
TwoAddressInstructionPassID
)
;
addPass
(
&
RegisterCoalescerID
)
;
if
(
addPass
(
&
MachineSchedulerID
)
)
printAndVerify
(
"After Machine Scheduling"
)
;
addPass
(
&
StackSlotColoringID
)
;
printAndVerify
(
"After StackSlotColoring"
)
;
}
</s>

addOptimizedRegAlloc - Add passes related to register allocation .

NVPTX
NVPTX
"NVPTX uses no regalloc!"
"After Machine Scheduling"
"After StackSlotColoring"


<s> void ARMAsmPrinter :: emitGlobalVariable ( const GlobalVariable * GV ) { if ( PromotedGlobals . count ( GV ) ) return ; AsmPrinter :: emitGlobalVariable ( GV ) ; } </s>

Emit the specified global variable to the .s file .


<s> bool ix86_expand_pinsr ( rtx * operands ) { rtx dst = operands [ 0 ] ; rtx src = operands [ 3 ] ; unsigned int size = INTVAL ( operands [ 1 ] ) ; unsigned int pos = INTVAL ( operands [ 2 ] ) ; if ( SUBREG_P ( dst ) ) { pos += SUBREG_BYTE ( dst ) * BITS_PER_UNIT ; dst = SUBREG_REG ( dst ) ; } switch ( GET_MODE ( dst ) ) { case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : case E_V1TImode : { machine_mode srcmode , dstmode ; rtx ( * pinsr ) ( rtx , rtx , rtx , rtx ) ; rtx d ; if ( ! int_mode_for_size ( size , 0 ) . exists ( & srcmode ) ) return false ; switch ( srcmode ) { case E_QImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V16QImode ; pinsr = gen_sse4_1_pinsrb ; break ; case E_HImode : if ( ! TARGET_SSE2 ) return false ; dstmode = V8HImode ; pinsr = gen_sse2_pinsrw ; break ; case E_SImode : if ( ! TARGET_SSE4_1 ) return false ; dstmode = V4SImode ; pinsr = gen_sse4_1_pinsrd ; break ; case E_DImode : gcc_assert ( TARGET_64BIT ) ; if ( ! TARGET_SSE4_1 ) return false ; dstmode = V2DImode ; pinsr = gen_sse4_1_pinsrq ; break ; default : return false ; } if ( pos & ( size - 1 ) ) return false ; if ( SUBREG_P ( src ) ) { unsigned int srcpos = SUBREG_BYTE ( src ) ; if ( srcpos > 0 ) { rtx extr_ops [ 4 ] ; extr_ops [ 0 ] = gen_reg_rtx ( srcmode ) ; extr_ops [ 1 ] = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; extr_ops [ 2 ] = GEN_INT ( size ) ; extr_ops [ 3 ] = GEN_INT ( srcpos * BITS_PER_UNIT ) ; if ( ! ix86_expand_pextr ( extr_ops ) ) return false ; src = extr_ops [ 0 ] ; } else src = gen_lowpart ( srcmode , SUBREG_REG ( src ) ) ; } if ( GET_MODE ( dst ) == dstmode ) d = dst ; else d = gen_reg_rtx ( dstmode ) ; emit_insn ( pinsr ( d , gen_lowpart ( dstmode , dst ) , gen_lowpart ( srcmode , src ) , GEN_INT ( 1 << ( pos / size ) ) ) ) ; if ( d != dst ) emit_move_insn ( dst , gen_lowpart ( GET_MODE ( dst ) , d ) ) ; return true ; } default : return false ; } } </s>

Expand an insert into a vector register through pinsr insn . Return true if successful .


<s>
void
HexagonFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
prior
(
MBB
.
end
(
)
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
if
(
hasFP
(
MF
)
||
MF
.
getTarget
(
)
.
getOptLevel
(
)
==
CodeGenOpt
::
)
{
MachineBasicBlock
::
iterator
MBBI
=
prior
(
MBB
.
end
(
)
)
;
MachineBasicBlock
::
iterator
MBBI_end
=
MBB
.
end
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
if
(
MBBI
->
getOpcode
(
)
==
Hexagon
::
EH_RETURN_JMPR
)
{
assert
(
MBBI
->
getOperand
(
0
)
.
isReg
(
)
&&
"Offset should be in register!"
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
DEALLOCFRAME
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
ADD_rr
)
,
Hexagon
::
R29
)
.
addReg
(
Hexagon
::
R29
)
.
addReg
(
Hexagon
::
R28
)
;
return
;
}
if
(
STI
.
hasV4TOps
(
)
&&
MBBI
->
getOpcode
(
)
==
Hexagon
::
JMPret
&&
!
DisableDeallocRet
)
{
MachineBasicBlock
::
iterator
BeforeJMPR
=
MBB
.
begin
(
)
==
MBBI
MBBI
:
prior
(
MBBI
)
;
if
(
BeforeJMPR
!=
MBBI
&&
BeforeJMPR
->
getOpcode
(
)
==
Hexagon
::
RESTORE_DEALLOC_RET_JMP_V4
)
{
MBB
.
erase
(
MBBI
)
;
return
;
}
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI_end
,
dl
,
TII
.
get
(
Hexagon
::
DEALLOC_RET_V4
)
)
;
MIB
->
copyImplicitOps
(
*
MBB
.
getParent
(
)
,
&
*
MBBI
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
MachineBasicBlock
::
iterator
Term
=
MBB
.
getFirstTerminator
(
)
;
MachineBasicBlock
::
iterator
I
=
Term
==
MBB
.
begin
(
)
MBB
.
end
(
)
:
prior
(
Term
)
;
if
(
I
!=
MBB
.
end
(
)
&&
I
->
getOpcode
(
)
==
Hexagon
::
RESTORE_DEALLOC_BEFORE_TAILCALL_V4
)
return
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
DEALLOCFRAME
)
)
;
}
}
}
</s>


"data-model=far not valid for cr16c architecture"

"invalid data model option -mdata-model=%s"


<s> bool DirectXTargetMachine :: addPassesToEmitMC ( PassManagerBase & PM , MCContext * & Ctx , raw_pwrite_stream & Out , bool DisableVerify ) { return true ; } </s>

Add passes to the specified pass manager to get machine code emitted with the MCJIT .


<s> bool MipsTargetMachine :: addInstSelector ( PassManagerBase & PM ) { PM . add ( createMipsISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool X86TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! X86 :: isOffsetSuitableForCodeModel ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget . classifyGlobalReference ( AM . BaseGV ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > 1 ) ) return false ; } switch ( AM . Scale ) { case 0 : case 1 : case 2 : case 4 : case 8 : break ; case 3 : case 5 : case 9 : if ( AM . HasBaseReg ) return false ; break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> static void ix86_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT bytes , words ; int nregs ; if ( ! cum -> caller && cfun -> machine -> func_type != TYPE_NORMAL ) return ; if ( mode == BLKmode ) bytes = int_size_in_bytes ( type ) ; else bytes = GET_MODE_SIZE ( mode ) ; words = CEIL ( bytes , UNITS_PER_WORD ) ; if ( type ) mode = type_natural_mode ( type , NULL , false ) ; if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( ! nregs ) { if ( cum -> caller ) cfun -> machine -> outgoing_args_on_stack = true ; } } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> std :: pair < unsigned , const TargetRegisterClass * > SITargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 's' : case 'r' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( 0U , nullptr ) ; case 32 : return std :: make_pair ( 0U , & AMDGPU :: SGPR_32RegClass ) ; case 64 : return std :: make_pair ( 0U , & AMDGPU :: SGPR_64RegClass ) ; case 128 : return std :: make_pair ( 0U , & AMDGPU :: SReg_128RegClass ) ; case 256 : return std :: make_pair ( 0U , & AMDGPU :: SReg_256RegClass ) ; } case 'v' : switch ( VT . getSizeInBits ( ) ) { default : return std :: make_pair ( 0U , nullptr ) ; case 32 : return std :: make_pair ( 0U , & AMDGPU :: VGPR_32RegClass ) ; case 64 : return std :: make_pair ( 0U , & AMDGPU :: VReg_64RegClass ) ; case 96 : return std :: make_pair ( 0U , & AMDGPU :: VReg_96RegClass ) ; case 128 : return std :: make_pair ( 0U , & AMDGPU :: VReg_128RegClass ) ; case 256 : return std :: make_pair ( 0U , & AMDGPU :: VReg_256RegClass ) ; case 512 : return std :: make_pair ( 0U , & AMDGPU :: VReg_512RegClass ) ; } } } if ( Constraint . size ( ) > 1 ) { const TargetRegisterClass * RC = nullptr ; if ( Constraint [ 1 ] == 'v' ) { RC = & AMDGPU :: VGPR_32RegClass ; } else if ( Constraint [ 1 ] == 's' ) { RC = & AMDGPU :: SGPR_32RegClass ; } if ( RC ) { uint32_t Idx ; bool Failed = Constraint . substr ( 2 ) . getAsInteger ( 10 , Idx ) ; if ( ! Failed && Idx < RC -> getNumRegs ( ) ) return std :: make_pair ( RC -> getRegister ( Idx ) , RC ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> static rtx avr_default_expand_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat , xop [ 3 ] ; int n_args = call_expr_nargs ( exp ) ; machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; gcc_assert ( n_args >= 1 && n_args <= 3 ) ; if ( target == NULL_RTX || GET_MODE ( target ) != tmode || ! insn_data [ icode ] . operand [ 0 ] . predicate ( target , tmode ) ) { target = gen_reg_rtx ( tmode ) ; } for ( int n = 0 ; n < n_args ; n ++ ) { tree arg = CALL_EXPR_ARG ( exp , n ) ; rtx op = expand_expr ( arg , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; machine_mode opmode = GET_MODE ( op ) ; machine_mode mode = insn_data [ icode ] . operand [ n + 1 ] . mode ; if ( ( opmode == SImode || opmode == VOIDmode ) && mode == HImode ) { opmode = HImode ; op = gen_lowpart ( HImode , op ) ; } gcc_assert ( opmode == mode || opmode == VOIDmode ) ; if ( ! insn_data [ icode ] . operand [ n + 1 ] . predicate ( op , mode ) ) op = copy_to_mode_reg ( mode , op ) ; xop [ n ] = op ; } switch ( n_args ) { case 1 : pat = GEN_FCN ( icode ) ( target , xop [ 0 ] ) ; break ; case 2 : pat = GEN_FCN ( icode ) ( target , xop [ 0 ] , xop [ 1 ] ) ; break ; case 3 : pat = GEN_FCN ( icode ) ( target , xop [ 0 ] , xop [ 1 ] , xop [ 2 ] ) ; break ; default : gcc_unreachable ( ) ; } if ( pat == NULL_RTX ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of avr_expand_builtin to expand vanilla builtins with non-void result and 1 ... 3 arguments .


<s> bool SPUPassConfig :: addInstSelector ( ) { addPass ( createSPUISelDag ( getSPUTargetMachine ( ) ) ) ; return false ; } </s>


<s> TargetPassConfig * GCNTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new GCNPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
MipsSubtarget
::
MipsSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
little
)
:
MipsGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
MipsArchVersion
(
Mips32
)
,
MipsABI
(
UnknownABI
)
,
IsLittle
(
little
)
,
IsSingleFloat
(
false
)
,
IsFP64bit
(
false
)
,
IsGP64bit
(
false
)
,
HasVFPU
(
false
)
,
IsLinux
(
true
)
,
HasSEInReg
(
false
)
,
HasCondMov
(
false
)
,
HasMulDivAdd
(
false
)
,
HasMinMax
(
false
)
,
HasSwap
(
false
)
,
HasBitCount
(
false
)
{
std
::
string
CPUName
=
CPU
;
if
(
CPUName
.
empty
(
)
)
CPUName
=
"mips32"
;
ParseSubtargetFeatures
(
CPUName
,
FS
)
;
InstrItins
=
getInstrItineraryForCPU
(
CPUName
)
;
if
(
MipsABI
==
UnknownABI
)
MipsABI
=
hasMips64
(
)
N64
:
O32
;
assert
(
(
(
!
hasMips64
(
)
&&
(
isABI_O32
(
)
||
isABI_EABI
(
)
)
)
||
(
hasMips64
(
)
&&
(
isABI_N32
(
)
||
isABI_N64
(
)
)
)
)
&&
"Invalid  Arch & ABI pair."
)
;
if
(
TT
.
find
(
"linux"
)
==
std
::
string
::
npos
)
IsLinux
=
false
;
}
</s>

This constructor initializes the data members to match that of the specified triple .

Mips
Mips
Mips
Mips
Mips
Mips
Mips
"mips32"
Mips
Mips
Mips
Mips
Mips
"Invalid  Arch & ABI pair."
"linux"