<s> static machine_mode pa_c_mode_for_suffix ( char suffix ) { if ( HPUX_LONG_DOUBLE_LIBRARY ) { if ( suffix == 'q' ) return TFmode ; } return VOIDmode ; } </s>


<s> bool ARMTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; const bool restrict_addressing_modes_for_nacl = Subtarget -> isTargetNaCl ( ) && ( N -> getOpcode ( ) == ISD :: LOAD || N -> getOpcode ( ) == ISD :: STORE ) ; if ( restrict_addressing_modes_for_nacl ) { return false ; } EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == ISD :: SEXTLOAD ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = getARMIndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; AM = isInc ? ISD :: PRE_INC : ISD :: PRE_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .

ARM ARM ISD::MemIndexedMode ISD::LOAD ISD::STORE ISD::SEXTLOAD ARM ISD::PRE_INC ISD::PRE_DEC


"Byval argument's alignment should be a multiple of"

Target-specific cleanup for formal ByVal parameters .


<s> bool HexagonTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { return true ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


"  Adding insn %d into chain's #%d queue\n"


<s>
void
XtensaAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
Value
=
adjustFixupValue
(
Fixup
,
Value
,
&
Asm
.
getContext
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
uint32_t
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void X86DAGToDAGISel :: PostprocessISelDAG ( ) { if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) return ; SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; ++ Position ; while ( Position != CurDAG -> allnodes_begin ( ) ) { SDNode * N = & * -- Position ; if ( N -> use_empty ( ) || ! N -> isMachineOpcode ( ) ) continue ; if ( N -> getMachineOpcode ( ) != TargetOpcode :: SUBREG_TO_REG ) continue ; unsigned SubRegIdx = N -> getConstantOperandVal ( 2 ) ; if ( SubRegIdx != X86 :: sub_xmm && SubRegIdx != X86 :: sub_ymm ) continue ; SDValue Move = N -> getOperand ( 1 ) ; if ( ! Move . isMachineOpcode ( ) ) continue ; switch ( Move . getMachineOpcode ( ) ) { default : continue ; case X86 :: VMOVAPDrr : case X86 :: VMOVUPDrr : case X86 :: VMOVAPSrr : case X86 :: VMOVUPSrr : case X86 :: VMOVDQArr : case X86 :: VMOVDQUrr : case X86 :: VMOVAPDYrr : case X86 :: VMOVUPDYrr : case X86 :: VMOVAPSYrr : case X86 :: VMOVUPSYrr : case X86 :: VMOVDQAYrr : case X86 :: VMOVDQUYrr : case X86 :: VMOVAPDZ128rr : case X86 :: VMOVUPDZ128rr : case X86 :: VMOVAPSZ128rr : case X86 :: VMOVUPSZ128rr : case X86 :: VMOVDQA32Z128rr : case X86 :: VMOVDQU32Z128rr : case X86 :: VMOVDQA64Z128rr : case X86 :: VMOVDQU64Z128rr : case X86 :: VMOVAPDZ256rr : case X86 :: VMOVUPDZ256rr : case X86 :: VMOVAPSZ256rr : case X86 :: VMOVUPSZ256rr : case X86 :: VMOVDQA32Z256rr : case X86 :: VMOVDQU32Z256rr : case X86 :: VMOVDQA64Z256rr : case X86 :: VMOVDQU64Z256rr : break ; } SDValue In = Move . getOperand ( 0 ) ; if ( ! In . isMachineOpcode ( ) || In . getMachineOpcode ( ) <= TargetOpcode :: GENERIC_OP_END ) continue ; uint64_t TSFlags = getInstrInfo ( ) -> get ( In . getMachineOpcode ( ) ) . TSFlags ; if ( ( TSFlags & X86II :: EncodingMask ) != X86II :: VEX && ( TSFlags & X86II :: EncodingMask ) != X86II :: EVEX && ( TSFlags & X86II :: EncodingMask ) != X86II :: XOP ) continue ; CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , In , N -> getOperand ( 2 ) ) ; if ( Move . getNode ( ) -> use_empty ( ) ) CurDAG -> RemoveDeadNode ( Move . getNode ( ) ) ; } } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> MachineInstr * X86InstrInfo :: optimizeLoadInstr ( MachineInstr * MI , const MachineRegisterInfo * MRI , unsigned & FoldAsLoadDefReg , MachineInstr * & DefMI ) const { if ( FoldAsLoadDefReg == 0 ) return nullptr ; if ( MI -> mayLoad ( ) ) { FoldAsLoadDefReg = 0 ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = 0 ; bool FoundSrcOperand = false ; for ( unsigned i = 0 , e = MI -> getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return nullptr ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return nullptr ; MachineInstr * FoldMI = foldMemoryOperand ( MI , SrcOperandId , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = 0 ; return FoldMI ; } return nullptr ; } </s>

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use .


<s> static int fp_regs_to_save ( void ) { int i , n = 0 ; if ( ! TARGET_AM33_2 ) return 0 ; for ( i = FIRST_FP_REGNUM ; i <= LAST_FP_REGNUM ; ++ i ) if ( regs_ever_live [ i ] && ! call_used_regs [ i ] ) ++ n ; return n ; } </s>

Count the number of FP registers that have to be saved .


<s> bool arc_is_longcall_p ( rtx sym_ref ) { if ( GET_CODE ( sym_ref ) != SYMBOL_REF ) return false ; return ( SYMBOL_REF_LONG_CALL_P ( sym_ref ) || ( TARGET_LONG_CALLS_SET && ! SYMBOL_REF_SHORT_CALL_P ( sym_ref ) && ! SYMBOL_REF_MEDIUM_CALL_P ( sym_ref ) ) ) ; } </s>

Return true if a 32 bit `` long_call '' should be generated for this calling SYM_REF . We generate a long_call if the function : a. has an __attribute__ ( ( long call ) ) or b. the -mlong-calls command line switch has been specified However we do not generate a long call if the function has an __attribute__ ( ( short_call ) ) or __attribute__ ( ( medium_call ) ) This function will be called by C fragments contained in the machine description file .


<s> bool RISCVTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { auto & DL = I . getModule ( ) -> getDataLayout ( ) ; switch ( Intrinsic ) { default : return false ; case Intrinsic :: riscv_masked_atomicrmw_xchg_i32 : case Intrinsic :: riscv_masked_atomicrmw_add_i32 : case Intrinsic :: riscv_masked_atomicrmw_sub_i32 : case Intrinsic :: riscv_masked_atomicrmw_nand_i32 : case Intrinsic :: riscv_masked_atomicrmw_max_i32 : case Intrinsic :: riscv_masked_atomicrmw_min_i32 : case Intrinsic :: riscv_masked_atomicrmw_umax_i32 : case Intrinsic :: riscv_masked_atomicrmw_umin_i32 : case Intrinsic :: riscv_masked_cmpxchg_i32 : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 4 ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case Intrinsic :: riscv_masked_strided_load : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / 8 ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case Intrinsic :: riscv_masked_strided_store : Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . memVT = getValueType ( DL , I . getArgOperand ( 0 ) -> getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getArgOperand ( 0 ) -> getType ( ) -> getScalarType ( ) ) / 8 ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOStore ; return true ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> static bool ia64_struct_retval_addr_is_first_parm_p ( tree fntype ) { tree ret_type = TREE_TYPE ( fntype ) ; return ( abi_version_at_least ( 2 ) && ret_type && TYPE_MODE ( ret_type ) == BLKmode && TREE_ADDRESSABLE ( ret_type ) && lang_GNU_CXX ( ) ) ; } </s>

Returns true if FNTYPE ( a FUNCTION_TYPE or a METHOD_TYPE ) returns a structure type and that the address of that type should be passed in out0 , rather than in r8 .


<s> unsigned MBlazeIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { if ( Len < 5 || Name [ 4 ] != '.' || Name [ 0 ] != 'l' || Name [ 1 ] != 'l' || Name [ 2 ] != 'v' || Name [ 3 ] != 'm' ) return 0 ; return 0 ; } </s>


<s> bool WebAssemblyPassConfig :: addPreISel ( ) { return false ; } </s>


"insertBranch must not be told to insert a fallthrough"

"ARM branch conditions have two components!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> bool PPCTargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; case MVT :: f128 : return ( EnableQuadPrecision && Subtarget . hasP9Vector ( ) ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> static void build_sv_offset ( function_builder & b , const char * signature , const function_group_info & group ) { build_32_64 ( b , signature , group , MODE_s32offset , MODE_s64offset ) ; build_32_64 ( b , signature , group , MODE_u32offset , MODE_u64offset ) ; } </s>

Like build_sv_index , but taking vector byte offsets instead of vector array indices .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; MVT RegisterVT ; unsigned NumRegisters ; std :: tie ( RegisterVT , NumRegisters ) = handleMaskRegisterForCallingConv ( NumElts , CC , Subtarget ) ; if ( RegisterVT != MVT :: INVALID_SIMPLE_VALUE_TYPE ) return NumRegisters ; } if ( VT == MVT :: v3f16 && Subtarget . hasFP16 ( ) ) return 1 ; if ( ! Subtarget . is64Bit ( ) && ! Subtarget . hasX87 ( ) ) { if ( VT == MVT :: f64 ) return 2 ; if ( VT == MVT :: f80 ) return 3 ; } return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> bool isReg ( ) const { return Kind == k_Register ; } </s>


<s> void clear ( ) { Map . clear ( ) ; } </s>


<s> unsigned getSize ( ) const { return size ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } </s>


"preferPredicateOverEpilogue: not a single block "

"preferPredicateOverEpilogue: hardware-loop is not "

Query the target whether it would be prefered to create a predicated vector loop , which can avoid the need to emit a scalar epilogue loop .


<s> virtual SMLoc getStartLoc ( ) const LLVM_OVERRIDE { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> int avr_function_arg_regno_p ( int r ) { return ( AVR_TINY ? r >= 20 && r <= 25 : r >= 8 && r <= 25 ) ; } </s>

Returns nonzero if REGNO is the number of a hard register in which function arguments are sometimes passed .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> static bool valid_bL_string_p ( const char * * core , const char * bL_string ) { return strstr ( bL_string , core [ 0 ] ) != NULL && strstr ( bL_string , core [ 1 ] ) != NULL ; } </s>

Check wether the string CORE contains the same CPU part numbers as BL_STRING . For example CORE= '' { 0xd03 , 0xd07 } '' and BL_STRING= '' 0xd07.0xd03 '' should return true .


<s> static void riscv_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size ATTRIBUTE_UNUSED , int no_rtl ) { CUMULATIVE_ARGS local_cum ; int gp_saved ; local_cum = * get_cumulative_args ( cum ) ; riscv_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > 0 ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == 0 ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ; } </s>


<s> MachineInstrBuilder SIInstrInfo :: buildIndirectRead ( MachineBasicBlock * MBB , MachineBasicBlock :: iterator I , unsigned ValueReg , unsigned Address , unsigned OffsetReg ) const { const DebugLoc & DL = MBB -> findDebugLoc ( I ) ; unsigned IndirectBaseReg = AMDGPU :: VGPR_32RegClass . getRegister ( getIndirectIndexBegin ( * MBB -> getParent ( ) ) ) ; return BuildMI ( * MBB , I , DL , get ( AMDGPU :: SI_INDIRECT_SRC_V1 ) ) . addOperand ( I -> getOperand ( 0 ) ) . addOperand ( I -> getOperand ( 1 ) ) . addReg ( IndirectBaseReg ) . addReg ( OffsetReg ) . addImm ( 0 ) ; } </s>

Build instruction ( s ) for an indirect register read .


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { return createVLIWMachineSched ( C ) ; } </s>

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level .


<s> static bool tilegx_emit_fp_setcc ( rtx res , enum rtx_code code , machine_mode mode , rtx op0 , rtx op1 ) { rtx flags ; int flag_index ; rtx a = force_reg ( DImode , gen_lowpart ( DImode , op0 ) ) ; rtx b = force_reg ( DImode , gen_lowpart ( DImode , op1 ) ) ; flags = gen_reg_rtx ( DImode ) ; if ( mode == SFmode ) { emit_insn ( gen_insn_fsingle_add1 ( flags , a , b ) ) ; } else { gcc_assert ( mode == DFmode ) ; emit_insn ( gen_insn_fdouble_add_flags ( flags , a , b ) ) ; } switch ( code ) { case EQ : flag_index = 30 ; break ; case NE : flag_index = 31 ; break ; case LE : flag_index = 27 ; break ; case LT : flag_index = 26 ; break ; case GE : flag_index = 29 ; break ; case GT : flag_index = 28 ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( GET_MODE ( res ) == DImode ) ; emit_move_insn ( res , gen_rtx_ZERO_EXTRACT ( DImode , flags , GEN_INT ( 1 ) , GEN_INT ( flag_index ) ) ) ; return true ; } </s>

Produce the rtx yielding a bool for a floating point comparison .


<s> bool Mips16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> const MCSection * TMS320C64XTargetObjectFileELF :: getSectionForConstant ( SectionKind Kind ) const { assert ( Kind . isReadOnly ( ) ) ; return getDataSection ( ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> void msp430_output_labelref ( FILE * file , const char * name ) { int i ; for ( i = 0 ; helper_function_name_mappings [ i ] . gcc_name ; i ++ ) if ( strcmp ( helper_function_name_mappings [ i ] . gcc_name , name ) == 0 ) { name = helper_function_name_mappings [ i ] . ti_name ; break ; } if ( msp430_hwmult_type != MSP430_HWMULT_NONE ) { if ( strcmp ( "__mspabi_mpyi" , name ) == 0 ) { if ( msp430_use_f5_series_hwmult ( ) ) name = "__mulhi2_f5" ; else if ( ! msp430_no_hwmult ( ) ) name = "__mulhi2" ; } else if ( strcmp ( "__mspabi_mpyl" , name ) == 0 ) { if ( msp430_use_f5_series_hwmult ( ) ) name = "__mulsi2_f5" ; else if ( use_32bit_hwmult ( ) ) name = "__mulsi2_hw32" ; else if ( ! msp430_no_hwmult ( ) ) name = "__mulsi2" ; } } if ( user_label_prefix [ 0 ] != 0 ) fputs ( user_label_prefix , file ) ; fputs ( name , file ) ; } </s>

This function does the same as the default , but it will replace GCC function names with the MSPABI-specified ones .


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static void epiphany_init ( void ) { pass_mode_switch_use = make_pass_mode_switch_use ( g ) ; struct register_pass_info insert_use_info = { pass_mode_switch_use , "mode_sw" , 1 , PASS_POS_INSERT_AFTER } ; opt_pass * mode_sw2 = g -> get_passes ( ) -> get_pass_mode_switching ( ) -> clone ( ) ; struct register_pass_info mode_sw2_info = { mode_sw2 , "mode_sw" , 1 , PASS_POS_INSERT_AFTER } ; opt_pass * mode_sw3 = make_pass_resolve_sw_modes ( g ) ; struct register_pass_info mode_sw3_info = { mode_sw3 , "mode_sw" , 1 , PASS_POS_INSERT_AFTER } ; opt_pass * mode_sw4 = g -> get_passes ( ) -> get_pass_split_all_insns ( ) -> clone ( ) ; struct register_pass_info mode_sw4_info = { mode_sw4 , "mode_sw" , 1 , PASS_POS_INSERT_AFTER } ; static const int num_modes [ ] = NUM_MODES_FOR_MODE_SWITCHING ; epiphany_init_reg_tables ( ) ; memset ( epiphany_punct_chars , 0 , sizeof ( epiphany_punct_chars ) ) ; epiphany_punct_chars [ '-' ] = 1 ; epiphany_normal_fp_rounding = ( epiphany_normal_fp_mode == FP_MODE_ROUND_TRUNC ? FP_MODE_ROUND_TRUNC : FP_MODE_ROUND_NEAREST ) ; register_pass ( & mode_sw4_info ) ; register_pass ( & mode_sw2_info ) ; register_pass ( & mode_sw3_info ) ; register_pass ( & insert_use_info ) ; register_pass ( & mode_sw2_info ) ; gcc_assert ( N_ENTITIES == EPIPHANY_MSW_ENTITY_NUM ) ; { opt_pass * extra_peephole2 = g -> get_passes ( ) -> get_pass_peephole2 ( ) -> clone ( ) ; struct register_pass_info peep2_2_info = { extra_peephole2 , "peephole2" , 1 , PASS_POS_INSERT_AFTER } ; register_pass ( & peep2_2_info ) ; } } </s>

Called from epiphany_override_options . We use this to initialize various things .


<s> static bool s390_cannot_force_const_mem ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : case CONST_WIDE_INT : case CONST_VECTOR : return false ; case LABEL_REF : return flag_pic != 0 ; case SYMBOL_REF : if ( tls_symbolic_operand ( x ) ) return true ; else return flag_pic != 0 ; case CONST : return s390_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) ; case PLUS : case MINUS : return s390_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) || s390_cannot_force_const_mem ( mode , XEXP ( x , 1 ) ) ; case UNSPEC : switch ( XINT ( x , 1 ) ) { case UNSPEC_LTREL_OFFSET : case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : case UNSPEC_TLSGD : case UNSPEC_TLSLDM : case UNSPEC_NTPOFF : case UNSPEC_DTPOFF : case UNSPEC_GOTNTPOFF : case UNSPEC_INDNTPOFF : return false ; case UNSPEC_INSN : return TARGET_CPU_ZARCH ; default : return true ; } break ; default : gcc_unreachable ( ) ; } } </s>

Determine if it 's legal to put X into the constant pool . This is not possible if X contains the address of a symbol that is not constant ( TLS ) or not known at final link time ( PIC ) .


<s> int64_t getOffset ( ) const { return Offset ; } </s>

Get the offest of a string in the string table .


<s> static void AnalyzeArguments ( CCState & State , SmallVectorImpl < CCValAssign > & ArgLocs , const SmallVectorImpl < ArgT > & Args ) { static const MCPhysReg RegList [ ] = { FISC :: X10 , FISC :: X11 , FISC :: X12 , FISC :: X13 , FISC :: X14 , FISC :: X15 , FISC :: X26 , FISC :: X27 , FISC :: X18 } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; SmallVector < unsigned , 4 > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; if ( State . isVarArg ( ) ) { unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; for ( unsigned j = 0 ; j < ArgsParts [ i ] ; j ++ ) { if ( i == 0 && j == 0 ) State . addLoc ( CCValAssign :: getCustomMem ( ValNo ++ , ArgVT , State . AllocateStack ( 8 , 8 ) , LocVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getCustomMem ( ValNo ++ , ArgVT , State . AllocateStack ( 8 , 8 ) , LocVT , LocInfo ) ) ; } } return ; } unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; ISD :: ArgFlagsTy ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 8 , 8 , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <= RegsLeft ) { unsigned FirstVal = ValNo ; for ( unsigned j = 0 ; j < Parts ; j ++ ) { unsigned Reg = State . AllocateReg ( RegList ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -- ; } SmallVectorImpl < CCValAssign > :: iterator B = ArgLocs . begin ( ) + FirstVal ; std :: reverse ( B , B + Parts ) ; } else { UseStack = true ; for ( unsigned j = 0 ; j < Parts ; j ++ ) CC_FISC ( ValNo ++ , ArgVT , LocVT , LocInfo , ArgFlags , State ) ; } } } </s>

The function will invoke AnalyzeCallOperands .


<s> int getIORegRAMPZ ( void ) const { return 0x3b ; } </s>


<s> bool HexagonInstrInfo :: getBaseAndOffsetPosition ( const MachineInstr & MI , unsigned & BasePos , unsigned & OffsetPos ) const { if ( ! isAddrModeWithOffset ( MI ) && ! isPostIncrement ( MI ) ) return false ; if ( isMemOp ( MI ) ) { BasePos = 0 ; OffsetPos = 1 ; } else if ( MI . mayStore ( ) ) { BasePos = 0 ; OffsetPos = 1 ; } else if ( MI . mayLoad ( ) ) { BasePos = 1 ; OffsetPos = 2 ; } else return false ; if ( isPredicated ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( isPostIncrement ( MI ) ) { BasePos ++ ; OffsetPos ++ ; } if ( ! MI . getOperand ( BasePos ) . isReg ( ) || ! MI . getOperand ( OffsetPos ) . isImm ( ) ) return false ; return true ; } </s>

Return true if the instruction contains a base register and offset .


<s> void sparc_flat_expand_prologue ( void ) { HOST_WIDE_INT size ; rtx_insn * insn ; sparc_leaf_function_p = optimize > 0 && crtl -> is_leaf ; size = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size - STACK_CHECK_PROTECT ) ; } else if ( size > 0 ) sparc_emit_probe_stack_range ( STACK_CHECK_PROTECT , size ) ; } if ( sparc_save_local_in_regs_p ) emit_save_or_restore_local_in_regs ( stack_pointer_rtx , SPARC_STACK_BIAS , SORR_SAVE ) ; if ( size == 0 ) ; else { rtx size_int_rtx , size_rtx ; size_rtx = size_int_rtx = GEN_INT ( - size ) ; if ( size <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= 8192 && ! frame_pointer_needed ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - size ) ) ) ; } else { size_rtx = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) { insn = emit_insn ( gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , size_rtx ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , size ) ) ) ; } if ( return_addr_reg_needed_p ( sparc_leaf_function_p ) ) { rtx o7 = gen_rtx_REG ( Pmode , INCOMING_RETURN_ADDR_REGNUM ) ; rtx i7 = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; insn = emit_move_insn ( i7 , o7 ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_REGISTER , gen_rtx_SET ( VOIDmode , i7 , o7 ) ) ; emit_use ( i7 ) ; } } if ( frame_pointer_needed ) { sparc_frame_base_reg = hard_frame_pointer_rtx ; sparc_frame_base_offset = SPARC_STACK_BIAS ; } else { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } if ( sparc_n_global_fp_regs > 0 ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_SAVE ) ; if ( crtl -> uses_pic_offset_table ) load_got_register ( ) ; sparc_prologue_data_valid_p = true ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the GOT register if needed .


<s> void X86InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . needsStackRealignment ( MF ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , TM ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> void XCoreAsmPrinter :: emitFunctionBodyStart ( ) { MCInstLowering . Initialize ( & MF -> getContext ( ) ) ; } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> int cris_legitimate_pic_operand ( rtx x ) { return cris_valid_pic_const ( x ) ; } </s>


<s> Optional < DestSourcePair > X86InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; return None ; } </s>

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands .


Return true iff x is a uniform vector of floating-point constants , and the constant can be represented in quarter-precision form . Note , as aarch64_float_const_representable rejects both +0.0 and -0.0 , we will also reject +0.0 and -0.0 .


<s> bool PPCSubtarget :: isPPC64 ( ) const { return TM . isPPC64 ( ) ; } </s>

Tests whether the target is 64-bit PowerPC ( little and big endian ) .


<s> const MCSection * getSectionForConstant ( SectionKind Kind , const Constant * C ) const override { return ReadOnlySection ; } </s>


<s> void PPCTargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const { if ( Subtarget . isDarwinABI ( ) ) return ; if ( ! Subtarget . isPPC64 ( ) ) return ; PPCFunctionInfo * PFI = Entry -> getParent ( ) -> getInfo < PPCFunctionInfo > ( ) ; PFI -> setIsSplitCSR ( true ) ; } </s>

Perform necessary initialization to handle a subset of CSRs explicitly via copies .


<s>
void
PPCTargetLowering
::
LowerAsmOperandForConstraint
(
SDValue
Op
,
std
::
string
&
Constraint
,
std
::
vector
<
SDValue
>
&
Ops
,
SelectionDAG
&
DAG
)
const
{
SDValue
Result
;
if
(
Constraint
.
length
(
)
>
1
)
return
;
char
Letter
=
Constraint
[
0
]
;
switch
(
Letter
)
{
default
:
break
;
case
'I'
:
case
'J'
:
case
'K'
:
case
'L'
:
case
'M'
:
case
'N'
:
case
'O'
:
case
'P'
:
{
ConstantSDNode
*
CST
=
dyn_cast
<
ConstantSDNode
>
(
Op
)
;
if
(
!
CST
)
return
;
SDLoc
dl
(
Op
)
;
int64_t
Value
=
CST
->
getSExtValue
(
)
;
EVT
TCVT
=
MVT
::
i64
;
switch
(
Letter
)
{
default
:
llvm_unreachable
(
"Unknown constraint letter!"
)
;
case
'I'
:
if
(
isInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'J'
:
if
(
isShiftedUInt
<
16
,
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'L'
:
if
(
isShiftedInt
<
16
,
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'K'
:
if
(
isUInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'M'
:
if
(
Value
>
31
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'N'
:
if
(
Value
>
0
&&
isPowerOf2_64
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'O'
:
if
(
Value
==
0
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
case
'P'
:
if
(
isInt
<
16
>
(
Value
)
)
Result
=
DAG
.
getTargetConstant
(
Value
,
dl
,
TCVT
)
;
break
;
}
break
;
}
}
if
(
Result
.
getNode
(
)
)
{
Ops
.
push_back
(
Result
)
;
return
;
}
TargetLowering
::
LowerAsmOperandForConstraint
(
Op
,
Constraint
,
Ops
,
DAG
)
;
}
</s>

Lower the specified operand into the Ops vector .


emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"MEMOPw offset is not aligned correctly."

"MEMOPh offset is not aligned correctly."

"No offset range is defined for this opcode. "

"Please define it in the above switch statement!"


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: CreateExpr ( Expr ) ) ; } </s>


<s> void iq2000_va_start ( tree valist , rtx nextarg ) { int int_arg_words ; int gpr_save_area_size ; int_arg_words = current_function_args_info . arg_words ; if ( int_arg_words < 8 ) gpr_save_area_size = ( 8 - int_arg_words ) * UNITS_PER_WORD ; else gpr_save_area_size = 0 ; nextarg = plus_constant ( nextarg , - gpr_save_area_size ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>


getTargetNodeName - This method returns the name of a target specific


<s> bool XCoreTargetMachine :: addInstSelector ( PassManagerBase & PM , bool Fast ) { PM . add ( createXCoreISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ; } </s>

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget .


<s> bool ShortInstrPeephole :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { Changed |= runOnInstruction ( MI ) ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> void ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return ; unsigned PairedPhys = 0 ; if ( TargetRegisterInfo :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = 0 , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> static rtx frv_volatile_memref ( machine_mode mode , rtx arg ) { rtx mem ; mem = gen_rtx_MEM ( mode , memory_address ( mode , arg ) ) ; MEM_VOLATILE_P ( mem ) = 1 ; return mem ; } </s>

Return a volatile memory reference of mode MODE whose address is ARG .


Targets may add passes immediately before machine code is emitted in this callback .


<s> bool HexagonTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { if ( Ty -> isSized ( ) ) { Align A = DL . getABITypeAlign ( Ty ) ; if ( ! isAligned ( A , AM . BaseOffs ) ) return false ; if ( ! isInt < 11 > ( AM . BaseOffs >> Log2 ( A ) ) ) return false ; } if ( AM . BaseGV ) return false ; int Scale = AM . Scale ; if ( Scale < 0 ) Scale = - Scale ; switch ( Scale ) { case 0 : break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> unsigned MipsFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return MaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return MaterializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s>
SDValue
XCoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
ConstantPool
:
return
LowerConstantPool
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
LOAD
:
return
LowerLOAD
(
Op
,
DAG
)
;
case
ISD
::
STORE
:
return
LowerSTORE
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
VAARG
:
return
LowerVAARG
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
SMUL_LOHI
:
return
LowerSMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
UMUL_LOHI
:
return
LowerUMUL_LOHI
(
Op
,
DAG
)
;
case
ISD
::
ADD
:
case
ISD
::
SUB
:
return
ExpandADDSUB
(
Op
.
getNode
(
)
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
return
SDValue
(
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

XCore
XCore
ISD::GlobalAddress
ISD::GlobalTLSAddress
ISD::BlockAddress
ISD::ConstantPool
ISD::BR_JT
ISD::LOAD
ISD::STORE
ISD::SELECT_CC
ISD::VAARG
ISD::VASTART
ISD::SMUL_LOHI
ISD::UMUL_LOHI
ISD::ADD
ISD::SUB
ISD::FRAMEADDR
"unimplemented operand"


<s> void reset ( size_type Idx ) { V . reset ( Idx ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> bool s390_offset_p ( rtx mem1 , rtx mem2 , rtx delta ) { rtx addr1 , addr2 , addr_delta ; if ( GET_CODE ( mem1 ) != MEM || GET_CODE ( mem2 ) != MEM ) return false ; addr1 = XEXP ( mem1 , 0 ) ; addr2 = XEXP ( mem2 , 0 ) ; addr_delta = simplify_binary_operation ( MINUS , Pmode , addr2 , addr1 ) ; if ( ! addr_delta || ! rtx_equal_p ( addr_delta , delta ) ) return false ; return true ; } </s>

Check whether the address of memory reference MEM2 equals exactly the address of memory reference MEM1 plus DELTA . Return true if we can prove this to be the case , false otherwise .


"Not all fixup kinds added to Infos array"


<s> int iq2000_check_split ( rtx address , enum machine_mode mode ) { if ( GET_MODE_SIZE ( mode ) > ( unsigned ) UNITS_PER_WORD ) return 0 ; if ( ( GET_CODE ( address ) == SYMBOL_REF ) || ( GET_CODE ( address ) == CONST && GET_CODE ( XEXP ( XEXP ( address , 0 ) , 0 ) ) == SYMBOL_REF ) || GET_CODE ( address ) == LABEL_REF ) return 1 ; return 0 ; } </s>

Return nonzero if we split the address into high and low parts .


<s> static int c6x_save_reg ( unsigned int regno ) { return ( ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) || ( regno == RETURN_ADDR_REGNO && ( df_regs_ever_live_p ( regno ) || ! crtl -> is_leaf ) ) || ( regno == PIC_OFFSET_TABLE_REGNUM && must_reload_pic_reg_p ( ) ) ) ; } </s>


<s> bool SIInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { if ( MI . isTerminator ( ) || MI . isPosition ( ) ) return true ; if ( MI . getOpcode ( ) == TargetOpcode :: INLINEASM_BR ) return true ; if ( MI . getOpcode ( ) == AMDGPU :: SCHED_BARRIER && MI . getOperand ( 0 ) . getImm ( ) == 0 ) return true ; return MI . modifiesRegister ( AMDGPU :: EXEC , & RI ) || MI . getOpcode ( ) == AMDGPU :: S_SETREG_IMM32_B32 || MI . getOpcode ( ) == AMDGPU :: S_SETREG_B32 || changesVGPRIndexingMode ( MI ) ; } </s>

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled .


<s> const AGCRegisterInfo * getRegisterInfo ( ) const override { return & RegInfo ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void pa_encode_label ( rtx sym ) { const char * str = XSTR ( sym , 0 ) ; int len = strlen ( str ) + 1 ; char * newstr , * p ; p = newstr = XALLOCAVEC ( char , len + 1 ) ; * p ++ = '@' ; strcpy ( p , str ) ; XSTR ( sym , 0 ) = ggc_alloc_string ( newstr , len ) ; } </s>

In HPUX 8.0 's shared library scheme , special relocations are needed for function labels if they might be passed to a function in a shared library ( because shared libraries do n't live in code space ) , and special magic is needed to construct their address .


<s>
bool
SNESFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
DebugLoc
DL
=
MBB
.
findDebugLoc
(
MI
)
;
const
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
SNESSubtarget
&
STI
=
MF
.
getSubtarget
<
SNESSubtarget
>
(
)
;
const
TargetInstrInfo
&
TII
=
*
STI
.
getInstrInfo
(
)
;
for
(
const
CalleeSavedInfo
&
CCSI
:
CSI
)
{
unsigned
Reg
=
CCSI
.
getReg
(
)
;
assert
(
TRI
->
getRegSizeInBits
(
*
TRI
->
getMinimalPhysRegClass
(
Reg
)
)
==
16
&&
"Invalid register size"
)
;
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
SNES
::
POPRd
)
,
Reg
)
;
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .

SNES
SNES
SNES
SNES
16
"Invalid register size"
SNES::POPRd


<s> SDValue OR1KTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_OR1K32 ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; InVals . push_back ( Chain . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: D14 ) ; Reserved . set ( Hexagon :: D15 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: SA1 ) ; Reserved . set ( Hexagon :: UGP ) ; Reserved . set ( Hexagon :: GP ) ; Reserved . set ( Hexagon :: CS0 ) ; Reserved . set ( Hexagon :: CS1 ) ; Reserved . set ( Hexagon :: CS ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"local variable memory requirements exceed capacity"

Called after register allocation to add any instructions needed for the prologue . Using a prologue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling . Also any insns generated here should have RTX_FRAME_RELATED_P ( insn ) = 1 so that the debug info generation code can handle them properly .


"\tARM::shouldCoalesce - Coalesced Weight: "


"You cannot use the same Regs with MOVX_RR"

"You cannot use the same Reg Classes with MOVX_RR"

Move across register classes without extension .


<s> rtx mips_gen_const_int_vector ( machine_mode mode , HOST_WIDE_INT val ) { int nunits = GET_MODE_NUNITS ( mode ) ; rtvec v = rtvec_alloc ( nunits ) ; int i ; for ( i = 0 ; i < nunits ; i ++ ) RTVEC_ELT ( v , i ) = gen_int_mode ( val , GET_MODE_INNER ( mode ) ) ; return gen_rtx_CONST_VECTOR ( mode , v ) ; } </s>

Return a const_int vector of VAL with mode MODE .


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { return false ; } </s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> bool isFI ( ) const { return Kind == MachineOperand :: MO_FrameIndex ; } </s>

isFI - Tests if this is a MO_FrameIndex operand .


<s> static ARMCC :: CondCodes getPredicate ( const MachineInstr * MI , unsigned & PredReg ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == ARM :: tBcc || Opc == ARM :: t2Bcc ) return ARMCC :: AL ; return llvm :: getInstrPredicate ( MI , PredReg ) ; } </s>

Returns the comparison predicate underlying the intrinsic .

ARM ARMCC::CondCodes ARM::tBcc ARM::t2Bcc ARMCC::AL


<s>
unsigned
BPFInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
I
->
getOpcode
(
)
!=
BPF
::
JMP
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .

BPF
BPF
"code size not handled"
0
BPF::JMP


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { const X86TargetMachine * TM = static_cast < const X86TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getSubtarget < X86Subtarget > ( ) . is64Bit ( ) ) return false ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = X86FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == 0 ) return false ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const X86InstrInfo * TII = TM -> getInstrInfo ( ) ; unsigned PC ; if ( TM -> getSubtarget < X86Subtarget > ( ) . isPICStyleGOT ( ) ) PC = RegInfo . createVirtualRegister ( & X86 :: GR32RegClass ) ; else PC = GlobalBaseReg ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: MOVPC32r ) , PC ) . addImm ( 0 ) ; if ( TM -> getSubtarget < X86Subtarget > ( ) . isPICStyleGOT ( ) ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( X86 :: ADD32ri ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( "_GLOBAL_OFFSET_TABLE_" , X86II :: MO_GOT_ABSOLUTE_ADDRESS ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
unsigned
getReg
(
)
const
{
assert
(
(
Kind
==
k_Register
||
Kind
==
k_CCOut
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> static bool hasUnscaledLdStOffset ( MachineInstr & MI ) { return hasUnscaledLdStOffset ( MI . getOpcode ( ) ) ; } </s>

Return true if it has an unscaled load/store offset .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
if
(
skipFunction
(
*
Func
.
getFunction
(
)
)
)
return
false
;
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
->
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
ST
.
slowLEA
(
)
||
ST
.
slow3OpsLEA
(
)
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TII
=
ST
.
getInstrInfo
(
)
;
DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>


<s>
void
ix86_file_end
(
void
)
{
rtx
xops
[
2
]
;
int
regno
;
for
(
regno
=
0
;
regno
<
8
;
++
regno
)
{
char
name
[
32
]
;
if
(
!
(
(
pic_labels_used
>>
regno
)
&
1
)
)
continue
;
get_pc_thunk_name
(
name
,
regno
)
;
if
(
USE_HIDDEN_LINKONCE
)
{
tree
decl
;
decl
=
build_decl
(
FUNCTION_DECL
,
get_identifier
(
name
)
,
error_mark_node
)
;
TREE_PUBLIC
(
decl
)
=
1
;
TREE_STATIC
(
decl
)
=
1
;
DECL_ONE_ONLY
(
decl
)
=
1
;
(
*
targetm
.
asm_out
.
unique_section
)
(
decl
,
0
)
;
named_section
(
decl
,
,
0
)
;
(
*
targetm
.
asm_out
.
globalize_label
)
(
asm_out_file
,
name
)
;
fputs
(
"\t.hidden\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
fputc
(
'\n'
,
asm_out_file
)
;
ASM_DECLARE_FUNCTION_NAME
(
asm_out_file
,
name
,
decl
)
;
}
else
{
text_section
(
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
}
xops
[
0
]
=
gen_rtx_REG
(
SImode
,
regno
)
;
xops
[
1
]
=
gen_rtx_MEM
(
SImode
,
stack_pointer_rtx
)
;
output_asm_insn
(
"mov{l}\t{%1, %0|%0, %1}"
,
xops
)
;
output_asm_insn
(
"ret"
,
xops
)
;
}
if
(
NEED_INDICATE_EXEC_STACK
)
file_end_indicate_exec_stack
(
)
;
}
</s>

This function generates code for -fpic that loads % ebx with the return address of the caller and then returns .


<s> BitVector PIC16RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; return Reserved ; } </s>


<s>
static
tree
resolve_vec_step
(
resolution
*
res
,
vec
<
tree
,
va_gc
>
*
arglist
,
unsigned
nargs
)
{
if
(
nargs
!=
1
)
{
error
(
"builtin %qs only accepts 1 argument"
,
"vec_step"
)
;
*
res
=
resolved
;
return
error_mark_node
;
}
tree
arg0
=
(
*
arglist
)
[
0
]
;
tree
arg0_type
=
TREE_TYPE
(
arg0
)
;
if
(
TREE_CODE
(
arg0_type
)
!=
VECTOR_TYPE
)
{
*
res
=
resolved_bad
;
return
error_mark_node
;
}
*
res
=
resolved
;
return
build_int_cst
(
NULL_TREE
,
TYPE_VECTOR_SUBPARTS
(
arg0_type
)
)
;
}
</s>

Resolve an overloaded vec_step call and return a tree expression for the resolved call if successful . NARGS is the number of arguments to the call . ARGLIST contains the arguments . RES must be set to indicate the status of the resolution attempt .


<s> bool TriCoreRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool X86TargetLowering :: isVectorLoadExtDesirable ( SDValue ) const { return true ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> bool n9_3r2w_consumed_by_ex_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_PBSAD : case TYPE_MUL : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


<s> static _Unwind_Reason_Code get_eit_entry ( _Unwind_Control_Block * ucbp , _uw return_address ) { const __EIT_entry * eitp ; int nrec ; return_address -= 2 ; if ( __gnu_Unwind_Find_exidx ) { eitp = ( const __EIT_entry * ) __gnu_Unwind_Find_exidx ( return_address , & nrec ) ; if ( ! eitp ) { UCB_PR_ADDR ( ucbp ) = 0 ; return _URC_FAILURE ; } } else { eitp = & __exidx_start ; nrec = & __exidx_end - & __exidx_start ; } eitp = search_EIT_table ( eitp , nrec , return_address ) ; if ( ! eitp ) { UCB_PR_ADDR ( ucbp ) = 0 ; return _URC_FAILURE ; } ucbp -> pr_cache . fnstart = selfrel_offset31 ( & eitp -> fnoffset ) ; if ( eitp -> content == EXIDX_CANTUNWIND ) { UCB_PR_ADDR ( ucbp ) = 0 ; return _URC_END_OF_STACK ; } if ( eitp -> content & uint32_highbit ) { ucbp -> pr_cache . ehtp = ( _Unwind_EHT_Header * ) & eitp -> content ; ucbp -> pr_cache . additional = 1 ; } else { ucbp -> pr_cache . ehtp = ( _Unwind_EHT_Header * ) selfrel_offset31 ( & eitp -> content ) ; ucbp -> pr_cache . additional = 0 ; } if ( * ucbp -> pr_cache . ehtp & ( 1u << 31 ) ) { _uw idx = ( * ( _uw * ) ucbp -> pr_cache . ehtp >> 24 ) & 0xf ; if ( idx == 0 ) UCB_PR_ADDR ( ucbp ) = ( _uw ) & __aeabi_unwind_cpp_pr0 ; else if ( idx == 1 ) UCB_PR_ADDR ( ucbp ) = ( _uw ) & __aeabi_unwind_cpp_pr1 ; else if ( idx == 2 ) UCB_PR_ADDR ( ucbp ) = ( _uw ) & __aeabi_unwind_cpp_pr2 ; else { UCB_PR_ADDR ( ucbp ) = 0 ; return _URC_FAILURE ; } } else { UCB_PR_ADDR ( ucbp ) = selfrel_offset31 ( ucbp -> pr_cache . ehtp ) ; } return _URC_OK ; } </s>

Find the exception index table eintry for the given address . Fill in the relevant fields of the UCB . Returns _URC_FAILURE if an error occurred , _URC_OK on success .


<s> poly_int64 m68k_push_rounding ( poly_int64 bytes ) { if ( TARGET_COLDFIRE ) return bytes ; return ( bytes + 1 ) & ~ 1 ; } </s>

Implement PUSH_ROUNDING . On the 680x0 , sp @ - in a byte insn really pushes a word . On the ColdFire , sp @ - in a byte insn pushes just a byte .


<s> bool function_checker :: require_immediate_range ( unsigned int rel_argno , HOST_WIDE_INT min , HOST_WIDE_INT max ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; gcc_assert ( min >= 0 && min <= max ) ; HOST_WIDE_INT actual ; if ( ! require_immediate ( argno , actual ) ) return false ; if ( ! IN_RANGE ( actual , min , max ) ) { report_out_of_range ( location , fndecl , argno , actual , min , max ) ; return false ; } return true ; } </s>

Check that argument REL_ARGNO is an integer constant expression in the range [ MIN , MAX ] . REL_ARGNO counts from the end of the predication arguments .


<s> static unsigned char riscv_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( reg_class_subset_p ( rclass , FP_REGS ) ) return riscv_hard_regno_nregs ( FP_REG_FIRST , mode ) ; if ( reg_class_subset_p ( rclass , GR_REGS ) ) return riscv_hard_regno_nregs ( GP_REG_FIRST , mode ) ; if ( reg_class_subset_p ( rclass , V_REGS ) ) return riscv_hard_regno_nregs ( V_REG_FIRST , mode ) ; return 0 ; } </s>


<s> void SIInstrInfo :: legalizeOpWithMove ( MachineInstr & MI , unsigned OpIdx ) const { MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineOperand & MO = MI . getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const SIRegisterInfo * TRI = static_cast < const SIRegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned RCID = get ( MI . getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Size = TRI -> getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == 64 ) ? AMDGPU :: V_MOV_B64_PSEUDO : AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) Opcode = AMDGPU :: COPY ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == 64 ) ? AMDGPU :: S_MOV_B64 : AMDGPU :: S_MOV_B32 ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & AMDGPU :: VReg_64RegClass , VRC ) ) VRC = & AMDGPU :: VReg_64RegClass ; else VRC = & AMDGPU :: VGPR_32RegClass ; unsigned Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI . getParent ( ) , I , DL , get ( Opcode ) , Reg ) . add ( MO ) ; MO . ChangeToRegister ( Reg , false ) ; } </s>

Legalize the OpIndex operand of this instruction by inserting a MOV .


<s> static void arm_relayout_function ( tree fndecl ) { if ( DECL_USER_ALIGN ( fndecl ) ) return ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; DECL_ALIGN ( fndecl ) = FUNCTION_BOUNDARY_P ( TREE_TARGET_OPTION ( callee_tree ) -> x_target_flags ) ; } </s>

Hook to fix function 's alignment affected by target attribute .


<s> rtx_insn * mips_expand_call ( enum mips_call_type type , rtx result , rtx addr , rtx args_size , rtx aux , bool lazy_p ) { rtx orig_addr , pattern ; rtx_insn * insn ; int fp_code ; fp_code = aux == 0 ? 0 : ( int ) GET_MODE ( aux ) ; insn = mips16_build_call_stub ( result , & addr , args_size , fp_code ) ; if ( insn ) { gcc_assert ( ! lazy_p && type == MIPS_CALL_NORMAL ) ; return insn ; } orig_addr = addr ; if ( ! call_insn_operand ( addr , VOIDmode ) ) { if ( type == MIPS_CALL_EPILOGUE ) addr = MIPS_EPILOGUE_TEMP ( Pmode ) ; else addr = gen_reg_rtx ( Pmode ) ; lazy_p |= mips_load_call_address ( type , addr , orig_addr ) ; } if ( result == 0 ) { rtx ( * fn ) ( rtx , rtx ) ; if ( type == MIPS_CALL_SIBCALL ) fn = gen_sibcall_internal ; else fn = gen_call_internal ; pattern = fn ( addr , args_size ) ; } else if ( GET_CODE ( result ) == PARALLEL && XVECLEN ( result , 0 ) == 2 ) { rtx ( * fn ) ( rtx , rtx , rtx , rtx ) ; rtx reg1 , reg2 ; if ( type == MIPS_CALL_SIBCALL ) fn = gen_sibcall_value_multiple_internal ; else fn = gen_call_value_multiple_internal ; reg1 = XEXP ( XVECEXP ( result , 0 , 0 ) , 0 ) ; reg2 = XEXP ( XVECEXP ( result , 0 , 1 ) , 0 ) ; pattern = fn ( reg1 , addr , args_size , reg2 ) ; } else { rtx ( * fn ) ( rtx , rtx , rtx ) ; if ( type == MIPS_CALL_SIBCALL ) fn = gen_sibcall_value_internal ; else fn = gen_call_value_internal ; if ( GET_CODE ( result ) == PARALLEL && XVECLEN ( result , 0 ) == 1 ) result = XEXP ( XVECEXP ( result , 0 , 0 ) , 0 ) ; pattern = fn ( result , addr , args_size ) ; } return mips_emit_call_insn ( pattern , orig_addr , addr , lazy_p ) ; } </s>

Expand a call or call_value instruction . RESULT is where the result will go ( null for calls ) , ADDR is the address of the function , ARGS_SIZE is the size of the arguments and AUX is the value passed to us by mips_function_arg . SIBCALL_P is true if we are expanding a sibling call , false if we 're expanding a normal call .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( EnableSVEIntrinsicOpts && TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createSVEIntrinsicOptsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool Thumb2ITBlockPass :: runOnMachineFunction ( MachineFunction & Fn ) { const TargetMachine & TM = Fn . getTarget ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; restrictIT = TM . getSubtarget < ARMSubtarget > ( ) . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; } if ( Modified ) AFI -> setHasITBlocks ( true ) ; return Modified ; } </s>


"sh_try_split_insn_simple n = %d i = \n"

Given an rtx x , which is assumed to be some expression that has been matched by the 'treg_set_expr ' predicate before , split and emit the insns that are necessary to calculate the expression and store the result in the T bit . The splitting is done recursively similar to 'try_split ' in emit-rt.c . Unfortunately we ca n't use 'try_split ' here directly , as it tries to invoke 'delete_insn ' which then causes the DF parts to bail out , because we currently are inside another gen_split * function and would invoke 'try_split ' in a reentrant way .


<s> ix86_dependencies_evaluation_hook static int ix86_reassociation_width ( unsigned int op , machine_mode mode ) { int width = 1 ; if ( VECTOR_MODE_P ( mode ) ) { int div = 1 ; if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_vec_fp ; if ( width == 1 ) return 1 ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return 1 ; if ( TARGET_AVX128_OPTIMAL && GET_MODE_BITSIZE ( mode ) > 128 ) div = GET_MODE_BITSIZE ( mode ) / 128 ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > 64 ) div = GET_MODE_BITSIZE ( mode ) / 64 ; width = ( width + div - 1 ) / div ; } else if ( INTEGRAL_MODE_P ( mode ) ) width = ix86_cost -> reassoc_int ; else if ( FLOAT_MODE_P ( mode ) ) width = ix86_cost -> reassoc_fp ; if ( ! TARGET_64BIT && width > 2 ) width = 2 ; return width ; } </s>

Implementation of reassociation_width target hook used by reassoc phase to identify parallelism level in reassociated tree . Statements tree_code is passed in OPC . Arguments type is passed in MODE . Currently parallel reassociation is enabled for Atom processors only and we set reassociation width to be 2 because Atom may issue up to 2 instructions per cycle . Return value should be fixed if parallel reassociation is enabled for other processors .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned SIInstrInfo :: readlaneVGPRToSGPR ( unsigned SrcReg , MachineInstr & UseMI , MachineRegisterInfo & MRI ) const { const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = RI . getRegSizeInBits ( * VRC ) / 32 ; if ( SubRegs == 1 ) { BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , DstReg ) . addReg ( SrcReg ) ; return DstReg ; } SmallVector < unsigned , 8 > SRegs ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , SGPR ) . addReg ( SrcReg , 0 , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( AMDGPU :: REG_SEQUENCE ) , DstReg ) ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { MIB . addReg ( SRegs [ i ] ) ; MIB . addImm ( RI . getSubRegFromChannel ( i ) ) ; } return DstReg ; } </s>

Copy a value from a VGPR ( SrcReg ) to SGPR .


<s> BitVector SystemZRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const SystemZFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( SystemZ :: R11D ) ; Reserved . set ( SystemZ :: R11L ) ; Reserved . set ( SystemZ :: R11H ) ; Reserved . set ( SystemZ :: R10Q ) ; } Reserved . set ( SystemZ :: R15D ) ; Reserved . set ( SystemZ :: R15L ) ; Reserved . set ( SystemZ :: R15H ) ; Reserved . set ( SystemZ :: R14Q ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> SDValue Cpu0SETargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { return Cpu0TargetLowering :: LowerOperation ( Op , DAG ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool PPCAsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( isDarwin ( ) ) { if ( IDVal == ".machine" ) ParseDarwinDirectiveMachine ( DirectiveID . getLoc ( ) ) ; else return true ; } else if ( IDVal == ".word" ) ParseDirectiveWord ( 2 , DirectiveID ) ; else if ( IDVal == ".llong" ) ParseDirectiveWord ( 8 , DirectiveID ) ; else if ( IDVal == ".tc" ) ParseDirectiveTC ( isPPC64 ( ) ? 8 : 4 , DirectiveID ) ; else if ( IDVal == ".machine" ) ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".abiversion" ) ParseDirectiveAbiVersion ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".localentry" ) ParseDirectiveLocalEntry ( DirectiveID . getLoc ( ) ) ; else return true ; return false ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMTargetMachine * TM = static_cast < const ARMTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned ARMPCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb ( ) ? 4 : 8 ; ARMConstantPoolValue * CPV = ARMConstantPoolSymbol :: Create ( * Context , "_GLOBAL_OFFSET_TABLE_" , ARMPCLabelIndex , PCAdj ) ; unsigned Align = TM -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned TempReg = MF . getRegInfo ( ) . createVirtualRegister ( & ARM :: rGPRRegClass ) ; unsigned Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: tPICADD : ARM :: PICADD ; MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addReg ( TempReg ) . addImm ( ARMPCLabelIndex ) ; if ( Opc == ARM :: PICADD ) AddDefaultPred ( MIB ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

ARM ARM ARM 0 ARM ARM ARM ARM 4 8 ARM ARM "_GLOBAL_OFFSET_TABLE_" ARM ARM::rGPRRegClass ARM ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0 ARM ARM::tPICADD ARM::PICADD ARM ARM::PICADD


<s> unsigned ARCInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . isInlineAsm ( ) ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsZeroVal , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( this -> PPCSubTarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
static
MCSymbol
*
GetSymbolFromOperand
(
const
MachineOperand
&
MO
,
AsmPrinter
&
AP
)
{
const
TargetMachine
&
TM
=
AP
.
TM
;
Mangler
&
Mang
=
TM
.
getObjFileLowering
(
)
->
getMangler
(
)
;
const
DataLayout
&
DL
=
AP
.
getDataLayout
(
)
;
MCContext
&
Ctx
=
AP
.
OutContext
;
SmallString
<
128
>
Name
;
if
(
!
MO
.
isGlobal
(
)
)
{
assert
(
MO
.
isSymbol
(
)
&&
"Isn't a symbol reference"
)
;
Mangler
::
getNameWithPrefix
(
Name
,
MO
.
getSymbolName
(
)
,
DL
)
;
}
else
{
const
GlobalValue
*
GV
=
MO
.
getGlobal
(
)
;
TM
.
getNameWithPrefix
(
Name
,
GV
,
Mang
)
;
}
MCSymbol
*
Sym
=
Ctx
.
getOrCreateSymbol
(
Name
)
;
return
Sym
;
}
</s>

Lower an MO_GlobalAddress or MO_ExternalSymbol operand to an MCSymbol .


<s> SMLoc getStartLoc ( ) const { return Start ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> const RISCVMCExpr * RISCVMCExpr :: create ( RISCVMCExpr :: VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) RISCVMCExpr ( Kind , Expr ) ; } </s>


<s> const uint32_t * RISCVRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { if ( MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtD ( ) ) return CSR_XLEN_F64_Interrupt_RegMask ; if ( MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_RegMask ; return CSR_Interrupt_RegMask ; } return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> MCFragment * findAssociatedFragment ( ) const override { return getSubExpr ( ) -> findAssociatedFragment ( ) ; } </s>

Find the `` associated section '' for this expression , which is currently defined as the absolute section for constants , or otherwise the section associated with the first defined symbol in the expression .


<s> bool ARMFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; unsigned PopOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDMIA_UPD : ARM :: LDMIA_UPD ; unsigned LdrOpc = AFI -> isThumbFunction ( ) ? ARM :: t2LDR_POST : ARM :: LDR_POST ; unsigned FltOpc = ARM :: VLDMDIA_UPD ; emitPopInst ( MBB , MI , CSI , FltOpc , 0 , isVarArg , true , & isARMArea3Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea2Register ) ; emitPopInst ( MBB , MI , CSI , PopOpc , LdrOpc , isVarArg , false , & isARMArea1Register ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> TargetIRAnalysis PPCTargetMachine :: getTargetIRAnalysis ( ) { return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( PPCTTIImpl ( this , F ) ) ; } ) ; } </s>

Get a TargetIRAnalysis appropriate for the target .


<s> static bool xtensa_tls_symbol_p ( rtx x ) { if ( ! targetm . have_tls ) return false ; return GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return TRUE if X is a thread-local symbol .


<s> unsigned getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: MUL : case ISD :: SDIV : case ISD :: UDIV : case ISD :: UREM : return 64 * BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

Lanai ISD::MUL ISD::SDIV ISD::UDIV ISD::UREM 64


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool AArch64PassConfig :: addPreEmitPass ( ) { addPass ( createAArch64BranchRelaxation ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < AArch64Subtarget > ( ) . isTargetMachO ( ) ) addPass ( createAArch64CollectLOHPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> void SystemZMCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { unsigned Opcode = MI -> getOpcode ( ) ; if ( ! AsmPrinter . OutStreamer . hasRawTextSupport ( ) ) Opcode = getShortenedInstr ( Opcode ) ; OutMI . setOpcode ( Opcode ) ; for ( unsigned I = 0 , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; MCOperand MCOp = lowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ; } } </s>


<s> MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return createAMDGPUELFObjectWriter ( Is64Bit , OS ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> void ARMBaseRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock :: iterator I , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { ARMFunctionInfo * AFI = I -> getParent ( ) -> getParent ( ) -> getInfo < ARMFunctionInfo > ( ) ; unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? ARM :: ADDri : ( AFI -> isThumb1OnlyFunction ( ) ? ARM :: tADDrSPi : ARM :: t2ADDri ) ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII . get ( ADDriOpc ) , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ; if ( ! AFI -> isThumb1OnlyFunction ( ) ) AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .

ARM ARM ARM ARM ARM::ADDri ARM::tADDrSPi ARM::t2ADDri


<s> const_pointer get ( ) const SPIMPL_NOEXCEPT { return ptr_ . get ( ) ; } </s>

Get the generated Value for a given VPValue and given Part and Lane .


<s> void rl78_expand_prologue ( void ) { int i , fs ; rtx sp = gen_rtx_REG ( HImode , STACK_POINTER_REGNUM ) ; rtx ax = gen_rtx_REG ( HImode , AX_REG ) ; int rb = 0 ; if ( rl78_is_naked_func ( ) ) return ; rl78_compute_frame_info ( ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> framesize ; if ( is_interrupt_func ( cfun -> decl ) && ! TARGET_G10 ) for ( i = 0 ; i < 4 ; i ++ ) if ( cfun -> machine -> need_to_push [ i ] ) { emit_insn ( gen_sel_rb ( GEN_INT ( 0 ) ) ) ; break ; } for ( i = 0 ; i < 16 ; i ++ ) if ( cfun -> machine -> need_to_push [ i ] ) { int reg = i * 2 ; if ( TARGET_G10 ) { if ( reg >= 8 ) { emit_move_insn ( ax , gen_rtx_REG ( HImode , reg ) ) ; reg = AX_REG ; } } else { int need_bank = i / 4 ; if ( need_bank != rb ) { emit_insn ( gen_sel_rb ( GEN_INT ( need_bank ) ) ) ; rb = need_bank ; } } F ( emit_insn ( gen_push ( gen_rtx_REG ( HImode , reg ) ) ) ) ; } if ( rb != 0 ) emit_insn ( gen_sel_rb ( GEN_INT ( 0 ) ) ) ; if ( is_interrupt_func ( cfun -> decl ) && cfun -> machine -> uses_es ) { emit_insn ( gen_movqi_from_es ( gen_rtx_REG ( QImode , A_REG ) ) ) ; F ( emit_insn ( gen_push ( ax ) ) ) ; } if ( frame_pointer_needed ) { F ( emit_move_insn ( ax , sp ) ) ; F ( emit_move_insn ( gen_rtx_REG ( HImode , FRAME_POINTER_REGNUM ) , ax ) ) ; } fs = cfun -> machine -> framesize_locals + cfun -> machine -> framesize_outgoing ; if ( fs > 0 ) { if ( fs > 254 * 3 ) { rtx insn ; emit_move_insn ( ax , sp ) ; emit_insn ( gen_subhi3 ( ax , ax , GEN_INT ( fs ) ) ) ; insn = F ( emit_move_insn ( sp , ax ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( sp , gen_rtx_PLUS ( HImode , sp , GEN_INT ( - fs ) ) ) ) ; } else { while ( fs > 0 ) { int fs_byte = ( fs > 254 ) ? 254 : fs ; F ( emit_insn ( gen_subhi3 ( sp , sp , GEN_INT ( fs_byte ) ) ) ) ; fs -= fs_byte ; } } } } </s>

Expand the function prologue ( from the prologue pattern ) .


<s> const P2RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s>
static
void
bpf_function_arg_advance
(
cumulative_args_t
ca
,
const
function_arg_info
&
arg
)
{
CUMULATIVE_ARGS
*
cum
=
get_cumulative_args
(
ca
)
;
unsigned
num_bytes
=
arg
.
type_size_in_bytes
(
)
;
unsigned
num_words
=
CEIL
(
num_bytes
,
UNITS_PER_WORD
)
;
if
(
*
cum
<=
5
&&
*
cum
+
num_words
>
5
)
error
(
"too many function arguments for eBPF"
)
;
*
cum
+=
num_words
;
}
</s>

Update the summarizer variable pointed by CA to advance past an argument in the argument list .


<s> int ix86_binary_operator_ok ( enum rtx_code code , enum machine_mode mode ATTRIBUTE_UNUSED , rtx operands [ 3 ] ) { if ( GET_CODE ( operands [ 1 ] ) == MEM && GET_CODE ( operands [ 2 ] ) == MEM ) return 0 ; if ( CONSTANT_P ( operands [ 1 ] ) && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH ) return 0 ; if ( GET_CODE ( operands [ 0 ] ) == MEM && ! ( rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) || ( GET_RTX_CLASS ( code ) == RTX_COMM_ARITH && rtx_equal_p ( operands [ 0 ] , operands [ 2 ] ) ) ) ) return 0 ; if ( GET_CODE ( operands [ 1 ] ) == MEM && GET_RTX_CLASS ( code ) != RTX_COMM_ARITH && ! rtx_equal_p ( operands [ 0 ] , operands [ 1 ] ) ) return 0 ; return 1 ; } </s>

Return TRUE or FALSE depending on whether the binary operator meets the appropriate constraints .


<s> MachineBasicBlock :: iterator Thumb1FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const Thumb1InstrInfo & TII = * static_cast < const Thumb1InstrInfo * > ( STI . getInstrInfo ( ) ) ; const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != 0 ) { Amount = alignTo ( Amount , getStackAlignment ( ) ) ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == ARM :: ADJCALLSTACKDOWN || Opc == ARM :: tADJCALLSTACKDOWN ) { emitCallSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == ARM :: ADJCALLSTACKUP || Opc == ARM :: tADJCALLSTACKUP ) ; emitCallSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; } } } return MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .

ARM 0 ARM::ADJCALLSTACKDOWN ARM::tADJCALLSTACKDOWN ARM::ADJCALLSTACKUP ARM::tADJCALLSTACKUP


"List of x86 specific tuning parameter names:\n"

Helper function to set ix86_tune_features . IX86_TUNE is the processor type .


<s> bool MipsTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { if ( ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) && Type == MVT :: i32 ) return true ; return IsSigned ; } </s>

Returns true if arguments should be sign-extended in lib calls .


<s> void X86PassConfig :: addPreRegAlloc ( ) { if ( GenerateSgxCode ) { addPass ( createSgxMCPass ( ) ) ; addPass ( createX86WinAllocaExpander ( ) ) ; return ; } if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createX86FixupSetCC ( ) ) ; addPass ( createX86OptimizeLEAs ( ) ) ; addPass ( createX86CallFrameOptimization ( ) ) ; } addPass ( createX86WinAllocaExpander ( ) ) ; addPass ( createMachineInstPrint ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static int cr16_memory_move_cost ( machine_mode mode , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { if ( reg_classes_intersect_p ( rclass , GENERAL_REGS ) ) return ( 4 * cr16_hard_regno_nregs ( 0 , mode ) ) ; else return ( 100 ) ; } </s>

Return the cost of moving data of mode MODE between a register of class CLASS and memory ; IN is zero if the value is to be written to memory , nonzero if it is to be read in . This cost is relative to those in REGISTER_MOVE_COST .


<s>
static
void
thumb_pop
(
FILE
*
f
,
unsigned
long
mask
)
{
int
regno
;
int
lo_mask
=
mask
&
0xFF
;
gcc_assert
(
mask
)
;
if
(
lo_mask
==
0
&&
(
mask
&
(
1
<<
PC_REGNUM
)
)
)
{
thumb_exit
(
f
,
1
)
;
return
;
}
fprintf
(
f
,
"\tpop\t{"
)
;
for
(
regno
=
0
;
regno
<=
LAST_LO_REGNUM
;
regno
++
,
lo_mask
>>=
1
)
{
if
(
lo_mask
&
1
)
{
asm_fprintf
(
f
,
"%r"
,
regno
)
;
if
(
(
lo_mask
&
~
1
)
!=
0
)
fprintf
(
f
,
", "
)
;
}
}
if
(
mask
&
(
1
<<
PC_REGNUM
)
)
{
if
(
TARGET_INTERWORK
||
TARGET_BACKTRACE
||
crtl
->
calls_eh_return
||
IS_CMSE_ENTRY
(
arm_current_func_type
(
)
)
)
{
fprintf
(
f
,
"}\n"
)
;
thumb_exit
(
f
,
1
)
;
return
;
}
else
{
if
(
mask
&
0xFF
)
fprintf
(
f
,
", "
)
;
asm_fprintf
(
f
,
"%r"
,
PC_REGNUM
)
;
}
}
fprintf
(
f
,
"}\n"
)
;
}
</s>

Emit code to push or pop registers to or from the stack . F is the assembly file . MASK is the registers to pop .


<s> unsigned Cpu0MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) { return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( 32 ) . getLimitedValue ( ) ) ; } assert ( MO . isExpr ( ) ) ; return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } </s>

getMachineOpValue - Return binary encoding of operand .


<s>
bool
MipsSEDAGToDAGISel
::
SelectInlineAsmMemoryOperand
(
const
SDValue
&
Op
,
unsigned
ConstraintID
,
std
::
vector
<
SDValue
>
&
OutOps
)
{
SDValue
Base
,
Offset
;
switch
(
ConstraintID
)
{
default
:
llvm_unreachable
(
"Unexpected asm memory constraint"
)
;
case
InlineAsm
::
Constraint_m
:
case
InlineAsm
::
Constraint_o
:
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_R
:
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
case
InlineAsm
::
Constraint_ZC
:
if
(
Subtarget
->
inMicroMipsMode
(
)
)
{
if
(
selectAddrRegImm12
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
Subtarget
->
hasMips32r6
(
)
)
{
if
(
selectAddrRegImm9
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
}
else
if
(
selectAddrRegImm16
(
Op
,
Base
,
Offset
)
)
{
OutOps
.
push_back
(
Base
)
;
OutOps
.
push_back
(
Offset
)
;
return
false
;
}
OutOps
.
push_back
(
Op
)
;
OutOps
.
push_back
(
CurDAG
->
getTargetConstant
(
0
,
SDLoc
(
Op
)
,
MVT
::
i32
)
)
;
return
false
;
}
return
true
;
}
</s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> static void m68k_conditional_register_usage ( void ) { int i ; HARD_REG_SET x ; if ( ! TARGET_HARD_FLOAT ) { COPY_HARD_REG_SET ( x , reg_class_contents [ ( int ) FP_REGS ] ) ; for ( i = 0 ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( x , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = 1 ; } if ( flag_pic ) fixed_regs [ PIC_REG ] = call_used_regs [ PIC_REG ] = 1 ; } </s>

Make sure everything 's fine if we * do n't * have a given processor . This assumes that putting a register in fixed_regs will keep the compiler 's mitts completely off it . We do n't bother to zero it out of register classes .


<s> rtx expand ( function_expander & e ) const OVERRIDE { int unspec = ( e . type_suffix ( 1 ) . unsigned_p ? m_unspec_for_uint : m_unspec_for_sint ) ; machine_mode pred_mode = e . vector_mode ( 0 ) ; scalar_mode reg_mode = GET_MODE_INNER ( e . vector_mode ( 1 ) ) ; return e . use_exact_insn ( code_for_while ( unspec , reg_mode , pred_mode ) ) ; } </s>


"\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n"

Internal function to add a potential insn to the list of insns to be inserted if the conditional execution conversion is successful .


<s> bool SparcAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> CCAssignFn * SNESTargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC ) const { switch ( CC ) { default : return RetCC_SNES ; } } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> static rtx frame_move_inc ( rtx dst , rtx src , rtx reg , rtx addr ) { rtx insn = frame_move ( dst , src ) ; if ( ! addr || GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC || GET_CODE ( addr ) == PRE_MODIFY || GET_CODE ( addr ) == POST_MODIFY ) add_reg_note ( insn , REG_INC , reg ) ; return insn ; } </s>

Like frame_move , but add a REG_INC note for REG if ADDR contains an auto increment address , or is zero .


<s> bool shouldBuildLookupTablesForConstant ( Constant * C ) const { if ( ST -> isROPI ( ) || ST -> isRWPI ( ) ) return ! C -> needsDynamicRelocation ( ) ; return true ; } </s>

Return true if switches should be turned into lookup tables containing this constant value for the target .


<s> void xtensa_split_operand_pair ( rtx operands [ 4 ] , machine_mode mode ) { switch ( GET_CODE ( operands [ 1 ] ) ) { case REG : operands [ 3 ] = gen_rtx_REG ( mode , REGNO ( operands [ 1 ] ) + 1 ) ; operands [ 2 ] = gen_rtx_REG ( mode , REGNO ( operands [ 1 ] ) ) ; break ; case MEM : operands [ 3 ] = adjust_address ( operands [ 1 ] , mode , GET_MODE_SIZE ( mode ) ) ; operands [ 2 ] = adjust_address ( operands [ 1 ] , mode , 0 ) ; break ; case CONST_INT : case CONST_DOUBLE : split_double ( operands [ 1 ] , & operands [ 2 ] , & operands [ 3 ] ) ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( operands [ 0 ] ) ) { case REG : operands [ 1 ] = gen_rtx_REG ( mode , REGNO ( operands [ 0 ] ) + 1 ) ; operands [ 0 ] = gen_rtx_REG ( mode , REGNO ( operands [ 0 ] ) ) ; break ; case MEM : operands [ 1 ] = adjust_address ( operands [ 0 ] , mode , GET_MODE_SIZE ( mode ) ) ; operands [ 0 ] = adjust_address ( operands [ 0 ] , mode , 0 ) ; break ; default : gcc_unreachable ( ) ; } } </s>

Split OP [ 1 ] into OP [ 2,3 ] and likewise for OP [ 0 ] into OP [ 0,1 ] . MODE is for the output , i.e. , the input operands are twice as big as MODE .


<s> static bool s390_z10_optimize_cmp ( rtx_insn * insn ) { rtx_insn * prev_insn , * next_insn ; bool insn_added_p = false ; rtx cond , * op0 , * op1 ; if ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL ) { rtx pattern = single_set ( insn ) ; if ( ! pattern || SET_DEST ( pattern ) != pc_rtx || GET_CODE ( SET_SRC ( pattern ) ) != IF_THEN_ELSE ) return false ; cond = XEXP ( SET_SRC ( pattern ) , 0 ) ; op0 = & XEXP ( cond , 0 ) ; op1 = & XEXP ( cond , 1 ) ; } else if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { rtx src , dest ; src = SET_SRC ( PATTERN ( insn ) ) ; dest = SET_DEST ( PATTERN ( insn ) ) ; if ( ! REG_P ( dest ) || ! CC_REGNO_P ( REGNO ( dest ) ) || GET_CODE ( src ) != COMPARE ) return false ; cond = NULL_RTX ; op0 = & XEXP ( src , 0 ) ; op1 = & XEXP ( src , 1 ) ; } else return false ; if ( ! REG_P ( * op0 ) || ! REG_P ( * op1 ) ) return false ; if ( GET_MODE_CLASS ( GET_MODE ( * op0 ) ) != MODE_INT ) return false ; prev_insn = prev_active_insn ( insn ) ; if ( prev_insn != NULL_RTX && INSN_P ( prev_insn ) && reg_referenced_p ( * op1 , PATTERN ( prev_insn ) ) ) s390_swap_cmp ( cond , op0 , op1 , insn ) ; next_insn = next_active_insn ( insn ) ; if ( next_insn != NULL_RTX && INSN_P ( next_insn ) && s390_non_addr_reg_read_p ( * op1 , next_insn ) ) { if ( prev_insn != NULL_RTX && INSN_P ( prev_insn ) && s390_non_addr_reg_read_p ( * op0 , prev_insn ) ) { if ( REGNO ( * op1 ) == 0 ) emit_insn_after ( gen_nop1 ( ) , insn ) ; else emit_insn_after ( gen_nop ( ) , insn ) ; insn_added_p = true ; } else s390_swap_cmp ( cond , op0 , op1 , insn ) ; } return insn_added_p ; } </s>

On z10 , instructions of the compare-and-branch family have the property to access the register occurring as second operand with its bits complemented . If such a compare is grouped with a second instruction that accesses the same register non-complemented , and if that register 's value is delivered via a bypass , then the pipeline recycles , thereby causing significant performance decline . This function locates such situations and exchanges the two operands of the compare . The function return true whenever it added an insn .


<s> static void c6x_gen_bundles ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * insn , * next ; rtx_insn * slot [ 15 ] ; int n_filled = 0 ; int first_slot = 0 ; for ( insn = BB_HEAD ( bb ) ; ; insn = next ) { int at_end ; rtx delete_this = NULL_RTX ; if ( NONDEBUG_INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) { first_slot ++ ; if ( n_filled ) { memmove ( & slot [ 1 ] , & slot [ 0 ] , n_filled * sizeof ( slot [ 0 ] ) ) ; } if ( ! shadow_p ( insn ) ) { PUT_MODE ( insn , TImode ) ; if ( n_filled ) PUT_MODE ( slot [ 1 ] , VOIDmode ) ; } n_filled ++ ; slot [ 0 ] = insn ; } else { slot [ n_filled ++ ] = insn ; } } next = NEXT_INSN ( insn ) ; while ( next && insn != BB_END ( bb ) && ! ( NONDEBUG_INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) != USE && GET_CODE ( PATTERN ( next ) ) != CLOBBER ) ) { insn = next ; next = NEXT_INSN ( insn ) ; } at_end = insn == BB_END ( bb ) ; if ( delete_this == NULL_RTX && ( at_end || ( GET_MODE ( next ) == TImode && ! ( shadow_p ( next ) && CALL_P ( next ) ) ) ) ) { if ( n_filled >= 2 ) gen_one_bundle ( slot , n_filled , first_slot ) ; n_filled = 0 ; first_slot = 0 ; } if ( at_end ) break ; } } } </s>

Move all parallel instructions into SEQUENCEs , so that no subsequent passes try to insert labels in the middle .


<s> static void merge_unit_reqs ( unit_req_table reqs ) { int side ; for ( side = 0 ; side < 2 ; side ++ ) { int d = reqs [ side ] [ UNIT_REQ_D ] ; int l = reqs [ side ] [ UNIT_REQ_L ] ; int s = reqs [ side ] [ UNIT_REQ_S ] ; int dl = reqs [ side ] [ UNIT_REQ_DL ] ; int ls = reqs [ side ] [ UNIT_REQ_LS ] ; int ds = reqs [ side ] [ UNIT_REQ_DS ] ; reqs [ side ] [ UNIT_REQ_DL ] += d ; reqs [ side ] [ UNIT_REQ_DL ] += l ; reqs [ side ] [ UNIT_REQ_DS ] += d ; reqs [ side ] [ UNIT_REQ_DS ] += s ; reqs [ side ] [ UNIT_REQ_LS ] += l ; reqs [ side ] [ UNIT_REQ_LS ] += s ; reqs [ side ] [ UNIT_REQ_DLS ] += ds + dl + ls + d + l + s ; } } </s>

Update the table REQS by merging more specific unit reservations into more general ones , i.e . counting ( for example ) UNIT_REQ_D also in UNIT_REQ_DL , DS , and DLS .


<s> static tree ix86_build_builtin_va_list ( void ) { tree ret = ix86_build_builtin_va_list_abi ( ix86_abi ) ; if ( TARGET_64BIT ) { tree t ; if ( ix86_abi == MS_ABI ) { t = ix86_build_builtin_va_list_abi ( SYSV_ABI ) ; if ( TREE_CODE ( t ) != RECORD_TYPE ) t = build_variant_type_copy ( t ) ; sysv_va_list_type_node = t ; } else { t = ret ; if ( TREE_CODE ( t ) != RECORD_TYPE ) t = build_variant_type_copy ( t ) ; sysv_va_list_type_node = t ; } if ( ix86_abi != MS_ABI ) { t = ix86_build_builtin_va_list_abi ( MS_ABI ) ; if ( TREE_CODE ( t ) != RECORD_TYPE ) t = build_variant_type_copy ( t ) ; ms_va_list_type_node = t ; } else { t = ret ; if ( TREE_CODE ( t ) != RECORD_TYPE ) t = build_variant_type_copy ( t ) ; ms_va_list_type_node = t ; } } return ret ; } </s>


<s> const MCPhysReg * VERegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { switch ( MF -> getFunction ( ) . getCallingConv ( ) ) { default : return CSR_SaveList ; case CallingConv :: PreserveAll : return CSR_preserve_all_SaveList ; } } </s>


<s> AMDGPUSubtarget & AMDGPUSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef GPU , StringRef FS ) { SmallString < 256 > FullFS ( "+promote-alloca,+fp64-denormals," ) ; FullFS += FS ; if ( GPU == "" && TT . getArch ( ) == Triple :: amdgcn ) GPU = "SI" ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ; FP64Denormals = false ; } return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .

AMDGPU AMDGPU AMDGPU 256 "+promote-alloca,+fp64-denormals," "" "SI" AMDGPU


<s> enum h8sx_shift_type h8sx_classify_shift ( enum machine_mode mode , enum rtx_code code , rtx op ) { if ( ! TARGET_H8300SX ) return H8SX_SHIFT_NONE ; switch ( code ) { case ASHIFT : case LSHIFTRT : if ( GET_CODE ( op ) != CONST_INT ) return H8SX_SHIFT_BINARY ; if ( INTVAL ( op ) <= 0 || INTVAL ( op ) >= GET_MODE_BITSIZE ( mode ) ) return H8SX_SHIFT_NONE ; if ( exact_log2 ( INTVAL ( op ) ) >= 0 ) return H8SX_SHIFT_UNARY ; return H8SX_SHIFT_BINARY ; case ASHIFTRT : if ( op == const1_rtx || op == const2_rtx ) return H8SX_SHIFT_UNARY ; return H8SX_SHIFT_NONE ; case ROTATE : if ( GET_CODE ( op ) == CONST_INT && ( INTVAL ( op ) == 1 || INTVAL ( op ) == 2 || INTVAL ( op ) == GET_MODE_BITSIZE ( mode ) - 2 || INTVAL ( op ) == GET_MODE_BITSIZE ( mode ) - 1 ) ) return H8SX_SHIFT_UNARY ; return H8SX_SHIFT_NONE ; default : return H8SX_SHIFT_NONE ; } } </s>

Classify a shift with the given mode and code . OP is the shift amount .


<s> void TL45PassConfig :: addPreEmitPass ( ) { } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
static
tree
avr_handle_progmem_attribute
(
tree
*
node
,
tree
name
,
tree
args
ATTRIBUTE_UNUSED
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
if
(
DECL_P
(
*
node
)
)
{
if
(
TREE_CODE
(
*
node
)
==
TYPE_DECL
)
{
tree
type
=
TREE_TYPE
(
*
node
)
;
tree
attr
=
tree_cons
(
name
,
args
,
TYPE_ATTRIBUTES
(
type
)
)
;
tree
newtype
=
build_type_attribute_variant
(
type
,
attr
)
;
TYPE_MAIN_VARIANT
(
newtype
)
=
TYPE_MAIN_VARIANT
(
type
)
;
TREE_TYPE
(
*
node
)
=
newtype
;
*
no_add_attrs
=
true
;
}
else
if
(
TREE_STATIC
(
*
node
)
||
DECL_EXTERNAL
(
*
node
)
)
{
*
no_add_attrs
=
false
;
}
else
{
warning
(
OPT_Wattributes
,
"%qE attribute ignored"
,
name
)
;
*
no_add_attrs
=
true
;
}
}
return
NULL_TREE
;
}
</s>

Handle a `` progmem '' attribute ; arguments as in struct attribute_spec.handler .


<s> rtx loongarch_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ATTRIBUTE_UNUSED ) { tree fndecl ; unsigned int fcode , avail ; const struct loongarch_builtin_description * d ; fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , 0 ) ; fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; gcc_assert ( fcode < ARRAY_SIZE ( loongarch_builtins ) ) ; d = & loongarch_builtins [ fcode ] ; avail = d -> avail ( ) ; gcc_assert ( avail != 0 ) ; switch ( d -> builtin_type ) { case LARCH_BUILTIN_DIRECT : return loongarch_expand_builtin_direct ( d -> icode , target , exp , true ) ; case LARCH_BUILTIN_DIRECT_NO_TARGET : return loongarch_expand_builtin_direct ( d -> icode , target , exp , false ) ; } gcc_unreachable ( ) ; } </s>


<s> unsigned FPGATTIImpl :: getNumberOfRegisters ( bool Vector ) { return std :: numeric_limits < unsigned > :: max ( ) >> 2 ; } </s>


"operation not permitted on type %<bfloat16_t%>"

Return the diagnostic message string if the unary operation OP is not permitted on TYPE , NULL otherwise .


<s> bool HexagonPassConfig :: addInstSelector ( ) { addPass ( createHexagonRemoveExtendOps ( getHexagonTargetMachine ( ) ) ) ; addPass ( createHexagonISelDag ( getHexagonTargetMachine ( ) ) ) ; addPass ( createHexagonPeephole ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon