<s> static void register_tuple_type ( unsigned int num_vectors , vector_type_index type ) { tree tuple_type = lang_hooks . types . make_type ( RECORD_TYPE ) ; tree vector_type = acle_vector_types [ 0 ] [ type ] ; tree array_type = build_array_type_nelts ( vector_type , num_vectors ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( array_type ) ) && TYPE_MODE_RAW ( array_type ) == TYPE_MODE ( array_type ) && TYPE_ALIGN ( array_type ) == 128 ) ; tree field = build_decl ( input_location , FIELD_DECL , get_identifier ( "__val" ) , array_type ) ; DECL_FIELD_CONTEXT ( field ) = tuple_type ; TYPE_FIELDS ( tuple_type ) = field ; add_sve_type_attribute ( tuple_type , num_vectors , 0 , NULL ) ; make_type_sizeless ( tuple_type ) ; layout_type ( tuple_type ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( tuple_type ) ) && TYPE_MODE_RAW ( tuple_type ) == TYPE_MODE ( tuple_type ) && TYPE_ALIGN ( tuple_type ) == 128 ) ; char buffer [ sizeof ( "svbfloat16x4_t" ) ] ; const char * vector_type_name = vector_types [ type ] . acle_name ; snprintf ( buffer , sizeof ( buffer ) , "%.*sx%d_t" , ( int ) strlen ( vector_type_name ) - 2 , vector_type_name , num_vectors ) ; tree decl = build_decl ( input_location , TYPE_DECL , get_identifier ( buffer ) , tuple_type ) ; TYPE_NAME ( tuple_type ) = decl ; TYPE_STUB_DECL ( tuple_type ) = decl ; lang_hooks . decls . pushdecl ( decl ) ; DECL_ORIGINAL_TYPE ( decl ) = NULL_TREE ; acle_vector_types [ num_vectors - 1 ] [ type ] = tuple_type ; } </s>

Register the tuple type that contains NUM_VECTORS vectors of type TYPE .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static bool save_local_or_in_reg_p ( unsigned int regno , int leaf_function ) { if ( ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ; if ( regno == PIC_OFFSET_TABLE_REGNUM && crtl -> uses_pic_offset_table ) return true ; if ( crtl -> accesses_prior_frames && ( regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM ) ) return true ; return false ; } </s>

Return whether REGNO , a local or in register , must be saved/restored .


<s> static void register_vector_type ( vector_type_index type ) { if ( vector_types [ type ] . requires_float && ! TARGET_HAVE_MVE_FLOAT ) return ; tree vectype = abi_vector_types [ type ] ; tree id = get_identifier ( vector_types [ type ] . acle_name ) ; tree decl = build_decl ( input_location , TYPE_DECL , id , vectype ) ; decl = lang_hooks . decls . pushdecl ( decl ) ; if ( decl && TREE_CODE ( decl ) == TYPE_DECL && TREE_TYPE ( decl ) != error_mark_node && TYPE_MAIN_VARIANT ( TREE_TYPE ( decl ) ) == vectype ) vectype = TREE_TYPE ( decl ) ; acle_vector_types [ 0 ] [ type ] = vectype ; } </s>

Register vector type TYPE under its risv_vector.h name .


<s>
bool
MSP430InstrInfo
::
analyzeBranch
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
*
&
TBB
,
MachineBasicBlock
*
&
FBB
,
SmallVectorImpl
<
MachineOperand
>
&
Cond
,
bool
AllowModify
)
const
{
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugInstr
(
)
)
continue
;
if
(
!
isUnpredicatedTerminator
(
*
I
)
)
break
;
if
(
!
I
->
isBranch
(
)
)
return
true
;
if
(
I
->
getOpcode
(
)
==
MSP430
::
Br
||
I
->
getOpcode
(
)
==
MSP430
::
Bm
)
return
true
;
if
(
I
->
getOpcode
(
)
==
MSP430
::
JMP
)
{
if
(
!
AllowModify
)
{
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
while
(
std
::
next
(
I
)
!=
MBB
.
end
(
)
)
std
::
next
(
I
)
->
eraseFromParent
(
)
;
Cond
.
clear
(
)
;
FBB
=
nullptr
;
if
(
MBB
.
isLayoutSuccessor
(
I
->
getOperand
(
0
)
.
getMBB
(
)
)
)
{
TBB
=
nullptr
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
continue
;
}
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
continue
;
}
assert
(
I
->
getOpcode
(
)
==
MSP430
::
JCC
&&
"Invalid conditional branch"
)
;
MSP430CC
::
CondCodes
BranchCode
=
static_cast
<
MSP430CC
::
CondCodes
>
(
I
->
getOperand
(
1
)
.
getImm
(
)
)
;
if
(
BranchCode
==
MSP430CC
::
COND_INVALID
)
return
true
;
if
(
Cond
.
empty
(
)
)
{
FBB
=
TBB
;
TBB
=
I
->
getOperand
(
0
)
.
getMBB
(
)
;
Cond
.
push_back
(
MachineOperand
::
CreateImm
(
BranchCode
)
)
;
continue
;
}
assert
(
Cond
.
size
(
)
==
1
)
;
assert
(
TBB
)
;
if
(
TBB
!=
I
->
getOperand
(
0
)
.
getMBB
(
)
)
return
true
;
MSP430CC
::
CondCodes
OldBranchCode
=
(
MSP430CC
::
CondCodes
)
Cond
[
0
]
.
getImm
(
)
;
if
(
OldBranchCode
==
BranchCode
)
continue
;
return
true
;
}
return
false
;
}
</s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static bool mips_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 ) { if ( lra_in_progress && ( class1 == NO_REGS || class2 == NO_REGS ) ) return false ; if ( ( ( class1 == FP_REGS ) != ( class2 == FP_REGS ) ) && ( ( TARGET_FLOATXX && ! ISA_HAS_MXHC1 ) || TARGET_O32_FP64A_ABI ) && GET_MODE_SIZE ( mode ) >= 8 ) return true ; return false ; } </s>


<s> static void nds32_conditional_register_usage ( void ) { int regno ; if ( TARGET_LINUX_ABI ) fixed_regs [ TP_REGNUM ] = 1 ; if ( TARGET_HARD_FLOAT ) { for ( regno = NDS32_FIRST_FPR_REGNUM ; regno <= NDS32_LAST_FPR_REGNUM ; regno ++ ) { fixed_regs [ regno ] = 0 ; if ( regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS ) call_used_regs [ regno ] = 1 ; else if ( regno >= NDS32_FIRST_FPR_REGNUM + 22 && regno < NDS32_FIRST_FPR_REGNUM + 48 ) call_used_regs [ regno ] = 1 ; else call_used_regs [ regno ] = 0 ; } } else if ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) { for ( regno = NDS32_FIRST_FPR_REGNUM ; regno <= NDS32_LAST_FPR_REGNUM ; regno ++ ) fixed_regs [ regno ] = 0 ; } } </s>


"WebAssembly does not use MCFixupKindInfo flags"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> static void iq2000_annotate_frame_insn ( rtx insn , rtx dwarf_pattern ) { RTX_FRAME_RELATED_P ( insn ) = 1 ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf_pattern , REG_NOTES ( insn ) ) ; } </s>

Make INSN frame related and note that it performs the frame-related operation DWARF_PATTERN .


<s> bool TMS320C64XInstrInfo :: isPredicated ( const MachineInstr * MI ) const { const int pred_idx = MI -> findFirstPredOperandIdx ( ) ; if ( pred_idx == - 1 ) return false ; const int pred_val = MI -> getOperand ( pred_idx ) . getImm ( ) ; if ( pred_val == - 1 ) return false ; return true ; } </s>

Returns true if the instruction is already predicated .


<s> static void frv_io_handle_set ( rtx x , rtx pat ATTRIBUTE_UNUSED , void * data ) { HARD_REG_SET * set = data ; unsigned int regno ; if ( REG_P ( x ) ) FOR_EACH_REGNO ( regno , x ) CLEAR_HARD_REG_BIT ( * set , regno ) ; } </s>

A note_stores callback for which DATA points to a HARD_REG_SET . Remove every modified register from the set .


<s> bool cris_base_or_autoincr_p ( const_rtx x , bool strict ) { return ( cris_base_p ( x , strict ) || ( GET_CODE ( x ) == POST_INC && cris_base_p ( XEXP ( x , 0 ) , strict ) ) ) ; } </s>

True if X is a valid base register with or without autoincrement .


<s> bool PPCFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const PPCInstrInfo & TII = * static_cast < const PPCInstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == PPC :: VRSAVE && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = PPC :: CR2 <= Reg && Reg <= PPC :: CR4 ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ; continue ; } if ( IsCRField ) { PPCFunctionInfo * FuncInfo = MF -> getInfo < PPCFunctionInfo > ( ) ; if ( Subtarget . isPPC64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( PPC :: MFCR ) , PPC :: R12 ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( PPC :: STW ) ) . addReg ( PPC :: R12 , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

PowerPC PPC PPC PPC 0 PPC::VRSAVE PPC::CR2 PPC::CR4 PPC PPC PPC PPC::MFCR PPC::R12 PPC::STW PPC::R12


<s> static int visium_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { enum attr_type attr_type ; if ( REG_NOTE_KIND ( link ) == REG_DEP_TRUE ) { if ( ! reload_completed && recog_memoized ( insn ) >= 0 && get_attr_type ( insn ) == TYPE_CMP ) { rtx pat = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pat ) == SET ) ; rtx src = SET_SRC ( pat ) ; if ( GET_CODE ( src ) == IF_THEN_ELSE && XEXP ( XEXP ( src , 0 ) , 1 ) == const0_rtx && recog_memoized ( dep_insn ) >= 0 ) { enum attr_type dep_attr_type = get_attr_type ( dep_insn ) ; if ( dep_attr_type == TYPE_LOGIC || ( dep_attr_type == TYPE_ARITH && visium_noov_operator ( XEXP ( src , 0 ) , GET_MODE ( XEXP ( src , 0 ) ) ) ) ) return 0 ; } } return cost ; } if ( recog_memoized ( insn ) < 0 ) return 0 ; attr_type = get_attr_type ( insn ) ; if ( REG_NOTE_KIND ( link ) == REG_DEP_ANTI ) { if ( attr_type == TYPE_REG_FP && visium_cpu == PROCESSOR_GR5 ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return 0 ; if ( reg_mentioned_p ( SET_DEST ( pat ) , SET_SRC ( dep_pat ) ) ) { if ( recog_memoized ( dep_insn ) < 0 ) return 0 ; switch ( get_attr_type ( dep_insn ) ) { case TYPE_FDIV : case TYPE_FSQRT : case TYPE_FTOI : case TYPE_ITOF : case TYPE_FP : case TYPE_FMOVE : return insn_default_latency ( dep_insn ) ; default : return 0 ; } } } else if ( attr_type == TYPE_RET && visium_cpu == PROCESSOR_GR6 ) { rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( dep_pat ) == SET && REG_P ( SET_DEST ( dep_pat ) ) && REGNO ( SET_DEST ( dep_pat ) ) == LINK_REGNUM ) return 8 ; } return 0 ; } else if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) { if ( attr_type == TYPE_REG_FP && visium_cpu == PROCESSOR_GR5 ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return 0 ; if ( reg_mentioned_p ( SET_DEST ( pat ) , SET_DEST ( dep_pat ) ) ) { if ( recog_memoized ( dep_insn ) < 0 ) return 0 ; switch ( get_attr_type ( dep_insn ) ) { case TYPE_FDIV : case TYPE_FSQRT : case TYPE_FTOI : case TYPE_ITOF : case TYPE_FP : case TYPE_FMOVE : return insn_default_latency ( dep_insn ) ; default : return 0 ; } } } return 0 ; } return 0 ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK of INSN on DEP_INSN . COST is the current cost .


<s> static inline int mov_insn_alignment_mask ( machine_mode mode , bool consider_sh2a ) { const int mov_insn_sz = mov_insn_size ( mode , consider_sh2a ) ; return mov_insn_sz > 0 ? ( mov_insn_sz - 1 ) : 0 ; } </s>

Determine the alignment mask for a move insn of the specified mode .


<s> TargetPassConfig * SPUTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SPUPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


"rs6000_builtin_md_vectorized_function (%s, %s, %s)\n"


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; addPass ( createIndirectBrExpandPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static pad_direction aarch64_function_arg_padding ( machine_mode mode , const_tree type ) { if ( ! BYTES_BIG_ENDIAN ) return PAD_UPWARD ; if ( type ? ( INTEGRAL_TYPE_P ( type ) || SCALAR_FLOAT_TYPE_P ( type ) || POINTER_TYPE_P ( type ) ) : ( SCALAR_INT_MODE_P ( mode ) || SCALAR_FLOAT_MODE_P ( mode ) ) ) return PAD_DOWNWARD ; return PAD_UPWARD ; } </s>

Implement TARGET_FUNCTION_ARG_PADDING . Small aggregate types are placed in the lowest memory address . The related parameter passing rules are B.4 , C.3 , C.5 and C.14 .


<s> bool arm_frame_pointer_required ( void ) { if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ( ) ) return true ; if ( ! IS_INTERRUPT ( arm_current_func_type ( ) ) && flag_stack_check == STATIC_BUILTIN_STACK_CHECK && arm_except_unwind_info ( & global_options ) == UI_TARGET && cfun -> can_throw_non_call_exceptions ) { HOST_WIDE_INT size = get_frame_size ( ) ; if ( size <= 0 ) return false ; if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { size += 32 * UNITS_PER_WORD ; if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) return true ; } else return true ; } return false ; } </s>


<s> static FunctionType * getType ( LLVMContext & Context , unsigned id ) { Type * ResultTy = NULL ; std :: vector < Type * > ArgTys ; bool IsVarArg = false ; return FunctionType :: get ( ResultTy , ArgTys , IsVarArg ) ; } </s>

Overload to return most specific vector type .


"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "


<s> unsigned SITargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { const unsigned PrefAlign = TargetLowering :: getPrefLoopAlignment ( ML ) ; const unsigned CacheLineAlign = 6 ; if ( ! ML || DisableLoopAlignment || ( getSubtarget ( ) -> getGeneration ( ) < AMDGPUSubtarget :: GFX10 ) || getSubtarget ( ) -> hasInstFwdPrefetchBug ( ) ) return PrefAlign ; const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; const MachineBasicBlock * Header = ML -> getHeader ( ) ; if ( Header -> getAlignment ( ) != PrefAlign ) return Header -> getAlignment ( ) ; unsigned LoopSize = 0 ; for ( const MachineBasicBlock * MBB : ML -> blocks ( ) ) { if ( MBB != Header ) LoopSize += ( 1 << MBB -> getAlignment ( ) ) / 2 ; for ( const MachineInstr & MI : * MBB ) { LoopSize += TII -> getInstSizeInBytes ( MI ) ; if ( LoopSize > 192 ) return PrefAlign ; } } if ( LoopSize <= 64 ) return PrefAlign ; if ( LoopSize <= 128 ) return CacheLineAlign ; for ( MachineLoop * P = ML -> getParentLoop ( ) ; P ; P = P -> getParentLoop ( ) ) { if ( MachineBasicBlock * Exit = P -> getExitBlock ( ) ) { auto I = Exit -> getFirstNonDebugInstr ( ) ; if ( I != Exit -> end ( ) && I -> getOpcode ( ) == AMDGPU :: S_INST_PREFETCH ) return CacheLineAlign ; } } MachineBasicBlock * Pre = ML -> getLoopPreheader ( ) ; MachineBasicBlock * Exit = ML -> getExitBlock ( ) ; if ( Pre && Exit ) { BuildMI ( * Pre , Pre -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_INST_PREFETCH ) ) . addImm ( 1 ) ; BuildMI ( * Exit , Exit -> getFirstNonDebugInstr ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_INST_PREFETCH ) ) . addImm ( 2 ) ; } return CacheLineAlign ; } </s>


<s> bool HSAILIntrinsicInfo :: isOverloaded ( unsigned IntrID ) const { if ( ! IntrID ) return false ; unsigned id = IntrID - Intrinsic :: num_intrinsics + 1 ; } </s>

Returns true if the intrinsic can be overloaded .


<s> int nds32_can_use_bclr_p ( int ival ) { int one_bit_count ; one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ~ ival ) ) ; return ( TARGET_PERF_EXT && ( one_bit_count == 1 ) ) ; } </s>

Function to check if 'bclr ' instruction can be used with IVAL .


<s> MachineMemOperand :: Flags SITargetLowering :: getTargetMMOFlags ( const Instruction & I ) const { if ( I . getMetadata ( "amdgpu.noclobber" ) ) return MONoClobber ; return MachineMemOperand :: MONone ; } </s>

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them .


<s> virtual const PatmosSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"Assembler does not support -mabi=ilp32"


<s>
static
void
alpha_output_function_end_prologue
(
FILE
*
file
)
{
if
(
TARGET_ABI_UNICOSMK
)
;
else
if
(
TARGET_ABI_OPEN_VMS
)
fputs
(
"\t.prologue\n"
,
file
)
;
else
if
(
TARGET_ABI_WINDOWS_NT
)
fputs
(
"\t.prologue 0\n"
,
file
)
;
else
if
(
!
flag_inhibit_size_directive
)
fprintf
(
file
,
"\t.prologue %d\n"
,
alpha_function_needs_gp
||
current_function_is_thunk
)
;
}
</s>

Emit the .prologue note at the scheduled end of the prologue .

alpha
"\t.prologue\n"
"\t.prologue 0\n"
"\t.prologue %d\n"


<s> bool isFpMLxInstruction ( unsigned Opcode ) const { return MLxEntryMap . count ( Opcode ) ; } </s>

isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to .


<s> static void aarch64_restore_callee_saves ( machine_mode mode , poly_int64 start_offset , unsigned start , unsigned limit , bool skip_wb , rtx * cfi_ops ) { rtx base_rtx = stack_pointer_rtx ; unsigned regno ; unsigned regno2 ; poly_int64 offset ; for ( regno = aarch64_next_callee_save ( start , limit ) ; regno <= limit ; regno = aarch64_next_callee_save ( regno + 1 , limit ) ) { if ( cfun -> machine -> reg_is_wrapped_separately [ regno ] ) continue ; rtx reg , mem ; if ( skip_wb && ( regno == cfun -> machine -> frame . wb_candidate1 || regno == cfun -> machine -> frame . wb_candidate2 ) ) continue ; reg = gen_rtx_REG ( mode , regno ) ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno ] ; mem = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; regno2 = aarch64_next_callee_save ( regno + 1 , limit ) ; if ( regno2 <= limit && ! cfun -> machine -> reg_is_wrapped_separately [ regno2 ] && ( ( cfun -> machine -> frame . reg_offset [ regno ] + UNITS_PER_WORD ) == cfun -> machine -> frame . reg_offset [ regno2 ] ) ) { rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; rtx mem2 ; offset = start_offset + cfun -> machine -> frame . reg_offset [ regno2 ] ; mem2 = gen_frame_mem ( mode , plus_constant ( Pmode , base_rtx , offset ) ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg2 , * cfi_ops ) ; regno = regno2 ; } else emit_move_insn ( reg , mem ) ; * cfi_ops = alloc_reg_note ( REG_CFA_RESTORE , reg , * cfi_ops ) ; } } </s>

Emit code to restore the callee registers of mode MODE from register number START up to and including LIMIT . Restore from the stack offset START_OFFSET , skipping any write-back candidates if SKIP_WB is true . Write the appropriate REG_CFA_RESTORE notes into CFI_OPS .


<s>
static
tree
arc_handle_uncached_attribute
(
tree
*
node
,
tree
name
,
tree
args
,
int
flags
ATTRIBUTE_UNUSED
,
bool
*
no_add_attrs
)
{
if
(
DECL_P
(
*
node
)
&&
TREE_CODE
(
*
node
)
!=
TYPE_DECL
)
{
error
(
"%qE attribute only applies to types"
,
name
)
;
*
no_add_attrs
=
true
;
}
else
if
(
args
)
{
warning
(
OPT_Wattributes
,
"argument of %qE attribute ignored"
,
name
)
;
}
return
NULL_TREE
;
}
</s>

arc
"%qE attribute only applies to types"
"argument of %qE attribute ignored"


<s> bool AArch64FastISel :: optimizeSelect ( const SelectInst * SI ) { if ( ! SI -> getType ( ) -> isIntegerTy ( 1 ) ) return false ; const Value * Src1Val , * Src2Val ; unsigned Opc = 0 ; bool NeedExtraOp = false ; if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getTrueValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getFalseValue ( ) ; Opc = AArch64 :: ORRWrr ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getFalseValue ( ) ; Src2Val = SI -> getCondition ( ) ; Opc = AArch64 :: BICWrr ; } } else if ( auto * CI = dyn_cast < ConstantInt > ( SI -> getFalseValue ( ) ) ) { if ( CI -> isOne ( ) ) { Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ORRWrr ; NeedExtraOp = true ; } else { assert ( CI -> isZero ( ) ) ; Src1Val = SI -> getCondition ( ) ; Src2Val = SI -> getTrueValue ( ) ; Opc = AArch64 :: ANDWrr ; } } if ( ! Opc ) return false ; Register Src1Reg = getRegForValue ( Src1Val ) ; if ( ! Src1Reg ) return false ; Register Src2Reg = getRegForValue ( Src2Val ) ; if ( ! Src2Reg ) return false ; if ( NeedExtraOp ) Src1Reg = emitLogicalOp_ri ( ISD :: XOR , MVT :: i32 , Src1Reg , 1 ) ; Register ResultReg = fastEmitInst_rr ( Opc , & AArch64 :: GPR32RegClass , Src1Reg , Src2Reg ) ; updateValueMap ( SI , ResultReg ) ; return true ; } </s>

Given a select instruction that was understood by analyzeSelect and returned Optimizable = true , attempt to optimize MI by merging it with one of its operands .


<s> virtual const ARMBaseRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool AArch64InstrInfo :: isAssociativeAndCommutative ( const MachineInstr & Inst ) const { switch ( Inst . getOpcode ( ) ) { case AArch64 :: FADDDrr : case AArch64 :: FADDSrr : case AArch64 :: FADDv2f32 : case AArch64 :: FADDv2f64 : case AArch64 :: FADDv4f32 : case AArch64 :: FMULDrr : case AArch64 :: FMULSrr : case AArch64 :: FMULX32 : case AArch64 :: FMULX64 : case AArch64 :: FMULXv2f32 : case AArch64 :: FMULXv2f64 : case AArch64 :: FMULXv4f32 : case AArch64 :: FMULv2f32 : case AArch64 :: FMULv2f64 : case AArch64 :: FMULv4f32 : return Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .


<s> bool SITargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { if ( GA -> getAddressSpace ( ) != AMDGPUAS :: GLOBAL_ADDRESS ) return false ; return TargetLowering :: isOffsetFoldingLegal ( GA ) ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { return VT . isScalarInteger ( ) ; } </s>

Use bitwise logic to make pairs of compares more efficient .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; initialize ( MF ) ; return simplifyCode ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static int n_pregs_to_save ( bool is_inthandler ) { unsigned i ; for ( i = REG_P0 ; i <= REG_P5 ; i ++ ) if ( ( regs_ever_live [ i ] && ( is_inthandler || ! call_used_regs [ i ] ) ) || ( i == PIC_OFFSET_TABLE_REGNUM && ( current_function_uses_pic_offset_table || ( TARGET_ID_SHARED_LIBRARY && ! current_function_is_leaf ) ) ) ) return REG_P5 - i + 1 ; return 0 ; } </s>

Like n_dregs_to_save , but compute number of PREGS to save .


<s> static void alpha_output_mi_thunk_osf ( FILE * file , tree thunk_fndecl ATTRIBUTE_UNUSED , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { HOST_WIDE_INT hi , lo ; rtx this , insn , funexp ; reset_block_changes ( ) ; emit_insn ( gen_prologue_ldgp ( ) ) ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ) this = gen_rtx_REG ( Pmode , 17 ) ; else this = gen_rtx_REG ( Pmode , 16 ) ; lo = ( ( delta & 0xffff ) ^ 0x8000 ) - 0x8000 ; hi = ( ( ( delta - lo ) & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; if ( hi + lo == delta ) { if ( hi ) emit_insn ( gen_adddi3 ( this , this , GEN_INT ( hi ) ) ) ; if ( lo ) emit_insn ( gen_adddi3 ( this , this , GEN_INT ( lo ) ) ) ; } else { rtx tmp = alpha_emit_set_long_const ( gen_rtx_REG ( Pmode , 0 ) , delta , - ( delta < 0 ) ) ; emit_insn ( gen_adddi3 ( this , this , tmp ) ) ; } if ( vcall_offset ) { rtx tmp , tmp2 ; tmp = gen_rtx_REG ( Pmode , 0 ) ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , this ) ) ; lo = ( ( vcall_offset & 0xffff ) ^ 0x8000 ) - 0x8000 ; hi = ( ( ( vcall_offset - lo ) & 0xffffffff ) ^ 0x80000000 ) - 0x80000000 ; if ( hi + lo == vcall_offset ) { if ( hi ) emit_insn ( gen_adddi3 ( tmp , tmp , GEN_INT ( hi ) ) ) ; } else { tmp2 = alpha_emit_set_long_const ( gen_rtx_REG ( Pmode , 1 ) , vcall_offset , - ( vcall_offset < 0 ) ) ; emit_insn ( gen_adddi3 ( tmp , tmp , tmp2 ) ) ; lo = 0 ; } if ( lo ) tmp2 = gen_rtx_PLUS ( Pmode , tmp , GEN_INT ( lo ) ) ; else tmp2 = tmp ; emit_move_insn ( tmp , gen_rtx_MEM ( Pmode , tmp2 ) ) ; emit_insn ( gen_adddi3 ( this , this , tmp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; insn_locators_initialize ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; } </s>

Emit a tail call to FUNCTION after adjusting THIS by DELTA . In order to avoid the hordes of differences between generated code with and without TARGET_EXPLICIT_RELOCS , and to avoid duplicating lots of code loading up large constants , generate rtl and emit it instead of going straight to text . Not sure why this idea has n't been explored before ...


"\n******** JVM Store/Dup insertion ********\n"


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static rtx nds32_gen_dup_4_byte_to_word_value ( rtx value ) { rtx value4word = gen_reg_rtx ( SImode ) ; gcc_assert ( GET_MODE ( value ) == QImode || CONST_INT_P ( value ) ) ; if ( CONST_INT_P ( value ) ) { unsigned HOST_WIDE_INT val = UINTVAL ( value ) & GET_MODE_MASK ( QImode ) ; rtx new_val = gen_int_mode ( val | ( val << 8 ) | ( val << 16 ) | ( val << 24 ) , SImode ) ; emit_move_insn ( value4word , new_val ) ; } else { rtx tmp1 , tmp2 , tmp3 , tmp4 , final_value ; tmp1 = expand_binop ( SImode , and_optab , value , gen_int_mode ( 0xff , SImode ) , NULL_RTX , 0 , OPTAB_WIDEN ) ; tmp2 = expand_binop ( SImode , ashl_optab , tmp1 , gen_int_mode ( 8 , SImode ) , NULL_RTX , 0 , OPTAB_WIDEN ) ; tmp3 = expand_binop ( SImode , ior_optab , tmp1 , tmp2 , NULL_RTX , 0 , OPTAB_WIDEN ) ; tmp4 = expand_binop ( SImode , ashl_optab , tmp3 , gen_int_mode ( 16 , SImode ) , NULL_RTX , 0 , OPTAB_WIDEN ) ; final_value = expand_binop ( SImode , ior_optab , tmp3 , tmp4 , NULL_RTX , 0 , OPTAB_WIDEN ) ; emit_move_insn ( value4word , final_value ) ; } return value4word ; } </s>

Auxiliary function for expand setmem pattern .


"Basic block should contain at least a RET but is empty"


"function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, "

Advance the argument of type TYPE and mode MODE to the next argument position in CUM .


<s> TargetLoweringBase :: LegalizeTypeAction X86TargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( VT . getVectorNumElements ( ) != 1 && VT . getVectorElementType ( ) != MVT :: i1 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> void SystemZFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + SystemZMC :: CallFrameSize ) ; int64_t MaxArgOffset = SystemZMC :: CallFrameSize ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != 0 ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= 0 ) { int64_t ArgOffset = SystemZMC :: CallFrameSize + MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < 12 > ( MaxReach ) ) { RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( 8 , 8 , false ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static unsigned int compute_vrsave_mask ( void ) { unsigned int i , mask = 0 ; if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) mask |= 0xFFF ; for ( i = FIRST_ALTIVEC_REGNO ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( df_regs_ever_live_p ( i ) ) mask |= ALTIVEC_REG_BIT ( i ) ; if ( mask == 0 ) return mask ; for ( i = ALTIVEC_ARG_MIN_REG ; i < ( unsigned ) crtl -> args . info . vregno ; i ++ ) mask &= ~ ALTIVEC_REG_BIT ( i ) ; { bool yes = false ; diddle_return_value ( is_altivec_return_reg , & yes ) ; if ( yes ) mask &= ~ ALTIVEC_REG_BIT ( ALTIVEC_ARG_RETURN ) ; } return mask ; } </s>

Return a 32-bit mask of the AltiVec registers we need to set in VRSAVE . Bit n of the return value is 1 if Vn is live . The MSB in the 32-bit word is 0 .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


"Unable to get the legal offset for nil instruction."

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s> static hsa_status_t get_kernarg_region ( hsa_region_t region , void * data __attribute__ ( ( unused ) ) ) { return get_memory_region ( region , & kernargs_region , HSA_REGION_GLOBAL_FLAG_KERNARG ) ; } </s>

Callback of hsa_iterate_regions . Called once for each available memory region , and returns `` break '' when a suitable one has been found .


<s> unsigned MipsSEInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == Mips :: LW ) || ( Opc == Mips :: LWC1 ) || ( Opc == Mips :: LDC1 ) ) { if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> const MCExpr * ARMElfTargetObjectFile :: getIndirectSymViaRWPI ( const MCSymbol * Sym ) const { return MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_ARM_SBREL , getContext ( ) ) ; } </s>

Get the target specific RWPI relocation .


<s> static int c6x_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { enum attr_type insn_type = TYPE_UNKNOWN , dep_insn_type = TYPE_UNKNOWN ; int dep_insn_code_number , insn_code_number ; int shadow_bonus = 0 ; enum reg_note kind ; dep_insn_code_number = recog_memoized ( dep_insn ) ; insn_code_number = recog_memoized ( insn ) ; if ( dep_insn_code_number >= 0 ) dep_insn_type = get_attr_type ( dep_insn ) ; if ( insn_code_number >= 0 ) insn_type = get_attr_type ( insn ) ; kind = REG_NOTE_KIND ( link ) ; if ( kind == 0 ) { if ( dep_insn_type == TYPE_LOAD ) { rtx set = PATTERN ( dep_insn ) ; if ( GET_CODE ( set ) == COND_EXEC ) set = COND_EXEC_CODE ( set ) ; if ( GET_CODE ( set ) == UNSPEC ) cost = 1 ; else { gcc_assert ( GET_CODE ( set ) == SET ) ; if ( ! reg_overlap_mentioned_p ( SET_DEST ( set ) , PATTERN ( insn ) ) ) cost = 1 ; } } } if ( shadow_type_p ( insn_type ) ) shadow_bonus = 1 ; if ( kind != 0 ) { if ( kind == REG_DEP_ANTI && insn_type == TYPE_SHADOW ) kind = REG_DEP_OUTPUT ; switch ( dep_insn_type ) { case TYPE_CALLP : return 1 ; case TYPE_BRANCH : case TYPE_CALL : if ( get_attr_has_shadow ( dep_insn ) == HAS_SHADOW_Y ) return 0 ; return 6 ; case TYPE_LOAD : case TYPE_LOADN : case TYPE_INTDP : if ( kind == REG_DEP_OUTPUT ) return 5 - shadow_bonus ; return 0 ; case TYPE_MPY4 : case TYPE_FP4 : if ( kind == REG_DEP_OUTPUT ) return 4 - shadow_bonus ; return 0 ; case TYPE_MPY2 : if ( kind == REG_DEP_OUTPUT ) return 2 - shadow_bonus ; return 0 ; case TYPE_CMPDP : if ( kind == REG_DEP_OUTPUT ) return 2 - shadow_bonus ; return 2 ; case TYPE_ADDDP : case TYPE_MPYSPDP : if ( kind == REG_DEP_OUTPUT ) return 7 - shadow_bonus ; return 2 ; case TYPE_MPYSP2DP : if ( kind == REG_DEP_OUTPUT ) return 5 - shadow_bonus ; return 2 ; case TYPE_MPYI : if ( kind == REG_DEP_OUTPUT ) return 9 - shadow_bonus ; return 4 ; case TYPE_MPYID : case TYPE_MPYDP : if ( kind == REG_DEP_OUTPUT ) return 10 - shadow_bonus ; return 4 ; default : if ( insn_type == TYPE_SPKERNEL ) return 0 ; if ( kind == REG_DEP_OUTPUT ) return 1 - shadow_bonus ; return 0 ; } } return cost - shadow_bonus ; } </s>

Implement the TARGET_SCHED_ADJUST_COST hook . We need special handling for anti- and output dependencies .


<s> static int xstormy16_memory_move_cost ( machine_mode mode , reg_class_t rclass , bool in ) { return ( 5 + memory_move_secondary_cost ( mode , rclass , in ) ) ; } </s>

Worker function for TARGET_MEMORY_MOVE_COST .


<s> static void free_label_states ( struct unw_labeled_state * ls ) { struct unw_labeled_state * next ; for ( ; ls ; ls = next ) { next = ls -> next ; free_state_stack ( & ls -> saved_state ) ; free_label_state ( ls ) ; } } </s>


<s>
uint32_t
AMDGPUTargetLowering
::
getImplicitParameterOffset
(
const
MachineFunction
&
MF
,
const
ImplicitParameter
Param
)
const
{
const
AMDGPUMachineFunction
*
MFI
=
MF
.
getInfo
<
AMDGPUMachineFunction
>
(
)
;
const
AMDGPUSubtarget
&
ST
=
AMDGPUSubtarget
::
get
(
getTargetMachine
(
)
,
MF
.
getFunction
(
)
)
;
unsigned
ExplicitArgOffset
=
ST
.
getExplicitKernelArgOffset
(
MF
.
getFunction
(
)
)
;
const
Align
Alignment
=
ST
.
getAlignmentForImplicitArgPtr
(
)
;
uint64_t
ArgOffset
=
alignTo
(
MFI
->
getExplicitKernArgSize
(
)
,
Alignment
)
+
ExplicitArgOffset
;
switch
(
Param
)
{
case
GRID_DIM
:
return
ArgOffset
;
case
GRID_OFFSET
:
return
ArgOffset
+
4
;
}
llvm_unreachable
(
"unexpected implicit parameter type"
)
;
}
</s>

Helper function that returns the byte offset of the given type of implicit parameter .

AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
4
"unexpected implicit parameter type"


<s>
bool
HexagonInstrInfo
::
getBaseAndOffsetPosition
(
const
MachineInstr
*
MI
,
unsigned
&
BasePos
,
unsigned
&
OffsetPos
)
const
{
if
(
isMemOp
(
MI
)
)
{
assert
(
MI
->
getOperand
(
0
)
.
isReg
(
)
&&
MI
->
getOperand
(
1
)
.
isImm
(
)
&&
"Bad Memop."
)
;
BasePos
=
0
;
OffsetPos
=
1
;
}
else
if
(
MI
->
mayStore
(
)
)
{
BasePos
=
0
;
OffsetPos
=
1
;
}
else
if
(
MI
->
mayLoad
(
)
)
{
BasePos
=
1
;
OffsetPos
=
2
;
}
else
return
false
;
if
(
isPredicated
(
MI
)
)
{
BasePos
++
;
OffsetPos
++
;
}
if
(
isPostIncrement
(
MI
)
)
{
BasePos
++
;
OffsetPos
++
;
}
if
(
!
MI
->
getOperand
(
BasePos
)
.
isReg
(
)
||
!
MI
->
getOperand
(
OffsetPos
)
.
isImm
(
)
)
return
false
;
return
true
;
}
</s>

Return true if the instruction contains a base register and offset .


<s>
virtual
const
char
*
getPassName
(
)
const
LLVM_OVERRIDE
{
return
"X86 AT&T-Style Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> const char * AArch64TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case AArch64ISD :: BR_CC : return "AArch64ISD::BR_CC" ; case AArch64ISD :: Call : return "AArch64ISD::Call" ; case AArch64ISD :: FPMOV : return "AArch64ISD::FPMOV" ; case AArch64ISD :: GOTLoad : return "AArch64ISD::GOTLoad" ; case AArch64ISD :: BFI : return "AArch64ISD::BFI" ; case AArch64ISD :: EXTR : return "AArch64ISD::EXTR" ; case AArch64ISD :: Ret : return "AArch64ISD::Ret" ; case AArch64ISD :: SBFX : return "AArch64ISD::SBFX" ; case AArch64ISD :: SELECT_CC : return "AArch64ISD::SELECT_CC" ; case AArch64ISD :: SETCC : return "AArch64ISD::SETCC" ; case AArch64ISD :: TC_RETURN : return "AArch64ISD::TC_RETURN" ; case AArch64ISD :: THREAD_POINTER : return "AArch64ISD::THREAD_POINTER" ; case AArch64ISD :: TLSDESCCALL : return "AArch64ISD::TLSDESCCALL" ; case AArch64ISD :: WrapperSmall : return "AArch64ISD::WrapperSmall" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugValue ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s>
const
char
*
lshrsi3_out
(
rtx_insn
*
insn
,
rtx
operands
[
]
,
int
*
len
)
{
if
(
CONST_INT_P
(
operands
[
2
]
)
)
{
int
k
;
int
*
t
=
len
;
if
(
!
len
)
len
=
&
k
;
switch
(
INTVAL
(
operands
[
2
]
)
)
{
default
:
if
(
INTVAL
(
operands
[
2
]
)
<
32
)
break
;
if
(
AVR_HAVE_MOVW
)
return
*
len
=
3
,
(
"clr %D0"
CR_TAB
"clr %C0"
CR_TAB
"movw %A0,%C0"
)
;
*
len
=
4
;
return
(
"clr %D0"
CR_TAB
"clr %C0"
CR_TAB
"clr %B0"
CR_TAB
"clr %A0"
)
;
case
8
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
*
len
=
4
;
if
(
reg0
<=
reg1
)
return
(
"mov %A0,%B1"
CR_TAB
"mov %B0,%C1"
CR_TAB
"mov %C0,%D1"
CR_TAB
"clr %D0"
)
;
else
return
(
"clr %D0"
CR_TAB
"mov %C0,%D1"
CR_TAB
"mov %B0,%C1"
CR_TAB
"mov %A0,%B1"
)
;
}
case
16
:
{
int
reg0
=
true_regnum
(
operands
[
0
]
)
;
int
reg1
=
true_regnum
(
operands
[
1
]
)
;
if
(
reg0
==
reg1
+
2
)
return
*
len
=
2
,
(
"clr %C0"
CR_TAB
"clr %D0"
)
;
if
(
AVR_HAVE_MOVW
)
return
*
len
=
3
,
(
"movw %A0,%C1"
CR_TAB
"clr %C0"
CR_TAB
"clr %D0"
)
;
else
return
*
len
=
4
,
(
"mov %B0,%D1"
CR_TAB
"mov %A0,%C1"
CR_TAB
"clr %C0"
CR_TAB
"clr %D0"
)
;
}
case
24
:
return
*
len
=
4
,
(
"mov %A0,%D1"
CR_TAB
"clr %B0"
CR_TAB
"clr %C0"
CR_TAB
"clr %D0"
)
;
case
31
:
*
len
=
6
;
return
(
"clr %A0"
CR_TAB
"sbrc %D0,7"
CR_TAB
"inc %A0"
CR_TAB
"clr %B0"
CR_TAB
"clr %C0"
CR_TAB
"clr %D0"
)
;
}
len
=
t
;
}
out_shift_with_cnt
(
"lsr %D0"
CR_TAB
"ror %C0"
CR_TAB
"ror %B0"
CR_TAB
"ror %A0"
,
insn
,
operands
,
len
,
4
)
;
return
""
;
}
</s>

32bit logic shift right ( ( unsigned int ) x > > i )


<s> bool PPCTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : case MVT :: f64 : return true ; case MVT :: f128 : return ( EnableQuadPrecision && Subtarget . hasP9Vector ( ) ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> bool AArch64AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == ".hword" ) return ParseDirectiveWord ( 2 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".word" ) return ParseDirectiveWord ( 4 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".xword" ) return ParseDirectiveWord ( 8 , DirectiveID . getLoc ( ) ) ; else if ( IDVal == ".tlsdesccall" ) return ParseDirectiveTLSDescCall ( DirectiveID . getLoc ( ) ) ; return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


Returns the description of caches on AIX .


<s> SDValue mprocTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , DebugLoc dl , SelectionDAG & DAG ) const { } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> unsigned getMinimumNopSize ( ) const override { return 2 ; } </s>

Returns the minimum size of a nop in bytes on this target .


<s> int X86TargetLowering :: getScalingFactorCost ( const AddrMode & AM , Type * Ty ) const { if ( isLegalAddressingMode ( AM , Ty ) ) return AM . Scale != 0 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


<s>
MCSection
*
XCoreTargetObjectFile
::
getSectionForConstant
(
const
DataLayout
&
DL
,
SectionKind
Kind
,
const
Constant
*
C
,
Align
&
Alignment
)
const
{
if
(
Kind
.
isMergeableConst4
(
)
)
return
MergeableConst4Section
;
if
(
Kind
.
isMergeableConst8
(
)
)
return
MergeableConst8Section
;
if
(
Kind
.
isMergeableConst16
(
)
)
return
MergeableConst16Section
;
assert
(
(
Kind
.
isReadOnly
(
)
||
Kind
.
isReadOnlyWithRel
(
)
)
&&
"Unknown section kind"
)
;
return
ReadOnlySection
;
}
</s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> bool Z80Operand :: isMem ( ) const { return false ; } </s>


Internal function to either define or undef the appropriate system macros .


"dynamic alloca in the static alloca map?"

Emit an alloca address in a register using target-specific logic .


<s> void print_operand_address ( FILE * file , rtx addr ) { rtx lhs , rhs ; retry : ; switch ( GET_CODE ( addr ) ) { case MEM : fprintf ( file , "#" ) ; addr = XEXP ( addr , 0 ) ; goto retry ; case REG : fprintf ( file , "@%s" , pointer_reg [ REGNO ( addr ) ] ) ; break ; case PRE_DEC : fprintf ( file , "%s" , pointer_reg [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case POST_INC : fprintf ( file , "%s" , pointer_reg [ REGNO ( XEXP ( addr , 0 ) ) ] ) ; break ; case PLUS : lhs = XEXP ( addr , 0 ) ; rhs = XEXP ( addr , 1 ) ; if ( GET_CODE ( rhs ) == REG && GET_CODE ( lhs ) != REG ) { rtx swap = lhs ; lhs = rhs ; rhs = swap ; } if ( GET_CODE ( rhs ) == SIGN_EXTEND || GET_CODE ( rhs ) == TRUNCATE ) { rtx swap = lhs ; lhs = rhs ; rhs = swap ; } if ( TARGET_BIG && ( inside_ba_p ( addr , 1 ) && ( STACK_REGISTER ( REGNO ( lhs ) ) || can_ba_bx ) && GET_CODE ( rhs ) == CONST_INT ) ) { int offset = INTVAL ( rhs ) ; if ( REGNO ( lhs ) == STACK_POINTER_REGNUM && saved_reg_on_stack_hack ) offset += 4 ; saved_reg_on_stack_hack = 0 ; fprintf ( file , "%s(#" , pointer_reg [ REGNO ( lhs ) ] ) ; fprintf ( file , "%d" , offset ) ; fprintf ( file , ")" ) ; } else if ( inside_bx_p ( addr , 1 ) && ( can_ba_bx || ( STACK_REGISTER ( REGNO ( lhs ) ) ) ) ) { rtx base ; rtx disp ; if ( GET_CODE ( lhs ) == REG ) { base = lhs ; disp = rhs ; } else { base = rhs ; disp = lhs ; } fprintf ( file , "%s(%s)" , pointer_reg [ REGNO ( base ) ] , regname ( REGNO ( getreg ( disp ) ) , HImode ) ) ; } else if ( inside_x_p ( addr , 1 ) ) { int r = REGNO ( lhs ) ; if ( TARGET_BIG ) { if ( GET_MODE ( lhs ) == SImode || GET_MODE ( lhs ) == PSImode ) r ++ ; } output_address ( rhs ) ; fprintf ( file , "(%s)" , regname ( r , HImode ) ) ; } else { output_address ( rhs ) ; fprintf ( file , "(%s)" , regname ( REGNO ( lhs ) , HImode ) ) ; } break ; default : output_addr_const ( file , addr ) ; } } </s>

Print the operand address represented by the rtx addr


"SIInstrInfo::loadRegFromStackSlot - Do not know how to"

Load the specified register of the given register class from the specified stack frame index .


<s> void x86_elf_aligned_decl_common ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned align ) { if ( ( ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC ) && size > ( unsigned int ) ix86_section_threshold ) { switch_to_section ( get_named_section ( decl , ".lbss" , 0 ) ) ; fputs ( LARGECOMM_SECTION_ASM_OP , file ) ; } else fputs ( COMMON_ASM_OP , file ) ; assemble_name ( file , name ) ; fprintf ( file , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n" , size , align / BITS_PER_UNIT ) ; } </s>

This says how to output assembler code to declare an uninitialized external linkage data object . For medium model x86-64 we need to use LARGECOMM_SECTION_ASM_OP opcode for large objects .


<s> static int frv_io_handle_use_1 ( rtx * x , void * data ) { HARD_REG_SET * set = data ; unsigned int regno ; if ( REG_P ( * x ) ) FOR_EACH_REGNO ( regno , * x ) SET_HARD_REG_BIT ( * set , regno ) ; return 0 ; } </s>

A for_each_rtx callback for which DATA points to a HARD_REG_SET . Add every register in * X to the set .


<s> static int arm_needs_doubleword_align ( machine_mode mode , const_tree type ) { if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) > PARM_BOUNDARY ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; int ret = 0 ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( DECL_ALIGN ( field ) > PARM_BOUNDARY ) { if ( TREE_CODE ( field ) == FIELD_DECL ) return 1 ; else ret = - 1 ; } return ret ; } </s>

Return 1 if double word alignment is required for argument passing . Return -1 if double word alignment used to be required for argument passing before PR77728 ABI fix , but is not required anymore . Return 0 if double word alignment is not required and was n't requried before either .


<s> static unsigned nvptx_function_arg_boundary ( machine_mode mode , const_tree ARG_UNUSED ( type ) ) { return GET_MODE_ALIGNMENT ( mode ) ; } </s>


<s> bool AArch64InstrInfo :: analyzeCompare ( const MachineInstr * MI , unsigned & SrcReg , unsigned & SrcReg2 , int & CmpMask , int & CmpValue ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case AArch64 :: PTEST_PP : SrcReg = MI -> getOperand ( 0 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 1 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case AArch64 :: SUBSWrr : case AArch64 :: SUBSWrs : case AArch64 :: SUBSWrx : case AArch64 :: SUBSXrr : case AArch64 :: SUBSXrs : case AArch64 :: SUBSXrx : case AArch64 :: ADDSWrr : case AArch64 :: ADDSWrs : case AArch64 :: ADDSWrx : case AArch64 :: ADDSXrr : case AArch64 :: ADDSXrs : case AArch64 :: ADDSXrx : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( 2 ) . getReg ( ) ; CmpMask = ~ 0 ; CmpValue = 0 ; return true ; case AArch64 :: SUBSWri : case AArch64 :: ADDSWri : case AArch64 :: SUBSXri : case AArch64 :: ADDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = ( MI -> getOperand ( 2 ) . getImm ( ) != 0 ) ; return true ; case AArch64 :: ANDSWri : case AArch64 :: ANDSXri : SrcReg = MI -> getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; CmpMask = ~ 0 ; CmpValue = ( AArch64_AM :: decodeLogicalImmediate ( MI -> getOperand ( 2 ) . getImm ( ) , MI -> getOpcode ( ) == AArch64 :: ANDSWri ? 32 : 64 ) != 0 ) ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> const uint32_t * AVRRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_Normal_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool aarch64_harden_sls_retbr_p ( void ) { return aarch64_sls_hardening & SLS_RETBR ; } </s>

Return whether we should mitigatate Straight Line Speculation for the RET and BR instructions .


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( MVT VT ) const override { if ( VT . getScalarSizeInBits ( ) % 8 == 0 ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool ARMTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( ! Subtarget -> hasVFP3 ( ) ) return false ; if ( VT == MVT :: f32 ) return ARM_AM :: getFP32Imm ( Imm ) != - 1 ; if ( VT == MVT :: f64 ) return ARM_AM :: getFP64Imm ( Imm ) != - 1 ; return false ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


"only uninitialized variables can be placed in the "

Implement ` TARGET_SECTION_TYPE_FLAGS ' .


<s> static rtx mips16_gp_pseudo_reg ( void ) { if ( cfun -> machine -> mips16_gp_pseudo_rtx == NULL_RTX ) { rtx unspec ; rtx insn , scan ; cfun -> machine -> mips16_gp_pseudo_rtx = gen_reg_rtx ( Pmode ) ; start_sequence ( ) ; unspec = gen_rtx_UNSPEC ( VOIDmode , gen_rtvec ( 1 , const0_rtx ) , UNSPEC_GP ) ; emit_move_insn ( cfun -> machine -> mips16_gp_pseudo_rtx , gen_rtx_CONST ( Pmode , unspec ) ) ; insn = get_insns ( ) ; end_sequence ( ) ; push_topmost_sequence ( ) ; for ( scan = get_insns ( ) ; scan != NULL_RTX ; scan = NEXT_INSN ( scan ) ) if ( NOTE_P ( scan ) && NOTE_LINE_NUMBER ( scan ) == NOTE_INSN_FUNCTION_BEG ) break ; if ( scan == NULL_RTX ) scan = get_insns ( ) ; insn = emit_insn_after ( insn , scan ) ; pop_topmost_sequence ( ) ; } return cfun -> machine -> mips16_gp_pseudo_rtx ; } </s>

If we can access small data directly ( using gp-relative relocation operators ) return the small data pointer , otherwise return null . For each mips16 function which refers to GP relative symbols , we use a pseudo register , initialized at the start of the function , to hold the $ gp value .


<s>
SDValue
MipsTargetLowering
::
LowerCallResult
(
SDValue
Chain
,
SDValue
InFlag
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
SDLoc
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
,
TargetLowering
::
CallLoweringInfo
&
CLI
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MipsCCState
CCInfo
(
CallConv
,
IsVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeCallResult
(
Ins
,
RetCC_Mips
,
CLI
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Val
=
DAG
.
getCopyFromReg
(
Chain
,
DL
,
RVLocs
[
i
]
.
getLocReg
(
)
,
RVLocs
[
i
]
.
getLocVT
(
)
,
InFlag
)
;
Chain
=
Val
.
getValue
(
1
)
;
InFlag
=
Val
.
getValue
(
2
)
;
if
(
VA
.
isUpperBitsInLoc
(
)
)
{
unsigned
ValSizeInBits
=
Ins
[
i
]
.
ArgVT
.
getSizeInBits
(
)
;
unsigned
LocSizeInBits
=
VA
.
getLocVT
(
)
.
getSizeInBits
(
)
;
unsigned
Shift
=
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExtUpper
ISD
::
SRL
:
ISD
::
SRA
;
Val
=
DAG
.
getNode
(
Shift
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getConstant
(
LocSizeInBits
ValSizeInBits
,
DL
,
VA
.
getLocVT
(
)
)
)
;
}
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
BCvt
:
Val
=
DAG
.
getNode
(
ISD
::
BITCAST
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
AExt
:
case
CCValAssign
::
AExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
ZExt
:
case
CCValAssign
::
ZExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertZext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
case
CCValAssign
::
SExt
:
case
CCValAssign
::
SExtUpper
:
Val
=
DAG
.
getNode
(
ISD
::
AssertSext
,
DL
,
VA
.
getLocVT
(
)
,
Val
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
Val
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
DL
,
VA
.
getValVT
(
)
,
Val
)
;
break
;
}
InVals
.
push_back
(
Val
)
;
}
return
Chain
;
}
</s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .

Mips
Mips
ISD::InputArg
16
Mips
Mips
0
"Can only return in registers!"
1
2
ISD::SRL
ISD::SRA
"Unknown loc info!"
ISD::BITCAST
ISD::TRUNCATE
ISD::AssertZext
ISD::TRUNCATE
ISD::AssertSext
ISD::TRUNCATE


<s> bool runOnFunction ( Function & F ) override { return BPFAbstractMemberAccess ( TM ) . run ( F ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void RISCVFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { const RISCVRegisterInfo * RegInfo = MF . getSubtarget < RISCVSubtarget > ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; int64_t RVVStackSize = assignRVVStackObjectOffsets ( MFI ) ; RVFI -> setRVVStackSize ( RVVStackSize ) ; const RISCVInstrInfo & TII = * MF . getSubtarget < RISCVSubtarget > ( ) . getInstrInfo ( ) ; if ( ! isInt < 11 > ( MFI . estimateStackSize ( MF ) ) || hasRVVSpillWithFIs ( MF , TII ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; if ( RVVStackSize != 0 ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( 0 ) ; return ; } unsigned Size = 0 ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ; if ( MFI . getStackID ( FrameIdx ) != TargetStackID :: Default ) continue ; Size += MFI . getObjectSize ( FrameIdx ) ; } RVFI -> setCalleeSavedStackSize ( Size ) ; if ( RVVStackSize && ! hasFP ( MF ) && Size % 8 != 0 ) { RVFI -> setRVVPadding ( getStackAlign ( ) . value ( ) ) ; } } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static struct constant_pool * s390_mainpool_start ( void ) { struct constant_pool * pool ; rtx_insn * insn ; pool = s390_alloc_pool ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SET && GET_CODE ( SET_SRC ( PATTERN ( insn ) ) ) == UNSPEC_VOLATILE && XINT ( SET_SRC ( PATTERN ( insn ) ) , 1 ) == UNSPECV_MAIN_POOL ) { if ( pool -> pool_insn ) { insn = PREV_INSN ( insn ) ; delete_insn ( NEXT_INSN ( insn ) ) ; continue ; } pool -> pool_insn = insn ; } if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { rtx pool_ref = NULL_RTX ; find_constant_pool_ref ( insn , & pool_ref ) ; if ( pool_ref ) { rtx constant = get_pool_constant ( pool_ref ) ; machine_mode mode = get_pool_mode ( pool_ref ) ; s390_add_constant ( pool , constant , mode ) ; } } if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS && ! pool -> emit_pool_after ) pool -> emit_pool_after = PREV_INSN ( insn ) ; } gcc_assert ( pool -> pool_insn || pool -> size == 0 ) ; if ( pool -> size >= 4096 ) { remove_insn ( pool -> pool_insn ) ; s390_free_pool ( pool ) ; pool = NULL ; } if ( pool && ! pool -> emit_pool_after ) pool -> emit_pool_after = get_last_insn ( ) ; return pool ; } </s>

Collect main literal pool . Return NULL on overflow .


<s>
void
MachineConstPropagator
::
propagate
(
MachineFunction
&
MF
)
{
MachineBasicBlock
*
Entry
=
GraphTraits
<
MachineFunction
*
>
::
getEntryNode
(
&
MF
)
;
unsigned
EntryNum
=
Entry
->
getNumber
(
)
;
FlowQ
.
push
(
CFGEdge
(
EntryNum
,
EntryNum
)
)
;
while
(
!
FlowQ
.
empty
(
)
)
{
CFGEdge
Edge
=
FlowQ
.
front
(
)
;
FlowQ
.
pop
(
)
;
DEBUG
(
dbgs
(
)
<<
"Picked edge BB#"
<<
Edge
.
first
<<
"->BB#"
<<
Edge
.
second
<<
'\n'
)
;
if
(
Edge
.
first
!=
EntryNum
)
if
(
EdgeExec
.
count
(
Edge
)
)
continue
;
EdgeExec
.
insert
(
Edge
)
;
MachineBasicBlock
*
SB
=
MF
.
getBlockNumbered
(
Edge
.
second
)
;
MachineBasicBlock
::
const_iterator
It
=
SB
->
begin
(
)
,
End
=
SB
->
end
(
)
;
while
(
It
!=
End
&&
It
->
isPHI
(
)
)
{
InstrExec
.
insert
(
&
*
It
)
;
visitPHI
(
*
It
)
;
++
It
;
}
while
(
It
!=
End
&&
It
->
isDebugValue
(
)
)
++
It
;
assert
(
It
==
End
||
!
It
->
isPHI
(
)
)
;
if
(
It
!=
End
&&
InstrExec
.
count
(
&
*
It
)
)
continue
;
while
(
It
!=
End
&&
!
It
->
isBranch
(
)
)
{
if
(
!
It
->
isDebugValue
(
)
)
{
InstrExec
.
insert
(
&
*
It
)
;
visitNonBranch
(
*
It
)
;
}
++
It
;
}
if
(
It
!=
End
)
{
visitBranchesFrom
(
*
It
)
;
}
else
{
unsigned
SBN
=
SB
->
getNumber
(
)
;
for
(
const
MachineBasicBlock
*
SSB
:
SB
->
successors
(
)
)
FlowQ
.
push
(
CFGEdge
(
SBN
,
SSB
->
getNumber
(
)
)
)
;
}
}
DEBUG
(
{
dbgs
(
)
<<
"Cells after propagation:\n"
;
Cells
.
print
(
dbgs
(
)
,
MCE
.
TRI
)
;
dbgs
(
)
<<
"Dead CFG edges:\n"
;
for
(
const
MachineBasicBlock
&
B
:
MF
)
{
unsigned
BN
=
B
.
getNumber
(
)
;
for
(
const
MachineBasicBlock
*
SB
:
B
.
successors
(
)
)
{
unsigned
SN
=
SB
->
getNumber
(
)
;
if
(
!
EdgeExec
.
count
(
CFGEdge
(
BN
,
SN
)
)
)
dbgs
(
)
<<
"  BB#"
<<
BN
<<
" -> BB#"
<<
SN
<<
'\n'
;
}
}
}
)
;
}
</s>

Propgate synthetic entry counts on a callgraph CG .

Hexagon
"Picked edge BB#"
"->BB#"
"Cells after propagation:\n"
"Dead CFG edges:\n"
"  BB#"
" -> BB#"


<s>
void
CAHPDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
Node
->
getOpcode
(
)
==
ISD
::
FrameIndex
)
{
SDLoc
DL
(
Node
)
;
SDValue
Imm
=
CurDAG
->
getTargetConstant
(
0
,
DL
,
MVT
::
i16
)
;
int
FI
=
dyn_cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
CAHP
::
ADDI
,
DL
,
VT
,
TFI
,
Imm
)
)
;
return
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> TargetPassConfig * MOSTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new MOSPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> unsigned PPCTTIImpl :: getPrefetchDistance ( ) const { return 300 ; } </s>

Return the preferred prefetch distance in terms of instructions .


<s>
static
void
nvptx_assemble_undefined_decl
(
FILE
*
file
,
const
char
*
name
,
const_tree
decl
)
{
if
(
DECL_IN_CONSTANT_POOL
(
decl
)
)
return
;
write_var_marker
(
file
,
false
,
TREE_PUBLIC
(
decl
)
,
name
)
;
fprintf
(
file
,
"\t.extern "
)
;
tree
size
=
DECL_SIZE_UNIT
(
decl
)
;
nvptx_assemble_decl_begin
(
file
,
name
,
section_for_decl
(
decl
)
,
TREE_TYPE
(
decl
)
,
size
tree_to_shwi
(
size
)
:
0
,
DECL_ALIGN
(
decl
)
)
;
nvptx_assemble_decl_end
(
)
;
}
</s>

Implement TARGET_ASM_ASSEMBLE_UNDEFINED_DECL . Write an extern declaration only for variable DECL with NAME to FILE .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Local Dynamic TLS Access Clean-up"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> StringRef ARM64NamedImmMapper :: toString ( uint32_t Value , bool & Valid ) const { for ( unsigned i = 0 ; i < NumPairs ; ++ i ) { if ( Pairs [ i ] . Value == Value ) { Valid = true ; return Pairs [ i ] . Name ; } } Valid = false ; return StringRef ( ) ; } </s>

Convert to a decimal representation in a string .


<s> static bool aarch_macro_fusion_pair_p ( rtx_insn * prev , rtx_insn * curr ) { rtx set_dest ; rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_AES_AESMC && aarch_crypto_can_dual_issue ( prev , curr ) ) return true ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT ) { set_dest = SET_DEST ( curr_set ) ; if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , 0 ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , 0 ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } else if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( SET_DEST ( curr_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && GET_CODE ( SET_SRC ( prev_set ) ) == HIGH && REGNO ( SET_DEST ( curr_set ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } return false ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_PAIR_P . Return true if PREV and CURR should be kept together during scheduling .


<s> int standard_sse_constant_p ( rtx x , machine_mode pred_mode ) { machine_mode mode ; if ( ! TARGET_SSE ) return 0 ; mode = GET_MODE ( x ) ; if ( x == const0_rtx || const0_operand ( x , mode ) ) return 1 ; if ( x == constm1_rtx || vector_all_ones_operand ( x , mode ) || ( ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || GET_MODE_CLASS ( pred_mode ) == MODE_VECTOR_FLOAT ) && float_vector_all_ones_operand ( x , mode ) ) ) { if ( mode == VOIDmode ) mode = pred_mode ; switch ( GET_MODE_SIZE ( mode ) ) { case 64 : if ( TARGET_AVX512F ) return 2 ; break ; case 32 : if ( TARGET_AVX2 ) return 2 ; break ; case 16 : if ( TARGET_SSE2 ) return 2 ; break ; case 0 : gcc_unreachable ( ) ; default : break ; } } return 0 ; } </s>

Return 1 if X is all 0s and 2 if x is all 1s in supported SSE/AVX vector mode .


<s> void reset ( ) { MappingSymbolCounter = 0 ; State = EMS_None ; MCELFStreamer :: reset ( ) ; } </s>

Reset an existing scalar value for Def and a given Instance .


<s> static void emit_soft_tfmode_binop ( enum rtx_code code , rtx * operands ) { const char * func ; switch ( code ) { case PLUS : func = "_Qp_add" ; break ; case MINUS : func = "_Qp_sub" ; break ; case MULT : func = "_Qp_mul" ; break ; case DIV : func = "_Qp_div" ; break ; default : gcc_unreachable ( ) ; } emit_soft_tfmode_libcall ( func , 3 , operands ) ; } </s>

Expand soft-float TFmode calls to sparc abi routines .


<s> bool PPCInstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int & Mask , int & Value ) const { unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return false ; case PPC :: CMPWI : case PPC :: CMPLWI : case PPC :: CMPDI : case PPC :: CMPLDI : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = 0 ; Value = MI . getOperand ( 2 ) . getImm ( ) ; Mask = 0xFFFF ; return true ; case PPC :: CMPW : case PPC :: CMPLW : case PPC :: CMPD : case PPC :: CMPLD : case PPC :: FCMPUS : case PPC :: FCMPUD : SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; SrcReg2 = MI . getOperand ( 2 ) . getReg ( ) ; Value = 0 ; Mask = 0 ; return true ; } } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> bool HexagonEarlyIfConversion :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & ST = MF . getSubtarget ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = EnableHexagonBP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; Changed |= visitLoop ( 0 ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool MCS51TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return true ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> bool X86TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case 128 : * Fast = ! Subtarget . isUnalignedMem16Slow ( ) ; break ; case 256 : * Fast = ! Subtarget . isUnalignedMem32Slow ( ) ; break ; } } return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> bool ScheduleDAGPostRA :: canAddEdge ( SUnit * SuccSU , SUnit * PredSU ) { return SuccSU == & ExitSU || ! Topo . IsReachable ( PredSU , SuccSU ) ; } </s>

True if an edge can be added from PredSU to SuccSU without creating a cycle .


<s> bool PPCPassConfig :: addInstSelector ( ) { addPass ( createPPCISelDag ( getPPCTargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCCTRLoopsVerify ( ) ) ; if ( getPPCSubtarget ( ) . hasVSX ( ) ) addPass ( createPPCVSXCopyPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void sparc_expand_prologue ( void ) { rtx insn ; int i ; sparc_leaf_function_p = optimize > 0 && leaf_function_p ( ) && only_leaf_regs_used ( ) ; actual_fsize = sparc_compute_frame_size ( get_frame_size ( ) , sparc_leaf_function_p ) ; sparc_prologue_data_valid_p = true ; if ( sparc_leaf_function_p ) { frame_base_reg = stack_pointer_rtx ; frame_base_offset = actual_fsize + SPARC_STACK_BIAS ; } else { frame_base_reg = hard_frame_pointer_rtx ; frame_base_offset = SPARC_STACK_BIAS ; } if ( actual_fsize == 0 ) ; else if ( sparc_leaf_function_p ) { if ( actual_fsize <= 4096 ) insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - actual_fsize ) ) ) ; else if ( actual_fsize <= 8192 ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - 4096 ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - actual_fsize ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( - actual_fsize ) ) ; insn = emit_insn ( gen_stack_pointer_inc ( reg ) ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_stack_pointer_inc ( GEN_INT ( - actual_fsize ) ) , REG_NOTES ( insn ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; } else { if ( actual_fsize <= 4096 ) insn = emit_insn ( gen_save_register_window ( GEN_INT ( - actual_fsize ) ) ) ; else if ( actual_fsize <= 8192 ) { insn = emit_insn ( gen_save_register_window ( GEN_INT ( - 4096 ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( 4096 - actual_fsize ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( - actual_fsize ) ) ; insn = emit_insn ( gen_save_register_window ( reg ) ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , 0 , i ) ) = 1 ; } if ( num_gfregs ) emit_save_or_restore_regs ( SORR_SAVE ) ; if ( flag_pic && current_function_uses_pic_offset_table ) load_pic_register ( false ) ; } </s>

Expand the function prologue . The prologue is responsible for reserving storage for the frame , saving the call-saved registers and loading the PIC register if needed .


<s>
MachineBasicBlock
*
SystemZTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
,
DenseMap
<
MachineBasicBlock
*
,
MachineBasicBlock
*
>
*
EM
)
const
{
const
SystemZInstrInfo
&
TII
=
*
TM
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
SystemZ
::
Select32
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF32
||
MI
->
getOpcode
(
)
==
SystemZ
::
Select64
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF64
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
SystemZCC
::
CondCodes
CC
=
(
SystemZCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
BuildMI
(
BB
,
dl
,
TII
.
getBrCond
(
CC
)
)
.
addMBB
(
copy1MBB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
for
(
MachineBasicBlock
::
succ_iterator
SI
=
BB
->
succ_begin
(
)
,
SE
=
BB
->
succ_end
(
)
;
SI
!=
SE
;
++
SI
)
EM
->
insert
(
std
::
make_pair
(
*
SI
,
copy1MBB
)
)
;
copy1MBB
->
transferSuccessors
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
SystemZ
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
F
->
DeleteMachineInstr
(
MI
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void aarch64_split_simd_combine ( rtx dst , rtx src1 , rtx src2 ) { machine_mode src_mode = GET_MODE ( src1 ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src1 ) && REG_P ( src2 ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( src_mode ) { case V8QImode : gen = gen_aarch64_simd_combinev8qi ; break ; case V4HImode : gen = gen_aarch64_simd_combinev4hi ; break ; case V2SImode : gen = gen_aarch64_simd_combinev2si ; break ; case V4HFmode : gen = gen_aarch64_simd_combinev4hf ; break ; case V2SFmode : gen = gen_aarch64_simd_combinev2sf ; break ; case DImode : gen = gen_aarch64_simd_combinedi ; break ; case DFmode : gen = gen_aarch64_simd_combinedf ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src1 , src2 ) ) ; return ; } } </s>


<s>
MachineInstr
*
RISCVInstrInfo
::
convertToThreeAddress
(
MachineInstr
&
MI
,
LiveVariables
*
LV
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
break
;
case
CASE_WIDEOP_OPCODE_LMULS
(
FWADD_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
FWSUB_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WADD_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WADDU_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WSUB_WV
)
:
case
CASE_WIDEOP_OPCODE_LMULS
(
WSUBU_WV
)
:
{
unsigned
NewOpc
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unexpected opcode"
)
;
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
FWADD_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
FWSUB_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WADD_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WADDU_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WSUB_WV
)
CASE_WIDEOP_CHANGE_OPCODE_LMULS
(
WSUBU_WV
)
}
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
MI
.
getDebugLoc
(
)
,
get
(
NewOpc
)
)
.
add
(
MI
.
getOperand
(
0
)
)
.
add
(
MI
.
getOperand
(
1
)
)
.
add
(
MI
.
getOperand
(
2
)
)
.
add
(
MI
.
getOperand
(
3
)
)
.
add
(
MI
.
getOperand
(
4
)
)
;
MIB
.
copyImplicitOps
(
MI
)
;
if
(
LV
)
{
unsigned
NumOps
=
MI
.
getNumOperands
(
)
;
for
(
unsigned
I
=
1
;
I
<
NumOps
;
++
I
)
{
MachineOperand
&
Op
=
MI
.
getOperand
(
I
)
;
if
(
Op
.
isReg
(
)
&&
Op
.
isKill
(
)
)
LV
->
replaceKillInstruction
(
Op
.
getReg
(
)
,
MI
,
*
MIB
)
;
}
}
return
MIB
;
}
}
return
nullptr
;
}
</s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s> SparcTargetLowering :: ConstraintType SparcTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : case 'f' : case 'e' : return C_RegisterClass ; case 'I' : return C_Other ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static rtx c6x_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , REG_A4 ) ; } </s>


<s> const MCExpr * createExprForCAPIVariantKind ( const MCExpr * SubExpr , unsigned VariantKind ) override { switch ( VariantKind ) { case LLVMDisassembler_VariantKind_ARM_HI16 : return ARMMCExpr :: CreateUpper16 ( SubExpr , Ctx ) ; case LLVMDisassembler_VariantKind_ARM_LO16 : return ARMMCExpr :: CreateLower16 ( SubExpr , Ctx ) ; default : return MCRelocationInfo :: createExprForCAPIVariantKind ( SubExpr , VariantKind ) ; } } </s>

Create an MCExpr for the target-specific VariantKind .


<s> bool AMDGPUAAResult :: pointsToConstantMemory ( const MemoryLocation & Loc , bool OrLocal ) { const Value * Base = GetUnderlyingObject ( Loc . Ptr , DL ) ; if ( Base -> getType ( ) -> getPointerAddressSpace ( ) == AS . CONSTANT_ADDRESS ) { return true ; } if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Base ) ) { if ( GV -> isConstant ( ) ) return true ; } else if ( const Argument * Arg = dyn_cast < Argument > ( Base ) ) { const Function * F = Arg -> getParent ( ) ; switch ( F -> getCallingConv ( ) ) { default : return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ; case CallingConv :: AMDGPU_VS : case CallingConv :: AMDGPU_GS : case CallingConv :: AMDGPU_PS : case CallingConv :: AMDGPU_CS : case CallingConv :: AMDGPU_KERNEL : case CallingConv :: SPIR_KERNEL : break ; } unsigned ArgNo = Arg -> getArgNo ( ) ; if ( F -> hasParamAttribute ( ArgNo , Attribute :: NoAlias ) && ( F -> hasParamAttribute ( ArgNo , Attribute :: ReadNone ) || F -> hasParamAttribute ( ArgNo , Attribute :: ReadOnly ) ) ) { return true ; } } return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ; } </s>

A convenience wrapper around the primary pointsToConstantMemory interface .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


"execute-only should not generate constant pools"

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetMachO ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && ! Subtarget -> isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new ARMFastISel ( funcInfo , libInfo ) ; } return nullptr ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> TargetLowering :: AtomicExpansionKind X86TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { auto PTy = cast < PointerType > ( LI -> getPointerOperandType ( ) ) ; return needsCmpXchgNb ( PTy -> getElementType ( ) ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ; } </s>

Returns how the given ( atomic ) load should be expanded by the IR-level AtomicExpand pass .


<s> bool MipsSEInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; bool isMicroMips = Subtarget . inMicroMipsMode ( ) ; unsigned Opc ; switch ( MI . getDesc ( ) . getOpcode ( ) ) { default : return false ; case Mips :: RetRA : expandRetRA ( MBB , MI ) ; break ; case Mips :: ERet : expandERet ( MBB , MI ) ; break ; case Mips :: PseudoMFHI : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI ) ; break ; case Mips :: PseudoMFHI_MM : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI16_MM ) ; break ; case Mips :: PseudoMFLO : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO ) ; break ; case Mips :: PseudoMFLO_MM : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO16_MM ) ; break ; case Mips :: PseudoMFHI64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFHI64 ) ; break ; case Mips :: PseudoMFLO64 : expandPseudoMFHiLo ( MBB , MI , Mips :: MFLO64 ) ; break ; case Mips :: PseudoMTLOHI : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO , Mips :: MTHI , false ) ; break ; case Mips :: PseudoMTLOHI64 : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO64 , Mips :: MTHI64 , false ) ; break ; case Mips :: PseudoMTLOHI_DSP : expandPseudoMTLoHi ( MBB , MI , Mips :: MTLO_DSP , Mips :: MTHI_DSP , true ) ; break ; case Mips :: PseudoCVT_S_W : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_W , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_D32_W : Opc = isMicroMips ? Mips :: CVT_D32_W_MM : Mips :: CVT_D32_W ; expandCvtFPInt ( MBB , MI , Opc , Mips :: MTC1 , false ) ; break ; case Mips :: PseudoCVT_S_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_S_L , Mips :: DMTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_W : Opc = isMicroMips ? Mips :: CVT_D64_W_MM : Mips :: CVT_D64_W ; expandCvtFPInt ( MBB , MI , Opc , Mips :: MTC1 , true ) ; break ; case Mips :: PseudoCVT_D64_L : expandCvtFPInt ( MBB , MI , Mips :: CVT_D64_L , Mips :: DMTC1 , true ) ; break ; case Mips :: BuildPairF64 : expandBuildPairF64 ( MBB , MI , isMicroMips , false ) ; break ; case Mips :: BuildPairF64_64 : expandBuildPairF64 ( MBB , MI , isMicroMips , true ) ; break ; case Mips :: ExtractElementF64 : expandExtractElementF64 ( MBB , MI , isMicroMips , false ) ; break ; case Mips :: ExtractElementF64_64 : expandExtractElementF64 ( MBB , MI , isMicroMips , true ) ; break ; case Mips :: MIPSeh_return32 : case Mips :: MIPSeh_return64 : expandEhReturn ( MBB , MI ) ; break ; } MBB . erase ( MI ) ; return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> auto HexagonVectorCombine :: isUndef ( const Value * Val ) const -> bool { return isa < UndefValue > ( Val ) ; } </s>

Return true if the result of this operation is always undefined .


<s> bool PPCCTRLoops :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; PreserveLCSSA = mustPreserveAnalysisID ( LCSSAID ) ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { Loop * L = * I ; if ( ! L -> getParentLoop ( ) ) MadeChange |= convertToCTRLoop ( L ) ; } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 ) return true ; } bool ReverseVEXT ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; return ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isVTRNMask ( M , VT , WhichResult ) || isVUZPMask ( M , VT , WhichResult ) || isVZIPMask ( M , VT , WhichResult ) || isVTRN_v_undef_Mask ( M , VT , WhichResult ) || isVUZP_v_undef_Mask ( M , VT , WhichResult ) || isVZIP_v_undef_Mask ( M , VT , WhichResult ) ) ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> rtx gen_compare_reg ( rtx cmp ) { return gen_compare_reg_1 ( GET_CODE ( cmp ) , XEXP ( cmp , 0 ) , XEXP ( cmp , 1 ) ) ; } </s>

Emit the compare insn and return the CC reg for the comparison in CMP .


<s> bool PPCAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { std :: string NewOpcode ; if ( getLexer ( ) . is ( AsmToken :: Plus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '+' ; Name = NewOpcode ; } if ( getLexer ( ) . is ( AsmToken :: Minus ) ) { getLexer ( ) . Lex ( ) ; NewOpcode = Name ; NewOpcode += '-' ; Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( 0 , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( Mnemonic , NameLoc , isPPC64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( PPCOperand :: CreateTokenWithStringCopy ( DotStr , DotLoc , isPPC64 ( ) ) ) ; else Operands . push_back ( PPCOperand :: CreateToken ( DotStr , DotLoc , isPPC64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ PPC :: FeatureBookE ] && Operands . size ( ) == 4 && ( Name == "dcbt" || Name == "dcbtst" ) ) { std :: swap ( Operands [ 1 ] , Operands [ 3 ] ) ; std :: swap ( Operands [ 2 ] , Operands [ 1 ] ) ; } return false ; } </s>

ParseInstruction - Parse one assembly instruction .

PowerPC PPC 0 PPC PPC PPC PPC PPC PPC PPC PPC PPC::FeatureBookE 4 "dcbt" "dcbtst" 1 3 2 1


<s> void MSP430FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MSP430InstrInfo & TII = * static_cast < const MSP430InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned StackAlign = getStackAlignment ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; if ( Amount != 0 ) { Amount = ( Amount + StackAlign - 1 ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old -> getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old -> getOperand ( 1 ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: ADD16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( 1 ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( MSP430 :: SUB16ri ) , MSP430 :: SPW ) . addReg ( MSP430 :: SPW ) . addImm ( CalleeAmt ) ; New -> getOperand ( 3 ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static rtx expand_mad ( function_expander & e , unsigned int merge_argno = DEFAULT_MERGE_ARGNO ) { if ( e . pred == PRED_x ) { insn_code icode ; if ( e . type_suffix ( 0 ) . integer_p ) icode = code_for_aarch64_pred_fma ( e . vector_mode ( 0 ) ) ; else icode = code_for_aarch64_pred ( UNSPEC_COND_FMLA , e . vector_mode ( 0 ) ) ; return e . use_pred_x_insn ( icode ) ; } insn_code icode = e . direct_optab_handler ( cond_fma_optab ) ; return e . use_cond_insn ( icode , merge_argno ) ; } </s>

Expand a call to svmad , or svmla after reordering its operands . Make _m forms merge with argument MERGE_ARGNO .


<s> static void replace_swapped_aligned_load ( swap_web_entry * insn_entry , rtx swap_insn ) { unsigned uid = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && ! insn_entry [ uid ] . is_load ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( swap_insn ) ; df_ref use = DF_INSN_INFO_USES ( insn_info ) ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; gcc_assert ( def_link && ! def_link -> next ) ; gcc_assert ( def_link && def_link -> ref && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) && ! def_link -> next ) ; rtx_insn * def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_load && insn_entry [ uid2 ] . is_swap ) ; rtx body = PATTERN ( def_insn ) ; gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) && MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_SRC ( new_body ) ) ) ; basic_block bb = BLOCK_FOR_INSN ( def_insn ) ; set_block_for_insn ( new_insn , bb ) ; if ( cfun -> can_throw_non_call_exceptions && BB_END ( bb ) == def_insn ) { rtx note = find_reg_note ( def_insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) add_reg_note ( new_insn , REG_EH_REGION , XEXP ( note , 0 ) ) ; } df_insn_rescan ( new_insn ) ; df_insn_delete ( def_insn ) ; remove_insn ( def_insn ) ; def_insn -> set_deleted ( ) ; mark_swaps_for_removal ( insn_entry , uid ) ; replace_swap_with_copy ( insn_entry , uid ) ; } </s>

Given that SWAP_INSN represents a swap of an aligned load-with-swap , replace the load with an aligned load ( without swap ) and replace the swap with a copy insn .


<s> void add ( const Argument * Arg , MachineFunction * MF , Register R ) { DT . add ( Arg , MF , R ) ; } </s>


<s>
bool
AMDGPUAnnotateKernelFeatures
::
doInitialization
(
CallGraph
&
CG
)
{
auto
*
TPC
=
getAnalysisIfAvailable
<
TargetPassConfig
>
(
)
;
if
(
!
TPC
)
report_fatal_error
(
"TargetMachine is required"
)
;
AS
=
AMDGPU
::
getAMDGPUAS
(
CG
.
getModule
(
)
)
;
TM
=
&
TPC
->
getTM
<
TargetMachine
>
(
)
;
return
false
;
}
</s>

Set up the AsmPrinter when we are working on a new module .

AMDGPU
AMDGPU
"TargetMachine is required"
AMDGPU::getAMDGPUAS


<s> bool TPCTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { return VT == MVT :: f32 || VT == MVT :: f16 || VT == MVT :: bf16 ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


"****** Hexagon Branch Relaxation ******\n"

runOnMachineFunction - Emit the function body .


<s>
bool
PPCRegisterInfo
::
needsFrameBaseReg
(
MachineInstr
*
MI
,
int64_t
Offset
)
const
{
assert
(
Offset
<
0
&&
"Local offset must be negative"
)
;
unsigned
OpC
=
MI
->
getOpcode
(
)
;
if
(
!
ImmToIdxMap
.
count
(
OpC
)
)
return
false
;
if
(
(
OpC
==
PPC
::
ADDI
||
OpC
==
PPC
::
ADDI8
)
&&
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
return
false
;
MachineBasicBlock
&
MBB
=
*
MI
->
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
PPCFrameLowering
*
PPCFI
=
static_cast
<
const
PPCFrameLowering
*
>
(
Subtarget
.
getFrameLowering
(
)
)
;
unsigned
StackEst
=
PPCFI
->
determineFrameLayout
(
MF
,
false
,
true
)
;
if
(
!
StackEst
)
return
false
;
Offset
+=
StackEst
;
return
!
isFrameOffsetLegal
(
MI
,
Offset
)
;
}
</s>

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .

PowerPC
PPC
0
"Local offset must be negative"
PPC::ADDI
PPC::ADDI8
2
0
PPC
PPC
PPC
PPC


<s>
Register
AArch64TargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
Register
Reg
=
MatchRegisterName
(
RegName
)
;
if
(
AArch64
::
X1
<=
Reg
&&
Reg
<=
AArch64
::
X28
)
{
const
MCRegisterInfo
*
MRI
=
Subtarget
->
getRegisterInfo
(
)
;
unsigned
DwarfRegNum
=
MRI
->
getDwarfRegNum
(
Reg
,
false
)
;
if
(
!
Subtarget
->
isXRegisterReserved
(
DwarfRegNum
)
)
Reg
=
0
;
}
if
(
Reg
)
return
Reg
;
report_fatal_error
(
Twine
(
"Invalid register name \""
+
StringRef
(
RegName
)
+
"\"."
)
)
;
}
</s>

Return the register ID of the name passed in .


"AltiVec argument passed to unprototyped function"

Target hook for invalid_arg_for_unprototyped_fn .


<s> bool z8k_regno_ok_for_index_p ( int regno , bool strict_p ) { if ( regno < FIRST_PSEUDO_REGISTER ) { if ( ! strict_p ) return true ; if ( ! reg_renumber ) return false ; regno = reg_renumber [ regno ] ; } return regno < FIRST_PSEUDO_REGISTER && regno >= 0 ; } </s>

These assume that REGNO is a hard or pseudo reg number . They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg . Since they use reg_renumber , they are safe only once reg_renumber has been allocated , which happens in local-alloc.c .


<s> static bool iq2000_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return ( REGNO_REG_CLASS ( regno ) == GR_REGS ? ( regno & 1 ) == 0 || GET_MODE_SIZE ( mode ) <= 4 : ( regno & 1 ) == 0 || GET_MODE_SIZE ( mode ) == 4 ) ; } </s>


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const MCConstantExpr * ConstExpr = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( static_cast < int32_t > ( ConstExpr -> getValue ( ) ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> static bool m32r_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total ) { switch ( code ) { case CONST_INT : if ( INT16_P ( INTVAL ( x ) ) ) { * total = 0 ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( 1 ) ; return true ; case CONST_DOUBLE : { rtx high , low ; split_double ( x , & high , & low ) ; * total = COSTS_N_INSNS ( ! INT16_P ( INTVAL ( high ) ) + ! INT16_P ( INTVAL ( low ) ) ) ; return true ; } case MULT : * total = COSTS_N_INSNS ( 3 ) ; return true ; case DIV : case UDIV : case MOD : case UMOD : * total = COSTS_N_INSNS ( 10 ) ; return true ; default : return false ; } } </s>


<s> bool legitimate_address_p ( enum machine_mode mode , rtx x , int strict ) { if ( CONSTANT_ADDRESS_P ( x ) && ( ! flag_pic || legitimate_pic_operand_p ( x ) ) ) return TRUE ; if ( RTX_OK_FOR_BASE_P ( x , strict ) ) return TRUE ; if ( TARGET_AM33 && GET_CODE ( x ) == POST_INC && RTX_OK_FOR_BASE_P ( XEXP ( x , 0 ) , strict ) && ( mode == SImode || mode == SFmode || mode == HImode ) ) return TRUE ; if ( GET_CODE ( x ) == PLUS ) { rtx base = 0 , index = 0 ; if ( REG_P ( XEXP ( x , 0 ) ) && REGNO_STRICT_OK_FOR_BASE_P ( REGNO ( XEXP ( x , 0 ) ) , strict ) ) { base = XEXP ( x , 0 ) ; index = XEXP ( x , 1 ) ; } if ( REG_P ( XEXP ( x , 1 ) ) && REGNO_STRICT_OK_FOR_BASE_P ( REGNO ( XEXP ( x , 1 ) ) , strict ) ) { base = XEXP ( x , 1 ) ; index = XEXP ( x , 0 ) ; } if ( base != 0 && index != 0 ) { if ( GET_CODE ( index ) == CONST_INT ) return TRUE ; if ( GET_CODE ( index ) == CONST && GET_CODE ( XEXP ( index , 0 ) ) != PLUS && ( ! flag_pic || legitimate_pic_operand_p ( index ) ) ) return TRUE ; } } return FALSE ; } </s>

legitimate_address_p returns 1 if it recognizes an RTL expression `` x '' that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address .


<s> inline void assign_registers ( const_tree field , int bitpos , bool fp , assign_data_t * data ) { if ( fp ) { assign_int_registers ( bitpos , data ) ; assign_fp_registers ( field , bitpos , data ) ; } else { if ( data -> intoffset < 0 ) data -> intoffset = bitpos ; } } </s>

A subroutine of function_arg_record_value . Assign FIELD and the bits of the structure between PARMS- > intoffset and BITPOS to registers .


<s> void UPTMCInstLower :: Initialize ( MCContext * C ) { Ctx = C ; } </s>

This method must be called before any actual lowering is done .


<s> long compute_frame_size ( int size ) { int regno ; if ( reload_completed && cfun -> machine -> frame_laid_out ) return cfun -> machine -> current_frame_size ; if ( cfun -> static_chain_decl != NULL ) size += ( 1 * UNITS_PER_WORD ) ; cfun -> machine -> callee_save_size = 0 ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; ++ regno ) { if ( xtensa_call_save_reg ( regno ) ) cfun -> machine -> callee_save_size += UNITS_PER_WORD ; } cfun -> machine -> current_frame_size = XTENSA_STACK_ALIGN ( size + cfun -> machine -> callee_save_size + crtl -> outgoing_args_size + ( WINDOW_SIZE * UNITS_PER_WORD ) ) ; cfun -> machine -> callee_save_size = XTENSA_STACK_ALIGN ( cfun -> machine -> callee_save_size ) ; cfun -> machine -> frame_laid_out = true ; return cfun -> machine -> current_frame_size ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> int ia64_ld_address_bypass_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx dest , src , reg , mem ; gcc_assert ( producer && consumer ) ; dest = ia64_single_set ( producer ) ; gcc_assert ( dest ) ; reg = SET_DEST ( dest ) ; gcc_assert ( reg ) ; if ( GET_CODE ( reg ) == SUBREG ) reg = SUBREG_REG ( reg ) ; gcc_assert ( GET_CODE ( reg ) == REG ) ; src = ia64_single_set ( consumer ) ; gcc_assert ( src ) ; mem = SET_SRC ( src ) ; gcc_assert ( mem ) ; if ( GET_CODE ( mem ) == UNSPEC && XVECLEN ( mem , 0 ) > 0 ) mem = XVECEXP ( mem , 0 , 0 ) ; else if ( GET_CODE ( mem ) == IF_THEN_ELSE ) { gcc_assert ( XINT ( XEXP ( XEXP ( mem , 0 ) , 0 ) , 1 ) == UNSPEC_LDCCLR ) ; mem = XEXP ( mem , 1 ) ; } while ( GET_CODE ( mem ) == SUBREG || GET_CODE ( mem ) == ZERO_EXTEND ) mem = XEXP ( mem , 0 ) ; if ( GET_CODE ( mem ) == UNSPEC ) { int c = XINT ( mem , 1 ) ; gcc_assert ( c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A || c == UNSPEC_LDSA ) ; mem = XVECEXP ( mem , 0 , 0 ) ; } gcc_assert ( GET_CODE ( mem ) == LO_SUM || GET_CODE ( mem ) == MEM ) ; return reg_mentioned_p ( reg , mem ) ; } </s>

The following function returns TRUE if PRODUCER ( of type ilog or ld ) produces address for CONSUMER ( of type ld or fld ) .


<s> static void nios2_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * pretend_size , int second_time ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; CUMULATIVE_ARGS local_cum ; cumulative_args_t local_cum_v = pack_cumulative_args ( & local_cum ) ; int regs_to_push ; int pret_size ; cfun -> machine -> uses_anonymous_args = 1 ; local_cum = * cum ; nios2_function_arg_advance ( local_cum_v , arg ) ; regs_to_push = NUM_ARG_REGS - local_cum . regs_used ; if ( ! TARGET_HAS_CDX && ! second_time && regs_to_push > 0 ) { rtx ptr = virtual_incoming_args_rtx ; rtx mem = gen_rtx_MEM ( BLKmode , ptr ) ; emit_insn ( gen_blockage ( ) ) ; move_block_from_reg ( local_cum . regs_used + FIRST_ARG_REGNO , mem , regs_to_push ) ; emit_insn ( gen_blockage ( ) ) ; } pret_size = regs_to_push * UNITS_PER_WORD ; if ( pret_size ) * pretend_size = pret_size ; } </s>

TODO : It may be possible to eliminate the copyback and implement own va_arg type .


<s>
bool
HexagonAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
if
(
!
InBrackets
)
{
MCB
.
clear
(
)
;
MCB
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
}
HexagonOperand
&
FirstOperand
=
static_cast
<
HexagonOperand
&
>
(
*
Operands
[
0
]
)
;
if
(
FirstOperand
.
isToken
(
)
&&
FirstOperand
.
getToken
(
)
==
"{"
)
{
assert
(
Operands
.
size
(
)
==
1
&&
"Brackets should be by themselves"
)
;
if
(
InBrackets
)
{
getParser
(
)
.
Error
(
IDLoc
,
"Already in a packet"
)
;
return
true
;
}
InBrackets
=
true
;
return
false
;
}
if
(
FirstOperand
.
isToken
(
)
&&
FirstOperand
.
getToken
(
)
==
"}"
)
{
assert
(
Operands
.
size
(
)
==
1
&&
"Brackets should be by themselves"
)
;
if
(
!
InBrackets
)
{
getParser
(
)
.
Error
(
IDLoc
,
"Not in a packet"
)
;
return
true
;
}
InBrackets
=
false
;
if
(
matchBundleOptions
(
)
)
return
true
;
return
finishBundle
(
IDLoc
,
Out
)
;
}
MCInst
*
SubInst
=
new
(
getParser
(
)
.
getContext
(
)
)
MCInst
;
bool
MustExtend
=
false
;
if
(
matchOneInstruction
(
*
SubInst
,
IDLoc
,
Operands
,
ErrorInfo
,
MatchingInlineAsm
,
MustExtend
)
)
return
true
;
HexagonMCInstrInfo
::
extendIfNeeded
(
getParser
(
)
.
getContext
(
)
,
MCII
,
MCB
,
*
SubInst
,
HexagonMCInstrInfo
::
isExtended
(
MCII
,
*
SubInst
)
||
MustExtend
)
;
MCB
.
addOperand
(
MCOperand
::
createInst
(
SubInst
)
)
;
if
(
!
InBrackets
)
return
finishBundle
(
IDLoc
,
Out
)
;
return
false
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

Hexagon
Hexagon
0
Hexagon
Hexagon
0
"{"
1
"Brackets should be by themselves"
"Already in a packet"
"}"
1
"Brackets should be by themselves"
"Not in a packet"
Hexagon
Hexagon