<s> bool HexagonSplitConst32AndConst64 :: runOnMachineFunction ( MachineFunction & Fn ) { auto & HST = Fn . getSubtarget < HexagonSubtarget > ( ) ; auto & HTM = static_cast < const HexagonTargetMachine & > ( Fn . getTarget ( ) ) ; auto & TLOF = * HTM . getObjFileLowering ( ) ; if ( HST . useSmallData ( ) && TLOF . isSmallDataEnabled ( HTM ) ) return false ; const TargetInstrInfo * TII = HST . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = HST . getRegisterInfo ( ) ; for ( MachineBasicBlock & B : Fn ) { for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; ) { MachineInstr & MI = * I ; ++ I ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == Hexagon :: CONST32 ) { Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( 1 ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == Hexagon :: CONST64 ) { Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; int64_t ImmValue = MI . getOperand ( 1 ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register DestLo = TRI -> getSubReg ( DestReg , Hexagon :: isub_lo ) ; Register DestHi = TRI -> getSubReg ( DestReg , Hexagon :: isub_hi ) ; int32_t LowWord = ( ImmValue & 0xFFFFFFFF ) ; int32_t HighWord = ( ImmValue >> 32 ) & 0xFFFFFFFF ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestLo ) . addImm ( LowWord ) ; BuildMI ( B , MI , DL , TII -> get ( Hexagon :: A2_tfrsi ) , DestHi ) . addImm ( HighWord ) ; B . erase ( & MI ) ; } } } return true ; } </s>


<s> bool ix86_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int flags ) { struct gcc_options func_options , func_options_set ; tree new_target , new_optimize ; bool ret = true ; if ( TREE_VALUE ( args ) && TREE_CODE ( TREE_VALUE ( args ) ) == STRING_CST && TREE_CHAIN ( args ) == NULL_TREE && strcmp ( TREE_STRING_POINTER ( TREE_VALUE ( args ) ) , "default" ) == 0 ) return true ; tree old_optimize = build_optimization_node ( & global_options , & global_options_set ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , 0 , sizeof ( func_options_set ) ) ; cl_optimization_restore ( & func_options , & func_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , & func_options_set , TREE_TARGET_OPTION ( target_option_default_node ) ) ; new_target = ix86_valid_target_attribute_tree ( fndecl , args , & func_options , & func_options_set , flags == 1 ) ; new_optimize = build_optimization_node ( & func_options , & func_options_set ) ; if ( new_target == error_mark_node ) ret = false ; else if ( fndecl && new_target ) { DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ; if ( old_optimize != new_optimize ) DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; } return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


<s> unsigned getPointerSize ( ) const { return 4 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> bool WebAssemblyTargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { if ( ! Subtarget -> hasUnimplementedSIMD128 ( ) ) return false ; MVT ExtT = ExtVal . getSimpleValueType ( ) ; MVT MemT = cast < LoadSDNode > ( ExtVal -> getOperand ( 0 ) ) -> getSimpleValueType ( 0 ) ; return ( ExtT == MVT :: v8i16 && MemT == MVT :: v8i8 ) || ( ExtT == MVT :: v4i32 && MemT == MVT :: v4i16 ) || ( ExtT == MVT :: v2i64 && MemT == MVT :: v2i32 ) ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> static bool has_vl_op ( rtx_insn * rinsn ) { return recog_memoized ( rinsn ) >= 0 && get_attr_has_vl_op ( rinsn ) ; } </s>

Return true if it is an RVV instruction depends on VL global status register .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Patmos Single-Path Info"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> bool runOnMachineFunction ( MachineFunction & MF ) { DEBUG ( MF . dump ( ) ; ) ; OrderedBlks . clear ( ) ; FuncRep = & MF ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; DEBUG ( dbgs ( ) << "LoopInfo:\n" ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; DEBUG ( MDT -> print ( dbgs ( ) , ( const llvm :: Module * ) 0 ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; DEBUG ( MF . dump ( ) ; ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool BPFAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , O ) ; printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
unsigned
MipsSEInstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BEQ
:
return
Mips
::
BNE
;
case
Mips
::
BNE
:
return
Mips
::
BEQ
;
case
Mips
::
BGTZ
:
return
Mips
::
BLEZ
;
case
Mips
::
BGEZ
:
return
Mips
::
BLTZ
;
case
Mips
::
BLTZ
:
return
Mips
::
BGEZ
;
case
Mips
::
BLEZ
:
return
Mips
::
BGTZ
;
case
Mips
::
BC1T
:
return
Mips
::
BC1F
;
case
Mips
::
BC1F
:
return
Mips
::
BC1T
;
}
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .

Mips
Mips
"Illegal opcode!"
Mips::BEQ
Mips::BNE
Mips::BNE
Mips::BEQ
Mips::BGTZ
Mips::BLEZ
Mips::BGEZ
Mips::BLTZ
Mips::BLTZ
Mips::BGEZ
Mips::BLEZ
Mips::BGTZ
Mips::BC1T
Mips::BC1F
Mips::BC1F
Mips::BC1T


<s> int arm_max_const_double_inline_cost ( ) { return ( ( optimize_size || arm_ld_sched ) ? 3 : 4 ) ; } </s>

Return maximum allowed cost of synthesizing a 64-bit constant VAL inline . Returns the number of insns needed , or 99 if we always want to synthesize the value .


<s> bool contains ( MachineInstr * MI ) { return liveInstrs . count ( MI ) ; } </s>

contains - Returns true if this trace contains the given basic block .


<s> bool ARMBaseTargetMachine :: addPreSched2 ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createARMLoadStoreOptimizationPass ( ) ) ; if ( Subtarget . hasNEON ( ) ) PM . add ( createExecutionDependencyFixPass ( & ARM :: DPRRegClass ) ) ; } PM . add ( createARMExpandPseudoPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) PM . add ( createThumb2ITBlockPass ( ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .


"Can only insert epilog into returning blocks"


"constant argument %d for builtin %qF is out of range (0.."

"constant argument %d for builtin %qF is out of range ("

Return true if ARG is appropriate as argument number ARGNUM of builtin DECL . The operand flags from s390-builtins.def have to passed as OP_FLAGS .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> auto HexagonVectorCombine :: concat ( IRBuilder < > & Builder , ArrayRef < Value * > Vecs ) const -> Value * { assert ( ! Vecs . empty ( ) ) ; SmallVector < int , 256 > SMask ; std :: vector < Value * > Work [ 2 ] ; int ThisW = 0 , OtherW = 1 ; Work [ ThisW ] . assign ( Vecs . begin ( ) , Vecs . end ( ) ) ; while ( Work [ ThisW ] . size ( ) > 1 ) { auto * Ty = cast < VectorType > ( Work [ ThisW ] . front ( ) -> getType ( ) ) ; int ElemCount = Ty -> getElementCount ( ) . getFixedValue ( ) ; SMask . resize ( ElemCount * 2 ) ; std :: iota ( SMask . begin ( ) , SMask . end ( ) , 0 ) ; Work [ OtherW ] . clear ( ) ; if ( Work [ ThisW ] . size ( ) % 2 != 0 ) Work [ ThisW ] . push_back ( UndefValue :: get ( Ty ) ) ; for ( int i = 0 , e = Work [ ThisW ] . size ( ) ; i < e ; i += 2 ) { Value * Joined = Builder . CreateShuffleVector ( Work [ ThisW ] [ i ] , Work [ ThisW ] [ i + 1 ] , SMask ) ; Work [ OtherW ] . push_back ( Joined ) ; } std :: swap ( ThisW , OtherW ) ; } SMask . resize ( Vecs . size ( ) * getSizeOf ( Vecs . front ( ) -> getType ( ) ) ) ; std :: iota ( SMask . begin ( ) , SMask . end ( ) , 0 ) ; Value * Total = Work [ OtherW ] . front ( ) ; return Builder . CreateShuffleVector ( Total , SMask ) ; } </s>

Concatenate the bits from Lo onto the bottom of * this .


<s>
static
wasm
::
ValType
getType
(
const
TargetRegisterClass
*
RC
)
{
if
(
RC
==
&
WebAssembly
::
I32RegClass
)
return
wasm
::
ValType
::
I32
;
if
(
RC
==
&
WebAssembly
::
I64RegClass
)
return
wasm
::
ValType
::
I64
;
if
(
RC
==
&
WebAssembly
::
F32RegClass
)
return
wasm
::
ValType
::
F32
;
if
(
RC
==
&
WebAssembly
::
F64RegClass
)
return
wasm
::
ValType
::
F64
;
if
(
RC
==
&
WebAssembly
::
V128RegClass
)
return
wasm
::
ValType
::
V128
;
llvm_unreachable
(
"Unexpected register class"
)
;
}
</s>

Overload to return most specific vector type .


<s> static void ix86_adjust_stack_and_probe ( const HOST_WIDE_INT size ) { const int dope = 4 * UNITS_PER_WORD ; rtx size_rtx = GEN_INT ( size ) , last ; if ( size <= 4 * PROBE_INTERVAL ) { HOST_WIDE_INT i , adjust ; bool first_probe = true ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) { if ( first_probe ) { adjust = 2 * PROBE_INTERVAL + dope ; first_probe = false ; } else adjust = PROBE_INTERVAL ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - adjust ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; } if ( first_probe ) adjust = size + PROBE_INTERVAL + dope ; else adjust = size + PROBE_INTERVAL - i ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - adjust ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; last = emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; } else { HOST_WIDE_INT rounded_size ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( PROBE_INTERVAL + dope ) ) ) ) ; if ( rounded_size <= ( HOST_WIDE_INT_1 << 31 ) ) emit_insn ( gen_rtx_SET ( sr . reg , plus_constant ( Pmode , stack_pointer_rtx , - rounded_size ) ) ) ; else { emit_move_insn ( sr . reg , GEN_INT ( - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( sr . reg , gen_rtx_PLUS ( Pmode , sr . reg , stack_pointer_rtx ) ) ) ; } emit_insn ( ix86_gen_adjust_stack_and_probe ( sr . reg , sr . reg , size_rtx ) ) ; if ( size != rounded_size ) { emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , rounded_size - size ) ) ) ; emit_stack_probe ( stack_pointer_rtx ) ; } last = emit_insn ( gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope ) ) ) ; release_scratch_register_on_entry ( & sr ) ; } if ( size > 0 ) { rtx expr = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( expr , 0 , 0 ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - size ) ) ; XVECEXP ( expr , 0 , 1 ) = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , PROBE_INTERVAL + dope + size ) ) ; add_reg_note ( last , REG_FRAME_RELATED_EXPR , expr ) ; RTX_FRAME_RELATED_P ( last ) = 1 ; cfun -> machine -> fs . sp_offset += size ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Emit code to adjust the stack pointer by SIZE bytes while probing it .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> int s390_mem_constraint ( const char * str , rtx op ) { char c = str [ 0 ] ; switch ( c ) { case 'A' : if ( ! MEM_P ( op ) || MEM_VOLATILE_P ( op ) ) return 0 ; if ( ( reload_completed || reload_in_progress ) ? ! offsettable_memref_p ( op ) : ! offsettable_nonstrict_memref_p ( op ) ) return 0 ; return s390_check_qrst_address ( str [ 1 ] , XEXP ( op , 0 ) , true ) ; case 'B' : if ( ! MEM_P ( op ) ) return 0 ; return s390_check_qrst_address ( str [ 1 ] , XEXP ( op , 0 ) , false ) ; case 'Q' : case 'R' : case 'S' : case 'T' : if ( GET_CODE ( op ) != MEM ) return 0 ; return s390_check_qrst_address ( c , XEXP ( op , 0 ) , true ) ; case 'U' : return ( s390_check_qrst_address ( 'Q' , op , true ) || s390_check_qrst_address ( 'R' , op , true ) ) ; case 'W' : return ( s390_check_qrst_address ( 'S' , op , true ) || s390_check_qrst_address ( 'T' , op , true ) ) ; case 'Y' : if ( ! s390_decompose_addrstyle_without_index ( op , NULL , NULL ) ) return 0 ; break ; case 'Z' : return s390_check_qrst_address ( str [ 1 ] , op , true ) ; default : return 0 ; } return 1 ; } </s>

Evaluates constraint strings described by the regular expression ( [ A|B|Z ] ( Q|R|S|T ) ) |U|W|Y and returns 1 if OP is a valid operand for the constraint given in STR , or 0 else .


<s> void sparc_expand_epilogue ( void ) { if ( num_gfregs ) emit_save_or_restore_regs ( SORR_RESTORE ) ; if ( actual_fsize == 0 ) ; else if ( sparc_leaf_function_p ) { if ( actual_fsize <= 4096 ) emit_insn ( gen_stack_pointer_dec ( GEN_INT ( - actual_fsize ) ) ) ; else if ( actual_fsize <= 8192 ) { emit_insn ( gen_stack_pointer_dec ( GEN_INT ( - 4096 ) ) ) ; emit_insn ( gen_stack_pointer_dec ( GEN_INT ( 4096 - actual_fsize ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( reg , GEN_INT ( - actual_fsize ) ) ; emit_insn ( gen_stack_pointer_dec ( reg ) ) ; } } } </s>

Expand the function epilogue , either normal or part of a sibcall . We emit all the instructions except the return or the call .


<s> int SIInstrInfo :: pseudoToMCOpcode ( int Opcode ) const { SIEncodingFamily Gen = subtargetEncodingFamily ( ST ) ; if ( ( get ( Opcode ) . TSFlags & SIInstrFlags :: renamedInGFX9 ) != 0 && ST . getGeneration ( ) >= SISubtarget :: GFX9 ) Gen = SIEncodingFamily :: GFX9 ; if ( get ( Opcode ) . TSFlags & SIInstrFlags :: SDWA ) Gen = ST . getGeneration ( ) == SISubtarget :: GFX9 ? SIEncodingFamily :: SDWA9 : SIEncodingFamily :: SDWA ; if ( ST . hasUnpackedD16VMem ( ) && ( get ( Opcode ) . TSFlags & SIInstrFlags :: D16Buf ) ) Gen = SIEncodingFamily :: GFX80 ; int MCOp = AMDGPU :: getMCOpcode ( Opcode , Gen ) ; if ( MCOp == - 1 ) return Opcode ; if ( MCOp == ( uint16_t ) - 1 ) return - 1 ; return MCOp ; } </s>

Return a target-specific opcode if Opcode is a pseudo instruction .


<s> void ARMPassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( ) ) ; addPass ( new ARMExecutionDomainFix ( ) ) ; addPass ( createBreakFalseDeps ( ) ) ; } addPass ( createARMExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < ARMSubtarget > ( F ) . hasMinSize ( ) || this -> TM -> getSubtarget < ARMSubtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < ARMSubtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createThumb2ITBlockPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & PostMachineSchedulerID ) ; addPass ( & PostRASchedulerID ) ; } addPass ( createMVEVPTBlockPass ( ) ) ; addPass ( createARMIndirectThunks ( ) ) ; addPass ( createARMSLSHardeningPass ( ) ) ; } </s>

ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM ARM


<s>
unsigned
TL45InstrInfo
::
loadImmediate
(
unsigned
FrameReg
,
int64_t
Imm
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
II
,
const
DebugLoc
&
DL
,
unsigned
&
NewImm
)
const
{
llvm_unreachable
(
"not yet implemented loadImmediate()"
)
;
}
</s>

Emit a series of instructions to load an immediate .


"ACLE function %qD is incompatible with the use of %qs"

Check whether the registers required by SVE function fndecl are available . Report an error against LOCATION and return false if not .


<s> void push ( NodeAddr < DefNode * > DA ) { Stack . push_back ( DA ) ; } </s>


<s>
MachineBasicBlock
*
VETargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown Custom Instruction!"
)
;
case
VE
::
EH_SjLj_LongJmp
:
return
emitEHSjLjLongJmp
(
MI
,
BB
)
;
case
VE
::
EH_SjLj_SetJmp
:
return
emitEHSjLjSetJmp
(
MI
,
BB
)
;
case
VE
::
EH_SjLj_Setup_Dispatch
:
return
emitSjLjDispatchBlock
(
MI
,
BB
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
bool
R600Packetizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
TargetInstrInfo
*
TII
=
Fn
.
getTarget
(
)
.
getInstrInfo
(
)
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MachineDominatorTree
&
MDT
=
getAnalysis
<
MachineDominatorTree
>
(
)
;
R600PacketizerList
Packetizer
(
Fn
,
MLI
,
MDT
)
;
assert
(
Packetizer
.
getResourceTracker
(
)
&&
"Empty DFA table!"
)
;
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
MachineBasicBlock
::
iterator
End
=
MBB
->
end
(
)
;
MachineBasicBlock
::
iterator
MI
=
MBB
->
begin
(
)
;
while
(
MI
!=
End
)
{
if
(
MI
->
isKill
(
)
||
MI
->
getOpcode
(
)
==
AMDGPU
::
IMPLICIT_DEF
||
(
MI
->
getOpcode
(
)
==
AMDGPU
::
CF_ALU
&&
!
MI
->
getOperand
(
8
)
.
getImm
(
)
)
)
{
MachineBasicBlock
::
iterator
DeleteMI
=
MI
;
++
MI
;
MBB
->
erase
(
DeleteMI
)
;
End
=
MBB
->
end
(
)
;
continue
;
}
++
MI
;
}
}
for
(
MachineFunction
::
iterator
MBB
=
Fn
.
begin
(
)
,
MBBe
=
Fn
.
end
(
)
;
MBB
!=
MBBe
;
++
MBB
)
{
unsigned
RemainingCount
=
MBB
->
size
(
)
;
for
(
MachineBasicBlock
::
iterator
RegionEnd
=
MBB
->
end
(
)
;
RegionEnd
!=
MBB
->
begin
(
)
;
)
{
MachineBasicBlock
::
iterator
I
=
RegionEnd
;
for
(
;
I
!=
MBB
->
begin
(
)
;
I
,
RemainingCount
)
{
if
(
TII
->
isSchedulingBoundary
(
llvm
::
prior
(
I
)
,
MBB
,
Fn
)
)
break
;
}
I
=
MBB
->
begin
(
)
;
if
(
I
==
RegionEnd
)
{
RegionEnd
=
llvm
::
prior
(
RegionEnd
)
;
RemainingCount
;
continue
;
}
if
(
I
==
llvm
::
prior
(
RegionEnd
)
)
{
RegionEnd
=
llvm
::
prior
(
RegionEnd
)
;
continue
;
}
Packetizer
.
PacketizeMIs
(
MBB
,
I
,
RegionEnd
)
;
RegionEnd
=
I
;
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool SPIRVMCAsmInfo :: shouldOmitSectionDirective ( StringRef SectionName ) const { return true ; } </s>

Return true if the .section directive should be omitted when emitting SectionName .


<s> bool s390_overlap_p ( rtx mem1 , rtx mem2 , HOST_WIDE_INT size ) { rtx addr1 , addr2 , addr_delta ; HOST_WIDE_INT delta ; if ( GET_CODE ( mem1 ) != MEM || GET_CODE ( mem2 ) != MEM ) return true ; if ( size == 0 ) return false ; addr1 = XEXP ( mem1 , 0 ) ; addr2 = XEXP ( mem2 , 0 ) ; addr_delta = simplify_binary_operation ( MINUS , Pmode , addr2 , addr1 ) ; if ( ! addr_delta || GET_CODE ( addr_delta ) != CONST_INT ) return false ; delta = INTVAL ( addr_delta ) ; if ( delta == 0 || ( delta > 0 && delta < size ) || ( delta < 0 && - delta < size ) ) return true ; return false ; } </s>

Return true if it can be proven that [ MEM1 , MEM1 + SIZE ] and [ MEM2 , MEM2 + SIZE ] do overlap and false otherwise .


<s> bool isThumb ( ) const { return IsThumb ; } </s>

Tests whether the target is Thumb ( little and big endian ) .


<s> unsigned X86TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: v32i1 && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return 1 ; if ( VT . isVector ( ) && VT . getVectorElementType ( ) == MVT :: i1 && Subtarget . hasAVX512 ( ) && ( ! isPowerOf2_32 ( VT . getVectorNumElements ( ) ) || ( VT . getVectorNumElements ( ) > 16 && ! Subtarget . hasBWI ( ) ) || ( VT . getVectorNumElements ( ) > 64 && Subtarget . hasBWI ( ) ) ) ) return VT . getVectorNumElements ( ) ; if ( ( VT == MVT :: v32i16 || VT == MVT :: v64i8 ) && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) && ! EnableOldKNLABI ) return 1 ; return TargetLowering :: getNumRegistersForCallingConv ( Context , CC , VT ) ; } </s>

Certain targets require unusual breakdowns of certain types .


<s> MachineMemOperand * NyuziInstrInfo :: getMemOperand ( MachineBasicBlock & MBB , int FI , MachineMemOperand :: Flags Flags ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , Flags , MFI . getObjectSize ( FI ) , Align ) ; } </s>

Return a MachineMemOperand object describing the memory reference performed by operation .


<s> static void mips_expand_msa_cmp ( rtx dest , enum rtx_code cond , rtx op0 , rtx op1 ) { machine_mode cmp_mode = GET_MODE ( op0 ) ; int unspec = - 1 ; bool negate = false ; switch ( cmp_mode ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : switch ( cond ) { case NE : cond = reverse_condition ( cond ) ; negate = true ; break ; case EQ : case LT : case LE : case LTU : case LEU : break ; case GE : case GT : case GEU : case GTU : std :: swap ( op0 , op1 ) ; cond = swap_condition ( cond ) ; break ; default : gcc_unreachable ( ) ; } mips_emit_binary ( cond , dest , op0 , op1 ) ; if ( negate ) emit_move_insn ( dest , gen_rtx_NOT ( GET_MODE ( dest ) , dest ) ) ; break ; case V4SFmode : case V2DFmode : switch ( cond ) { case UNORDERED : case ORDERED : case EQ : case NE : case UNEQ : case UNLE : case UNLT : break ; case LTGT : cond = NE ; break ; case UNGE : cond = UNLE ; std :: swap ( op0 , op1 ) ; break ; case UNGT : cond = UNLT ; std :: swap ( op0 , op1 ) ; break ; case LE : unspec = UNSPEC_MSA_FSLE ; break ; case LT : unspec = UNSPEC_MSA_FSLT ; break ; case GE : unspec = UNSPEC_MSA_FSLE ; std :: swap ( op0 , op1 ) ; break ; case GT : unspec = UNSPEC_MSA_FSLT ; std :: swap ( op0 , op1 ) ; break ; default : gcc_unreachable ( ) ; } if ( unspec < 0 ) mips_emit_binary ( cond , dest , op0 , op1 ) ; else { rtx x = gen_rtx_UNSPEC ( GET_MODE ( dest ) , gen_rtvec ( 2 , op0 , op1 ) , unspec ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } break ; default : gcc_unreachable ( ) ; break ; } } </s>

Generate RTL for comparing CMP_OP0 and CMP_OP1 using condition COND and store the result -1 or 0 in DEST .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { ARM64FI = F . getInfo < ARM64FunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction ( F ) ; } </s>


<s> static void scan_record_type ( tree type , int * intregs_p , int * fpregs_p , int * packed_p ) { tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) scan_record_type ( TREE_TYPE ( field ) , intregs_p , fpregs_p , 0 ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU ) * fpregs_p = 1 ; else * intregs_p = 1 ; if ( packed_p && DECL_PACKED ( field ) ) * packed_p = 1 ; } } } </s>

Scan the record type TYPE and return the following predicates : - INTREGS_P : the record contains at least one field or sub-field that is eligible for promotion in integer registers . - FP_REGS_P : the record contains at least one field or sub-field that is eligible for promotion in floating-point registers . - PACKED_P : the record contains at least one field that is packed . Sub-fields are not taken into account for the PACKED_P predicate .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( ! EnablePPCPreinc ) return false ; SDValue Ptr ; EVT VT ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> bool XCoreFrameLowering :: hasFP ( const MachineFunction & MF ) const { return DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> unsigned X86AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: EVEX ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: VEX ) return Match_Unsupported ; switch ( Opc ) { case X86 :: VCVTSD2SIZrm_Int : case X86 :: VCVTSD2SI64Zrm_Int : case X86 :: VCVTSS2SIZrm_Int : case X86 :: VCVTSS2SI64Zrm_Int : case X86 :: VCVTTSD2SIZrm : case X86 :: VCVTTSD2SIZrm_Int : case X86 :: VCVTTSD2SI64Zrm : case X86 :: VCVTTSD2SI64Zrm_Int : case X86 :: VCVTTSS2SIZrm : case X86 :: VCVTTSS2SIZrm_Int : case X86 :: VCVTTSS2SI64Zrm : case X86 :: VCVTTSS2SI64Zrm_Int : if ( ForcedVEXEncoding != VEXEncoding_EVEX ) return Match_Unsupported ; break ; } return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> SDValue SystemZSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool IsVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { if ( IsVolatile ) return SDValue ( ) ; if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) return emitMemMem ( DAG , DL , SystemZISD :: MVC , SystemZISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .

SystemZ SystemZ SystemZISD::MVC SystemZISD::MVC_LOOP


"the ABI of passing aggregates with %d-byte alignment"

If defined , a C expression that gives the alignment boundary , in bits , of an argument with the specified mode and type . If it is not defined , PARM_BOUNDARY is used for all arguments . V.4 wants long longs and doubles to be double word aligned . Just testing the mode size is a boneheaded way to do this as it means that other types such as complex int are also double word aligned . However , we 're stuck with this because changing the ABI might break existing library interfaces . Quadword align Altivec/VSX vectors . Quadword align large synthetic vector types .


<s>
static
void
add_sve_type_attribute
(
tree
type
,
unsigned
int
num_zr
,
unsigned
int
num_pr
,
const
char
*
mangled_name
)
{
tree
mangled_name_tree
=
(
mangled_name
get_identifier
(
mangled_name
)
:
NULL_TREE
)
;
tree
value
=
tree_cons
(
NULL_TREE
,
mangled_name_tree
,
NULL_TREE
)
;
value
=
tree_cons
(
NULL_TREE
,
size_int
(
num_pr
)
,
value
)
;
value
=
tree_cons
(
NULL_TREE
,
size_int
(
num_zr
)
,
value
)
;
TYPE_ATTRIBUTES
(
type
)
=
tree_cons
(
get_identifier
(
"SVE type"
)
,
value
,
TYPE_ATTRIBUTES
(
type
)
)
;
}
</s>

Record that TYPE is an ABI-defined SVE type that contains NUM_ZR SVE vectors and NUM_PR SVE predicates . MANGLED_NAME , if nonnull , is the ABI-defined mangling of the type . ACLE_NAME is the < arm_sve.h > name of the type .


<s> bool arc_is_uncached_mem_p ( rtx pat ) { tree attrs ; tree ttype ; struct mem_attrs * refattrs ; if ( ! MEM_P ( pat ) ) return false ; refattrs = MEM_ATTRS ( pat ) ; if ( ! refattrs || ! refattrs -> expr ) return false ; ttype = TREE_TYPE ( refattrs -> expr ) ; if ( ! ttype ) return false ; attrs = TYPE_ATTRIBUTES ( ttype ) ; if ( lookup_attribute ( "uncached" , attrs ) ) return true ; return false ; } </s>

Return TRUE if PAT is a memory addressing an uncached data .


<s> bool ARMBaseInstrInfo :: hasHighOperandLatency ( const InstrItineraryData * ItinData , const MachineRegisterInfo * MRI , const MachineInstr * DefMI , unsigned DefIdx , const MachineInstr * UseMI , unsigned UseIdx ) const { unsigned DDomain = DefMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; unsigned UDomain = UseMI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Subtarget . isCortexA8 ( ) && ( DDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainVFP ) ) return true ; int Latency = getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( Latency <= 3 ) return false ; return DDomain == ARMII :: DomainVFP || DDomain == ARMII :: DomainNEON || UDomain == ARMII :: DomainVFP || UDomain == ARMII :: DomainNEON ; } </s>

Compute operand latency between a def of 'Reg ' and a use in the current loop .

ARM ARM ARMII::DomainMask ARMII::DomainMask ARMII::DomainVFP ARMII::DomainVFP 3 ARMII::DomainVFP ARMII::DomainNEON ARMII::DomainVFP ARMII::DomainNEON


<s> bool SITargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & CI , MachineFunction & MF , unsigned IntrID ) const { if ( const AMDGPU :: RsrcIntrinsic * RsrcIntr = AMDGPU :: lookupRsrcIntrinsic ( IntrID ) ) { AttributeList Attr = Intrinsic :: getAttributes ( CI . getContext ( ) , ( Intrinsic :: ID ) IntrID ) ; if ( Attr . hasFnAttribute ( Attribute :: ReadNone ) ) return false ; SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; if ( RsrcIntr -> IsImage ) { Info . ptrVal = MFI -> getImagePSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; Info . align = 0 ; } else { Info . ptrVal = MFI -> getBufferPSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; } Info . flags = MachineMemOperand :: MODereferenceable ; if ( Attr . hasFnAttribute ( Attribute :: ReadOnly ) ) { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) , true ) ; if ( Info . memVT == MVT :: Other ) { Info . memVT = memVTFromAggregate ( CI . getType ( ) ) ; } Info . flags |= MachineMemOperand :: MOLoad ; } else if ( Attr . hasFnAttribute ( Attribute :: WriteOnly ) ) { Info . opc = ISD :: INTRINSIC_VOID ; Info . memVT = MVT :: getVT ( CI . getArgOperand ( 0 ) -> getType ( ) ) ; Info . flags |= MachineMemOperand :: MOStore ; } else { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MODereferenceable ; Info . flags |= MachineMemOperand :: MOVolatile ; } return true ; } switch ( IntrID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( 0 ) ; Info . align = 0 ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( 4 ) ) ; if ( ! Vol || ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } default : return false ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


runOnMachineFunction - Emit the function body .


<s> const MCSection * SystemZMCAsmInfo :: getNonexecutableStackSection ( MCContext & Ctx ) const { return Ctx . getELFSection ( ".note.GNU-stack" , MCSectionELF :: SHT_PROGBITS , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

Targets can implement this method to specify a section to switch to if the translation unit does n't have any trampolines that require an executable stack .


<s>
void
print
(
raw_ostream
&
OS
)
const
override
{
switch
(
Kind
)
{
case
Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
Register
:
OS
<<
"<register x"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> static bool arm_9e_rtx_costs ( rtx x , int code , int outer_code , int * total ) { enum machine_mode mode = GET_MODE ( x ) ; int nonreg_cost ; int cost ; if ( TARGET_THUMB ) { switch ( code ) { case MULT : * total = COSTS_N_INSNS ( 3 ) ; return true ; default : * total = thumb_rtx_costs ( x , code , outer_code ) ; return true ; } } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , 0 ) ) == GET_CODE ( XEXP ( x , 1 ) ) ) && ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , 0 ) ) == SIGN_EXTEND ) ) { * total = 3 ; return true ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { * total = 30 ; return true ; } if ( mode == DImode ) { cost = 7 ; nonreg_cost = 8 ; } else { cost = 2 ; nonreg_cost = 4 ; } * total = cost + ( REG_OR_SUBREG_REG ( XEXP ( x , 0 ) ) ? 0 : nonreg_cost ) + ( REG_OR_SUBREG_REG ( XEXP ( x , 1 ) ) ? 0 : nonreg_cost ) ; return true ; default : * total = arm_rtx_costs_1 ( x , code , outer_code ) ; return true ; } } </s>


<s> static int rs6000_emit_p9_fp_minmax ( rtx dest , rtx op , rtx true_cond , rtx false_cond ) { enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , 0 ) ; rtx op1 = XEXP ( op , 1 ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return 0 ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code == LT ) max_p = false ; else return 0 ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) ) max_p = ! max_p ; else return 0 ; rs6000_emit_minmax ( dest , max_p ? SMAX : SMIN , op0 , op1 ) ; return 1 ; } </s>

ISA 3.0 ( power9 ) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction for SF/DF scalars . Move TRUE_COND to DEST if OP of the operands of the last comparison is nonzero/true , FALSE_COND if it is zero/false . Return 0 if the hardware has no such operation .


<s> bool GCNDPPCombine :: runOnMachineFunction ( MachineFunction & MF ) { ST = & MF . getSubtarget < GCNSubtarget > ( ) ; if ( ! ST -> hasDPP ( ) || skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = ST -> getInstrInfo ( ) ; bool Changed = false ; for ( auto & MBB : MF ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( llvm :: reverse ( MBB ) ) ) { if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_B32_dpp && combineDPPMov ( MI ) ) { Changed = true ; ++ NumDPPMovsCombined ; } else if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_B64_DPP_PSEUDO ) { if ( ST -> has64BitDPP ( ) && combineDPPMov ( MI ) ) { Changed = true ; ++ NumDPPMovsCombined ; } else { auto Split = TII -> expandMovDPP64 ( MI ) ; for ( auto M : { Split . first , Split . second } ) { if ( M && combineDPPMov ( * M ) ) ++ NumDPPMovsCombined ; } Changed = true ; } } } } return Changed ; } </s>


<s> bool Thumb1InstrInfo :: canCopyGluedNodeDuringSchedule ( SDNode * N ) const { unsigned Opcode = N -> getMachineOpcode ( ) ; if ( Opcode == ARM :: tADCS || Opcode == ARM :: tSBCS ) return true ; return false ; } </s>

Return true if the given SDNode can be copied during scheduling even if it has glue .


The guts of ix86_expand_vec_perm_const , also used by the ok hook . With all of the interface bits taken care of , perform the expansion in D and return true on success .


<s>
bool
FPS
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
bool
FPIsUsed
=
false
;
assert
(
X86
::
FP6
==
X86
::
FP0
+
6
&&
"Register enums aren't sorted right!"
)
;
for
(
unsigned
i
=
0
;
i
<=
6
;
++
i
)
if
(
MF
.
getRegInfo
(
)
.
isPhysRegUsed
(
X86
::
FP0
+
i
)
)
{
FPIsUsed
=
true
;
break
;
}
if
(
!
FPIsUsed
)
return
false
;
TII
=
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
StackTop
=
0
;
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
Processed
;
MachineBasicBlock
*
Entry
=
MF
.
begin
(
)
;
bool
Changed
=
false
;
for
(
df_ext_iterator
<
MachineBasicBlock
*
,
SmallPtrSet
<
MachineBasicBlock
*
,
8
>
>
I
=
df_ext_begin
(
Entry
,
Processed
)
,
E
=
df_ext_end
(
Entry
,
Processed
)
;
I
!=
E
;
++
I
)
Changed
|=
processBasicBlock
(
MF
,
*
*
I
)
;
if
(
MF
.
size
(
)
==
Processed
.
size
(
)
)
return
Changed
;
for
(
MachineFunction
::
iterator
BB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
BB
!=
E
;
++
BB
)
if
(
Processed
.
insert
(
BB
)
)
Changed
|=
processBasicBlock
(
MF
,
*
BB
)
;
return
Changed
;
}
</s>


<s> unsigned MSP430RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return hasFP ( MF ) ? MSP430 :: FPW : MSP430 :: SPW ; } </s>


<s> void pass_vsetvl :: compute_local_properties ( void ) { basic_block cfg_bb ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) { unsigned int curr_bb_idx = bb -> index ( ) ; const auto local_dem = m_vector_manager -> vector_block_infos [ curr_bb_idx ] . local_dem ; const auto reaching_out = m_vector_manager -> vector_block_infos [ curr_bb_idx ] . reaching_out ; for ( size_t i = 0 ; i < m_vector_manager -> vector_exprs . length ( ) ; i ++ ) { const vector_insn_info * expr = m_vector_manager -> vector_exprs [ i ] ; if ( local_dem . real_dirty_p ( ) || local_dem . valid_p ( ) || local_dem . unknown_p ( ) || has_vsetvl_killed_avl_p ( bb , local_dem ) ) bitmap_clear_bit ( m_vector_manager -> vector_transp [ curr_bb_idx ] , i ) ; if ( find_reg_killed_by ( bb , expr -> get_avl ( ) ) ) { hash_set < set_info * > sets = get_all_sets ( expr -> get_avl_source ( ) , true , false , false ) ; if ( any_set_in_bb_p ( sets , bb ) ) bitmap_clear_bit ( m_vector_manager -> vector_transp [ curr_bb_idx ] , i ) ; } } if ( local_dem . valid_p ( ) || local_dem . real_dirty_p ( ) || ( has_vsetvl_killed_avl_p ( bb , local_dem ) && vlmax_avl_p ( local_dem . get_avl ( ) ) ) ) if ( anticipatable_occurrence_p ( bb , local_dem ) ) bitmap_set_bit ( m_vector_manager -> vector_antic [ curr_bb_idx ] , m_vector_manager -> get_expr_id ( local_dem ) ) ; if ( reaching_out . valid_or_dirty_p ( ) ) { auto_vec < size_t > available_list = m_vector_manager -> get_all_available_exprs ( reaching_out ) ; for ( size_t i = 0 ; i < available_list . length ( ) ; i ++ ) { const vector_insn_info * expr = m_vector_manager -> vector_exprs [ available_list [ i ] ] ; if ( reaching_out . real_dirty_p ( ) || has_vsetvl_killed_avl_p ( bb , reaching_out ) || available_occurrence_p ( bb , * expr ) ) bitmap_set_bit ( m_vector_manager -> vector_comp [ curr_bb_idx ] , available_list [ i ] ) ; } } } FOR_EACH_BB_FN ( cfg_bb , cfun ) { bitmap_ior ( m_vector_manager -> vector_kill [ cfg_bb -> index ] , m_vector_manager -> vector_transp [ cfg_bb -> index ] , m_vector_manager -> vector_comp [ cfg_bb -> index ] ) ; bitmap_not ( m_vector_manager -> vector_kill [ cfg_bb -> index ] , m_vector_manager -> vector_kill [ cfg_bb -> index ] ) ; } FOR_EACH_BB_FN ( cfg_bb , cfun ) { edge e ; edge_iterator ei ; FOR_EACH_EDGE ( e , ei , cfg_bb -> preds ) if ( e -> flags & EDGE_COMPLEX ) { bitmap_clear ( m_vector_manager -> vector_antic [ cfg_bb -> index ] ) ; bitmap_clear ( m_vector_manager -> vector_transp [ cfg_bb -> index ] ) ; } } } </s>

Compute the local properties of each recorded expression . Local properties are those that are defined by the block , irrespective of other blocks . An expression is transparent in a block if its operands are not modified in the block . An expression is computed ( locally available ) in a block if it is computed at least once and expression would contain the same value if the computation was moved to the end of the block . An expression is locally anticipatable in a block if it is computed at least once and expression would contain the same value if the computation was moved to the beginning of the block .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> unsigned ARMBaseInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: LDRrs : case ARM :: t2LDRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: LDRi12 : case ARM :: t2LDRi12 : case ARM :: tLDRspi : case ARM :: VLDRD : case ARM :: VLDRS : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDR_P0_off : if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 1 ) . isImm ( ) && MI . getOperand ( 1 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return ARM :: P0 ; } break ; case ARM :: VLD1q64 : case ARM :: VLD1d8TPseudo : case ARM :: VLD1d16TPseudo : case ARM :: VLD1d32TPseudo : case ARM :: VLD1d64TPseudo : case ARM :: VLD1d8QPseudo : case ARM :: VLD1d16QPseudo : case ARM :: VLD1d32QPseudo : case ARM :: VLD1d64QPseudo : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VLDMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> static bool s390_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { if ( size == 8 && aligned_p && GET_CODE ( x ) == CONST_INT && INTVAL ( x ) < INT_MIN ) { fprintf ( asm_out_file , "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n" , INTVAL ( x ) ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . We need to define it here to work a round a bug in some versions of GAS , which could n't handle values smaller than INT_MIN when printed in decimal .


<s>
unsigned
ARMMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
)
const
{
if
(
MO
.
isReg
(
)
)
{
unsigned
Reg
=
MO
.
getReg
(
)
;
unsigned
RegNo
=
getARMRegisterNumbering
(
Reg
)
;
switch
(
Reg
)
{
default
:
return
RegNo
;
case
ARM
::
Q0
:
case
ARM
::
Q1
:
case
ARM
::
Q2
:
case
ARM
::
Q3
:
case
ARM
::
Q4
:
case
ARM
::
Q5
:
case
ARM
::
Q6
:
case
ARM
::
Q7
:
case
ARM
::
Q8
:
case
ARM
::
Q9
:
case
ARM
::
Q10
:
case
ARM
::
Q11
:
case
ARM
::
Q12
:
case
ARM
::
Q13
:
case
ARM
::
Q14
:
case
ARM
::
Q15
:
return
2
*
RegNo
;
}
}
else
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
else
if
(
MO
.
isFPImm
(
)
)
{
return
static_cast
<
unsigned
>
(
APFloat
(
MO
.
getFPImm
(
)
)
.
bitcastToAPInt
(
)
.
getHiBits
(
32
)
.
getLimitedValue
(
)
)
;
}
llvm_unreachable
(
"Unable to encode MCOperand!"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s>
void
HexagonFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineBasicBlock
::
iterator
MBBI
=
std
::
prev
(
MBB
.
end
(
)
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
if
(
hasFP
(
MF
)
||
MF
.
getTarget
(
)
.
getOptLevel
(
)
==
CodeGenOpt
::
)
{
MachineBasicBlock
::
iterator
MBBI
=
std
::
prev
(
MBB
.
end
(
)
)
;
MachineBasicBlock
::
iterator
MBBI_end
=
MBB
.
end
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getTarget
(
)
.
getInstrInfo
(
)
;
if
(
MBBI
->
getOpcode
(
)
==
Hexagon
::
EH_RETURN_JMPR
)
{
assert
(
MBBI
->
getOperand
(
0
)
.
isReg
(
)
&&
"Offset should be in register!"
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
DEALLOCFRAME
)
)
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
ADD_rr
)
,
Hexagon
::
R29
)
.
addReg
(
Hexagon
::
R29
)
.
addReg
(
Hexagon
::
R28
)
;
return
;
}
if
(
STI
.
hasV4TOps
(
)
&&
MBBI
->
getOpcode
(
)
==
Hexagon
::
JMPret
&&
!
DisableDeallocRet
)
{
MachineBasicBlock
::
iterator
BeforeJMPR
=
MBB
.
begin
(
)
==
MBBI
MBBI
:
std
::
prev
(
MBBI
)
;
if
(
BeforeJMPR
!=
MBBI
&&
BeforeJMPR
->
getOpcode
(
)
==
Hexagon
::
RESTORE_DEALLOC_RET_JMP_V4
)
{
MBB
.
erase
(
MBBI
)
;
return
;
}
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MBBI_end
,
dl
,
TII
.
get
(
Hexagon
::
DEALLOC_RET_V4
)
)
;
MIB
->
copyImplicitOps
(
*
MBB
.
getParent
(
)
,
&
*
MBBI
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
MachineBasicBlock
::
iterator
Term
=
MBB
.
getFirstTerminator
(
)
;
MachineBasicBlock
::
iterator
I
=
Term
==
MBB
.
begin
(
)
MBB
.
end
(
)
:
std
::
prev
(
Term
)
;
if
(
I
!=
MBB
.
end
(
)
&&
I
->
getOpcode
(
)
==
Hexagon
::
RESTORE_DEALLOC_BEFORE_TAILCALL_V4
)
return
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Hexagon
::
DEALLOCFRAME
)
)
;
}
}
}
</s>


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI -> estimateStackSize ( MF ) : MFI -> getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = static_cast < const PPCRegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; bool DisableRedZone = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoRedZone ) ; if ( ! DisableRedZone && ( Subtarget . isPPC64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == 0 ) && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI -> setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) , Subtarget . isELFv2ABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI -> setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s>
void
emitInst
(
uint32_t
Inst
,
char
Suffix
)
{
unsigned
Size
;
char
Buffer
[
4
]
;
const
bool
LittleEndian
=
getContext
(
)
.
getAsmInfo
(
)
->
isLittleEndian
(
)
;
switch
(
Suffix
)
{
case
'\0'
:
Size
=
4
;
assert
(
!
IsThumb
)
;
EmitARMMappingSymbol
(
)
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
++
)
{
const
unsigned
I
=
LittleEndian
(
Size
II
1
)
:
II
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I
*
CHAR_BIT
)
;
}
break
;
case
'n'
:
case
'w'
:
Size
=
(
Suffix
==
'n'
2
:
4
)
;
assert
(
IsThumb
)
;
EmitThumbMappingSymbol
(
)
;
for
(
unsigned
II
=
0
,
IE
=
Size
;
II
!=
IE
;
II
=
II
+
2
)
{
const
unsigned
I0
=
LittleEndian
II
+
0
:
II
+
1
;
const
unsigned
I1
=
LittleEndian
II
+
1
:
II
+
0
;
Buffer
[
Size
II
2
]
=
uint8_t
(
Inst
>>
I0
*
CHAR_BIT
)
;
Buffer
[
Size
II
1
]
=
uint8_t
(
Inst
>>
I1
*
CHAR_BIT
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid Suffix"
)
;
}
MCELFStreamer
::
emitBytes
(
StringRef
(
Buffer
,
Size
)
)
;
}
</s>

Callback used to implement the .inst directive .


"LEG DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> const LegalizerInfo * AArch64Subtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ; } </s>

Expose LegalizerInfo so the clients can re-use .


<s> static void emit_nop_for_insn ( rtx_insn * insn ) { int p ; rtx_insn * new_insn ; if ( JUMP_TABLE_DATA_P ( insn ) ) { new_insn = emit_insn_after ( gen_lnop ( ) , insn ) ; recog_memoized ( new_insn ) ; INSN_LOCATION ( new_insn ) = UNKNOWN_LOCATION ; return ; } p = get_pipe ( insn ) ; if ( ( CALL_P ( insn ) || JUMP_P ( insn ) ) && SCHED_ON_EVEN_P ( insn ) ) new_insn = emit_insn_after ( gen_lnop ( ) , insn ) ; else if ( p == 1 && GET_MODE ( insn ) == TImode ) { new_insn = emit_insn_before ( gen_nopn ( GEN_INT ( 127 ) ) , insn ) ; PUT_MODE ( new_insn , TImode ) ; PUT_MODE ( insn , VOIDmode ) ; } else new_insn = emit_insn_after ( gen_lnop ( ) , insn ) ; recog_memoized ( new_insn ) ; INSN_LOCATION ( new_insn ) = INSN_LOCATION ( insn ) ; } </s>

Emit a nop for INSN such that the two will dual issue . This assumes INSN is 8-byte aligned . When INSN is inline asm we emit an lnop . We check for TImode to handle a MULTI1 insn which has dual issued its first instruction . get_pipe returns -1 for MULTI0 or inline asm .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool hasReservedCallFrame ( const MachineFunction & MF ) const { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
bool
SITargetLowering
::
isLegalAddressingMode
(
const
DataLayout
&
DL
,
const
AddrMode
&
AM
,
Type
*
Ty
,
unsigned
AS
,
Instruction
*
I
)
const
{
if
(
AM
.
BaseGV
)
return
false
;
if
(
AS
==
AMDGPUAS
::
GLOBAL_ADDRESS
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
AS
==
AMDGPUAS
::
CONSTANT_ADDRESS
||
AS
==
AMDGPUAS
::
CONSTANT_ADDRESS_32BIT
||
AS
==
AMDGPUAS
::
BUFFER_FAT_POINTER
)
{
if
(
AM
.
BaseOffs
%
4
!=
0
)
return
isLegalMUBUFAddressingMode
(
AM
)
;
if
(
Ty
->
isSized
(
)
&&
DL
.
getTypeStoreSize
(
Ty
)
<
4
)
return
isLegalGlobalAddressingMode
(
AM
)
;
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
if
(
!
isUInt
<
8
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
==
AMDGPUSubtarget
::
SEA_ISLANDS
)
{
if
(
!
isUInt
<
32
>
(
AM
.
BaseOffs
/
4
)
)
return
false
;
}
else
if
(
Subtarget
->
getGeneration
(
)
>=
AMDGPUSubtarget
::
VOLCANIC_ISLANDS
)
{
if
(
!
isUInt
<
20
>
(
AM
.
BaseOffs
)
)
return
false
;
}
else
llvm_unreachable
(
"unhandled generation"
)
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUAS
::
PRIVATE_ADDRESS
)
{
return
isLegalMUBUFAddressingMode
(
AM
)
;
}
else
if
(
AS
==
AMDGPUAS
::
LOCAL_ADDRESS
||
AS
==
AMDGPUAS
::
REGION_ADDRESS
)
{
if
(
!
isUInt
<
16
>
(
AM
.
BaseOffs
)
)
return
false
;
if
(
AM
.
Scale
==
0
)
return
true
;
if
(
AM
.
Scale
==
1
&&
AM
.
HasBaseReg
)
return
true
;
return
false
;
}
else
if
(
AS
==
AMDGPUAS
::
FLAT_ADDRESS
||
AS
==
AMDGPUAS
::
UNKNOWN_ADDRESS_SPACE
)
{
return
isLegalFlatAddressingMode
(
AM
)
;
}
else
{
llvm_unreachable
(
"unhandled address space"
)
;
}
}
</s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> int ARMBaseRegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const { return ARMGenRegisterInfo :: getDwarfRegNumFull ( RegNum , 0 ) ; } </s>

Map a target register to an equivalent dwarf register number .


<s> static rtx nvptx_gen_wcast ( rtx reg , propagate_mask pm , unsigned rep , wcast_data_t * data ) { rtx res ; machine_mode mode = GET_MODE ( reg ) ; switch ( mode ) { case E_BImode : { rtx tmp = gen_reg_rtx ( SImode ) ; start_sequence ( ) ; if ( pm & PM_read ) emit_insn ( gen_sel_truesi ( tmp , reg , GEN_INT ( 1 ) , const0_rtx ) ) ; emit_insn ( nvptx_gen_wcast ( tmp , pm , rep , data ) ) ; if ( pm & PM_write ) emit_insn ( gen_rtx_SET ( reg , gen_rtx_NE ( BImode , tmp , const0_rtx ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } break ; default : { rtx addr = data -> ptr ; if ( ! addr ) { unsigned align = GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ; if ( align > worker_bcast_align ) worker_bcast_align = align ; data -> offset = ( data -> offset + align - 1 ) & ~ ( align - 1 ) ; addr = data -> base ; if ( data -> offset ) addr = gen_rtx_PLUS ( Pmode , addr , GEN_INT ( data -> offset ) ) ; } addr = gen_rtx_MEM ( mode , addr ) ; if ( pm == PM_read ) res = gen_rtx_SET ( addr , reg ) ; else if ( pm == PM_write ) res = gen_rtx_SET ( reg , addr ) ; else gcc_unreachable ( ) ; if ( data -> ptr ) { start_sequence ( ) ; emit_insn ( res ) ; emit_insn ( gen_adddi3 ( data -> ptr , data -> ptr , GEN_INT ( GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; res = get_insns ( ) ; end_sequence ( ) ; } else rep = 1 ; data -> offset += rep * GET_MODE_SIZE ( GET_MODE ( reg ) ) ; } break ; } return res ; } </s>

Generate instruction ( s ) to spill or fill register REG to/from the worker broadcast array . PM indicates what is to be done , REP how many loop iterations will be executed ( 0 for not a loop ) .


<s> InstructionCost X86TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != 0 ; return - 1 ; } </s>

Return the cost of the scaling factor used in the addressing mode represented by AM for this target , for a load/store of the specified type .


"fixed register %s used to pass parameter to function"

Update the summarizer variable CUM to advance past an argument in the argument list .


Invoke the PassBuilder callback registration .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> void RISCVAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const { return ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void s390_expand_atomic_exchange_tdsi ( rtx output , rtx mem , rtx input ) { machine_mode mode = GET_MODE ( mem ) ; rtx_code_label * csloop ; if ( TARGET_Z196 && ( mode == DImode || mode == SImode ) && CONST_INT_P ( input ) && INTVAL ( input ) == 0 ) { emit_move_insn ( output , const0_rtx ) ; if ( mode == DImode ) emit_insn ( gen_atomic_fetch_anddi ( output , mem , const0_rtx , input ) ) ; else emit_insn ( gen_atomic_fetch_andsi ( output , mem , const0_rtx , input ) ) ; return ; } input = force_reg ( mode , input ) ; emit_move_insn ( output , mem ) ; csloop = gen_label_rtx ( ) ; emit_label ( csloop ) ; s390_emit_jump ( csloop , s390_emit_compare_and_swap ( NE , output , mem , output , input , CCZ1mode ) ) ; } </s>

Expand an atomic_exchange operation simulated with a compare-and-swap loop . The memory location MEM is set to INPUT . OUTPUT is set to the previous value of MEM .


<s> bool Z80FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MF . getInfo < Z80MachineFunctionInfo > ( ) -> setCalleeSavedFrameSize ( ( CSI . size ( ) + hasFP ( MF ) ) * SlotSize ) ; return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


"LR & FP are always handled in emitPrologue"

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"No expandLargeImm(SP, -StackSize, false, TII, MBB, MBBI, dl);"

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> static bool s390_cannot_force_const_mem ( machine_mode mode , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : case CONST_DOUBLE : case CONST_WIDE_INT : case CONST_VECTOR : return false ; case NEG : switch ( GET_CODE ( XEXP ( x , 0 ) ) ) { case CONST_INT : case CONST_DOUBLE : case CONST_WIDE_INT : return false ; default : return true ; } case LABEL_REF : return flag_pic != 0 ; case SYMBOL_REF : if ( tls_symbolic_operand ( x ) ) return true ; else return flag_pic != 0 ; case CONST : return s390_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) ; case PLUS : case MINUS : return s390_cannot_force_const_mem ( mode , XEXP ( x , 0 ) ) || s390_cannot_force_const_mem ( mode , XEXP ( x , 1 ) ) ; case UNSPEC : switch ( XINT ( x , 1 ) ) { case UNSPEC_LTREL_OFFSET : case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLTOFF : case UNSPEC_TLSGD : case UNSPEC_TLSLDM : case UNSPEC_NTPOFF : case UNSPEC_DTPOFF : case UNSPEC_GOTNTPOFF : case UNSPEC_INDNTPOFF : return false ; case UNSPEC_INSN : default : return true ; } break ; default : gcc_unreachable ( ) ; } } </s>

Determine if it 's legal to put X into the constant pool . This is not possible if X contains the address of a symbol that is not constant ( TLS ) or not known at final link time ( PIC ) .


<s> static void assign_int_registers ( int bitpos , assign_data_t * data ) { int intoffset = data -> intoffset ; machine_mode mode ; int nregs ; if ( ! compute_int_layout ( bitpos , data , & nregs ) ) return ; if ( intoffset % BITS_PER_WORD != 0 ) mode = smallest_int_mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD ) ; else mode = word_mode ; const int this_slotno = data -> slotno + intoffset / BITS_PER_WORD ; unsigned int regno = data -> regbase + this_slotno ; intoffset /= BITS_PER_UNIT ; do { rtx reg = gen_rtx_REG ( mode , regno ) ; XVECEXP ( data -> ret , 0 , data -> stack + data -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( intoffset ) ) ; data -> nregs += 1 ; mode = word_mode ; regno += 1 ; intoffset = ( intoffset | ( UNITS_PER_WORD - 1 ) ) + 1 ; } while ( -- nregs > 0 ) ; } </s>

A subroutine of function_arg_record_value . Assign the bits of the structure between PARMS- > intoffset and BITPOS to integer registers .


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( 1 , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> void TOYInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( TOY :: LDR ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s>
bool
FixupLEAPass
::
runOnMachineFunction
(
MachineFunction
&
Func
)
{
if
(
skipFunction
(
Func
.
getFunction
(
)
)
)
return
false
;
MF
=
&
Func
;
const
X86Subtarget
&
ST
=
Func
.
getSubtarget
<
X86Subtarget
>
(
)
;
OptIncDec
=
!
ST
.
slowIncDec
(
)
||
Func
.
getFunction
(
)
.
optForMinSize
(
)
;
OptLEA
=
ST
.
LEAusesAG
(
)
||
ST
.
slowLEA
(
)
||
ST
.
slow3OpsLEA
(
)
;
if
(
!
OptLEA
&&
!
OptIncDec
)
return
false
;
TSM
.
init
(
&
Func
.
getSubtarget
(
)
)
;
TII
=
ST
.
getInstrInfo
(
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Start X86FixupLEAs\n"
;
)
;
for
(
MachineFunction
::
iterator
I
=
Func
.
begin
(
)
,
E
=
Func
.
end
(
)
;
I
!=
E
;
++
I
)
processBasicBlock
(
Func
,
I
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"End X86FixupLEAs\n"
;
)
;
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> const ARMBaseInstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ; } </s>


<s> static void m68k_sched_dfa_pre_advance_cycle ( void ) { if ( ! sched_ib . enabled_p ) return ; if ( ! cpu_unit_reservation_p ( curr_state , sched_mem_unit_code ) ) { sched_ib . filled += 2 ; if ( sched_ib . filled > sched_ib . size ) sched_ib . filled = sched_ib . size ; } } </s>

Implementation of targetm.sched.dfa_pre_advance_cycle ( ) hook . It is invoked just before current cycle finishes and is used here to track if instruction buffer got its two words this cycle .


<s>
bool
AArch64InstrInfo
::
isLdStPairSuppressed
(
const
MachineInstr
&
MI
)
const
{
static_assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
,
"Too many target MO flags"
)
;
for
(
auto
*
MM
:
MI
.
memoperands
(
)
)
{
if
(
MM
->
getFlags
(
)
&
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
)
{
return
true
;
}
}
return
false
;
}
</s>

Return true if pairing the given load or store is hinted to be unprofitable .


"There are no defined alternate asm variants"

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> section * vms_function_section ( tree decl ATTRIBUTE_UNUSED , enum node_frequency freq ATTRIBUTE_UNUSED , bool startup ATTRIBUTE_UNUSED , bool exit ATTRIBUTE_UNUSED ) { return NULL ; } </s>


<s> static void m68hc11_asm_out_destructor ( rtx symbol , int priority ) { default_dtor_section_asm_out_destructor ( symbol , priority ) ; fprintf ( asm_out_file , "\t.globl\t__do_global_dtors\n" ) ; } </s>

Worker function for TARGET_ASM_DESTRUCTOR .


<s> unsigned SIInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( ! MI . mayLoad ( ) ) return AMDGPU :: NoRegister ; if ( isMUBUF ( MI ) || isVGPRSpill ( MI ) ) return isStackAccess ( MI , FrameIndex ) ; if ( isSGPRSpill ( MI ) ) return isSGPRStackAccess ( MI , FrameIndex ) ; return AMDGPU :: NoRegister ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .

AMDGPU SI AMDGPU::NoRegister AMDGPU::NoRegister


<s> unsigned PPCTargetLowering :: getByValTypeAlignment ( const Type * Ty ) const { const TargetMachine & TM = getTargetMachine ( ) ; if ( TM . getSubtarget < PPCSubtarget > ( ) . isDarwin ( ) ) return 4 ; return 4 ; } </s>

Return the desired alignment for ByVal aggregate function arguments in the caller parameter area .


<s> rtx s390_gen_lowpart_subreg ( machine_mode mode , rtx expr ) { rtx lowpart = gen_lowpart ( mode , expr ) ; if ( ! SUBREG_P ( lowpart ) ) { machine_mode reg_mode = TARGET_ZARCH ? DImode : SImode ; gcc_assert ( REG_P ( lowpart ) ) ; lowpart = gen_lowpart_SUBREG ( mode , gen_rtx_REG ( reg_mode , REGNO ( lowpart ) ) ) ; } return lowpart ; } </s>

Generate a SUBREG for the MODE lowpart of EXPR . In contrast to gen_lowpart it will always return a SUBREG expression . This is useful to generate STRICT_LOW_PART expressions .


"@c Copyright (C) 2012-2019 Free Software Foundation, Inc.\n"

"@c For copying conditions, see the file "

"@c This file is generated automatically using\n"

Main program to convert flat files into built-in initialization code .


<s> unsigned SIRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned Occupancy = ST . getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , MF . getFunction ( ) ) ; switch ( RC -> getID ( ) ) { default : return AMDGPURegisterInfo :: getRegPressureLimit ( RC , MF ) ; case AMDGPU :: VGPR_32RegClassID : return std :: min ( ST . getMaxNumVGPRs ( Occupancy ) , ST . getMaxNumVGPRs ( MF ) ) ; case AMDGPU :: SGPR_32RegClassID : return std :: min ( ST . getMaxNumSGPRs ( Occupancy , true ) , ST . getMaxNumSGPRs ( MF ) ) ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .

AMDGPU SI SI SI AMDGPU AMDGPU::VGPR_32RegClassID AMDGPU::SGPR_32RegClassID


<s> const uint16_t * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { bool ghcCall = false ; if ( MF ) { const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) return CSR_NoRegs_SaveList ; else return ( STI . isTargetIOS ( ) && ! STI . isAAPCS_ABI ( ) ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; } </s>


<s> bool PatmosInstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { assert ( Pred1 . size ( ) == 2 && Pred2 . size ( ) == 2 ) ; unsigned preg1 = Pred1 [ 0 ] . getReg ( ) ; int flag1 = Pred1 [ 1 ] . getImm ( ) ; if ( ( preg1 == Patmos :: NoRegister || preg1 == Patmos :: P0 ) && ! flag1 ) return true ; if ( preg1 == Pred2 [ 0 ] . getReg ( ) && flag1 == Pred2 [ 1 ] . getImm ( ) ) return true ; return false ; } </s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> void riscv_expand_int_scc ( rtx target , enum rtx_code code , rtx op0 , rtx op1 ) { riscv_extend_comparands ( code , & op0 , & op1 ) ; op0 = force_reg ( word_mode , op0 ) ; if ( code == EQ || code == NE ) { rtx zie = riscv_zero_if_equal ( op0 , op1 ) ; riscv_emit_binary ( code , target , zie , const0_rtx ) ; } else riscv_emit_int_order_test ( code , 0 , target , op0 , op1 ) ; } </s>

CODE-compare OP0 and OP1 . Store the result in TARGET .


<s> virtual const MipsRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static bool isIndirectCall ( const SDValue & Callee , SelectionDAG & DAG , const PPCSubtarget & Subtarget , bool isPatchPoint ) { if ( isPatchPoint ) return false ; if ( isFunctionGlobalAddress ( Callee ) || isa < ExternalSymbolSDNode > ( Callee ) ) return false ; if ( ! Subtarget . usesFunctionDescriptors ( ) && ! Subtarget . isELFv2ABI ( ) && isBLACompatibleAddress ( Callee , DAG ) ) return false ; return true ; } </s>

Return true if the callsite is an indirect call .


<s> bool PPCAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; O << "0(" ; printOperand ( MI , OpNo , O ) ; O << ")" ; return false ; } </s>


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( I . isPHI ( ) ) return selectPHI ( I ) ; if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_ADD : case TargetOpcode :: G_SUB : if ( selectG_ADD_SUB ( I ) ) return true ; LLVM_FALLTHROUGH ; default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_EXTRACT : return selectG_EXTRACT ( I ) ; case TargetOpcode :: G_MERGE_VALUES : case TargetOpcode :: G_CONCAT_VECTORS : return selectG_MERGE_VALUES ( I ) ; case TargetOpcode :: G_UNMERGE_VALUES : return selectG_UNMERGE_VALUES ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INSERT : return selectG_INSERT ( I ) ; case TargetOpcode :: G_INTRINSIC : return selectG_INTRINSIC ( I , CoverageInfo ) ; case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : return selectG_INTRINSIC_W_SIDE_EFFECTS ( I , CoverageInfo ) ; case TargetOpcode :: G_ICMP : if ( selectG_ICMP ( I ) ) return true ; return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_LOAD : if ( selectImpl ( I , CoverageInfo ) ) return true ; return selectG_LOAD ( I ) ; case TargetOpcode :: G_SELECT : return selectG_SELECT ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; case TargetOpcode :: G_TRUNC : return selectG_TRUNC ( I ) ; case TargetOpcode :: G_SEXT : case TargetOpcode :: G_ZEXT : case TargetOpcode :: G_ANYEXT : if ( selectG_SZA_EXT ( I ) ) { I . eraseFromParent ( ) ; return true ; } return false ; case TargetOpcode :: G_BRCOND : return selectG_BRCOND ( I ) ; case TargetOpcode :: G_FRAME_INDEX : return selectG_FRAME_INDEX ( I ) ; case TargetOpcode :: G_FENCE : I . setDesc ( TII . get ( AMDGPU :: ATOMIC_FENCE ) ) ; return true ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .

AMDGPU AMDGPU SI SI SI SI AMDGPU::ATOMIC_FENCE


"Some operands reg class are incompatible!"

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare ; remove Compare if possible .


<s> static void workaround_arc_anomaly ( void ) { rtx_insn * insn , * succ0 ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { succ0 = next_real_insn ( insn ) ; if ( arc_hazard ( insn , succ0 ) ) { emit_insn_before ( gen_nopv ( ) , succ0 ) ; } } if ( ! TARGET_ARC700 ) return ; if ( arc_tune != ARC_TUNE_ARC7XX ) check_store_cacheline_hazard ( ) ; } </s>

The same functionality as arc_hazard . It is called in machine reorg before any other optimization . Hence , the NOP size is taken into account when doing branch shortening .


<s> static std :: unique_ptr < AArch64Operand > CreateReg ( unsigned RegNum , RegKind Kind , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < AArch64Operand > ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . Kind = Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s>
bool
ARMAsmParser
::
MatchAndEmitInstruction
(
SMLoc
IDLoc
,
unsigned
&
Opcode
,
OperandVector
&
Operands
,
MCStreamer
&
Out
,
uint64_t
&
ErrorInfo
,
bool
MatchingInlineAsm
)
{
MCInst
Inst
;
unsigned
MatchResult
;
bool
PendConditionalInstruction
=
false
;
SmallVector
<
NearMissInfo
,
4
>
NearMisses
;
MatchResult
=
MatchInstruction
(
Operands
,
Inst
,
NearMisses
,
MatchingInlineAsm
,
PendConditionalInstruction
,
Out
)
;
switch
(
MatchResult
)
{
case
Match_Success
:
LLVM_DEBUG
(
dbgs
(
)
<<
"Parsed as: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
validateInstruction
(
Inst
,
Operands
)
)
{
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
return
true
;
}
{
bool
wasInITBlock
=
inITBlock
(
)
;
while
(
processInstruction
(
Inst
,
Operands
,
Out
)
)
LLVM_DEBUG
(
dbgs
(
)
<<
"Changed to: "
;
Inst
.
dump_pretty
(
dbgs
(
)
,
MII
.
getName
(
Inst
.
getOpcode
(
)
)
)
;
dbgs
(
)
<<
"\n"
)
;
if
(
wasInITBlock
&&
hasV8Ops
(
)
&&
isThumb
(
)
&&
!
isV8EligibleForIT
(
&
Inst
)
)
{
Warning
(
IDLoc
,
"deprecated instruction in IT block"
)
;
}
}
forwardITPosition
(
)
;
forwardVPTPosition
(
)
;
if
(
Inst
.
getOpcode
(
)
==
ARM
::
ITasm
)
return
false
;
Inst
.
setLoc
(
IDLoc
)
;
if
(
PendConditionalInstruction
)
{
PendingConditionalInsts
.
push_back
(
Inst
)
;
if
(
isITBlockFull
(
)
||
isITBlockTerminator
(
Inst
)
)
flushPendingInstructions
(
Out
)
;
}
else
{
Out
.
EmitInstruction
(
Inst
,
getSTI
(
)
)
;
}
return
false
;
case
Match_NearMisses
:
ReportNearMisses
(
NearMisses
,
IDLoc
,
Operands
)
;
return
true
;
case
Match_MnemonicFail
:
{
FeatureBitset
FBS
=
ComputeAvailableFeatures
(
getSTI
(
)
.
getFeatureBits
(
)
)
;
std
::
string
Suggestion
=
ARMMnemonicSpellCheck
(
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getToken
(
)
,
FBS
)
;
return
Error
(
IDLoc
,
"invalid instruction"
+
Suggestion
,
(
(
ARMOperand
&
)
*
Operands
[
0
]
)
.
getLocRange
(
)
)
;
}
}
llvm_unreachable
(
"Implement any new match types added!"
)
;
}
</s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .

ARM
ARM
4
"Parsed as: "
"\n"
"Changed to: "
"\n"
"deprecated instruction in IT block"
ARM::ITasm
ARM
ARM
0
"invalid instruction"
ARM
0
"Implement any new match types added!"


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s>
bool
AMDGPUCallLowering
::
lowerReturn
(
MachineIRBuilder
&
B
,
const
Value
*
Val
,
ArrayRef
<
Register
>
VRegs
,
FunctionLoweringInfo
&
FLI
)
const
{
MachineFunction
&
MF
=
B
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MFI
->
setIfReturnsVoid
(
!
Val
)
;
assert
(
!
Val
==
VRegs
.
empty
(
)
&&
"Return value without a vreg"
)
;
CallingConv
::
ID
CC
=
B
.
getMF
(
)
.
getFunction
(
)
.
getCallingConv
(
)
;
const
bool
IsShader
=
AMDGPU
::
isShader
(
CC
)
;
const
bool
IsWaveEnd
=
(
IsShader
&&
MFI
->
returnsVoid
(
)
)
||
AMDGPU
::
isKernel
(
CC
)
;
if
(
IsWaveEnd
)
{
B
.
buildInstr
(
AMDGPU
::
S_ENDPGM
)
.
addImm
(
0
)
;
return
true
;
}
auto
const
&
ST
=
MF
.
getSubtarget
<
GCNSubtarget
>
(
)
;
unsigned
ReturnOpc
=
0
;
if
(
IsShader
)
ReturnOpc
=
AMDGPU
::
SI_RETURN_TO_EPILOG
;
else
if
(
CC
==
CallingConv
::
AMDGPU_Gfx
)
ReturnOpc
=
AMDGPU
::
S_SETPC_B64_return_gfx
;
else
ReturnOpc
=
AMDGPU
::
S_SETPC_B64_return
;
auto
Ret
=
B
.
buildInstrNoInsert
(
ReturnOpc
)
;
Register
ReturnAddrVReg
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
)
{
ReturnAddrVReg
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
CCR_SGPR_64RegClass
)
;
Ret
.
addUse
(
ReturnAddrVReg
)
;
}
else
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return_gfx
)
{
ReturnAddrVReg
=
MRI
.
createVirtualRegister
(
&
AMDGPU
::
Gfx_CCR_SGPR_64RegClass
)
;
Ret
.
addUse
(
ReturnAddrVReg
)
;
}
if
(
!
FLI
.
CanLowerReturn
)
insertSRetStores
(
B
,
Val
->
getType
(
)
,
VRegs
,
FLI
.
DemoteRegister
)
;
else
if
(
!
lowerReturnVal
(
B
,
Val
,
VRegs
,
Ret
)
)
return
false
;
if
(
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return
||
ReturnOpc
==
AMDGPU
::
S_SETPC_B64_return_gfx
)
{
const
SIRegisterInfo
*
TRI
=
ST
.
getRegisterInfo
(
)
;
Register
LiveInReturn
=
MF
.
addLiveIn
(
TRI
->
getReturnAddressReg
(
MF
)
,
&
AMDGPU
::
SGPR_64RegClass
)
;
B
.
buildCopy
(
ReturnAddrVReg
,
LiveInReturn
)
;
}
B
.
insertInstr
(
Ret
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> static bool arm_cookie_has_size ( void ) { return TARGET_AAPCS_BASED ; } </s>

The EABI says that array cookies should also contain the element size .


<s> static void emit_link_insn ( rtx spreg , HOST_WIDE_INT frame_size ) { HOST_WIDE_INT link_size = frame_size ; rtx insn ; int i ; if ( link_size > 262140 ) link_size = 262140 ; insn = emit_insn ( gen_link ( GEN_INT ( - 8 - link_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; for ( i = 0 ; i < XVECLEN ( PATTERN ( insn ) , 0 ) ; i ++ ) { rtx set = XVECEXP ( PATTERN ( insn ) , 0 , i ) ; gcc_assert ( GET_CODE ( set ) == SET ) ; RTX_FRAME_RELATED_P ( set ) = 1 ; } frame_size -= link_size ; if ( frame_size > 0 ) { rtx tmpreg = gen_rtx_REG ( Pmode , REG_P1 ) ; frame_related_constant_load ( tmpreg , - frame_size , TRUE ) ; insn = emit_insn ( gen_addsi3 ( spreg , spreg , tmpreg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Generate a LINK insn for a frame sized FRAME_SIZE . If this constant is too large , generate a sequence of insns that has the same effect . SPREG contains ( reg : SI REG_SP ) .


"Cannot store this register to stack slot!"

Load the specified register of the given register class from the specified stack frame index .


<s> static X86Operand * CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc , bool AddressOf = false , SMLoc OffsetOfLoc = SMLoc ( ) , StringRef SymName = StringRef ( ) , void * OpDecl = nullptr ) { X86Operand * Res = new X86Operand ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> AddressOf = AddressOf ; Res -> OffsetOfLoc = OffsetOfLoc ; Res -> SymName = SymName ; Res -> OpDecl = OpDecl ; return Res ; } </s>


<s>
MCSymbol
*
MBlazeMCInstLower
::
GetBlockAddressSymbol
(
const
MachineOperand
&
MO
)
const
{
switch
(
MO
.
getTargetFlags
(
)
)
{
default
:
llvm_unreachable
(
"Unknown target flag on GV operand"
)
;
case
0
:
break
;
}
return
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
;
}
</s>

Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block .

MBlaze
MBlaze
"Unknown target flag on GV operand"
0


Implement TARGET_MODES_TIEABLE_P . Tie QI/HI/SI modes together .


<s> static bool s390_adjust_loop_scan_osc ( struct loop * loop ) { HARD_REG_SET modregs , newregs ; rtx_insn * insn , * store_insn = NULL ; rtx set ; struct s390_address addr_store , addr_load ; subrtx_iterator :: array_type array ; int insn_count ; CLEAR_HARD_REG_SET ( modregs ) ; insn_count = 0 ; FOR_BB_INSNS_REVERSE ( loop -> latch , insn ) { if ( ! INSN_P ( insn ) || INSN_CODE ( insn ) <= 0 ) continue ; insn_count ++ ; if ( insn_count > S390_OSC_SCAN_INSN_NUM ) return false ; find_all_hard_reg_sets ( insn , & newregs , true ) ; IOR_HARD_REG_SET ( modregs , newregs ) ; set = single_set ( insn ) ; if ( ! set ) continue ; if ( MEM_P ( SET_DEST ( set ) ) && s390_decompose_address ( XEXP ( SET_DEST ( set ) , 0 ) , & addr_store ) ) { store_insn = insn ; break ; } } if ( store_insn == NULL_RTX ) return false ; insn_count = 0 ; FOR_BB_INSNS ( loop -> header , insn ) { if ( ! INSN_P ( insn ) || INSN_CODE ( insn ) <= 0 ) continue ; if ( insn == store_insn ) return false ; insn_count ++ ; if ( insn_count > S390_OSC_SCAN_INSN_NUM ) return false ; find_all_hard_reg_sets ( insn , & newregs , true ) ; IOR_HARD_REG_SET ( modregs , newregs ) ; set = single_set ( insn ) ; if ( ! set ) continue ; if ( MEM_P ( SET_DEST ( set ) ) && s390_decompose_address ( XEXP ( SET_DEST ( set ) , 0 ) , NULL ) ) return false ; FOR_EACH_SUBRTX ( iter , array , SET_SRC ( set ) , NONCONST ) if ( MEM_P ( * iter ) && s390_decompose_address ( XEXP ( * iter , 0 ) , & addr_load ) && rtx_equal_p ( addr_load . base , addr_store . base ) && rtx_equal_p ( addr_load . indx , addr_store . indx ) && rtx_equal_p ( addr_load . disp , addr_store . disp ) ) { if ( ( addr_load . base != NULL_RTX && TEST_HARD_REG_BIT ( modregs , REGNO ( addr_load . base ) ) ) || ( addr_load . indx != NULL_RTX && TEST_HARD_REG_BIT ( modregs , REGNO ( addr_load . indx ) ) ) ) return true ; } } return false ; } </s>

Scan LOOP for static OSC collisions and return true if a osc_break should be issued for this loop .


<s>
static
const
char
*
avr_out_plus_symbol
(
rtx
*
xop
,
enum
rtx_code
code
,
int
*
plen
,
int
*
pcc
)
{
machine_mode
mode
=
GET_MODE
(
xop
[
0
]
)
;
gcc_assert
(
mode
==
HImode
||
mode
==
PSImode
)
;
*
pcc
=
MINUS
==
code
(
int
)
CC_SET_CZN
:
(
int
)
CC_SET_N
;
avr_asm_len
(
PLUS
==
code
"subi %A0,lo8(-(%2))"
CR_TAB
"sbci %B0,hi8(-(%2))"
:
"subi %A0,lo8(%2)"
CR_TAB
"sbci %B0,hi8(%2)"
,
xop
,
plen
,
2
)
;
if
(
PSImode
==
mode
)
avr_asm_len
(
PLUS
==
code
"sbci %C0,hlo8(-(%2))"
:
"sbci %C0,hlo8(%2)"
,
xop
,
plen
,
1
)
;
return
""
;
}
</s>

Output addition/subtraction of register XOP [ 0 ] and a constant XOP [ 2 ] that is ont a compile-time constant : XOP [ 0 ] = XOP [ 0 ] +/- XOP [ 2 ] This is a helper for the function below . The only insns that need this are additions/subtraction for pointer modes , i.e . HImode and PSImode .


<s> rtx assign_386_stack_local ( machine_mode mode , enum ix86_stack_slot n ) { struct stack_local_entry * s ; gcc_assert ( n < MAX_386_STACK_LOCALS ) ; for ( s = ix86_stack_locals ; s ; s = s -> next ) if ( s -> mode == mode && s -> n == n ) return validize_mem ( copy_rtx ( s -> rtl ) ) ; int align = 0 ; if ( mode == DImode && ! TARGET_64BIT && n == SLOT_FLOATxFDI_387 && ix86_preferred_stack_boundary < GET_MODE_ALIGNMENT ( DImode ) ) align = 32 ; s = ggc_alloc < stack_local_entry > ( ) ; s -> n = n ; s -> mode = mode ; s -> rtl = assign_stack_local ( mode , GET_MODE_SIZE ( mode ) , align ) ; s -> next = ix86_stack_locals ; ix86_stack_locals = s ; return validize_mem ( copy_rtx ( s -> rtl ) ) ; } </s>

Return a MEM corresponding to a stack slot with mode MODE . Allocate a new slot if necessary . The RTL for a function can have several slots available : N is which slot to use .


<s> static void alpha_emit_xfloating_libcall ( rtx func , rtx target , rtx operands [ ] , int noperands , rtx equiv ) { rtx usage = NULL_RTX , tmp , reg ; int regno = 16 , i ; start_sequence ( ) ; for ( i = 0 ; i < noperands ; ++ i ) { switch ( GET_MODE ( operands [ i ] ) ) { case TFmode : reg = gen_rtx_REG ( TFmode , regno ) ; regno += 2 ; break ; case DFmode : reg = gen_rtx_REG ( DFmode , regno + 32 ) ; regno += 1 ; break ; case VOIDmode : gcc_assert ( CONST_INT_P ( operands [ i ] ) ) ; case DImode : reg = gen_rtx_REG ( DImode , regno ) ; regno += 1 ; break ; default : gcc_unreachable ( ) ; } emit_move_insn ( reg , operands [ i ] ) ; use_reg ( & usage , reg ) ; } switch ( GET_MODE ( target ) ) { case TFmode : reg = gen_rtx_REG ( TFmode , 16 ) ; break ; case DFmode : reg = gen_rtx_REG ( DFmode , 32 ) ; break ; case DImode : reg = gen_rtx_REG ( DImode , 0 ) ; break ; default : gcc_unreachable ( ) ; } tmp = gen_rtx_MEM ( QImode , func ) ; tmp = emit_call_insn ( gen_call_value ( reg , tmp , const0_rtx , const0_rtx , const0_rtx ) ) ; CALL_INSN_FUNCTION_USAGE ( tmp ) = usage ; RTL_CONST_CALL_P ( tmp ) = 1 ; tmp = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( tmp , target , reg , equiv ) ; } </s>

Emit an X_floating library function call . Note that these functions do not follow normal calling conventions : TFmode arguments are passed in two integer registers ( as opposed to indirect ) ; TFmode return values appear in R16+R17 . FUNC is the function name to call . TARGET is where the output belongs . OPERANDS are the inputs . NOPERANDS is the count of inputs . EQUIV is the expression equivalent for the function .


"Unexpected short instruction with fixup"

Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned JVMAsmBackend :: getNumFixupKinds ( ) const { return 0 ; } </s>

Get the number of target specific fixup kinds .


<s>
const
char
*
output_movedouble
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
,
enum
machine_mode
mode
)
{
rtx
dst
=
operands
[
0
]
;
rtx
src
=
operands
[
1
]
;
if
(
GET_CODE
(
dst
)
==
MEM
&&
GET_CODE
(
XEXP
(
dst
,
0
)
)
==
PRE_DEC
)
return
"mov.l	%T1,%0\n\tmov.l	%1,%0"
;
if
(
register_operand
(
dst
,
mode
)
&&
register_operand
(
src
,
mode
)
)
{
if
(
REGNO
(
src
)
==
MACH_REG
)
return
"sts	mach,%S0\n\tsts	macl,%R0"
;
if
(
REGNO
(
src
)
+
1
==
REGNO
(
dst
)
)
return
"mov	%T1,%T0\n\tmov	%1,%0"
;
else
return
"mov	%1,%0\n\tmov	%T1,%T0"
;
}
else
if
(
GET_CODE
(
src
)
==
CONST_INT
)
{
if
(
INTVAL
(
src
)
<
0
)
output_asm_insn
(
"mov	#-1,%S0"
,
operands
)
;
else
output_asm_insn
(
"mov	#0,%S0"
,
operands
)
;
return
"mov	%1,%R0"
;
}
else
if
(
GET_CODE
(
src
)
==
MEM
)
{
int
ptrreg
=
1
;
int
dreg
=
REGNO
(
dst
)
;
rtx
inside
=
XEXP
(
src
,
0
)
;
switch
(
GET_CODE
(
inside
)
)
{
case
REG
:
ptrreg
=
REGNO
(
inside
)
;
break
;
case
SUBREG
:
ptrreg
=
subreg_regno
(
inside
)
;
break
;
case
PLUS
:
ptrreg
=
REGNO
(
XEXP
(
inside
,
0
)
)
;
gcc_assert
(
GET_CODE
(
XEXP
(
inside
,
1
)
)
!=
REG
)
;
break
;
case
LABEL_REF
:
return
"mov.l	%1,%0\n\tmov.l	%1+4,%T0"
;
case
POST_INC
:
return
"mov.l	%1,%0\n\tmov.l	%1,%T0"
;
default
:
gcc_unreachable
(
)
;
}
if
(
dreg
==
ptrreg
)
return
"mov.l	%T1,%T0\n\tmov.l	%1,%0"
;
}
return
"mov.l	%1,%0\n\tmov.l	%T1,%T0"
;
}
</s>

Return a sequence of instructions to perform DI or DF move . Since the SH can not move a DI or DF in one instruction , we have to take care when we see overlapping source and dest registers .


<s> iterator_range < block_iterator > blocks ( ) const override { return Unit -> blocks ( ) ; } </s>

Returns a range view of the basic blocks in the region .


<s> static void iq2000_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_CODE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , Pmode , TRAMPOLINE_CODE_SIZE ) ; emit_move_insn ( mem , fnaddr ) ; mem = adjust_address ( m_tramp , Pmode , TRAMPOLINE_CODE_SIZE + GET_MODE_SIZE ( Pmode ) ) ; emit_move_insn ( mem , chain_value ) ; } </s>


<s> bool ix86_expand_strlen ( rtx out , rtx src , rtx eoschar , rtx align ) { rtx addr , scratch1 , scratch2 , scratch3 , scratch4 ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && ! TARGET_INLINE_ALL_STRINGOPS && ! optimize_insn_for_size_p ( ) && ( ! CONST_INT_P ( align ) || INTVAL ( align ) < 4 ) ) return false ; addr = force_reg ( Pmode , XEXP ( src , 0 ) ) ; scratch1 = gen_reg_rtx ( Pmode ) ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1 && ! optimize_insn_for_size_p ( ) ) { emit_move_insn ( out , addr ) ; ix86_expand_strlensi_unroll_1 ( out , src , align ) ; emit_insn ( ix86_gen_sub3 ( out , out , addr ) ) ; } else { rtx unspec ; if ( fixed_regs [ AX_REG ] || fixed_regs [ CX_REG ] || fixed_regs [ DI_REG ] ) return false ; if ( ! ADDR_SPACE_GENERIC_P ( MEM_ADDR_SPACE ( src ) ) ) return false ; scratch2 = gen_reg_rtx ( Pmode ) ; scratch3 = gen_reg_rtx ( Pmode ) ; scratch4 = force_reg ( Pmode , constm1_rtx ) ; emit_move_insn ( scratch3 , addr ) ; eoschar = force_reg ( QImode , eoschar ) ; src = replace_equiv_address_nv ( src , scratch3 ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , src , eoschar , align , scratch4 ) , UNSPEC_SCAS ) ; emit_insn ( gen_strlenqi_1 ( scratch1 , scratch3 , unspec ) ) ; emit_insn ( ix86_gen_one_cmpl2 ( scratch2 , scratch1 ) ) ; emit_insn ( ix86_gen_add3 ( out , scratch2 , constm1_rtx ) ) ; } return true ; } </s>


<s> bool aarch64_simd_mem_operand_p ( rtx op ) { return MEM_P ( op ) && ( GET_CODE ( XEXP ( op , 0 ) ) == POST_INC || REG_P ( XEXP ( op , 0 ) ) ) ; } </s>

Return TRUE if OP is a valid vector addressing mode .


<s> void TVMPassConfig :: addPostRegAlloc ( ) { disablePass ( & MachineCopyPropagationID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; TargetPassConfig :: addPostRegAlloc ( ) ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> bool SITargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { VT = VT . getScalarType ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f32 : return Subtarget -> hasFP32Denormals ( ) && Subtarget -> hasFastFMAF32 ( ) ; case MVT :: f64 : return true ; case MVT :: f16 : return Subtarget -> has16BitInsts ( ) && Subtarget -> hasFP16Denormals ( ) ; default : break ; } return false ; } </s>

Return true if an FMA operation is faster than a pair of fmul and fadd instructions .


<s> int legitimate_pic_operand_p ( rtx x ) { switch ( GET_CODE ( x ) ) { case SYMBOL_REF : return 0 ; break ; case LABEL_REF : return 0 ; break ; case CONST : if ( GET_CODE ( XEXP ( x , 0 ) ) == PLUS && ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF ) && ( GET_CODE ( XEXP ( XEXP ( x , 0 ) , 1 ) ) == CONST_INT ) ) return 0 ; break ; case MEM : return legitimate_pic_operand_p ( XEXP ( x , 0 ) ) ; break ; default : break ; } return 1 ; } </s>

Return true if OP is a legitimate general operand when generating PIC code . It is given that flag_pic is on and that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s>
bool
X86TargetLowering
::
shouldExpandAtomicRMWInIR
(
AtomicRMWInst
*
AI
)
const
{
unsigned
NativeWidth
=
Subtarget
->
is64Bit
(
)
64
:
32
;
const
Type
*
MemType
=
AI
->
getType
(
)
;
if
(
MemType
->
getPrimitiveSizeInBits
(
)
>
NativeWidth
)
return
needsCmpXchgNb
(
MemType
)
;
AtomicRMWInst
::
BinOp
Op
=
AI
->
getOperation
(
)
;
switch
(
Op
)
{
default
:
llvm_unreachable
(
"Unknown atomic operation"
)
;
case
AtomicRMWInst
::
Xchg
:
case
AtomicRMWInst
::
Add
:
case
AtomicRMWInst
::
Sub
:
return
false
;
case
AtomicRMWInst
::
Or
:
case
AtomicRMWInst
::
And
:
case
AtomicRMWInst
::
Xor
:
return
!
AI
->
use_empty
(
)
;
case
AtomicRMWInst
::
Nand
:
case
AtomicRMWInst
::
Max
:
case
AtomicRMWInst
::
Min
:
case
AtomicRMWInst
::
UMax
:
case
AtomicRMWInst
::
UMin
:
return
true
;
}
}
</s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s>
char
*
xstormy16_output_cbranch_hi
(
rtx
op
,
const
char
*
label
,
int
reversed
,
rtx
insn
)
{
static
char
string
[
64
]
;
int
need_longbranch
=
(
op
!=
NULL_RTX
get_attr_length
(
insn
)
==
8
:
get_attr_length
(
insn
)
==
4
)
;
int
really_reversed
=
reversed
^
need_longbranch
;
const
char
*
ccode
;
const
char
*
template
;
const
char
*
operands
;
enum
rtx_code
code
;
if
(
!
op
)
{
if
(
need_longbranch
)
ccode
=
"jmpf"
;
else
ccode
=
"br"
;
sprintf
(
string
,
"%s %s"
,
ccode
,
label
)
;
return
string
;
}
code
=
GET_CODE
(
op
)
;
if
(
GET_CODE
(
XEXP
(
op
,
0
)
)
!=
REG
)
{
code
=
swap_condition
(
code
)
;
operands
=
"%3,%2"
;
}
else
operands
=
"%2,%3"
;
if
(
really_reversed
)
code
=
reverse_condition
(
code
)
;
switch
(
code
)
{
case
EQ
:
ccode
=
"z"
;
break
;
case
NE
:
ccode
=
"nz"
;
break
;
case
GE
:
ccode
=
"ge"
;
break
;
case
LT
:
ccode
=
"lt"
;
break
;
case
GT
:
ccode
=
"gt"
;
break
;
case
LE
:
ccode
=
"le"
;
break
;
case
GEU
:
ccode
=
"nc"
;
break
;
case
LTU
:
ccode
=
"c"
;
break
;
case
GTU
:
ccode
=
"hi"
;
break
;
case
LEU
:
ccode
=
"ls"
;
break
;
default
:
gcc_unreachable
(
)
;
}
if
(
need_longbranch
)
template
=
"b%s %s,.+8 | jmpf %s"
;
else
template
=
"b%s %s,%s"
;
sprintf
(
string
,
template
,
ccode
,
operands
,
label
)
;
return
string
;
}
</s>

Return the string to output a conditional branch to LABEL , which is the operand number of the label . OP is the conditional expression , or NULL for branch-always . REVERSED is non-zero if we should reverse the sense of the comparison . INSN is the insn .


<s> static int rs6000_issue_rate ( void ) { if ( ! reload_completed && ! flag_sched_pressure ) return 1 ; switch ( rs6000_cpu_attr ) { case CPU_RS64A : case CPU_PPC601 : case CPU_PPC7450 : return 3 ; case CPU_PPC440 : case CPU_PPC603 : case CPU_PPC750 : case CPU_PPC7400 : case CPU_PPC8540 : case CPU_PPC8548 : case CPU_CELL : case CPU_PPCE300C2 : case CPU_PPCE300C3 : case CPU_PPCE500MC : case CPU_PPCE500MC64 : case CPU_PPCE5500 : case CPU_PPCE6500 : case CPU_TITAN : return 2 ; case CPU_PPC476 : case CPU_PPC604 : case CPU_PPC604E : case CPU_PPC620 : case CPU_PPC630 : return 4 ; case CPU_POWER4 : case CPU_POWER5 : case CPU_POWER6 : case CPU_POWER7 : return 5 ; case CPU_POWER8 : case CPU_POWER9 : return 7 ; default : return 1 ; } } </s>

Return how many instructions the machine can issue per cycle .


<s> void HexagonAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB ; MCB . setOpcode ( Hexagon :: BUNDLE ) ; MCB . addOperand ( MCOperand :: createImm ( 0 ) ) ; const MCInstrInfo & MCII = * Subtarget -> getInstrInfo ( ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI -> getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( ! MII -> isDebugInstr ( ) && ! MII -> isImplicitDef ( ) ) HexagonLowerToMC ( MCII , & * MII , MCB , * this ) ; } else { HexagonLowerToMC ( MCII , MI , MCB , * this ) ; } const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const auto & HII = * MF . getSubtarget < HexagonSubtarget > ( ) . getInstrInfo ( ) ; if ( MI -> isBundle ( ) && HII . getBundleNoShuf ( * MI ) ) HexagonMCInstrInfo :: setMemReorderDisabled ( MCB ) ; MCContext & Ctx = OutStreamer -> getContext ( ) ; bool Ok = HexagonMCInstrInfo :: canonicalizePacket ( MCII , * Subtarget , Ctx , MCB , nullptr ) ; assert ( Ok ) ; ( void ) Ok ; if ( HexagonMCInstrInfo :: bundleSize ( MCB ) == 0 ) return ; OutStreamer -> EmitInstruction ( MCB , getSubtargetInfo ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon::BUNDLE 0 Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon 0


<s> void LEGFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; uint64_t StackSize = computeStackSize ( MF ) ; if ( ! StackSize ) { return ; } unsigned StackReg = LEG :: SP ; unsigned OffsetReg = materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ; if ( OffsetReg ) { BuildMI ( MBB , MBBI , dl , TII . get ( LEG :: ADDrr ) , StackReg ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( LEG :: ADDri ) , StackReg ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } </s>


<s>
const
char
*
avr_out_addto_sp
(
rtx
*
op
,
int
*
plen
)
{
int
pc_len
=
AVR_2_BYTE_PC
2
:
3
;
int
addend
=
INTVAL
(
op
[
0
]
)
;
if
(
plen
)
*
plen
=
0
;
if
(
addend
<
0
)
{
if
(
flag_verbose_asm
||
flag_print_asm_name
)
avr_asm_len
(
ASM_COMMENT_START
"SP -= %n0"
,
op
,
plen
,
0
)
;
while
(
addend
<=
pc_len
)
{
addend
+=
pc_len
;
avr_asm_len
(
"rcall ."
,
op
,
plen
,
1
)
;
}
while
(
addend
++
<
0
)
avr_asm_len
(
"push __tmp_reg__"
,
op
,
plen
,
1
)
;
}
else
if
(
addend
>
0
)
{
if
(
flag_verbose_asm
||
flag_print_asm_name
)
avr_asm_len
(
ASM_COMMENT_START
"SP += %0"
,
op
,
plen
,
0
)
;
while
(
addend
>
0
)
avr_asm_len
(
"pop __tmp_reg__"
,
op
,
plen
,
1
)
;
}
return
""
;
}
</s>

PLEN == NULL : Output code to add CONST_INT OP [ 0 ] to SP . PLEN ! = NULL : Set * PLEN to the length of that sequence . Return `` '' .


<s> static bool is_attr_preserve_access ( tree t ) { if ( t == NULL_TREE ) return false ; poly_int64 bitsize , bitpos ; tree var_off ; machine_mode mode ; int sign , reverse , vol ; tree base = get_inner_reference ( t , & bitsize , & bitpos , & var_off , & mode , & sign , & reverse , & vol ) ; if ( TREE_CODE ( base ) == MEM_REF ) { return lookup_attribute ( "preserve_access_index" , TYPE_ATTRIBUTES ( TREE_TYPE ( base ) ) ) ; } if ( TREE_CODE ( t ) == COMPONENT_REF ) { const tree op = TREE_OPERAND ( t , 0 ) ; if ( TREE_CODE ( op ) == COMPONENT_REF ) return is_attr_preserve_access ( op ) ; const tree container = DECL_CONTEXT ( TREE_OPERAND ( t , 1 ) ) ; return lookup_attribute ( "preserve_access_index" , TYPE_ATTRIBUTES ( container ) ) ; } else if ( TREE_CODE ( t ) == ADDR_EXPR ) return is_attr_preserve_access ( TREE_OPERAND ( t , 0 ) ) ; return false ; } </s>

True iff tree T accesses any member of a struct/union/class which is marked with the PRESERVE_ACCESS_INDEX attribute .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .