<s>
const
char
*
arm_output_iwmmxt_shift_immediate
(
const
char
*
insn_name
,
rtx
*
operands
,
bool
wror_or_wsra
)
{
int
shift
=
INTVAL
(
operands
[
2
]
)
;
char
templ
[
50
]
;
machine_mode
opmode
=
GET_MODE
(
operands
[
0
]
)
;
gcc_assert
(
shift
>=
0
)
;
if
(
(
(
opmode
==
V4HImode
)
&&
(
shift
>
15
)
)
||
(
(
opmode
==
V2SImode
)
&&
(
shift
>
31
)
)
||
(
(
opmode
==
DImode
)
&&
(
shift
>
63
)
)
)
{
if
(
wror_or_wsra
)
{
sprintf
(
templ
,
"%s\t%%0, %%1, #%d"
,
insn_name
,
32
)
;
output_asm_insn
(
templ
,
operands
)
;
if
(
opmode
==
DImode
)
{
sprintf
(
templ
,
"%s\t%%0, %%0, #%d"
,
insn_name
,
32
)
;
output_asm_insn
(
templ
,
operands
)
;
}
}
else
{
sprintf
(
templ
,
"wzero\t%%0"
)
;
output_asm_insn
(
templ
,
operands
)
;
}
return
""
;
}
if
(
(
opmode
==
DImode
)
&&
(
shift
>
32
)
)
{
sprintf
(
templ
,
"%s\t%%0, %%1, #%d"
,
insn_name
,
32
)
;
output_asm_insn
(
templ
,
operands
)
;
sprintf
(
templ
,
"%s\t%%0, %%0, #%d"
,
insn_name
,
shift
32
)
;
output_asm_insn
(
templ
,
operands
)
;
}
else
{
sprintf
(
templ
,
"%s\t%%0, %%1, #%d"
,
insn_name
,
shift
)
;
output_asm_insn
(
templ
,
operands
)
;
}
return
""
;
}
</s>

Output assembly for a WMMX immediate shift instruction .


<s> int arc_output_addsi ( rtx * operands , bool cond_p , bool output_p ) { char format [ 32 ] ; int match = operands_match_p ( operands [ 0 ] , operands [ 1 ] ) ; int match2 = operands_match_p ( operands [ 0 ] , operands [ 2 ] ) ; int intval = ( REG_P ( operands [ 2 ] ) ? 1 : CONST_INT_P ( operands [ 2 ] ) ? INTVAL ( operands [ 2 ] ) : 0xbadc057 ) ; int neg_intval = - intval ; int short_0 = satisfies_constraint_Rcq ( operands [ 0 ] ) ; int short_p = ( ! cond_p && short_0 && satisfies_constraint_Rcq ( operands [ 1 ] ) ) ; int ret = 0 ; if ( output_p ) \ output_asm_insn ( FORMAT , operands ) ; \ return ret ; \ } </s>

Emit code for an addsi3 instruction with OPERANDS . COND_P indicates if this will use conditional execution . Return the length of the instruction . If OUTPUT_P is false , do n't actually output the instruction , just return its length .


<s> const MipsTargetLowering * MipsTargetLowering :: create ( const MipsTargetMachine & TM , const MipsSubtarget & STI ) { return llvm :: createMipsSETargetLowering ( TM , STI ) ; } </s>


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
if
(
auto
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
Expr
)
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
CE
->
getValue
(
)
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>


<s> bool HexagonAsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> hasAddressTaken ( ) ) return false ; return AsmPrinter :: isBlockOnlyReachableByFallthrough ( MBB ) ; } </s>

isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the control transfer mechanism between the predecessor and this block is a fall-through .


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ; } </s>

Return information about object file lowering .


<s> bool ARMExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
Thumb1InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
ARMSubtarget
&
st
=
MF
.
getSubtarget
<
ARMSubtarget
>
(
)
;
assert
(
ARM
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
&&
"Thumb1 can only copy GPR registers"
)
;
if
(
st
.
hasV6Ops
(
)
||
ARM
::
hGPRRegClass
.
contains
(
SrcReg
)
||
!
ARM
::
tGPRRegClass
.
contains
(
DestReg
)
)
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tMOVr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
)
;
else
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPUSH
)
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tPOP
)
)
)
.
addReg
(
DestReg
,
getDefRegState
(
true
)
)
;
}
}
</s>

ARM
ARM
ARM
ARM::GPRRegClass
"Thumb1 can only copy GPR registers"
ARM::hGPRRegClass
ARM::tGPRRegClass
ARM::tMOVr
ARM::tPUSH
ARM::tPOP


<s> static rtx ix86_broadcast_from_constant ( machine_mode mode , rtx op ) { int nunits = GET_MODE_NUNITS ( mode ) ; if ( nunits < 2 ) return nullptr ; if ( ! TARGET_INTER_UNIT_MOVES_TO_VEC && INTEGRAL_MODE_P ( mode ) ) return nullptr ; if ( ! ( TARGET_AVX2 || ( TARGET_AVX && ( GET_MODE_INNER ( mode ) == SImode || GET_MODE_INNER ( mode ) == DImode ) ) || FLOAT_MODE_P ( mode ) ) || standard_sse_constant_p ( op , mode ) ) return nullptr ; if ( GET_MODE_INNER ( mode ) == DImode && ! TARGET_64BIT && ( ! TARGET_AVX512F || ( GET_MODE_SIZE ( mode ) < 64 && ! TARGET_AVX512VL ) ) ) return nullptr ; if ( GET_MODE_INNER ( mode ) == TImode ) return nullptr ; rtx constant = get_pool_constant ( XEXP ( op , 0 ) ) ; if ( GET_CODE ( constant ) != CONST_VECTOR ) return nullptr ; if ( GET_MODE ( constant ) != mode ) { constant = simplify_subreg ( mode , constant , GET_MODE ( constant ) , 0 ) ; if ( constant == nullptr || GET_CODE ( constant ) != CONST_VECTOR ) return nullptr ; } rtx first = XVECEXP ( constant , 0 , 0 ) ; for ( int i = 1 ; i < nunits ; ++ i ) { rtx tmp = XVECEXP ( constant , 0 , i ) ; if ( ! rtx_equal_p ( tmp , first ) ) return nullptr ; } return first ; } </s>

OP is a memref of CONST_VECTOR , return scalar constant mem if CONST_VECTOR is a vec_duplicate , else return NULL .


<s>
void
NVPTXInstPrinter
::
printRegName
(
raw_ostream
&
OS
,
unsigned
RegNo
)
const
{
unsigned
RCId
=
(
RegNo
>>
28
)
;
switch
(
RCId
)
{
default
:
report_fatal_error
(
"Bad virtual register encoding"
)
;
case
0
:
OS
<<
getRegisterName
(
RegNo
)
;
return
;
case
1
:
OS
<<
"%p"
;
break
;
case
2
:
OS
<<
"%rs"
;
break
;
case
3
:
OS
<<
"%r"
;
break
;
case
4
:
OS
<<
"%rl"
;
break
;
case
5
:
OS
<<
"%f"
;
break
;
case
6
:
OS
<<
"%fl"
;
break
;
}
unsigned
VReg
=
RegNo
&
0x0FFFFFFF
;
OS
<<
VReg
;
}
</s>


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? STI . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> static void vax_option_override ( void ) { if ( TARGET_G_FLOAT ) REAL_MODE_FORMAT ( DFmode ) = & vax_g_format ; SUBTARGET_OVERRIDE_OPTIONS ; } </s>

Set global variables as needed for the options enabled .


<s> void LanaiFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; const LanaiInstrInfo & LII = * static_cast < const LanaiInstrInfo * > ( STI . getInstrInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , LII . get ( Lanai :: ADD_I_LO ) , Lanai :: SP ) . addReg ( Lanai :: FP ) . addImm ( 0 ) ; BuildMI ( MBB , MBBI , DL , LII . get ( Lanai :: LDW_RI ) , Lanai :: FP ) . addReg ( Lanai :: FP ) . addImm ( - 8 ) . addImm ( LPAC :: ADD ) ; } </s>

Lanai Lanai Lanai Lanai Lanai::ADD_I_LO Lanai::SP Lanai::FP 0 Lanai::LDW_RI Lanai::FP Lanai::FP 8


<s> bool AMDGPUPromoteAlloca :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; if ( auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ) TM = & TPC -> getTM < TargetMachine > ( ) ; else return false ; const Triple & TT = TM -> getTargetTriple ( ) ; IsAMDGCN = TT . getArch ( ) == Triple :: amdgcn ; IsAMDHSA = TT . getOS ( ) == Triple :: AMDHSA ; const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( F ) ; if ( ! ST . isPromoteAllocaEnabled ( ) ) return false ; AS = AMDGPU :: getAMDGPUAS ( * F . getParent ( ) ) ; bool SufficientLDS = hasSufficientLocalMem ( F ) ; bool Changed = false ; BasicBlock & EntryBB = * F . begin ( ) ; for ( auto I = EntryBB . begin ( ) , E = EntryBB . end ( ) ; I != E ; ) { AllocaInst * AI = dyn_cast < AllocaInst > ( I ) ; ++ I ; if ( AI ) Changed |= handleAlloca ( * AI , SufficientLDS ) ; } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU::getAMDGPUAS


<s> void BTFTypeTag :: emitType ( MCStreamer & OS ) { BTFTypeBase :: emitType ( OS ) ; OS . emitInt32 ( Info ) ; } </s>


<s>
bool
AArch64AsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
assert
(
!
MO
.
getSubReg
(
)
&&
"Subregs should be eliminated!"
)
;
MCOp
=
MCOperand
::
CreateReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Mang
->
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_RegisterMask
:
return
false
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s>
const
LegalizerInfo
*
ARMSubtarget
::
getLegalizerInfo
(
)
const
{
assert
(
GISel
&&
"Access to GlobalISel APIs not set"
)
;
return
GISel
->
getLegalizerInfo
(
)
;
}
</s>

Expose LegalizerInfo so the clients can re-use .

ARM
ARM
"Access to GlobalISel APIs not set"


<s> virtual bool runOnFunction ( Function & Fn ) { GlobalBaseReg = 0 ; return SelectionDAGISel :: runOnFunction ( Fn ) ; } </s>


<s> void LoongArchAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { return ; } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
NVPTXPassConfig
::
addOptimizedRegAlloc
(
)
{
addPass
(
&
ProcessImplicitDefsID
)
;
addPass
(
&
LiveVariablesID
)
;
addPass
(
&
MachineLoopInfoID
)
;
addPass
(
&
PHIEliminationID
)
;
addPass
(
&
TwoAddressInstructionPassID
)
;
addPass
(
&
RegisterCoalescerID
)
;
if
(
addPass
(
&
MachineSchedulerID
)
)
printAndVerify
(
"After Machine Scheduling"
)
;
addPass
(
&
StackSlotColoringID
)
;
printAndVerify
(
"After StackSlotColoring"
)
;
}
</s>

addOptimizedRegAlloc - Add passes related to register allocation .

NVPTX
NVPTX
"After Machine Scheduling"
"After StackSlotColoring"


"the layout of aggregates containing vectors with"

" %d-byte alignment has changed in GCC 5"

Previous GCC releases forced all vector types to have 16-byte alignment .


"Unhandled instruction encoding format!"

Targets should implement this to emit instructions .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; AU . addRequired < MachineDominatorTree > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool LanaiInstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { return false ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> void * getAdjustedAnalysisPointer ( const void * ID ) override { if ( ID == & TargetTransformInfo :: ID ) return ( TargetTransformInfo * ) this ; return this ; } </s>

getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance .


<s> outliner :: OutlinedFunction RISCVInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { auto CannotInsertCall = [ ] ( outliner :: Candidate & C ) { const TargetRegisterInfo * TRI = C . getMF ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; return ! C . isAvailableAcrossAndOutOfSeq ( RISCV :: X5 , * TRI ) ; } ; llvm :: erase_if ( RepeatedSequenceLocs , CannotInsertCall ) ; if ( RepeatedSequenceLocs . size ( ) < 2 ) return outliner :: OutlinedFunction ( ) ; unsigned SequenceSize = 0 ; auto I = RepeatedSequenceLocs [ 0 ] . front ( ) ; auto E = std :: next ( RepeatedSequenceLocs [ 0 ] . back ( ) ) ; for ( ; I != E ; ++ I ) SequenceSize += getInstSizeInBytes ( * I ) ; unsigned CallOverhead = 8 ; for ( auto & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerDefault , CallOverhead ) ; unsigned FrameOverhead = 4 ; if ( RepeatedSequenceLocs [ 0 ] . getMF ( ) -> getSubtarget ( ) . getFeatureBits ( ) [ RISCV :: FeatureStdExtC ] ) FrameOverhead = 2 ; return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , FrameOverhead , MachineOutlinerDefault ) ; } </s>

Returns a outliner : :OutlinedFunction struct containing target-specific information for a set of outlining candidates .


<s> bool PatmosRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { if ( Patmos :: PRegsRegClass . contains ( Reg ) ) return true ; const PatmosMachineFunctionInfo & PMFI = * MF . getInfo < PatmosMachineFunctionInfo > ( ) ; if ( Reg == Patmos :: S0 && PMFI . getS0SpillReg ( ) ) return true ; return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .

Patmos Patmos Patmos::PRegsRegClass Patmos Patmos Patmos::S0


<s> void mmix_initialize_trampoline ( rtx trampaddr , rtx fnaddr , rtx static_chain ) { emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( trampaddr , 16 ) ) , static_chain ) ; emit_move_insn ( gen_rtx_MEM ( DImode , plus_constant ( trampaddr , 24 ) ) , fnaddr ) ; emit_insn ( gen_sync_icache ( validize_mem ( gen_rtx_MEM ( DImode , trampaddr ) ) , GEN_INT ( mmix_trampoline_size - 1 ) ) ) ; } </s>

Set the static chain and function pointer field in the trampoline . We also SYNCID here to be sure ( does n't matter in the simulator , but some day it will ) .


<s> static inline int extract_22 ( unsigned word ) { return sign_extend ( GET_FIELD ( word , 19 , 28 ) | GET_FIELD ( word , 29 , 29 ) << 10 | GET_FIELD ( word , 11 , 15 ) << 11 | GET_FIELD ( word , 6 , 10 ) << 16 | ( word & 0x1 ) << 21 , 22 ) ; } </s>

Extract a 22-bit signed constant from branch instructions .


<s> unsigned SystemZInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { if ( MI . isInlineAsm ( ) ) { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const char * AsmStr = MI . getOperand ( 0 ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } return MI . getDesc ( ) . getSize ( ) ; } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> rtx extract_offset_rtx ( rtx_insn * insn ) { rtx mem_rtx ; rtx plus_rtx ; rtx offset_rtx ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : return NULL_RTX ; case TYPE_LOAD : case TYPE_FLOAD : case TYPE_STORE : case TYPE_FSTORE : mem_rtx = extract_mem_rtx ( insn ) ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( MEM_P ( mem_rtx ) ) ; if ( REG_P ( XEXP ( mem_rtx , 0 ) ) ) return NULL_RTX ; plus_rtx = XEXP ( mem_rtx , 0 ) ; switch ( GET_CODE ( plus_rtx ) ) { case SYMBOL_REF : case CONST : case POST_INC : case POST_DEC : return NULL_RTX ; case PLUS : if ( REG_P ( XEXP ( plus_rtx , 0 ) ) ) offset_rtx = XEXP ( plus_rtx , 1 ) ; else { gcc_assert ( REG_P ( XEXP ( plus_rtx , 1 ) ) ) ; offset_rtx = XEXP ( plus_rtx , 0 ) ; } if ( ARITHMETIC_P ( offset_rtx ) ) { gcc_assert ( GET_CODE ( offset_rtx ) == MULT ) ; gcc_assert ( REG_P ( XEXP ( offset_rtx , 0 ) ) ) ; offset_rtx = XEXP ( offset_rtx , 0 ) ; } break ; case LO_SUM : offset_rtx = XEXP ( plus_rtx , 1 ) ; break ; case POST_MODIFY : gcc_assert ( REG_P ( XEXP ( plus_rtx , 0 ) ) ) ; plus_rtx = XEXP ( plus_rtx , 1 ) ; gcc_assert ( GET_CODE ( plus_rtx ) == PLUS ) ; offset_rtx = XEXP ( plus_rtx , 0 ) ; break ; default : gcc_unreachable ( ) ; } return offset_rtx ; } </s>

Extract the offset rtx from load/store insns . The function returns NULL_RTX if offset is absent .


"MIa must load from or modify a memory location"

"MIb must load from or modify a memory location"

Sometimes , it is possible for the target to tell , even without aliasing information , that two MIs access different memory addresses .


<s>
void
BPFInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
BPF
::
GPRRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
BPF
::
MOV_rr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
BPF
::
GPR32RegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
BPF
::
MOV_rr_32
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
</s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < Nios2Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createSystemZObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s>
const
char
*
getPassName
(
)
const
{
return
"DCPU16 optimize conditional branches"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Load should return a value and a chain"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static void fixup_mova ( rtx mova ) { if ( ! flag_pic ) { SET_SRC ( PATTERN ( mova ) ) = XVECEXP ( SET_SRC ( PATTERN ( mova ) ) , 0 , 0 ) ; INSN_CODE ( mova ) = - 1 ; } else { rtx worker = mova ; rtx lab = gen_label_rtx ( ) ; rtx wpat , wpat0 , wpat1 , wsrc , diff ; do { worker = NEXT_INSN ( worker ) ; gcc_assert ( worker && GET_CODE ( worker ) != CODE_LABEL && GET_CODE ( worker ) != JUMP_INSN ) ; } while ( GET_CODE ( worker ) == NOTE || recog_memoized ( worker ) != CODE_FOR_casesi_worker_1 ) ; wpat = PATTERN ( worker ) ; wpat0 = XVECEXP ( wpat , 0 , 0 ) ; wpat1 = XVECEXP ( wpat , 0 , 1 ) ; wsrc = SET_SRC ( wpat0 ) ; PATTERN ( worker ) = ( gen_casesi_worker_2 ( SET_DEST ( wpat0 ) , XVECEXP ( wsrc , 0 , 1 ) , XEXP ( XVECEXP ( wsrc , 0 , 2 ) , 0 ) , lab , XEXP ( wpat1 , 0 ) ) ) ; INSN_CODE ( worker ) = - 1 ; diff = gen_rtx_MINUS ( Pmode , XVECEXP ( SET_SRC ( PATTERN ( mova ) ) , 0 , 0 ) , gen_rtx_LABEL_REF ( Pmode , lab ) ) ; diff = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , diff ) , UNSPEC_PIC ) ; SET_SRC ( PATTERN ( mova ) ) = gen_rtx_CONST ( Pmode , diff ) ; INSN_CODE ( mova ) = - 1 ; } } </s>

Fix up a mova from a switch that went out of range .


<s> yaml :: MachineFunctionInfo * RISCVTargetMachine :: convertFuncInfoToYAML ( const MachineFunction & MF ) const { const auto * MFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; return new yaml :: RISCVMachineFunctionInfo ( * MFI ) ; } </s>

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo .


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> const uint32_t * WDC65816RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { return CSR_NoRegs_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void mips_split_msa_insert_d ( rtx dest , rtx src1 , rtx index , rtx src2 ) { int i ; gcc_assert ( GET_MODE ( dest ) == GET_MODE ( src1 ) ) ; gcc_assert ( ( GET_MODE ( dest ) == V2DImode && ( GET_MODE ( src2 ) == DImode || src2 == const0_rtx ) ) || ( GET_MODE ( dest ) == V2DFmode && GET_MODE ( src2 ) == DFmode ) ) ; rtx low = mips_subword ( src2 , false ) ; rtx high = mips_subword ( src2 , true ) ; rtx new_dest = simplify_gen_subreg ( V4SImode , dest , GET_MODE ( dest ) , 0 ) ; rtx new_src1 = simplify_gen_subreg ( V4SImode , src1 , GET_MODE ( src1 ) , 0 ) ; i = exact_log2 ( INTVAL ( index ) ) ; gcc_assert ( i != - 1 ) ; emit_insn ( gen_msa_insert_w ( new_dest , low , new_src1 , GEN_INT ( 1 << ( i * 2 ) ) ) ) ; emit_insn ( gen_msa_insert_w ( new_dest , high , new_dest , GEN_INT ( 1 << ( i * 2 + 1 ) ) ) ) ; } </s>

Split a INSERT.D with operand DEST , SRC1.INDEX and SRC2 .


"Branch removal not supported, as MBB info not propagated"

" to OpPhi instructions. Try using -O0 instead."

Remove the branching code at the end of the specific MBB .


"-max-stackframe=%d is not usable, not between 0 and %d"

"unknown CRIS version specification in -march= or -mcpu= : %s"

"unknown CRIS cpu version specification in -mtune= : %s"

"-fPIC and -fpic are not supported in this configuration"

"that particular -g option is invalid with -maout and -melinux"

The OVERRIDE_OPTIONS worker . As is the norm , this also parses -mfoo=bar type parameters .


<s> bool compact_sda_memory_operand ( rtx op , machine_mode mode ) { rtx addr ; int size ; if ( GET_CODE ( op ) != MEM ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; size = GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD ) return false ; addr = XEXP ( op , 0 ) ; return LEGITIMATE_SMALL_DATA_ADDRESS_P ( addr ) ; } </s>

volatile cache option still to be handled .


<s> static rtx_insn * frame_insn ( rtx x ) { int i ; rtx note = NULL_RTX ; rtx_insn * insn ; if ( GET_CODE ( x ) == PARALLEL ) { rtx part = XVECEXP ( x , 0 , 0 ) ; if ( GET_MODE ( SET_DEST ( part ) ) == DImode ) { note = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( XVECLEN ( x , 0 ) + 1 ) ) ; XVECEXP ( note , 0 , 0 ) = frame_subreg_note ( part , 0 ) ; XVECEXP ( note , 0 , 1 ) = frame_subreg_note ( part , UNITS_PER_WORD ) ; for ( i = XVECLEN ( x , 0 ) - 1 ; i >= 1 ; i -- ) { part = copy_rtx ( XVECEXP ( x , 0 , i ) ) ; if ( GET_CODE ( part ) == SET ) RTX_FRAME_RELATED_P ( part ) = 1 ; XVECEXP ( note , 0 , i + 1 ) = part ; } } else { for ( i = XVECLEN ( x , 0 ) - 1 ; i >= 0 ; i -- ) { part = XVECEXP ( x , 0 , i ) ; if ( GET_CODE ( part ) == SET ) RTX_FRAME_RELATED_P ( part ) = 1 ; } } } else if ( GET_CODE ( x ) == SET && GET_MODE ( SET_DEST ( x ) ) == DImode ) note = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , frame_subreg_note ( x , 0 ) , frame_subreg_note ( x , UNITS_PER_WORD ) ) ) ; insn = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; if ( note ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note ) ; return insn ; } </s>

Emit the specified insn and mark it as frame related . FIXME : Rename this to emit_frame_insn .


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , DebugLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s>
MachineBasicBlock
::
iterator
XtensaFrameLowering
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
llvm_unreachable
(
"Couldn't reach here"
)
;
return
I
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void m32r_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size , int no_rtl ) { int first_anon_arg ; if ( no_rtl ) return ; gcc_assert ( arg . mode != BLKmode ) ; first_anon_arg = ( ROUND_ADVANCE_CUM ( * get_cumulative_args ( cum ) , arg . mode , arg . type ) + ROUND_ADVANCE_ARG ( arg . mode , arg . type ) ) ; if ( first_anon_arg < M32R_MAX_PARM_REGS ) { int first_reg_offset = first_anon_arg ; int size = M32R_MAX_PARM_REGS - first_reg_offset ; rtx regblock ; regblock = gen_frame_mem ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( 0 ) ) ) ; set_mem_alias_set ( regblock , get_varargs_alias_set ( ) ) ; move_block_from_reg ( first_reg_offset , regblock , size ) ; * pretend_size = ( size * UNITS_PER_WORD ) ; } } </s>

Do any needed setup for a variadic function . For the M32R , we must create a register parameter block , and then copy any anonymous arguments in registers to memory . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> SDValue AMDGPUTargetLowering :: SplitVectorLoad ( const SDValue Op , SelectionDAG & DAG ) const { LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return scalarizeVectorLoad ( Load , DAG ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; EVT PtrVT = BasePtr . getValueType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; SDLoc SL ( Op ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( Size , SL , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ops [ ] = { DAG . getNode ( ISD :: CONCAT_VECTORS , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoLoad . getValue ( 1 ) , HiLoad . getValue ( 1 ) ) } ; return DAG . getMergeValues ( Ops , SL ) ; } </s>

Split a vector load into 2 loads of half the vector .


<s> void EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static inline bool mode_supports_vsx_dform_quad ( machine_mode mode ) { return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_ANY ] & RELOAD_REG_QUAD_OFFSET ) != 0 ) ; } </s>

Return true if we have D-form addressing in VSX registers . This addressing is more limited than normal d-form addressing in that the offset must be aligned on a 16-byte boundary .


<s> int mcore_num_zeros ( int mask ) { return 32 - mcore_num_ones ( mask ) ; } </s>


"Prefetch distance is not set for target"

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void split_adds_subs ( enum machine_mode mode , rtx * operands ) { HOST_WIDE_INT val = INTVAL ( operands [ 1 ] ) ; rtx reg = operands [ 0 ] ; HOST_WIDE_INT sign = 1 ; HOST_WIDE_INT amount ; rtx ( * gen_add ) ( rtx , rtx , rtx ) ; if ( val < 0 ) { val = - val ; sign = - 1 ; } switch ( mode ) { case HImode : gen_add = gen_addhi3 ; break ; case SImode : gen_add = gen_addsi3 ; break ; default : gcc_unreachable ( ) ; } for ( amount = ( TARGET_H8300H || TARGET_H8300S ) ? 4 : 2 ; amount > 0 ; amount /= 2 ) { for ( ; val >= amount ; val -= amount ) emit_insn ( gen_add ( reg , reg , GEN_INT ( sign * amount ) ) ) ; } return ; } </s>

Split an add of a small constant into two adds/subs insns .


<s> void AArch64PassConfig :: addCodeGenPrepare ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createTypePromotionPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> Value * X86TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( Subtarget . getTargetTriple ( ) . isOSContiki ( ) ) return getDefaultSafeStackPointerLocation ( IRB , false ) ; if ( Subtarget . isTargetAndroid ( ) ) { unsigned Offset = ( Subtarget . is64Bit ( ) ) ? 0x48 : 0x24 ; return SegmentOffset ( IRB , Offset , getAddressSpace ( ) ) ; } if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , 0x18 , 257 ) ; } return TargetLowering :: getSafeStackPointerLocation ( IRB ) ; } </s>

Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space , and populates the address space and offset as appropriate .


<s> const ARMSubtarget & getSubtarget ( ) const { return Subtarget ; } </s>

getSubtarget - Return the subtarget for which this machine code is being compiled .


<s>
void
relaxInstruction
(
const
MCInst
&
Inst
,
MCInst
&
Res
)
const
{
assert
(
0
&&
"relaxInstruction() unimplemented"
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .

Sparc
0
"relaxInstruction() unimplemented"


<s> bool AMDGPUAnnotateKernelFeatures :: runOnSCC ( CallGraphSCC & SCC ) { bool Changed = false ; for ( CallGraphNode * I : SCC ) { if ( I -> getNumReferences ( ) ) NodeList . push_back ( I ) ; else { processUniformWorkGroupAttribute ( ) ; NodeList . clear ( ) ; } Function * F = I -> getFunction ( ) ; if ( ! F || F -> isDeclaration ( ) ) continue ; Changed |= addFeatureAttributes ( * F ) ; } return Changed ; } </s>

runOnSCC - This method should be implemented by the subclass to perform whatever action is necessary for the specified SCC .


<s> bool X86TargetLowering :: hasBitTest ( SDValue X , SDValue Y ) const { return X . getValueType ( ) . isScalarInteger ( ) ; } </s>

Return true if the target has a bit-test instruction : ( X & ( 1 < < Y ) ) ==/ ! = 0 This knowledge can be used to prevent breaking the pattern , or creating it if it could be recognized .


<s> void XNCMInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> bool arm_frame_pointer_required ( void ) { return ( cfun -> has_nonlocal_label || SUBTARGET_FRAME_POINTER_REQUIRED || ( TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ( ) ) ) ; } </s>


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; initialize ( MF ) ; bool ZExtSeqExist , ZExtExist ; ZExtSeqExist = eliminateZExtSeq ( ) ; ZExtExist = eliminateZExt ( ) ; return ZExtSeqExist || ZExtExist ; } </s>

runOnMachineFunction - Emit the function body .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


"parameter passing for argument of type "

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


<s> bool Z80AsmPrinter :: doFinalization ( Module & M ) { bool res = AsmPrinter :: doFinalization ( M ) ; return res ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s>
const
char
*
rs6000_insn_for_insert_mask
(
machine_mode
mode
,
rtx
*
operands
,
bool
dot
)
{
int
nb
,
ne
;
if
(
!
rs6000_is_valid_mask
(
operands
[
3
]
,
&
nb
,
&
ne
,
mode
)
)
gcc_unreachable
(
)
;
if
(
TARGET_POWERPC64
&&
(
!
dot
||
mode
==
DImode
)
&&
GET_CODE
(
operands
[
4
]
)
!=
LSHIFTRT
&&
ne
==
INTVAL
(
operands
[
2
]
)
)
{
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rldimi. %0,%1,%2,%3"
;
return
"rldimi %0,%1,%2,%3"
;
}
if
(
nb
<
32
&&
ne
<
32
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
32
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
31
nb
)
;
operands
[
4
]
=
GEN_INT
(
31
ne
)
;
if
(
dot
)
return
"rlwimi. %0,%1,%2,%3,%4"
;
return
"rlwimi %0,%1,%2,%3,%4"
;
}
gcc_unreachable
(
)
;
}
</s>

Return the instruction template for an insert with mask in mode MODE , with operands OPERANDS . If DOT is true , make it a record-form instruction .


<s> rtx_insn * sh_peephole_emit_move_insn ( rtx dst , rtx src ) { return sh_check_add_incdec_notes ( emit_move_insn ( dst , sh_remove_overlapping_post_inc ( dst , src ) ) ) ; } </s>

Emit a move insn that is safe to be used in peephole patterns .


<s> static bool isEqual ( const SlotWithTag & A , const SlotWithTag & B ) { return A == B ; } </s>

isEqual - Compares two trees for structural equality and returns true if they are equal .


<s> bool BTFDebug :: InstLower ( const MachineInstr * MI , MCInst & OutMI ) { if ( MI -> getOpcode ( ) == BPF :: LD_imm64 ) { const MachineOperand & MO = MI -> getOperand ( 1 ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar ) { int64_t Imm ; uint32_t Reloc ; if ( GVar -> hasAttribute ( BPFCoreSharedInfo :: AmaAttr ) || GVar -> hasAttribute ( BPFCoreSharedInfo :: TypeIdAttr ) ) { Imm = PatchImms [ GVar ] . first ; Reloc = PatchImms [ GVar ] . second ; } else { return false ; } if ( Reloc == BPFCoreSharedInfo :: ENUM_VALUE_EXISTENCE || Reloc == BPFCoreSharedInfo :: ENUM_VALUE ) OutMI . setOpcode ( BPF :: LD_imm64 ) ; else OutMI . setOpcode ( BPF :: MOV_ri ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ; } } } else if ( MI -> getOpcode ( ) == BPF :: CORE_MEM || MI -> getOpcode ( ) == BPF :: CORE_ALU32_MEM || MI -> getOpcode ( ) == BPF :: CORE_SHIFT ) { const MachineOperand & MO = MI -> getOperand ( 3 ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( BPFCoreSharedInfo :: AmaAttr ) ) { uint32_t Imm = PatchImms [ GVar ] . first ; OutMI . setOpcode ( MI -> getOperand ( 1 ) . getImm ( ) ) ; if ( MI -> getOperand ( 0 ) . isImm ( ) ) OutMI . addOperand ( MCOperand :: createImm ( MI -> getOperand ( 0 ) . getImm ( ) ) ) ; else OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( 2 ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ; } } } return false ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > SparcTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return std :: make_pair ( 0U , & SP :: IntRegsRegClass ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= 5 && Constraint [ 0 ] == '{' && * ( Constraint . end ( ) - 1 ) == '}' ) { StringRef name ( Constraint . data ( ) + 1 , Constraint . size ( ) - 2 ) ; uint64_t intVal = 0 ; if ( name . substr ( 0 , 1 ) . equals ( "r" ) && ! name . substr ( 1 ) . getAsInteger ( 10 , intVal ) && intVal <= 31 ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / 8 ] ; char regIdx = '0' + ( intVal % 8 ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , 0 } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( newConstraint , VT ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"CPRESTORE's operand must be an immediate."

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static rtx compute_frame_addr ( int offset_from_fp , int * next_scratch_regno ) { rtx base_reg_rtx , tmp_reg_rtx , offset_rtx ; int offset_from_base ; if ( frame_pointer_needed ) { base_reg_rtx = hard_frame_pointer_rtx ; offset_from_base = offset_from_fp ; } else { int offset_from_sp = compute_total_frame_size ( ) + offset_from_fp ; offset_from_base = offset_from_sp ; base_reg_rtx = stack_pointer_rtx ; } if ( offset_from_base == 0 ) return base_reg_rtx ; tmp_reg_rtx = gen_rtx_REG ( Pmode , ( * next_scratch_regno ) -- ) ; offset_rtx = GEN_INT ( offset_from_base ) ; if ( ! add_operand ( offset_rtx , Pmode ) ) { expand_set_cint64 ( tmp_reg_rtx , offset_rtx ) ; offset_rtx = tmp_reg_rtx ; } emit_insn ( gen_rtx_SET ( VOIDmode , tmp_reg_rtx , gen_rtx_PLUS ( Pmode , base_reg_rtx , offset_rtx ) ) ) ; return tmp_reg_rtx ; } </s>

Returns an rtx for a stack slot at 'FP + offset_from_fp ' . If there is a frame pointer , it computes the value relative to that . Otherwise it uses the stack pointer .


<s> void aarch64_split_simd_move ( rtx dst , rtx src ) { machine_mode src_mode = GET_MODE ( src ) ; machine_mode dst_mode = GET_MODE ( dst ) ; gcc_assert ( VECTOR_MODE_P ( dst_mode ) ) ; if ( REG_P ( dst ) && REG_P ( src ) ) { rtx ( * gen ) ( rtx , rtx ) ; gcc_assert ( VECTOR_MODE_P ( src_mode ) ) ; switch ( src_mode ) { case V16QImode : gen = gen_aarch64_split_simd_movv16qi ; break ; case V8HImode : gen = gen_aarch64_split_simd_movv8hi ; break ; case V4SImode : gen = gen_aarch64_split_simd_movv4si ; break ; case V2DImode : gen = gen_aarch64_split_simd_movv2di ; break ; case V8HFmode : gen = gen_aarch64_split_simd_movv8hf ; break ; case V4SFmode : gen = gen_aarch64_split_simd_movv4sf ; break ; case V2DFmode : gen = gen_aarch64_split_simd_movv2df ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src ) ) ; return ; } } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > NVPTXTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'c' : return std :: make_pair ( 0U , & NVPTX :: Int8RegsRegClass ) ; case 'h' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'r' : return std :: make_pair ( 0U , & NVPTX :: Int32RegsRegClass ) ; case 'l' : case 'N' : return std :: make_pair ( 0U , & NVPTX :: Int64RegsRegClass ) ; case 'f' : return std :: make_pair ( 0U , & NVPTX :: Float32RegsRegClass ) ; case 'd' : return std :: make_pair ( 0U , & NVPTX :: Float64RegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>


" Declaring this symbol tells the CRT that it should"

"copy all variables from program memory to RAM on startup"

"clear the zeroed data section on startup"

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo . get ( ) ; } </s>

getRegInfo - Return information about the registers currently in use .


<s> const M88kRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"could not find corresponding %pcrel_hi"

Hook to check if a relocation is needed for some target specific reason .


<s> bool ARMFastISel :: fastLowerArguments ( ) { if ( ! FuncInfo . CanLowerReturn ) return false ; const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { default : return false ; case CallingConv :: Fast : case CallingConv :: C : case CallingConv :: ARM_AAPCS_VFP : case CallingConv :: ARM_AAPCS : case CallingConv :: ARM_APCS : break ; } unsigned Idx = 1 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( Idx > 4 ) return false ; if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) return false ; Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : break ; default : return false ; } } static const uint16_t GPRArgRegs [ ] = { ARM :: R0 , ARM :: R1 , ARM :: R2 , ARM :: R3 } ; const TargetRegisterClass * RC = & ARM :: rGPRRegClass ; Idx = 0 ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ; updateValueMap ( & * I , ResultReg ) ; } return true ; } </s>

This method is called by target-independent code to do target- specific argument lowering .


<s> bool HexagonSubtarget :: enableSubRegLiveness ( ) const { return EnableSubregLiveness ; } </s>

Enable tracking of subregister liveness in register allocator .


<s> bool legitimate_address_p ( enum machine_mode mode ATTRIBUTE_UNUSED , rtx addr , int strict ) { struct s390_address ad ; if ( ! s390_decompose_address ( addr , & ad ) ) return false ; if ( strict ) { if ( ad . base && ! REG_OK_FOR_BASE_STRICT_P ( ad . base ) ) return false ; if ( ad . indx && ! REG_OK_FOR_INDEX_STRICT_P ( ad . indx ) ) return false ; } else { if ( ad . base && ! REG_OK_FOR_BASE_NONSTRICT_P ( ad . base ) ) return false ; if ( ad . indx && ! REG_OK_FOR_INDEX_NONSTRICT_P ( ad . indx ) ) return false ; } return true ; } </s>

legitimate_address_p returns 1 if it recognizes an RTL expression `` x '' that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address .


<s> bool CheckReturn ( const SmallVectorImpl < ISD :: OutputArg > & ArgsFlags , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ; OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ; return Return ; } </s>

CheckReturn - Analyze the return values of a function , returning true if the return can be performed without sret-demotion , and false otherwise .


Return an array that contains the direct target flag values and their names .


Allocate ORIG_SIZE bytes on the stack and probe the newly allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes . COPY_REG , if non-null , should contain a copy of the original stack pointer at exit from this function . This is subtly different than the Ada probing in that it tries hard to prevent attacks that jump the stack guard . Thus it is never allowed to allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack space without a suitable probe .


<s> bool PPCTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { if ( ! Subtarget . is64BitELFABI ( ) ) return false ; if ( ! CI -> isTailCall ( ) ) return false ; const Function * Caller = CI -> getParent ( ) -> getParent ( ) ; auto Attr = Caller -> getFnAttribute ( "disable-tail-calls" ) ; if ( Attr . getValueAsString ( ) == "true" ) return false ; auto & TM = getTargetMachine ( ) ; if ( ! TM . Options . GuaranteedTailCallOpt && DisableSCO ) return false ; const Function * Callee = CI -> getCalledFunction ( ) ; if ( ! Callee || Callee -> isVarArg ( ) ) return false ; if ( ! areCallingConvEligibleForTCO_64SVR4 ( Caller -> getCallingConv ( ) , CI -> getCallingConv ( ) ) ) return false ; return getTargetMachine ( ) . shouldAssumeDSOLocal ( * Caller -> getParent ( ) , Callee ) ; } </s>

Return true if the target may be able emit the call instruction as a tail call .


<s> SMLoc getEndLoc ( ) const override { return EndLoc ; } </s>

getEndLoc - Get the location of the last token of this operand .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineFunction
::
iterator
MFI
=
Fn
.
begin
(
)
,
E
=
Fn
.
end
(
)
;
MFI
!=
E
;
++
MFI
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MFI
->
begin
(
)
,
ME
=
MFI
->
end
(
)
;
MI
!=
ME
;
)
{
Modified
|=
runOnInstruction
(
MI
++
)
;
}
}
for
(
std
::
set
<
MachineInstr
*
>
::
iterator
I
=
DeadInstr
.
begin
(
)
,
E
=
DeadInstr
.
end
(
)
;
I
!=
E
;
++
I
)
{
(
*
I
)
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> rtx extract_mac_non_acc_rtx ( rtx_insn * insn ) { rtx exp = SET_SRC ( PATTERN ( insn ) ) ; switch ( get_attr_type ( insn ) ) { case TYPE_MAC : case TYPE_DMAC : if ( REG_P ( XEXP ( exp , 0 ) ) ) return XEXP ( exp , 1 ) ; else return XEXP ( exp , 0 ) ; default : gcc_unreachable ( ) ; } } </s>

Extract the rtx representing non-accumulation operands of a MAC insn .


<s> bool MSP430TargetLowering :: shouldAvoidTransformToShift ( EVT VT , unsigned Amount ) const { return ! ( Subtarget -> hasMSP430X ( ) || Amount == 8 || Amount == 9 || Amount <= 2 ) ; } </s>

Return true if creating a shift of the type by the given amount is not profitable .


<s> static bool can_use_mov_pic_label_ref ( rtx label ) { if ( TARGET_VXWORKS_RTP ) return false ; if ( LABEL_REF_NONLOCAL_P ( label ) ) return false ; if ( flag_reorder_blocks_and_partition ) return false ; return true ; } </s>

Return true if the address of LABEL can be loaded by means of the mov { si , di } _pic_label_ref patterns in PIC mode .


<s> int frv_adjust_field_align ( tree field , int computed ) { if ( DECL_BIT_FIELD ( field ) && ! DECL_ARTIFICIAL ( field ) ) { tree parent = DECL_CONTEXT ( field ) ; tree prev = NULL_TREE ; tree cur ; for ( cur = TYPE_FIELDS ( parent ) ; cur && cur != field ; cur = DECL_CHAIN ( cur ) ) { if ( TREE_CODE ( cur ) != FIELD_DECL ) continue ; prev = cur ; } gcc_assert ( cur ) ; if ( prev && ! DECL_PACKED ( field ) && ! integer_zerop ( DECL_SIZE ( field ) ) && DECL_BIT_FIELD_TYPE ( field ) != DECL_BIT_FIELD_TYPE ( prev ) ) { int prev_align = TYPE_ALIGN ( TREE_TYPE ( prev ) ) ; int cur_align = TYPE_ALIGN ( TREE_TYPE ( field ) ) ; computed = ( prev_align > cur_align ) ? prev_align : cur_align ; } } return computed ; } </s>

The definition type of the bit field data is either char , short , long or long long . The maximum bit size is the number of bits of its own type . The bit field data is assigned to a storage unit that has an adequate size for bit field data retention and is located at the smallest address . Consecutive bit field data are packed at consecutive bits having the same storage unit , with regard to the type , beginning with the MSB and continuing toward the LSB . If a field to be assigned lies over a bit field type boundary , its assignment is completed by aligning it with a boundary suitable for the type . When a bit field having a bit length of 0 is declared , it is forcibly assigned to the next storage unit . e.g ) struct { int a:2 ; int b:6 ; char c:4 ; int d:10 ; int :0 ; int f:2 ; } x ; +0 +1 +2 +3 & x 00000000 00000000 00000000 00000000 MLM -- -- L a b & x+4 00000000 00000000 00000000 00000000 M -- L c & x+8 00000000 00000000 00000000 00000000 M -- -- -- -- -- L d & x+12 00000000 00000000 00000000 00000000 ML f


<s>
void
HexagonInstPrinter
::
printInst
(
const
HexagonMCInst
*
MI
,
raw_ostream
&
O
,
StringRef
Annot
)
{
const
char
startPacket
=
'{'
,
endPacket
=
'}'
;
if
(
MI
->
getOpcode
(
)
==
Hexagon
::
ENDLOOP0
)
{
assert
(
MI
->
isPacketEnd
(
)
&&
"Loop-end must also end the packet"
)
;
if
(
MI
->
isPacketStart
(
)
)
{
HexagonMCInst
Nop
;
StringRef
NoAnnot
;
Nop
.
setOpcode
(
Hexagon
::
NOP
)
;
Nop
.
setPacketStart
(
MI
->
isPacketStart
(
)
)
;
printInst
(
&
Nop
,
O
,
NoAnnot
)
;
}
if
(
MI
->
isPacketEnd
(
)
)
O
<<
PacketPadding
<<
endPacket
;
printInstruction
(
MI
,
O
)
;
}
else
{
if
(
MI
->
isPacketStart
(
)
)
O
<<
PacketPadding
<<
startPacket
<<
'\n'
;
printInstruction
(
MI
,
O
)
;
if
(
MI
->
isPacketEnd
(
)
)
O
<<
'\n'
<<
PacketPadding
<<
endPacket
;
}
printAnnotation
(
O
,
Annot
)
;
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
Hexagon
Hexagon::ENDLOOP0
"Loop-end must also end the packet"
Hexagon
Hexagon::NOP


<s> bool isImm ( ) const { return Kind == Immediate ; } </s>


<s> bool Cpu0SEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & static_cast < const Cpu0Subtarget & > ( MF . getSubtarget ( ) ) ; return Cpu0DAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s>
static
const
char
*
pru_output_gtge_signed_cbranch
(
rtx
*
operands
,
bool
is_near
)
{
static
char
buf
[
1024
]
;
enum
rtx_code
code
=
GET_CODE
(
operands
[
0
]
)
;
rtx
op1
;
rtx
op2
;
const
char
*
cmp_opstr
;
int
bufi
=
0
;
op1
=
operands
[
1
]
;
op2
=
operands
[
2
]
;
gcc_assert
(
GET_CODE
(
op1
)
==
REG
&&
GET_CODE
(
op2
)
==
REG
)
;
if
(
code
==
GT
)
cmp_opstr
=
"qbgt"
;
else
if
(
code
==
GE
)
cmp_opstr
=
"qbge"
;
else
gcc_unreachable
(
)
;
if
(
is_near
)
bufi
=
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+12, %%1, %d\n\t"
"qbbs\t%%l3, %%2, %d\n\t"
"%s\t%%l3, %%2, %%1\n\t"
"qbbc\t.+8, %%2, %d\n\t"
"%s\t%%l3, %%2, %%1"
,
sign_bit_position
(
op1
)
,
sign_bit_position
(
op2
)
,
cmp_opstr
,
sign_bit_position
(
op2
)
,
cmp_opstr
)
;
else
bufi
=
snprintf
(
buf
,
sizeof
(
buf
)
,
"qbbs\t.+12, %%1, %d\n\t"
"qbbs\t.+20, %%2, %d\n\t"
"%s\t.+16, %%2, %%1\n\t"
"qbbc\t.+16, %%2, %d\n\t"
"%s\t.+8, %%2, %%1\n\t"
"jmp\t.+8\n\t"
"jmp\t%%%%label(%%l3)"
,
sign_bit_position
(
op1
)
,
sign_bit_position
(
op2
)
,
cmp_opstr
,
sign_bit_position
(
op2
)
,
cmp_opstr
)
;
gcc_assert
(
bufi
>
0
)
;
gcc_assert
(
(
unsigned
int
)
bufi
<
sizeof
(
buf
)
)
;
return
buf
;
}
</s>

Output asm code for a signed-compare GT/GE conditional branch .


<s> SUnit * SIScheduleBlock :: pickNode ( ) { SISchedCandidate TopCand ; for ( SUnit * SU : TopReadySUs ) { SISchedCandidate TryCand ; std :: vector < unsigned > pressure ; std :: vector < unsigned > MaxPressure ; TryCand . SU = SU ; TopRPTracker . getDownwardPressure ( SU -> getInstr ( ) , pressure , MaxPressure ) ; TryCand . SGPRUsage = pressure [ DAG -> getSGPRSetID ( ) ] ; TryCand . VGPRUsage = pressure [ DAG -> getVGPRSetID ( ) ] ; TryCand . IsLowLatency = DAG -> IsLowLatencySU [ SU -> NodeNum ] ; TryCand . LowLatencyOffset = DAG -> LowLatencyOffset [ SU -> NodeNum ] ; TryCand . HasLowLatencyNonWaitedParent = HasLowLatencyNonWaitedParent [ NodeNum2Index [ SU -> NodeNum ] ] ; tryCandidateTopDown ( TopCand , TryCand ) ; if ( TryCand . Reason != NoCand ) TopCand . setBest ( TryCand ) ; } return TopCand . SU ; } </s>

Pick the next node to schedule , or return NULL .


<s>
bool
LinuxAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
O
<<
"\n\n"
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
SwitchToSection
(
TAI
->
SectionForGlobal
(
F
)
)
;
EmitAlignment
(
3
,
F
)
;
switch
(
F
->
getLinkage
(
)
)
{
default
:
assert
(
0
&&
"Unknown linkage type!"
)
;
case
Function
::
PrivateLinkage
:
case
Function
::
InternalLinkage
:
break
;
case
Function
::
ExternalLinkage
:
O
<<
"\t.global\t"
<<
CurrentFnName
<<
"\n"
<<
"\t.type\t"
<<
CurrentFnName
<<
", @function\n"
;
break
;
case
Function
::
WeakAnyLinkage
:
case
Function
::
WeakODRLinkage
:
case
Function
::
LinkOnceAnyLinkage
:
case
Function
::
LinkOnceODRLinkage
:
O
<<
"\t.global\t"
<<
CurrentFnName
<<
"\n"
;
O
<<
"\t.weak_definition\t"
<<
CurrentFnName
<<
"\n"
;
break
;
}
O
<<
CurrentFnName
<<
":\n"
;
DW
->
BeginFunction
(
&
MF
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printMachineInstruction
(
II
)
;
}
}
O
<<
"\t.size\t"
<<
CurrentFnName
<<
",.-"
<<
CurrentFnName
<<
"\n"
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
DW
->
EndFunction
(
&
MF
)
;
return
false
;
}
</s>


<s> bool VLIWResourceModel :: isResourceAvailable ( SUnit * SU ) { if ( ! SU || ! SU -> getInstr ( ) ) return false ; switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : if ( ! ResourcesModel -> canReserveResources ( * SU -> getInstr ( ) ) ) return false ; case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } for ( unsigned i = 0 , e = Packet . size ( ) ; i != e ; ++ i ) { if ( Packet [ i ] -> Succs . size ( ) == 0 ) continue ; for ( SUnit :: const_succ_iterator I = Packet [ i ] -> Succs . begin ( ) , E = Packet [ i ] -> Succs . end ( ) ; I != E ; ++ I ) { if ( I -> isCtrl ( ) ) continue ; if ( I -> getSUnit ( ) == SU ) return false ; } } return true ; } </s>

Check if scheduling of this SU is possible in the current packet .


<s>
static
uint8_t
name
(
struct
InternalInstruction
*
insn
,
\
OperandType
type
,
\
uint8_t
index
,
\
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
if
(
insn
->
rexPrefix
&&
\
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_XMM512
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_XMM256
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM128
:
\
case
TYPE_XMM64
:
\
case
TYPE_XMM32
:
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK1
:
\
case
TYPE_VK8
:
\
case
TYPE_VK16
:
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
index
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
index
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> ARMBaseTargetMachine :: ARMBaseTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( CM ) , OL ) , TargetABI ( computeTargetABI ( TT , CPU , Options ) ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( isLittle ) { if ( Options . FloatABIType == FloatABI :: Default ) { if ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF || TargetTriple . getEnvironment ( ) == Triple :: EABIHF || TargetTriple . isOSWindows ( ) || TargetABI == ARMBaseTargetMachine :: ARM_ABI_AAPCS16 ) this -> Options . FloatABIType = FloatABI :: Hard ; else this -> Options . FloatABIType = FloatABI :: Soft ; } if ( Options . EABIVersion == EABI :: Default || Options . EABIVersion == EABI :: Unknown ) { if ( ( TargetTriple . getEnvironment ( ) == Triple :: GNUEABI || TargetTriple . getEnvironment ( ) == Triple :: GNUEABIHF || TargetTriple . getEnvironment ( ) == Triple :: MuslEABI || TargetTriple . getEnvironment ( ) == Triple :: MuslEABIHF ) && ! ( TargetTriple . isOSWindows ( ) || TargetTriple . isOSDarwin ( ) ) ) this -> Options . EABIVersion = EABI :: GNU ; else this -> Options . EABIVersion = EABI :: EABI5 ; } if ( TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = true ; } initAsmInfo ( ) ; } </s>


<s>
DecodeStatus
AMDGPUDisassembler
::
getInstruction
(
MCInst
&
MI
,
uint64_t
&
Size
,
ArrayRef
<
uint8_t
>
Bytes_
,
uint64_t
Address
,
raw_ostream
&
WS
,
raw_ostream
&
CS
)
const
{
CommentStream
=
&
CS
;
assert
(
AMDGPU
::
isVI
(
STI
)
&&
"Can disassemble only VI ISA."
)
;
const
unsigned
MaxInstBytesNum
=
(
std
::
min
)
(
(
size_t
)
8
,
Bytes_
.
size
(
)
)
;
Bytes
=
Bytes_
.
slice
(
0
,
MaxInstBytesNum
)
;
DecodeStatus
Res
=
MCDisassembler
::
Fail
;
do
{
if
(
Bytes
.
size
(
)
<
4
)
break
;
const
uint32_t
DW
=
eatB32
(
Bytes
)
;
Res
=
tryDecodeInst
(
DecoderTableVI32
,
MI
,
DW
,
Address
)
;
if
(
Res
)
break
;
Res
=
tryDecodeInst
(
DecoderTableAMDGPU32
,
MI
,
DW
,
Address
)
;
if
(
Res
)
break
;
if
(
Bytes
.
size
(
)
<
4
)
break
;
const
uint64_t
QW
=
(
(
uint64_t
)
eatB32
(
Bytes
)
<<
32
)
|
DW
;
Res
=
tryDecodeInst
(
DecoderTableVI64
,
MI
,
QW
,
Address
)
;
if
(
Res
)
break
;
Res
=
tryDecodeInst
(
DecoderTableAMDGPU64
,
MI
,
QW
,
Address
)
;
}
while
(
false
)
;
Size
=
Res
(
MaxInstBytesNum
Bytes
.
size
(
)
)
:
0
;
return
Res
;
}
</s>

Returns the disassembly of a single instruction .


<s>
static
void
arm_unwind_emit
(
FILE
*
out_file
,
rtx_insn
*
insn
)
{
rtx
note
,
pat
;
bool
handled_one
=
false
;
if
(
arm_except_unwind_info
(
&
global_options
)
!=
UI_TARGET
)
return
;
if
(
!
(
flag_unwind_tables
||
crtl
->
uses_eh_lsda
)
&&
(
TREE_NOTHROW
(
current_function_decl
)
||
crtl
->
all_throwers_are_sibcalls
)
)
return
;
if
(
NOTE_P
(
insn
)
||
!
RTX_FRAME_RELATED_P
(
insn
)
)
return
;
for
(
note
=
REG_NOTES
(
insn
)
;
note
;
note
=
XEXP
(
note
,
1
)
)
{
switch
(
REG_NOTE_KIND
(
note
)
)
{
case
REG_FRAME_RELATED_EXPR
:
pat
=
XEXP
(
note
,
0
)
;
goto
found
;
case
REG_CFA_REGISTER
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
{
pat
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pat
)
==
PARALLEL
)
pat
=
XVECEXP
(
pat
,
0
,
0
)
;
}
{
rtx
dest
,
src
;
unsigned
reg
;
src
=
SET_SRC
(
pat
)
;
dest
=
SET_DEST
(
pat
)
;
gcc_assert
(
src
==
stack_pointer_rtx
||
IS_PAC_REGNUM
(
REGNO
(
src
)
)
)
;
reg
=
REGNO
(
dest
)
;
if
(
IS_PAC_REGNUM
(
REGNO
(
src
)
)
)
arm_unwind_emit_set
(
out_file
,
PATTERN
(
insn
)
)
;
else
asm_fprintf
(
out_file
,
"\t.unwind_raw 0, 0x%x @ vsp = r%d\n"
,
reg
+
0x90
,
reg
)
;
}
handled_one
=
true
;
break
;
case
REG_CFA_DEF_CFA
:
case
REG_CFA_ADJUST_CFA
:
case
REG_CFA_RESTORE
:
return
;
case
REG_CFA_EXPRESSION
:
case
REG_CFA_OFFSET
:
gcc_unreachable
(
)
;
default
:
break
;
}
}
if
(
handled_one
)
return
;
pat
=
PATTERN
(
insn
)
;
found
:
switch
(
GET_CODE
(
pat
)
)
{
case
SET
:
arm_unwind_emit_set
(
out_file
,
pat
)
;
break
;
case
SEQUENCE
:
arm_unwind_emit_sequence
(
out_file
,
pat
)
;
break
;
default
:
abort
(
)
;
}
}
</s>

Emit unwind directives for the given insn .


"Branch-taken block should post-dominate first candidate"

"Error in code produced by branch coalescing"


<s> static bool aarch64_extr_rtx_p ( rtx x , rtx * res_op0 , rtx * res_op1 ) { rtx op0 , op1 ; scalar_int_mode mode ; if ( ! is_a < scalar_int_mode > ( GET_MODE ( x ) , & mode ) ) return false ; * res_op0 = NULL_RTX ; * res_op1 = NULL_RTX ; if ( GET_CODE ( x ) != IOR ) return false ; op0 = XEXP ( x , 0 ) ; op1 = XEXP ( x , 1 ) ; if ( ( GET_CODE ( op0 ) == ASHIFT && GET_CODE ( op1 ) == LSHIFTRT ) || ( GET_CODE ( op1 ) == ASHIFT && GET_CODE ( op0 ) == LSHIFTRT ) ) { if ( GET_CODE ( op1 ) == ASHIFT ) std :: swap ( op0 , op1 ) ; if ( ! CONST_INT_P ( XEXP ( op0 , 1 ) ) || ! CONST_INT_P ( XEXP ( op1 , 1 ) ) ) return false ; unsigned HOST_WIDE_INT shft_amnt_0 = UINTVAL ( XEXP ( op0 , 1 ) ) ; unsigned HOST_WIDE_INT shft_amnt_1 = UINTVAL ( XEXP ( op1 , 1 ) ) ; if ( shft_amnt_0 < GET_MODE_BITSIZE ( mode ) && shft_amnt_0 + shft_amnt_1 == GET_MODE_BITSIZE ( mode ) ) { * res_op0 = XEXP ( op0 , 0 ) ; * res_op1 = XEXP ( op1 , 0 ) ; return true ; } } return false ; } </s>

Return true iff X is an rtx that will match an extr instruction i.e . as described in the * extr < mode > 5_insn family of patterns . OP0 and OP1 will be set to the operands of the shifts involved on success and will be NULL_RTX otherwise .


<s> int arm_legitimate_address_outer_p ( machine_mode mode , rtx x , RTX_CODE outer , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; if ( use_ldrd && GET_CODE ( x ) == POST_MODIFY && REG_P ( addend ) ) return 0 ; return ( ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) && arm_legitimate_index_p ( mode , addend , outer , strict_p ) ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( ( CONST_INT_P ( xop1 ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && arm_legitimate_index_p ( mode , xop0 , outer , strict_p ) ) ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( arm_address_register_rtx_p ( xop0 , strict_p ) && arm_legitimate_index_p ( mode , xop1 , outer , strict_p ) ) ; } else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid ARM state address operand .


<s> static bool high_pressure ( machine_mode mode ) { if ( r0_life_regions >= R0_MAX_LIFE_REGIONS ) return true ; if ( mode == SFmode ) return ( CURR_REGMODE_PRESSURE ( SFmode ) > SFMODE_MAX_WEIGHT ) ; else return ( CURR_REGMODE_PRESSURE ( SImode ) > SIMODE_MAX_WEIGHT ) ; } </s>

Return true if the pressure is high for MODE .


<s> bool HexagonInstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { return false ; } </s>

Returns true if the first specified predicate subsumes the second , e.g .


<s>
bool
ARCFrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
DEBUG
(
dbgs
(
)
<<
"Spill callee saved registers: "
<<
MBB
.
getParent
(
)
->
getName
(
)
<<
"\n"
)
;
unsigned
Last
=
determineLastCalleeSave
(
CSI
)
;
if
(
UseSaveRestoreFunclet
&&
Last
>
ARC
::
R14
)
{
return
true
;
}
return
false
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .

ARC
ARC
"Spill callee saved registers: "
"\n"
ARC::R14


<s> void RISCVAsmPrinter :: emitEndOfAsmFile ( Module & M ) { RISCVTargetStreamer & RTS = static_cast < RISCVTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) RTS . finishAttributeSection ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> static bool rs6000_lra_p ( void ) { return TARGET_LRA ; } </s>

Return true if we use LRA instead of reload pass .


"JIT relocation model must be set to static or default!"

runOnMachineFunction - Emit the function body .


<s> void assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) override { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ; } </s>

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> StringRef getDesc ( ) const { return StringRef ( getName ( ) . data ( ) + alignTo ( namesz , ALIGN ) , descsz ) ; } </s>

Returns the target instruction descriptor of this MachineInstr .


<s> bool HexagonFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const HexagonMachineFunctionInfo * FuncInfo = MF . getInfo < HexagonMachineFunctionInfo > ( ) ; return ( MFI -> hasCalls ( ) || ( MFI -> getStackSize ( ) > 0 ) || FuncInfo -> hasClobberLR ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"Can only put epilog before 'retl' instruction!"


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> static void ix86_set_current_function ( tree fndecl ) { if ( fndecl == ix86_previous_fndecl ) return ; tree old_tree ; if ( ix86_previous_fndecl == NULL_TREE ) old_tree = target_option_current_node ; else if ( DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ) old_tree = DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ; else old_tree = target_option_default_node ; if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) ix86_reset_previous_fndecl ( ) ; return ; } tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) { cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } ix86_previous_fndecl = fndecl ; } </s>

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> bool Mips16DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! Subtarget . inMips16Mode ( ) ) return false ; return MipsDAGToDAGISel :: runOnMachineFunction ( MF ) ; } </s>


<s> static void sparc_va_start ( tree valist , rtx nextarg ) { nextarg = expand_builtin_saveregs ( ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>

Implement ` va_start ' for varargs and stdarg .


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override { MCFixupKind Kind = Fixup . getKind ( ) ; if ( Kind >= FirstLiteralRelocationKind ) return ; Value = adjustFixupValue ( Kind , Value ) ; if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Kind ) ; for ( unsigned i = 0 ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == support :: little ? i : ( NumBytes - 1 - i ) ; Data [ Offset + i ] |= uint8_t ( ( Value >> ( Idx * 8 ) ) & 0xff ) ; } } </s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


"attribute %<target%> argument not a string"

"invalid fpu for target attribute or pragma %qs"

"auto fpu selection not currently permitted here"

"invalid architecture for target attribute or pragma %qs"

"unknown target attribute or pragma %qs"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Nios2 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void s390_expand_cs_hqi ( machine_mode mode , rtx btarget , rtx vtarget , rtx mem , rtx cmp , rtx new_rtx , bool is_weak ) { struct alignment_context ac ; rtx cmpv , newv , val , cc , seq0 , seq1 , seq2 , seq3 ; rtx res = gen_reg_rtx ( SImode ) ; rtx_code_label * csloop = NULL , * csend = NULL ; gcc_assert ( MEM_P ( mem ) ) ; init_alignment_context ( & ac , mem , mode ) ; val = expand_simple_binop ( SImode , AND , ac . memsi , ac . modemaski , NULL_RTX , 1 , OPTAB_DIRECT ) ; cmpv = s390_two_part_insv ( & ac , & seq0 , & seq2 , mode , val , cmp ) ; newv = s390_two_part_insv ( & ac , & seq1 , & seq3 , mode , val , new_rtx ) ; if ( seq0 ) emit_insn ( seq0 ) ; if ( seq1 ) emit_insn ( seq1 ) ; if ( ! is_weak ) { emit_move_insn ( btarget , const1_rtx ) ; csloop = gen_label_rtx ( ) ; csend = gen_label_rtx ( ) ; emit_label ( csloop ) ; } emit_insn ( seq2 ) ; emit_insn ( seq3 ) ; cc = s390_emit_compare_and_swap ( EQ , res , ac . memsi , cmpv , newv , CCZ1mode ) ; if ( is_weak ) emit_insn ( gen_cstorecc4 ( btarget , cc , XEXP ( cc , 0 ) , XEXP ( cc , 1 ) ) ) ; else { rtx tmp ; s390_emit_jump ( csend , cc ) ; tmp = copy_to_reg ( val ) ; force_expand_binop ( SImode , and_optab , res , ac . modemaski , val , 1 , OPTAB_DIRECT ) ; cc = s390_emit_compare ( NE , val , tmp ) ; s390_emit_jump ( csloop , cc ) ; emit_move_insn ( btarget , const0_rtx ) ; emit_label ( csend ) ; } convert_move ( vtarget , expand_simple_binop ( SImode , LSHIFTRT , res , ac . shift , NULL_RTX , 1 , OPTAB_DIRECT ) , 1 ) ; } </s>

Expand an atomic compare and swap operation for HImode and QImode . MEM is the memory location , CMP the old value to compare MEM with and NEW the value to set if CMP == MEM . CMP is never in memory for compare_and_swap_cc because expand_bool_compare_and_swap puts it into a register for later compare .


<s> static bool ix86_pic_register_p ( rtx x ) { if ( GET_CODE ( x ) == VALUE && CSELIB_VAL_PTR ( x ) ) return ( pic_offset_table_rtx && rtx_equal_for_cselib_p ( x , pic_offset_table_rtx ) ) ; else if ( ! REG_P ( x ) ) return false ; else if ( pic_offset_table_rtx ) { if ( REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; if ( HARD_REGISTER_P ( x ) && ! HARD_REGISTER_P ( pic_offset_table_rtx ) && ORIGINAL_REGNO ( x ) == REGNO ( pic_offset_table_rtx ) ) return true ; return false ; } else return REGNO ( x ) == PIC_OFFSET_TABLE_REGNUM ; } </s>

Return true if X is a representation of the PIC register . This copes with calls from ix86_find_base_term , where the register might have been replaced by a cselib value .


<s> unsigned getSize ( ) { return CurType . Size ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> bool AArch64TargetLowering :: shouldSinkOperands ( Instruction * I , SmallVectorImpl < Use * > & Ops ) const { if ( ! I -> getType ( ) -> isVectorTy ( ) ) return false ; if ( IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case Intrinsic :: aarch64_neon_umull : if ( ! areExtractShuffleVectors ( II -> getOperand ( 0 ) , II -> getOperand ( 1 ) ) ) return false ; Ops . push_back ( & II -> getOperandUse ( 0 ) ) ; Ops . push_back ( & II -> getOperandUse ( 1 ) ) ; return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( 0 ) , I -> getOperand ( 1 ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( 0 ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( 1 ) ) ; if ( areExtractShuffleVectors ( Ext1 , Ext2 ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( 0 ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( 0 ) ) ; } Ops . push_back ( & I -> getOperandUse ( 0 ) ) ; Ops . push_back ( & I -> getOperandUse ( 1 ) ) ; return true ; } default : return false ; } return false ; } </s>

Return true if sinking I 's operands to the same basic block as I is profitable , e.g .


<s> static rtx rs6000_function_value ( const_tree valtype , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode ; unsigned int regno ; machine_mode elt_mode ; int n_elts ; if ( TARGET_MACHO && rs6000_darwin64_struct_check_p ( TYPE_MODE ( valtype ) , valtype ) ) { CUMULATIVE_ARGS valcum ; rtx valret ; valcum . words = 0 ; valcum . fregno = FP_ARG_MIN_REG ; valcum . vregno = ALTIVEC_ARG_MIN_REG ; valret = rs6000_darwin64_record_arg ( & valcum , valtype , true , true ) ; if ( valret ) return valret ; } mode = TYPE_MODE ( valtype ) ; if ( rs6000_discover_homogeneous_aggregate ( mode , valtype , & elt_mode , & n_elts ) ) { int first_reg , n_regs ; if ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( elt_mode ) ) { first_reg = ( elt_mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; n_regs = ( GET_MODE_SIZE ( elt_mode ) + 7 ) >> 3 ; } else { first_reg = ALTIVEC_ARG_RETURN ; n_regs = 1 ; } return rs6000_parallel_return ( mode , n_elts , elt_mode , first_reg , n_regs ) ; } if ( TARGET_32BIT && TARGET_POWERPC64 ) switch ( mode ) { default : break ; case E_DImode : case E_SCmode : case E_DCmode : case E_TCmode : int count = GET_MODE_SIZE ( mode ) / 4 ; return rs6000_parallel_return ( mode , count , SImode , GP_ARG_RETURN , 1 ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && GET_MODE_BITSIZE ( mode ) < ( TARGET_32BIT ? 32 : 64 ) ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ; if ( DECIMAL_FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT ) regno = ( mode == TDmode ) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN ; else if ( SCALAR_FLOAT_TYPE_P ( valtype ) && TARGET_HARD_FLOAT && ! FLOAT128_VECTOR_P ( mode ) && ( ( TARGET_SINGLE_FLOAT && ( mode == SFmode ) ) || TARGET_DOUBLE_FLOAT ) ) regno = FP_ARG_RETURN ; else if ( TREE_CODE ( valtype ) == COMPLEX_TYPE && targetm . calls . split_complex_arg ) return rs6000_complex_function_value ( mode ) ; else if ( ( TREE_CODE ( valtype ) == VECTOR_TYPE || FLOAT128_VECTOR_P ( mode ) ) && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI && ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) regno = ALTIVEC_ARG_RETURN ; else regno = GP_ARG_RETURN ; return gen_rtx_REG ( mode , regno ) ; } </s>

Define how to find the value returned by a function . VALTYPE is the data type of the value ( as a tree ) . If the precise function being called is known , FUNC is its FUNCTION_DECL ; otherwise , FUNC is 0 . On the SPE , both FPs and vectors are returned in r3 . On RS/6000 an integer value is in r3 and a floating-point value is in fp1 , unless -msoft-float .


<s> bool hasStandaloneRem ( EVT VT ) const override { return HasStandaloneRem ; } </s>

Return true if the target can handle a standalone remainder operation .


<s> void ScheduleDAGPostRA :: moveInstruction ( MachineInstr * MI , MachineBasicBlock :: iterator InsertPos ) { if ( & * RegionBegin == MI ) ++ RegionBegin ; bool InsideBundle = MI -> isBundledWithPred ( ) && MI -> isBundledWithSucc ( ) ; MachineInstr * PrevMI = InsideBundle ? MI -> getPrevNode ( ) : NULL ; if ( ! InsideBundle && ( ( MI -> isBundledWithPred ( ) && ! MI -> getPrevNode ( ) -> isBundledWithPred ( ) ) || ( MI -> isBundledWithSucc ( ) && ! MI -> getNextNode ( ) -> isBundledWithSucc ( ) ) ) ) { NumBundled -- ; NumNotBundled ++ ; } if ( MI -> isBundledWithPred ( ) ) MI -> unbundleFromPred ( ) ; if ( MI -> isBundledWithSucc ( ) ) MI -> unbundleFromSucc ( ) ; BB -> splice ( InsertPos , BB , MI ) ; if ( InsideBundle ) { PrevMI -> bundleWithSucc ( ) ; } if ( RegionBegin == InsertPos ) RegionBegin = MI ; } </s>

Change the position of an instruction within the basic block and update live ranges and region boundary iterators .


<s> bool SystemZInstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumCyclesT , unsigned ExtraPredCyclesT , MachineBasicBlock & FMBB , unsigned NumCyclesF , unsigned ExtraPredCyclesF , const BranchProbability & Probability ) const { return false ; } </s>


<s> AArch64TargetLowering :: ConstraintType AArch64TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'x' : case 'w' : case 'y' : return C_RegisterClass ; case 'Q' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'Y' : case 'Z' : return C_Immediate ; case 'z' : case 'S' : return C_Other ; } } else if ( parsePredicateConstraint ( Constraint ) != PredicateConstraint :: Invalid ) return C_RegisterClass ; return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


"Can only put epilog before 'retl' instruction!"


<s>
const
char
*
getPassName
(
)
const
override
{
return
"ARM64 Assembly Printer"
;
}
</s>


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BR_JT : return lowerBR_JT ( Op , DAG ) ; case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return lowerConstantPool ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return lowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return lowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return lowerVASTART ( Op , DAG ) ; case ISD :: VAARG : return lowerVAARG ( Op , DAG ) ; case ISD :: FCOPYSIGN : return lowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FRAMEADDR : return lowerFRAMEADDR ( Op , DAG ) ; case ISD :: RETURNADDR : return lowerRETURNADDR ( Op , DAG ) ; case ISD :: EH_RETURN : return lowerEH_RETURN ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return lowerATOMIC_FENCE ( Op , DAG ) ; case ISD :: SHL_PARTS : return lowerShiftLeftParts ( Op , DAG ) ; case ISD :: SRA_PARTS : return lowerShiftRightParts ( Op , DAG , true ) ; case ISD :: SRL_PARTS : return lowerShiftRightParts ( Op , DAG , false ) ; case ISD :: LOAD : return lowerLOAD ( Op , DAG ) ; case ISD :: STORE : return lowerSTORE ( Op , DAG ) ; case ISD :: ADD : return lowerADD ( Op , DAG ) ; case ISD :: FP_TO_SINT : return lowerFP_TO_SINT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BR_JT ISD::BRCOND ISD::ConstantPool ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SETCC ISD::VASTART ISD::VAARG ISD::FCOPYSIGN ISD::FRAMEADDR ISD::RETURNADDR ISD::EH_RETURN ISD::ATOMIC_FENCE ISD::SHL_PARTS ISD::SRA_PARTS ISD::SRL_PARTS ISD::LOAD ISD::STORE ISD::ADD ISD::FP_TO_SINT


<s>
unsigned
SIInstrInfo
::
getInstSizeInBytes
(
const
MachineInstr
&
MI
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
getMCOpcodeFromPseudo
(
Opc
)
;
unsigned
DescSize
=
Desc
.
getSize
(
)
;
if
(
DescSize
!=
0
&&
DescSize
!=
4
)
return
DescSize
;
if
(
isVALU
(
MI
)
||
isSALU
(
MI
)
)
{
if
(
isFixedSize
(
MI
)
)
return
DescSize
;
int
Src0Idx
=
AMDGPU
::
getNamedOperandIdx
(
Opc
,
AMDGPU
::
OpName
::
src0
)
;
if
(
Src0Idx
==
1
)
return
4
;
if
(
isLiteralConstantLike
(
MI
.
getOperand
(
Src0Idx
)
,
Desc
.
OpInfo
[
Src0Idx
]
)
)
return
8
;
int
Src1Idx
=
AMDGPU
::
getNamedOperandIdx
(
Opc
,
AMDGPU
::
OpName
::
src1
)
;
if
(
Src1Idx
==
1
)
return
4
;
if
(
isLiteralConstantLike
(
MI
.
getOperand
(
Src1Idx
)
,
Desc
.
OpInfo
[
Src1Idx
]
)
)
return
8
;
return
4
;
}
if
(
DescSize
==
4
)
return
4
;
switch
(
Opc
)
{
case
TargetOpcode
::
IMPLICIT_DEF
:
case
TargetOpcode
::
KILL
:
case
TargetOpcode
::
DBG_VALUE
:
case
TargetOpcode
::
EH_LABEL
:
return
0
;
case
TargetOpcode
::
BUNDLE
:
return
getInstBundleSize
(
MI
)
;
case
TargetOpcode
::
INLINEASM
:
{
const
MachineFunction
*
MF
=
MI
.
getParent
(
)
->
getParent
(
)
;
const
char
*
AsmStr
=
MI
.
getOperand
(
0
)
.
getSymbolName
(
)
;
return
getInlineAsmLength
(
AsmStr
,
*
MF
->
getTarget
(
)
.
getMCAsmInfo
(
)
)
;
}
default
:
llvm_unreachable
(
"unable to find instruction size"
)
;
}
}
</s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> void PPCLinuxAsmPrinter :: emitStartOfAsmFile ( Module & M ) { if ( static_cast < const PPCTargetMachine & > ( TM ) . isELFv2ABI ( ) ) { PPCTargetStreamer * TS = static_cast < PPCTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; if ( TS ) TS -> emitAbiVersion ( 2 ) ; } if ( static_cast < const PPCTargetMachine & > ( TM ) . isPPC64 ( ) || ! isPositionIndependent ( ) ) return AsmPrinter :: emitStartOfAsmFile ( M ) ; if ( M . getPICLevel ( ) == PICLevel :: SmallPIC ) return AsmPrinter :: emitStartOfAsmFile ( M ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( ".got2" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ) ; MCSymbol * TOCSym = OutContext . getOrCreateSymbol ( Twine ( ".LTOC" ) ) ; MCSymbol * CurrentPos = OutContext . createTempSymbol ( ) ; OutStreamer -> emitLabel ( CurrentPos ) ; const MCExpr * tocExpr = MCBinaryExpr :: createAdd ( MCSymbolRefExpr :: create ( CurrentPos , OutContext ) , MCConstantExpr :: create ( 0x8000 , OutContext ) , OutContext ) ; OutStreamer -> emitAssignment ( TOCSym , tocExpr ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


"\nRelevant insns with their flag settings\n\n"


" is return block without RETURN instr\n"

Convenience function that returns true if the block ends in a return instruction .


<s> static void rs6000_emit_epilogue_components ( sbitmap components ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; rtx ptr_reg = gen_rtx_REG ( Pmode , frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ) ; int reg_size = TARGET_32BIT ? 4 : 8 ; int offset = info -> gp_save_offset ; if ( info -> push_p ) offset += info -> total_size ; for ( int i = info -> first_gp_reg_save ; i < 32 ; i ++ ) { if ( bitmap_bit_p ( components , i ) ) { rtx reg = gen_rtx_REG ( Pmode , i ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } offset += reg_size ; } if ( bitmap_bit_p ( components , 0 ) ) { int offset = info -> lr_save_offset ; if ( info -> push_p ) offset += info -> total_size ; rtx reg = gen_rtx_REG ( Pmode , 0 ) ; rtx_insn * insn = emit_insn ( gen_frame_load ( reg , ptr_reg , offset ) ) ; rtx lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( lr , reg ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; add_reg_note ( insn , REG_CFA_RESTORE , lr ) ; } } </s>


<s> TargetLowering :: ConstraintWeight SparcTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( isInt < 13 > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; } break ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> static int riscv_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type , bool named ) { struct riscv_arg_info arg ; riscv_get_arg_info ( & arg , get_cumulative_args ( cum ) , mode , type , named , false ) ; return arg . stack_p ? arg . num_gprs * UNITS_PER_WORD : 0 ; } </s>


<s> bool RISCVAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( Fixup . getKind ( ) >= FirstLiteralRelocationKind ) return true ; switch ( Fixup . getTargetKind ( ) ) { default : break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : if ( Target . isAbsolute ( ) ) return false ; break ; case RISCV :: fixup_riscv_got_hi20 : case RISCV :: fixup_riscv_tls_got_hi20 : case RISCV :: fixup_riscv_tls_gd_hi20 : return true ; } return STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] || ForceRelocs ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> bool AMDGPUUnifyMetadata :: runOnFunction ( Function & F ) { return runOnModule ( * F . getParent ( ) ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void AGCFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> void NVPTXFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"Entry block with non-zero block Number."

Returns true if this is the entry block of the function .


<s> const XCoreInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


The guts of ix86_expand_vec_perm_const , also used by the ok hook . With all of the interface bits taken care of , perform the expansion in D and return true on success .


<s> MVT RISCVTargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == MVT :: f16 && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfh ( ) ) return MVT :: f32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> bool MipsTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseGV ) return false ; switch ( AM . Scale ) { case 0 : break ; case 1 : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> rtx legitimize_tls_address ( rtx x , rtx reg ) { rtx dest , tp , label , labelno , sum , insns , ret , eqv , addend ; unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; } return dest ; case TLS_MODEL_LOCAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? 8 : 4 ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX ) ; reg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ; reg = force_reg ( SImode , gen_rtx_CONST ( SImode , reg ) ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; default : abort ( ) ; } } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> int ft32_is_mem_pm ( rtx o ) { return ( MEM_P ( o ) && ! ADDR_SPACE_GENERIC_P ( MEM_ADDR_SPACE ( o ) ) ) ; } </s>

Used by constraints.md to distinguish between GENERIC and PM memory addresses .


"Don't know how to lower this operation."


<s>
bool
SIInstrInfo
::
isInlineConstant
(
const
MachineOperand
&
MO
,
uint8_t
OperandType
)
const
{
if
(
!
MO
.
isImm
(
)
||
OperandType
<
AMDGPU
::
OPERAND_SRC_FIRST
||
OperandType
>
AMDGPU
::
OPERAND_SRC_LAST
)
return
false
;
int64_t
Imm
=
MO
.
getImm
(
)
;
switch
(
OperandType
)
{
case
AMDGPU
::
OPERAND_REG_IMM_INT32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32
:
case
AMDGPU
::
OPERAND_REG_IMM_FP32_DEFERRED
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP32
:
case
AMDGPU
::
OPERAND_REG_IMM_V2FP32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP32
:
case
AMDGPU
::
OPERAND_REG_IMM_V2INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_INT32
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP32
:
{
int32_t
Trunc
=
static_cast
<
int32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteral32
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_REG_IMM_INT64
:
case
AMDGPU
::
OPERAND_REG_IMM_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT64
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP64
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP64
:
return
AMDGPU
::
isInlinableLiteral64
(
MO
.
getImm
(
)
,
ST
.
hasInv2PiInlineImm
(
)
)
;
case
AMDGPU
::
OPERAND_REG_IMM_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_INT16
:
return
AMDGPU
::
isInlinableIntLiteral
(
Imm
)
;
case
AMDGPU
::
OPERAND_REG_IMM_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2INT16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_V2INT16
:
return
AMDGPU
::
isInlinableIntLiteralV216
(
Imm
)
;
case
AMDGPU
::
OPERAND_REG_IMM_FP16
:
case
AMDGPU
::
OPERAND_REG_IMM_FP16_DEFERRED
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_FP16
:
{
if
(
isInt
<
16
>
(
Imm
)
||
isUInt
<
16
>
(
Imm
)
)
{
int16_t
Trunc
=
static_cast
<
int16_t
>
(
Imm
)
;
return
ST
.
has16BitInsts
(
)
&&
AMDGPU
::
isInlinableLiteral16
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
return
false
;
}
case
AMDGPU
::
OPERAND_REG_IMM_V2FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_C_V2FP16
:
case
AMDGPU
::
OPERAND_REG_INLINE_AC_V2FP16
:
{
uint32_t
Trunc
=
static_cast
<
uint32_t
>
(
Imm
)
;
return
AMDGPU
::
isInlinableLiteralV216
(
Trunc
,
ST
.
hasInv2PiInlineImm
(
)
)
;
}
case
AMDGPU
::
OPERAND_KIMM32
:
case
AMDGPU
::
OPERAND_KIMM16
:
return
false
;
default
:
llvm_unreachable
(
"invalid bitwidth"
)
;
}
}
</s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> TargetTransformInfo ARMBaseTargetMachine :: getTargetTransformInfo ( const Function & F ) const { return TargetTransformInfo ( ARMTTIImpl ( this , F ) ) ; } </s>

Get a TargetTransformInfo implementation for the target .


<s>
void
assignValueToReg
(
Register
ValVReg
,
Register
PhysReg
,
CCValAssign
&
VA
)
override
{
assert
(
VA
.
isRegLoc
(
)
&&
"Value shouldn't be assigned to reg"
)
;
assert
(
VA
.
getLocReg
(
)
==
PhysReg
&&
"Assigning to the wrong reg?"
)
;
uint64_t
ValSize
=
VA
.
getValVT
(
)
.
getFixedSizeInBits
(
)
;
uint64_t
LocSize
=
VA
.
getLocVT
(
)
.
getFixedSizeInBits
(
)
;
assert
(
ValSize
<=
64
&&
"Unsupported value size"
)
;
assert
(
LocSize
<=
64
&&
"Unsupported location size"
)
;
markPhysRegUsed
(
PhysReg
)
;
if
(
ValSize
==
LocSize
)
{
MIRBuilder
.
buildCopy
(
ValVReg
,
PhysReg
)
;
}
else
{
assert
(
ValSize
<
LocSize
&&
"Extensions not supported"
)
;
auto
PhysRegToVReg
=
MIRBuilder
.
buildCopy
(
LLT
::
scalar
(
LocSize
)
,
PhysReg
)
;
MIRBuilder
.
buildTrunc
(
ValVReg
,
PhysRegToVReg
)
;
}
}
</s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .

ARM
"Value shouldn't be assigned to reg"
"Assigning to the wrong reg?"
64
"Unsupported value size"
64
"Unsupported location size"
"Extensions not supported"


<s> unsigned CJGRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return CJG :: SP ; } </s>


<s> void xstormy16_expand_call ( rtx retval , rtx dest , rtx counter ) { rtx call , temp ; machine_mode mode ; gcc_assert ( MEM_P ( dest ) ) ; dest = XEXP ( dest , 0 ) ; if ( ! CONSTANT_P ( dest ) && ! REG_P ( dest ) ) dest = force_reg ( Pmode , dest ) ; if ( retval == NULL ) mode = VOIDmode ; else mode = GET_MODE ( retval ) ; call = gen_rtx_CALL ( mode , gen_rtx_MEM ( FUNCTION_MODE , dest ) , counter ) ; if ( retval ) call = gen_rtx_SET ( VOIDmode , retval , call ) ; if ( ! CONSTANT_P ( dest ) ) { temp = gen_reg_rtx ( HImode ) ; emit_move_insn ( temp , const0_rtx ) ; } else temp = const0_rtx ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , call , gen_rtx_USE ( VOIDmode , temp ) ) ) ; emit_call_insn ( call ) ; } </s>

Expander for the ` call ' patterns . INDEX is the index of the switch statement . LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding to the first table entry . RANGE is the number of table entries . TABLE is an ADDR_VEC that is the jump table . DEFAULT_LABEL is the address to branch to if INDEX is outside the range LOWER_BOUND to LOWER_BOUND+RANGE-1 .