<s> bool SystemZShortenInst :: runOnMachineFunction ( MachineFunction & F ) { if ( skipFunction ( F . getFunction ( ) ) ) return false ; const SystemZSubtarget & ST = F . getSubtarget < SystemZSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LiveRegs . init ( * TRI ) ; bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ; } </s>


<s> MVT getScalarShiftAmountTy ( EVT LHSTy ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool MSP430RegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( NoFramePointerElim || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool isDef ( long pos ) const { return defs . test ( pos ) ; } </s>

Tests if this MemDepResult represents a query that is an instruction definition dependency .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AArch64 :: SP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) { Reserved . set ( AArch64 :: FP ) ; Reserved . set ( AArch64 :: W29 ) ; } if ( STI -> isTargetDarwin ( ) || ReserveX18 ) { Reserved . set ( AArch64 :: X18 ) ; Reserved . set ( AArch64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( AArch64 :: X19 ) ; Reserved . set ( AArch64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> DecodeStatus MSP430Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { if ( Bytes . size ( ) < 2 ) { Size = 0 ; return MCDisassembler :: Fail ; } uint64_t Insn = support :: endian :: read16le ( Bytes . data ( ) ) ; unsigned Opc = fieldFromInstruction ( Insn , 13 , 3 ) ; switch ( Opc ) { case 0 : return getInstructionII ( MI , Size , Bytes , Address , CStream ) ; case 1 : return getInstructionCJ ( MI , Size , Bytes , Address , CStream ) ; default : return getInstructionI ( MI , Size , Bytes , Address , CStream ) ; } } </s>

Returns the disassembly of a single instruction .


<s> void ARMPassConfig :: addPreEmitPass2 ( ) { addPass ( createARMConstantIslandPass ( ) ) ; addPass ( createARMLowOverheadLoopsPass ( ) ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) { addPass ( createCFGuardLongjmpPass ( ) ) ; addPass ( createEHContGuardCatchretPass ( ) ) ; } } </s>

Targets may add passes immediately before machine code is emitted in this callback .


<s> static void arm_emit_ldrd_pop ( unsigned long saved_regs_mask ) { int j = 0 ; int offset = 0 ; rtx par = NULL_RTX ; rtx dwarf = NULL_RTX ; rtx tmp , mem ; gcc_assert ( ! ( ( saved_regs_mask & ( 1 << SP_REGNUM ) ) ) ) ; j = 0 ; while ( j <= LAST_ARM_REGNUM ) if ( saved_regs_mask & ( 1 << j ) ) { if ( ( j % 2 ) == 0 && ( saved_regs_mask & ( 1 << ( j + 1 ) ) ) && ( j + 1 ) != PC_REGNUM ) { if ( offset > 0 ) mem = gen_frame_mem ( DImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( DImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( gen_rtx_REG ( DImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j + 1 ) , dwarf ) ; REG_NOTES ( tmp ) = dwarf ; offset += 8 ; j += 2 ; } else if ( j != PC_REGNUM ) { if ( offset > 0 ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( gen_rtx_REG ( SImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; offset += 4 ; j += 1 ; } else j ++ ; } else j ++ ; if ( offset > 0 ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; tmp = emit_insn ( tmp ) ; arm_add_cfa_adjust_cfa_note ( tmp , offset , stack_pointer_rtx , stack_pointer_rtx ) ; offset = 0 ; } if ( saved_regs_mask & ( 1 << PC_REGNUM ) ) { par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; tmp = gen_rtx_SET ( gen_rtx_REG ( SImode , PC_REGNUM ) , gen_frame_mem ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 1 ) = tmp ; par = emit_jump_insn ( par ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , PC_REGNUM ) , NULL_RTX ) ; REG_NOTES ( par ) = dwarf ; arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD , stack_pointer_rtx , stack_pointer_rtx ) ; } } </s>

LDRD in ARM mode needs consecutive registers as operands . This function emits LDRD whenever possible , otherwise it emits single-word loads . It uses offset addressing and then generates one separate stack udpate . This provides more scheduling freedom , compared to writeback on every load . However , if the function returns using load into PC directly ( i.e. , if PC is in SAVED_REGS_MASK ) , the stack needs to be updated before the last load . TODO : Add a peephole optimization to recognize the new epilogue sequence as an LDM instruction whenever possible . TODO : Add peephole optimization to merge the load at stack-offset zero with the stack update instruction using load with writeback in post-index addressing mode .


<s> bool HexagonAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , OS ) ; case 'c' : printOperand ( MI , OpNo , OS ) ; return false ; case 'L' : case 'H' : { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; unsigned RegNumber = MO . getReg ( ) ; if ( Hexagon :: DoubleRegsRegClass . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ 0 ] == 'L' ? Hexagon :: isub_lo : Hexagon :: isub_hi ) ; OS << HexagonInstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << "i" ; return false ; } } printOperand ( MI , OpNo , OS ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> int arc_ccfsm_branch_deleted_p ( ) { if ( arc_ccfsm_state == 1 || arc_ccfsm_state == 2 ) return 1 ; return 0 ; } </s>

See if the current insn , which is a conditional branch , is to be deleted .


<s> bool X86TargetLowering :: isTruncateFree ( MVT VT1 , MVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; if ( NumBits1 <= NumBits2 ) return false ; return Subtarget -> is64Bit ( ) || NumBits1 < 64 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


"setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n"

Worker function for TARGET_SETUP_INCOMING_VARARGS .


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override { return createAArch64WinCOFFObjectWriter ( OS ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> static bool ix86_save_reg ( unsigned int regno , bool maybe_eh_return ) { if ( regno == REAL_PIC_OFFSET_TABLE_REGNUM && pic_offset_table_rtx ) { if ( ix86_use_pseudo_pic_reg ( ) ) { if ( ! TARGET_64BIT && flag_pic && crtl -> profile ) return true ; } else if ( df_regs_ever_live_p ( REAL_PIC_OFFSET_TABLE_REGNUM ) || crtl -> profile || crtl -> calls_eh_return || crtl -> uses_const_pool || cfun -> has_nonlocal_label ) return ix86_select_alt_pic_regnum ( ) == INVALID_REGNUM ; } if ( crtl -> calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = 0 ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return true ; } } if ( crtl -> drap_reg && regno == REGNO ( crtl -> drap_reg ) && ! cfun -> machine -> no_drap_save_restore ) return true ; return ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] && ! fixed_regs [ regno ] && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } </s>


<s> bool arc_split_mov_const ( rtx * operands ) { unsigned HOST_WIDE_INT ival ; HOST_WIDE_INT shimm ; machine_mode mode = GET_MODE ( operands [ 0 ] ) ; gcc_assert ( CONST_INT_P ( operands [ 1 ] ) ) ; ival = INTVAL ( operands [ 1 ] ) & 0xffffffff ; if ( TARGET_BARREL_SHIFTER && TARGET_V2 && ( ( ival & ~ 0x3f000000 ) == 0 ) ) { shimm = ( ival >> 24 ) & 0x3f ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_ROTATERT ( mode , GEN_INT ( shimm ) , GEN_INT ( 8 ) ) ) ) ; return true ; } if ( TARGET_BARREL_SHIFTER && TARGET_V2 && ( ( ival & ~ 0x3f00 ) == 0 ) ) { shimm = ( ival >> 8 ) & 0x3f ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_ASHIFT ( mode , GEN_INT ( shimm ) , GEN_INT ( 8 ) ) ) ) ; return true ; } if ( TARGET_BARREL_SHIFTER && TARGET_V2 && ( ( ival & ~ 0x3f0000 ) == 0 ) ) { shimm = ( ival >> 16 ) & 0x3f ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_ASHIFT ( mode , GEN_INT ( shimm ) , GEN_INT ( 16 ) ) ) ) ; return true ; } if ( ( ( ival >> ( __builtin_ffs ( ival ) - 1 ) ) & 0xffffff00 ) == 0 && TARGET_BARREL_SHIFTER ) { HOST_WIDE_INT shift = __builtin_ffs ( ival ) ; shimm = ( ival >> ( shift - 1 ) ) & 0xff ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , GEN_INT ( shimm ) ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_ASHIFT ( mode , operands [ 0 ] , GEN_INT ( shift - 1 ) ) ) ) ; return true ; } if ( ( ival & ~ 0x8000001f ) == 0 ) { shimm = ( ival * 2 + 1 ) & 0x3f ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_ROTATERT ( mode , GEN_INT ( shimm ) , const1_rtx ) ) ) ; return true ; } if ( IS_POWEROF2_P ( ival + 1 ) ) { emit_insn ( gen_rtx_SET ( operands [ 0 ] , constm1_rtx ) ) ; emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_AND ( mode , operands [ 0 ] , GEN_INT ( ival ) ) ) ) ; return true ; } gcc_unreachable ( ) ; } </s>

Split a mov with long immediate instruction into smaller , size friendly instructions .


<s> bool SIWholeQuadMode :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getFunction ( ) -> getCallingConv ( ) != CallingConv :: AMDGPU_PS ) return false ; Instructions . clear ( ) ; Blocks . clear ( ) ; ExecExports . clear ( ) ; LiveMaskQueries . clear ( ) ; const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; char GlobalFlags = analyzeFunction ( MF ) ; if ( ! ( GlobalFlags & StateWQM ) ) { lowerLiveMaskQueries ( AMDGPU :: EXEC ) ; return ! LiveMaskQueries . empty ( ) ; } unsigned LiveMaskReg = 0 ; { MachineBasicBlock & Entry = MF . front ( ) ; MachineBasicBlock :: iterator EntryMI = Entry . getFirstNonPHI ( ) ; if ( GlobalFlags & StateExact || ! LiveMaskQueries . empty ( ) ) { LiveMaskReg = MRI -> createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: COPY ) , LiveMaskReg ) . addReg ( AMDGPU :: EXEC ) ; } if ( GlobalFlags == StateWQM ) { BuildMI ( Entry , EntryMI , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; lowerLiveMaskQueries ( LiveMaskReg ) ; return true ; } } lowerLiveMaskQueries ( LiveMaskReg ) ; for ( const auto & BII : Blocks ) processBlock ( const_cast < MachineBasicBlock & > ( * BII . first ) , LiveMaskReg , BII . first == & * MF . begin ( ) ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI AMDGPU SI SI AMDGPU::EXEC 0 AMDGPU::SReg_64RegClass AMDGPU::COPY AMDGPU::EXEC AMDGPU::S_WQM_B64 AMDGPU::EXEC AMDGPU::EXEC


<s> static bool s390_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { int size = s390_function_arg_size ( arg . mode , arg . type ) ; if ( s390_function_arg_vector ( arg . mode , arg . type ) ) return false ; if ( size > 8 ) return true ; if ( tree type = arg . type ) { if ( AGGREGATE_TYPE_P ( type ) && exact_log2 ( size ) < 0 ) return true ; if ( TREE_CODE ( type ) == COMPLEX_TYPE || TREE_CODE ( type ) == VECTOR_TYPE ) return true ; } return false ; } </s>

Return 1 if a function argument of type TYPE and mode MODE is to be passed by reference . The ABI specifies that only structures of size 1 , 2 , 4 , or 8 bytes are passed by value , all other structures ( and complex numbers ) are passed by reference .


<s> void PPCSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , unsigned NumRegionInstrs ) const { if ( needsAggressiveScheduling ( DarwinDirective ) ) { Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; } Policy . ShouldTrackPressure = true ; } </s>

Override generic scheduling policy within a region .


<s> bool toc_relative_expr_p ( const_rtx op , bool strict , const_rtx * tocrel_base_ret , const_rtx * tocrel_offset_ret ) { if ( ! TARGET_TOC ) return false ; if ( TARGET_CMODEL != CMODEL_SMALL ) { if ( strict && ! ( GET_CODE ( op ) == LO_SUM && REG_P ( XEXP ( op , 0 ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( op , 0 ) , strict ) ) ) return false ; if ( GET_CODE ( op ) == LO_SUM ) op = XEXP ( op , 1 ) ; } const_rtx tocrel_base = op ; const_rtx tocrel_offset = const0_rtx ; if ( GET_CODE ( op ) == PLUS && add_cint_operand ( XEXP ( op , 1 ) , GET_MODE ( op ) ) ) { tocrel_base = XEXP ( op , 0 ) ; tocrel_offset = XEXP ( op , 1 ) ; } if ( tocrel_base_ret ) * tocrel_base_ret = tocrel_base ; if ( tocrel_offset_ret ) * tocrel_offset_ret = tocrel_offset ; return ( GET_CODE ( tocrel_base ) == UNSPEC && XINT ( tocrel_base , 1 ) == UNSPEC_TOCREL && REG_P ( XVECEXP ( tocrel_base , 0 , 1 ) ) && REGNO ( XVECEXP ( tocrel_base , 0 , 1 ) ) == TOC_REGISTER ) ; } </s>

Return true if OP is a toc pointer relative address ( the output of create_TOC_reference ) . If STRICT , do not match high part or non-split -mcmodel=large/medium toc pointer relative addresses .


Return an appropriate const instance of xlogue_layout based upon values in cfun- > machine and crtl .


<s> EVT R600TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> static void allocateSpecialInputVGPRs ( CCState & CCInfo , MachineFunction & MF , const SIRegisterInfo & TRI , SIMachineFunctionInfo & Info ) { if ( Info . hasWorkItemIDX ( ) ) Info . setWorkItemIDX ( allocateVGPR32Input ( CCInfo ) ) ; if ( Info . hasWorkItemIDY ( ) ) Info . setWorkItemIDY ( allocateVGPR32Input ( CCInfo ) ) ; if ( Info . hasWorkItemIDZ ( ) ) Info . setWorkItemIDZ ( allocateVGPR32Input ( CCInfo ) ) ; } </s>

Allocate implicit function VGPR arguments at the end of allocated user arguments .


<s> static bool isNodeHidden ( const SCANode * N , const SpillCostAnalysisGraph G ) { return ! N -> isVisible ( ) ; } </s>

Do not print nodes that are part of a pi-block separately .


<s> EVT PPCTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & C , EVT VT ) const { if ( ! VT . isVector ( ) ) return Subtarget . useCRBits ( ) ? MVT :: i1 : MVT :: i32 ; if ( Subtarget . hasQPX ( ) ) return EVT :: getVectorVT ( C , MVT :: i1 , VT . getVectorNumElements ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>


"  Copied r%d to a vector register r%d for insn %d\n"

Make vector copies for all register REGNO definitions and replace its uses in a chain .


<s> static void expand_block_move_4 ( rtx dst , rtx dst_reg , rtx src , rtx src_reg , rtx bytes_rtx ) { unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % 4 ; if ( TARGET_BMI ) { unsigned int i ; rtx insn ; emit_move_insn ( regno_reg_rtx [ 1 ] , dst_reg ) ; emit_move_insn ( regno_reg_rtx [ 2 ] , src_reg ) ; emit_move_insn ( regno_reg_rtx [ 3 ] , bytes_rtx ) ; insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 8 ) ) ; XVECEXP ( insn , 0 , 0 ) = gen_rtx_SET ( replace_equiv_address_nv ( dst , regno_reg_rtx [ 1 ] ) , replace_equiv_address_nv ( src , regno_reg_rtx [ 2 ] ) ) ; XVECEXP ( insn , 0 , 1 ) = gen_rtx_USE ( VOIDmode , regno_reg_rtx [ 3 ] ) ; for ( i = 1 ; i <= 6 ; i ++ ) XVECEXP ( insn , 0 , 1 + i ) = gen_rtx_CLOBBER ( VOIDmode , regno_reg_rtx [ i ] ) ; emit_insn ( insn ) ; } else emit_library_call ( long_int_memcpy_libfunc , LCT_NORMAL , VOIDmode , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> 2 ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == 0 ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; src = replace_equiv_address_nv ( src , src_reg ) ; bytes -= rem ; if ( rem > 1 ) { emit_move_insn ( adjust_address_nv ( dst , HImode , bytes ) , adjust_address_nv ( src , HImode , bytes ) ) ; bytes += 2 ; rem -= 2 ; } if ( rem > 0 ) emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , adjust_address_nv ( src , QImode , bytes ) ) ; } </s>

Generate a call to a library function to move BYTES_RTX bytes from SRC with address SRC_REG to DST with address DST_REG in 4-byte chunks .


<s> static bool rs6000_legitimate_address_p ( machine_mode mode , rtx x , bool reg_ok_strict ) { bool reg_offset_p = reg_offset_addressing_ok_p ( mode ) ; bool quad_offset_p = mode_supports_dq_form ( mode ) ; if ( VECTOR_MEM_ALTIVEC_P ( mode ) && GET_CODE ( x ) == AND && CONST_INT_P ( XEXP ( x , 1 ) ) && INTVAL ( XEXP ( x , 1 ) ) == - 16 ) x = XEXP ( x , 0 ) ; if ( TARGET_ELF && RS6000_SYMBOL_REF_TLS_P ( x ) ) return 0 ; if ( legitimate_indirect_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && ( GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) ) return 1 ; if ( quad_offset_p ) { if ( quad_address_p ( x , mode , reg_ok_strict ) ) return 1 ; } else if ( virtual_stack_registers_memory_p ( x ) ) return 1 ; else if ( reg_offset_p ) { if ( legitimate_small_data_p ( mode , x ) ) return 1 ; if ( legitimate_constant_pool_address_p ( x , mode , reg_ok_strict || lra_in_progress ) ) return 1 ; } if ( mode == TImode && TARGET_VSX ) return 0 ; if ( ! reg_ok_strict && reg_offset_p && GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , 0 ) ) && ( XEXP ( x , 0 ) == virtual_stack_vars_rtx || XEXP ( x , 0 ) == arg_pointer_rtx ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) return 1 ; if ( rs6000_legitimate_offset_address_p ( mode , x , reg_ok_strict , false ) ) return 1 ; if ( ! FLOAT128_2REG_P ( mode ) && ( TARGET_HARD_FLOAT || TARGET_POWERPC64 || ( mode != DFmode && mode != DDmode ) ) && ( TARGET_POWERPC64 || mode != DImode ) && ( mode != TImode || VECTOR_MEM_VSX_P ( TImode ) ) && mode != PTImode && ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( x , reg_ok_strict ) ) return 1 ; if ( TARGET_UPDATE && GET_CODE ( x ) == PRE_MODIFY && mode_supports_pre_modify_p ( mode ) && legitimate_indirect_address_p ( XEXP ( x , 0 ) , reg_ok_strict ) && ( rs6000_legitimate_offset_address_p ( mode , XEXP ( x , 1 ) , reg_ok_strict , false ) || ( ! avoiding_indexed_address_p ( mode ) && legitimate_indexed_address_p ( XEXP ( x , 1 ) , reg_ok_strict ) ) ) && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) return 1 ; if ( reg_offset_p && ! quad_offset_p && legitimate_lo_sum_address_p ( mode , x , reg_ok_strict ) ) return 1 ; return 0 ; } </s>

TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address . On the RS/6000 , there are four valid address : a SYMBOL_REF that refers to a constant pool entry of an address ( or the sum of it plus a constant ) , a short ( 16-bit signed ) constant plus a register , the sum of two registers , or a register indirect , possibly with an auto-increment . For DFmode , DDmode and DImode with a constant plus register , we must ensure that both words are addressable or PowerPC64 with offset word aligned . For modes spanning multiple registers ( DFmode and DDmode in 32-bit GPRs , 32-bit DImode , TImode , TFmode , TDmode ) , indexed addressing can not be used because adjacent memory cells are accessed by adding word-sized offsets during assembly output .


<s> Value * ARMTargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isAtLeastRelease ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlexd : Intrinsic :: arm_strexd ; Function * Strex = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int32Ty = Type :: getInt32Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int32Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 32 ) , Int32Ty , "hi" ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: arm_stlex : Intrinsic :: arm_strex ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Strex = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall ( Strex , { Builder . CreateZExtOrBitCast ( Val , Strex -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> rtx mmix_eh_return_stackadj_rtx ( void ) { return gen_rtx_REG ( Pmode , MMIX_EH_RETURN_STACKADJ_REGNUM ) ; } </s>


<s> fma_forest * fma_root_node :: get_forest ( ) { return this -> m_forest ; } </s>

Get the actual forest associated with a non root node as the one the node points to might have been merged into another one . In that case the pointer in the root nodes are updated so we return the forest pointer of a root node pointed to by the initial forest . Despite being a oneliner , this method is defined here as it references a method from fma_root_node .


<s> const DataLayout * getDataLayout ( ) const override { return & Layout ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


We precompute a number of expression trees for multiplying by constants . This generates code for such an expression tree by walking through the nodes in the tree ( which are conveniently pre-linearized ) and emitting an instruction for each one .


<s> static void emit_unlikely_jump ( rtx cond , rtx label ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx x ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , cond , label , pc_rtx ) ; x = emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , x ) ) ; add_int_reg_note ( x , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


"SPUTargetLowering::ReplaceNodeResults(): need to fix this!\n"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


Metadata straight from the call to llvm.gcroot .


<s> SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueType ( ) . getSizeInBits ( ) ; if ( ! AlwaysInline && ( Align & 3 ) == 0 && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , 3 ) ) ) { const TargetLowering & TLI = * DAG . getTarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( "__memcpy_4" , TLI . getPointerTy ( ) ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> bool isScalarFPTypeInSSEReg ( EVT VT ) const { return ( VT == MVT :: f64 && X86ScalarSSEf64 ) || ( VT == MVT :: f32 && X86ScalarSSEf32 ) ; } </s>

Return true if the specified scalar FP type is computed in an SSE register , not on the X87 floating point stack .


<s> static unsigned addLiveIn ( MachineFunction & MF , unsigned PReg , const TargetRegisterClass * RC ) { unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ; return VReg ; } </s>

addLiveIn - Add the specified register as a live-in .


<s> static rtx z8k_libcall_value ( enum machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , \ ( TARGET_STD_RET ? ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( HImode ) ? 7 : \ GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( SImode ) ? 6 : 4 ) : 2 ) ) ; } </s>

Define how to find the value returned by a library function assuming the value has mode MODE .


<s> void P2PassConfig :: addPreEmitPass ( ) { P2TargetMachine & TM = getP2TargetMachine ( ) ; addPass ( createP2DelJmpPass ( TM ) ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool runOnMachineFunction ( MachineFunction & Fn ) override { Subtarget = & Fn . getSubtarget < HexagonSubtarget > ( ) ; const bool Modified = AsmPrinter :: runOnMachineFunction ( Fn ) ; emitXRayTable ( ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


"PPC hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> yaml :: MachineFunctionInfo * AArch64TargetMachine :: createDefaultFuncInfoYAML ( ) const { return new yaml :: AArch64FunctionInfo ( ) ; } </s>

Allocate and return a default initialized instance of the YAML representation for the MachineFunctionInfo .


<s>
CCAssignFn
*
AArch64TargetLowering
::
CCAssignFnForCall
(
CallingConv
::
ID
CC
,
bool
IsVarArg
)
const
{
switch
(
CC
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention."
)
;
case
CallingConv
::
WebKit_JS
:
return
CC_AArch64_WebKit_JS
;
case
CallingConv
::
GHC
:
return
CC_AArch64_GHC
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
case
CallingConv
::
PreserveMost
:
case
CallingConv
::
CXX_FAST_TLS
:
case
CallingConv
::
Swift
:
if
(
!
Subtarget
->
isTargetDarwin
(
)
)
return
CC_AArch64_AAPCS
;
return
IsVarArg
CC_AArch64_DarwinPCS_VarArg
:
CC_AArch64_DarwinPCS
;
}
}
</s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> bool X86TargetLowering :: isIntDivCheap ( EVT VT , AttributeSet Attr ) const { bool OptSize = Attr . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ; } </s>

Return true if integer divide is usually cheaper than a sequence of several shifts , adds , and multiplies for this target .


<s> bool RISCVInstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { if ( Opt == "no-aliases" ) { PrintAliases = false ; return true ; } if ( Opt == "numeric" ) { ArchRegNames = true ; return true ; } return false ; } </s>

Customize the printer according to a command line option .


<s> static unsigned int aarch64_sve_rev_unspec ( machine_mode mode ) { switch ( GET_MODE_UNIT_SIZE ( mode ) ) { case 1 : return UNSPEC_REVB ; case 2 : return UNSPEC_REVH ; case 4 : return UNSPEC_REVW ; } gcc_unreachable ( ) ; } </s>

Return the SVE REV [ BHW ] unspec for reversing quantites of mode MODE stored in wider integer containers .


<s> static std :: string readline ( FILE * f ) { char * buf = NULL ; int size = 0 ; int last = 0 ; const int buf_size = 128 ; if ( feof ( f ) ) return std :: string ( ) ; do { size += buf_size ; buf = ( char * ) xrealloc ( buf , size ) ; gcc_assert ( buf ) ; if ( ! fgets ( buf + last , buf_size , f ) ) return std :: string ( ) ; last = strnlen ( buf , size ) - 1 ; } while ( ! feof ( f ) && buf [ last ] != '\n' ) ; std :: string result ( buf ) ; free ( buf ) ; return result ; } </s>

Read an entire line from F until '\n ' or EOF .


<s> static rtx alpha_emit_set_const ( rtx target , enum machine_mode mode , HOST_WIDE_INT c , int n , bool no_output ) { enum machine_mode orig_mode = mode ; rtx orig_target = target ; rtx result = 0 ; int i ; if ( no_new_pseudos && mode == SImode && GET_CODE ( target ) == REG && REGNO ( target ) < FIRST_PSEUDO_REGISTER ) { result = alpha_emit_set_const_1 ( target , mode , c , 1 , no_output ) ; if ( result ) return result ; target = no_output ? NULL : gen_lowpart ( DImode , target ) ; mode = DImode ; } else if ( mode == V8QImode || mode == V4HImode || mode == V2SImode ) { target = no_output ? NULL : gen_lowpart ( DImode , target ) ; mode = DImode ; } for ( i = 1 ; i <= n ; i ++ ) { result = alpha_emit_set_const_1 ( target , mode , c , i , no_output ) ; if ( result ) { rtx insn , set ; if ( no_output ) return result ; insn = get_last_insn ( ) ; set = single_set ( insn ) ; if ( ! CONSTANT_P ( SET_SRC ( set ) ) ) set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , GEN_INT ( c ) ) ; break ; } } if ( result ) { if ( result == target ) result = orig_target ; else if ( mode != orig_mode ) result = gen_lowpart ( orig_mode , result ) ; } return result ; } </s>

Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns . Do all computations in MODE . Returns the place where the output has been placed if it can be done and the insns have been emitted . If it would take more than N insns , zero is returned and no insns and emitted .


"Pseudo flag setting opcodes only exist in Selection DAG"

"Non-flag-setting Thumb1 mov is v6-only"

"Unsupported register in Thumb1 push/pop"

"Incorrect array index for MVE_VMOV_q_rr"

"Incorrect AddrMode Imm for instruction"

Perform target-specific instruction verification .


<s> void erase ( const Node * N ) { Root = remove ( Root , N ) ; delete N ; } </s>

erase - Erases an element identified by Key , if it exists .


"********* Hexagon Hardware Loops *********\n"


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { if ( Subtarget -> isTargetNaCl ( ) || ! EnableARMAEABIFunctions || ! Subtarget -> isAAPCS_ABI ( ) || Subtarget -> isTargetDarwin ( ) ) return SDValue ( ) ; const ARMTargetLowering & TLI = * static_cast < const ARMTargetLowering * > ( DAG . getTarget ( ) . getTargetLowering ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Type * IntPtrTy = TLI . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Entry . Ty = IntPtrTy ; Entry . isSExt = false ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( MVT :: i32 ) ) Src = DAG . getNode ( ISD :: TRUNCATE , dl , MVT :: i32 , Src ) ; else Src = DAG . getNode ( ISD :: ZERO_EXTEND , dl , MVT :: i32 , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , 0 , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } </s>

Emit target-specific code that performs a memset .


<s> bool R600TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , Align Alignment , MachineMemOperand :: Flags Flags , bool * IsFast ) const { if ( IsFast ) * IsFast = false ; if ( ! VT . isSimple ( ) || VT == MVT :: Other ) return false ; if ( VT . bitsLT ( MVT :: i32 ) ) return false ; if ( IsFast ) * IsFast = true ; return VT . bitsGT ( MVT :: i32 ) && Alignment >= Align ( 4 ) ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


"Load should return a value and a chain"

LowerOperation - Provide custom lowering hooks for some operations .


<s> static bool ix86_in_large_data_p ( tree exp ) { if ( ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = TREE_STRING_POINTER ( DECL_SECTION_NAME ( exp ) ) ; if ( strcmp ( section , ".ldata" ) == 0 || strcmp ( section , ".lbss" ) == 0 ) return true ; return false ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp ) ) ; if ( ! size || size > ix86_section_threshold ) return true ; } return false ; } </s>

Return true if this goes in small data/bss .


<s> unsigned TGSIInstrInfo :: isStoreToStackSlot ( const MachineInstr * mi , int & fi ) const { if ( ( mi -> getOpcode ( ) == TGSI :: STpis || mi -> getOpcode ( ) == TGSI :: STpfs || mi -> getOpcode ( ) == TGSI :: STpiv || mi -> getOpcode ( ) == TGSI :: STpfv ) && mi -> getOperand ( 0 ) . isFI ( ) ) { assert ( 0 ) ; fi = mi -> getOperand ( 0 ) . getIndex ( ) ; return mi -> getOperand ( 1 ) . getReg ( ) ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> rtx function_expander :: get_contiguous_base ( machine_mode mem_mode ) { rtx base = convert_to_pmode ( args [ 1 ] ) ; if ( mode_suffix_id == MODE_vnum ) { poly_int64 size = ordered_min ( GET_MODE_SIZE ( mem_mode ) , BYTES_PER_SVE_VECTOR ) ; rtx offset = gen_int_mode ( size , Pmode ) ; offset = simplify_gen_binary ( MULT , Pmode , args [ 2 ] , offset ) ; base = simplify_gen_binary ( PLUS , Pmode , base , offset ) ; } return base ; } </s>

Return the base address for a contiguous load or store function . MEM_MODE is the mode of the addressed memory .


<s> void StackFixup :: apply ( Stack & stack ) const { for ( auto p : Changes ) stack += p . first ; } </s>

Apply the profile inference algorithm for a given function .


<s> bool Error ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = ArrayRef < SMRange > ( ) ) { return Parser . Error ( L , Msg , Ranges ) ; } </s>

Return an error at the location L , with the message Msg .


<s> MachineBasicBlock * getHeader ( ) const { return EHPad ; } </s>

The header is the entry for each iteration .


<s> static bool ix86_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( mode1 == mode2 ) return true ; if ( ix86_tieable_integer_mode_p ( mode1 ) && ix86_tieable_integer_mode_p ( mode2 ) ) return true ; if ( mode2 == XFmode ) return mode1 == SFmode || mode1 == DFmode ; if ( mode2 == DFmode ) return mode1 == SFmode ; if ( GET_MODE_SIZE ( mode2 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 32 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 16 && ix86_hard_regno_mode_ok ( FIRST_SSE_REG , mode1 ) ) ; if ( GET_MODE_SIZE ( mode2 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode2 ) ) return ( GET_MODE_SIZE ( mode1 ) == 8 && ix86_hard_regno_mode_ok ( FIRST_MMX_REG , mode1 ) ) ; return false ; } </s>

Return true if MODE1 is accessible in a register that can hold MODE2 without copying . That is , all register classes that can hold MODE2 can also hold MODE1 .


<s> bool HSAILInstrInfo :: areLoadsFromSameBasePtr ( SDNode * Node1 , SDNode * Node2 , int64_t & Offset1 , int64_t & Offset2 ) const { if ( ! Node1 -> isMachineOpcode ( ) || ! Node2 -> isMachineOpcode ( ) ) return false ; MachineSDNode * mnode1 = cast < MachineSDNode > ( Node1 ) , * mnode2 = cast < MachineSDNode > ( Node2 ) ; if ( mnode1 -> memoperands_empty ( ) || mnode2 -> memoperands_empty ( ) ) return false ; if ( ( mnode1 -> memoperands_begin ( ) + 1 ) != mnode1 -> memoperands_end ( ) || ( mnode2 -> memoperands_begin ( ) + 1 ) != mnode2 -> memoperands_end ( ) ) return false ; MachineMemOperand * mo1 , * mo2 ; mo1 = * mnode1 -> memoperands_begin ( ) ; mo2 = * mnode2 -> memoperands_begin ( ) ; if ( mo1 -> getSize ( ) != mo2 -> getSize ( ) || mo1 -> getPointerInfo ( ) . getAddrSpace ( ) != mo2 -> getPointerInfo ( ) . getAddrSpace ( ) || mo1 -> getValue ( ) != mo2 -> getValue ( ) || mo1 -> getFlags ( ) != mo2 -> getFlags ( ) ) { return false ; } Offset1 = mo1 -> getOffset ( ) ; Offset2 = mo2 -> getOffset ( ) ; return true ; } </s>

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address .


<s> static void arm_set_fixed_optab_libfunc ( optab optable , machine_mode mode , const char * funcname , const char * modename , int num_suffix ) { char buffer [ 50 ] ; if ( num_suffix == 0 ) sprintf ( buffer , "__gnu_%s%s" , funcname , modename ) ; else sprintf ( buffer , "__gnu_%s%s%d" , funcname , modename , num_suffix ) ; set_optab_libfunc ( optable , mode , buffer ) ; } </s>

A small helper for setting fixed-point library libfuncs .


<s> TTI :: AddressingModeKind ARMTTIImpl :: getPreferredAddressingMode ( const Loop * L , ScalarEvolution * SE ) const { if ( ST -> hasMVEIntegerOps ( ) ) return TTI :: AMK_PostIndexed ; if ( L -> getHeader ( ) -> getParent ( ) -> hasOptSize ( ) ) return TTI :: AMK_None ; if ( ST -> isMClass ( ) && ST -> isThumb2 ( ) && L -> getNumBlocks ( ) == 1 ) return TTI :: AMK_PreIndexed ; return TTI :: AMK_None ; } </s>

Return the preferred addressing mode LSR should make efforts to generate .


<s> void SITargetLowering :: AdjustInstrPostInstrSelection ( MachineInstr * MI , SDNode * Node ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; if ( ! TII -> isMIMG ( MI -> getOpcode ( ) ) ) return ; unsigned VReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned Writemask = MI -> getOperand ( 1 ) . getImm ( ) ; unsigned BitsSet = 0 ; for ( unsigned i = 0 ; i < 4 ; ++ i ) BitsSet += Writemask & ( 1 << i ) ? 1 : 0 ; const TargetRegisterClass * RC ; switch ( BitsSet ) { default : return ; case 1 : RC = & AMDGPU :: VReg_32RegClass ; break ; case 2 : RC = & AMDGPU :: VReg_64RegClass ; break ; case 3 : RC = & AMDGPU :: VReg_96RegClass ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get ( NewOpcode ) ) ; MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MRI . setRegClass ( VReg , RC ) ; } </s>

This method should be implemented by targets that mark instructions with the 'hasPostISelHook ' flag .


<s>
bool
SPIRVGenerateDecorations
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
MachineIRBuilder
MIRBuilder
(
MF
)
;
auto
&
MRI
=
MF
.
getRegInfo
(
)
;
for
(
auto
&
MBB
:
MF
)
{
MIRBuilder
.
setMBB
(
MBB
)
;
for
(
auto
&
MI
:
MBB
)
{
if
(
!
canUseFastMathFlags
(
MI
.
getOpcode
(
)
)
)
continue
;
MIRBuilder
.
setInstr
(
MI
)
;
auto
FMFlags
=
getFastMathFlags
(
MI
)
;
if
(
FMFlags
!=
FPFastMathMode
::
)
{
Register
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
assert
(
MRI
.
hasOneUse
(
DstReg
)
&&
"One use is expected"
)
;
Register
NewReg
=
MRI
.
use_instr_begin
(
DstReg
)
->
getOperand
(
0
)
.
getReg
(
)
;
MIRBuilder
.
buildInstr
(
SPIRV
::
OpDecorate
)
.
addUse
(
NewReg
)
.
addImm
(
Decoration
::
FPFastMathMode
)
.
addImm
(
FMFlags
)
;
}
}
}
for
(
auto
&
MBB
:
MF
)
{
for
(
auto
&
MI
:
MBB
)
{
if
(
MI
.
getOpcode
(
)
==
SPIRV
::
ASSIGN_TYPE
)
{
Register
SrcReg
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
if
(
isTypeFoldingSupported
(
MRI
.
getVRegDef
(
SrcReg
)
->
getOpcode
(
)
)
)
{
Register
DstReg
=
MI
.
getOperand
(
0
)
.
getReg
(
)
;
if
(
MRI
.
getType
(
DstReg
)
.
isVector
(
)
)
MRI
.
setRegClass
(
DstReg
,
&
SPIRV
::
IDRegClass
)
;
MRI
.
setType
(
DstReg
,
LLT
::
scalar
(
32
)
)
;
}
}
}
}
return
true
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> bool M88kDelaySlotFiller :: runOnMachineFunction ( MachineFunction & MF ) { const M88kSubtarget & Subtarget = MF . getSubtarget < M88kSubtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= runOnMachineBasicBlock ( MBB ) ; return Changed ; } </s>


<s> static unsigned int arm_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( IS_VPR_REGNUM ( regno ) ) return CEIL ( GET_MODE_SIZE ( mode ) , 2 ) ; if ( TARGET_32BIT && regno > PC_REGNUM && regno != FRAME_POINTER_REGNUM && regno != ARG_POINTER_REGNUM && ! IS_VFP_REGNUM ( regno ) ) return 1 ; return ARM_NUM_REGS ( mode ) ; } </s>

Implement TARGET_HARD_REGNO_NREGS . On the ARM core regs are UNITS_PER_WORD bytes wide .


<s> unsigned ARMBaseInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case ARM :: STRrs : case ARM :: t2STRs : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isReg ( ) && MI . getOperand ( 3 ) . isImm ( ) && MI . getOperand ( 2 ) . getReg ( ) == 0 && MI . getOperand ( 3 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: STRi12 : case ARM :: t2STRi12 : case ARM :: tSTRspi : case ARM :: VSTRD : case ARM :: VSTRS : case ARM :: VSTR_P0_off : case ARM :: MVE_VSTRWU32 : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: VST1q64 : case ARM :: VST1d64TPseudo : case ARM :: VST1d64QPseudo : if ( MI . getOperand ( 0 ) . isFI ( ) && MI . getOperand ( 2 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 0 ) . getIndex ( ) ; return MI . getOperand ( 2 ) . getReg ( ) ; } break ; case ARM :: VSTMQIA : if ( MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 0 ) . getSubReg ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; case ARM :: MQQPRStore : case ARM :: MQQQQPRStore : if ( MI . getOperand ( 1 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>


<s> bool AMDGPUSubtarget :: makeLIDRangeMetadata ( Instruction * I ) const { Function * Kernel = I -> getParent ( ) -> getParent ( ) ; unsigned MinSize = 0 ; unsigned MaxSize = getFlatWorkGroupSizes ( * Kernel ) . second ; bool IdQuery = false ; if ( auto * CI = dyn_cast < CallInst > ( I ) ) { const Function * F = CI -> getCalledFunction ( ) ; if ( F ) { unsigned Dim = UINT_MAX ; switch ( F -> getIntrinsicID ( ) ) { case Intrinsic :: amdgcn_workitem_id_x : case Intrinsic :: r600_read_tidig_x : IdQuery = true ; LLVM_FALLTHROUGH ; case Intrinsic :: r600_read_local_size_x : Dim = 0 ; break ; case Intrinsic :: amdgcn_workitem_id_y : case Intrinsic :: r600_read_tidig_y : IdQuery = true ; LLVM_FALLTHROUGH ; case Intrinsic :: r600_read_local_size_y : Dim = 1 ; break ; case Intrinsic :: amdgcn_workitem_id_z : case Intrinsic :: r600_read_tidig_z : IdQuery = true ; LLVM_FALLTHROUGH ; case Intrinsic :: r600_read_local_size_z : Dim = 2 ; break ; default : break ; } if ( Dim <= 3 ) { unsigned ReqdSize = getReqdWorkGroupSize ( * Kernel , Dim ) ; if ( ReqdSize != std :: numeric_limits < unsigned > :: max ( ) ) MinSize = MaxSize = ReqdSize ; } } } if ( ! MaxSize ) return false ; if ( IdQuery ) MinSize = 0 ; else ++ MaxSize ; MDBuilder MDB ( I -> getContext ( ) ) ; MDNode * MaxWorkGroupSizeRange = MDB . createRange ( APInt ( 32 , MinSize ) , APInt ( 32 , MaxSize ) ) ; I -> setMetadata ( LLVMContext :: MD_range , MaxWorkGroupSizeRange ) ; return true ; } </s>

Creates value range metadata on an workitemid . * intrinsic call or load .


<s> bool ARMTargetLowering :: isLegalInterleavedAccessType ( unsigned Factor , VectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( ! Subtarget -> hasNEON ( ) && ! Subtarget -> hasMVEIntegerOps ( ) ) return false ; if ( Subtarget -> hasNEON ( ) && VecTy -> getElementType ( ) -> isHalfTy ( ) ) return false ; if ( Subtarget -> hasMVEIntegerOps ( ) && Factor == 3 ) return false ; if ( VecTy -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 ) return false ; if ( Subtarget -> hasNEON ( ) && VecSize == 64 ) return true ; return VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( "use-soft-float" ) . getValueAsBool ( ) ; if ( SoftFloat ) FS += FS . empty ( ) ? "-hard-float" : ",-hard-float" ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < PPCSubtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" "use-soft-float" "-hard-float" ",-hard-float" PPC


<s> static bool tilepro_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : return ! tilepro_tls_referenced_p ( x ) ; default : return true ; } } </s>

Implement TARGET_LEGITIMATE_CONSTANT_P . This is all constants for which we are willing to load the value into a register via a move pattern . TLS can not be treated as a constant because it can include a function call .


<s> void emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned AArch64AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { AArch64Operand & Op = static_cast < AArch64Operand & > ( AsmOp ) ; int64_t ExpectedVal ; switch ( Kind ) { default : return Match_InvalidOperand ; case MCK__HASH_0 : ExpectedVal = 0 ; break ; case MCK__HASH_1 : ExpectedVal = 1 ; break ; case MCK__HASH_12 : ExpectedVal = 12 ; break ; case MCK__HASH_16 : ExpectedVal = 16 ; break ; case MCK__HASH_2 : ExpectedVal = 2 ; break ; case MCK__HASH_24 : ExpectedVal = 24 ; break ; case MCK__HASH_3 : ExpectedVal = 3 ; break ; case MCK__HASH_32 : ExpectedVal = 32 ; break ; case MCK__HASH_4 : ExpectedVal = 4 ; break ; case MCK__HASH_48 : ExpectedVal = 48 ; break ; case MCK__HASH_6 : ExpectedVal = 6 ; break ; case MCK__HASH_64 : ExpectedVal = 64 ; break ; case MCK__HASH_8 : ExpectedVal = 8 ; break ; case MCK_MPR : if ( Op . isTokenEqual ( "za" ) ) return Match_Success ; break ; } if ( ! Op . isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == ExpectedVal ) return Match_Success ; return Match_InvalidOperand ; } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


"Only FP0 could be passed as an argument"


<s> bool ARMTargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == 0 || Bits > 32 ) return false ; return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> bool direct_move_p ( rtx op0 , rtx op1 ) { int regno0 , regno1 ; if ( ! REG_P ( op0 ) || ! REG_P ( op1 ) ) return false ; if ( ! TARGET_DIRECT_MOVE && ! TARGET_MFPGPR ) return false ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; if ( regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER ) return false ; if ( INT_REGNO_P ( regno0 ) ) return ( TARGET_DIRECT_MOVE ) ? VSX_REGNO_P ( regno1 ) : FP_REGNO_P ( regno1 ) ; else if ( INT_REGNO_P ( regno1 ) ) { if ( TARGET_MFPGPR && FP_REGNO_P ( regno0 ) ) return true ; else if ( TARGET_DIRECT_MOVE && VSX_REGNO_P ( regno0 ) ) return true ; } return false ; } </s>

Return true if this is a move direct operation between GPR registers and floating point/VSX registers .


<s> void MipsPassConfig :: addPreLegalizeMachineIR ( ) { addPass ( createMipsPreLegalizeCombiner ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before legalization .


"WebAssembly hasn't implemented computed gotos"

"WebAssembly hasn't implemented __builtin_return_address"

LowerOperation - Provide custom lowering hooks for some operations .


<s> const char * SystemZTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { OPCODE ( RET_FLAG ) ; OPCODE ( CALL ) ; OPCODE ( PCREL_WRAPPER ) ; OPCODE ( CMP ) ; OPCODE ( UCMP ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; } return NULL ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool X86DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , Op2 , Op3 , Op4 ; switch ( ConstraintCode ) { case 'o' : case 'v' : default : return true ; case 'm' : if ( ! SelectAddr ( Op . getNode ( ) , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ; OutOps . push_back ( Op3 ) ; OutOps . push_back ( Op4 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; MipsSubtarget const & STI = static_cast < const MipsSubtarget & > ( MF . getSubtarget ( ) ) ; const TargetRegisterClass * RC = STI . inMips16Mode ( ) ? & Mips :: CPU16RegsRegClass : STI . inMicroMipsMode ( ) ? & Mips :: GPRMM16RegClass : static_cast < const MipsTargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> static void emitSPUpdate ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , unsigned StackPtr , int64_t NumBytes , bool Is64BitTarget , bool Is64BitStackPtr , bool UseLEA , const TargetInstrInfo & TII , const TargetRegisterInfo & TRI ) { bool isSub = NumBytes < 0 ; uint64_t Offset = isSub ? - NumBytes : NumBytes ; unsigned Opc ; if ( UseLEA ) Opc = getLEArOpcode ( Is64BitStackPtr ) ; else Opc = isSub ? getSUBriOpcode ( Is64BitStackPtr , Offset ) : getADDriOpcode ( Is64BitStackPtr , Offset ) ; uint64_t Chunk = ( 1LL << 31 ) - 1 ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64BitTarget ? 8 : 4 ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64BitTarget ? X86 :: RAX : X86 :: EAX ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = isSub ? ( Is64BitTarget ? X86 :: PUSH64r : X86 :: PUSH32r ) : ( Is64BitTarget ? X86 :: POP64r : X86 :: POP32r ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ; if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; continue ; } } MachineInstr * MI = nullptr ; if ( UseLEA ) { MI = addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , StackPtr , false , isSub ? - ThisVal : ThisVal ) ; } else { MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( ThisVal ) ; MI -> getOperand ( 3 ) . setIsDead ( ) ; } if ( isSub ) MI -> setFlag ( MachineInstr :: FrameSetup ) ; Offset -= ThisVal ; } } </s>

Emit a series of instructions to increment / decrement the stack pointer by a constant value .


<s>
void
ArgDescriptor
::
print
(
raw_ostream
&
OS
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
!
isSet
(
)
)
{
OS
<<
"<not set>\n"
;
return
;
}
if
(
isRegister
(
)
)
OS
<<
"Reg "
<<
PrintReg
(
getRegister
(
)
,
TRI
)
<<
'\n'
;
else
OS
<<
"Stack offset "
<<
getStackOffset
(
)
<<
'\n'
;
}
</s>

print - Print a debug representation of the operand to the given stream .

AMDGPU
"<not set>\n"
"Reg "
"Stack offset "


<s> static rtl_opt_pass * make_pass_fma_steering ( gcc :: context * ctxt ) { return new pass_fma_steering ( ctxt ) ; } </s>

Create a new fma steering pass instance .


<s> enum reg_class alpha_preferred_reload_class ( rtx x , enum reg_class rclass ) { if ( x == CONST0_RTX ( GET_MODE ( x ) ) ) return rclass ; if ( CONST_SCALAR_INT_P ( x ) || CONST_DOUBLE_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) { if ( rclass == FLOAT_REGS ) return NO_REGS ; if ( rclass == ALL_REGS ) return GENERAL_REGS ; return rclass ; } if ( CONSTANT_P ( x ) ) return ( rclass == ALL_REGS ? GENERAL_REGS : rclass ) ; return rclass ; } </s>

On the Alpha , all ( non-symbolic ) constants except zero go into a floating-point register via memory . Note that we can not return anything that is not a subset of CLASS , and that some symbolic constants can not be dropped to memory .


<s>
static
void
rs6000_elf_output_toc_section_asm_op
(
const
char
*
data
ATTRIBUTE_UNUSED
)
{
if
(
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
&&
TARGET_MINIMAL_TOC
)
{
if
(
!
toc_initialized
)
{
fprintf
(
asm_out_file
,
"%s\n"
,
TOC_SECTION_ASM_OP
)
;
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
(
*
targetm
.
asm_out
.
internal_label
)
(
asm_out_file
,
"LCTOC"
,
0
)
;
fprintf
(
asm_out_file
,
"\t.tc "
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1[TC],"
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
"\n"
)
;
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
" = .+32768\n"
)
;
toc_initialized
=
1
;
}
else
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
}
else
if
(
DEFAULT_ABI
==
ABI_AIX
||
DEFAULT_ABI
==
ABI_ELFv2
)
{
fprintf
(
asm_out_file
,
"%s\n"
,
TOC_SECTION_ASM_OP
)
;
if
(
!
toc_initialized
)
{
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
toc_initialized
=
1
;
}
}
else
{
fprintf
(
asm_out_file
,
"%s\n"
,
MINIMAL_TOC_SECTION_ASM_OP
)
;
if
(
!
toc_initialized
)
{
ASM_OUTPUT_ALIGN
(
asm_out_file
,
TARGET_64BIT
3
:
2
)
;
ASM_OUTPUT_INTERNAL_LABEL_PREFIX
(
asm_out_file
,
"LCTOC1"
)
;
fprintf
(
asm_out_file
,
" = .+32768\n"
)
;
toc_initialized
=
1
;
}
}
}
</s>

A get_unnamed_section callback , used for switching to toc_section .


<s> unsigned getNumFixupKinds ( ) const override { return 0 ; } </s>

Get the number of target specific fixup kinds .


<s> static void tilepro_expand_unaligned_store ( rtx mem , rtx src , HOST_WIDE_INT bitsize , HOST_WIDE_INT bit_offset ) { HOST_WIDE_INT byte_offset = bit_offset / BITS_PER_UNIT ; HOST_WIDE_INT bytesize = bitsize / BITS_PER_UNIT ; HOST_WIDE_INT shift_amt ; HOST_WIDE_INT i ; rtx mem_addr ; rtx store_val ; for ( i = 0 , shift_amt = 0 ; i < bytesize ; i ++ , shift_amt += BITS_PER_UNIT ) { mem_addr = adjust_address ( mem , QImode , byte_offset + i ) ; if ( shift_amt ) { store_val = expand_simple_binop ( SImode , LSHIFTRT , gen_lowpart ( SImode , src ) , GEN_INT ( shift_amt ) , NULL , 1 , OPTAB_LIB_WIDEN ) ; store_val = gen_lowpart ( QImode , store_val ) ; } else { store_val = gen_lowpart ( QImode , src ) ; } emit_move_insn ( mem_addr , store_val ) ; } } </s>


<s> bool find ( const Function * F , MachineFunction * MF , Register & R ) { return DT . find ( F , MF , R ) ; } </s>

Search for the first string Str in the string .


runOnMachineFunction - Emit the function body .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
if
(
skipFunction
(
*
Fn
.
getFunction
(
)
)
)
return
false
;
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineBasicBlock
&
MBB
:
Fn
)
{
for
(
MachineInstr
&
MI
:
MBB
)
{
Modified
|=
runOnInstruction
(
&
MI
)
;
}
}
for
(
MachineInstr
*
MI
:
DeadInstr
)
{
MI
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>


<s> const SDValue & getValue ( ) const { return getOperand ( 3 ) ; } </s>


<s> bool X86FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; if ( isFuncletReturnInstr ( MI ) && STI . is32Bit ( ) && STI . isOSWindows ( ) ) return true ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? X86 :: POP64r : X86 :: POP32r ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) ; } return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static unsigned int frv_insn_unit ( rtx insn ) { enum attr_type type ; type = get_attr_type ( insn ) ; if ( frv_type_to_unit [ type ] == ARRAY_SIZE ( frv_unit_codes ) ) { state_t state ; unsigned int unit ; state = alloca ( state_size ( ) ) ; state_reset ( state ) ; state_transition ( state , insn ) ; for ( unit = 0 ; unit < ARRAY_SIZE ( frv_unit_codes ) ; unit ++ ) if ( cpu_unit_reservation_p ( state , frv_unit_codes [ unit ] ) ) break ; gcc_assert ( unit != ARRAY_SIZE ( frv_unit_codes ) ) ; frv_type_to_unit [ type ] = unit ; } return frv_type_to_unit [ type ] ; } </s>

Return the index of the DFA unit in FRV_UNIT_NAMES [ ] that instruction INSN will try to claim first . Since this value depends only on the type attribute , we can cache the results in FRV_TYPE_TO_UNIT [ ] .


<s> static int supersparc_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep_insn , int cost ) { enum attr_type insn_type ; if ( recog_memoized ( insn ) < 0 ) return cost ; insn_type = get_attr_type ( insn ) ; if ( dep_type == 0 ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD ) return cost + 3 ; if ( insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return cost ; if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return cost ; return cost + 3 ; } if ( insn_type == TYPE_SHIFT ) return cost + 3 ; } else { if ( insn_type == TYPE_IALU || insn_type == TYPE_SHIFT ) return 0 ; } return cost ; } </s>

Adjust the cost of a scheduling dependency . Return the new cost of a dependency LINK or INSN on DEP_INSN . COST is the current cost .


Create and return the va_list datatype . On S/390 , va_list is an array type equivalent to typedef struct __va_list_tag { long __gpr ; long __fpr ; void * __overflow_arg_area ; void * __reg_save_area ; } va_list [ 1 ] ; where __gpr and __fpr hold the number of general purpose or floating point arguments used up to now , respectively , __overflow_arg_area points to the stack location of the next argument passed on the stack , and __reg_save_area always points to the start of the register area in the call frame of the current function . The function prologue saves all registers used for argument passing into this area if the function uses variable arguments .


<s> bool AArch64PassConfig :: addPreISel ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnablePromoteConstant ) addPass ( createAArch64PromoteConstantPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createGlobalMergePass ( TM , 4095 ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createAArch64AddressTypePromotionPass ( ) ) ; return false ; } </s>


<s> static rtx choose_baseaddr ( HOST_WIDE_INT cfa_offset ) { const struct machine_function * m = cfun -> machine ; rtx base_reg = NULL ; HOST_WIDE_INT base_offset = 0 ; if ( m -> use_fast_prologue_epilogue ) { if ( m -> fs . fp_valid ) { base_reg = hard_frame_pointer_rtx ; base_offset = m -> fs . fp_offset - cfa_offset ; } else if ( m -> fs . drap_valid ) { base_reg = crtl -> drap_reg ; base_offset = 0 - cfa_offset ; } else if ( m -> fs . sp_valid ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; } } else { HOST_WIDE_INT toffset ; int len = 16 , tlen ; if ( m -> fs . sp_valid ) { base_reg = stack_pointer_rtx ; base_offset = m -> fs . sp_offset - cfa_offset ; len = choose_baseaddr_len ( STACK_POINTER_REGNUM , base_offset ) ; } if ( m -> fs . drap_valid ) { toffset = 0 - cfa_offset ; tlen = choose_baseaddr_len ( REGNO ( crtl -> drap_reg ) , toffset ) ; if ( tlen <= len ) { base_reg = crtl -> drap_reg ; base_offset = toffset ; len = tlen ; } } if ( m -> fs . fp_valid ) { toffset = m -> fs . fp_offset - cfa_offset ; tlen = choose_baseaddr_len ( HARD_FRAME_POINTER_REGNUM , toffset ) ; if ( tlen <= len ) { base_reg = hard_frame_pointer_rtx ; base_offset = toffset ; len = tlen ; } } } gcc_assert ( base_reg != NULL ) ; return plus_constant ( Pmode , base_reg , base_offset ) ; } </s>

Return an RTX that points to CFA_OFFSET within the stack frame . The valid base registers are taken from CFUN- > MACHINE- > FS .


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s>
static
bool
rs6000_declare_alias
(
struct
symtab_node
*
n
,
void
*
d
)
{
struct
declare_alias_data
*
data
=
(
struct
declare_alias_data
*
)
d
;
if
(
!
n
->
alias
||
n
->
weakref
)
return
false
;
if
(
lookup_attribute
(
"ifunc"
,
DECL_ATTRIBUTES
(
n
->
decl
)
)
)
return
false
;
TREE_ASM_WRITTEN
(
n
->
decl
)
=
true
;
const
char
*
name
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
n
->
decl
)
)
;
char
*
buffer
=
(
char
*
)
alloca
(
strlen
(
name
)
+
2
)
;
char
*
p
;
int
dollar_inside
=
0
;
strcpy
(
buffer
,
name
)
;
p
=
strchr
(
buffer
,
'$'
)
;
while
(
p
)
{
*
p
=
'_'
;
dollar_inside
++
;
p
=
strchr
(
p
+
1
,
'$'
)
;
}
if
(
TREE_PUBLIC
(
n
->
decl
)
)
{
if
(
!
RS6000_WEAK
||
!
DECL_WEAK
(
n
->
decl
)
)
{
if
(
dollar_inside
)
{
if
(
data
->
function_descriptor
)
fprintf
(
data
->
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
else
fprintf
(
data
->
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
}
if
(
data
->
function_descriptor
)
fputs
(
"\t.globl ."
,
data
->
file
)
;
else
fputs
(
"\t.globl "
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
else
if
(
DECL_WEAK
(
n
->
decl
)
&&
!
data
->
function_descriptor
)
ASM_WEAKEN_DECL
(
data
->
file
,
n
->
decl
,
name
,
)
;
}
else
{
if
(
dollar_inside
)
{
if
(
data
->
function_descriptor
)
fprintf
(
data
->
file
,
"\t.rename %s,\"%s\"\n"
,
buffer
,
name
)
;
else
fprintf
(
data
->
file
,
"\t.rename .%s,\".%s\"\n"
,
buffer
,
name
)
;
}
if
(
data
->
function_descriptor
)
fputs
(
"\t.lglobl ."
,
data
->
file
)
;
else
fputs
(
"\t.lglobl "
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
putc
(
'\n'
,
data
->
file
)
;
}
if
(
data
->
function_descriptor
)
fputs
(
"."
,
data
->
file
)
;
RS6000_OUTPUT_BASENAME
(
data
->
file
,
buffer
)
;
fputs
(
":\n"
,
data
->
file
)
;
return
false
;
}
</s>

Declare alias N. A helper function for for_node_and_aliases .


<s> static bool csky_tls_symbol_p ( rtx x ) { if ( ! TARGET_TLS ) return false ; if ( GET_CODE ( x ) != SYMBOL_REF ) return false ; return SYMBOL_REF_TLS_MODEL ( x ) != 0 ; } </s>

Return TRUE if X is a thread-local symbol .


<s> static tree ix86_make_bounds_constant ( HOST_WIDE_INT lb , HOST_WIDE_INT ub ) { tree low = lb ? build_minus_one_cst ( pointer_sized_int_node ) : build_zero_cst ( pointer_sized_int_node ) ; tree high = ub ? build_zero_cst ( pointer_sized_int_node ) : build_minus_one_cst ( pointer_sized_int_node ) ; gcc_assert ( ( lb == 0 && ub == - 1 ) || ( lb == - 1 && ub == 0 ) ) ; return build_complex ( NULL , low , high ) ; } </s>

Return constant used to statically initialize constant bounds . This function is used to create special bound values . For now only INIT bounds and NONE bounds are expected . More special values may be added later .


<s> unsigned Z80RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return ( FrameRegister == IX ) ? Z80 :: IX : Z80 :: IY ; } </s>


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ 0 ] + 1 ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = 1 ; i < nelt ; next ++ , i ++ ) { if ( next == 2 * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == 2 ) && ( d -> vmode != V2DImode ) ) return false ; else next = 0 ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ 0 ] ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vextv16qi ; break ; case V8QImode : gen = gen_neon_vextv8qi ; break ; case V4HImode : gen = gen_neon_vextv4hi ; break ; case V8HImode : gen = gen_neon_vextv8hi ; break ; case V2SImode : gen = gen_neon_vextv2si ; break ; case V4SImode : gen = gen_neon_vextv4si ; break ; case V2SFmode : gen = gen_neon_vextv2sf ; break ; case V4SFmode : gen = gen_neon_vextv4sf ; break ; case V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> void PPCTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , 0 ) ; switch ( Op . getOpcode ( ) ) { default : break ; case PPCISD :: LBRX : { if ( cast < VTSDNode > ( Op . getOperand ( 2 ) ) -> getVT ( ) == MVT :: i16 ) KnownZero = 0xFFFF0000 ; break ; } case ISD :: INTRINSIC_WO_CHAIN : { switch ( cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ) { default : break ; case Intrinsic :: ppc_altivec_vcmpbfp_p : case Intrinsic :: ppc_altivec_vcmpeqfp_p : case Intrinsic :: ppc_altivec_vcmpequb_p : case Intrinsic :: ppc_altivec_vcmpequh_p : case Intrinsic :: ppc_altivec_vcmpequw_p : case Intrinsic :: ppc_altivec_vcmpequd_p : case Intrinsic :: ppc_altivec_vcmpgefp_p : case Intrinsic :: ppc_altivec_vcmpgtfp_p : case Intrinsic :: ppc_altivec_vcmpgtsb_p : case Intrinsic :: ppc_altivec_vcmpgtsh_p : case Intrinsic :: ppc_altivec_vcmpgtsw_p : case Intrinsic :: ppc_altivec_vcmpgtsd_p : case Intrinsic :: ppc_altivec_vcmpgtub_p : case Intrinsic :: ppc_altivec_vcmpgtuh_p : case Intrinsic :: ppc_altivec_vcmpgtuw_p : case Intrinsic :: ppc_altivec_vcmpgtud_p : KnownZero = ~ 1U ; break ; } } } } </s>

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> unsigned SIRegisterInfo :: reservedPrivateSegmentBufferReg ( const MachineFunction & MF ) const { const SISubtarget & ST = MF . getSubtarget < SISubtarget > ( ) ; unsigned BaseIdx = alignDown ( ST . getMaxNumSGPRs ( MF ) , 4 ) - 4 ; unsigned BaseReg ( AMDGPU :: SGPR_32RegClass . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , AMDGPU :: sub0 , & AMDGPU :: SReg_128RegClass ) ; } </s>

Return the end register initially reserved for the scratch buffer in case spilling is needed .


<s> unsigned AMDGPUTargetMachine :: getAssumedAddrSpace ( const Value * V ) const { const auto * LD = dyn_cast < LoadInst > ( V ) ; if ( ! LD ) return AMDGPUAS :: UNKNOWN_ADDRESS_SPACE ; assert ( V -> getType ( ) -> isPointerTy ( ) && V -> getType ( ) -> getPointerAddressSpace ( ) == AMDGPUAS :: FLAT_ADDRESS ) ; const auto * Ptr = LD -> getPointerOperand ( ) ; if ( Ptr -> getType ( ) -> getPointerAddressSpace ( ) != AMDGPUAS :: CONSTANT_ADDRESS ) return AMDGPUAS :: UNKNOWN_ADDRESS_SPACE ; return AMDGPUAS :: GLOBAL_ADDRESS ; } </s>

If the specified generic pointer could be assumed as a pointer to a specific address space , return that address space .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> bool AMDGPURegBankCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const AMDGPULegalizerInfo * LI = static_cast < const AMDGPULegalizerInfo * > ( ST . getLegalizerInfo ( ) ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = IsOptNone ? nullptr : & getAnalysis < MachineDominatorTree > ( ) ; AMDGPURegBankCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , LI , KB , MDT ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ; } </s>


<s> Optional < MCFixupKind > MipsAsmBackend :: getFixupKind ( StringRef Name ) const { return StringSwitch < Optional < MCFixupKind >> ( Name ) . Case ( "R_MIPS_NONE" , FK_NONE ) . Case ( "R_MIPS_32" , FK_Data_4 ) . Case ( "R_MIPS_CALL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_HI16 ) . Case ( "R_MIPS_CALL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL_LO16 ) . Case ( "R_MIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_Mips_CALL16 ) . Case ( "R_MIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT ) . Case ( "R_MIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_PAGE ) . Case ( "R_MIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_OFST ) . Case ( "R_MIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_DISP ) . Case ( "R_MIPS_GOT_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_HI16 ) . Case ( "R_MIPS_GOT_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_GOT_LO16 ) . Case ( "R_MIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_Mips_GOTTPREL ) . Case ( "R_MIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_HI ) . Case ( "R_MIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_DTPREL_LO ) . Case ( "R_MIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_Mips_TLSGD ) . Case ( "R_MIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_Mips_TLSLDM ) . Case ( "R_MIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_HI ) . Case ( "R_MIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_Mips_TPREL_LO ) . Case ( "R_MICROMIPS_CALL16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_CALL16 ) . Case ( "R_MICROMIPS_GOT_DISP" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_DISP ) . Case ( "R_MICROMIPS_GOT_PAGE" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_PAGE ) . Case ( "R_MICROMIPS_GOT_OFST" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT_OFST ) . Case ( "R_MICROMIPS_GOT16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOT16 ) . Case ( "R_MICROMIPS_TLS_GOTTPREL" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_GOTTPREL ) . Case ( "R_MICROMIPS_TLS_DTPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_DTPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_DTPREL_LO16 ) . Case ( "R_MICROMIPS_TLS_GD" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_GD ) . Case ( "R_MICROMIPS_TLS_LDM" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_LDM ) . Case ( "R_MICROMIPS_TLS_TPREL_HI16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_HI16 ) . Case ( "R_MICROMIPS_TLS_TPREL_LO16" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_TLS_TPREL_LO16 ) . Case ( "R_MIPS_JALR" , ( MCFixupKind ) Mips :: fixup_Mips_JALR ) . Case ( "R_MICROMIPS_JALR" , ( MCFixupKind ) Mips :: fixup_MICROMIPS_JALR ) . Default ( MCAsmBackend :: getFixupKind ( Name ) ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> static HOST_WIDE_INT cris_preferred_minimum_alignment ( void ) { if ( ! TARGET_CONST_ALIGN ) return 8 ; if ( TARGET_ALIGN_BY_32 ) return 32 ; return 16 ; } </s>

Return the preferred minimum alignment for a static object .


"Pseudo opcode found in EmitInstruction()"

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
MachineBasicBlock
*
MSP430TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
if
(
Opc
==
MSP430
::
Shl8
||
Opc
==
MSP430
::
Shl16
||
Opc
==
MSP430
::
Sra8
||
Opc
==
MSP430
::
Sra16
||
Opc
==
MSP430
::
Srl8
||
Opc
==
MSP430
::
Srl16
)
return
EmitShiftInstr
(
MI
,
BB
)
;
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
Opc
==
MSP430
::
Select16
||
Opc
==
MSP430
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
MSP430
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
->
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
MSP430
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"Empty ranges shouldn't remain in the worklist"


<s> static tree tilegx_build_builtin_va_list ( void ) { tree f_args , f_skip , record , type_decl ; bool owp ; record = lang_hooks . types . make_type ( RECORD_TYPE ) ; type_decl = build_decl ( BUILTINS_LOCATION , TYPE_DECL , get_identifier ( "__va_list_tag" ) , record ) ; f_args = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__args" ) , ptr_type_node ) ; f_skip = build_decl ( BUILTINS_LOCATION , FIELD_DECL , get_identifier ( "__skip" ) , ptr_type_node ) ; DECL_FIELD_CONTEXT ( f_args ) = record ; DECL_FIELD_CONTEXT ( f_skip ) = record ; TREE_CHAIN ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_args ; TREE_CHAIN ( f_args ) = f_skip ; owp = warn_padded ; warn_padded = false ; layout_type ( record ) ; warn_padded = owp ; return record ; } </s>


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> bool avr_mem_memx_p ( rtx x ) { return ( MEM_P ( x ) && ADDR_SPACE_MEMX == MEM_ADDR_SPACE ( x ) ) ; } </s>

Return TRUE if X is a MEM rtx located in the 24-bit flash address space and FALSE , otherwise .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"MSP430 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> SDValue MipsTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; switch ( Opc ) { default : break ; case ISD :: SDIVREM : case ISD :: UDIVREM : return performDivRemCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SELECT : return performSELECTCombine ( N , DAG , DCI , Subtarget ) ; case MipsISD :: CMovFP_F : case MipsISD :: CMovFP_T : return performCMovFPCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AND : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: OR : return performORCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: ADD : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: AssertZext : return performAssertZextCombine ( N , DAG , DCI , Subtarget ) ; case ISD :: SHL : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

Mips Mips ISD::SDIVREM ISD::UDIVREM ISD::SELECT MipsISD::CMovFP_F MipsISD::CMovFP_T ISD::AND ISD::OR ISD::ADD ISD::AssertZext ISD::SHL


<s> const char * MipsTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case MipsISD :: JmpLink : return "MipsISD::JmpLink" ; case MipsISD :: Hi : return "MipsISD::Hi" ; case MipsISD :: Lo : return "MipsISD::Lo" ; case MipsISD :: GPRel : return "MipsISD::GPRel" ; case MipsISD :: Ret : return "MipsISD::Ret" ; case MipsISD :: CMov : return "MipsISD::CMov" ; case MipsISD :: SelectCC : return "MipsISD::SelectCC" ; case MipsISD :: FPSelectCC : return "MipsISD::FPSelectCC" ; case MipsISD :: FPBrcond : return "MipsISD::FPBrcond" ; case MipsISD :: FPCmp : return "MipsISD::FPCmp" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific

Mips Mips MipsISD::JmpLink "MipsISD::JmpLink" MipsISD::Hi "MipsISD::Hi" MipsISD::Lo "MipsISD::Lo" MipsISD::GPRel "MipsISD::GPRel" MipsISD::Ret "MipsISD::Ret" MipsISD::CMov "MipsISD::CMov" MipsISD::SelectCC "MipsISD::SelectCC" MipsISD::FPSelectCC "MipsISD::FPSelectCC" MipsISD::FPBrcond "MipsISD::FPBrcond" MipsISD::FPCmp "MipsISD::FPCmp"


<s> static int aarch64_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ATTRIBUTE_UNUSED ) { unsigned elements ; const cpu_vector_cost * costs = aarch64_tune_params . vec_costs ; bool fp = false ; if ( vectype != NULL ) fp = FLOAT_TYPE_P ( vectype ) ; switch ( type_of_cost ) { case scalar_stmt : return fp ? costs -> scalar_fp_stmt_cost : costs -> scalar_int_stmt_cost ; case scalar_load : return costs -> scalar_load_cost ; case scalar_store : return costs -> scalar_store_cost ; case vector_stmt : return fp ? costs -> vec_fp_stmt_cost : costs -> vec_int_stmt_cost ; case vector_load : return costs -> vec_align_load_cost ; case vector_store : return costs -> vec_store_cost ; case vec_to_scalar : return costs -> vec_to_scalar_cost ; case scalar_to_vec : return costs -> scalar_to_vec_cost ; case unaligned_load : return costs -> vec_unalign_load_cost ; case unaligned_store : return costs -> vec_unalign_store_cost ; case cond_branch_taken : return costs -> cond_taken_branch_cost ; case cond_branch_not_taken : return costs -> cond_not_taken_branch_cost ; case vec_perm : return costs -> vec_permute_cost ; case vec_promote_demote : return fp ? costs -> vec_fp_stmt_cost : costs -> vec_int_stmt_cost ; case vec_construct : elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; return elements / 2 + 1 ; default : gcc_unreachable ( ) ; } } </s>


<s> static bool has_immediate ( rtx_insn * insn ) { int num_imm_operand ; int num_imm32_operand ; int num_imm64_operand ; if ( insn ) return get_num_immediates ( insn , & num_imm_operand , & num_imm32_operand , & num_imm64_operand ) ; return false ; } </s>

This function indicates if an operand of an instruction is an immediate .


<s> int eligible_for_call_delay ( rtx_insn * trial ) { rtx pat ; if ( get_attr_in_branch_delay ( trial ) == IN_BRANCH_DELAY_FALSE ) return 0 ; if ( ( TARGET_GNU_TLS && HAVE_GNU_LD ) || ! TARGET_TLS ) return 1 ; pat = PATTERN ( trial ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == PLUS ) { rtx unspec = XEXP ( SET_SRC ( pat ) , 1 ) ; if ( GET_CODE ( unspec ) == UNSPEC && ( XINT ( unspec , 1 ) == UNSPEC_TLSGD || XINT ( unspec , 1 ) == UNSPEC_TLSLDM ) ) return 0 ; } return 1 ; } </s>

Return nonzero if TRIAL can go into the call delay slot .


<s> bool function_checker :: require_immediate_either_or ( unsigned int rel_argno , HOST_WIDE_INT value0 , HOST_WIDE_INT value1 ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; HOST_WIDE_INT actual ; if ( ! require_immediate ( argno , actual ) ) return false ; if ( actual != value0 && actual != value1 ) { report_neither_nor ( location , fndecl , argno , actual , 90 , 270 ) ; return false ; } return true ; } </s>

Check that argument REL_ARGNO is an integer constant expression that has the value VALUE0 or VALUE1 . REL_ARGNO counts from the end of the predication arguments .


<s>
bool
SparcAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
this
->
MF
=
&
MF
;
SetupMachineFunction
(
MF
)
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
O
<<
"\n\n"
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
EmitAlignment
(
MF
.
getAlignment
(
)
,
F
)
;
O
<<
"\t.globl\t"
<<
CurrentFnName
<<
'\n'
;
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
O
<<
"\t.type\t"
<<
CurrentFnName
<<
", #function\n"
;
O
<<
CurrentFnName
<<
":\n"
;
NumberForBB
.
clear
(
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
NumberForBB
[
I
->
getBasicBlock
(
)
]
=
BBNumber
++
;
}
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
!=
MF
.
begin
(
)
)
{
printBasicBlockLabel
(
I
,
true
,
true
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printInstruction
(
II
)
;
++
EmittedInsts
;
}
}
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Sparc
Sparc
"\n\n"
"\t.globl\t"
"\t.type\t"
", #function\n"
":\n"


<s> bool F2003fFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return false ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s> bool hasFP ( const MachineFunction & MF ) const { return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> static reg_class_t s390_preferred_reload_class ( rtx op , reg_class_t rclass ) { switch ( GET_CODE ( op ) ) { case CONST_DOUBLE : case CONST_INT : if ( reg_class_subset_p ( GENERAL_REGS , rclass ) && legitimate_reload_constant_p ( op ) ) return GENERAL_REGS ; else if ( reg_class_subset_p ( ADDR_REGS , rclass ) && legitimate_reload_constant_p ( op ) ) return ADDR_REGS ; else if ( reg_class_subset_p ( FP_REGS , rclass ) && legitimate_reload_fp_constant_p ( op ) ) return FP_REGS ; return NO_REGS ; case CONST : if ( TARGET_CPU_ZARCH && GET_CODE ( XEXP ( op , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 0 ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( op , 0 ) , 1 ) ) == CONST_INT ) { if ( flag_pic && reg_class_subset_p ( ADDR_REGS , rclass ) ) return ADDR_REGS ; else return NO_REGS ; } case LABEL_REF : case SYMBOL_REF : if ( ! legitimate_reload_constant_p ( op ) ) return NO_REGS ; case PLUS : if ( reg_class_subset_p ( ADDR_REGS , rclass ) ) return ADDR_REGS ; else return NO_REGS ; default : break ; } return rclass ; } </s>

Given an rtx OP being reloaded into a reg required to be in class CLASS , return the class of reg to actually use .


<s>
void
Mips16InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
;
if
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
&&
Mips
::
GPR32RegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
MoveR3216
;
else
if
(
Mips
::
GPR32RegClass
.
contains
(
DestReg
)
&&
Mips
::
CPU16RegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
Move32R16
;
else
if
(
(
SrcReg
==
Mips
::
HI0
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mfhi16
,
SrcReg
=
0
;
else
if
(
(
SrcReg
==
Mips
::
LO0
)
&&
(
Mips
::
CPU16RegsRegClass
.
contains
(
DestReg
)
)
)
Opc
=
Mips
::
Mflo16
,
SrcReg
=
0
;
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


"%s instructions aren't allowed in %s service routine"

"%s instructions aren't allowed in function with "

Establish appropriate back-end context for processing the function FNDECL . The argument might be NULL to indicate processing at top level , outside of any function scope .


<s> bool X86AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) { printSymbolOperand ( MO , O ) ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo , O ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO , O ) ; else printOperand ( MI , OpNo , O ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; printOperand ( MI , OpNo , O ) ; return false ; case 'P' : print_pcrel_imm ( MI , OpNo , O ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> static void h8300_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; cum -> nbytes += ( ( arg . promoted_size_in_bytes ( ) + UNITS_PER_WORD - 1 ) & - UNITS_PER_WORD ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> unsigned SIRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const SIMachineFunctionInfo * FuncInfo = MF . getInfo < SIMachineFunctionInfo > ( ) ; return FuncInfo -> getFrameOffsetReg ( ) ; } </s>


<s> bool HSAILInstrInfo :: isSafeToMoveRegClassDefs ( const TargetRegisterClass * RC ) const { return true ; } </s>

isSafeToMoveRegClassDefs - Return true if it 's safe to move a machine instruction that defines the specified register class .


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override { return createARM64ELFObjectWriter ( OS , OSABI , IsLittleEndian ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool Thumb1InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI ) const { MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( CSI . empty ( ) ) return false ; bool isVarArg = AFI -> getVarArgsRegSaveSize ( ) > 0 ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( ARM :: tPOP ) ) ; AddDefaultPred ( MIB ) ; bool NumRegs = 0 ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( Reg == ARM :: LR ) { if ( isVarArg ) continue ; Reg = ARM :: PC ; ( * MIB ) . setDesc ( get ( ARM :: tPOP_RET ) ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; ++ NumRegs ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool HexagonHardwareLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const { for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MRI -> use_nodbg_empty ( Reg ) ) continue ; typedef MachineRegisterInfo :: use_nodbg_iterator use_nodbg_iterator ; use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ; use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ; if ( llvm :: next ( I ) != End || ! I . getOperand ( ) . getParent ( ) -> isPHI ( ) ) return false ; MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ; for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( ! OPO . isReg ( ) || ! OPO . isDef ( ) ) continue ; unsigned OPReg = OPO . getReg ( ) ; use_nodbg_iterator nextJ ; for ( use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { nextJ = llvm :: next ( J ) ; MachineOperand & Use = J . getOperand ( ) ; MachineInstr * UseMI = Use . getParent ( ) ; if ( MI != UseMI ) return false ; } } DeadPhis . push_back ( OnePhi ) ; } return true ; } </s>

isDead - Returns true if this is a dead def kill slot .


<s>
bool
AMDGPUPerfHint
::
runOnFunction
(
Function
&
F
)
{
const
Module
&
M
=
*
F
.
getParent
(
)
;
DL
=
&
M
.
getDataLayout
(
)
;
if
(
F
.
hasFnAttribute
(
"amdgpu-wave-limiter"
)
&&
F
.
hasFnAttribute
(
"amdgpu-memory-bound"
)
)
return
false
;
const
AMDGPUPerfHintAnalysis
::
FuncInfo
*
Info
=
visit
(
F
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" MemInst cost: "
<<
Info
->
MemInstCost
<<
'\n'
<<
" IAMInst cost: "
<<
Info
->
IAMInstCost
<<
'\n'
<<
" LSMInst cost: "
<<
Info
->
LSMInstCost
<<
'\n'
<<
" TotalInst cost: "
<<
Info
->
InstCost
<<
'\n'
)
;
if
(
isMemBound
(
*
Info
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" is memory bound\n"
)
;
NumMemBound
++
;
F
.
addFnAttr
(
"amdgpu-memory-bound"
,
"true"
)
;
}
if
(
AMDGPU
::
isEntryFunctionCC
(
F
.
getCallingConv
(
)
)
&&
needLimitWave
(
*
Info
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
F
.
getName
(
)
<<
" needs limit wave\n"
)
;
NumLimitWave
++
;
F
.
addFnAttr
(
"amdgpu-wave-limiter"
,
"true"
)
;
}
return
true
;
}
</s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

AMDGPU
AMDGPU
"amdgpu-wave-limiter"
"amdgpu-memory-bound"
AMDGPU
" MemInst cost: "
" IAMInst cost: "
" LSMInst cost: "
" TotalInst cost: "
" is memory bound\n"
"amdgpu-memory-bound"
"true"
AMDGPU::isEntryFunctionCC
" needs limit wave\n"
"amdgpu-wave-limiter"
"true"


<s> SDValue MipsTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return LowerBRCOND ( Op , DAG ) ; case ISD :: ConstantPool : return LowerConstantPool ( Op , DAG ) ; case ISD :: DYNAMIC_STACKALLOC : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case ISD :: GlobalAddress : return LowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return LowerBlockAddress ( Op , DAG ) ; case ISD :: GlobalTLSAddress : return LowerGlobalTLSAddress ( Op , DAG ) ; case ISD :: JumpTable : return LowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return LowerSELECT ( Op , DAG ) ; case ISD :: SETCC : return LowerSETCC ( Op , DAG ) ; case ISD :: VASTART : return LowerVASTART ( Op , DAG ) ; case ISD :: FCOPYSIGN : return LowerFCOPYSIGN ( Op , DAG ) ; case ISD :: FABS : return LowerFABS ( Op , DAG ) ; case ISD :: FRAMEADDR : return LowerFRAMEADDR ( Op , DAG ) ; case ISD :: MEMBARRIER : return LowerMEMBARRIER ( Op , DAG ) ; case ISD :: ATOMIC_FENCE : return LowerATOMIC_FENCE ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

Mips Mips ISD::BRCOND ISD::ConstantPool ISD::DYNAMIC_STACKALLOC ISD::GlobalAddress ISD::BlockAddress ISD::GlobalTLSAddress ISD::JumpTable ISD::SELECT ISD::SETCC ISD::VASTART ISD::FCOPYSIGN ISD::FABS ISD::FRAMEADDR ISD::MEMBARRIER ISD::ATOMIC_FENCE


<s> static rtx mips_unspec_address_offset ( rtx base , rtx offset , enum mips_symbol_type symbol_type ) { base = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , base ) , UNSPEC_ADDRESS_FIRST + symbol_type ) ; if ( offset != const0_rtx ) base = gen_rtx_PLUS ( Pmode , base , offset ) ; return gen_rtx_CONST ( Pmode , base ) ; } </s>

Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE , then add CONST_INT OFFSET to the result .


<s> rtx expand ( function_expander & e ) const override { int unspec = ( e . type_suffix ( 1 ) . unsigned_p ? m_unspec_for_uint : m_unspec_for_sint ) ; machine_mode pred_mode = e . vector_mode ( 0 ) ; scalar_mode reg_mode = GET_MODE_INNER ( e . vector_mode ( 1 ) ) ; return e . use_exact_insn ( code_for_while ( unspec , reg_mode , pred_mode ) ) ; } </s>


"expression value must be representable in 32 bits"

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> rtx extract_mac_non_acc_rtx ( rtx_insn * insn ) { rtx exp = SET_SRC ( PATTERN ( insn ) ) ; switch ( get_attr_type ( insn ) ) { case TYPE_MAC : if ( REG_P ( XEXP ( exp , 0 ) ) ) return XEXP ( exp , 1 ) ; else return XEXP ( exp , 0 ) ; default : gcc_unreachable ( ) ; } } </s>

Extract the rtx representing non-accumulation operands of a MAC insn .


<s> static HOST_WIDE_INT aarch64_simd_vector_alignment ( const_tree type ) { if ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return GET_MODE_CLASS ( TYPE_MODE ( type ) ) == MODE_VECTOR_BOOL ? 16 : 128 ; HOST_WIDE_INT align = tree_to_shwi ( TYPE_SIZE ( type ) ) ; return MIN ( align , 128 ) ; } </s>

Implement target hook TARGET_VECTOR_ALIGNMENT . The AAPCS64 sets the maximum alignment of a vector to 128 bits .


<s> const MipsRegisterInfo & MipsInstrInfo :: getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .