<s> int rs6000_hard_regno_nregs ( int regno , enum machine_mode mode ) { if ( FP_REGNO_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FP_WORD - 1 ) / UNITS_PER_FP_WORD ; if ( TARGET_E500_DOUBLE && mode == DFmode ) return 1 ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_SPE_WORD - 1 ) / UNITS_PER_SPE_WORD ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + UNITS_PER_ALTIVEC_WORD - 1 ) / UNITS_PER_ALTIVEC_WORD ; return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; } </s>

Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE . This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers . For the SPE , GPRs are 64 bits but only 32 bits are visible in scalar instructions . The upper 32 bits are only available to the SIMD instructions . POWER and PowerPC GPRs hold 32 bits worth ; PowerPC64 GPRs and FPRs point register holds 64 bits worth .


<s> void SVEVecStackRegion :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , uint64_t & AddedSize , unsigned & Basereg , uint64_t Offset ) const { if ( RegionSize == 0 ) return ; if ( CSRs . size ( ) == 0 ) { AddedSize += this -> getRegionSize ( ) ; return ; } bool BPChanged = false ; if ( CSRs . size ( ) > 0 && ( ( AddedSize + Offset ) - Scale ) > ( uint64_t ) Scale * 255 ) { Basereg = adjustRegBySVE ( MF , MBB , MBBI , DL , Basereg , AddedSize + Offset , true ) ; AddedSize = 0 ; Offset = 0 ; BPChanged = true ; } SaveRestoreSVEFromPointer ( MF , MBB , MBBI , DL , AddedSize + Offset , Basereg , false ) ; if ( ! BPChanged ) AddedSize += this -> getRegionSize ( ) ; } </s>


"Unexpected register class in CSRsViaCopy!"

"Function should be nounwind in insertCopiesSplitCSR!"

Insert explicit copies in entry and exit blocks .


<s>
int
m32c_secondary_reload_class
(
int
rclass
,
enum
machine_mode
mode
,
rtx
x
)
{
int
cc
=
class_contents
[
rclass
]
[
0
]
;
fprintf
(
stderr
,
"\nsecondary reload class %s %s\n"
,
class_names
[
rclass
]
,
mode_name
[
mode
]
)
;
debug_rtx
(
x
)
;
if
(
mode
==
QImode
&&
GET_CODE
(
x
)
==
MEM
&&
(
cc
&
~
class_contents
[
R23_REGS
]
[
0
]
)
==
0
)
return
QI_REGS
;
if
(
classes_intersect
(
rclass
,
CR_REGS
)
&&
GET_CODE
(
x
)
==
REG
&&
REGNO
(
x
)
>=
SB_REGNO
&&
REGNO
(
x
)
<=
SP_REGNO
)
return
TARGET_A16
HI_REGS
:
A_REGS
;
return
NO_REGS
;
}
</s>

Implements SECONDARY_RELOAD_CLASS . QImode have to be reloaded in r0 or r1 , as those are the only real QImode registers . CR regs get reloaded through appropriately sized general or address registers .


<s> static inline bool s390_fpload_toreg ( rtx_insn * insn , unsigned int regno ) { rtx set ; enum attr_type flag = s390_safe_attr_type ( insn ) ; if ( flag != TYPE_FLOADSF && flag != TYPE_FLOADDF ) return false ; set = single_set ( insn ) ; if ( set == NULL_RTX ) return false ; if ( ! REG_P ( SET_DEST ( set ) ) || ! MEM_P ( SET_SRC ( set ) ) ) return false ; if ( REGNO ( SET_DEST ( set ) ) != regno ) return false ; return true ; } </s>

Return true if INSN is a fp load insn writing register REGNO .


<s> static void replace_swapped_aligned_load ( swap_web_entry * insn_entry , rtx swap_insn ) { unsigned uid = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid ] . is_swap && ! insn_entry [ uid ] . is_load ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( swap_insn ) ; df_ref use = DF_INSN_INFO_USES ( insn_info ) ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; gcc_assert ( def_link && ! def_link -> next ) ; gcc_assert ( def_link && def_link -> ref && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) && ! def_link -> next ) ; rtx_insn * def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_load && insn_entry [ uid2 ] . is_swap ) ; rtx body = PATTERN ( def_insn ) ; gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) && MEM_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , 0 ) ; enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_SRC ( new_body ) ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( def_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( def_insn ) ; remove_insn ( def_insn ) ; def_insn -> set_deleted ( ) ; mark_swaps_for_removal ( insn_entry , uid ) ; replace_swap_with_copy ( insn_entry , uid ) ; } </s>

Given that SWAP_INSN represents a swap of an aligned load-with-swap , replace the load with an aligned load ( without swap ) and replace the swap with a copy insn .


"function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, "

Advance the argument of type TYPE and mode MODE to the next argument position in CUM .


"M68k pseudo instruction expansion pass"

getPassName - Return a nice clean name for a pass .


<s> unsigned M88kMCAsmBackend :: getNumFixupKinds ( ) const { return M88k :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
bool
X86CallLowering
::
lowerReturn
(
MachineIRBuilder
&
MIRBuilder
,
const
Value
*
Val
,
unsigned
VReg
)
const
{
assert
(
(
(
Val
&&
VReg
)
||
(
!
Val
&&
!
VReg
)
)
&&
"Return value without a vreg"
)
;
auto
MIB
=
MIRBuilder
.
buildInstrNoInsert
(
X86
::
RET
)
.
addImm
(
0
)
;
if
(
VReg
)
{
MachineFunction
&
MF
=
MIRBuilder
.
getMF
(
)
;
MachineRegisterInfo
&
MRI
=
MF
.
getRegInfo
(
)
;
auto
&
DL
=
MF
.
getDataLayout
(
)
;
const
Function
&
F
=
*
MF
.
getFunction
(
)
;
ArgInfo
OrigArg
{
VReg
,
Val
->
getType
(
)
}
;
setArgFlags
(
OrigArg
,
AttributeList
::
ReturnIndex
,
DL
,
F
)
;
SmallVector
<
ArgInfo
,
8
>
SplitArgs
;
splitToValueTypes
(
OrigArg
,
SplitArgs
,
DL
,
MRI
,
[
&
]
(
unsigned
Reg
,
uint64_t
Offset
)
{
MIRBuilder
.
buildExtract
(
Reg
,
VReg
,
Offset
)
;
}
)
;
FuncReturnHandler
Handler
(
MIRBuilder
,
MRI
,
MIB
,
RetCC_X86
)
;
if
(
!
handleAssignments
(
MIRBuilder
,
SplitArgs
,
Handler
)
)
return
false
;
}
MIRBuilder
.
insertInstr
(
MIB
)
;
return
true
;
}
</s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> void nds32_expand_epilogue ( bool sibcall_p ) { int sp_adjust ; int en4_const ; rtx Rb , Re ; rtx sp_adjust_insn ; nds32_compute_stack_frame ( ) ; emit_insn ( gen_blockage ( ) ) ; if ( cfun -> machine -> naked_p ) { if ( cfun -> machine -> va_args_size != 0 ) { sp_adjust = cfun -> machine -> va_args_size + cfun -> machine -> va_args_area_padding_bytes ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; return ; } if ( frame_pointer_needed ) { sp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - 1 * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = nds32_force_addi_stack_int ( sp_adjust ) ; if ( sp_adjust ) { sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } } Rb = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_first_gpr_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_last_gpr_regno ) ; en4_const = 0 ; if ( cfun -> machine -> fp_size ) en4_const += 8 ; if ( cfun -> machine -> gp_size ) en4_const += 4 ; if ( cfun -> machine -> lp_size ) en4_const += 2 ; if ( ! ( REGNO ( Rb ) == SP_REGNUM && REGNO ( Re ) == SP_REGNUM && en4_const == 0 ) ) { nds32_emit_stack_pop_multiple ( Rb , Re , GEN_INT ( en4_const ) ) ; } if ( cfun -> machine -> va_args_size != 0 ) { sp_adjust = cfun -> machine -> va_args_size + cfun -> machine -> va_args_area_padding_bytes ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } if ( ! sibcall_p ) emit_jump_insn ( gen_return_internal ( ) ) ; } </s>

Function for normal multiple pop epilogue .


<s> const MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const override { return DataSection ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


<s> static rtx visium_function_arg ( cumulative_args_t pcum_v , const function_arg_info & arg ) { int size ; CUMULATIVE_ARGS * ca = get_cumulative_args ( pcum_v ) ; size = ( GET_MODE_SIZE ( arg . mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; if ( arg . end_marker_p ( ) ) return GEN_INT ( 0 ) ; if ( TARGET_FPU && ( ( GET_MODE_CLASS ( arg . mode ) == MODE_FLOAT && GET_MODE_SIZE ( arg . mode ) <= UNITS_PER_HWFPVALUE ) || ( GET_MODE_CLASS ( arg . mode ) == MODE_COMPLEX_FLOAT && GET_MODE_SIZE ( arg . mode ) <= UNITS_PER_HWFPVALUE * 2 ) ) ) { if ( ca -> frcount + size <= MAX_ARGS_IN_FP_REGISTERS ) return gen_rtx_REG ( arg . mode , FP_ARG_FIRST + ca -> frcount ) ; else return NULL_RTX ; } if ( ca -> grcount + size <= MAX_ARGS_IN_GP_REGISTERS ) return gen_rtx_REG ( arg . mode , ca -> grcount + GP_ARG_FIRST ) ; return NULL_RTX ; } </s>

Define how arguments are passed . A range of general registers and floating registers is available for passing arguments . When the class of registers which an argument would normally use is exhausted , that argument , is passed in the overflow region of the stack . No argument is split between registers and stack . Arguments of type float or _Complex float go in FP registers if FP hardware is available . If there is no FP hardware , arguments of type float go in general registers . All other arguments are passed in general registers .


<s>
bool
AArch64TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
VectorType
*
VecTy
=
SVI
->
getType
(
)
;
assert
(
VecTy
->
getVectorNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
unsigned
NumSubElts
=
VecTy
->
getVectorNumElements
(
)
/
Factor
;
Type
*
EltTy
=
VecTy
->
getVectorElementType
(
)
;
VectorType
*
SubVecTy
=
VectorType
::
get
(
EltTy
,
NumSubElts
)
;
const
DataLayout
&
DL
=
SI
->
getModule
(
)
->
getDataLayout
(
)
;
unsigned
SubVecSize
=
DL
.
getTypeAllocSizeInBits
(
SubVecTy
)
;
if
(
!
Subtarget
->
hasNEON
(
)
||
(
SubVecSize
!=
64
&&
SubVecSize
!=
128
)
)
return
false
;
Value
*
Op0
=
SVI
->
getOperand
(
0
)
;
Value
*
Op1
=
SVI
->
getOperand
(
1
)
;
IRBuilder
<
>
Builder
(
SI
)
;
if
(
EltTy
->
isPointerTy
(
)
)
{
Type
*
IntTy
=
DL
.
getIntPtrType
(
EltTy
)
;
unsigned
NumOpElts
=
dyn_cast
<
VectorType
>
(
Op0
->
getType
(
)
)
->
getVectorNumElements
(
)
;
Type
*
IntVecTy
=
VectorType
::
get
(
IntTy
,
NumOpElts
)
;
Op0
=
Builder
.
CreatePtrToInt
(
Op0
,
IntVecTy
)
;
Op1
=
Builder
.
CreatePtrToInt
(
Op1
,
IntVecTy
)
;
SubVecTy
=
VectorType
::
get
(
IntTy
,
NumSubElts
)
;
}
Type
*
PtrTy
=
SubVecTy
->
getPointerTo
(
SI
->
getPointerAddressSpace
(
)
)
;
Type
*
Tys
[
2
]
=
{
SubVecTy
,
PtrTy
}
;
static
const
Intrinsic
::
ID
StoreInts
[
3
]
=
{
Intrinsic
::
aarch64_neon_st2
,
Intrinsic
::
aarch64_neon_st3
,
Intrinsic
::
aarch64_neon_st4
}
;
Function
*
StNFunc
=
Intrinsic
::
getDeclaration
(
SI
->
getModule
(
)
,
StoreInts
[
Factor
2
]
,
Tys
)
;
SmallVector
<
Value
*
,
5
>
Ops
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Ops
.
push_back
(
Builder
.
CreateShuffleVector
(
Op0
,
Op1
,
getSequentialMask
(
Builder
,
NumSubElts
*
i
,
NumSubElts
)
)
)
;
Ops
.
push_back
(
Builder
.
CreateBitCast
(
SI
->
getPointerOperand
(
)
,
PtrTy
)
)
;
Builder
.
CreateCall
(
StNFunc
,
Ops
)
;
return
true
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> enum ix86_fpcmp_strategy ix86_fp_comparison_strategy ( enum rtx_code ) { if ( TARGET_CMOVE ) return IX86_FPCMP_COMI ; if ( TARGET_SAHF && ( TARGET_USE_SAHF || optimize_insn_for_size_p ( ) ) ) return IX86_FPCMP_SAHF ; return IX86_FPCMP_ARITH ; } </s>

Return strategy to use for floating-point . We assume that fcomi is always preferrable where available , since that is also true when looking at size ( 2 bytes , vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test ) .


<s> const char * TVMTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( static_cast < TVMISD :: NodeType > ( Opcode ) ) { case TVMISD :: FIRST_NUMBER : break ; case TVMISD :: NODE : \ return "TVMISD::" # NODE ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

TVM TVM TVMISD::NodeType TVMISD::FIRST_NUMBER TVMISD::NODE "TVMISD::"


<s> const char * loongarch_output_division ( const char * division , rtx * operands ) { const char * s ; s = division ; if ( loongarch_check_zero_div_p ( ) ) { output_asm_insn ( s , operands ) ; s = "bne\t%2,%.,1f\n\tbreak\t7\n1:" ; } return s ; } </s>

Return the assembly code for DIV . { W/D } instruction DIVISION , which has the operands given by OPERANDS . Add in a divide-by-zero check if needed .


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> const char * m68k_cpp_cpu_ident ( const char * prefix ) { if ( ! m68k_cpu_entry ) return NULL ; return concat ( "__m" , prefix , "_cpu_" , m68k_cpu_entry -> name , NULL ) ; } </s>

Generate a macro of the form __mPREFIX_cpu_NAME , where PREFIX is the given argument and NAME is the argument passed to -mcpu . Return NULL if -mcpu was not passed .


<s> void ix86_split_mmx_pack ( rtx operands [ ] , enum rtx_code code ) { rtx op0 = operands [ 0 ] ; rtx op1 = operands [ 1 ] ; rtx op2 = operands [ 2 ] ; machine_mode dmode = GET_MODE ( op0 ) ; machine_mode smode = GET_MODE ( op1 ) ; machine_mode inner_dmode = GET_MODE_INNER ( dmode ) ; machine_mode inner_smode = GET_MODE_INNER ( smode ) ; int nunits = 16 / GET_MODE_SIZE ( inner_dmode ) ; machine_mode sse_dmode = mode_for_vector ( GET_MODE_INNER ( dmode ) , nunits ) . require ( ) ; machine_mode sse_half_dmode = mode_for_vector ( GET_MODE_INNER ( dmode ) , nunits / 2 ) . require ( ) ; nunits = 16 / GET_MODE_SIZE ( inner_smode ) ; machine_mode sse_smode = mode_for_vector ( GET_MODE_INNER ( smode ) , nunits ) . require ( ) ; rtx dest = lowpart_subreg ( sse_dmode , op0 , GET_MODE ( op0 ) ) ; op1 = lowpart_subreg ( sse_smode , op1 , GET_MODE ( op1 ) ) ; op2 = lowpart_subreg ( sse_smode , op2 , GET_MODE ( op2 ) ) ; op1 = gen_rtx_fmt_e ( code , sse_half_dmode , op1 ) ; op2 = gen_rtx_fmt_e ( code , sse_half_dmode , op2 ) ; rtx insn = gen_rtx_SET ( dest , gen_rtx_VEC_CONCAT ( sse_dmode , op1 , op2 ) ) ; emit_insn ( insn ) ; ix86_move_vector_high_sse_to_mmx ( op0 ) ; } </s>

Split MMX pack with signed/unsigned saturation with SSE/SSE2 .


<s>
StringRef
CSKYMCExpr
::
getVariantKindName
(
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Invalid ELF symbol kind"
)
;
case
VK_CSKY_ADDR
:
return
""
;
case
VK_CSKY_PCREL
:
return
""
;
case
VK_CSKY_GOT
:
return
"@GOT"
;
case
VK_CSKY_GOTPC
:
return
"@GOTPC"
;
case
VK_CSKY_GOTOFF
:
return
"@GOTOFF"
;
case
VK_CSKY_PLT
:
return
"@PLT"
;
case
VK_CSKY_TPOFF
:
return
"@TPOFF"
;
case
VK_CSKY_TLSGD
:
return
"@TLSGD"
;
}
}
</s>

Convert the variant kind into an ELF-appropriate modifier ( e.g .

CSKY
CSKY
"Invalid ELF symbol kind"
CSKY
""
CSKY
""
CSKY
"@GOT"
CSKY
"@GOTPC"
CSKY
"@GOTOFF"
CSKY
"@PLT"
CSKY
"@TPOFF"
CSKY
"@TLSGD"


<s>
void
ConvergingVLIWScheduler
::
releaseBottomNode
(
SUnit
*
SU
)
{
if
(
SU
->
isScheduled
)
return
;
assert
(
SU
->
getInstr
(
)
&&
"Scheduled SUnit must have instr"
)
;
for
(
SUnit
::
succ_iterator
I
=
SU
->
Succs
.
begin
(
)
,
E
=
SU
->
Succs
.
end
(
)
;
I
!=
E
;
++
I
)
{
unsigned
SuccReadyCycle
=
I
->
getSUnit
(
)
->
BotReadyCycle
;
unsigned
MinLatency
=
I
->
getMinLatency
(
)
;
Bot
.
MaxMinLatency
=
std
::
max
(
MinLatency
,
Bot
.
MaxMinLatency
)
;
if
(
SU
->
BotReadyCycle
<
SuccReadyCycle
+
MinLatency
)
SU
->
BotReadyCycle
=
SuccReadyCycle
+
MinLatency
;
}
Bot
.
releaseNode
(
SU
,
SU
->
BotReadyCycle
)
;
}
</s>

Currently only scheduling top-down , so this method is empty .

Hexagon
"Scheduled SUnit must have instr"


<s> MCGNode * getCaller ( ) const { return Caller ; } </s>

Helper to get the caller ( the parent function ) .


<s> MVT getScalarShiftAmountTy ( const DataLayout & DL , EVT ) const override { return MVT :: i32 ; } </s>

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> uint32_t getSize ( ) { return BTFTypeBase :: getSize ( ) + BTF :: BTFDataSecVarSize * Vars . size ( ) ; } </s>

Return the number of bytes in the encoding of this instruction , or zero if the encoding size can not be known from the opcode .


<s> bool PPCFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MFI . getStackSize ( ) ) && needsFP ( MF ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Cpu0 Del Useless jmp"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void sh_va_start ( tree valist , rtx nextarg ) { tree f_next_o , f_next_o_limit , f_next_fp , f_next_fp_limit , f_next_stack ; tree next_o , next_o_limit , next_fp , next_fp_limit , next_stack ; tree t , u ; int nfp , nint ; if ( TARGET_SH5 ) { expand_builtin_saveregs ( ) ; std_expand_builtin_va_start ( valist , nextarg ) ; return ; } if ( ( ! TARGET_SH2E && ! TARGET_SH4 ) || TARGET_HITACHI || sh_cfun_attr_renesas_p ( ) ) { std_expand_builtin_va_start ( valist , nextarg ) ; return ; } f_next_o = TYPE_FIELDS ( va_list_type_node ) ; f_next_o_limit = DECL_CHAIN ( f_next_o ) ; f_next_fp = DECL_CHAIN ( f_next_o_limit ) ; f_next_fp_limit = DECL_CHAIN ( f_next_fp ) ; f_next_stack = DECL_CHAIN ( f_next_fp_limit ) ; next_o = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_o ) , valist , f_next_o , NULL_TREE ) ; next_o_limit = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_o_limit ) , valist , f_next_o_limit , NULL_TREE ) ; next_fp = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_fp ) , valist , f_next_fp , NULL_TREE ) ; next_fp_limit = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_fp_limit ) , valist , f_next_fp_limit , NULL_TREE ) ; next_stack = build3 ( COMPONENT_REF , TREE_TYPE ( f_next_stack ) , valist , f_next_stack , NULL_TREE ) ; u = make_tree ( sizetype , expand_builtin_saveregs ( ) ) ; u = fold_convert ( ptr_type_node , u ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_fp , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; nfp = crtl -> args . info . arg_count [ SH_ARG_FLOAT ] ; if ( nfp < 8 ) nfp = 8 - nfp ; else nfp = 0 ; u = fold_build_pointer_plus_hwi ( u , UNITS_PER_WORD * nfp ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_fp_limit , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_o , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; nint = crtl -> args . info . arg_count [ SH_ARG_INT ] ; if ( nint < 4 ) nint = 4 - nint ; else nint = 0 ; u = fold_build_pointer_plus_hwi ( u , UNITS_PER_WORD * nint ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_o_limit , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = make_tree ( ptr_type_node , nextarg ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , next_stack , u ) ; TREE_SIDE_EFFECTS ( t ) = 1 ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } </s>

Implement ` va_start ' for varargs and stdarg .


<s>
bool
X86CmovConverterPass
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
if
(
!
EnableCmovConverter
)
return
false
;
DEBUG
(
dbgs
(
)
<<
"********** "
<<
getPassName
(
)
<<
" : "
<<
MF
.
getName
(
)
<<
"**********\n"
)
;
bool
Changed
=
false
;
MachineLoopInfo
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
const
TargetSubtargetInfo
&
STI
=
MF
.
getSubtarget
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
STI
.
getInstrInfo
(
)
;
TSchedModel
.
init
(
STI
.
getSchedModel
(
)
,
&
STI
,
TII
)
;
for
(
MachineBasicBlock
&
MBB
:
MF
)
{
MachineLoop
*
CurrLoop
=
MLI
.
getLoopFor
(
&
MBB
)
;
if
(
!
CurrLoop
||
CurrLoop
->
getHeader
(
)
!=
&
MBB
||
!
CurrLoop
->
getSubLoops
(
)
.
empty
(
)
)
continue
;
CmovGroups
CmovInstGroups
;
if
(
!
collectCmovCandidates
(
CurrLoop
,
CmovInstGroups
)
)
continue
;
if
(
!
checkForProfitableCmovCandidates
(
CurrLoop
,
CmovInstGroups
)
)
continue
;
Changed
=
true
;
for
(
auto
&
Group
:
CmovInstGroups
)
convertCmovInstsToBranches
(
Group
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .


<s> MVT M680x0TargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT Ty ) const { if ( Ty . isSimple ( ) ) { return Ty . getSimpleVT ( ) ; } return MVT :: getIntegerVT ( 8 * DL . getPointerSize ( 0 ) ) ; } </s>


<s> static Mfix * create_fix_barrier ( Mfix * fix , HOST_WIDE_INT max_address ) { HOST_WIDE_INT count = 0 ; rtx barrier ; rtx from = fix -> insn ; rtx selected = from ; int selected_cost ; HOST_WIDE_INT selected_address ; Mfix * new_fix ; HOST_WIDE_INT max_count = max_address - fix -> address ; rtx label = gen_label_rtx ( ) ; selected_cost = arm_barrier_cost ( from ) ; selected_address = fix -> address ; while ( from && count < max_count ) { rtx tmp ; int new_cost ; gcc_assert ( GET_CODE ( from ) != BARRIER ) ; count += get_attr_length ( from ) ; tmp = is_jump_table ( from ) ; if ( tmp != NULL ) { count += get_jump_table_size ( tmp ) ; new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && new_cost <= selected_cost ) { selected = tmp ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( tmp ) ; continue ; } new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && new_cost <= selected_cost ) { selected = from ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( from ) ; } from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; new_fix -> next = fix -> next ; fix -> next = new_fix ; return new_fix ; } </s>

Find the best place in the insn stream in the range ( FIX- > address , MAX_ADDRESS ) to forcibly insert a minipool barrier . Create the barrier by inserting a jump and add a new fix entry for it .


"insertBranch must not be told to insert a fallthrough"

"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> void HexagonPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableExpandCondsets ) insertPass ( & RegisterCoalescerID , & HexagonExpandCondsetsID ) ; if ( ! DisableStoreWidening ) addPass ( createHexagonStoreWidening ( ) ) ; if ( ! DisableHardwareLoops ) addPass ( createHexagonHardwareLoops ( ) ) ; } if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default ) addPass ( & MachinePipelinerID ) ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
SDValue
TOYTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
MF
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_TOY
)
;
SDValue
Flag
;
if
(
MF
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
MF
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
TOYISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getRegister
(
TOY
::
LR
,
MVT
::
i32
)
,
Flag
)
;
return
DAG
.
getNode
(
TOYISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
DAG
.
getRegister
(
TOY
::
LR
,
MVT
::
i32
)
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> virtual const TargetRegisterClass * getCFGStructurizerRegClass ( MVT VT ) const { assert ( ! "Unimplemented" ) ; return nullptr ; } </s>

get the register class of the specified type to use in the CFGStructurizer


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = 0 ; if ( GET_CODE ( addr ) == CONST ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( addr , 0 ) , 0 ) ) ; } else if ( GET_CODE ( addr ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( addr ) ; return tls_kind ; } </s>

Return the TLS model to use for SYMBOL .


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
TargetInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrMode3
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrModeT1_s
:
{
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
}
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
break
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> void SPURegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( createSIMemoryLegalizerPass ( ) ) ; addPass ( createSIInsertWaitcntsPass ( ) ) ; addPass ( createSIModeRegisterPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & SIInsertHardClausesID ) ; addPass ( & SILateBranchLoweringPassID ) ; if ( isPassEnabled ( EnableSetWavePriority , CodeGenOpt :: Less ) ) addPass ( createAMDGPUSetWavePriorityPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & SIPreEmitPeepholeID ) ; addPass ( & PostRAHazardRecognizerID ) ; addPass ( & BranchRelaxationPassID ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static void arm_option_restore ( struct gcc_options * , struct gcc_options * , struct cl_target_option * ptr ) { arm_configure_build_target ( & arm_active_target , ptr , false ) ; arm_option_reconfigure_globals ( ) ; } </s>


<s> static void arm_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { if ( mode == SImode ) gcc_assert ( ! TARGET_IDIV ) ; scalar_int_mode libval_mode = smallest_int_mode_for_size ( 2 * GET_MODE_BITSIZE ( mode ) ) ; rtx libval = emit_library_call_value ( libfunc , NULL_RTX , LCT_CONST , libval_mode , op0 , mode , op1 , mode ) ; rtx quotient = simplify_gen_subreg ( mode , libval , libval_mode , 0 ) ; rtx remainder = simplify_gen_subreg ( mode , libval , libval_mode , GET_MODE_SIZE ( mode ) ) ; gcc_assert ( quotient ) ; gcc_assert ( remainder ) ; * quot_p = quotient ; * rem_p = remainder ; } </s>

Generate call to __aeabi_ [ mode ] divmod ( op0 , op1 ) .


<s>
SDValue
XCoreTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_XCore
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
RetOps
.
push_back
(
DAG
.
getConstant
(
0
,
MVT
::
i32
)
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
XCoreISD
::
RETSP
,
dl
,
MVT
::
Other
,
&
RetOps
[
0
]
,
RetOps
.
size
(
)
)
;
}
</s>


<s>
void
CSKYAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
if
(
Kind
>=
FirstLiteralRelocationKind
)
return
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Kind
)
;
if
(
!
Value
)
return
;
Value
=
adjustFixupValue
(
Fixup
,
Value
,
Ctx
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
alignTo
(
Info
.
TargetSize
+
Info
.
TargetOffset
,
8
)
/
8
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
bool
IsLittleEndian
=
(
Endian
==
support
::
little
)
;
if
(
IsLittleEndian
&&
(
NumBytes
==
4
)
)
{
Data
[
Offset
+
0
]
|=
uint8_t
(
(
Value
>>
16
)
&
0xff
)
;
Data
[
Offset
+
1
]
|=
uint8_t
(
(
Value
>>
24
)
&
0xff
)
;
Data
[
Offset
+
2
]
|=
uint8_t
(
Value
&
0xff
)
;
Data
[
Offset
+
3
]
|=
uint8_t
(
(
Value
>>
8
)
&
0xff
)
;
}
else
{
for
(
unsigned
I
=
0
;
I
!=
NumBytes
;
I
++
)
{
unsigned
Idx
=
IsLittleEndian
I
:
(
NumBytes
1
I
)
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
I
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
WebAssemblyAsmPrinter
::
emitConstantPool
(
)
{
assert
(
MF
->
getConstantPool
(
)
->
getConstants
(
)
.
empty
(
)
&&
"WebAssembly disables constant pools"
)
;
}
</s>

Print to the current output stream assembly representations of the constants in the constant pool MCP .

WebAssembly
WebAssembly
"WebAssembly disables constant pools"


<s> static rtx push ( int rn ) { rtx x ; if ( rn == FPUL_REG ) x = gen_push_fpul ( ) ; else if ( rn == FPSCR_REG ) x = gen_push_fpscr ( ) ; else if ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P ( rn ) ) { if ( FP_REGISTER_P ( rn ) && ( rn - FIRST_FP_REG ) & 1 ) return NULL_RTX ; x = gen_push_4 ( gen_rtx_REG ( DFmode , rn ) ) ; } else if ( TARGET_SH2E && FP_REGISTER_P ( rn ) ) x = gen_push_e ( gen_rtx_REG ( SFmode , rn ) ) ; else x = gen_push ( gen_rtx_REG ( SImode , rn ) ) ; x = frame_insn ( x ) ; REG_NOTES ( x ) = gen_rtx_EXPR_LIST ( REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) , 0 ) ; return x ; } </s>

Output RTL to push register RN onto the stack .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( AFI -> getGlobalBaseReg ( ) == 0 ) return false ; const ARMTargetMachine * TM = static_cast < const ARMTargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; GlobalValue * GV = new GlobalVariable ( Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , 0 , "_GLOBAL_OFFSET_TABLE_" ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; ARMConstantPoolValue * CPV = ARMConstantPoolConstant :: Create ( GV , Id ) ; unsigned Align = TM -> getTargetData ( ) -> getPrefTypeAlignment ( GV -> getType ( ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < ARMSubtarget > ( ) . isThumb2 ( ) ? ARM :: t2LDRpci : ARM :: LDRcp ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == ARM :: LDRcp ) MIB . addImm ( 0 ) ; AddDefaultPred ( MIB ) ; return true ; } </s>

ARM ARM ARM 0 ARM ARM 0 "_GLOBAL_OFFSET_TABLE_" ARM ARM ARM ARM::t2LDRpci ARM::LDRcp ARM::LDRcp 0


<s> bool SITypeRewriter :: runOnFunction ( Function & F ) { if ( ! AMDGPU :: isShader ( F . getCallingConv ( ) ) ) return false ; visit ( F ) ; visit ( F ) ; return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> static bool ia64_expand_vecint_compare ( enum rtx_code code , machine_mode mode , rtx dest , rtx op0 , rtx op1 ) { bool negate = false ; rtx x ; switch ( code ) { case EQ : case GT : case GTU : break ; case NE : case LE : case LEU : code = reverse_condition ( code ) ; negate = true ; break ; case GE : case GEU : code = reverse_condition ( code ) ; negate = true ; case LT : case LTU : code = swap_condition ( code ) ; x = op0 , op0 = op1 , op1 = x ; break ; default : gcc_unreachable ( ) ; } if ( code == GTU ) { switch ( mode ) { case V2SImode : { rtx t1 , t2 , mask ; mask = GEN_INT ( 0x80000000 ) ; mask = gen_rtx_CONST_VECTOR ( V2SImode , gen_rtvec ( 2 , mask , mask ) ) ; mask = force_reg ( mode , mask ) ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv2si3 ( t1 , op0 , mask ) ) ; t2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_subv2si3 ( t2 , op1 , mask ) ) ; op0 = t1 ; op1 = t2 ; code = GT ; } break ; case V8QImode : case V4HImode : x = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , x , gen_rtx_US_MINUS ( mode , op0 , op1 ) ) ) ; code = EQ ; op0 = x ; op1 = CONST0_RTX ( mode ) ; negate = ! negate ; break ; default : gcc_unreachable ( ) ; } } x = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; return negate ; } </s>

Generate an integral vector comparison . Return true if the condition has been reversed , and so the sense of the comparison should be inverted .


Constant pools are per function only when PC relative literal loads are true or we are in the large memory model .


<s>
void
XCoreAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
SmallString
<
128
>
Str
;
raw_svector_ostream
O
(
Str
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
XCore
::
DBG_VALUE
:
{
if
(
isVerbose
(
)
&&
OutStreamer
.
hasRawTextSupport
(
)
)
{
SmallString
<
128
>
TmpStr
;
raw_svector_ostream
OS
(
TmpStr
)
;
PrintDebugValueComment
(
MI
,
OS
)
;
OutStreamer
.
EmitRawText
(
StringRef
(
OS
.
str
(
)
)
)
;
}
return
;
}
case
XCore
::
ADD_2rus
:
if
(
MI
->
getOperand
(
2
)
.
getImm
(
)
==
0
)
{
O
<<
"\tmov "
<<
XCoreInstPrinter
::
getRegisterName
(
MI
->
getOperand
(
0
)
.
getReg
(
)
)
<<
", "
<<
XCoreInstPrinter
::
getRegisterName
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
return
;
}
break
;
case
XCore
::
BR_JT
:
case
XCore
::
BR_JT32
:
O
<<
"\tbru "
<<
XCoreInstPrinter
::
getRegisterName
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
<<
'\n'
;
if
(
MI
->
getOpcode
(
)
==
XCore
::
BR_JT
)
printInlineJT
(
MI
,
0
,
O
)
;
else
printInlineJT32
(
MI
,
0
,
O
)
;
O
<<
'\n'
;
OutStreamer
.
EmitRawText
(
O
.
str
(
)
)
;
return
;
}
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
OutStreamer
.
EmitInstruction
(
TmpInst
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void save_restore_target_globals ( tree new_tree ) { if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else { TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } arm_option_params_internal ( ) ; } </s>

Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE .


<s> bool SIRegisterInfo :: shouldCoalesce ( MachineInstr * MI , const TargetRegisterClass * SrcRC , unsigned SubReg , const TargetRegisterClass * DstRC , unsigned DstSubReg , const TargetRegisterClass * NewRC , LiveIntervals & LIS ) const { unsigned SrcSize = getRegSizeInBits ( * SrcRC ) ; unsigned DstSize = getRegSizeInBits ( * DstRC ) ; unsigned NewSize = getRegSizeInBits ( * NewRC ) ; if ( SrcSize <= 32 || DstSize <= 32 ) return true ; return NewSize <= DstSize || NewSize <= SrcSize ; } </s>


<s> tree riscv_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( riscv_builtins ) ) return error_mark_node ; return riscv_builtin_decls [ code ] ; } </s>


<s> bool aarch64_mask_and_shift_for_ubfiz_p ( scalar_int_mode mode , rtx mask , rtx shft_amnt ) { return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL ( shft_amnt ) ) + 1 ) >= 0 && ( INTVAL ( mask ) & ( ( 1 << INTVAL ( shft_amnt ) ) - 1 ) ) == 0 ; } </s>

Return true if the mask and a shift amount from an RTX of the form ( x < < SHFT_AMNT ) & MASK are valid to combine into a UBFIZ instruction of mode MODE . See the * andim_ashift < mode > _bfiz pattern .


<s> int ARMTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { if ( ( Opcode == Instruction :: SDiv || Opcode == Instruction :: UDiv || Opcode == Instruction :: SRem || Opcode == Instruction :: URem ) && Idx == 1 ) return 0 ; if ( Opcode == Instruction :: And ) { if ( Imm == 255 || Imm == 65535 ) return 0 ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == 32 ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < 1 << 12 ) return 0 ; if ( ST -> isThumb ( ) && NegImm < 1 << 8 ) return 0 ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return 0 ; return getIntImmCost ( Imm , Ty , CostKind ) ; } </s>

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> static void mark_swaps_for_removal ( swap_web_entry * insn_entry , unsigned int i ) { rtx insn = insn_entry [ i ] . insn ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; if ( insn_entry [ i ] . is_load ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; while ( link ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( use_insn ) ] . will_delete = 1 ; link = link -> next ; } } } else if ( insn_entry [ i ] . is_store ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { machine_mode mode = GET_MODE ( DF_REF_REG ( use ) ) ; if ( ! ALTIVEC_OR_VSX_VECTOR_MODE ( mode ) ) continue ; struct df_link * link = DF_REF_CHAIN ( use ) ; while ( link ) { rtx def_insn = DF_REF_INSN ( link -> ref ) ; insn_entry [ INSN_UID ( def_insn ) ] . will_delete = 1 ; link = link -> next ; } } } } </s>

Mark the xxswapdi instructions associated with permuting loads and stores for removal . Note that we only flag them for deletion here , as there is a possibility of a swap being reached from multiple loads , etc .


<s> BitVector TriCoreRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( TriCore :: PC ) ; Reserved . set ( TriCore :: PCXI ) ; Reserved . set ( TriCore :: A10 ) ; Reserved . set ( TriCore :: A11 ) ; Reserved . set ( TriCore :: PSW ) ; Reserved . set ( TriCore :: FCX ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

TriCore TriCore TriCore::PC TriCore::PCXI TriCore::A10 TriCore::A11 TriCore::PSW TriCore::FCX


<s>
void
addExpr
(
MCInst
&
Inst
,
const
MCExpr
*
Expr
)
const
{
assert
(
Expr
&&
"Expr shouldn't be null!"
)
;
int64_t
Imm
=
0
;
bool
IsConstant
=
false
;
if
(
auto
*
RE
=
dyn_cast
<
RISCVMCExpr
>
(
Expr
)
)
{
IsConstant
=
RE
->
evaluateAsConstant
(
Imm
)
;
}
else
if
(
auto
*
CE
=
dyn_cast
<
MCConstantExpr
>
(
Expr
)
)
{
IsConstant
=
true
;
Imm
=
CE
->
getValue
(
)
;
}
if
(
IsConstant
)
Inst
.
addOperand
(
MCOperand
::
createImm
(
Imm
)
)
;
else
Inst
.
addOperand
(
MCOperand
::
createExpr
(
Expr
)
)
;
}
</s>


<s> bool MipsAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & TM . getSubtarget < MipsSubtarget > ( ) ; if ( Subtarget -> allowMixed16_32 ( ) ) const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; if ( Subtarget -> inMips16Mode ( ) ) for ( std :: map < const char * , const llvm :: Mips16HardFloatInfo :: FuncSignature * > :: const_iterator it = MipsFI -> StubsNeeded . begin ( ) ; it != MipsFI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: Mips16HardFloatInfo :: FuncSignature * Signature = it -> second ; if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ; } MCP = MF . getConstantPool ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) NaClAlignIndirectJumpTargets ( MF ) ; AsmPrinter :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .

Mips Mips Mips Mips Mips Mips Mips16HardFloatInfo::FuncSignature Mips Mips Mips16HardFloatInfo::FuncSignature


<s> static rtx sparc_function_arg ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) { return sparc_function_arg_1 ( cum , mode , type , named , false ) ; } </s>

Handle the TARGET_FUNCTION_ARG target hook .


<s> unsigned int getNumFixupKinds ( ) const override { return CSKY :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void TGSIAsmPrinter :: emitImplicitDef ( const MachineInstr * MI ) const { return ; } </s>

Targets can override this to customize the output of IMPLICIT_DEF instructions in verbose mode .


<s> bool AMDGPUTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { EVT ScalarVT = VT . getScalarType ( ) ; return ( ScalarVT == MVT :: f32 || ScalarVT == MVT :: f64 || ( ScalarVT == MVT :: f16 && Subtarget -> has16BitInsts ( ) ) ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


<s>
unsigned
NyuziInstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
iterator
I
=
MBB
.
end
(
)
;
unsigned
Count
=
0
;
while
(
I
!=
MBB
.
begin
(
)
)
{
I
;
if
(
I
->
isDebugValue
(
)
)
continue
;
if
(
!
isUncondBranchOpcode
(
I
->
getOpcode
(
)
)
&&
!
isCondBranchOpcode
(
I
->
getOpcode
(
)
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
end
(
)
;
++
Count
;
}
return
Count
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s>
SDValue
XCoreTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
return
LowerCCCArguments
(
Chain
,
CallConv
,
isVarArg
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .

XCore
XCore
ISD::InputArg
"Unsupported calling convention"


<s> char * aarch64_output_sve_cnt_immediate ( const char * prefix , const char * operands , rtx x ) { poly_int64 value = rtx_to_poly_int64 ( x ) ; gcc_assert ( aarch64_sve_cnt_immediate_p ( value ) ) ; return aarch64_output_sve_cnt_immediate ( prefix , operands , value . coeffs [ 1 ] , 0 ) ; } </s>

Return the asm string for an instruction with a CNT-like vector size operand ( a vector pattern followed by a multiplier in the range [ 1 , 16 ] ) . PREFIX is the mnemonic without the size suffix and OPERANDS is the first part of the operands template ( the part that comes before the vector size itself ) . X is the value of the vector size operand , as a polynomial integer rtx .


<s> static void vms_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { fputc ( '\n' , asm_out_file ) ; fprintf ( asm_out_file , ".section\t%s" , name ) ; if ( flags & SECTION_VMS_OVERLAY ) fprintf ( asm_out_file , ",OVR" ) ; if ( flags & SECTION_VMS_GLOBAL ) fprintf ( asm_out_file , ",GBL" ) ; if ( flags & SECTION_VMS_INITIALIZE ) fprintf ( asm_out_file , ",NOMOD" ) ; if ( flags & SECTION_DEBUG ) fprintf ( asm_out_file , ",NOWRT" ) ; fputc ( '\n' , asm_out_file ) ; } </s>

Switch to an arbitrary section NAME with attributes as specified by FLAGS . ALIGN specifies any known alignment requirements for the section ; 0 if the default should be used .

alpha ".section\t%s" ",OVR" ",GBL" ",NOMOD" ",NOWRT"


"Patmos Single-Path Scheduler (machine code)"

getPassName - Return a nice clean name for a pass .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( const MachineFunction & MF , bool UseEstimate , unsigned * NewMaxCallFrameSize ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const PPCFunctionInfo * FI = MF . getInfo < PPCFunctionInfo > ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! FI -> mustSaveTOC ( ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( NewMaxCallFrameSize ) * NewMaxCallFrameSize = maxCallFrameSize ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s>
SDValue
WebAssemblyTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"unimplemented operation lowering"
)
;
return
SDValue
(
)
;
case
ISD
::
FrameIndex
:
return
LowerFrameIndex
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
BR_JT
:
return
LowerBR_JT
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

WebAssembly
WebAssembly
"unimplemented operation lowering"
ISD::FrameIndex
ISD::GlobalAddress
ISD::ExternalSymbol
ISD::JumpTable
ISD::BR_JT
ISD::VASTART


<s> bool MSP430InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MSP430MachineFunctionInfo * MFI = MF . getInfo < MSP430MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; BuildMI ( MBB , MI , DL , get ( MSP430 :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; } return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> bool TriCoreRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> const char * Cpu0TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case Cpu0ISD :: JmpLink : return "Cpu0ISD::JmpLink" ; case Cpu0ISD :: Hi : return "Cpu0ISD::Hi" ; case Cpu0ISD :: Lo : return "Cpu0ISD::Lo" ; case Cpu0ISD :: GPRel : return "Cpu0ISD::GPRel" ; case Cpu0ISD :: Ret : return "Cpu0ISD::Ret" ; case Cpu0ISD :: DivRem : return "Cpu0ISD::DivRem" ; case Cpu0ISD :: DivRemU : return "Cpu0ISD::DivRemU" ; case Cpu0ISD :: Wrapper : return "Cpu0ISD::Wrapper" ; default : return NULL ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> BitVector HexagonRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( Hexagon :: R29 ) ; Reserved . set ( Hexagon :: R30 ) ; Reserved . set ( Hexagon :: R31 ) ; Reserved . set ( Hexagon :: SA0 ) ; Reserved . set ( Hexagon :: LC0 ) ; Reserved . set ( Hexagon :: SA1 ) ; Reserved . set ( Hexagon :: LC1 ) ; Reserved . set ( Hexagon :: P3_0 ) ; Reserved . set ( Hexagon :: USR ) ; Reserved . set ( Hexagon :: PC ) ; Reserved . set ( Hexagon :: UGP ) ; Reserved . set ( Hexagon :: GP ) ; Reserved . set ( Hexagon :: CS0 ) ; Reserved . set ( Hexagon :: CS1 ) ; Reserved . set ( Hexagon :: UPCL ) ; Reserved . set ( Hexagon :: UPCH ) ; Reserved . set ( Hexagon :: FRAMELIMIT ) ; Reserved . set ( Hexagon :: FRAMEKEY ) ; Reserved . set ( Hexagon :: PKTCOUNTLO ) ; Reserved . set ( Hexagon :: PKTCOUNTHI ) ; Reserved . set ( Hexagon :: UTIMERLO ) ; Reserved . set ( Hexagon :: UTIMERHI ) ; Reserved . set ( Hexagon :: C8 ) ; Reserved . set ( Hexagon :: USR_OVF ) ; for ( int x = Reserved . find_first ( ) ; x >= 0 ; x = Reserved . find_next ( x ) ) markSuperRegs ( Reserved , x ) ; return Reserved ; } </s>


<s> bool expand_a_shift ( enum machine_mode mode , int code , rtx operands [ ] ) { switch ( h8sx_classify_shift ( mode , code , operands [ 2 ] ) ) { case H8SX_SHIFT_BINARY : operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; return false ; case H8SX_SHIFT_UNARY : return false ; case H8SX_SHIFT_NONE : break ; } emit_move_insn ( operands [ 0 ] , operands [ 1 ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , gen_rtx_SET ( VOIDmode , operands [ 0 ] , gen_rtx_fmt_ee ( code , mode , operands [ 0 ] , operands [ 2 ] ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_SCRATCH ( QImode ) ) ) ) ) ; return true ; } </s>

Called from the .md file to emit code to do shifts . Returns a boolean indicating success ( currently this is always TRUE ) .


<s> bool MipsSEFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == Mips :: RA || Reg == Mips :: RA_64 ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == Mips :: LO0 || Reg == Mips :: LO0_64 || Reg == Mips :: HI0 || Reg == Mips :: HI0_64 ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( "interrupt" ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = 0 ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI : Mips :: MFLO ; Reg = Mips :: K0 ; } else { Op = ( Reg == Mips :: HI0 ) ? Mips :: MFHI64 : Mips :: MFLO64 ; Reg = Mips :: K0_64 ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , Mips :: K0 ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } return true ; } </s>


<s> void XCoreAsmPrinter :: emitFunctionEntryLabel ( ) { getTargetStreamer ( ) . emitCCTopFunction ( CurrentFnSym -> getName ( ) ) ; OutStreamer -> emitLabel ( CurrentFnSym ) ; } </s>

EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function .


<s> bool RISCVTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { default : return false ; case Intrinsic :: riscv_masked_atomicrmw_xchg_i32 : case Intrinsic :: riscv_masked_atomicrmw_add_i32 : case Intrinsic :: riscv_masked_atomicrmw_sub_i32 : case Intrinsic :: riscv_masked_atomicrmw_nand_i32 : case Intrinsic :: riscv_masked_atomicrmw_max_i32 : case Intrinsic :: riscv_masked_atomicrmw_min_i32 : case Intrinsic :: riscv_masked_atomicrmw_umax_i32 : case Intrinsic :: riscv_masked_atomicrmw_umin_i32 : case Intrinsic :: riscv_masked_cmpxchg_i32 : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 4 ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case Intrinsic :: riscv_masked_strided_load : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . memVT = MVT :: getVT ( I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( I . getType ( ) -> getScalarSizeInBits ( ) / 8 ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case Intrinsic :: riscv_masked_strided_store : Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . memVT = MVT :: getVT ( I . getArgOperand ( 0 ) -> getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( I . getArgOperand ( 0 ) -> getType ( ) -> getScalarSizeInBits ( ) / 8 ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOStore ; return true ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s>
void
LinearizedRegion
::
print
(
raw_ostream
&
OS
,
const
TargetRegisterInfo
*
TRI
)
{
OS
<<
"Linearized Region {"
;
bool
IsFirst
=
true
;
for
(
const
auto
&
MBB
:
MBBs
)
{
if
(
IsFirst
)
{
IsFirst
=
false
;
}
else
{
OS
<<
" ,"
;
}
OS
<<
MBB
->
getNumber
(
)
;
}
OS
<<
"} ("
<<
Entry
->
getNumber
(
)
<<
", "
<<
(
Exit
==
nullptr
1
:
Exit
->
getNumber
(
)
)
<<
"): In:"
<<
PrintReg
(
getBBSelectRegIn
(
)
,
TRI
)
<<
" Out:"
<<
PrintReg
(
getBBSelectRegOut
(
)
,
TRI
)
<<
" {"
;
for
(
auto
&
LI
:
LiveOuts
)
{
OS
<<
PrintReg
(
LI
,
TRI
)
<<
" "
;
}
OS
<<
"} \n"
;
}
</s>

print - Print a debug representation of the operand to the given stream .


<s> void OR1KFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const OR1KInstrInfo & TII = * static_cast < const OR1KInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const OR1KRegisterInfo * TRI = static_cast < const OR1KRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; bool IsPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool HasRA = MFI -> adjustsStack ( ) || IsPIC ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FPOffset = HasRA ? - 8 : - 4 ; int RAOffset = - 4 ; int BPOffset = FPOffset - 4 ; int StackSize = ( int ) MFI -> getStackSize ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: ADDI ) , OR1K :: R1 ) . addReg ( OR1K :: R2 ) . addImm ( 0 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: LWZ ) , OR1K :: R2 ) . addReg ( OR1K :: R1 ) . addImm ( FPOffset ) ; } else if ( isInt < 16 > ( StackSize ) ) { if ( StackSize ) { BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: ADDI ) , OR1K :: R1 ) . addReg ( OR1K :: R1 ) . addImm ( StackSize ) ; } } else { unsigned ScratchReg = OR1K :: R13 ; BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: MOVHI ) , ScratchReg ) . addImm ( ( uint32_t ) StackSize >> 16 ) ; BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: ORI ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( StackSize & 0xffffU ) ; BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: ADD ) , OR1K :: R1 ) . addReg ( OR1K :: R1 ) . addReg ( ScratchReg ) ; } if ( TRI -> hasBasePointer ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: LWZ ) , TRI -> getBaseRegister ( ) ) . addReg ( OR1K :: R1 ) . addImm ( BPOffset ) ; } if ( HasRA ) { BuildMI ( MBB , MBBI , dl , TII . get ( OR1K :: LWZ ) , OR1K :: R9 ) . addReg ( OR1K :: R1 ) . addImm ( RAOffset ) ; } } </s>


<s> static HOST_WIDE_INT riscv_constant_alignment ( const_tree exp , HOST_WIDE_INT align ) { if ( TREE_CODE ( exp ) == STRING_CST || TREE_CODE ( exp ) == CONSTRUCTOR ) return MAX ( align , BITS_PER_WORD ) ; return align ; } </s>


<s> static rtx sh_allocate_initial_value ( rtx hard_reg ) { rtx x ; if ( REGNO ( hard_reg ) == ( TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG ) ) { if ( current_function_is_leaf && ! sh_pr_n_sets ( ) && ! ( TARGET_SHCOMPACT && ( ( current_function_args_info . call_cookie & ~ CALL_COOKIE_RET_TRAMP ( 1 ) ) || current_function_has_nonlocal_label ) ) ) x = hard_reg ; else x = gen_frame_mem ( Pmode , return_address_pointer_rtx ) ; } else x = NULL_RTX ; return x ; } </s>

Return where to allocate pseudo for a given hard register initial value .


<s>
void
SHUXIMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
if
(
Desc
.
getSize
(
)
!=
4
)
{
llvm_unreachable
(
"Unexpected instruction size!"
)
;
}
const
uint32_t
Binary
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
emitConstant
(
Binary
,
Desc
.
getSize
(
)
,
OS
)
;
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

SHUXI
SHUXI
4
"Unexpected instruction size!"


<s> int ix86_constant_alignment ( tree exp , int align ) { if ( TREE_CODE ( exp ) == REAL_CST ) { if ( TYPE_MODE ( TREE_TYPE ( exp ) ) == DFmode && align < 64 ) return 64 ; else if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( exp ) ) ) && align < 128 ) return 128 ; } else if ( ! optimize_size && TREE_CODE ( exp ) == STRING_CST && TREE_STRING_LENGTH ( exp ) >= 31 && align < BITS_PER_WORD ) return BITS_PER_WORD ; return align ; } </s>

Compute the alignment given to a constant that is being placed in memory . EXP is the constant and ALIGN is the alignment that the object would ordinarily have . The value of this function is used instead of that alignment to align the object .


<s> static rtx ix86_copy_addr_to_reg ( rtx addr ) { rtx reg ; if ( GET_MODE ( addr ) == Pmode || GET_MODE ( addr ) == VOIDmode ) { reg = copy_addr_to_reg ( addr ) ; REG_POINTER ( reg ) = 1 ; return reg ; } else { gcc_assert ( GET_MODE ( addr ) == DImode && Pmode == SImode ) ; reg = copy_to_mode_reg ( DImode , addr ) ; REG_POINTER ( reg ) = 1 ; return gen_rtx_SUBREG ( SImode , reg , 0 ) ; } } </s>

Copy the address to a Pmode register . This is used for x32 to truncate DImode TLS address to a SImode register .


<s> bool MipsFastISel :: fastSelectInstruction ( const Instruction * I ) { if ( ! TargetSupported ) return false ; switch ( I -> getOpcode ( ) ) { default : break ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Trunc : return selectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPToSI : return selectFPToInt ( I , true ) ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ICmp : case Instruction :: FCmp : return selectCmp ( I ) ; } return false ; } </s>

This method is called by target-independent code when the normal FastISel process fails to select an instruction .


<s> void HexagonPassConfig :: addPostRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableRDFOpt ) addPass ( createHexagonRDFOpt ( ) ) ; if ( ! DisableHexagonCFGOpt ) addPass ( createHexagonCFGOptimizer ( ) ) ; if ( ! DisableAModeOpt ) addPass ( createHexagonOptAddrMode ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon


<s> bool ARMTTIImpl :: isLegalMaskedLoad ( Type * DataTy , Align Alignment ) { if ( ! EnableMaskedLoadStores || ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( auto * VecTy = dyn_cast < FixedVectorType > ( DataTy ) ) { if ( VecTy -> getNumElements ( ) == 2 ) return false ; unsigned VecWidth = DataTy -> getPrimitiveSizeInBits ( ) ; if ( VecWidth != 128 && VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ) return false ; } unsigned EltWidth = DataTy -> getScalarSizeInBits ( ) ; return ( EltWidth == 32 && Alignment >= 4 ) || ( EltWidth == 16 && Alignment >= 2 ) || ( EltWidth == 8 ) ; } </s>

Return true if the target supports masked load .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
MIRBuilder
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
MIRBuilder
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeSmallCMGlobalValue
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_TRUNC
:
return
legalizeVectorTrunc
(
MI
,
Helper
)
;
case
TargetOpcode
::
G_SBFX
:
case
TargetOpcode
::
G_UBFX
:
return
legalizeBitfieldExtract
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ROTR
:
return
legalizeRotate
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTPOP
:
return
legalizeCTPOP
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpxchg128
(
MI
,
MRI
,
Helper
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


"Invalid number of NOP bytes requested!"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


Return the DataLayout associated with the module this SCEV instance is operating on .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 DynAlloca Expander"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void SPIRVPassConfig :: addISelPrepare ( ) { auto * TM = & getTM < SPIRVTargetMachine > ( ) ; addPass ( createSPIRVEmitIntrinsicsPass ( TM ) ) ; TargetPassConfig :: addISelPrepare ( ) ; addPass ( createSPIRVBasicBlockDominancePass ( ) ) ; } </s>

Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection .


"%<-mdiv%> requires %<-march%> to subsume the %<M%> extension"

"requested ABI requires %<-march%> to subsume the %qc extension"

"%<-mpreferred-stack-boundary=%d%> must be between %d and %d"

"%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32"

"incompatible options %<-mstack-protector-guard=global%> and "

"both %<-mstack-protector-guard-offset%> and "

"%<-mstack-protector-guard-reg%> must be used "

"%qs is not a valid base register in %qs"


<s> unsigned getNumberOfRegisters ( bool Vector ) const { return 1 ; } </s>


<s> static void s390_def_or_undef_macro ( cpp_reader * pfile , F is_set , const struct cl_target_option * old_opts , const struct cl_target_option * new_opts , const char * macro_def , const char * macro_undef ) { bool was_set ; bool set ; was_set = ( ! old_opts ) ? false : is_set ( old_opts ) ; set = is_set ( new_opts ) ; if ( was_set == set ) return ; if ( set ) cpp_define ( pfile , macro_def ) ; else cpp_undef ( pfile , macro_undef ) ; } </s>

Helper function that defines or undefines macros . If SET is true , the macro MACRO_DEF is defined . If SET is false , the macro MACRO_UNDEF is undefined . Nothing is done if SET and WAS_SET have the same value .


<s> bool ARMOptimizeBarriersPass :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; std :: vector < MachineInstr * > ToRemove ; int64_t DMBType = - 1 ; for ( auto & MBB : MF ) { bool IsRemovableNextDMB = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == ARM :: DMB ) { if ( IsRemovableNextDMB ) { if ( MI . getOperand ( 0 ) . getImm ( ) == DMBType ) { ToRemove . push_back ( & MI ) ; } else { DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else { IsRemovableNextDMB = true ; DMBType = MI . getOperand ( 0 ) . getImm ( ) ; } } else if ( ! CanMovePastDMB ( & MI ) ) { IsRemovableNextDMB = false ; } } } bool Changed = false ; for ( auto MI : ToRemove ) { MI -> eraseFromParent ( ) ; ++ NumDMBsRemoved ; Changed = true ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> static bool mep_reuse_lo_p_1 ( rtx lo , rtx gpr , rtx_insn * insn , bool gpr_dead_p ) { do { insn = PREV_INSN ( insn ) ; if ( INSN_P ( insn ) ) switch ( recog_memoized ( insn ) ) { case CODE_FOR_mulsi3_1 : extract_insn ( insn ) ; if ( rtx_equal_p ( recog_data . operand [ 0 ] , gpr ) ) { mep_rewrite_mulsi3 ( insn , gpr_dead_p ? NULL : recog_data . operand [ 0 ] , recog_data . operand [ 1 ] , recog_data . operand [ 2 ] ) ; return true ; } return false ; case CODE_FOR_maddsi3 : extract_insn ( insn ) ; if ( rtx_equal_p ( recog_data . operand [ 0 ] , gpr ) ) { mep_rewrite_maddsi3 ( insn , gpr_dead_p ? NULL : recog_data . operand [ 0 ] , recog_data . operand [ 1 ] , recog_data . operand [ 2 ] , recog_data . operand [ 3 ] ) ; return true ; } return false ; case CODE_FOR_mulsi3r : case CODE_FOR_maddsi3r : extract_insn ( insn ) ; return rtx_equal_p ( recog_data . operand [ 1 ] , gpr ) ; default : if ( reg_set_p ( lo , insn ) || reg_set_p ( gpr , insn ) || volatile_insn_p ( PATTERN ( insn ) ) ) return false ; if ( gpr_dead_p && reg_referenced_p ( gpr , PATTERN ( insn ) ) ) gpr_dead_p = false ; break ; } } while ( ! NOTE_INSN_BASIC_BLOCK_P ( insn ) ) ; return false ; } </s>

Return true if $ lo has the same value as integer register GPR when instruction INSN is reached . If necessary , rewrite the instruction that sets $ lo so that it uses a proper SET , not a CLOBBER . LO is an rtx for ( reg : SI LO_REGNO ) . This function is intended to be used by the peephole2 pass . Since that pass goes from the end of a basic block to the beginning , and propagates liveness information on the way , there is no need to update register notes here . If GPR_DEAD_P is true on entry , and this function returns true , then the caller will replace _every_ use of GPR in and after INSN with LO . This means that if the instruction that sets $ lo is a mulr- or maddr-type instruction , we can rewrite it to use mul or madd instead . In combination with the copy progagation pass , this allows us to replace sequences like : mov GPR , R1 mulr GPR , R2 with : mul R1 , R2 if GPR is no longer used .


<s> bool SIInstrInfo :: isOperandLegal ( const MachineInstr * MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & InstDesc = get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - 1 ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI -> getOperand ( OpIdx ) ; if ( isVALU ( InstDesc . Opcode ) && usesConstantBus ( MRI , * MO ) ) { unsigned SGPRUsed = MO -> isReg ( ) ? MO -> getReg ( ) : ( unsigned ) AMDGPU :: NoRegister ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; if ( usesConstantBus ( MRI , MI -> getOperand ( i ) ) && MI -> getOperand ( i ) . isReg ( ) && MI -> getOperand ( i ) . getReg ( ) != SGPRUsed ) { return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; const TargetRegisterClass * RC = MRI . getRegClass ( MO -> getReg ( ) ) ; return RI . getCommonSubClass ( RC , RI . getRegClass ( OpInfo . RegClass ) ) == RC ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO ) ; } </s>

Check if MO is a legal operand if it was the OpIdx Operand for MI .


<s> MVT SITargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( CC == CallingConv :: AMDGPU_KERNEL ) return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; if ( VT . isVector ( ) ) { EVT ScalarVT = VT . getScalarType ( ) ; unsigned Size = ScalarVT . getSizeInBits ( ) ; if ( Size == 16 ) { if ( Subtarget -> has16BitInsts ( ) ) return VT . isInteger ( ) ? MVT :: v2i16 : MVT :: v2f16 ; return VT . isInteger ( ) ? MVT :: i32 : MVT :: f32 ; } if ( Size < 16 ) return Subtarget -> has16BitInsts ( ) ? MVT :: i16 : MVT :: i32 ; return Size == 32 ? ScalarVT . getSimpleVT ( ) : MVT :: i32 ; } if ( VT . getSizeInBits ( ) > 32 ) return MVT :: i32 ; return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ; } </s>

Certain combinations of ABIs , Targets and features require that types are legal for some operations and not for other operations .


<s> bool ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM , const LiveRegMatrix * Matrix ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return false ; } unsigned Paired = Hint . second ; if ( Paired == 0 ) return false ; unsigned PairedPhys = 0 ; if ( TargetRegisterInfo :: isPhysicalRegister ( Paired ) ) { PairedPhys = Paired ; } else if ( VRM && VRM -> hasPhys ( Paired ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Paired ) , Odd , this ) ; } if ( PairedPhys && is_contained ( Order , PairedPhys ) ) Hints . push_back ( PairedPhys ) ; for ( unsigned Reg : Order ) { if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } return false ; } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> unsigned WebAssemblyTTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Opd1Info , TTI :: OperandValueKind Opd2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { unsigned Cost = BasicTTIImplBase < WebAssemblyTTIImpl > :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( auto * VTy = dyn_cast < VectorType > ( Ty ) ) { switch ( Opcode ) { case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : if ( Opd2Info != TTI :: OK_UniformValue && Opd2Info != TTI :: OK_UniformConstantValue ) Cost = cast < FixedVectorType > ( VTy ) -> getNumElements ( ) * ( TargetTransformInfo :: TCC_Basic + getArithmeticInstrCost ( Opcode , VTy -> getElementType ( ) , CostKind ) + TargetTransformInfo :: TCC_Basic ) ; break ; } } return Cost ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


<s> static bool arm_cxx_use_aeabi_atexit ( void ) { return TARGET_AAPCS_BASED ; } </s>

The EABI says __aeabi_atexit should be used to register static destructors .


<s> static machine_mode rs6000_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_VSX ) switch ( mode ) { case E_DFmode : return V2DFmode ; default : ; } if ( TARGET_ALTIVEC || TARGET_VSX ) switch ( mode ) { case E_SFmode : return V4SFmode ; case E_TImode : return V1TImode ; case E_DImode : return V2DImode ; case E_SImode : return V4SImode ; case E_HImode : return V8HImode ; case E_QImode : return V16QImode ; default : ; } if ( TARGET_SPE ) switch ( mode ) { case E_SFmode : return V2SFmode ; case E_SImode : return V2SImode ; default : ; } if ( TARGET_PAIRED_FLOAT && mode == SFmode ) return V2SFmode ; return word_mode ; } </s>


"This eliminateCallFramePseudoInstr does not support Thumb1!"

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> static void s390_reorg ( void ) { bool pool_overflow = false ; split_all_insns_noflow ( ) ; cfun -> machine -> decomposed_literal_pool_addresses_ok_p = true ; for ( ; ; ) { struct constant_pool * pool = NULL ; if ( ! pool_overflow ) { pool = s390_mainpool_start ( ) ; if ( ! pool ) pool_overflow = true ; } if ( pool_overflow ) pool = s390_chunkify_start ( ) ; if ( ! TARGET_CPU_ZARCH && s390_split_branches ( ) ) { if ( pool_overflow ) s390_chunkify_cancel ( pool ) ; else s390_mainpool_cancel ( pool ) ; continue ; } if ( pool_overflow ) s390_chunkify_finish ( pool ) ; else s390_mainpool_finish ( pool ) ; cfun -> machine -> split_branches_pending_p = false ; break ; } if ( TARGET_CPU_ZARCH ) { rtx insn , label , target ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { label = s390_execute_label ( insn ) ; if ( ! label ) continue ; gcc_assert ( label != const0_rtx ) ; target = emit_label ( XEXP ( label , 0 ) ) ; INSN_ADDRESSES_NEW ( target , - 1 ) ; target = emit_insn ( s390_execute_target ( insn ) ) ; INSN_ADDRESSES_NEW ( target , - 1 ) ; } } s390_optimize_prologue ( ) ; } </s>


<s>
static
void
build_mips16_function_stub
(
FILE
*
file
)
{
const
char
*
fnname
;
char
*
secname
,
*
stubname
;
tree
stubid
,
stubdecl
;
int
need_comma
;
unsigned
int
f
;
fnname
=
XSTR
(
XEXP
(
DECL_RTL
(
current_function_decl
)
,
0
)
,
0
)
;
secname
=
(
char
*
)
alloca
(
strlen
(
fnname
)
+
20
)
;
sprintf
(
secname
,
".mips16.fn.%s"
,
fnname
)
;
stubname
=
(
char
*
)
alloca
(
strlen
(
fnname
)
+
20
)
;
sprintf
(
stubname
,
"__fn_stub_%s"
,
fnname
)
;
stubid
=
get_identifier
(
stubname
)
;
stubdecl
=
build_decl
(
FUNCTION_DECL
,
stubid
,
build_function_type
(
void_type_node
,
NULL_TREE
)
)
;
DECL_SECTION_NAME
(
stubdecl
)
=
build_string
(
strlen
(
secname
)
,
secname
)
;
fprintf
(
file
,
"\t# Stub function for %s ("
,
current_function_name
(
)
)
;
need_comma
=
0
;
for
(
f
=
(
unsigned
int
)
current_function_args_info
.
fp_code
;
f
!=
0
;
f
>>=
2
)
{
fprintf
(
file
,
"%s%s"
,
need_comma
", "
:
""
,
(
f
&
3
)
==
1
"float"
:
"double"
)
;
need_comma
=
1
;
}
fprintf
(
file
,
")\n"
)
;
fprintf
(
file
,
"\t.set\tnomips16\n"
)
;
function_section
(
stubdecl
)
;
ASM_OUTPUT_ALIGN
(
file
,
floor_log2
(
FUNCTION_BOUNDARY
/
BITS_PER_UNIT
)
)
;
if
(
!
FUNCTION_NAME_ALREADY_DECLARED
)
{
fputs
(
"\t.ent\t"
,
file
)
;
assemble_name
(
file
,
stubname
)
;
fputs
(
"\n"
,
file
)
;
}
assemble_name
(
file
,
stubname
)
;
fputs
(
":\n"
,
file
)
;
fprintf
(
file
,
"\t.set\tnoreorder\n"
)
;
mips16_fp_args
(
file
,
current_function_args_info
.
fp_code
,
1
)
;
fprintf
(
asm_out_file
,
"\t.set\tnoat\n"
)
;
fprintf
(
asm_out_file
,
"\tla\t%s,"
,
reg_names
[
GP_REG_FIRST
+
1
]
)
;
assemble_name
(
file
,
fnname
)
;
fprintf
(
file
,
"\n"
)
;
fprintf
(
asm_out_file
,
"\tjr\t%s\n"
,
reg_names
[
GP_REG_FIRST
+
1
]
)
;
fprintf
(
asm_out_file
,
"\t.set\tat\n"
)
;
fprintf
(
file
,
"\tnop\n"
)
;
fprintf
(
file
,
"\t.set\treorder\n"
)
;
if
(
!
FUNCTION_NAME_ALREADY_DECLARED
)
{
fputs
(
"\t.end\t"
,
file
)
;
assemble_name
(
file
,
stubname
)
;
fputs
(
"\n"
,
file
)
;
}
fprintf
(
file
,
"\t.set\tmips16\n"
)
;
function_section
(
current_function_decl
)
;
}
</s>

Build a mips16 function stub . This is used for functions which take arguments in the floating point registers . It is 32 bit code that moves the floating point args into the general registers , and then jumps to the 16 bit code .


<s> bool AMDGPUAlwaysInline :: runOnModule ( Module & M ) { std :: vector < GlobalAlias * > AliasesToRemove ; std :: vector < Function * > FuncsToClone ; for ( GlobalAlias & A : M . aliases ( ) ) { if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } for ( Function & F : M ) { if ( ! F . hasLocalLinkage ( ) && ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) FuncsToClone . push_back ( & F ) ; } for ( Function * F : FuncsToClone ) { ValueToValueMapTy VMap ; Function * NewFunc = CloneFunction ( F , VMap ) ; NewFunc -> setLinkage ( GlobalValue :: InternalLinkage ) ; F -> replaceAllUsesWith ( NewFunc ) ; } for ( Function & F : M ) { if ( F . hasLocalLinkage ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) { F . addFnAttr ( Attribute :: AlwaysInline ) ; } } return false ; } </s>

runOnModule - Virtual method overriden by subclasses to process the module being operated on .


<s> void AArch64AsmPrinter :: emitFunctionBodyEnd ( ) { if ( ! AArch64FI -> getLOHRelated ( ) . empty ( ) ) emitLOHs ( ) ; } </s>

Targets can override this to emit stuff after the last basic block in the function .


<s> static int function_arg_slotno ( const struct sparc_args * cum , machine_mode mode , const_tree type , bool named , bool incoming , int * pregno , int * ppadding ) { int regbase = ( incoming ? SPARC_INCOMING_INT_ARG_FIRST : SPARC_OUTGOING_INT_ARG_FIRST ) ; int slotno = cum -> words ; enum mode_class mclass ; int regno ; * ppadding = 0 ; if ( type && TREE_ADDRESSABLE ( type ) ) return - 1 ; if ( TARGET_ARCH32 && mode == BLKmode && type && TYPE_ALIGN ( type ) % PARM_BOUNDARY != 0 ) return - 1 ; if ( TARGET_ARCH64 && ( type ? TYPE_ALIGN ( type ) : GET_MODE_ALIGNMENT ( mode ) ) >= 128 && ( slotno & 1 ) != 0 ) slotno ++ , * ppadding = 1 ; mclass = GET_MODE_CLASS ( mode ) ; if ( type && TREE_CODE ( type ) == VECTOR_TYPE ) { if ( TREE_CODE ( TREE_TYPE ( type ) ) == REAL_TYPE ) { gcc_assert ( mode == BLKmode ) ; } else { gcc_assert ( mode != BLKmode ) ; mclass = MODE_FLOAT ; } } switch ( mclass ) { case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_INT : if ( TARGET_ARCH64 && TARGET_FPU && named ) { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; regno = SPARC_FP_ARG_FIRST + slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 ) regno ++ ; break ; } case MODE_INT : case MODE_COMPLEX_INT : if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; break ; case MODE_RANDOM : if ( mode == VOIDmode ) return - 1 ; gcc_assert ( mode == BLKmode ) ; if ( TARGET_ARCH32 || ! type || ( TREE_CODE ( type ) != RECORD_TYPE && TREE_CODE ( type ) != VECTOR_TYPE ) ) { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; regno = regbase + slotno ; } else { if ( slotno >= SPARC_FP_ARG_MAX ) return - 1 ; if ( TREE_CODE ( type ) == RECORD_TYPE ) { classify_data_t data = { false , false } ; traverse_record_type < classify_data_t , classify_registers > ( type , named , & data ) ; if ( data . fp_regs ) { if ( slotno >= SPARC_FP_ARG_MAX - 1 && ! data . fp_regs_in_first_word ) return - 1 ; } else { if ( slotno >= SPARC_INT_ARG_MAX ) return - 1 ; } } return slotno ; } break ; default : gcc_unreachable ( ) ; } * pregno = regno ; return slotno ; } </s>

Compute the slot number to pass an argument in . Return the slot number or -1 if passing on the stack . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . INCOMING_P is zero for FUNCTION_ARG , nonzero for FUNCTION_INCOMING_ARG . * PREGNO records the register number to use if scalar type . * PPADDING records the amount of padding needed in words .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Sparc Assembly Printer"
;
}
</s>


<s> void NVPTXAsmPrinter :: emitFunctionBodyStart ( ) { SmallString < 128 > Str ; raw_svector_ostream O ( Str ) ; emitDemotedVars ( & MF -> getFunction ( ) , O ) ; OutStreamer -> emitRawText ( O . str ( ) ) ; } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> void canonicalize ( ) { if ( ! isLHSReg ( ) && isRHSReg ( ) ) { std :: swap ( LHSReg , RHSReg ) ; std :: swap ( LHSImm , RHSImm ) ; CC = ISD :: getSetCCSwappedOperands ( CC ) ; } } </s>

Form a canonical key for the specified mangling .


<s> static int symbolic_expression_p ( rtx x ) { if ( GET_CODE ( x ) == SYMBOL_REF ) return 1 ; if ( GET_CODE ( x ) == CONST ) return symbolic_expression_p ( XEXP ( x , 0 ) ) ; if ( UNARY_P ( x ) ) return symbolic_expression_p ( XEXP ( x , 0 ) ) ; if ( ARITHMETIC_P ( x ) ) return ( symbolic_expression_p ( XEXP ( x , 0 ) ) || symbolic_expression_p ( XEXP ( x , 1 ) ) ) ; return 0 ; } </s>

Return 1 if X contains a symbolic expression . We know these expressions will have one of a few well defined forms , so we need only check those forms .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasInlineAsmWithSPAdjust ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
MachineBasicBlock
::
iterator
ARMBaseInstrInfo
::
insertOutlinedCall
(
Module
&
M
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
&
It
,
MachineFunction
&
MF
,
outliner
::
Candidate
&
C
)
const
{
MachineInstrBuilder
MIB
;
MachineBasicBlock
::
iterator
CallPt
;
unsigned
Opc
;
bool
isThumb
=
Subtarget
.
isThumb
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerTailCall
)
{
Opc
=
isThumb
Subtarget
.
isTargetMachO
(
)
ARM
::
tTAILJMPd
:
ARM
::
tTAILJMPdND
:
ARM
::
TAILJMPd
;
MIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
isThumb
)
MIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
It
=
MBB
.
insert
(
It
,
MIB
)
;
return
It
;
}
Opc
=
isThumb
ARM
::
tBL
:
ARM
::
BL
;
MachineInstrBuilder
CallMIB
=
BuildMI
(
MF
,
DebugLoc
(
)
,
get
(
Opc
)
)
;
if
(
isThumb
)
CallMIB
.
add
(
predOps
(
ARMCC
::
AL
)
)
;
CallMIB
.
addGlobalAddress
(
M
.
getNamedValue
(
MF
.
getName
(
)
)
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerNoLRSave
||
C
.
CallConstructionID
==
MachineOutlinerThunk
)
{
It
=
MBB
.
insert
(
It
,
CallMIB
)
;
return
It
;
}
const
ARMFunctionInfo
&
AFI
=
*
C
.
getMF
(
)
->
getInfo
<
ARMFunctionInfo
>
(
)
;
if
(
C
.
CallConstructionID
==
MachineOutlinerRegSave
)
{
unsigned
Reg
=
findRegisterToSaveLRTo
(
C
)
;
assert
(
Reg
!=
0
&&
"No callee-saved register available?"
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
Reg
,
ARM
::
LR
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRSaveToReg
(
MBB
,
It
,
Reg
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
copyPhysReg
(
MBB
,
It
,
DebugLoc
(
)
,
ARM
::
LR
,
Reg
,
true
)
;
if
(
!
AFI
.
isLRSpilled
(
)
)
emitCFIForLRRestoreFromReg
(
MBB
,
It
)
;
It
;
return
CallPt
;
}
if
(
!
MBB
.
isLiveIn
(
ARM
::
LR
)
)
MBB
.
addLiveIn
(
ARM
::
LR
)
;
bool
Auth
=
!
AFI
.
isLRSpilled
(
)
&&
AFI
.
shouldSignReturnAddress
(
true
)
;
saveLROnStack
(
MBB
,
It
,
!
AFI
.
isLRSpilled
(
)
,
Auth
)
;
CallPt
=
MBB
.
insert
(
It
,
CallMIB
)
;
restoreLRFromStack
(
MBB
,
It
,
!
AFI
.
isLRSpilled
(
)
,
Auth
)
;
It
;
return
CallPt
;
}
</s>

Insert a call to an outlined function into the program .

ARM
ARM
ARM::tTAILJMPd
ARM::tTAILJMPdND
ARM::TAILJMPd
ARMCC::AL
ARM::tBL
ARM::BL
ARMCC::AL
ARM
ARM
0
"No callee-saved register available?"
ARM::LR
ARM::LR
ARM::LR
ARM::LR


"// rs6000_variable_issue (more = %d) = %d\n"

Power4 load update and store update instructions are cracked into a load or store and an integer insn which are executed in the same cycle . Branches have their own dispatch slot which does not count against the GCC issue rate , but it changes the program flow so there are no other instructions to issue in this cycle .


<s> yaml :: MachineFunctionInfo * WebAssemblyTargetMachine :: convertFuncInfoToYAML ( const MachineFunction & MF ) const { const auto * MFI = MF . getInfo < WebAssemblyFunctionInfo > ( ) ; return new yaml :: WebAssemblyFunctionInfo ( * MFI ) ; } </s>

Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> static rtx alpha_emit_xfloating_compare ( enum rtx_code * pcode , rtx op0 , rtx op1 ) { enum rtx_code cmp_code , res_code ; rtx func , out , operands [ 2 ] ; cmp_code = * pcode ; switch ( cmp_code ) { case UNORDERED : cmp_code = EQ ; res_code = LT ; break ; case ORDERED : cmp_code = EQ ; res_code = GE ; break ; case NE : res_code = NE ; break ; case EQ : case LT : case GT : case LE : case GE : res_code = GT ; break ; default : gcc_unreachable ( ) ; } * pcode = res_code ; func = alpha_lookup_xfloating_lib_func ( cmp_code ) ; operands [ 0 ] = op0 ; operands [ 1 ] = op1 ; out = gen_reg_rtx ( DImode ) ; alpha_emit_xfloating_libcall ( func , out , operands , 2 , gen_rtx_fmt_ee ( cmp_code , CCmode , op0 , op1 ) ) ; return out ; } </s>

Emit an X_floating library function call for a comparison .


<s> Optional < Instruction * > AArch64TTIImpl :: instCombineIntrinsic ( InstCombiner & IC , IntrinsicInst & II ) const { Intrinsic :: ID IID = II . getIntrinsicID ( ) ; switch ( IID ) { default : break ; case Intrinsic :: aarch64_sve_convert_from_svbool : return instCombineConvertFromSVBool ( IC , II ) ; case Intrinsic :: aarch64_sve_dup : return instCombineSVEDup ( IC , II ) ; case Intrinsic :: aarch64_sve_dup_x : return instCombineSVEDupX ( IC , II ) ; case Intrinsic :: aarch64_sve_cmpne : case Intrinsic :: aarch64_sve_cmpne_wide : return instCombineSVECmpNE ( IC , II ) ; case Intrinsic :: aarch64_sve_rdffr : return instCombineRDFFR ( IC , II ) ; case Intrinsic :: aarch64_sve_lasta : case Intrinsic :: aarch64_sve_lastb : return instCombineSVELast ( IC , II ) ; case Intrinsic :: aarch64_sve_cntd : return instCombineSVECntElts ( IC , II , 2 ) ; case Intrinsic :: aarch64_sve_cntw : return instCombineSVECntElts ( IC , II , 4 ) ; case Intrinsic :: aarch64_sve_cnth : return instCombineSVECntElts ( IC , II , 8 ) ; case Intrinsic :: aarch64_sve_cntb : return instCombineSVECntElts ( IC , II , 16 ) ; case Intrinsic :: aarch64_sve_ptest_any : case Intrinsic :: aarch64_sve_ptest_first : case Intrinsic :: aarch64_sve_ptest_last : return instCombineSVEPTest ( IC , II ) ; case Intrinsic :: aarch64_sve_mul : case Intrinsic :: aarch64_sve_fmul : return instCombineSVEVectorMul ( IC , II ) ; case Intrinsic :: aarch64_sve_tbl : return instCombineSVETBL ( IC , II ) ; case Intrinsic :: aarch64_sve_uunpkhi : case Intrinsic :: aarch64_sve_uunpklo : case Intrinsic :: aarch64_sve_sunpkhi : case Intrinsic :: aarch64_sve_sunpklo : return instCombineSVEUnpack ( IC , II ) ; case Intrinsic :: aarch64_sve_tuple_get : return instCombineSVETupleGet ( IC , II ) ; case Intrinsic :: aarch64_sve_zip1 : case Intrinsic :: aarch64_sve_zip2 : return instCombineSVEZip ( IC , II ) ; } return None ; } </s>

Targets can implement their own combinations for target-specific intrinsics .


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool aarch64_bti_enabled ( void ) { return ( aarch64_enable_bti == 1 ) ; } </s>

Return TRUE if Branch Target Identification Mechanism is enabled .


<s>
void
AMDGPUArgumentUsageInfo
::
print
(
raw_ostream
&
OS
,
const
Module
*
M
)
const
{
for
(
const
auto
&
FI
:
ArgInfoMap
)
{
OS
<<
"Arguments for "
<<
FI
.
first
->
getName
(
)
<<
'\n'
<<
"  PrivateSegmentBuffer: "
<<
FI
.
second
.
PrivateSegmentBuffer
<<
"  DispatchPtr: "
<<
FI
.
second
.
DispatchPtr
<<
"  QueuePtr: "
<<
FI
.
second
.
QueuePtr
<<
"  KernargSegmentPtr: "
<<
FI
.
second
.
KernargSegmentPtr
<<
"  DispatchID: "
<<
FI
.
second
.
DispatchID
<<
"  FlatScratchInit: "
<<
FI
.
second
.
FlatScratchInit
<<
"  PrivateSegmentSize: "
<<
FI
.
second
.
PrivateSegmentSize
<<
"  GridWorkgroupCountX: "
<<
FI
.
second
.
GridWorkGroupCountX
<<
"  GridWorkgroupCountY: "
<<
FI
.
second
.
GridWorkGroupCountY
<<
"  GridWorkgroupCountZ: "
<<
FI
.
second
.
GridWorkGroupCountZ
<<
"  WorkGroupIDX: "
<<
FI
.
second
.
WorkGroupIDX
<<
"  WorkGroupIDY: "
<<
FI
.
second
.
WorkGroupIDY
<<
"  WorkGroupIDZ: "
<<
FI
.
second
.
WorkGroupIDZ
<<
"  WorkGroupInfo: "
<<
FI
.
second
.
WorkGroupInfo
<<
"  PrivateSegmentWaveByteOffset: "
<<
FI
.
second
.
PrivateSegmentWaveByteOffset
<<
"  ImplicitBufferPtr: "
<<
FI
.
second
.
ImplicitBufferPtr
<<
"  ImplicitArgPtr: "
<<
FI
.
second
.
ImplicitArgPtr
<<
"  WorkItemIDX "
<<
FI
.
second
.
WorkItemIDX
<<
"  WorkItemIDY "
<<
FI
.
second
.
WorkItemIDY
<<
"  WorkItemIDZ "
<<
FI
.
second
.
WorkItemIDZ
<<
'\n'
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AMDGPU
AMDGPU
"Arguments for "
"  PrivateSegmentBuffer: "
"  DispatchPtr: "
"  QueuePtr: "
"  KernargSegmentPtr: "
"  DispatchID: "
"  FlatScratchInit: "
"  PrivateSegmentSize: "
"  GridWorkgroupCountX: "
"  GridWorkgroupCountY: "
"  GridWorkgroupCountZ: "
"  WorkGroupIDX: "
"  WorkGroupIDY: "
"  WorkGroupIDZ: "
"  WorkGroupInfo: "
"  PrivateSegmentWaveByteOffset: "
"  ImplicitBufferPtr: "
"  ImplicitArgPtr: "
"  WorkItemIDX "
"  WorkItemIDY "
"  WorkItemIDZ "


<s> static void riscv_va_start ( tree valist , rtx nextarg ) { nextarg = plus_constant ( Pmode , nextarg , - cfun -> machine -> varargs_size ) ; std_expand_builtin_va_start ( valist , nextarg ) ; } </s>


<s> bool isMem ( ) const override { return false ; } </s>


"iwmmxt requires an AAPCS compatible ABI for proper operation"

"iwmmxt abi requires an iwmmxt capable cpu"

"target CPU does not support interworking"

"AAPCS does not support -mcaller-super-interworking"

"AAPCS does not support -mcallee-super-interworking"

"target CPU does not support ARMv8-M Security Extensions"

"ARMv8-M Security Extensions incompatible with selected FPU"

"-mfloat-abi=hard: selected processor lacks an FPU"

Perform some validation between the desired architecture and the rest of the options .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; AArch64BranchTargetAligner BTA ; unsigned Opcode = Inst . getOpcode ( ) ; if ( BTA . needsSpecialAlignment ( STI . getCPU ( ) , Opcode ) ) { unsigned BA = BTA . getBranchTargetAlignment ( Inst ) ; if ( BA ) { EmitA64MappingSymbol ( ) ; MCELFStreamer :: EmitCodeAlignment ( BA ) ; } } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void ARCompactInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( ARC :: STrri ) ) . addFrameIndex ( FrameIdx ) . addImm ( 0 ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && ! getARMSubtarget ( ) . isThumb1Only ( ) ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isLikeA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && getARMSubtarget ( ) . isCortexA15 ( ) && getARMSubtarget ( ) . hasNEON ( ) && ! DisableA15SDOptimization ) { addPass ( createA15SDOptimizerPass ( ) ) ; } return true ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AArch64 :: SP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) { Reserved . set ( AArch64 :: FP ) ; Reserved . set ( AArch64 :: W29 ) ; } if ( STI -> isTargetDarwin ( ) ) { Reserved . set ( AArch64 :: X18 ) ; Reserved . set ( AArch64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( AArch64 :: X19 ) ; Reserved . set ( AArch64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .