<s> bool SIInstrInfo :: analyzeCompare ( const MachineInstr & MI , Register & SrcReg , Register & SrcReg2 , int64_t & CmpMask , int64_t & CmpValue ) const { if ( ! MI . getOperand ( 0 ) . isReg ( ) || MI . getOperand ( 0 ) . getSubReg ( ) ) return false ; switch ( MI . getOpcode ( ) ) { default : break ; case AMDGPU :: S_CMP_EQ_U32 : case AMDGPU :: S_CMP_EQ_I32 : case AMDGPU :: S_CMP_LG_U32 : case AMDGPU :: S_CMP_LG_I32 : case AMDGPU :: S_CMP_LT_U32 : case AMDGPU :: S_CMP_LT_I32 : case AMDGPU :: S_CMP_GT_U32 : case AMDGPU :: S_CMP_GT_I32 : case AMDGPU :: S_CMP_LE_U32 : case AMDGPU :: S_CMP_LE_I32 : case AMDGPU :: S_CMP_GE_U32 : case AMDGPU :: S_CMP_GE_I32 : case AMDGPU :: S_CMP_EQ_U64 : case AMDGPU :: S_CMP_LG_U64 : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; if ( MI . getOperand ( 1 ) . isReg ( ) ) { if ( MI . getOperand ( 1 ) . getSubReg ( ) ) return false ; SrcReg2 = MI . getOperand ( 1 ) . getReg ( ) ; CmpValue = 0 ; } else if ( MI . getOperand ( 1 ) . isImm ( ) ) { SrcReg2 = Register ( ) ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; } else { return false ; } CmpMask = ~ 0 ; return true ; case AMDGPU :: S_CMPK_EQ_U32 : case AMDGPU :: S_CMPK_EQ_I32 : case AMDGPU :: S_CMPK_LG_U32 : case AMDGPU :: S_CMPK_LG_I32 : case AMDGPU :: S_CMPK_LT_U32 : case AMDGPU :: S_CMPK_LT_I32 : case AMDGPU :: S_CMPK_GT_U32 : case AMDGPU :: S_CMPK_GT_I32 : case AMDGPU :: S_CMPK_LE_U32 : case AMDGPU :: S_CMPK_LE_I32 : case AMDGPU :: S_CMPK_GE_U32 : case AMDGPU :: S_CMPK_GE_I32 : SrcReg = MI . getOperand ( 0 ) . getReg ( ) ; SrcReg2 = Register ( ) ; CmpValue = MI . getOperand ( 1 ) . getImm ( ) ; CmpMask = ~ 0 ; return true ; } return false ; } </s>

analyzeCompare - For a comparison instruction , return the source registers in SrcReg and SrcReg2 if having two register operands , and the value it compares against in CmpValue .


<s> static rtx emit_adjust_base_to_offset ( rtx base , int offset ) { rtx new_base = gen_rtx_REG ( Pmode , 1 ) ; emit_move_insn ( new_base , GEN_INT ( offset ) ) ; emit_insn ( gen_rtx_SET ( new_base , gen_rtx_PLUS ( Pmode , base , new_base ) ) ) ; return new_base ; } </s>

Emit code to adjust BASE to OFFSET . Return the new base .


<s> static MachineMemOperand * getMachineMemOperand ( MachineBasicBlock & MBB , int FI , MachineMemOperand :: Flags Flags ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; } </s>

Allocate a new MachineMemOperand by copying an existing one , replacing the flags .


<s> bool MOSMCExpr :: evaluateAsConstant ( int64_t & Result ) const { MCValue Value ; bool IsRelocatable = getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ; if ( ! IsRelocatable ) { return false ; } if ( Value . isAbsolute ( ) ) { Result = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } return false ; } </s>

Evaluates the fixup as a constant value .


<s> static bool riscv_save_reg_p ( unsigned int regno ) { bool call_saved = ! global_regs [ regno ] && ! call_used_regs [ regno ] ; bool might_clobber = crtl -> saves_all_registers || df_regs_ever_live_p ( regno ) ; if ( call_saved && might_clobber ) return true ; if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && crtl -> calls_eh_return ) return true ; return false ; } </s>

Return true if the current function must save register REGNO .


<s> virtual void getAnalysisUsage ( AnalysisUsage & Info ) { Info . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool ARMGlobalMerge :: runOnFunction ( Function & F ) { return false ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void NVPTXTargetStreamer :: outputDwarfFileDirectives ( ) { for ( const std :: string & S : DwarfFiles ) getStreamer ( ) . emitRawText ( S . data ( ) ) ; DwarfFiles . clear ( ) ; } </s>

Outputs the list of the DWARF '.file ' directives to the streamer .


"Instr doesn't have FrameIndex operand!"

Returns true if the instruction 's frame index reference would be better served by a base register other than FP or SP .


"DCPU16 DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> MVT :: SimpleValueType Z80oldTargetLowering :: getCmpLibcallReturnType ( ) const { return MVT :: Other ; } </s>

Return the ValueType for comparison libcalls .


<s> int get_ma ( rtx ma ) { if ( INTVAL ( ma ) == MASK_ANY ) return INVALID_ATTRIBUTE ; return INTVAL ( ma ) ; } </s>

Get ma according to operand [ mask_op_idx ] .


<s> static void mips_multi_start ( void ) { mips_multi_members . truncate ( 0 ) ; mips_multi_num_insns = 0 ; } </s>


<s> bool XtensaAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { llvm_unreachable ( "XXX:" ) ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case ARM :: GPRRegClassID : case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : case ARM :: QPRRegClassID : case ARM :: QQPRRegClassID : case ARM :: QQQQPRRegClassID : case ARM :: GPRPairRegClassID : return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .

ARM ARM ARM::GPRRegClassID ARM::SPRRegClassID ARM::DPRRegClassID ARM::QPRRegClassID ARM::QQPRRegClassID ARM::QQQQPRRegClassID ARM::GPRPairRegClassID


This function will set the fpscr from memory . MODE is the mode we are setting it to .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"LEG Assembly Printer"
;
}
</s>


"Alloca should always return a pointer."

Emit an alloca address in a register using target-specific logic .


<s> void emitInst ( uint32_t Inst ) { char Buffer [ 4 ] ; for ( char & C : Buffer ) { C = uint8_t ( Inst ) ; Inst >>= 8 ; } emitA64MappingSymbol ( ) ; MCELFStreamer :: emitBytes ( StringRef ( Buffer , 4 ) ) ; } </s>

Callback used to implement the .inst directive .


<s> static bool iq2000_return_in_memory ( tree type , tree fntype ATTRIBUTE_UNUSED ) { return ( ( int_size_in_bytes ( type ) > ( 2 * UNITS_PER_WORD ) ) || ( int_size_in_bytes ( type ) == - 1 ) ) ; } </s>

Worker function for TARGET_RETURN_IN_MEMORY .


<s> static void alpha_setup_incoming_varargs ( cumulative_args_t pcum , machine_mode mode , tree type , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS cum = * get_cumulative_args ( pcum ) ; targetm . calls . function_arg_advance ( pack_cumulative_args ( & cum ) , mode , type , true ) ; if ( cum . num_args < 6 ) { if ( ! no_rtl ) { emit_move_insn ( gen_rtx_REG ( DImode , 1 ) , virtual_incoming_args_rtx ) ; emit_insn ( gen_arg_home ( ) ) ; } * pretend_size = 7 * UNITS_PER_WORD ; } if ( cum >= 6 ) return ; if ( ! no_rtl ) { int count ; alias_set_type set = get_varargs_alias_set ( ) ; rtx tmp ; count = cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( count > 6 - cum ) count = 6 - cum ; gcc_assert ( ( VA_LIST_MAX_FPR_SIZE & 3 ) == 3 ) ; if ( cfun -> va_list_fpr_size & 1 ) { tmp = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , virtual_incoming_args_rtx , ( cum + 6 ) * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( 16 + cum , tmp , count ) ; } if ( cfun -> va_list_fpr_size & 2 ) { tmp = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , virtual_incoming_args_rtx , cum * UNITS_PER_WORD ) ) ; MEM_NOTRAP_P ( tmp ) = 1 ; set_mem_alias_set ( tmp , set ) ; move_block_from_reg ( 16 + cum + TARGET_FPREGS * 32 , tmp , count ) ; } } * pretend_size = 12 * UNITS_PER_WORD ; } </s>

Perform any needed actions needed for a function that is receiving a variable number of arguments .


<s> TargetLowering :: ConstraintType MSP430TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'r' : return C_RegisterClass ; default : break ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static bool vspltis_constant ( rtx op , unsigned step , unsigned copies ) { machine_mode mode = GET_MODE ( op ) ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned i ; unsigned nunits ; unsigned bitsize ; unsigned mask ; HOST_WIDE_INT val ; HOST_WIDE_INT splat_val ; HOST_WIDE_INT msb_val ; if ( mode == V2DImode || mode == V2DFmode || mode == V1TImode ) return false ; nunits = GET_MODE_NUNITS ( mode ) ; bitsize = GET_MODE_BITSIZE ( inner ) ; mask = GET_MODE_MASK ( inner ) ; val = const_vector_elt_as_int ( op , BYTES_BIG_ENDIAN ? nunits - 1 : 0 ) ; splat_val = val ; msb_val = val >= 0 ? 0 : - 1 ; if ( val == 0 && step > 1 ) { for ( i = 1 ; i < nunits ; ++ i ) { unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i ; HOST_WIDE_INT elt_val = const_vector_elt_as_int ( op , elt ) ; if ( ( i & ( step - 1 ) ) == step - 1 ) { if ( ! EASY_VECTOR_MSB ( elt_val , inner ) ) break ; } else if ( elt_val ) break ; } if ( i == nunits ) return true ; } for ( i = 2 ; i <= copies ; i *= 2 ) { HOST_WIDE_INT small_val ; bitsize /= 2 ; small_val = splat_val >> bitsize ; mask >>= bitsize ; if ( splat_val != ( ( HOST_WIDE_INT ) ( ( unsigned HOST_WIDE_INT ) small_val << bitsize ) | ( small_val & mask ) ) ) return false ; splat_val = small_val ; inner = smallest_int_mode_for_size ( bitsize ) ; } if ( EASY_VECTOR_15 ( splat_val ) ) ; else if ( EASY_VECTOR_15_ADD_SELF ( splat_val ) && ( splat_val >= 0 || ( step == 1 && copies == 1 ) ) ) ; else if ( EASY_VECTOR_MSB ( splat_val , inner ) && step == 1 ) ; else return false ; for ( i = 1 ; i < nunits ; ++ i ) { HOST_WIDE_INT desired_val ; unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i ; if ( ( i & ( step - 1 ) ) == 0 ) desired_val = val ; else desired_val = msb_val ; if ( desired_val != const_vector_elt_as_int ( op , elt ) ) return false ; } return true ; } </s>

Return true if OP can be synthesized with a particular vspltisb , vspltish or vspltisw instruction . OP is a CONST_VECTOR . Which instruction is used depends on STEP and COPIES , one of which will be 1 . If COPIES > 1 , all items are set to the same value and contain COPIES replicas of the vsplt 's operand ; if STEP > 1 , one in STEP elements is set to the vsplt 's operand and the others are set to the value of the operand 's msb .


<s>
void
ARMInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
ARMFunctionInfo
*
AFI
=
MF
.
getInfo
<
ARMFunctionInfo
>
(
)
;
if
(
AFI
->
isThumbFunction
(
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
else
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
LDR
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FLDD
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
else
{
assert
(
RC
==
ARM
::
SPRRegisterClass
&&
"Unknown regclass!"
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
FLDS
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM
ARM::GPRRegisterClass
ARM
ARM
ARM::tRestore
0
ARM::LDR
0
0
ARM::DPRRegisterClass
ARM::FLDD
0
ARM::SPRRegisterClass
"Unknown regclass!"
ARM::FLDS
0


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreservedID ( LiveVariablesID ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static int get_some_local_dynamic_name_1 ( rtx * px , void * data ATTRIBUTE_UNUSED ) { rtx x = * px ; if ( GET_CODE ( x ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) { x = get_pool_constant ( x ) ; return for_each_rtx ( & x , get_some_local_dynamic_name_1 , 0 ) ; } if ( GET_CODE ( x ) == SYMBOL_REF && tls_symbolic_operand ( x ) == TLS_MODEL_LOCAL_DYNAMIC ) { cfun -> machine -> some_ld_name = XSTR ( x , 0 ) ; return 1 ; } return 0 ; } </s>


<s>
void
ARMTTIImpl
::
getUnrollingPreferences
(
Loop
*
L
,
ScalarEvolution
&
SE
,
TTI
::
UnrollingPreferences
&
UP
)
{
UP
.
UpperBound
=
true
;
if
(
!
ST
->
isMClass
(
)
)
return
BasicTTIImplBase
::
getUnrollingPreferences
(
L
,
SE
,
UP
)
;
UP
.
OptSizeThreshold
=
0
;
UP
.
PartialOptSizeThreshold
=
0
;
if
(
L
->
getHeader
(
)
->
getParent
(
)
->
hasOptSize
(
)
)
return
;
SmallVector
<
BasicBlock
*
,
4
>
ExitingBlocks
;
L
->
getExitingBlocks
(
ExitingBlocks
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Loop has:\n"
<<
"Blocks: "
<<
L
->
getNumBlocks
(
)
<<
"\n"
<<
"Exit blocks: "
<<
ExitingBlocks
.
size
(
)
<<
"\n"
)
;
if
(
ExitingBlocks
.
size
(
)
>
2
)
return
;
if
(
ST
->
hasBranchPredictor
(
)
&&
L
->
getNumBlocks
(
)
>
4
)
return
;
if
(
getBooleanLoopAttribute
(
L
,
"llvm.loop.isvectorized"
)
)
return
;
InstructionCost
Cost
=
0
;
for
(
auto
*
BB
:
L
->
getBlocks
(
)
)
{
for
(
auto
&
I
:
*
BB
)
{
if
(
I
.
getType
(
)
->
isVectorTy
(
)
)
return
;
if
(
isa
<
CallInst
>
(
I
)
||
isa
<
InvokeInst
>
(
I
)
)
{
if
(
const
Function
*
F
=
cast
<
CallBase
>
(
I
)
.
getCalledFunction
(
)
)
{
if
(
!
isLoweredToCall
(
F
)
)
continue
;
}
return
;
}
SmallVector
<
const
Value
*
,
4
>
Operands
(
I
.
operand_values
(
)
)
;
Cost
+=
getUserCost
(
&
I
,
Operands
,
TargetTransformInfo
::
TCK_SizeAndLatency
)
;
}
}
LLVM_DEBUG
(
dbgs
(
)
<<
"Cost of loop: "
<<
Cost
<<
"\n"
)
;
UP
.
Partial
=
true
;
UP
.
Runtime
=
true
;
UP
.
UnrollRemainder
=
true
;
UP
.
DefaultUnrollRuntimeCount
=
4
;
UP
.
UnrollAndJam
=
true
;
UP
.
UnrollAndJamInnerLoopThreshold
=
60
;
if
(
Cost
<
12
)
UP
.
Force
=
true
;
}
</s>

Get target-customized preferences for the generic loop unrolling transformation .


<s> MachineInstr * AlphaInstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops , int FrameIndex ) const { if ( Ops . size ( ) != 1 ) return NULL ; unsigned Opc = MI -> getOpcode ( ) ; MachineInstr * NewMI = NULL ; switch ( Opc ) { default : break ; case Alpha :: BISr : case Alpha :: CPYSS : case Alpha :: CPYST : if ( MI -> getOperand ( 1 ) . getReg ( ) == MI -> getOperand ( 2 ) . getReg ( ) ) { if ( Ops [ 0 ] == 0 ) { unsigned InReg = MI -> getOperand ( 1 ) . getReg ( ) ; bool isKill = MI -> getOperand ( 1 ) . isKill ( ) ; Opc = ( Opc == Alpha :: BISr ) ? Alpha :: STQ : ( ( Opc == Alpha :: CPYSS ) ? Alpha :: STS : Alpha :: STT ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( Opc ) ) . addReg ( InReg , false , false , isKill ) . addFrameIndex ( FrameIndex ) . addReg ( Alpha :: F31 ) ; } else { unsigned OutReg = MI -> getOperand ( 0 ) . getReg ( ) ; bool isDead = MI -> getOperand ( 0 ) . isDead ( ) ; Opc = ( Opc == Alpha :: BISr ) ? Alpha :: LDQ : ( ( Opc == Alpha :: CPYSS ) ? Alpha :: LDS : Alpha :: LDT ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( Opc ) ) . addReg ( OutReg , true , false , false , isDead ) . addFrameIndex ( FrameIndex ) . addReg ( Alpha :: F31 ) ; } } break ; } return NewMI ; } </s>

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address , not just from a specific stack slot .


<s> SDValue VETargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { assert ( isPositionIndependent ( ) ) ; SDLoc DL ( Table ) ; Function * Function = & DAG . getMachineFunction ( ) . getFunction ( ) ; assert ( Function != nullptr ) ; auto PtrTy = getPointerTy ( DAG . getDataLayout ( ) , Function -> getAddressSpace ( ) ) ; SDValue Op = DAG . getGlobalAddress ( Function , DL , PtrTy ) ; SDValue HiLo = makeHiLoPair ( Op , VEMCExpr :: VK_VE_GOTOFF_HI32 , VEMCExpr :: VK_VE_GOTOFF_LO32 , DAG ) ; SDValue GlobalBase = DAG . getNode ( VEISD :: GLOBAL_BASE_REG , DL , PtrTy ) ; return DAG . getNode ( ISD :: ADD , DL , PtrTy , GlobalBase , HiLo ) ; } </s>

Returns relocation base for the given PIC jumptable .

VE VE VE VE VE VE VEISD::GLOBAL_BASE_REG ISD::ADD


<s>
SDNode
*
MSP430DAGToDAGISel
::
Select
(
SDValue
Op
)
{
SDNode
*
Node
=
Op
.
getNode
(
)
;
DebugLoc
dl
=
Op
.
getDebugLoc
(
)
;
DOUT
(
llvm
::
dbgs
(
)
<<
std
::
string
(
Indent
,
' '
)
<<
"Selecting: "
;
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
DOUT
(
llvm
::
dbgs
(
)
<<
"\n"
;
Indent
+=
2
;
if
(
Node
->
isMachineOpcode
(
)
)
{
DOUT
(
llvm
::
dbgs
(
)
<<
std
::
string
(
Indent
2
,
' '
)
<<
"== "
;
DEBUG
(
Node
->
dump
(
CurDAG
)
)
;
DOUT
(
llvm
::
dbgs
(
)
<<
"\n"
;
Indent
-=
2
;
return
;
}
switch
(
Node
->
getOpcode
(
)
)
{
default
:
break
;
case
ISD
::
FrameIndex
:
{
assert
(
Op
.
getValueType
(
)
==
MVT
::
i16
)
;
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
MVT
::
i16
)
;
if
(
Node
->
hasOneUse
(
)
)
return
CurDAG
->
SelectNodeTo
(
Node
,
MSP430
::
ADD16ri
,
MVT
::
i16
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i16
)
)
;
return
CurDAG
->
getTargetNode
(
MSP430
::
ADD16ri
,
dl
,
MVT
::
i16
,
TFI
,
CurDAG
->
getTargetConstant
(
0
,
MVT
::
i16
)
)
;
}
}
SDNode
*
ResNode
=
SelectCode
(
Op
)
;
DOUT
(
llvm
::
dbgs
(
)
<<
std
::
string
(
Indent
2
,
' '
)
<<
"=> "
;
if
(
ResNode
==
||
ResNode
==
Op
.
getNode
(
)
)
DEBUG
(
Op
.
getNode
(
)
->
dump
(
CurDAG
)
)
;
else
DEBUG
(
ResNode
->
dump
(
CurDAG
)
)
;
DOUT
(
llvm
::
dbgs
(
)
<<
"\n"
;
Indent
-=
2
;
return
ResNode
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> void PPCInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; SmallVector < MachineInstr * , 4 > NewMIs ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ; for ( unsigned i = 0 , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ; } </s>


<s> int eligible_for_return_delay ( rtx trial ) { rtx pat ; if ( GET_CODE ( trial ) != INSN || GET_CODE ( PATTERN ( trial ) ) != SET ) return 0 ; if ( get_attr_length ( trial ) != 1 ) return 0 ; if ( num_gfregs ) return 0 ; if ( current_function_calls_eh_return ) return 0 ; if ( sparc_leaf_function_p ) return get_attr_in_uncond_branch_delay ( trial ) == IN_UNCOND_BRANCH_DELAY_TRUE ; pat = PATTERN ( trial ) ; if ( GET_CODE ( SET_DEST ( pat ) ) != REG || ( REGNO ( SET_DEST ( pat ) ) >= 8 && REGNO ( SET_DEST ( pat ) ) < 24 ) ) return 0 ; if ( REGNO ( SET_DEST ( pat ) ) >= 32 ) return ( TARGET_V9 && ! epilogue_renumber ( & pat , 1 ) && ( get_attr_in_uncond_branch_delay ( trial ) == IN_UNCOND_BRANCH_DELAY_TRUE ) ) ; return eligible_for_restore_insn ( trial , true ) ; } </s>

Return nonzero if TRIAL can go into the function return 's delay slot .


<s> bool hasLowDefLatency ( const TargetSchedModel & SchedModel , const MachineInstr & DefMI , unsigned DefIdx ) const override { return false ; } </s>

Compute operand latency of a def of 'Reg ' .


<s>
static
void
csky_output_mi_thunk
(
FILE
*
file
,
tree
thunk
ATTRIBUTE_UNUSED
,
HOST_WIDE_INT
delta
,
HOST_WIDE_INT
vcall_offset
,
tree
function
)
{
const
char
*
fnname
=
IDENTIFIER_POINTER
(
DECL_ASSEMBLER_NAME
(
thunk
)
)
;
const
char
*
thiz
=
"a0"
;
const
char
*
reg0
=
"t0"
;
const
char
*
reg1
=
"t1"
;
int
maxoff
=
4096
;
assemble_start_function
(
thunk
,
fnname
)
;
final_start_function
(
emit_barrier
(
)
,
file
,
1
)
;
rtx
fnaddr
=
XEXP
(
DECL_RTL
(
function
)
,
0
)
;
if
(
CSKY_TARGET_ARCH
(
CK801
)
)
{
reg0
=
"l0"
;
reg1
=
"l1"
;
maxoff
=
256
;
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
fprintf
(
file
,
"\tpush\tl0, l1\n"
)
;
else
if
(
delta
>
maxoff
||
delta
<
maxoff
)
fprintf
(
file
,
"\tpush\tl0\n"
)
;
}
if
(
aggregate_value_p
(
TREE_TYPE
(
TREE_TYPE
(
function
)
)
,
function
)
)
thiz
=
"a1"
;
if
(
delta
!=
0
)
{
if
(
delta
>
maxoff
||
delta
<
maxoff
)
{
fprintf
(
file
,
"\tlrw\t%s, %ld\n"
,
reg0
,
(
long
)
delta
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
thiz
,
thiz
,
reg0
)
;
}
else
fprintf
(
file
,
"\t%s\t%s, %s, %ld\n"
,
(
delta
>
0
"addi"
:
"subi"
)
,
thiz
,
thiz
,
(
long
)
(
delta
>
0
delta
:
delta
)
)
;
}
if
(
vcall_offset
!=
0
)
{
fprintf
(
file
,
"\tld.w\t%s, (%s, 0)\n"
,
reg0
,
thiz
)
;
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
{
fprintf
(
file
,
"\tlrw\t%s, %ld\n"
,
reg1
,
(
long
)
vcall_offset
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
reg0
,
reg0
,
reg1
)
;
}
else
fprintf
(
file
,
"\t%s\t%s, %s, %ld\n"
,
(
vcall_offset
>
0
"addi"
:
"subi"
)
,
reg0
,
reg0
,
(
long
)
(
vcall_offset
>
0
vcall_offset
:
vcall_offset
)
)
;
fprintf
(
file
,
"\tld.w\t%s, (%s, 0)\n"
,
reg0
,
reg0
)
;
fprintf
(
file
,
"\taddu\t%s, %s, %s\n"
,
thiz
,
thiz
,
reg0
)
;
}
if
(
CSKY_TARGET_ARCH
(
CK801
)
)
{
if
(
vcall_offset
>
maxoff
||
vcall_offset
<
maxoff
)
{
fprintf
(
file
,
"\tld.w\tl0, (sp, 0)\n"
)
;
fprintf
(
file
,
"\tld.w\tl1, (sp, 4)\n"
)
;
fprintf
(
file
,
"\taddi\t sp, sp, 8\n"
)
;
}
else
if
(
delta
>
maxoff
||
delta
<
maxoff
)
{
fprintf
(
file
,
"\tld.w\tl0, (sp, 0)\n"
)
;
fprintf
(
file
,
"\taddi\tsp, sp, 4\n"
)
;
}
}
fprintf
(
file
,
"\tjbr\t"
)
;
output_addr_const
(
file
,
fnaddr
)
;
fprintf
(
file
,
"\n"
)
;
final_end_function
(
)
;
assemble_end_function
(
thunk
,
fnname
)
;
}
</s>

Implement TARGET_ASM_OUTPUT_MI_THUNK . Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s>
void
SIMCCodeEmitter
::
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
verifyInstructionPredicates
(
MI
,
computeAvailableFeatures
(
STI
.
getFeatureBits
(
)
)
)
;
uint64_t
Encoding
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
MI
.
getOpcode
(
)
)
;
unsigned
bytes
=
Desc
.
getSize
(
)
;
for
(
unsigned
i
=
0
;
i
<
bytes
;
i
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Encoding
>>
(
8
*
i
)
)
&
0xff
)
)
;
}
if
(
AMDGPU
::
isGFX10
(
STI
)
&&
Desc
.
TSFlags
&
SIInstrFlags
::
MIMG
)
{
int
vaddr0
=
AMDGPU
::
getNamedOperandIdx
(
MI
.
getOpcode
(
)
,
AMDGPU
::
OpName
::
vaddr0
)
;
int
srsrc
=
AMDGPU
::
getNamedOperandIdx
(
MI
.
getOpcode
(
)
,
AMDGPU
::
OpName
::
srsrc
)
;
assert
(
vaddr0
>=
0
&&
srsrc
>
vaddr0
)
;
unsigned
NumExtraAddrs
=
srsrc
vaddr0
1
;
unsigned
NumPadding
=
(
NumExtraAddrs
)
&
3
;
for
(
unsigned
i
=
0
;
i
<
NumExtraAddrs
;
++
i
)
OS
.
write
(
(
uint8_t
)
getMachineOpValue
(
MI
,
MI
.
getOperand
(
vaddr0
+
1
+
i
)
,
Fixups
,
STI
)
)
;
for
(
unsigned
i
=
0
;
i
<
NumPadding
;
++
i
)
OS
.
write
(
0
)
;
}
if
(
(
bytes
>
8
&&
STI
.
getFeatureBits
(
)
[
AMDGPU
::
FeatureVOP3Literal
]
)
||
(
bytes
>
4
&&
!
STI
.
getFeatureBits
(
)
[
AMDGPU
::
FeatureVOP3Literal
]
)
)
return
;
for
(
unsigned
i
=
0
,
e
=
Desc
.
getNumOperands
(
)
;
i
<
e
;
++
i
)
{
if
(
!
AMDGPU
::
isSISrcOperand
(
Desc
,
i
)
)
continue
;
const
MCOperand
&
Op
=
MI
.
getOperand
(
i
)
;
if
(
getLitEncoding
(
Op
,
Desc
.
OpInfo
[
i
]
,
STI
)
!=
255
)
continue
;
int64_t
Imm
=
0
;
if
(
Op
.
isImm
(
)
)
Imm
=
Op
.
getImm
(
)
;
else
if
(
Op
.
isExpr
(
)
)
{
if
(
const
auto
*
C
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
)
Imm
=
C
->
getValue
(
)
;
}
else
if
(
!
Op
.
isExpr
(
)
)
llvm_unreachable
(
"Must be immediate or expr"
)
;
for
(
unsigned
j
=
0
;
j
<
4
;
j
++
)
{
OS
.
write
(
(
uint8_t
)
(
(
Imm
>>
(
8
*
j
)
)
&
0xff
)
)
;
}
break
;
}
}
</s>

Encode the given Inst to bytes and append to CB .


<s> bool aarch64_simd_imm_zero_p ( rtx x , machine_mode mode ) { return x == CONST0_RTX ( mode ) ; } </s>

Return true if X is a uniform vector where all elements are either the floating-point constant 0.0 or the integer constant 0 .


<s> static bool canonicalize_vector_int_perm ( const struct expand_vec_perm_d * d , struct expand_vec_perm_d * nd ) { int i ; machine_mode mode = VOIDmode ; switch ( d -> vmode ) { case E_V8QImode : mode = V4HImode ; break ; case E_V16QImode : mode = V8HImode ; break ; case E_V32QImode : mode = V16HImode ; break ; case E_V64QImode : mode = V32HImode ; break ; case E_V4HImode : mode = V2SImode ; break ; case E_V8HImode : mode = V4SImode ; break ; case E_V16HImode : mode = V8SImode ; break ; case E_V32HImode : mode = V16SImode ; break ; case E_V4SImode : mode = V2DImode ; break ; case E_V8SImode : mode = V4DImode ; break ; case E_V16SImode : mode = V8DImode ; break ; default : return false ; } for ( i = 0 ; i < d -> nelt ; i += 2 ) if ( ( d -> perm [ i ] & 1 ) || d -> perm [ i + 1 ] != d -> perm [ i ] + 1 ) return false ; nd -> vmode = mode ; nd -> nelt = d -> nelt / 2 ; for ( i = 0 ; i < nd -> nelt ; i ++ ) nd -> perm [ i ] = d -> perm [ 2 * i ] / 2 ; if ( GET_MODE_INNER ( mode ) != DImode ) canonicalize_vector_int_perm ( nd , nd ) ; if ( nd != d ) { nd -> one_operand_p = d -> one_operand_p ; nd -> testing_p = d -> testing_p ; if ( d -> op0 == d -> op1 ) nd -> op0 = nd -> op1 = gen_lowpart ( nd -> vmode , d -> op0 ) ; else { nd -> op0 = gen_lowpart ( nd -> vmode , d -> op0 ) ; nd -> op1 = gen_lowpart ( nd -> vmode , d -> op1 ) ; } if ( d -> testing_p ) nd -> target = gen_raw_REG ( nd -> vmode , LAST_VIRTUAL_REGISTER + 1 ) ; else nd -> target = gen_reg_rtx ( nd -> vmode ) ; } return true ; } </s>

For V * [ QHS ] Imode permutations , check if the same permutation ca n't be performed in a 2x , 4x or 8x wider inner mode .


"Missing call preserved mask for calling convention"

This function fills Ops , which is the list of operands that will later be used when a function call node is created .


<s> bool HexagonInstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const { return false ; } </s>

Returns true if the first specified predicate subsumes the second , e.g .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>


<s> static unsigned HOST_WIDE_INT ix86_asan_shadow_offset ( void ) { return SUBTARGET_SHADOW_OFFSET ; } </s>

Implement the TARGET_ASAN_SHADOW_OFFSET hook .


<s> bool X86TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth >= 32 && ST -> hasAVX ( ) ) || ( DataWidth >= 8 && ST -> hasBWI ( ) ) ; } </s>

Return true if the target supports masked load .


<s>
const
MCPhysReg
*
LoongArchRegisterInfo
::
getCalleeSavedRegs
(
const
MachineFunction
*
MF
)
const
{
auto
&
Subtarget
=
MF
->
getSubtarget
<
LoongArchSubtarget
>
(
)
;
switch
(
Subtarget
.
getTargetABI
(
)
)
{
default
:
llvm_unreachable
(
"Unrecognized ABI"
)
;
case
LoongArchABI
::
ABI_ILP32S
:
case
LoongArchABI
::
ABI_LP64S
:
return
CSR_ILP32S_LP64S_SaveList
;
case
LoongArchABI
::
ABI_ILP32F
:
case
LoongArchABI
::
ABI_LP64F
:
return
CSR_ILP32F_LP64F_SaveList
;
case
LoongArchABI
::
ABI_ILP32D
:
case
LoongArchABI
::
ABI_LP64D
:
return
CSR_ILP32D_LP64D_SaveList
;
}
}
</s>


<s> void ARMJITInfo :: Initialize ( const MachineFunction & MF , bool isPIC ) { const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; ConstPoolId2AddrMap . resize ( AFI -> getNumPICLabels ( ) ) ; JumpTableId2AddrMap . resize ( AFI -> getNumJumpTables ( ) ) ; IsPIC = isPIC ; } </s>

This method must be called before any actual lowering is done .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly CFG Stackify"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool n10_consumed_by_ex_dep_p ( rtx_insn * consumer , rtx def_reg ) { rtx use_rtx ; switch ( get_attr_type ( consumer ) ) { case TYPE_ALU : case TYPE_PBSAD : case TYPE_MUL : case TYPE_DALU : case TYPE_DALU64 : case TYPE_DMUL : case TYPE_DPACK : case TYPE_DINSB : case TYPE_DCMP : case TYPE_DCLIP : case TYPE_DALUROUND : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : case TYPE_DMAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , 0 ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_DWEXT : return wext_odd_dep_p ( consumer , def_reg ) ; case TYPE_DBPICK : return bpick_ra_rb_dep_p ( consumer , def_reg ) ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default : gcc_unreachable ( ) ; } if ( reg_overlap_p ( def_reg , use_rtx ) ) return true ; return false ; } </s>

Check the dependency between the producer defining DEF_REG and CONSUMER requiring input operand at EX .


<s> static bool h8300_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { if ( GET_CODE ( addr ) == PLUS && h8300_get_index ( XEXP ( addr , 0 ) , VOIDmode , 0 ) != XEXP ( addr , 0 ) ) return true ; return false ; } </s>

Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P . On the H8/300 , the predecrement and postincrement address depend thus ( the amount of decrement or increment being the length of the operand ) .


<s> SDValue HexagonSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { flag_aligned_memcpy = false ; if ( ( Align & 0x3 ) == 0 ) { ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; if ( ConstantSize ) { uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; if ( ( SizeVal > 32 ) && ( ( SizeVal % 8 ) == 0 ) ) flag_aligned_memcpy = true ; } } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memcpy .


<s> const char * Z80TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return NULL ; case Z80ISD :: WRAPPER : return "Z80ISD::WRAPPER" ; case Z80ISD :: SCF : return "Z80ISD::SCF" ; case Z80ISD :: CCF : return "Z80ISD::CCF" ; case Z80ISD :: RLC : return "Z80ISD::RLC" ; case Z80ISD :: RRC : return "Z80ISD::RRC" ; case Z80ISD :: RL : return "Z80ISD::RL" ; case Z80ISD :: RR : return "Z80ISD::RR" ; case Z80ISD :: SLA : return "Z80ISD::SLA" ; case Z80ISD :: SRA : return "Z80ISD::SRA" ; case Z80ISD :: SLL : return "Z80ISD::SLL" ; case Z80ISD :: SRL : return "Z80ISD::SRL" ; case Z80ISD :: SHL : return "Z80ISD::SHL" ; case Z80ISD :: LSHR : return "Z80ISD::LSHR" ; case Z80ISD :: ASHR : return "Z80ISD::ASHR" ; case Z80ISD :: CP : return "Z80ISD::CP" ; case Z80ISD :: SELECT_CC : return "Z80ISD::SELECT_CC" ; case Z80ISD :: BR_CC : return "Z80ISD::BR_CC" ; case Z80ISD :: CALL : return "Z80ISD::CALL" ; case Z80ISD :: RET : return "Z80ISD::RET" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> int AArch64FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute ( Attribute :: SanitizeHWAddress ) , false ) ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> const SystemZRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> const HexagonGOT & HexagonLDBackend :: getGOT ( ) const { assert ( m_pGOT != NULL ) ; return * m_pGOT ; } </s>

Return a pseudo source value referencing the global offset table ( or something the like ) .


<s> Optional < MCFixupKind > RISCVAsmBackend :: getFixupKind ( StringRef Name ) const { if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { unsigned Type ; Type = llvm :: StringSwitch < unsigned > ( Name ) . Case ( "BFD_RELOC_NONE" , ELF :: R_RISCV_NONE ) . Case ( "BFD_RELOC_32" , ELF :: R_RISCV_32 ) . Case ( "BFD_RELOC_64" , ELF :: R_RISCV_64 ) . Default ( - 1u ) ; if ( Type != - 1u ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; } return None ; } </s>

getFixupKind - Get the fixup kind of this expression .


<s> std :: pair < const TargetRegisterClass * , uint8_t > X86TargetLowering :: findRepresentativeClass ( MVT VT ) const { const TargetRegisterClass * RRC = nullptr ; uint8_t Cost = 1 ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : case MVT :: i64 : RRC = Subtarget -> is64Bit ( ) ? ( const TargetRegisterClass * ) & X86 :: GR64RegClass : ( const TargetRegisterClass * ) & X86 :: GR32RegClass ; break ; case MVT :: x86mmx : RRC = & X86 :: VR64RegClass ; break ; case MVT :: f32 : case MVT :: f64 : case MVT :: v16i8 : case MVT :: v8i16 : case MVT :: v4i32 : case MVT :: v2i64 : case MVT :: v4f32 : case MVT :: v2f64 : case MVT :: v32i8 : case MVT :: v8i32 : case MVT :: v4i64 : case MVT :: v8f32 : case MVT :: v4f64 : RRC = & X86 :: VR128RegClass ; break ; } return std :: make_pair ( RRC , Cost ) ; } </s>

Return the largest legal super-reg register class of the register class for the specified type and its associated `` cost '' .


<s> const char * GBZ80MCExpr :: getName ( ) const { const auto & Modifier = std :: find_if ( std :: begin ( ModifierNames ) , std :: end ( ModifierNames ) , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> Spelling ; } return nullptr ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static bool epiphany_function_ok_for_sibcall ( tree decl , tree exp ) { bool cfun_interrupt_p , call_interrupt_p ; cfun_interrupt_p = EPIPHANY_INTERRUPT_P ( epiphany_compute_function_type ( current_function_decl ) ) ; if ( decl ) call_interrupt_p = EPIPHANY_INTERRUPT_P ( epiphany_compute_function_type ( decl ) ) ; else { tree fn_type = TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ; gcc_assert ( POINTER_TYPE_P ( fn_type ) ) ; fn_type = TREE_TYPE ( fn_type ) ; gcc_assert ( TREE_CODE ( fn_type ) == FUNCTION_TYPE || TREE_CODE ( fn_type ) == METHOD_TYPE ) ; call_interrupt_p = lookup_attribute ( "interrupt" , TYPE_ATTRIBUTES ( fn_type ) ) != NULL ; } if ( cfun_interrupt_p || call_interrupt_p ) return false ; return true ; } </s>

Return nonzero if it is ok to make a tail-call to DECL .


<s> static bool must_save_fp_p ( void ) { return frame_pointer_needed || regs_ever_live [ REG_FP ] ; } </s>

Determine if we are going to save the frame pointer in the prologue .


<s>
void
BPFDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
dbgs
(
)
<<
'\n'
)
;
return
;
}
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
SDIV
:
{
DebugLoc
Empty
;
const
DebugLoc
&
DL
=
Node
->
getDebugLoc
(
)
;
if
(
DL
!=
Empty
)
errs
(
)
<<
"Error at line "
<<
DL
.
getLine
(
)
<<
": "
;
else
errs
(
)
<<
"Error: "
;
errs
(
)
<<
"Unsupport signed division for DAG: "
;
Node
->
print
(
errs
(
)
,
CurDAG
)
;
errs
(
)
<<
"Please convert to unsigned div/mod.\n"
;
break
;
}
case
ISD
::
INTRINSIC_W_CHAIN
:
{
unsigned
IntNo
=
cast
<
ConstantSDNode
>
(
Node
->
getOperand
(
1
)
)
->
getZExtValue
(
)
;
switch
(
IntNo
)
{
case
Intrinsic
::
bpf_load_byte
:
case
Intrinsic
::
bpf_load_half
:
case
Intrinsic
::
bpf_load_word
:
{
SDLoc
DL
(
Node
)
;
SDValue
Chain
=
Node
->
getOperand
(
0
)
;
SDValue
N1
=
Node
->
getOperand
(
1
)
;
SDValue
Skb
=
Node
->
getOperand
(
2
)
;
SDValue
N3
=
Node
->
getOperand
(
3
)
;
SDValue
R6Reg
=
CurDAG
->
getRegister
(
BPF
::
R6
,
MVT
::
i64
)
;
Chain
=
CurDAG
->
getCopyToReg
(
Chain
,
DL
,
R6Reg
,
Skb
,
SDValue
(
)
)
;
Node
=
CurDAG
->
UpdateNodeOperands
(
Node
,
Chain
,
N1
,
R6Reg
,
N3
)
;
break
;
}
}
break
;
}
case
ISD
::
FrameIndex
:
{
int
FI
=
cast
<
FrameIndexSDNode
>
(
Node
)
->
getIndex
(
)
;
EVT
VT
=
Node
->
getValueType
(
0
)
;
SDValue
TFI
=
CurDAG
->
getTargetFrameIndex
(
FI
,
VT
)
;
unsigned
Opc
=
BPF
::
MOV_rr
;
if
(
Node
->
hasOneUse
(
)
)
{
CurDAG
->
SelectNodeTo
(
Node
,
Opc
,
VT
,
TFI
)
;
return
;
}
ReplaceNode
(
Node
,
CurDAG
->
getMachineNode
(
Opc
,
SDLoc
(
Node
)
,
VT
,
TFI
)
)
;
return
;
}
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s>
static
void
aarch64_start_file
(
void
)
{
if
(
selected_arch
)
{
asm_fprintf
(
asm_out_file
,
"\t.arch %s"
,
selected_arch
->
name
)
;
aarch64_print_extension
(
)
;
}
else
if
(
selected_cpu
)
{
const
char
*
truncated_name
=
aarch64_rewrite_selected_cpu
(
selected_cpu
->
name
)
;
asm_fprintf
(
asm_out_file
,
"\t.cpu %s"
,
truncated_name
)
;
aarch64_print_extension
(
)
;
}
default_file_start
(
)
;
}
</s>

Implements TARGET_ASM_FILE_START . Output the assembly header .


<s> void rs6000_scale_v2df ( rtx tgt , rtx src , int scale ) { HOST_WIDE_INT hwi_scale ( scale ) ; REAL_VALUE_TYPE r_pow ; rtvec v = rtvec_alloc ( 2 ) ; rtx elt ; rtx scale_vec = gen_reg_rtx ( V2DFmode ) ; ( void ) real_powi ( & r_pow , DFmode , & dconst2 , hwi_scale ) ; elt = const_double_from_real_value ( r_pow , DFmode ) ; RTVEC_ELT ( v , 0 ) = elt ; RTVEC_ELT ( v , 1 ) = elt ; rs6000_expand_vector_init ( scale_vec , gen_rtx_PARALLEL ( V2DFmode , v ) ) ; emit_insn ( gen_mulv2df3 ( tgt , src , scale_vec ) ) ; } </s>

Scale a V2DF vector SRC by two to the SCALE and place in TGT .


<s> static int nios2_address_cost ( rtx address , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) { if ( nios2_plus_large_constant_p ( address ) ) return COSTS_N_INSNS ( 1 ) ; if ( nios2_large_constant_p ( address ) ) { if ( GET_CODE ( address ) == CONST ) return COSTS_N_INSNS ( 1 ) ; else return COSTS_N_INSNS ( 0 ) ; } return COSTS_N_INSNS ( 0 ) ; } </s>

Implement TARGET_ADDRESS_COST . Experimentation has shown that we get better code by penalizing the the ( plus reg symbolic_constant ) and ( plus reg ( const ... ) ) forms but giving ( plus reg symbol_ref ) address modes the same cost as those that do n't require splitting . Also , from a theoretical point of view : - This is in line with the recommendation in the GCC internals documentation to make address forms involving multiple registers more expensive than single-register forms . - OTOH it still encourages fwprop1 to propagate constants into address expressions more aggressively . - We should discourage splitting ( symbol + offset ) into hi/lo pairs to allow CSE'ing the symbol when it 's used with more than one offset , but not so heavily as to avoid this addressing mode at all .


<s> bool HexagonInstrInfo :: doesNotReturn ( const MachineInstr & CallMI ) const { unsigned Opc = CallMI . getOpcode ( ) ; return Opc == Hexagon :: PS_call_nr || Opc == Hexagon :: PS_callr_nr ; } </s>

Determine if the function can not return .


<s>
StringRef
getPassName
(
)
const
override
{
return
"WebAssembly Set p2align Operands"
;
}
</s>

getPassName - Return a nice clean name for a pass .

WebAssembly
"WebAssembly Set p2align Operands"


<s>
int
X86FrameLowering
::
getFrameIndexReferencePreferSP
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
,
bool
IgnoreSPUpdates
)
const
{
const
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
uint64_t
StackSize
=
MFI
.
getStackSize
(
)
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
&&
TRI
->
needsStackRealignment
(
MF
)
&&
!
STI
.
isTargetWin64
(
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
const
TargetFrameLowering
*
TFI
=
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
;
if
(
!
IgnoreSPUpdates
&&
!
TFI
->
hasReservedCallFrame
(
MF
)
)
return
getFrameIndexReference
(
MF
,
FI
,
FrameReg
)
;
assert
(
MF
.
getInfo
<
X86MachineFunctionInfo
>
(
)
->
getTCReturnAddrDelta
(
)
>=
0
&&
"we don't handle this case!"
)
;
return
getFrameIndexReferenceSP
(
MF
,
FI
,
FrameReg
,
StackSize
)
;
}
</s>

Same as getFrameIndexReference , except that the stack pointer ( as opposed to the frame pointer ) will be the preferred value for FrameReg .


<s>
bool
HexagonFrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
->
getTarget
(
)
.
getInstrInfo
(
)
;
if
(
CSI
.
empty
(
)
)
{
return
false
;
}
bool
ContiguousRegs
=
true
;
for
(
unsigned
i
=
0
;
i
<
CSI
.
size
(
)
;
++
i
)
{
unsigned
Reg
=
CSI
[
i
]
.
getReg
(
)
;
const
uint16_t
*
SuperReg
=
TRI
->
getSuperRegisters
(
Reg
)
;
const
TargetRegisterClass
*
SuperRegClass
=
0
;
assert
(
SuperReg
[
0
]
&&
!
SuperReg
[
1
]
&&
"Expected exactly one superreg"
)
;
bool
CanUseDblLoad
=
false
;
if
(
ContiguousRegs
&&
(
i
<
CSI
.
size
(
)
1
)
)
{
const
uint16_t
*
SuperRegNext
=
TRI
->
getSuperRegisters
(
CSI
[
i
+
1
]
.
getReg
(
)
)
;
assert
(
SuperRegNext
[
0
]
&&
!
SuperRegNext
[
1
]
&&
"Expected exactly one superreg"
)
;
SuperRegClass
=
TRI
->
getMinimalPhysRegClass
(
SuperReg
[
0
]
)
;
CanUseDblLoad
=
(
SuperRegNext
[
0
]
==
SuperReg
[
0
]
)
;
}
if
(
CanUseDblLoad
)
{
TII
.
loadRegFromStackSlot
(
MBB
,
MI
,
SuperReg
[
0
]
,
CSI
[
i
+
1
]
.
getFrameIdx
(
)
,
SuperRegClass
,
TRI
)
;
MBB
.
addLiveIn
(
SuperReg
[
0
]
)
;
++
i
;
}
else
{
ContiguousRegs
=
false
;
const
TargetRegisterClass
*
RC
=
TRI
->
getMinimalPhysRegClass
(
Reg
)
;
TII
.
loadRegFromStackSlot
(
MBB
,
MI
,
Reg
,
CSI
[
i
]
.
getFrameIdx
(
)
,
RC
,
TRI
)
;
MBB
.
addLiveIn
(
Reg
)
;
}
}
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> bool ARMTargetLowering :: isUsedByReturnOnly ( SDNode * N , SDValue & Chain ) const { if ( N -> getNumValues ( ) != 1 ) return false ; if ( ! N -> hasNUsesOfValue ( 1 , 0 ) ) return false ; SDValue TCChain = Chain ; SDNode * Copy = * N -> use_begin ( ) ; if ( Copy -> getOpcode ( ) == ISD :: CopyToReg ) { if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else if ( Copy -> getOpcode ( ) == ARMISD :: VMOVRRD ) { SDNode * VMov = Copy ; SmallPtrSet < SDNode * , 2 > Copies ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ISD :: CopyToReg ) return false ; Copies . insert ( * UI ) ; } if ( Copies . size ( ) > 2 ) return false ; for ( SDNode :: use_iterator UI = VMov -> use_begin ( ) , UE = VMov -> use_end ( ) ; UI != UE ; ++ UI ) { SDValue UseChain = UI -> getOperand ( 0 ) ; if ( Copies . count ( UseChain . getNode ( ) ) ) Copy = * UI ; else { if ( UI -> getOperand ( UI -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = UseChain ; } } } else if ( Copy -> getOpcode ( ) == ISD :: BITCAST ) { if ( ! Copy -> hasOneUse ( ) ) return false ; Copy = * Copy -> use_begin ( ) ; if ( Copy -> getOpcode ( ) != ISD :: CopyToReg || ! Copy -> hasNUsesOfValue ( 1 , 0 ) ) return false ; if ( Copy -> getOperand ( Copy -> getNumOperands ( ) - 1 ) . getValueType ( ) == MVT :: Glue ) return false ; TCChain = Copy -> getOperand ( 0 ) ; } else { return false ; } bool HasRet = false ; for ( SDNode :: use_iterator UI = Copy -> use_begin ( ) , UE = Copy -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) != ARMISD :: RET_FLAG && UI -> getOpcode ( ) != ARMISD :: INTRET_FLAG ) return false ; HasRet = true ; } if ( ! HasRet ) return false ; Chain = TCChain ; return true ; } </s>

Return true if result of the specified node is used by a return node only .


<s>
SDValue
RISCVTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
switch
(
CallConv
)
{
default
:
report_fatal_error
(
"Unsupported calling convention"
)
;
case
CallingConv
::
C
:
case
CallingConv
::
Fast
:
break
;
}
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
EVT
PtrVT
=
getPointerTy
(
DAG
.
getDataLayout
(
)
)
;
if
(
IsVarArg
)
report_fatal_error
(
"VarArg not supported"
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
analyzeInputArgs
(
MF
,
CCInfo
,
Ins
,
false
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
assert
(
VA
.
getLocVT
(
)
==
Subtarget
.
getXLenVT
(
)
&&
"Unhandled argument type"
)
;
SDValue
ArgValue
;
if
(
VA
.
isRegLoc
(
)
)
ArgValue
=
unpackFromRegLoc
(
DAG
,
Chain
,
VA
,
DL
)
;
else
ArgValue
=
unpackFromMemLoc
(
DAG
,
Chain
,
VA
,
DL
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
Indirect
)
{
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
DL
,
Chain
,
ArgValue
,
MachinePointerInfo
(
)
)
)
;
unsigned
ArgIndex
=
Ins
[
i
]
.
OrigArgIndex
;
assert
(
Ins
[
i
]
.
PartOffset
==
0
)
;
while
(
i
+
1
!=
e
&&
Ins
[
i
+
1
]
.
OrigArgIndex
==
ArgIndex
)
{
CCValAssign
&
PartVA
=
ArgLocs
[
i
+
1
]
;
unsigned
PartOffset
=
Ins
[
i
+
1
]
.
PartOffset
;
SDValue
Address
=
DAG
.
getNode
(
ISD
::
ADD
,
DL
,
PtrVT
,
ArgValue
,
DAG
.
getIntPtrConstant
(
PartOffset
,
DL
)
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
PartVA
.
getValVT
(
)
,
DL
,
Chain
,
Address
,
MachinePointerInfo
(
)
)
)
;
++
i
;
}
continue
;
}
InVals
.
push_back
(
ArgValue
)
;
}
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> const TargetRegisterClass * ARMBaseRegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC , const MachineFunction & ) const { const TargetRegisterClass * Super = RC ; TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case ARM :: GPRRegClassID : case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : case ARM :: QPRRegClassID : case ARM :: QQPRRegClassID : case ARM :: QQQQPRRegClassID : case ARM :: GPRPairRegClassID : return Super ; } Super = * I ++ ; } while ( Super ) ; return RC ; } </s>

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size .


<s> bool AArch64PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; GISelCSEAnalysisWrapper & Wrapper = getAnalysis < GISelCSEAnalysisWrapperPass > ( ) . getCSEWrapper ( ) ; auto * CSEInfo = & Wrapper . get ( TPC . getCSEConfig ( ) ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; AArch64PreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; Combiner C ( PCInfo , & TPC ) ; return C . combineMachineInstrs ( MF , CSEInfo ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> static rtx_insn * arc_next_active_insn ( rtx_insn * insn , struct arc_ccfsm * statep ) { rtx pat ; do { if ( statep ) arc_ccfsm_post_advance ( insn , statep ) ; insn = NEXT_INSN ( insn ) ; if ( ! insn || BARRIER_P ( insn ) ) return NULL ; if ( statep ) arc_ccfsm_advance ( insn , statep ) ; } while ( NOTE_P ( insn ) || ( cfun -> machine -> arc_reorg_started && LABEL_P ( insn ) && ! label_to_alignment ( insn ) ) || ( NONJUMP_INSN_P ( insn ) && ( GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) ) ) ; if ( ! LABEL_P ( insn ) ) { gcc_assert ( INSN_P ( insn ) ) ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == ADDR_VEC || GET_CODE ( pat ) == ADDR_DIFF_VEC ) return NULL ; if ( GET_CODE ( pat ) == SEQUENCE ) return as_a < rtx_insn * > ( XVECEXP ( pat , 0 , 0 ) ) ; } return insn ; } </s>

Like next_active_insn , but return NULL if we find an ADDR_ ( DIFF_ ) VEC , and look inside SEQUENCEs .


<s> const DataLayout * getDataLayout ( ) const { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> bool mprocBSel :: runOnMachineFunction ( MachineFunction & Fn ) { return true ; } </s>


<s> std :: pair < unsigned , const TargetRegisterClass * > AAPTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'r' : return std :: make_pair ( 0U , & AAP :: GR64RegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> void X86DynAllocaExpander :: lower ( MachineInstr * MI , Lowering L ) { const DebugLoc & DL = MI -> getDebugLoc ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getDynAllocaAmount ( MI , MRI ) ; if ( Amount == 0 ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; bool Is64BitAlloca = MI -> getOpcode ( ) == X86 :: DYN_ALLOCA_64 ; assert ( SlotSize == 4 || SlotSize == 8 ) ; switch ( L ) { case TouchAndSub : { assert ( Amount >= SlotSize ) ; unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; LLVM_FALLTHROUGH ; } case Sub : assert ( Amount > 0 ) ; if ( Amount == SlotSize ) { unsigned RegA = Is64Bit ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? X86 :: PUSH64r : X86 :: PUSH32r ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64BitAlloca , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { unsigned RegA = Is64BitAlloca ? X86 :: RAX : X86 :: EAX ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( Is64BitAlloca ? X86 :: SUB64rr : X86 :: SUB32rr ) , StackPtr ) . addReg ( StackPtr ) . addReg ( MI -> getOperand ( 0 ) . getReg ( ) ) ; } break ; } Register AmountReg = MI -> getOperand ( 0 ) . getReg ( ) ; MI -> eraseFromParent ( ) ; if ( MRI -> use_empty ( AmountReg ) ) if ( MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ) AmountDef -> eraseFromParent ( ) ; } </s>


<s> bool SITargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return ( GA -> getAddressSpace ( ) == AMDGPUASI . GLOBAL_ADDRESS || GA -> getAddressSpace ( ) == AMDGPUASI . CONSTANT_ADDRESS ) && ! shouldEmitGOTReloc ( GA -> getGlobal ( ) ) ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> static bool isAssociativeAndCommutative ( unsigned Opcode ) { switch ( Opcode ) { case X86 :: ADDSDrr : case X86 :: ADDSSrr : case X86 :: VADDSDrr : case X86 :: VADDSSrr : case X86 :: MULSDrr : case X86 :: MULSSrr : case X86 :: VMULSDrr : case X86 :: VMULSSrr : return true ; default : return false ; } } </s>

Return true when \P Inst is both associative and commutative .


<s> unsigned DLXInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return 1 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s>
void
X86AsmBackend
::
relaxInstruction
(
const
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
,
MCInst
&
Res
)
const
{
bool
Is16BitMode
=
STI
.
getFeatureBits
(
)
[
X86
::
Mode16Bit
]
;
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
,
Is16BitMode
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Res
=
Inst
;
Res
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


"Add prototypes to prototypes-less functions"


<s> void MipsSEInstrInfo :: adjustStackPtr ( unsigned SP , int64_t Amount , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const MipsSubtarget & STI = Subtarget ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned ADDu = Mips :: ADDu ; unsigned ADDiu = Mips :: ADDiu ; if ( isInt < 14 > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { const TargetRegisterClass * RC = & Mips :: GPR32RegClass ; unsigned Reg = MBB . getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( MBB , I , DL , get ( Mips :: LOAD_IMM_PSEUDO ) , Reg ) . addImm ( Amount ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; } } </s>


<s> unsigned MipsInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( ( MI -> getOpcode ( ) == Mips :: LW ) || ( MI -> getOpcode ( ) == Mips :: LWC1 ) || ( MI -> getOpcode ( ) == Mips :: LDC1 ) ) { if ( ( MI -> getOperand ( 2 ) . isFI ( ) ) && ( MI -> getOperand ( 1 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 1 ) ) ) ) { FrameIndex = MI -> getOperand ( 2 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } } return 0 ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"XCore Assembly Printer"
;
}
</s>


<s>
const
char
*
MipsAsmPrinter
::
getCurrentABIString
(
)
const
{
switch
(
Subtarget
->
getABI
(
)
.
GetEnumValue
(
)
)
{
case
MipsABIInfo
::
ABI
::
O32
:
return
"abi32"
;
case
MipsABIInfo
::
ABI
::
N32
:
return
"abiN32"
;
case
MipsABIInfo
::
ABI
::
N64
:
return
"abi64"
;
case
MipsABIInfo
::
ABI
::
EABI
:
return
"eabi32"
;
default
:
llvm_unreachable
(
"Unknown Mips ABI"
)
;
}
}
</s>


<s> unsigned AArch64TTIImpl :: getMinPrefetchStride ( ) { return ST -> getMinPrefetchStride ( ) ; } </s>

Some HW prefetchers can handle accesses up to a certain constant stride .


<s> TargetTransformInfo :: PopcntSupportKind HexagonTTIImpl :: getPopcntSupport ( unsigned IntTyWidthInBit ) const { return TargetTransformInfo :: PSK_FastHardware ; } </s>

Return hardware support for population count .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Stack Cache Analysis"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void X86AsmParser :: EmitInstruction ( MCInst & Inst , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCStreamer & Out ) { Instrumentation -> InstrumentInstruction ( Inst , Operands , getContext ( ) , Out ) ; Out . EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void seh_emit_push ( FILE * f , struct seh_frame_state * seh , rtx reg ) { unsigned int regno = REGNO ( reg ) ; gcc_checking_assert ( GENERAL_REGNO_P ( regno ) ) ; seh -> sp_offset += UNITS_PER_WORD ; if ( seh -> cfa_reg == stack_pointer_rtx ) seh -> cfa_offset += UNITS_PER_WORD ; fputs ( "\t.seh_pushreg\t" , f ) ; print_reg ( reg , 0 , f ) ; fputc ( '\n' , f ) ; } </s>

Emit an assembler directive to save REG via a PUSH .


<s> bool X86FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < X86MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . callsEHReturn ( ) ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
void
J2InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
DebugLoc
&
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
J2
::
MOV32rr
;
if
(
J2
::
GPRRegClass
.
contains
(
DestReg
)
&&
J2
::
GPRRegClass
.
contains
(
SrcReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
if
(
!
J2
::
GPRRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
[
&
]
(
)
->
unsigned
{
switch
(
SrcReg
)
{
case
J2
::
X
:
\
return
J2
::
ST
##
Type
##
X
CASE
(
S
,
MACL
)
;
CASE
(
S
,
MACH
)
;
CASE
(
S
,
PR
)
;
CASE
(
C
,
GBR
)
;
CASE
(
C
,
VBR
)
;
default
:
llvm_unreachable
(
"Special register not handled."
)
;
}
}
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
;
}
else
if
(
!
J2
::
GPRRegClass
.
contains
(
DestReg
)
)
{
Opc
=
[
&
]
(
)
->
unsigned
{
switch
(
SrcReg
)
{
case
J2
::
X
:
\
return
J2
::
LD
##
Type
##
X
CASE
(
S
,
MACL
)
;
CASE
(
S
,
MACH
)
;
CASE
(
S
,
PR
)
;
CASE
(
C
,
GBR
)
;
CASE
(
C
,
VBR
)
;
default
:
llvm_unreachable
(
"Special register not handled."
)
;
}
}
(
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
}
</s>


<s> static rtx mips16e_save_restore_reg ( bool restore_p , bool reg_parm_p , HOST_WIDE_INT offset , unsigned int regno ) { rtx reg , mem ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( restore_p ) { mips_add_cfa_restore ( reg ) ; return gen_rtx_SET ( reg , mem ) ; } if ( reg_parm_p ) return gen_rtx_SET ( mem , reg ) ; return mips_frame_set ( mem , reg ) ; } </s>

Return a move between register REGNO and memory location SP + OFFSET . REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE . Make the move a load if RESTORE_P , otherwise make it a store .


<s> virtual void dump ( raw_ostream & OS ) const { } </s>

Dump the plan to stderr ( for debugging ) .


"without AVX512F enabled changes the ABI"

Return the `` natural '' mode for TYPE . In most cases , this is just TYPE_MODE . But in the case of vector types , it is some vector mode . When we have only some of our vector isa extensions enabled , then there are some modes for which vector_mode_supported_p is false . For these modes , the generic vector support in gcc will choose some non-vector mode in order to implement the type . By computing the natural mode , we 'll select the proper ABI location for the operand and not depend on whatever the middle-end decides to do with these vector types .


<s> const PatmosSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


"eliminateCallFramePseudoInstr size too big: "

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> int arc_initial_elimination_offset ( int from , int to ) { if ( ! cfun -> machine -> frame_info . initialized ) arc_compute_frame_size ( get_frame_size ( ) ) ; if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) { return ( cfun -> machine -> frame_info . extra_size + cfun -> machine -> frame_info . reg_size ) ; } if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return ( cfun -> machine -> frame_info . total_size - cfun -> machine -> frame_info . pretend_size ) ; } if ( ( from == FRAME_POINTER_REGNUM ) && ( to == STACK_POINTER_REGNUM ) ) { return ( cfun -> machine -> frame_info . total_size - ( cfun -> machine -> frame_info . pretend_size + cfun -> machine -> frame_info . extra_size + cfun -> machine -> frame_info . reg_size ) ) ; } gcc_unreachable ( ) ; } </s>

Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


Emit code to initialize predicate and master lane index registers for -muniform-simt code generation variant .


<s> const uint16_t * NyuziRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return NyuziCSR_SaveList ; } </s>


<s> void ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( TM -> isPagerando ( ) ) addPass ( createARMPagerandoOptimizerPass ( ) ) ; addPass ( createMLxExpansionPass ( ) ) ; if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( ! DisableA15SDOptimization ) addPass ( createA15SDOptimizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static bool mmix_pass_by_reference ( cumulative_args_t argsp_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * argsp = get_cumulative_args ( argsp_v ) ; if ( targetm . calls . must_pass_in_stack ( mode , type ) ) return true ; if ( MMIX_FUNCTION_ARG_SIZE ( mode , type ) > 8 && ! TARGET_LIBFUNC && ( ! argsp || ! argsp -> lib ) ) return true ; return false ; } </s>

Returns nonzero for everything that goes by reference , 0 for everything that goes by value .


<s> void ValueReplacer :: clear ( ) { for ( Instruction * I : DeletedInstructions ) I -> eraseFromParent ( ) ; } </s>


<s> static machine_mode vax_cc_modes_compatible ( machine_mode m1 , machine_mode m2 ) { switch ( m1 ) { default : gcc_unreachable ( ) ; case E_CCmode : switch ( m2 ) { default : gcc_unreachable ( ) ; case E_CCmode : case E_CCNZmode : case E_CCNmode : case E_CCZmode : return m1 ; } case E_CCNZmode : switch ( m2 ) { default : gcc_unreachable ( ) ; case E_CCmode : return m2 ; case E_CCNmode : case E_CCNZmode : case E_CCZmode : return m1 ; } case E_CCNmode : case E_CCZmode : switch ( m2 ) { default : gcc_unreachable ( ) ; case E_CCmode : case E_CCNZmode : return m2 ; case E_CCNmode : case E_CCZmode : return m1 == m2 ? m1 : E_CCNZmode ; } } } </s>

Return the narrowest CC mode that spans both modes offered . If they intersect , this will be the wider of the two , and if they do not then find find one that is a superset of both ( i.e . CCNZmode for a pair consisting of CCNmode and CCZmode ) . A wider CC writer will satisfy a narrower CC reader , e.g . a comparison operator that uses CCZmode can use a CCNZmode output of a previous instruction .


Return an appropriate const instance of xlogue_layout based upon values in cfun- > machine and crtl .


<s> bool HexagonGenExtract :: runOnFunction ( Function & F ) { DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; bool Changed ; BasicBlock * Entry = GraphTraits < Function * > :: getEntryNode ( & F ) ; Changed = visitBlock ( Entry ) ; return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void XCoreFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool AArch64CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , 8 > SplitArgs ; unsigned i = 0 ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg . getType ( ) } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < AArch64FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const AArch64TargetLowering & TLI = * getTLI < AArch64TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; AArch64FunctionInfo * FuncInfo = MF . getInfo < AArch64FunctionInfo > ( ) ; uint64_t StackOffset = Handler . StackUsed ; if ( F . isVarArg ( ) ) { auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( ! Subtarget . isTargetDarwin ( ) ) { return false ; } StackOffset = alignTo ( Handler . StackUsed , Subtarget . isTargetILP32 ( ) ? 4 : 8 ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( 4 , StackOffset , true ) ) ; } if ( doesCalleeRestoreStack ( F . getCallingConv ( ) , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) { StackOffset = alignTo ( StackOffset , 16 ) ; FuncInfo -> setArgumentStackToRestore ( StackOffset ) ; } FuncInfo -> setBytesInStackArgArea ( StackOffset ) ; auto & Subtarget = MF . getSubtarget < AArch64Subtarget > ( ) ; if ( Subtarget . hasCustomCallingConv ( ) ) Subtarget . getRegisterInfo ( ) -> UpdateCustomCalleeSavedRegs ( MF ) ; handleMustTailForwardedRegisters ( MIRBuilder , AssignFn ) ; MIRBuilder . setMBB ( MBB ) ; return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> bool BlackfinRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) ; } </s>


<s> static void add_dependee_for_func_arg ( rtx_insn * arg , basic_block bb ) { rtx_insn * insn = BB_END ( bb ) ; while ( insn ) { if ( NONDEBUG_INSN_P ( insn ) && NONJUMP_INSN_P ( insn ) ) { rtx set = single_set ( insn ) ; if ( set ) { avoid_func_arg_motion ( arg , insn ) ; return ; } } if ( insn == BB_HEAD ( bb ) ) return ; insn = PREV_INSN ( insn ) ; } } </s>

Avoid cross block motion of function argument through adding dependency from the first non-jump instruction in bb .


<s> SDValue AArch64TargetLowering :: getSqrtInputTest ( SDValue Op , SelectionDAG & DAG , const DenormalMode & Mode ) const { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT CCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue FPZero = DAG . getConstantFP ( 0.0 , DL , VT ) ; return DAG . getSetCC ( DL , CCVT , Op , FPZero , ISD :: SETEQ ) ; } </s>

Return a target-dependent comparison result if the input operand is suitable for use with a square root estimate calculation .


<s>
AddressSpace
getAddressSpace
(
T
*
V
)
{
auto
*
PT
=
cast
<
PointerType
>
(
V
->
getType
(
)
)
;
assert
(
PT
!=
nullptr
&&
"unexpected MemSDNode"
)
;
unsigned
AS
=
PT
->
getAddressSpace
(
)
;
if
(
AS
<
NumAddrSpaces
)
return
static_cast
<
AddressSpace
>
(
AS
)
;
return
NumAddrSpaces
;
}
</s>

Return the address space of the Pointer type .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; case RISCVISD :: RET_FLAG : return "RISCVISD::RET_FLAG" ; case RISCVISD :: URET_FLAG : return "RISCVISD::URET_FLAG" ; case RISCVISD :: SRET_FLAG : return "RISCVISD::SRET_FLAG" ; case RISCVISD :: MRET_FLAG : return "RISCVISD::MRET_FLAG" ; case RISCVISD :: CALL : return "RISCVISD::CALL" ; case RISCVISD :: SELECT_CC : return "RISCVISD::SELECT_CC" ; case RISCVISD :: BuildPairF64 : return "RISCVISD::BuildPairF64" ; case RISCVISD :: SplitF64 : return "RISCVISD::SplitF64" ; case RISCVISD :: TAIL : return "RISCVISD::TAIL" ; case RISCVISD :: SLLW : return "RISCVISD::SLLW" ; case RISCVISD :: SRAW : return "RISCVISD::SRAW" ; case RISCVISD :: SRLW : return "RISCVISD::SRLW" ; case RISCVISD :: DIVW : return "RISCVISD::DIVW" ; case RISCVISD :: DIVUW : return "RISCVISD::DIVUW" ; case RISCVISD :: REMUW : return "RISCVISD::REMUW" ; case RISCVISD :: FMV_W_X_RV64 : return "RISCVISD::FMV_W_X_RV64" ; case RISCVISD :: FMV_H_X_RV32 : return "RISCVISD::FMV_H_X_RV32" ; case RISCVISD :: FMV_H_X_RV64 : return "RISCVISD::FMV_H_X_RV64" ; case RISCVISD :: FMV_X_ANYEXTW_RV64 : return "RISCVISD::FMV_X_ANYEXTW_RV64" ; case RISCVISD :: FMV_X_ANYEXTH_RV64 : return "RISCVISD::FMV_X_ANYEXTH_RV64" ; case RISCVISD :: FMV_X_ANYEXTH_RV32 : return "RISCVISD::FMV_X_ANYEXTH_RV32" ; case RISCVISD :: READ_CYCLE_WIDE : return "RISCVISD::READ_CYCLE_WIDE" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> const TargetRegisterClass * PPCRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { if ( Kind == 1 ) { if ( TM . isPPC64 ( ) ) return & PPC :: G8RC_NOX0RegClass ; return & PPC :: GPRC_NOR0RegClass ; } if ( TM . isPPC64 ( ) ) return & PPC :: G8RCRegClass ; return & PPC :: GPRCRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


"total size of local variables exceeds architecture limit"

Fill FRAME with info about frame of current function .


<s>
EVT
MCS51TargetLowering
::
getSetCCResultType
(
const
DataLayout
&
DL
,
LLVMContext
&
,
EVT
VT
)
const
{
assert
(
!
VT
.
isVector
(
)
&&
"No MCS51 SetCC type for vectors!"
)
;
return
MVT
::
i8
;
}
</s>

Return the value type to use for ISD : :SETCC .


<s> bool sh_reg_dead_or_unused_after_insn ( const rtx_insn * i , int regno ) { return find_regno_note ( i , REG_DEAD , regno ) != NULL || find_regno_note ( i , REG_UNUSED , regno ) != NULL ; } </s>

Given an insn and a reg number , tell whether the reg dies or is unused after the insn .


<s> bool X86PassConfig :: addInstSelector ( ) { addPass ( createX86ISelDag ( getX86TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( getX86Subtarget ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ; addPass ( createX86GlobalBaseRegPass ( ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> static bool mips_strict_argument_naming ( cumulative_args_t ca ATTRIBUTE_UNUSED ) { return ! TARGET_OLDABI ; } </s>


"********* Hexagon Hardware Loops *********\n"

runOnMachineFunction - Emit the function body .


<s> static rtx rs6000_darwin64_record_arg ( CUMULATIVE_ARGS * orig_cum , const_tree type , bool named , bool retval ) { rtx rvec [ FIRST_PSEUDO_REGISTER ] ; int k = 1 , kbase = 1 ; HOST_WIDE_INT typesize = int_size_in_bytes ( type ) ; CUMULATIVE_ARGS copy_cum = * orig_cum ; CUMULATIVE_ARGS * cum = & copy_cum ; if ( ! retval && TYPE_ALIGN ( type ) >= 2 * BITS_PER_WORD && ( cum -> words % 2 ) != 0 ) cum -> words ++ ; cum -> intoffset = 0 ; cum -> use_stack = 0 ; cum -> named = named ; rs6000_darwin64_record_arg_recurse ( cum , type , 0 , rvec , & k ) ; rs6000_darwin64_record_arg_flush ( cum , typesize * BITS_PER_UNIT , rvec , & k ) ; if ( cum -> use_stack ) { if ( retval ) return NULL_RTX ; kbase = 0 ; rvec [ 0 ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } if ( k > 1 || cum -> use_stack ) return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( k - kbase , & rvec [ kbase ] ) ) ; else return NULL_RTX ; } </s>

For the darwin64 ABI , we want to construct a PARALLEL consisting of the register ( s ) to be used for each field and subfield of a struct being passed by value , along with the offset of where the register 's value may be found in the block . FP fields go in FP register , vector fields go in vector registers , and everything else goes in int registers , packed as in memory . This code is also used for function return values . RETVAL indicates whether this is the case . Much of this is taken from the SPARC V9 port , which has a similar calling convention .


<s> bool NyuziRegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> bool SIInstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { SIMachineFunctionInfo * MFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < SIMachineFunctionInfo > ( ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUInstrInfo :: expandPostRAPseudo ( MI ) ; case AMDGPU :: SI_SPILL_S512_SAVE : case AMDGPU :: SI_SPILL_S256_SAVE : case AMDGPU :: SI_SPILL_S128_SAVE : case AMDGPU :: SI_SPILL_S64_SAVE : { unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; unsigned FrameIndex = MI -> getOperand ( 2 ) . getImm ( ) ; for ( unsigned i = 0 , e = NumSubRegs ; i < e ; ++ i ) { SIMachineFunctionInfo :: SpilledReg Spill ; unsigned SubReg = RI . getPhysRegSubReg ( MI -> getOperand ( 1 ) . getReg ( ) , & AMDGPU :: SGPR_32RegClass , i ) ; Spill = MFI -> SpillTracker . getSpilledReg ( FrameIndex ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_WRITELANE_B32 ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( SubReg ) . addImm ( Spill . Lane + i ) ; } MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: SI_SPILL_S512_RESTORE : case AMDGPU :: SI_SPILL_S256_RESTORE : case AMDGPU :: SI_SPILL_S128_RESTORE : case AMDGPU :: SI_SPILL_S64_RESTORE : case AMDGPU :: SI_SPILL_S32_RESTORE : { unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; for ( unsigned i = 0 , e = NumSubRegs ; i < e ; ++ i ) { SIMachineFunctionInfo :: SpilledReg Spill ; unsigned FrameIndex = MI -> getOperand ( 2 ) . getImm ( ) ; unsigned SubReg = RI . getPhysRegSubReg ( MI -> getOperand ( 0 ) . getReg ( ) , & AMDGPU :: SGPR_32RegClass , i ) ; Spill = MFI -> SpillTracker . getSpilledReg ( FrameIndex ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_READLANE_B32 ) , SubReg ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addImm ( Spill . Lane + i ) ; } insertNOPs ( MI , 3 ) ; MI -> eraseFromParent ( ) ; break ; } } return true ; } </s>

This function is called for all pseudo instructions that remain after register allocation .


<s> static struct machine_function * loongarch_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s> const char * LanaiTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case LanaiISD :: ADJDYNALLOC : return "LanaiISD::ADJDYNALLOC" ; case LanaiISD :: RET_FLAG : return "LanaiISD::RET_FLAG" ; case LanaiISD :: CALL : return "LanaiISD::CALL" ; case LanaiISD :: SELECT_CC : return "LanaiISD::SELECT_CC" ; case LanaiISD :: SETCC : return "LanaiISD::SETCC" ; case LanaiISD :: SUBBF : return "LanaiISD::SUBBF" ; case LanaiISD :: SET_FLAG : return "LanaiISD::SET_FLAG" ; case LanaiISD :: BR_CC : return "LanaiISD::BR_CC" ; case LanaiISD :: Wrapper : return "LanaiISD::Wrapper" ; case LanaiISD :: HI : return "LanaiISD::HI" ; case LanaiISD :: LO : return "LanaiISD::LO" ; case LanaiISD :: SMALL : return "LanaiISD::SMALL" ; default : return NULL ; } } </s>

Lanai Lanai LanaiISD::ADJDYNALLOC "LanaiISD::ADJDYNALLOC" LanaiISD::RET_FLAG "LanaiISD::RET_FLAG" LanaiISD::CALL "LanaiISD::CALL" LanaiISD::SELECT_CC "LanaiISD::SELECT_CC" LanaiISD::SETCC "LanaiISD::SETCC" LanaiISD::SUBBF "LanaiISD::SUBBF" LanaiISD::SET_FLAG "LanaiISD::SET_FLAG" LanaiISD::BR_CC "LanaiISD::BR_CC" LanaiISD::Wrapper "LanaiISD::Wrapper" LanaiISD::HI "LanaiISD::HI" LanaiISD::LO "LanaiISD::LO" LanaiISD::SMALL "LanaiISD::SMALL"


<s> const unsigned * ARCompactRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { ARC :: T5 , ARC :: T6 , ARC :: T7 , ARC :: S0 , ARC :: S1 , ARC :: S2 , ARC :: S3 , ARC :: S4 , ARC :: S5 , ARC :: S6 , ARC :: S7 , ARC :: S8 , ARC :: S9 , 0 } ; return CalleeSavedRegs ; } </s>


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & TuneCPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian , unsigned MinSVEVectorSizeInBitsOverride , unsigned MaxSVEVectorSizeInBitsOverride ) : AArch64GenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , MinSVEVectorSizeInBits ( MinSVEVectorSizeInBitsOverride ) , MaxSVEVectorSizeInBits ( MaxSVEVectorSizeInBitsOverride ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU , TuneCPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; InlineAsmLoweringInfo . reset ( new InlineAsmLowering ( getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> void BitcodeWriter :: writeStrtab ( ) { assert ( ! WroteStrtab ) ; std :: vector < char > Strtab ; StrtabBuilder . finalizeInOrder ( ) ; Strtab . resize ( StrtabBuilder . getSize ( ) ) ; StrtabBuilder . write ( ( uint8_t * ) Strtab . data ( ) ) ; writeBlob ( bitc :: STRTAB_BLOCK_ID , bitc :: STRTAB_BLOB , { Strtab . data ( ) , Strtab . size ( ) } ) ; WroteStrtab = true ; } </s>

Write the bitcode file 's string table .


<s> TargetLowering :: AtomicExpansionKind SITargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * RMW ) const { switch ( RMW -> getOperation ( ) ) { case AtomicRMWInst :: FAdd : { Type * Ty = RMW -> getType ( ) ; if ( Ty -> isHalfTy ( ) ) return AtomicExpansionKind :: None ; if ( ! Ty -> isFloatTy ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned AS = RMW -> getPointerAddressSpace ( ) ; if ( AS == AMDGPUAS :: GLOBAL_ADDRESS && Subtarget -> hasAtomicFaddInsts ( ) ) { if ( ! fpModeMatchesGlobalFPAtomicMode ( RMW ) ) return AtomicExpansionKind :: CmpXChg ; return RMW -> use_empty ( ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: CmpXChg ; } return ( AS == AMDGPUAS :: LOCAL_ADDRESS && Subtarget -> hasLDSFPAtomics ( ) ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: CmpXChg ; } default : break ; } return AMDGPUTargetLowering :: shouldExpandAtomicRMWInIR ( RMW ) ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> int reg_unused_after ( rtx_insn * insn , rtx reg ) { return ( dead_or_set_p ( insn , reg ) || ( REG_P ( reg ) && _reg_unused_after ( insn , reg ) ) ) ; } </s>

Return nonzero if REG is not used after INSN . We assume REG is a reload reg , and therefore does not live past labels or calls or jumps .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; if ( TM . getSubtarget < ARMSubtarget > ( ) . isAAPCS_ABI ( ) ) { StaticCtorSection = getContext ( ) . getELFSection ( ".init_array" , MCSectionELF :: SHT_INIT_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; StaticDtorSection = getContext ( ) . getELFSection ( ".fini_array" , MCSectionELF :: SHT_FINI_ARRAY , MCSectionELF :: SHF_WRITE | MCSectionELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ; } AttributesSection = getContext ( ) . getELFSection ( ".ARM.attributes" , MCSectionELF :: SHT_ARM_ATTRIBUTES , 0 , SectionKind :: getMetadata ( ) ) ; } </s>

This method must be called before any actual lowering is done .


<s> AArch64Subtarget :: AArch64Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool LittleEndian ) : AArch64GenSubtargetInfo ( TT , CPU , FS ) , ReserveXRegister ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , CustomCallSavedXRegs ( AArch64 :: GPR64commonRegClass . getNumRegs ( ) ) , IsLittle ( LittleEndian ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS , CPU ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { if ( AArch64 :: isX18ReservedByDefault ( TT ) ) ReserveXRegister . set ( 18 ) ; CallLoweringInfo . reset ( new AArch64CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new AArch64LegalizerInfo ( * this ) ) ; auto * RBI = new AArch64RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( createAArch64InstructionSelector ( * static_cast < const AArch64TargetMachine * > ( & TM ) , * this , * RBI ) ) ; RegBankInfo . reset ( RBI ) ; } </s>


<s> bool LoongArchTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { return Outs . size ( ) <= 2 ; } </s>

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers .


<s>
bool
X86AsmParser
::
ParseDirective
(
AsmToken
DirectiveID
)
{
MCAsmParser
&
Parser
=
getParser
(
)
;
StringRef
IDVal
=
DirectiveID
.
getIdentifier
(
)
;
if
(
IDVal
.
startswith
(
".arch"
)
)
return
parseDirectiveArch
(
)
;
if
(
IDVal
.
startswith
(
".code"
)
)
return
ParseDirectiveCode
(
IDVal
,
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
.
startswith
(
".att_syntax"
)
)
{
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.att_syntax noprefix' is not "
"supported: registers must have a "
"'%' prefix in .att_syntax"
)
;
}
getParser
(
)
.
setAssemblerDialect
(
0
)
;
return
false
;
}
else
if
(
IDVal
.
startswith
(
".intel_syntax"
)
)
{
getParser
(
)
.
setAssemblerDialect
(
1
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"noprefix"
)
Parser
.
Lex
(
)
;
else
if
(
Parser
.
getTok
(
)
.
getString
(
)
==
"prefix"
)
return
Error
(
DirectiveID
.
getLoc
(
)
,
"'.intel_syntax prefix' is not "
"supported: registers must not have "
"a '%' prefix in .intel_syntax"
)
;
}
return
false
;
}
else
if
(
IDVal
==
".nops"
)
return
parseDirectiveNops
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".even"
)
return
parseDirectiveEven
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_proc"
)
return
parseDirectiveFPOProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_setframe"
)
return
parseDirectiveFPOSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_pushreg"
)
return
parseDirectiveFPOPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalloc"
)
return
parseDirectiveFPOStackAlloc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_stackalign"
)
return
parseDirectiveFPOStackAlign
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endprologue"
)
return
parseDirectiveFPOEndPrologue
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".cv_fpo_endproc"
)
return
parseDirectiveFPOEndProc
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_pushreg"
)
return
parseDirectiveSEHPushReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_setframe"
)
return
parseDirectiveSEHSetFrame
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_savereg"
)
return
parseDirectiveSEHSaveReg
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_savexmm"
)
return
parseDirectiveSEHSaveXMM
(
DirectiveID
.
getLoc
(
)
)
;
else
if
(
IDVal
==
".seh_pushframe"
)
return
parseDirectiveSEHPushFrame
(
DirectiveID
.
getLoc
(
)
)
;
return
true
;
}
</s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> bool AMDGPUAAResult :: pointsToConstantMemory ( const MemoryLocation & Loc , bool OrLocal ) { const Value * Base = GetUnderlyingObject ( Loc . Ptr , DL ) ; if ( Base -> getType ( ) -> getPointerAddressSpace ( ) == AS . CONSTANT_ADDRESS ) { return true ; } if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Base ) ) { if ( GV -> isConstant ( ) ) return true ; } else if ( const Argument * Arg = dyn_cast < Argument > ( Base ) ) { const Function * F = Arg -> getParent ( ) ; switch ( F -> getCallingConv ( ) ) { default : return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ; case CallingConv :: AMDGPU_LS : case CallingConv :: AMDGPU_HS : case CallingConv :: AMDGPU_ES : case CallingConv :: AMDGPU_GS : case CallingConv :: AMDGPU_VS : case CallingConv :: AMDGPU_PS : case CallingConv :: AMDGPU_CS : case CallingConv :: AMDGPU_KERNEL : case CallingConv :: SPIR_KERNEL : break ; } unsigned ArgNo = Arg -> getArgNo ( ) ; if ( F -> hasParamAttribute ( ArgNo , Attribute :: NoAlias ) && ( F -> hasParamAttribute ( ArgNo , Attribute :: ReadNone ) || F -> hasParamAttribute ( ArgNo , Attribute :: ReadOnly ) ) ) { return true ; } } return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ; } </s>

A convenience wrapper around the primary pointsToConstantMemory interface .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> static unsigned int aarch64_detect_vector_stmt_subtype ( vec_info * vinfo , vect_cost_for_stmt kind , stmt_vec_info stmt_info , tree vectype , enum vect_cost_model_location where , unsigned int stmt_cost ) { const simd_vec_cost * simd_costs = aarch64_simd_vec_costs ( vectype ) ; const sve_vec_cost * sve_costs = nullptr ; if ( aarch64_sve_mode_p ( TYPE_MODE ( vectype ) ) ) sve_costs = aarch64_tune_params . vec_costs -> sve ; if ( is_a < gphi * > ( stmt_info -> stmt ) ) return 0 ; if ( kind == vec_to_scalar && STMT_VINFO_DATA_REF ( stmt_info ) && DR_IS_WRITE ( STMT_VINFO_DATA_REF ( stmt_info ) ) ) return simd_costs -> store_elt_extra_cost ; if ( kind == scalar_store && sve_costs && STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_GATHER_SCATTER ) return sve_costs -> scatter_store_elt_cost ; if ( kind == vec_to_scalar && where == vect_body && sve_costs ) { unsigned int latency = aarch64_sve_in_loop_reduction_latency ( vinfo , stmt_info , vectype , sve_costs ) ; if ( latency ) return latency ; } if ( kind == vec_to_scalar && where == vect_epilogue && aarch64_is_reduction ( stmt_info ) ) switch ( GET_MODE_INNER ( TYPE_MODE ( vectype ) ) ) { case E_QImode : return simd_costs -> reduc_i8_cost ; case E_HImode : return simd_costs -> reduc_i16_cost ; case E_SImode : return simd_costs -> reduc_i32_cost ; case E_DImode : return simd_costs -> reduc_i64_cost ; case E_HFmode : case E_BFmode : return simd_costs -> reduc_f16_cost ; case E_SFmode : return simd_costs -> reduc_f32_cost ; case E_DFmode : return simd_costs -> reduc_f64_cost ; default : break ; } return stmt_cost ; } </s>

STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost for the vectorized form of STMT_INFO , which has cost kind KIND and which when vectorized would operate on vector type VECTYPE . Try to subdivide the target-independent categorization provided by KIND to get a more accurate cost . WHERE specifies where the cost associated with KIND occurs .


"the destination register can't equal the base register in an "

"instruction that modifies the base register."

ParseInstruction - Parse one assembly instruction .


<s>
void
Thumb1InstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
DestReg
)
&&
isARMLowRegister
(
DestReg
)
)
)
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
MachinePointerInfo
(
PseudoSourceValue
::
getFixedStack
(
FI
)
)
,
MachineMemOperand
::
MOLoad
,
MFI
.
getObjectSize
(
FI
)
,
MFI
.
getObjectAlignment
(
FI
)
)
;
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tRestore
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM
ARM::tRestore
0


<s>
bool
CSKYMCInstLower
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
const
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_RegisterMask
:
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
createImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_Register
:
if
(
MO
.
isImplicit
(
)
)
return
false
;
MCOp
=
MCOperand
::
createReg
(
MO
.
getReg
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
createExpr
(
MCSymbolRefExpr
::
create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
Ctx
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_BlockAddress
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetBlockAddressSymbol
(
MO
.
getBlockAddress
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_ConstantPoolIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetCPISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_JumpTableIndex
:
MCOp
=
lowerSymbolOperand
(
MO
,
Printer
.
GetJTISymbol
(
MO
.
getIndex
(
)
)
)
;
break
;
case
MachineOperand
::
MO_MCSymbol
:
MCOp
=
lowerSymbolOperand
(
MO
,
MO
.
getMCSymbol
(
)
)
;
break
;
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .


<s> const LC3RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool SystemZInstrInfo :: isPredicable ( MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == SystemZ :: Return || Opcode == SystemZ :: Trap || Opcode == SystemZ :: CallJG || Opcode == SystemZ :: CallBR ) return true ; return false ; } </s>

Return true if the specified instruction can be predicated .

SystemZ SystemZ SystemZ::Return SystemZ::Trap SystemZ::CallJG SystemZ::CallBR


<s> unsigned getIndex ( ) const { return cast < ConstantInt > ( Extract -> getOperand ( 1 ) ) -> getZExtValue ( ) ; } </s>


<s> rtx sparc_legitimize_reload_address ( rtx x , machine_mode mode , int opnum , int type , int ind_levels ATTRIBUTE_UNUSED , int * win ) { if ( CONSTANT_P ( x ) && ( mode != TFmode || TARGET_ARCH64 ) && GET_MODE ( x ) == SImode && GET_CODE ( x ) != LO_SUM && GET_CODE ( x ) != HIGH && sparc_cmodel <= CM_MEDLOW && ! ( flag_pic && ( symbolic_operand ( x , Pmode ) || pic_address_needs_scratch ( x ) ) ) ) { x = gen_rtx_LO_SUM ( GET_MODE ( x ) , gen_rtx_HIGH ( GET_MODE ( x ) , x ) , x ) ; push_reload ( XEXP ( x , 0 ) , NULL_RTX , & XEXP ( x , 0 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; * win = 1 ; return x ; } if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , 0 ) ) == HIGH ) { push_reload ( XEXP ( x , 0 ) , NULL_RTX , & XEXP ( x , 0 ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , 0 , 0 , opnum , ( enum reload_type ) type ) ; * win = 1 ; return x ; } * win = 0 ; return x ; } </s>

SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS . Returns a value to replace the input X , or the original X if no replacement is called for . The output parameter * WIN is 1 if the calling macro should goto WIN , 0 if it should not . For SPARC , we wish to handle addresses by splitting them into HIGH+LO_SUM pairs , retaining the LO_SUM in the memory reference . This cuts the number of extra insns by one . Do nothing when generating PIC code and the address is a symbolic operand or requires a scratch register .


<s> bool runOnMachineFunction ( MachineFunction & F ) { isEvenPlace = true ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) runOnMachineBasicBlock ( * FI ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C ) const override { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> int mmix_constant_alignment ( tree constant ATTRIBUTE_UNUSED , int basic_align ) { if ( basic_align < 32 ) return 32 ; return basic_align ; } </s>


<s> SDValue SITargetLowering :: getMemIntrinsicNode ( unsigned Opcode , const SDLoc & DL , SDVTList VTList , ArrayRef < SDValue > Ops , EVT MemVT , MachineMemOperand * MMO , SelectionDAG & DAG ) const { EVT VT = VTList . VTs [ 0 ] ; EVT WidenedVT = VT ; EVT WidenedMemVT = MemVT ; if ( ! Subtarget -> hasDwordx3LoadStores ( ) && ( WidenedVT == MVT :: v3i32 || WidenedVT == MVT :: v3f32 ) ) { WidenedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , WidenedVT . getVectorElementType ( ) , 4 ) ; WidenedMemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , WidenedMemVT . getVectorElementType ( ) , 4 ) ; MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MMO , 0 , 16 ) ; } assert ( VTList . NumVTs == 2 ) ; SDVTList WidenedVTList = DAG . getVTList ( WidenedVT , VTList . VTs [ 1 ] ) ; auto NewOp = DAG . getMemIntrinsicNode ( Opcode , DL , WidenedVTList , Ops , WidenedMemVT , MMO ) ; if ( WidenedVT != VT ) { auto Extract = DAG . getNode ( ISD :: EXTRACT_SUBVECTOR , DL , VT , NewOp , DAG . getConstant ( 0 , DL , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; NewOp = DAG . getMergeValues ( { Extract , SDValue ( NewOp . getNode ( ) , 1 ) } , DL ) ; } return NewOp ; } </s>

Creates a MemIntrinsicNode that may produce a result and takes a list of operands .


<s> void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const override { loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI , 0 ) ; } </s>


<s> static machine_mode arc_preferred_simd_mode ( scalar_mode mode ) { switch ( mode ) { case E_HImode : return TARGET_PLUS_QMACW ? V4HImode : V2HImode ; case E_SImode : return V2SImode ; default : return word_mode ; } } </s>

Implements target hook TARGET_VECTORIZE_PREFERRED_SIMD_MODE .


<s> bool HexagonPassConfig :: addPostRegAlloc ( ) { PM -> add ( createHexagonCFGOptimizer ( getHexagonTargetMachine ( ) ) ) ; return true ; } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


<s> inline void count_registers ( const_tree field , HOST_WIDE_INT bitpos , bool fp , assign_data_t * data ) { if ( fp ) { int nregs ; machine_mode mode ; if ( compute_int_layout ( bitpos , data , & nregs ) ) data -> nregs += nregs ; if ( compute_fp_layout ( field , bitpos , data , & nregs , & mode ) ) data -> nregs += nregs ; } else { if ( data -> intoffset < 0 ) data -> intoffset = bitpos ; } } </s>

A subroutine of function_arg_record_value . Count the number of registers to be assigned for FIELD and between PARMS- > intoffset and BITPOS .


"__float128 and __ibm128 cannot be used in the same "

"__ibm128 and long double cannot be used in the same "

"__float128 and long double cannot be used in the same "

Return the diagnostic message string if the binary operation OP is not permitted on TYPE1 and TYPE2 , NULL otherwise .


"getInstSizeInBytes()- Unable to determin insn size"

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> static rtx rs6000_complex_function_value ( machine_mode mode ) { unsigned int regno ; rtx r1 , r2 ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int inner_bytes = GET_MODE_UNIT_SIZE ( mode ) ; if ( TARGET_FLOAT128_TYPE && ( mode == KCmode || ( mode == TCmode && TARGET_IEEEQUAD ) ) ) regno = ALTIVEC_ARG_RETURN ; else if ( FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else { regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= 4 ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= 8 ) return gen_rtx_REG ( mode , regno ) ; r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno ) , const0_rtx ) ; r2 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno + 1 ) , GEN_INT ( inner_bytes ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } </s>

Return an RTX representing where to find the function value of a function returning MODE .