<s> MachineBasicBlock * SITargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { MachineBasicBlock :: iterator I = * MI ; switch ( MI -> getOpcode ( ) ) { default : return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: SI_ADDR64_RSRC : { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned SuperReg = MI -> getOperand ( 0 ) . getReg ( ) ; unsigned SubRegLo = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; unsigned SubRegHi = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; unsigned SubRegHiHi = MRI . createVirtualRegister ( & AMDGPU :: SReg_32RegClass ) ; unsigned SubRegHiLo = MRI . createVirtualRegister ( & AMDGPU :: SReg_32RegClass ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B64 ) , SubRegLo ) . addOperand ( MI -> getOperand ( 1 ) ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , SubRegHiLo ) . addImm ( 0 ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , SubRegHiHi ) . addImm ( RSRC_DATA_FORMAT >> 32 ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: REG_SEQUENCE ) , SubRegHi ) . addReg ( SubRegHiLo ) . addImm ( AMDGPU :: sub0 ) . addReg ( SubRegHiHi ) . addImm ( AMDGPU :: sub1 ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: REG_SEQUENCE ) , SuperReg ) . addReg ( SubRegLo ) . addImm ( AMDGPU :: sub0_sub1 ) . addReg ( SubRegHi ) . addImm ( AMDGPU :: sub2_sub3 ) ; MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: V_SUB_F64 : { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: V_ADD_F64 ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 2 ) ; MI -> eraseFromParent ( ) ; break ; } } return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s>
bool
HexagonOptAddrMode
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
bool
Changed
=
false
;
auto
&
HST
=
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
;
auto
&
MRI
=
MF
.
getRegInfo
(
)
;
HII
=
HST
.
getInstrInfo
(
)
;
const
auto
&
MDF
=
getAnalysis
<
MachineDominanceFrontier
>
(
)
;
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
auto
&
TRI
=
*
MF
.
getSubtarget
(
)
.
getRegisterInfo
(
)
;
const
TargetOperandInfo
TOI
(
*
HII
)
;
DataFlowGraph
G
(
MF
,
*
HII
,
TRI
,
*
MDT
,
MDF
,
TOI
)
;
G
.
build
(
)
;
DFG
=
&
G
;
Liveness
L
(
MRI
,
*
DFG
)
;
L
.
computePhiInfo
(
)
;
LV
=
&
L
;
Deleted
.
clear
(
)
;
NodeAddr
<
FuncNode
*
>
FA
=
DFG
->
getFunc
(
)
;
DEBUG
(
dbgs
(
)
<<
"==== [RefMap#]=====:\n "
<<
Print
<
NodeAddr
<
FuncNode
*
>>
(
FA
,
*
DFG
)
<<
"\n"
)
;
for
(
NodeAddr
<
BlockNode
*
>
BA
:
FA
.
Addr
->
members
(
*
DFG
)
)
Changed
|=
processBlock
(
BA
)
;
for
(
auto
MI
:
Deleted
)
MI
->
eraseFromParent
(
)
;
if
(
Changed
)
{
G
.
build
(
)
;
L
.
computeLiveIns
(
)
;
L
.
resetLiveIns
(
)
;
L
.
resetKills
(
)
;
}
return
Changed
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
"==== [RefMap#]=====:\n "
"\n"


<s> static AArch64Operand * CreateReg ( unsigned RegNum , bool isVector , SMLoc S , SMLoc E , MCContext & Ctx ) { AArch64Operand * Op = new AArch64Operand ( k_Register , Ctx ) ; Op -> Reg . RegNum = RegNum ; Op -> Reg . isVector = isVector ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> static bool classof ( const MCStreamer * S ) { return S -> getKind ( ) == SK_AsmStreamer ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static inline int and_xor_ior_costs ( rtx x , int code ) { const int cost_scale = ! TARGET_SHMEDIA && GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ? 2 : 1 ; if ( ! CONST_INT_P ( XEXP ( x , 1 ) ) ) return 1 * cost_scale ; int i = INTVAL ( XEXP ( x , 1 ) ) ; if ( TARGET_SHMEDIA ) { if ( satisfies_constraint_I10 ( XEXP ( x , 1 ) ) || satisfies_constraint_J16 ( XEXP ( x , 1 ) ) ) return 1 ; else return 1 + rtx_cost ( XEXP ( x , 1 ) , GET_MODE ( x ) , AND , 1 , ! optimize_size ) ; } if ( ( i == 0xff || i == 0xffff ) && code == AND ) return 1 * cost_scale ; if ( CONST_OK_FOR_K08 ( i ) ) return 2 * cost_scale ; if ( CONST_OK_FOR_I08 ( i ) ) return 2 * cost_scale ; return 3 * cost_scale ; } </s>

Return the cost of an AND/XOR/IOR operation .


"total size of local variables exceeds architecture limit"

Fill FRAME with info about frame of current function .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < MachineDominatorTree > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreservedID ( LiveVariablesID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SDValue PPCTargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( PPCSubTarget . isSVR4ABI ( ) ) { if ( PPCSubTarget . isPPC64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; else return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } </s>

This hook must be implemented to lower calls into the specified DAG .

PowerPC PPC ISD::OutputArg 32 32 ISD::InputArg 32 PPC PPC PPC


Return an array that contains the bitmask target flag values and their names .

PowerPC PPC PPC "ppc-plt" "ppc-pic" "ppc-pcrel" "ppc-got" "ppc-opt-pcrel" "ppc-tlsgd" "ppc-tlsld" "ppc-tprel" "ppc-got-tlsgd-pcrel" "ppc-got-tlsld-pcrel" "ppc-got-tprel-pcrel"


<s> void xstormy16_expand_epilogue ( void ) { struct xstormy16_stack_layout layout ; rtx mem_pop_rtx , insn ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; mem_pop_rtx = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; mem_pop_rtx = gen_rtx_MEM ( HImode , mem_pop_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . locals_size ) { if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; else { insn = emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . locals_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno >= 0 ; regno -- ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) { rtx dwarf ; insn = emit_move_insn ( gen_rtx_REG ( HImode , regno ) , mem_pop_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; dwarf = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( stack_pointer_rtx , - GET_MODE_SIZE ( Pmode ) ) ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf , REG_NOTES ( insn ) ) ; } if ( layout . stdarg_save_size ) { insn = emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . stdarg_save_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( ifun ) emit_jump_insn ( gen_return_internal_interrupt ( ) ) ; else emit_jump_insn ( gen_return_internal ( ) ) ; } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> Align PPCTargetLowering :: getPrefLoopAlignment ( MachineLoop * ML ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : break ; case PPC :: DIR_970 : case PPC :: DIR_PWR4 : case PPC :: DIR_PWR5 : case PPC :: DIR_PWR5X : case PPC :: DIR_PWR6 : case PPC :: DIR_PWR6X : case PPC :: DIR_PWR7 : case PPC :: DIR_PWR8 : case PPC :: DIR_PWR9 : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > 1 && ML -> getSubLoops ( ) . empty ( ) ) return Align ( 32 ) ; } const PPCInstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = 0 ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > 32 ) break ; } if ( LoopSize > 16 && LoopSize <= 32 ) return Align ( 32 ) ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ; } </s>


<s>
void
HexagonOperand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
Immediate
:
getImm
(
)
->
print
(
OS
,
nullptr
)
;
break
;
case
Register
:
OS
<<
"<register R"
;
OS
<<
getReg
(
)
<<
">"
;
break
;
case
Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

Hexagon
Hexagon
"<register R"
">"
"'"
"'"


"RX FPU instructions do not support NaNs and infinities"


<s> const NyuziTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> bool RISCVMCExpr :: evaluateAsConstant ( int64_t & Res ) const { MCValue Value ; if ( Kind == VK_RISCV_PCREL_HI ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ; Res = evaluateAsInt64 ( Value . getConstant ( ) ) ; return true ; } </s>

Evaluates the fixup as a constant value .


<s> bool NVPTXAllocaHoisting :: runOnFunction ( Function & function ) { bool functionModified = false ; Function :: iterator I = function . begin ( ) ; TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ; for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) { for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) { AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ; if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) { allocaInst -> moveBefore ( firstTerminatorInst ) ; functionModified = true ; } } } return functionModified ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool nds32_n13_load_to_e2_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; gcc_assert ( get_attr_type ( producer ) == TYPE_LOAD ) ; gcc_assert ( REG_P ( def_reg ) || GET_CODE ( def_reg ) == SUBREG ) ; return n13_consumed_by_e2_dep_p ( consumer , def_reg ) ; } </s>

Check dependencies from Load-Store Unit ( E3 ) to E2 .


<s> static void mips_set_tuning_info ( void ) { if ( mips_tuning_info . initialized_p && mips_tuning_info . arch == mips_arch && mips_tuning_info . tune == mips_tune && mips_tuning_info . mips16_p == TARGET_MIPS16 ) return ; mips_tuning_info . arch = mips_arch ; mips_tuning_info . tune = mips_tune ; mips_tuning_info . mips16_p = TARGET_MIPS16 ; mips_tuning_info . initialized_p = true ; dfa_start ( ) ; struct mips_sim state ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; mips_set_fast_mult_zero_zero_p ( & state ) ; dfa_finish ( ) ; } </s>

Set up costs based on the current architecture and tuning settings .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> void X86InstrInfo :: reMaterialize ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , const MachineInstr * Orig ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned SubIdx = Orig -> getOperand ( 0 ) . isReg ( ) ? Orig -> getOperand ( 0 ) . getSubReg ( ) : 0 ; bool ChangeSubIdx = SubIdx != 0 ; if ( SubIdx && TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) { DestReg = RI . getSubReg ( DestReg , SubIdx ) ; SubIdx = 0 ; } bool Emitted = false ; switch ( Orig -> getOpcode ( ) ) { default : break ; case X86 :: MOV8r0 : case X86 :: MOV16r0 : case X86 :: MOV32r0 : case X86 :: MOV64r0 : { if ( ! isSafeToClobberEFLAGS ( MBB , I ) ) { unsigned Opc = 0 ; switch ( Orig -> getOpcode ( ) ) { default : break ; case X86 :: MOV8r0 : Opc = X86 :: MOV8ri ; break ; case X86 :: MOV16r0 : Opc = X86 :: MOV16ri ; break ; case X86 :: MOV32r0 : Opc = X86 :: MOV32ri ; break ; case X86 :: MOV64r0 : Opc = X86 :: MOV64ri32 ; break ; } BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addImm ( 0 ) ; Emitted = true ; } break ; } } if ( ! Emitted ) { MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( Orig ) ; MI -> getOperand ( 0 ) . setReg ( DestReg ) ; MBB . insert ( I , MI ) ; } if ( ChangeSubIdx ) { MachineInstr * NewMI = prior ( I ) ; NewMI -> getOperand ( 0 ) . setSubReg ( SubIdx ) ; } } </s>

Re-issue the specified 'original ' instruction at the specific location targeting a new destination register .


<s>
bool
X86CallLowering
::
splitToValueTypes
(
const
ArgInfo
&
OrigArg
,
SmallVectorImpl
<
ArgInfo
>
&
SplitArgs
,
const
DataLayout
&
DL
,
MachineRegisterInfo
&
MRI
,
SplitArgTy
PerformArgSplit
)
const
{
const
X86TargetLowering
&
TLI
=
*
getTLI
<
X86TargetLowering
>
(
)
;
LLVMContext
&
Context
=
OrigArg
.
Ty
->
getContext
(
)
;
SmallVector
<
EVT
,
4
>
SplitVTs
;
SmallVector
<
uint64_t
,
4
>
Offsets
;
ComputeValueVTs
(
TLI
,
DL
,
OrigArg
.
Ty
,
SplitVTs
,
&
Offsets
,
0
)
;
assert
(
OrigArg
.
Regs
.
size
(
)
==
1
&&
"Can't handle multple regs yet"
)
;
if
(
OrigArg
.
Ty
->
isVoidTy
(
)
)
return
true
;
EVT
VT
=
SplitVTs
[
0
]
;
unsigned
NumParts
=
TLI
.
getNumRegisters
(
Context
,
VT
)
;
if
(
NumParts
==
1
)
{
SplitArgs
.
emplace_back
(
OrigArg
.
Regs
[
0
]
,
VT
.
getTypeForEVT
(
Context
)
,
OrigArg
.
Flags
,
OrigArg
.
IsFixed
)
;
return
true
;
}
SmallVector
<
Register
,
8
>
SplitRegs
;
EVT
PartVT
=
TLI
.
getRegisterType
(
Context
,
VT
)
;
Type
*
PartTy
=
PartVT
.
getTypeForEVT
(
Context
)
;
for
(
unsigned
i
=
0
;
i
<
NumParts
;
++
i
)
{
ArgInfo
Info
=
ArgInfo
{
MRI
.
createGenericVirtualRegister
(
getLLTForType
(
*
PartTy
,
DL
)
)
,
PartTy
,
OrigArg
.
Flags
}
;
SplitArgs
.
push_back
(
Info
)
;
SplitRegs
.
push_back
(
Info
.
Regs
[
0
]
)
;
}
PerformArgSplit
(
SplitRegs
)
;
return
true
;
}
</s>

Break OrigArgInfo into one or more pieces the calling convention can process , returned in SplitArgs .


"PRINT_OPERAND, invalid operand for relocation"

Print symbolic operand OP , which is part of a HIGH or LO_SUM . RELOCS is the array of relocations to use .


<s> Fragment * MipsGOTPLT :: create ( ) { return new GOTPLTEntry ( 0 , m_SectionData ) ; } </s>


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> void ARMBaseRegisterInfo :: getRegAllocationHints ( unsigned VirtReg , ArrayRef < MCPhysReg > Order , SmallVectorImpl < MCPhysReg > & Hints , const MachineFunction & MF , const VirtRegMap * VRM ) const { const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI . getRegAllocationHint ( VirtReg ) ; unsigned Odd ; switch ( Hint . first ) { case ARMRI :: RegPairEven : Odd = 0 ; break ; case ARMRI :: RegPairOdd : Odd = 1 ; break ; default : TargetRegisterInfo :: getRegAllocationHints ( VirtReg , Order , Hints , MF , VRM ) ; return ; } unsigned PairedPhys = 0 ; if ( VRM && VRM -> hasPhys ( Hint . second ) ) { PairedPhys = getPairedGPR ( VRM -> getPhys ( Hint . second ) , Odd , this ) ; if ( PairedPhys && MRI . isReserved ( PairedPhys ) ) PairedPhys = 0 ; } if ( PairedPhys ) Hints . push_back ( PairedPhys ) ; for ( unsigned I = 0 , E = Order . size ( ) ; I != E ; ++ I ) { unsigned Reg = Order [ I ] ; if ( Reg == PairedPhys || ( getEncodingValue ( Reg ) & 1 ) != Odd ) continue ; unsigned Paired = getPairedGPR ( Reg , ! Odd , this ) ; if ( ! Paired || MRI . isReserved ( Paired ) ) continue ; Hints . push_back ( Reg ) ; } } </s>

Get a list of 'hint ' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg .


<s> static void emit_add_sp_const ( HOST_WIDE_INT offset , bool frame_related_p ) { rtx to_add = GEN_INT ( offset ) ; rtx orig_to_add = to_add ; rtx_insn * insn ; if ( offset == 0 ) return ; if ( offset < - 32768 || offset > 32767 ) { rtx reg = gen_rtx_REG ( SImode , REG_A0 ) ; rtx low = GEN_INT ( trunc_int_for_mode ( offset , HImode ) ) ; insn = emit_insn ( gen_movsi_high ( reg , low ) ) ; if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_insn ( gen_movsi_lo_sum ( reg , reg , to_add ) ) ; if ( frame_related_p ) RTX_FRAME_RELATED_P ( insn ) = 1 ; to_add = reg ; } insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ) ; if ( frame_related_p ) { if ( REG_P ( to_add ) ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , orig_to_add ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } } </s>

Emit insns to increment the stack pointer by OFFSET . If FRAME_RELATED_P , set the RTX_FRAME_RELATED_P flag on the insns . Does nothing if the offset is zero .


<s>
const
char
*
output_v9branch
(
rtx
op
,
rtx
dest
,
int
reg
,
int
label
,
int
reversed
,
int
annul
,
rtx
insn
)
{
static
char
string
[
64
]
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
enum
machine_mode
mode
=
GET_MODE
(
XEXP
(
op
,
0
)
)
;
rtx
note
;
int
far
;
char
*
p
;
far
=
get_attr_length
(
insn
)
>=
3
;
if
(
reversed
^
far
)
code
=
reverse_condition
(
code
)
;
gcc_assert
(
mode
==
DImode
)
;
switch
(
code
)
{
case
NE
:
strcpy
(
string
,
"brnz"
)
;
break
;
case
EQ
:
strcpy
(
string
,
"brz"
)
;
break
;
case
GE
:
strcpy
(
string
,
"brgez"
)
;
break
;
case
LT
:
strcpy
(
string
,
"brlz"
)
;
break
;
case
LE
:
strcpy
(
string
,
"brlez"
)
;
break
;
case
GT
:
strcpy
(
string
,
"brgz"
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
p
=
strchr
(
string
,
'\0'
)
;
if
(
annul
&&
!
far
)
{
strcpy
(
p
,
",a"
)
;
p
+=
2
;
}
if
(
insn
&&
(
note
=
find_reg_note
(
insn
,
REG_BR_PROB
,
NULL_RTX
)
)
)
{
strcpy
(
p
,
(
(
INTVAL
(
XEXP
(
note
,
0
)
)
>=
REG_BR_PROB_BASE
/
2
)
^
far
)
",pt"
:
",pn"
)
;
p
+=
3
;
}
*
p
=
p
<
string
+
8
'\t'
:
' '
;
p
++
;
*
p
++
=
'%'
;
*
p
++
=
'0'
+
reg
;
*
p
++
=
','
;
*
p
++
=
' '
;
if
(
far
)
{
int
veryfar
=
1
,
delta
;
if
(
INSN_ADDRESSES_SET_P
(
)
)
{
delta
=
(
INSN_ADDRESSES
(
INSN_UID
(
dest
)
)
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
delta
>=
260000
&&
delta
<
260000
)
veryfar
=
0
;
}
strcpy
(
p
,
".+12\n\t nop\n\t"
)
;
if
(
annul
||
!
final_sequence
)
p
[
3
]
=
'6'
;
p
+=
12
;
if
(
veryfar
)
{
strcpy
(
p
,
"b\t"
)
;
p
+=
2
;
}
else
{
strcpy
(
p
,
"ba,pt\t%%xcc, "
)
;
p
+=
13
;
}
}
*
p
++
=
'%'
;
*
p
++
=
'l'
;
*
p
++
=
'0'
+
label
;
*
p
++
=
'%'
;
*
p
++
=
'#'
;
*
p
=
'\0'
;
return
string
;
}
</s>

Return the string to output a conditional branch to LABEL , testing register REG . LABEL is the operand number of the label ; REG is the operand number of the reg . OP is the conditional expression . The mode of REG says what kind of comparison we made . REVERSED is non-zero if we should reverse the sense of the comparison . ANNUL is non-zero if we should generate an annulling branch . NOOP is non-zero if we have to follow this branch by a noop .


<s> static int mips_adjust_cost ( rtx_insn * , int dep_type , rtx_insn * , int cost , unsigned int ) { if ( dep_type != 0 && ( dep_type != REG_DEP_OUTPUT || ! TUNE_20KC ) ) return 0 ; return cost ; } </s>

Implement TARGET_SCHED_ADJUST_COST . We assume that anti and output dependencies have no cost .


<s> unsigned DLXRegisterInfo :: getFrameRegister ( const MachineFunction & ) const { return DLX :: FP ; } </s>


"Can't load this register from stack slot"

Load the specified register of the given register class from the specified stack frame index .


<s> static void s390_init_frame_layout ( void ) { HOST_WIDE_INT frame_size ; int base_used ; if ( reload_completed ) return ; if ( ! TARGET_CPU_ZARCH ) cfun -> machine -> split_branches_pending_p = true ; do { frame_size = cfun_frame_layout . frame_size ; base_used = cfun -> machine -> split_branches_pending_p || crtl -> uses_const_pool || ( ! DISP_IN_RANGE ( frame_size ) && ! CONST_OK_FOR_K ( frame_size ) ) ; if ( ! base_used ) cfun -> machine -> base_reg = NULL_RTX ; else { int br = 0 ; if ( crtl -> is_leaf ) for ( br = 5 ; br >= 2 && df_regs_ever_live_p ( br ) ; br -- ) ; cfun -> machine -> base_reg = gen_rtx_REG ( Pmode , ( br >= 2 ) ? br : BASE_REGNUM ) ; } s390_register_info ( ) ; s390_frame_info ( ) ; } while ( frame_size != cfun_frame_layout . frame_size ) ; } </s>

Generate frame layout . Fills in register and frame data for the current function in cfun- > machine . This routine can be called multiple times ; it will re-do the complete frame layout every time .


<s> MCSection * getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const override { return ReadOnlySection ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> static machine_mode arm_preferred_simd_mode ( scalar_mode mode ) { if ( TARGET_NEON ) switch ( mode ) { case E_HFmode : return TARGET_NEON_VECTORIZE_DOUBLE ? V4HFmode : V8HFmode ; case E_SFmode : return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode ; case E_SImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V2SImode : V4SImode ; case E_HImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V4HImode : V8HImode ; case E_QImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V8QImode : V16QImode ; case E_DImode : if ( ! TARGET_NEON_VECTORIZE_DOUBLE ) return V2DImode ; break ; default : ; } if ( TARGET_REALLY_IWMMXT ) switch ( mode ) { case E_SImode : return V2SImode ; case E_HImode : return V4HImode ; case E_QImode : return V8QImode ; default : ; } if ( TARGET_HAVE_MVE ) switch ( mode ) { case E_QImode : return V16QImode ; case E_HImode : return V8HImode ; case E_SImode : return V4SImode ; default : ; } if ( TARGET_HAVE_MVE_FLOAT ) switch ( mode ) { case E_HFmode : return V8HFmode ; case E_SFmode : return V4SFmode ; default : ; } return word_mode ; } </s>

Use the option -mvectorize-with-neon-double to override the use of quardword registers when autovectorizing for Neon , at least until multiple vector widths are supported properly by the middle-end .


<s> bool X86CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { return F . arg_empty ( ) ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s> SDValue AArch64TargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG , unsigned Flags ) const { DEBUG ( dbgs ( ) << "AArch64TargetLowering::getAddr\n" ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , AArch64II :: MO_PAGE | Flags ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , AArch64II :: MO_PAGEOFF | AArch64II :: MO_NC | Flags ) ; SDValue ADRP = DAG . getNode ( AArch64ISD :: ADRP , DL , Ty , Hi ) ; return DAG . getNode ( AArch64ISD :: ADDlow , DL , Ty , ADRP , Lo ) ; } </s>

Return the address accessed by this recipe .


<s> const LC3RegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>


<s> SDValue HexagonTargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { int Idx = cast < JumpTableSDNode > ( Table ) -> getIndex ( ) ; EVT VT = Table . getValueType ( ) ; SDValue T = DAG . getTargetJumpTable ( Idx , VT , HexagonII :: MO_PCREL ) ; return DAG . getNode ( HexagonISD :: AT_PCREL , SDLoc ( Table ) , VT , T ) ; } </s>

Returns relocation base for the given PIC jumptable .


<s> bool ix86_function_arg_regno_p ( int regno ) { int i ; const int * parm_regs ; if ( TARGET_MPX && BND_REGNO_P ( regno ) ) return true ; if ( ! TARGET_64BIT ) { if ( TARGET_MACHO ) return ( regno < REGPARM_MAX || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ! fixed_regs [ regno ] ) ) ; else return ( regno < REGPARM_MAX || ( TARGET_MMX && MMX_REGNO_P ( regno ) && ( regno < FIRST_MMX_REG + MMX_REGPARM_MAX ) ) || ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) ) ; } if ( TARGET_SSE && SSE_REGNO_P ( regno ) && ( regno < FIRST_SSE_REG + SSE_REGPARM_MAX ) ) return true ; if ( ix86_abi == SYSV_ABI && regno == AX_REG ) return true ; if ( ix86_abi == MS_ABI ) parm_regs = x86_64_ms_abi_int_parameter_registers ; else parm_regs = x86_64_int_parameter_registers ; for ( i = 0 ; i < ( ix86_abi == MS_ABI ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX ) ; i ++ ) if ( regno == parm_regs [ i ] ) return true ; return false ; } </s>

Return true when register may be used to pass function parameters .


<s> void function_expander :: rotate_inputs_left ( unsigned int start , unsigned int end ) { rtx new_last = args [ start ] ; for ( unsigned int i = start ; i < end - 1 ; ++ i ) args [ i ] = args [ i + 1 ] ; args [ end - 1 ] = new_last ; } </s>

Rotate inputs args [ START : END ] one position to the left , so that args [ START ] becomes args [ END - 1 ] .


<s> static bool nvptx_wpropagate ( bool pre_p , bool is_call , basic_block block , rtx_insn * insn ) { wcast_data_t data ; data . base = gen_reg_rtx ( Pmode ) ; data . offset = 0 ; data . ptr = NULL_RTX ; bool empty = nvptx_propagate ( is_call , block , insn , pre_p ? PM_read : PM_write , wprop_gen , & data ) ; gcc_assert ( empty == ! data . offset ) ; if ( data . offset ) { rtx init = gen_rtx_SET ( data . base , worker_bcast_sym ) ; emit_insn_after ( init , insn ) ; if ( worker_bcast_size < data . offset ) worker_bcast_size = data . offset ; } return empty ; } </s>

Spill or fill live state that is live at start of BLOCK . PRE_P indicates if this is just before partitioned mode ( do spill ) , or just after it starts ( do fill ) . Sequence is inserted just after INSN . IS_CALL and return as for nvptx_propagate .


<s> const LanaiSubtarget * getSubtargetImpl ( const llvm :: Function & Fn ) const override { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static bool xstormy16_mode_dependent_address_p ( const_rtx x , addr_space_t as ATTRIBUTE_UNUSED ) { if ( LEGITIMATE_ADDRESS_CONST_INT_P ( x , 0 ) && ! LEGITIMATE_ADDRESS_CONST_INT_P ( x , 6 ) ) return true ; if ( GET_CODE ( x ) == PLUS && LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , 1 ) , 0 ) && ! LEGITIMATE_ADDRESS_INTEGER_P ( XEXP ( x , 1 ) , 6 ) ) return true ; return false ; } </s>

Return nonzero if memory address X ( an RTX ) can have different meanings depending on the machine mode of the memory reference it is used for or if the address is valid for some modes but not others . Autoincrement and autodecrement addresses typically have mode-dependent effects because the amount of the increment or decrement is the size of the operand being addressed . Some machines have other mode-dependent addresses . Many RISC machines have no mode-dependent addresses . You may assume that ADDR is a valid address for the machine . On this chip , this is true if the address is valid with an offset of 0 but not of 6 , because in that case it can not be used as an address for DImode or DFmode , or if the address is a post-increment or pre-decrement address .


<s>
void
XCoreRegisterInfo
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
prior
(
MBB
.
end
(
)
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
bool
FP
=
hasFP
(
MF
)
;
if
(
FP
)
{
unsigned
FramePtr
=
XCore
::
R10
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
XCore
::
SETSP_1r
)
)
.
addReg
(
FramePtr
)
;
}
int
FrameSize
=
MFI
->
getStackSize
(
)
;
assert
(
FrameSize
%
4
==
0
&&
"Misaligned frame size"
)
;
FrameSize
/=
4
;
bool
isU6
=
isImmU6
(
FrameSize
)
;
if
(
!
isU6
&&
!
isImmU16
(
FrameSize
)
)
{
std
::
string
msg
;
raw_string_ostream
Msg
(
msg
)
;
Msg
<<
"emitEpilogue Frame size too big: "
<<
FrameSize
;
llvm_report_error
(
Msg
.
str
(
)
)
;
}
if
(
FrameSize
)
{
XCoreFunctionInfo
*
XFI
=
MF
.
getInfo
<
XCoreFunctionInfo
>
(
)
;
if
(
FP
)
{
int
FPSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getFPSpillSlot
(
)
)
;
FPSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
R10
,
FPSpillOffset
,
dl
)
;
}
bool
restoreLR
=
XFI
->
getUsesLR
(
)
;
if
(
restoreLR
&&
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
!=
0
)
{
int
LRSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
;
LRSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
LR
,
LRSpillOffset
,
dl
)
;
restoreLR
=
false
;
}
if
(
restoreLR
)
{
assert
(
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_u6
||
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_lu6
)
;
int
Opcode
=
(
isU6
)
XCore
::
RETSP_u6
:
XCore
::
RETSP_lu6
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
)
.
addImm
(
FrameSize
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
int
Opcode
=
(
isU6
)
XCore
::
LDAWSP_ru6_RRegs
:
XCore
::
LDAWSP_lru6_RRegs
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
,
XCore
::
SP
)
.
addImm
(
FrameSize
)
;
}
}
}
</s>


<s> void SITargetLowering :: bundleInstWithWaitcnt ( MachineInstr & MI ) const { MachineBasicBlock * MBB = MI . getParent ( ) ; const SIInstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; auto I = MI . getIterator ( ) ; auto E = std :: next ( I ) ; BuildMI ( * MBB , E , MI . getDebugLoc ( ) , TII -> get ( AMDGPU :: S_WAITCNT ) ) . addImm ( 0 ) ; MIBundleBuilder Bundler ( * MBB , I , E ) ; finalizeBundle ( * MBB , Bundler . begin ( ) ) ; } </s>

Insert MI into a BUNDLE with an S_WAITCNT 0 immediately following it .


<s> bool isImm ( ) const { return sz <= BlkdropImmLimit ; } </s>


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: Other ) break ; if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 || VT == MVT :: i32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> MCSymbol * LanaiMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> bool enableMachineScheduler ( ) const override { return true ; } </s>

Enable the MachineScheduler pass for all X86 subtargets .


<s> void RISCVInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> static int bank_switch_p ( tree node ATTRIBUTE_UNUSED ) { tree list = M32C_ATTRIBUTES ( node ) ; while ( list ) { if ( is_attribute_p ( "bank_switch" , TREE_PURPOSE ( list ) ) ) return 1 ; list = TREE_CHAIN ( list ) ; } return 0 ; } </s>

Returns TRUE if the given tree has the `` bank_switch '' attribute .


<s> int frame_pointer_required_p ( ) { return ( current_function_calls_alloca || current_function_args_info . nregs == 0 || current_function_varargs || get_frame_size ( ) > 0 ) ; } </s>

Return 1 if frame pointer for current function required .


<s> static int rank_for_reorder ( const void * x , const void * y ) { rtx_insn * tmp = * ( rtx_insn * const * ) y ; rtx_insn * tmp2 = * ( rtx_insn * const * ) x ; if ( SCHED_GROUP_P ( tmp ) != SCHED_GROUP_P ( tmp2 ) ) return SCHED_GROUP_P ( tmp2 ) ? 1 : - 1 ; return INSN_LUID ( tmp ) - INSN_LUID ( tmp2 ) ; } </s>

Comparison function for ready queue sorting .


"SRetReturnReg should have been set in LowerFormalArguments()."

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> const Constant * getValue ( ) const { return Value ; } </s>


<s> static rtx alpha_function_value ( const_tree valtype , const_tree fn_decl_or_type , bool ) { return alpha_function_value_1 ( valtype , fn_decl_or_type , VOIDmode ) ; } </s>


"selector must be an integer constant in the range 0..%wi"

Return the integer constant in ARG . Constrain it to be in the range of the subparts of VEC_TYPE ; issue an error if not .


<s> void aarch64_expand_prologue ( void ) { aarch64_layout_frame ( ) ; HOST_WIDE_INT frame_size = cfun -> machine -> frame . frame_size ; HOST_WIDE_INT initial_adjust = cfun -> machine -> frame . initial_adjust ; HOST_WIDE_INT callee_adjust = cfun -> machine -> frame . callee_adjust ; HOST_WIDE_INT final_adjust = cfun -> machine -> frame . final_adjust ; HOST_WIDE_INT callee_offset = cfun -> machine -> frame . callee_offset ; unsigned reg1 = cfun -> machine -> frame . wb_candidate1 ; unsigned reg2 = cfun -> machine -> frame . wb_candidate2 ; rtx_insn * insn ; if ( aarch64_return_address_signing_enabled ( ) ) { insn = emit_insn ( gen_pacisp ( ) ) ; add_reg_note ( insn , REG_CFA_TOGGLE_RA_MANGLE , const0_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( flag_stack_usage_info ) current_function_static_stack_size = frame_size ; if ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK ) { if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { if ( frame_size > PROBE_INTERVAL && frame_size > STACK_CHECK_PROTECT ) aarch64_emit_probe_stack_range ( STACK_CHECK_PROTECT , frame_size - STACK_CHECK_PROTECT ) ; } else if ( frame_size > 0 ) aarch64_emit_probe_stack_range ( STACK_CHECK_PROTECT , frame_size ) ; } aarch64_sub_sp ( IP0_REGNUM , initial_adjust , true ) ; if ( callee_adjust != 0 ) aarch64_push_regs ( reg1 , reg2 , callee_adjust ) ; if ( frame_pointer_needed ) { if ( callee_adjust == 0 ) aarch64_save_callee_saves ( DImode , callee_offset , R29_REGNUM , R30_REGNUM , false ) ; insn = emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( callee_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; emit_insn ( gen_stack_tie ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } aarch64_save_callee_saves ( DImode , callee_offset , R0_REGNUM , R30_REGNUM , callee_adjust != 0 || frame_pointer_needed ) ; aarch64_save_callee_saves ( DFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != 0 || frame_pointer_needed ) ; aarch64_sub_sp ( IP1_REGNUM , final_adjust , ! frame_pointer_needed ) ; } </s>

Generate the prologue instructions for entry into a function . Establish the stack frame by decreasing the stack pointer with a properly calculated size and , if necessary , create a frame record filled with the values of LR and previous frame pointer . The current FP is also set up if it is in use .


<s> BitVector OpenRISCRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( OpenRISC :: SP ) ; Reserved . set ( OpenRISC :: PC ) ; Reserved . set ( OpenRISC :: ZERO ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( OpenRISC :: FP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .

OpenRISC OpenRISC OpenRISC::SP OpenRISC::PC OpenRISC::ZERO OpenRISC::FP


"Instr doesn't have FrameIndex operand!"

"16-byte alignment violated in eliminateFrameIndex"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { if ( ( Count % 4 ) != 0 ) return false ; for ( uint64_t i = 0 ; i < Count ; i += 4 ) OW -> Write32 ( 0x00400000 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s> const OR1KInstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


"Unsupported calling convention for call"

Selects the correct CCAssignFn for a given CallingConvention value .


<s> const Triple & getTargetTriple ( ) const { return TargetTriple ; } </s>

Get the target triple which is a string describing the target host .


<s> unsigned PPCFrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - 1 ; const PPCRegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { if ( UpdateMF ) MFI . setStackSize ( 0 ) ; return 0 ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize ( FrameSize ) ; return FrameSize ; } </s>

Determine the frame layout but do not update the machine function .


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case E_DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_THUMB1 ) { switch ( mode ) { case E_QImode : gen = gen_atomic_compare_and_swapt1qi_1 ; break ; case E_HImode : gen = gen_atomic_compare_and_swapt1hi_1 ; break ; case E_SImode : gen = gen_atomic_compare_and_swapt1si_1 ; break ; case E_DImode : gen = gen_atomic_compare_and_swapt1di_1 ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : gen = gen_atomic_compare_and_swap32qi_1 ; break ; case E_HImode : gen = gen_atomic_compare_and_swap32hi_1 ; break ; case E_SImode : gen = gen_atomic_compare_and_swap32si_1 ; break ; case E_DImode : gen = gen_atomic_compare_and_swap32di_1 ; break ; default : gcc_unreachable ( ) ; } } bdst = TARGET_THUMB1 ? bval : gen_rtx_REG ( CC_Zmode , CC_REGNUM ) ; emit_insn ( gen ( bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; if ( TARGET_THUMB1 ) emit_insn ( gen_cstoresi_eq0_thumb1 ( bval , bdst ) ) ; else { x = gen_rtx_EQ ( SImode , bdst , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } } </s>


<s> EVT ARMTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= 16 && ( memOpAlign ( SrcAlign , DstAlign , 16 ) || ( allowsUnalignedMemoryAccesses ( MVT :: v2f64 , & Fast ) && Fast ) ) ) { return MVT :: v2f64 ; } else if ( Size >= 8 && ( memOpAlign ( SrcAlign , DstAlign , 8 ) || ( allowsUnalignedMemoryAccesses ( MVT :: f64 , & Fast ) && Fast ) ) ) { return MVT :: f64 ; } } if ( Size >= 4 ) return MVT :: i32 ; else if ( Size >= 2 ) return MVT :: i16 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> unsigned X86AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: EVEX ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX || ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & X86II :: EncodingMask ) != X86II :: VEX ) return Match_Unsupported ; if ( MCID . TSFlags & X86II :: ExplicitVEXPrefix && ( ForcedVEXEncoding != VEXEncoding_VEX && ForcedVEXEncoding != VEXEncoding_VEX2 && ForcedVEXEncoding != VEXEncoding_VEX3 ) ) return Match_Unsupported ; switch ( Opc ) { case X86 :: VCVTSD2SIZrm_Int : case X86 :: VCVTSD2SI64Zrm_Int : case X86 :: VCVTSS2SIZrm_Int : case X86 :: VCVTSS2SI64Zrm_Int : case X86 :: VCVTTSD2SIZrm : case X86 :: VCVTTSD2SIZrm_Int : case X86 :: VCVTTSD2SI64Zrm : case X86 :: VCVTTSD2SI64Zrm_Int : case X86 :: VCVTTSS2SIZrm : case X86 :: VCVTTSS2SIZrm_Int : case X86 :: VCVTTSS2SI64Zrm : case X86 :: VCVTTSS2SI64Zrm_Int : if ( ForcedVEXEncoding != VEXEncoding_EVEX ) return Match_Unsupported ; break ; } return Match_Success ; } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


Return nonzero if X ( an RTX ) is a legitimate memory address on the target machine for a memory operand of mode MODE .


runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> Value * AArch64TargetLowering :: getIRStackGuard ( IRBuilderBase & IRB ) const { if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , 0x28 ) ; if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - 0x10 ) ; return TargetLowering :: getIRStackGuard ( IRB ) ; } </s>

If the target has a standard location for the stack protector cookie , returns the address of that location .


<s> void ARMElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { const ARMBaseTargetMachine & ARM_TM = static_cast < const ARMBaseTargetMachine & > ( TM ) ; bool isAAPCS_ABI = ARM_TM . TargetABI == ARMBaseTargetMachine :: ARMABI :: ARM_ABI_AAPCS ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( isAAPCS_ABI ) ; if ( isAAPCS_ABI ) { LSDASection = nullptr ; } } </s>

This method must be called before any actual lowering is done .

ARM ARM ARM ARM ARM ARM ARM ARMABI::ARM_ABI_AAPCS


<s> static bool ix86_expand_vector_init_one_var ( bool mmx_ok , machine_mode mode , rtx target , rtx vals , int one_var ) { rtx var = XVECEXP ( vals , 0 , one_var ) ; machine_mode wmode ; rtx const_vec , x ; const_vec = copy_rtx ( vals ) ; XVECEXP ( const_vec , 0 , one_var ) = CONST0_RTX ( GET_MODE_INNER ( mode ) ) ; const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( const_vec , 0 ) ) ; switch ( mode ) { case V2DFmode : case V2DImode : case V2SFmode : case V2SImode : return false ; case V4DImode : if ( ! TARGET_64BIT ) return false ; case V4DFmode : case V8SFmode : case V8SImode : case V16HImode : case V32QImode : case V4SFmode : case V4SImode : case V8HImode : case V4HImode : break ; case V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case V8QImode : wmode = V4HImode ; goto widen ; widen : x = XVECEXP ( vals , 0 , one_var ^ 1 ) ; if ( one_var & 1 ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( 8 ) , NULL_RTX , 1 , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & 0xff ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( INTVAL ( x ) << 8 , HImode ) ; } if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , 1 , OPTAB_LIB_WIDEN ) ; x = gen_reg_rtx ( wmode ) ; emit_move_insn ( x , gen_lowpart ( wmode , const_vec ) ) ; ix86_expand_vector_set ( mmx_ok , x , var , one_var >> 1 ) ; emit_move_insn ( target , gen_lowpart ( mode , x ) ) ; return true ; default : return false ; } emit_move_insn ( target , const_vec ) ; ix86_expand_vector_set ( mmx_ok , target , var , one_var ) ; return true ; } </s>

A subroutine of ix86_expand_vector_init . Store into TARGET a vector consisting of the values in VALS . It is known that all elements except ONE_VAR are constants . Return true if successful .


<s> CCAssignFn * X86FastISel :: CCAssignFnForCall ( unsigned CC , bool isTaillCall ) { if ( Subtarget -> is64Bit ( ) ) { if ( Subtarget -> isTargetWin64 ( ) ) return CC_X86_Win64_C ; else if ( CC == CallingConv :: Fast && isTaillCall ) return CC_X86_64_TailCall ; else return CC_X86_64_C ; } if ( CC == CallingConv :: X86_FastCall ) return CC_X86_32_FastCall ; else if ( CC == CallingConv :: Fast ) return CC_X86_32_FastCC ; else return CC_X86_32_C ; } </s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> SMLoc getStartLoc ( ) const override { return StartLoc ; } </s>

getStartLoc - Get the location of the first token of this operand .


<s> void visitCallInst ( CallInst & I ) { if ( ! I . getCalledFunction ( ) ) return ; StringRef Name = I . getCalledFunction ( ) -> getName ( ) ; if ( Name == "llvm.AMDGPU.tex" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.R600.tex" , "llvm.R600.texc" ) ; return ; } if ( Name == "llvm.AMDGPU.txl" ) { ReplaceTexIntrinsic ( I , true , TexSign , "llvm.R600.txl" , "llvm.R600.txlc" ) ; return ; } if ( Name == "llvm.AMDGPU.txb" ) { ReplaceTexIntrinsic ( I , true , TexSign , "llvm.R600.txb" , "llvm.R600.txbc" ) ; return ; } if ( Name == "llvm.AMDGPU.txf" ) { ReplaceTXF ( I ) ; return ; } if ( Name == "llvm.AMDGPU.txq" ) { ReplaceTexIntrinsic ( I , false , TexQSign , "llvm.R600.txq" , "llvm.R600.txq" ) ; return ; } if ( Name == "llvm.AMDGPU.ddx" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.R600.ddx" , "llvm.R600.ddx" ) ; return ; } if ( Name == "llvm.AMDGPU.ddy" ) { ReplaceTexIntrinsic ( I , false , TexSign , "llvm.R600.ddy" , "llvm.R600.ddy" ) ; return ; } } </s>


"position-independent code requires the Linux ABI"

"BMX instructions are only supported with R2 architecture"

"CDX instructions are only supported with R2 architecture"


<s> bool forceScalarizeMaskedScatter ( VectorType * VTy , Align Alignment ) { return forceScalarizeMaskedGather ( VTy , Alignment ) ; } </s>

Return true if the target forces scalarizing of llvm.masked.scatter intrinsics .


<s> const MCPhysReg * ARMBaseRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const ARMSubtarget & STI = MF -> getSubtarget < ARMSubtarget > ( ) ; bool UseSplitPush = STI . splitFramePushPop ( ) ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : ( UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ) ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( "interrupt" ) ) { if ( STI . isMClass ( ) ) { return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( "interrupt" ) . getValueAsString ( ) == "FIQ" ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } if ( STI . isTargetDarwin ( ) && STI . getTargetLowering ( ) -> supportSwiftError ( ) && F -> getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_iOS_SwiftError_SaveList ; if ( STI . isTargetDarwin ( ) && F -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS ) return MF -> getInfo < ARMFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_iOS_CXX_TLS_PE_SaveList : CSR_iOS_CXX_TLS_SaveList ; return RegList ; } </s>

ARM ARM ARM ARM "interrupt" "interrupt" "FIQ" ARM


<s> MachineInstr * SystemZInstrInfo :: convertToThreeAddress ( MachineInstr & MI , LiveVariables * LV ) const { MachineBasicBlock * MBB = MI . getParent ( ) ; if ( LogicOp And = interpretAndImmediate ( MI . getOpcode ( ) ) ) { uint64_t Imm = MI . getOperand ( 2 ) . getImm ( ) << And . ImmLSB ; Imm |= allOnes ( And . RegSize ) & ~ ( allOnes ( And . ImmSize ) << And . ImmLSB ) ; unsigned Start , End ; if ( isRxSBGMask ( Imm , And . RegSize , Start , End ) ) { unsigned NewOpcode ; if ( And . RegSize == 64 ) { NewOpcode = SystemZ :: RISBG ; if ( STI . hasMiscellaneousExtensions ( ) ) NewOpcode = SystemZ :: RISBGN ; } else { NewOpcode = SystemZ :: RISBMux ; Start &= 31 ; End &= 31 ; } MachineOperand & Dest = MI . getOperand ( 0 ) ; MachineOperand & Src = MI . getOperand ( 1 ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpcode ) ) . add ( Dest ) . addReg ( 0 ) . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) . addImm ( Start ) . addImm ( End + 128 ) . addImm ( 0 ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = 1 ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } transferDeadCC ( & MI , MIB ) ; return MIB ; } } return nullptr ; } </s>

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag .


<s> unsigned getReturnSaveOffset ( ) const { return ReturnSaveOffset ; } </s>

getReturnSaveOffset - Return the previous frame offset to save the return address .


<s> bool aarch64_float_const_zero_rtx_p ( rtx x ) { REAL_VALUE_TYPE r ; if ( GET_MODE ( x ) == VOIDmode ) return false ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_MINUS_ZERO ( r ) ) return ! HONOR_SIGNED_ZEROS ( GET_MODE ( x ) ) ; return REAL_VALUES_EQUAL ( r , dconst0 ) ; } </s>

Return TRUE if rtx X is immediate constant 0.0


<s> bool PatmosRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , unsigned Reg , int & FrameIdx ) const { if ( Patmos :: PRegsRegClass . contains ( Reg ) ) return true ; const PatmosMachineFunctionInfo & PMFI = * MF . getInfo < PatmosMachineFunctionInfo > ( ) ; if ( Reg == Patmos :: S0 && PMFI . getS0SpillReg ( ) ) return true ; return false ; } </s>

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register .

Patmos Patmos Patmos::PRegsRegClass Patmos Patmos Patmos::S0


<s>
bool
WebAssemblyInstrInfo
::
reverseBranchCondition
(
SmallVectorImpl
<
MachineOperand
>
&
Cond
)
const
{
assert
(
Cond
.
size
(
)
==
2
&&
"Expected a flag and a successor block"
)
;
Cond
.
front
(
)
=
MachineOperand
::
CreateImm
(
!
Cond
.
front
(
)
.
getImm
(
)
)
;
return
false
;
}
</s>

Reverses the branch condition of the specified condition list , returning false on success and true if it can not be reversed .

WebAssembly
WebAssembly
2
"Expected a flag and a successor block"


<s> void SPIRVOCLRegularizer :: visitCallInst ( CallInst & CI ) { auto F = CI . getCalledFunction ( ) ; if ( ! F ) return ; auto MangledName = F -> getName ( ) ; size_t n ; int status ; char * NameStr = itaniumDemangle ( F -> getName ( ) . data ( ) , nullptr , & n , & status ) ; StringRef DemangledName ( NameStr ) ; if ( DemangledName . startswith ( "fmin" ) || DemangledName . startswith ( "fmax" ) || DemangledName . startswith ( "min" ) || DemangledName . startswith ( "max" ) ) visitCallScalToVec ( & CI , MangledName , DemangledName ) ; free ( NameStr ) ; } </s>


<s> void mips_gen_conditional_trap ( rtx * operands ) { rtx op0 , op1 ; enum rtx_code cmp_code = GET_CODE ( operands [ 0 ] ) ; enum machine_mode mode = GET_MODE ( cmp_operands [ 0 ] ) ; switch ( cmp_code ) { case GT : cmp_code = LT ; break ; case LE : cmp_code = GE ; break ; case GTU : cmp_code = LTU ; break ; case LEU : cmp_code = GEU ; break ; default : break ; } if ( cmp_code == GET_CODE ( operands [ 0 ] ) ) { op0 = cmp_operands [ 0 ] ; op1 = cmp_operands [ 1 ] ; } else { op0 = cmp_operands [ 1 ] ; op1 = cmp_operands [ 0 ] ; } op0 = force_reg ( mode , op0 ) ; if ( ! arith_operand ( op1 , mode ) ) op1 = force_reg ( mode , op1 ) ; emit_insn ( gen_rtx_TRAP_IF ( VOIDmode , gen_rtx_fmt_ee ( cmp_code , mode , op0 , op1 ) , operands [ 1 ] ) ) ; } </s>

Emit a conditional trap . OPERANDS is the array of operands passed to the conditional_trap expander .


<s> void RISCVFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; for ( int Id = MFI . getObjectIndexBegin ( ) , EId = MFI . getObjectIndexEnd ( ) ; Id < EId ; Id ++ ) { if ( MFI . getStackID ( Id ) == TargetStackID :: RISCVVector && ! MFI . isDeadObjectIndex ( Id ) ) { RVFI -> setHasSpillVRs ( ) ; } } if ( hasFP ( MF ) ) { SavedRegs . set ( RISCV :: X1 ) ; SavedRegs . set ( RISCV :: X8 ) ; } if ( hasBP ( MF ) ) SavedRegs . set ( RISCVABI :: getBPReg ( ) ) ; if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { RISCV :: X1 , RISCV :: X5 , RISCV :: X6 , RISCV :: X7 , RISCV :: X10 , RISCV :: X11 , RISCV :: X12 , RISCV :: X13 , RISCV :: X14 , RISCV :: X15 , RISCV :: X16 , RISCV :: X17 , RISCV :: X28 , RISCV :: X29 , RISCV :: X30 , RISCV :: X31 , 0 } ; for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtD ( ) || MF . getSubtarget < RISCVSubtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = 0 ; Regs [ i ] ; ++ i ) if ( RISCV :: FPR32RegClass . contains ( Regs [ i ] ) || RISCV :: FPR64RegClass . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s> bool X86FastISel :: tryToFoldLoadIntoMI ( MachineInstr * MI , unsigned OpNo , const LoadInst * LI ) { X86AddressMode AM ; if ( ! X86SelectAddress ( LI -> getOperand ( 0 ) , AM ) ) return false ; const X86InstrInfo & XII = ( const X86InstrInfo & ) TII ; unsigned Size = DL . getTypeAllocSize ( LI -> getType ( ) ) ; unsigned Alignment = LI -> getAlignment ( ) ; SmallVector < MachineOperand , 8 > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( ! Result ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ; } </s>

The specified machine instr operand is a vreg , and that vreg is being provided by the specified load instruction .


<s> bool aarch64_sve_struct_memory_operand_p ( rtx op ) { if ( ! MEM_P ( op ) ) return false ; machine_mode mode = GET_MODE ( op ) ; struct aarch64_address_info addr ; if ( ! aarch64_classify_address ( & addr , XEXP ( op , 0 ) , SVE_BYTE_MODE , false , ADDR_QUERY_ANY ) || addr . type != ADDRESS_REG_IMM ) return false ; poly_int64 first = addr . const_offset ; poly_int64 last = first + GET_MODE_SIZE ( mode ) - BYTES_PER_SVE_VECTOR ; return ( offset_4bit_signed_scaled_p ( SVE_BYTE_MODE , first ) && offset_4bit_signed_scaled_p ( SVE_BYTE_MODE , last ) ) ; } </s>

Return true if OP is a valid MEM operand for an SVE_STRUCT mode . We need to be able to access the individual pieces , so the range is different from LD [ 234 ] and ST [ 234 ] .


<s> bool ARMTargetLowering :: shouldExpandAtomicStoreInIR ( StoreInst * SI ) const { bool has64BitAtomicStore ; if ( Subtarget -> isMClass ( ) ) has64BitAtomicStore = false ; else if ( Subtarget -> isThumb ( ) ) has64BitAtomicStore = Subtarget -> hasV7Ops ( ) ; else has64BitAtomicStore = Subtarget -> hasV6Ops ( ) ; unsigned Size = SI -> getValueOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == 64 && has64BitAtomicStore ; } </s>

Returns how the given ( atomic ) store should be expanded by the IR-level AtomicExpand pass into .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , 0 , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> bool NyuziRegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool RISCVTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { if ( VT == MVT :: f16 && ! Subtarget . hasStdExtZfh ( ) ) return false ; if ( VT == MVT :: f32 && ! Subtarget . hasStdExtF ( ) ) return false ; if ( VT == MVT :: f64 && ! Subtarget . hasStdExtD ( ) ) return false ; return Imm . isZero ( ) ; } </s>

Returns true if the target can instruction select the specified FP immediate natively .


"AMDGPU Control Flow Graph structurizer Pass"

getPassName - Return a nice clean name for a pass .


<s> SDValue ARMSelectionDAGInfo :: EmitTargetCodeForMemmove ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , Align Alignment , bool isVolatile , bool MustPreserveCheriCapabilities , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { return EmitSpecializedLibcall ( DAG , dl , Chain , Dst , Src , Size , Alignment . value ( ) , RTLIB :: MEMMOVE ) ; } </s>

Emit target-specific code that performs a memmove .


<s> bool isMem ( ) const override { return false ; } </s>


<s>
void
X86AsmBackend
::
relaxInstruction
(
MCInst
&
Inst
,
const
MCSubtargetInfo
&
STI
)
const
{
bool
Is16BitMode
=
STI
.
getFeatureBits
(
)
[
X86
::
Is16Bit
]
;
unsigned
RelaxedOp
=
getRelaxedOpcode
(
Inst
,
Is16BitMode
)
;
if
(
RelaxedOp
==
Inst
.
getOpcode
(
)
)
{
SmallString
<
256
>
Tmp
;
raw_svector_ostream
OS
(
Tmp
)
;
Inst
.
dump_pretty
(
OS
)
;
OS
<<
"\n"
;
report_fatal_error
(
"unexpected instruction to relax: "
+
OS
.
str
(
)
)
;
}
Inst
.
setOpcode
(
RelaxedOp
)
;
}
</s>

Relax the instruction in the given fragment to the next wider instruction .


<s> bool nds32_isr_function_p ( tree func ) { tree t_intr ; tree t_excp ; tree t_reset ; tree attrs ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) abort ( ) ; attrs = DECL_ATTRIBUTES ( func ) ; t_intr = lookup_attribute ( "interrupt" , attrs ) ; t_excp = lookup_attribute ( "exception" , attrs ) ; t_reset = lookup_attribute ( "reset" , attrs ) ; return ( ( t_intr != NULL_TREE ) || ( t_excp != NULL_TREE ) || ( t_reset != NULL_TREE ) ) ; } </s>


<s> bool AArch64FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MFI . hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ; return false ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
SDValue
VideocoreTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Videocore
Videocore
"Should not custom lower this!"
ISD::BRCOND
ISD::BR_CC
ISD::SELECT
ISD::SELECT_CC
ISD::SETCC


<s>
void
encodeInstruction
(
const
MCInst
&
MI
,
raw_ostream
&
OS
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
override
{
unsigned
Opcode
=
MI
.
getOpcode
(
)
;
const
MCInstrDesc
&
Desc
=
MCII
.
get
(
Opcode
)
;
if
(
Opcode
==
TargetOpcode
::
COPY_TO_REGCLASS
)
return
;
uint64_t
Bits
=
getBinaryCodeForInstr
(
MI
,
Fixups
,
STI
)
;
unsigned
Size
=
Desc
.
getSize
(
)
;
switch
(
Size
)
{
case
4
:
if
(
IsLittleEndian
)
{
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint32_t
>
(
Bits
)
;
}
break
;
case
8
:
if
(
IsLittleEndian
)
{
uint64_t
Swapped
=
(
Bits
<<
32
)
|
(
Bits
>>
32
)
;
support
::
endian
::
Writer
<
support
::
little
>
(
OS
)
.
write
<
uint64_t
>
(
Swapped
)
;
}
else
{
support
::
endian
::
Writer
<
support
::
big
>
(
OS
)
.
write
<
uint64_t
>
(
Bits
)
;
}
break
;
default
:
llvm_unreachable
(
"Invalid instruction size"
)
;
}
++
MCNumEmitted
;
}
</s>

Encode the given Inst to bytes and append to CB .

PowerPC
4
support::endian
support::little
support::endian
support::big
8
32
32
support::endian
support::little
support::endian
support::big
"Invalid instruction size"


<s> bool SIInstrInfo :: isOperandLegal ( const MachineInstr * MI , unsigned OpIdx , const MachineOperand * MO ) const { const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & InstDesc = MI -> getDesc ( ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - 1 ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI -> getOperand ( OpIdx ) ; if ( isVALU ( * MI ) && usesConstantBus ( MRI , * MO , DefinedRC -> getSize ( ) ) ) { RegSubRegPair SGPRUsed ; if ( MO -> isReg ( ) ) SGPRUsed = RegSubRegPair ( MO -> getReg ( ) , MO -> getSubReg ( ) ) ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI -> getOperand ( i ) ; if ( Op . isReg ( ) && ( Op . getReg ( ) != SGPRUsed . Reg || Op . getSubReg ( ) != SGPRUsed . SubReg ) && usesConstantBus ( MRI , Op , getOpSize ( * MI , i ) ) ) { return false ; } } } if ( MO -> isReg ( ) ) { assert ( DefinedRC ) ; return isLegalRegOperand ( MRI , OpInfo , * MO ) ; } assert ( MO -> isImm ( ) || MO -> isTargetIndex ( ) || MO -> isFI ( ) ) ; if ( ! DefinedRC ) { return true ; } return isImmOperandLegal ( MI , OpIdx , * MO ) ; } </s>

Check if MO is a legal operand if it was the OpIdx Operand for MI .


<s> ARMSubtarget :: ARMSubtarget ( const std :: string & TT , const std :: string & FS , bool isT ) : ARMArchVersion ( V4 ) , ARMFPUType ( None ) , UseNEONForSinglePrecisionFP ( false ) , SlowVMLx ( false ) , IsThumb ( isT ) , ThumbMode ( Thumb1 ) , PostRAScheduler ( false ) , IsR9Reserved ( ReserveR9 ) , UseMovt ( UseMOVT ) , HasFP16 ( false ) , stackAlignment ( 4 ) , CPUString ( "generic" ) , TargetType ( isELF ) , TargetABI ( ARM_ABI_APCS ) { if ( FloatABIType == FloatABI :: Default ) FloatABIType = FloatABI :: Soft ; CPUString = ParseSubtargetFeatures ( FS , CPUString ) ; if ( CPUString == "generic" && ( FS . empty ( ) || FS == "generic" ) ) ARMArchVersion = V4T ; unsigned Len = TT . length ( ) ; unsigned Idx = 0 ; if ( Len >= 5 && TT . substr ( 0 , 4 ) == "armv" ) Idx = 4 ; else if ( Len >= 6 && TT . substr ( 0 , 5 ) == "thumb" ) { IsThumb = true ; if ( Len >= 7 && TT [ 5 ] == 'v' ) Idx = 6 ; } if ( Idx ) { unsigned SubVer = TT [ Idx ] ; if ( SubVer >= '7' && SubVer <= '9' ) { ARMArchVersion = V7A ; } else if ( SubVer == '6' ) { ARMArchVersion = V6 ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == '2' ) ARMArchVersion = V6T2 ; } else if ( SubVer == '5' ) { ARMArchVersion = V5T ; if ( Len >= Idx + 3 && TT [ Idx + 1 ] == 't' && TT [ Idx + 2 ] == 'e' ) ARMArchVersion = V5TE ; } else if ( SubVer == '4' ) { if ( Len >= Idx + 2 && TT [ Idx + 1 ] == 't' ) ARMArchVersion = V4T ; else ARMArchVersion = V4 ; } } if ( ARMArchVersion >= V6T2 ) ThumbMode = Thumb2 ; else if ( ThumbMode >= Thumb2 ) ARMArchVersion = V6T2 ; if ( Len >= 10 ) { if ( TT . find ( "-darwin" ) != std :: string :: npos ) TargetType = isDarwin ; } if ( TT . find ( "eabi" ) != std :: string :: npos ) TargetABI = ARM_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = 8 ; if ( isTargetDarwin ( ) ) IsR9Reserved = ReserveR9 | ( ARMArchVersion < V6 ) ; if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> static void emit_load_locked ( machine_mode mode , rtx reg , rtx mem ) { rtx ( * fn ) ( rtx , rtx ) = NULL ; switch ( mode ) { case E_QImode : fn = gen_load_lockedqi ; break ; case E_HImode : fn = gen_load_lockedhi ; break ; case E_SImode : if ( GET_MODE ( mem ) == QImode ) fn = gen_load_lockedqi_si ; else if ( GET_MODE ( mem ) == HImode ) fn = gen_load_lockedhi_si ; else fn = gen_load_lockedsi ; break ; case E_DImode : fn = gen_load_lockeddi ; break ; case E_TImode : fn = gen_load_lockedti ; break ; default : gcc_unreachable ( ) ; } emit_insn ( fn ( reg , mem ) ) ; } </s>

A subroutine of the atomic operation splitters . Emit a load-locked instruction in MODE . For QI/HImode , possibly use a pattern than includes the zero_extend operation .


<s>
void
P2AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
MCFixupKind
Kind
=
Fixup
.
getKind
(
)
;
Value
=
adjustFixupValue
(
Fixup
,
Value
)
;
if
(
!
Value
)
return
;
LLVM_DEBUG
(
errs
(
)
<<
"-- applying fixup\n"
)
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
unsigned
NumBytes
=
(
getFixupKindInfo
(
Kind
)
.
TargetSize
+
7
)
/
8
;
uint64_t
CurVal
=
0
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
CurVal
|=
(
uint64_t
)
(
(
uint8_t
)
Data
[
Offset
+
i
]
)
<<
(
i
*
8
)
;
}
uint64_t
Mask
=
(
(
uint64_t
)
(
1
)
>>
(
64
getFixupKindInfo
(
Kind
)
.
TargetSize
)
)
;
CurVal
|=
Value
&
Mask
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
=
(
uint8_t
)
(
(
CurVal
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
void
AMDGPUAsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
Value
=
adjustFixupValue
(
Fixup
,
Value
,
&
Asm
.
getContext
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
uint32_t
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
Data
[
Offset
+
i
]
|=
static_cast
<
uint8_t
>
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
</s>


<s> WebAssemblySubtarget :: WebAssemblySubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : WebAssemblyGenSubtargetInfo ( TT , CPU , FS ) , HasSIMD128 ( false ) , HasAtomics ( false ) , HasNontrappingFPToInt ( false ) , HasSignExt ( false ) , HasExceptionHandling ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

WebAssembly WebAssembly WebAssembly WebAssembly


"initialize $fp near to $gp location.\n"

"\t! If linker fails to use fp-as-gp transformation,\n"

After rtl prologue has been expanded , this function is used .


"Function has local memory argument.  Promoting to "

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


"Relocation required in an instruction that we cannot encode!"

getMachineOpValue - Return binary encoding of operand .


<s>
unsigned
X86TargetLowering
::
getRegisterByName
(
const
char
*
RegName
)
const
{
unsigned
Reg
=
StringSwitch
<
unsigned
>
(
RegName
)
.
Case
(
"esp"
,
X86
::
ESP
)
.
Case
(
"rsp"
,
X86
::
RSP
)
.
Default
(
0
)
;
if
(
Reg
)
return
Reg
;
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
bool
AArch64FrameLowering
::
spillCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
for
(
auto
RPII
=
RegPairs
.
rbegin
(
)
,
RPIE
=
RegPairs
.
rend
(
)
;
RPII
!=
RPIE
;
++
RPII
)
{
RegPairInfo
RPI
=
*
RPII
;
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
StrOpc
;
bool
BumpSP
=
RPII
==
RegPairs
.
rbegin
(
)
;
if
(
RPI
.
IsGPR
)
{
if
(
BumpSP
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXpre
:
AArch64
::
STRXpre
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPXi
:
AArch64
::
STRXui
;
}
else
{
if
(
BumpSP
)
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDpre
:
AArch64
::
STRDpre
;
else
StrOpc
=
RPI
.
isPaired
(
)
AArch64
::
STPDi
:
AArch64
::
STRDui
;
}
DEBUG
(
dbgs
(
)
<<
"CSR spill: ("
<<
TRI
->
getName
(
Reg1
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
TRI
->
getName
(
Reg2
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
const
int
Offset
=
BumpSP
RPI
.
Offset
:
RPI
.
Offset
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
StrOpc
)
)
;
if
(
BumpSP
)
MIB
.
addReg
(
AArch64
::
SP
,
RegState
::
Define
)
;
if
(
RPI
.
isPaired
(
)
)
{
MBB
.
addLiveIn
(
Reg1
)
;
MBB
.
addLiveIn
(
Reg2
)
;
MIB
.
addReg
(
Reg2
,
getPrologueDeath
(
MF
,
Reg2
)
)
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
else
{
MBB
.
addLiveIn
(
Reg1
)
;
MIB
.
addReg
(
Reg1
,
getPrologueDeath
(
MF
,
Reg1
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
BumpSP
Offset
*
8
:
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
}
return
true
;
}
</s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static bool pa_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; if ( TARGET_64BIT ) return size <= 0 ; else return size <= 0 || size > 8 ; } </s>

In the 32-bit runtime , arguments larger than eight bytes are passed by invisible reference . As a GCC extension , we also pass anything with a zero or variable size by reference . The 64-bit runtime does not describe passing any types by invisible reference . The internals of GCC ca n't currently handle passing empty structures , and zero or variable length arrays when they are not passed entirely on the stack or by reference . Thus , as a GCC extension , we pass these types by reference . The HP compiler does n't support these types , so hopefully there should n't be any compatibility issues . This may have to be revisited when HP releases a C99 compiler or updates the ABI .


<s> virtual void initialize ( ScheduleDAGMI * dag ) { } </s>

Initialize the strategy after building the DAG for a new region .


<s> bool isSuitableForJumpTable ( const SwitchInst * SI , uint64_t NumCases , uint64_t Range ) const override { return false ; } </s>

Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases , Range range of values .


<s>
SDValue
CSKYTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"unimplemented op"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
}
}
</s>

CSKY
CSKY
"unimplemented op"
ISD::GlobalAddress
ISD::ExternalSymbol
ISD::GlobalTLSAddress
ISD::JumpTable
ISD::BlockAddress
ISD::VASTART
ISD::FRAMEADDR
ISD::RETURNADDR


<s> bool SystemZTDCPass :: runOnFunction ( Function & F ) { ConvertedInsts . clear ( ) ; LogicOpsWorklist . clear ( ) ; PossibleJunk . clear ( ) ; for ( auto & I : instructions ( F ) ) { if ( I . getOpcode ( ) == Instruction :: FCmp ) convertFCmp ( cast < CmpInst > ( I ) ) ; else if ( I . getOpcode ( ) == Instruction :: ICmp ) convertICmp ( cast < CmpInst > ( I ) ) ; } if ( ConvertedInsts . empty ( ) ) return false ; while ( ! LogicOpsWorklist . empty ( ) ) { BinaryOperator * Op = LogicOpsWorklist . back ( ) ; LogicOpsWorklist . pop_back ( ) ; if ( ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 0 ) ) ) && ConvertedInsts . count ( dyn_cast < Instruction > ( Op -> getOperand ( 1 ) ) ) && ! ConvertedInsts . count ( Op ) ) convertLogicOp ( * Op ) ; } Module & M = * F . getParent ( ) ; auto & Ctx = M . getContext ( ) ; Value * Zero32 = ConstantInt :: get ( Type :: getInt32Ty ( Ctx ) , 0 ) ; bool MadeChange = false ; for ( auto & It : reverse ( ConvertedInsts ) ) { Instruction * I = It . first ; Value * V ; int Mask ; bool Worthy ; std :: tie ( V , Mask , Worthy ) = It . second ; if ( ! I -> user_empty ( ) ) { if ( ! Worthy ) continue ; Value * TDCFunc = Intrinsic :: getDeclaration ( & M , Intrinsic :: s390_tdc , V -> getType ( ) ) ; IRBuilder < > IRB ( I ) ; Value * MaskVal = ConstantInt :: get ( Type :: getInt64Ty ( Ctx ) , Mask ) ; Instruction * TDC = IRB . CreateCall ( TDCFunc , { V , MaskVal } ) ; Value * ICmp = IRB . CreateICmp ( CmpInst :: ICMP_NE , TDC , Zero32 ) ; I -> replaceAllUsesWith ( ICmp ) ; } I -> eraseFromParent ( ) ; MadeChange = true ; } if ( ! MadeChange ) return false ; for ( auto * I : PossibleJunk ) if ( I -> user_empty ( ) ) I -> eraseFromParent ( ) ; return true ; } </s>


<s> rtx riscv_gen_gpr_save_insn ( struct riscv_frame_info * frame ) { unsigned count = riscv_save_libcall_count ( frame -> mask ) ; unsigned veclen = 1 + 2 + 1 + count ; rtvec vec = rtvec_alloc ( veclen ) ; gcc_assert ( veclen <= ARRAY_SIZE ( gpr_save_reg_order ) ) ; RTVEC_ELT ( vec , 0 ) = gen_rtx_UNSPEC_VOLATILE ( VOIDmode , gen_rtvec ( 1 , GEN_INT ( count ) ) , UNSPECV_GPR_SAVE ) ; for ( unsigned i = 1 ; i < veclen ; ++ i ) { unsigned regno = gpr_save_reg_order [ i ] ; rtx reg = gen_rtx_REG ( Pmode , regno ) ; rtx elt ; if ( i < 3 ) elt = gen_rtx_CLOBBER ( Pmode , reg ) ; else elt = gen_rtx_USE ( Pmode , reg ) ; RTVEC_ELT ( vec , i ) = elt ; } gcc_assert ( ( count == 0 ) || BITSET_P ( frame -> mask , gpr_save_reg_order [ veclen - 1 ] ) ) ; return gen_rtx_PARALLEL ( VOIDmode , vec ) ; } </s>

Helper function for generating gpr_save pattern .


<s> void mips_expand_vcondv2sf ( rtx dest , rtx true_src , rtx false_src , enum rtx_code cond , rtx cmp_op0 , rtx cmp_op1 ) { rtx cmp_result ; bool reversed_p ; reversed_p = mips_reversed_fp_cond ( & cond ) ; cmp_result = mips_allocate_fcc ( CCV2mode ) ; emit_insn ( gen_scc_ps ( cmp_result , gen_rtx_fmt_ee ( cond , VOIDmode , cmp_op0 , cmp_op1 ) ) ) ; if ( reversed_p ) emit_insn ( gen_mips_cond_move_tf_ps ( dest , false_src , true_src , cmp_result ) ) ; else emit_insn ( gen_mips_cond_move_tf_ps ( dest , true_src , false_src , cmp_result ) ) ; } </s>

Implement : ( set temp ( COND : CCV2 CMP_OP0 CMP_OP1 ) ) ( set DEST ( unspec [ TRUE_SRC FALSE_SRC temp ] UNSPEC_MOVE_TF_PS ) )


<s> bool AArch64TargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { return ExtVal . getValueType ( ) . isScalableVector ( ) || useSVEForFixedLengthVectorVT ( ExtVal . getValueType ( ) , true ) ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .


<s> Optional < ParamLoadedValue > MipsInstrInfo :: describeLoadedValue ( const MachineInstr & MI , Register Reg ) const { DIExpression * Expr = DIExpression :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , { } ) ; if ( auto RegImm = isAddImmediate ( MI , Reg ) ) { Register SrcReg = RegImm -> Reg ; int64_t Offset = RegImm -> Imm ; if ( SrcReg == Mips :: ZERO || SrcReg == Mips :: ZERO_64 ) { return ParamLoadedValue ( MI . getOperand ( 2 ) , Expr ) ; } Expr = DIExpression :: prepend ( Expr , DIExpression :: ApplyOffset , Offset ) ; return ParamLoadedValue ( MachineOperand :: CreateReg ( SrcReg , false ) , Expr ) ; } else if ( auto DestSrc = isCopyInstr ( MI ) ) { const MachineFunction * MF = MI . getMF ( ) ; const TargetRegisterInfo * TRI = MF -> getSubtarget ( ) . getRegisterInfo ( ) ; Register DestReg = DestSrc -> Destination -> getReg ( ) ; if ( TRI -> isSuperRegister ( Reg , DestReg ) || TRI -> isSubRegister ( Reg , DestReg ) ) return None ; } return TargetInstrInfo :: describeLoadedValue ( MI , Reg ) ; } </s>

Produce the expression describing the MI loading a value into the physical register Reg .


<s> bool X86TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; unsigned NumBits1 = VT1 . getSizeInBits ( ) ; unsigned NumBits2 = VT2 . getSizeInBits ( ) ; return NumBits1 > NumBits2 ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s> int AArch64AsmParser :: tryParseRegister ( ) { MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return - 1 ; std :: string lowerCase = Tok . getString ( ) . lower ( ) ; unsigned RegNum = matchRegisterNameAlias ( lowerCase , RegKind :: Scalar ) ; if ( RegNum == 0 ) RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( "fp" , AArch64 :: FP ) . Case ( "lr" , AArch64 :: LR ) . Case ( "x31" , AArch64 :: XZR ) . Case ( "w31" , AArch64 :: WZR ) . Default ( 0 ) ; if ( RegNum == 0 ) return - 1 ; Parser . Lex ( ) ; return RegNum ; } </s>

tryParseRegister - parse one register if possible


<s> std :: string getName ( ) const override { return Name ; } </s>

Return a string with the name of the plan and the applicable VFs and UFs .


<s> static void frv_option_override ( void ) { int regno ; unsigned int i ; target_flags |= ( frv_default_flags_for_cpu ( ) & ~ target_flags_explicit ) ; if ( TARGET_LIBPIC ) { if ( ! flag_pic ) flag_pic = 2 ; if ( ! OPTION_SET_P ( g_switch_value ) ) { g_switch_value = 0 ; } } for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { enum reg_class rclass ; if ( GPR_P ( regno ) ) { int gpr_reg = regno - GPR_FIRST ; if ( gpr_reg == GR8_REG ) rclass = GR8_REGS ; else if ( gpr_reg == GR9_REG ) rclass = GR9_REGS ; else if ( gpr_reg == GR14_REG ) rclass = FDPIC_FPTR_REGS ; else if ( gpr_reg == FDPIC_REGNO ) rclass = FDPIC_REGS ; else if ( ( gpr_reg & 3 ) == 0 ) rclass = QUAD_REGS ; else if ( ( gpr_reg & 1 ) == 0 ) rclass = EVEN_REGS ; else rclass = GPR_REGS ; } else if ( FPR_P ( regno ) ) { int fpr_reg = regno - GPR_FIRST ; if ( ( fpr_reg & 3 ) == 0 ) rclass = QUAD_FPR_REGS ; else if ( ( fpr_reg & 1 ) == 0 ) rclass = FEVEN_REGS ; else rclass = FPR_REGS ; } else if ( regno == LR_REGNO ) rclass = LR_REG ; else if ( regno == LCR_REGNO ) rclass = LCR_REG ; else if ( ICC_P ( regno ) ) rclass = ICC_REGS ; else if ( FCC_P ( regno ) ) rclass = FCC_REGS ; else if ( ICR_P ( regno ) ) rclass = ICR_REGS ; else if ( FCR_P ( regno ) ) rclass = FCR_REGS ; else if ( ACC_P ( regno ) ) { int r = regno - ACC_FIRST ; if ( ( r & 3 ) == 0 ) rclass = QUAD_ACC_REGS ; else if ( ( r & 1 ) == 0 ) rclass = EVEN_ACC_REGS ; else rclass = ACC_REGS ; } else if ( ACCG_P ( regno ) ) rclass = ACCG_REGS ; else rclass = NO_REGS ; regno_reg_class [ regno ] = rclass ; } if ( ! OPTION_SET_P ( g_switch_value ) && ! TARGET_LIBPIC ) g_switch_value = SDATA_DEFAULT_SIZE ; if ( flag_pic || TARGET_FDPIC ) targetm . asm_out . unaligned_op . si = 0 ; if ( ( target_flags_explicit & MASK_LINKED_FP ) == 0 ) target_flags |= MASK_LINKED_FP ; if ( ( target_flags_explicit & MASK_OPTIMIZE_MEMBAR ) == 0 ) target_flags |= MASK_OPTIMIZE_MEMBAR ; for ( i = 0 ; i < ARRAY_SIZE ( frv_unit_names ) ; i ++ ) frv_unit_codes [ i ] = get_cpu_unit_code ( frv_unit_names [ i ] ) ; for ( i = 0 ; i < ARRAY_SIZE ( frv_type_to_unit ) ; i ++ ) frv_type_to_unit [ i ] = ARRAY_SIZE ( frv_unit_codes ) ; init_machine_status = frv_init_machine_status ; } </s>


<s>
void
HexagonInstPrinter
::
printInst
(
const
MCInst
*
MI
,
uint64_t
Address
,
StringRef
Annot
,
const
MCSubtargetInfo
&
STI
,
raw_ostream
&
OS
)
{
assert
(
HexagonMCInstrInfo
::
isBundle
(
*
MI
)
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
<=
HEXAGON_PACKET_SIZE
)
;
assert
(
HexagonMCInstrInfo
::
bundleSize
(
*
MI
)
>
0
)
;
HasExtender
=
false
;
for
(
auto
const
&
I
:
HexagonMCInstrInfo
::
bundleInstructions
(
*
MI
)
)
{
MCInst
const
&
MCI
=
*
I
.
getInst
(
)
;
if
(
HexagonMCInstrInfo
::
isDuplex
(
MII
,
MCI
)
)
{
printInstruction
(
MCI
.
getOperand
(
1
)
.
getInst
(
)
,
Address
,
OS
)
;
OS
<<
'\v'
;
HasExtender
=
false
;
printInstruction
(
MCI
.
getOperand
(
0
)
.
getInst
(
)
,
Address
,
OS
)
;
}
else
printInstruction
(
&
MCI
,
Address
,
OS
)
;
HasExtender
=
HexagonMCInstrInfo
::
isImmext
(
MCI
)
;
OS
<<
"\n"
;
}
bool
IsLoop0
=
HexagonMCInstrInfo
::
isInnerLoop
(
*
MI
)
;
bool
IsLoop1
=
HexagonMCInstrInfo
::
isOuterLoop
(
*
MI
)
;
if
(
IsLoop0
)
{
OS
<<
(
IsLoop1
" :endloop01"
:
" :endloop0"
)
;
}
else
if
(
IsLoop1
)
{
OS
<<
" :endloop1"
;
}
}
</s>

Print the specified MCInst to the specified raw_ostream .

Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
0
Hexagon
Hexagon
1
0
Hexagon
"\n"
Hexagon
Hexagon
" :endloop01"
" :endloop0"
" :endloop1"


<s> bool ARMTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case MVT :: i8 : case MVT :: i16 : case MVT :: i32 : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case MVT :: f64 : case MVT :: v2f64 : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false ; } } } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook .


<s> bool SystemZFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void addPostRegAlloc ( ) override { if ( PatmosSinglePathInfo :: isEnabled ( ) ) { addPass ( createPatmosSPMarkPass ( getPatmosTargetMachine ( ) ) ) ; addPass ( createPatmosSinglePathInfoPass ( getPatmosTargetMachine ( ) ) ) ; addPass ( createPatmosSPPreparePass ( getPatmosTargetMachine ( ) ) ) ; } } </s>

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .

Patmos Patmos Patmos Patmos Patmos Patmos Patmos Patmos


<s> void TeakDAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode ( ) ) { case ISD :: LOAD : if ( SelectLoad ( N ) ) return ; break ; } SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> SDValue X86TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: VECTOR_SHUFFLE : return PerformShuffleCombine ( N , DAG , * this ) ; case ISD :: SELECT : return PerformSELECTCombine ( N , DAG , Subtarget ) ; case X86ISD :: CMOV : return PerformCMOVCombine ( N , DAG , DCI ) ; case ISD :: MUL : return PerformMulCombine ( N , DAG , DCI ) ; case ISD :: SHL : case ISD :: SRA : case ISD :: SRL : return PerformShiftCombine ( N , DAG , Subtarget ) ; case ISD :: STORE : return PerformSTORECombine ( N , DAG , Subtarget ) ; case X86ISD :: FXOR : case X86ISD :: FOR : return PerformFORCombine ( N , DAG ) ; case X86ISD :: FAND : return PerformFANDCombine ( N , DAG ) ; case X86ISD :: BT : return PerformBTCombine ( N , DAG , DCI ) ; case X86ISD :: VZEXT_MOVL : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case ISD :: MEMBARRIER : return PerformMEMBARRIERCombine ( N , DAG ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void MBlazeRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MBlazeFunctionInfo * MBlazeFI = MF . getInfo < MBlazeFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; adjustMBlazeStackFrame ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; if ( StackSize == 0 && ! MFI -> adjustsStack ( ) ) return ; if ( StackSize < 28 && MFI -> adjustsStack ( ) ) StackSize = 28 ; int FPOffset = MBlazeFI -> getFPStackOffset ( ) ; int RAOffset = MBlazeFI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: ADDI ) , MBlaze :: R1 ) . addReg ( MBlaze :: R1 ) . addImm ( - StackSize ) ; if ( MFI -> adjustsStack ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: SWI ) ) . addReg ( MBlaze :: R15 ) . addImm ( RAOffset ) . addReg ( MBlaze :: R1 ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: SWI ) ) . addReg ( MBlaze :: R19 ) . addImm ( FPOffset ) . addReg ( MBlaze :: R1 ) ; BuildMI ( MBB , MBBI , DL , TII . get ( MBlaze :: ADD ) , MBlaze :: R19 ) . addReg ( MBlaze :: R1 ) . addReg ( MBlaze :: R0 ) ; } } </s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> static void rs6000_function_specific_restore ( struct gcc_options * opts , struct cl_target_option * ptr ) { opts -> x_rs6000_isa_flags = ptr -> x_rs6000_isa_flags ; opts -> x_rs6000_isa_flags_explicit = ptr -> x_rs6000_isa_flags_explicit ; ( void ) rs6000_option_override_internal ( false ) ; } </s>


<s> SDValue HexagonTargetLowering :: LowerCallResult ( SDValue Chain , SDValue Glue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_Hexagon ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == MVT :: i1 ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , MVT :: i32 , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & Hexagon :: PredRegsRegClass ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( 1 ) , dl , PredR , FR0 . getValue ( 0 ) , FR0 . getValue ( 2 ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( 0 ) , dl , PredR , MVT :: i1 ) ; Glue = TPR . getValue ( 1 ) ; Chain = TPR . getValue ( 0 ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Glue ) ; Glue = RetVal . getValue ( 2 ) ; Chain = RetVal . getValue ( 1 ) ; } InVals . push_back ( RetVal . getValue ( 0 ) ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void RISCVELFTargetObjectFile :: getModuleMetadata ( Module & M ) { SmallVector < Module :: ModuleFlagEntry , 8 > ModuleFlags ; M . getModuleFlagsMetadata ( ModuleFlags ) ; for ( const auto & MFE : ModuleFlags ) { StringRef Key = MFE . Key -> getString ( ) ; if ( Key == "SmallDataLimit" ) { SSThreshold = mdconst :: extract < ConstantInt > ( MFE . Val ) -> getZExtValue ( ) ; break ; } } } </s>

Get the module-level metadata that the platform cares about .


<s> void X86AsmPrinter :: emitEndOfAsmFile ( Module & M ) { const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) { emitNonLazyStubs ( MMI , * OutStreamer ) ; emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; OutStreamer -> emitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } else if ( TT . isOSBinFormatCOFF ( ) ) { if ( MMI -> usesMSVCFloatingPoint ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86 ) ? "__fltused" : "_fltused" ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> emitSymbolAttribute ( S , MCSA_Global ) ; return ; } emitStackMaps ( SM ) ; } else if ( TT . isOSBinFormatELF ( ) ) { emitStackMaps ( SM ) ; FM . serializeToFaultMapSection ( ) ; } } </s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> bool sh_split_movrt_negc_to_movt_xor ( rtx_insn * curr_insn , rtx operands [ ] ) { if ( ! can_create_pseudo_p ( ) ) return false ; set_of_reg t_before_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , prev_nonnote_insn_bb ) ; set_of_reg t_after_negc = sh_find_set_of_reg ( get_t_reg_rtx ( ) , curr_insn , next_nonnote_insn_bb ) ; if ( t_before_negc . set_rtx != NULL_RTX && t_after_negc . set_rtx != NULL_RTX && rtx_equal_p ( t_before_negc . set_rtx , t_after_negc . set_rtx ) && ! reg_used_between_p ( get_t_reg_rtx ( ) , curr_insn , t_after_negc . insn ) && ! sh_insn_operands_modified_between_p ( t_before_negc . insn , t_before_negc . insn , t_after_negc . insn ) && ! sh_unspec_insn_p ( t_after_negc . insn ) && ! volatile_insn_p ( PATTERN ( t_after_negc . insn ) ) && ! side_effects_p ( PATTERN ( t_after_negc . insn ) ) && ! may_trap_or_fault_p ( PATTERN ( t_after_negc . insn ) ) ) { emit_insn ( gen_movrt_xor ( operands [ 0 ] , get_t_reg_rtx ( ) ) ) ; set_insn_deleted ( t_after_negc . insn ) ; return true ; } else return false ; } </s>

Given the current insn , which is assumed to be a movrt_negc insn , try to figure out whether it should be converted into a movt-xor sequence in the movrt_negc splitter . Returns true if insns have been modified and the splitter has succeeded .


<s>
static
const
char
*
avr_out_movhi_r_mr_pre_dec_tiny
(
rtx_insn
*
insn
,
rtx
op
[
]
,
int
*
plen
)
{
int
mem_volatile_p
=
0
;
rtx
dest
=
op
[
0
]
;
rtx
src
=
op
[
1
]
;
rtx
base
=
XEXP
(
src
,
0
)
;
mem_volatile_p
=
MEM_VOLATILE_P
(
src
)
;
if
(
reg_overlap_mentioned_p
(
dest
,
XEXP
(
base
,
0
)
)
)
fatal_insn
(
"incorrect insn:"
,
insn
)
;
if
(
!
mem_volatile_p
)
return
avr_asm_len
(
"ld %B0,%1"
CR_TAB
"ld %A0,%1"
,
op
,
plen
,
2
)
;
return
avr_asm_len
(
TINY_SBIW
(
%
I1
,
%
J1
,
2
)
CR_TAB
"ld %A0,%p1+"
CR_TAB
"ld %B0,%p1"
CR_TAB
TINY_SBIW
(
%
I1
,
%
J1
,
1
)
,
op
,
plen
,
6
)
;
}
</s>

Same as movhi_r_mr , but TINY does not have ADIW , SBIW and LDD


<s> void HexagonDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - 1 ) ; return ; } switch ( N -> getOpcode ( ) ) { case ISD :: Constant : SelectConstant ( N ) ; return ; case ISD :: ConstantFP : SelectConstantFP ( N ) ; return ; case ISD :: FrameIndex : SelectFrameIndex ( N ) ; return ; case ISD :: BITCAST : SelectBitcast ( N ) ; return ; case ISD :: SHL : SelectSHL ( N ) ; return ; case ISD :: LOAD : SelectLoad ( N ) ; return ; case ISD :: STORE : SelectStore ( N ) ; return ; case ISD :: MUL : SelectMul ( N ) ; return ; case ISD :: ZERO_EXTEND : SelectZeroExtend ( N ) ; return ; case ISD :: INTRINSIC_W_CHAIN : SelectIntrinsicWChain ( N ) ; return ; case ISD :: INTRINSIC_WO_CHAIN : SelectIntrinsicWOChain ( N ) ; return ; } SelectCode ( N ) ; } </s>

Hexagon Hexagon 1 ISD::Constant ISD::ConstantFP ISD::FrameIndex ISD::BITCAST ISD::SHL ISD::LOAD ISD::STORE ISD::MUL ISD::ZERO_EXTEND ISD::INTRINSIC_W_CHAIN ISD::INTRINSIC_WO_CHAIN


<s>
static
void
create_complex_muldiv
(
const
char
*
name
,
built_in_function
fncode
,
tree
fntype
)
{
tree
fndecl
=
add_builtin_function
(
name
,
fntype
,
fncode
,
BUILT_IN_NORMAL
,
name
,
NULL_TREE
)
;
set_builtin_decl
(
fncode
,
fndecl
,
true
)
;
if
(
TARGET_DEBUG_BUILTIN
)
fprintf
(
stderr
,
"create complex %s, fncode: %d\n"
,
name
,
(
int
)
fncode
)
;
return
;
}
</s>

Create a decl for either complex long double multiply or complex long double divide when long double is IEEE 128-bit floating point . We ca n't use __multc3 and __divtc3 because the original long double using IBM extended double used those names . The complex multiply/divide functions are encoded as builtin functions with a complex result and 4 scalar inputs .


<s> FastISel * ARM :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) { const TargetMachine & TM = funcInfo . MF -> getTarget ( ) ; const ARMSubtarget * Subtarget = & TM . getSubtarget < ARMSubtarget > ( ) ; bool UseFastISel = false ; UseFastISel |= Subtarget -> isTargetMachO ( ) && ! Subtarget -> isThumb1Only ( ) ; UseFastISel |= Subtarget -> isTargetLinux ( ) && ! Subtarget -> isThumb ( ) ; UseFastISel |= Subtarget -> isTargetNaCl ( ) && ! Subtarget -> isThumb ( ) ; if ( UseFastISel ) { TM . Options . NoFramePointerElim = true ; return new ARMFastISel ( funcInfo , libInfo ) ; } return 0 ; } </s>

This method returns a target specific FastISel object , or null if the target does not support `` fast '' ISel .


<s> bool isMem ( ) const { return Kind == k_Memory ; } </s>