<s> static bool isF128SoftLibCall ( const char * CallSym ) { const char * const LibCalls [ ] = { "__addtf3" , "__divtf3" , "__eqtf2" , "__extenddftf2" , "__extendsftf2" , "__fixtfdi" , "__fixtfsi" , "__fixtfti" , "__fixunstfdi" , "__fixunstfsi" , "__fixunstfti" , "__floatditf" , "__floatsitf" , "__floattitf" , "__floatunditf" , "__floatunsitf" , "__floatuntitf" , "__getf2" , "__gttf2" , "__letf2" , "__lttf2" , "__multf3" , "__netf2" , "__powitf2" , "__subtf3" , "__trunctfdf2" , "__trunctfsf2" , "__unordtf2" , "ceill" , "copysignl" , "cosl" , "exp2l" , "expl" , "floorl" , "fmal" , "fmaxl" , "fmodl" , "log10l" , "log2l" , "logl" , "nearbyintl" , "powl" , "rintl" , "roundl" , "sinl" , "sqrtl" , "truncl" } ; auto Comp = [ ] ( const char * S1 , const char * S2 ) { return strcmp ( S1 , S2 ) < 0 ; } ; assert ( std :: is_sorted ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , Comp ) ) ; return std :: binary_search ( std :: begin ( LibCalls ) , std :: end ( LibCalls ) , CallSym , Comp ) ; } </s>

This function returns true if CallSym is a long double emulation routine .


<s>
InstructionCost
RISCVTTIImpl
::
getArithmeticReductionCost
(
unsigned
Opcode
,
VectorType
*
VTy
,
Optional
<
FastMathFlags
>
FMF
,
TTI
::
TargetCostKind
CostKind
)
{
if
(
!
isa
<
FixedVectorType
>
(
VTy
)
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
VTy
,
FMF
,
CostKind
)
;
if
(
VTy
->
getElementType
(
)
->
isIntegerTy
(
1
)
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
VTy
,
FMF
,
CostKind
)
;
if
(
!
ST
->
useRVVForFixedLengthVectors
(
)
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
VTy
,
FMF
,
CostKind
)
;
if
(
VTy
->
getScalarSizeInBits
(
)
>
ST
->
getMaxELENForFixedLengthVectors
(
)
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
VTy
,
FMF
,
CostKind
)
;
int
ISD
=
TLI
->
InstructionOpcodeToISD
(
Opcode
)
;
assert
(
ISD
&&
"Invalid opcode"
)
;
if
(
ISD
!=
ISD
::
ADD
&&
ISD
!=
ISD
::
OR
&&
ISD
!=
ISD
::
XOR
&&
ISD
!=
ISD
::
AND
&&
ISD
!=
ISD
::
FADD
)
return
BaseT
::
getArithmeticReductionCost
(
Opcode
,
VTy
,
FMF
,
CostKind
)
;
InstructionCost
BaseCost
=
2
;
unsigned
VL
=
cast
<
FixedVectorType
>
(
VTy
)
->
getNumElements
(
)
;
std
::
pair
<
InstructionCost
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
VTy
)
;
if
(
TTI
::
requiresOrderedReduction
(
FMF
)
)
return
(
LT
.
first
1
)
+
BaseCost
+
VL
;
return
(
LT
.
first
1
)
+
BaseCost
+
Log2_32_Ceil
(
VL
)
;
}
</s>

Calculate the cost of vector reduction intrinsics .

RISCV
RISCV
1
"Invalid opcode"
ISD::ADD
ISD::OR
ISD::XOR
ISD::AND
ISD::FADD
2
1
1


<s> const HSAILIntrinsicInfo * getIntrinsicInfo ( ) const override { return & IntrinsicInfo ; } </s>

If intrinsic information is available , return it . If not , return null .


This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly WebAssembly


<s> SDValue AArch64TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , std :: vector < SDNode * > * Created ) const { AttributeSet Attr = DAG . getMachineFunction ( ) . getFunction ( ) -> getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( 0 ) , Attr ) ) return SDValue ( N , 0 ) ; EVT VT = N -> getValueType ( 0 ) ; if ( ( VT != MVT :: i32 && VT != MVT :: i64 ) || ! ( Divisor . isPowerOf2 ( ) || ( - Divisor ) . isPowerOf2 ( ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( 0 ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; SDValue Pow2MinusOne = DAG . getConstant ( ( 1ULL << Lg2 ) - 1 , DL , VT ) ; SDValue CCVal ; SDValue Cmp = getAArch64Cmp ( N0 , Zero , ISD :: SETLT , CCVal , DAG , DL ) ; SDValue Add = DAG . getNode ( ISD :: ADD , DL , VT , N0 , Pow2MinusOne ) ; SDValue CSel = DAG . getNode ( AArch64ISD :: CSEL , DL , VT , Add , N0 , CCVal , Cmp ) ; if ( Created ) { Created -> push_back ( Cmp . getNode ( ) ) ; Created -> push_back ( Add . getNode ( ) ) ; Created -> push_back ( CSel . getNode ( ) ) ; } SDValue SRA = DAG . getNode ( ISD :: SRA , DL , VT , CSel , DAG . getConstant ( Lg2 , DL , MVT :: i64 ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; if ( Created ) Created -> push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( ISD :: SUB , DL , VT , DAG . getConstant ( 0 , DL , VT ) , SRA ) ; } </s>

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators .


<s> inline bool function_base :: can_be_overloaded_p ( enum predication_type_index ) const { return true ; } </s>

Since most of intrinsics can be overloaded , we set it true by default .


<s> unsigned int h8300_unary_length ( rtx op ) { enum h8300_operand_class opclass ; unsigned int size , operand_length ; size = GET_MODE_SIZE ( GET_MODE ( op ) ) ; operand_length = h8300_classify_operand ( op , size , & opclass ) ; switch ( opclass ) { case H8OP_REGISTER : return 2 ; case H8OP_MEM_BASE : return ( size == 4 ? 6 : 4 ) ; case H8OP_MEM_ABSOLUTE : return operand_length + ( size == 4 ? 6 : 4 ) ; case H8OP_MEM_COMPLEX : return operand_length + 6 ; default : gcc_unreachable ( ) ; } } </s>

Return the length of a unary instruction such as neg or not given that its operand is OP .


<s> const MCPhysReg * Nios2RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return nullptr ; } </s>


<s> void emitFunctionBodyStart ( ) override { } </s>

Targets can override this to emit stuff before the first basic block in the function .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { assert ( 0 ) ; } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> unsigned MipsAsmParser :: getReg ( int RC , int RegNo ) { return * ( getContext ( ) . getRegisterInfo ( ) . getRegClass ( RC ) . begin ( ) + RegNo ) ; } </s>

Returns the register associated with this edge .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool ARCRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { return MF . needsFrameMoves ( ) ; } </s>


<s> void X86InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; unsigned Alignment = std :: max < uint32_t > ( RC -> getSize ( ) , 16 ) ; bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> unsigned AMDGPUInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> int mt_function_arg_boundary ( enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED ) { return BITS_PER_WORD ; } </s>


<s> void Initialize ( const MachineFunction & MF , bool isPIC ) { const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; ConstPoolId2AddrMap . resize ( AFI -> getNumConstPoolEntries ( ) ) ; JumpTableId2AddrMap . resize ( AFI -> getNumJumpTables ( ) ) ; IsPIC = isPIC ; } </s>

This method must be called before any actual lowering is done .


<s> PPCSubtarget :: PPCSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : PPCGenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( 16 ) , DarwinDirective ( PPC :: DIR_NONE ) , HasMFOCRF ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , IsPPC64 ( is64Bit ) , HasAltivec ( false ) , HasQPX ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasISEL ( false ) , IsBookE ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == "generic" ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( is64Bit ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = "+64bit," + FullFS ; else FullFS = "+64bit" ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( use64BitRegs ( ) && ! has64BitSupport ( ) ) Use64BitRegs = false ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( hasQPX ( ) || isBGQ ( ) ) StackAlignment = 32 ; } </s>

This constructor initializes the data members to match that of the specified triple .


<s> bool ARMTargetLowering :: shouldConvertFpToSat ( unsigned Op , EVT FPVT , EVT VT ) const { if ( ! isOperationLegalOrCustom ( Op , VT ) || ! FPVT . isSimple ( ) ) return false ; switch ( FPVT . getSimpleVT ( ) . SimpleTy ) { case MVT :: f16 : return Subtarget -> hasVFP2Base ( ) ; case MVT :: f32 : return Subtarget -> hasVFP2Base ( ) ; case MVT :: f64 : return Subtarget -> hasFP64 ( ) ; case MVT :: v4f32 : case MVT :: v8f16 : return Subtarget -> hasMVEFloatOps ( ) ; default : return false ; } } </s>

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min ( max ( fptoi ) ) saturation patterns .


<s> void SHUXIInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( SHUXI :: POP ) ) . addReg ( DestReg , getDefRegState ( true ) ) ; } </s>


<s> static reg_class_t aarch64_ira_change_pseudo_allocno_class ( int regno , reg_class_t allocno_class , reg_class_t best_class ) { machine_mode mode ; if ( ! reg_class_subset_p ( GENERAL_REGS , allocno_class ) || ! reg_class_subset_p ( FP_REGS , allocno_class ) ) return allocno_class ; if ( ! reg_class_subset_p ( GENERAL_REGS , best_class ) || ! reg_class_subset_p ( FP_REGS , best_class ) ) return best_class ; mode = PSEUDO_REGNO_MODE ( regno ) ; return FLOAT_MODE_P ( mode ) || VECTOR_MODE_P ( mode ) ? FP_REGS : GENERAL_REGS ; } </s>

Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS . The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS have the same cost even if ALL_REGS has a much larger cost . ALL_REGS is also used if the cost of both FP_REGS and GENERAL_REGS is lower than the memory cost ( in this case the best class is the lowest cost one ) . Using ALL_REGS irrespectively of its cost results in bad allocations with many redundant int < - > FP moves which are expensive on various cores . To avoid this we do n't allow ALL_REGS as the allocno class , but force a decision between FP_REGS and GENERAL_REGS . We use the allocno class if it is n't ALL_REGS . Similarly , use the best class if it is n't ALL_REGS . Otherwise set the allocno class depending on the mode . The result of this is that it is no longer inefficient to have a higher memory move cost than the register move cost .


<s> void SITargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { switch ( N -> getOpcode ( ) ) { case ISD :: INSERT_VECTOR_ELT : { if ( SDValue Res = lowerINSERT_VECTOR_ELT ( SDValue ( N , 0 ) , DAG ) ) Results . push_back ( Res ) ; return ; } case ISD :: EXTRACT_VECTOR_ELT : { if ( SDValue Res = lowerEXTRACT_VECTOR_ELT ( SDValue ( N , 0 ) , DAG ) ) Results . push_back ( Res ) ; return ; } case ISD :: INTRINSIC_WO_CHAIN : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) -> getZExtValue ( ) ; switch ( IID ) { case Intrinsic :: amdgcn_cvt_pkrtz : { SDValue Src0 = N -> getOperand ( 1 ) ; SDValue Src1 = N -> getOperand ( 2 ) ; SDLoc SL ( N ) ; SDValue Cvt = DAG . getNode ( AMDGPUISD :: CVT_PKRTZ_F16_F32 , SL , MVT :: i32 , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( ISD :: BITCAST , SL , MVT :: v2f16 , Cvt ) ) ; return ; } default : break ; } } default : break ; } } </s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> bool PPCTargetLowering :: getPreIndexedAddressParts ( SDNode * N , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { if ( DisablePPCPreinc ) return false ; SDValue Ptr ; EVT VT ; unsigned Alignment ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { Ptr = LD -> getBasePtr ( ) ; VT = LD -> getMemoryVT ( ) ; Alignment = LD -> getAlignment ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { Ptr = ST -> getBasePtr ( ) ; VT = ST -> getMemoryVT ( ) ; Alignment = ST -> getAlignment ( ) ; } else return false ; if ( VT . isVector ( ) ) return false ; if ( SelectAddressRegReg ( Ptr , Offset , Base , DAG ) ) { AM = ISD :: PRE_INC ; return true ; } if ( VT != MVT :: i64 ) { if ( ! SelectAddressRegImm ( Ptr , Offset , Base , DAG ) ) return false ; } else { if ( Alignment < 4 ) return false ; if ( ! SelectAddressRegImmShift ( Ptr , Offset , Base , DAG ) ) return false ; } if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { if ( LD -> getValueType ( 0 ) == MVT :: i64 && LD -> getMemoryVT ( ) == MVT :: i32 && LD -> getExtensionType ( ) == ISD :: SEXTLOAD && isa < ConstantSDNode > ( Offset ) ) return false ; } AM = ISD :: PRE_INC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if the node 's address can be legally represented as pre-indexed load / store address .


<s> SDValue SparcTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { if ( Subtarget -> is64Bit ( ) ) return LowerReturn_64 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; return LowerReturn_32 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; } </s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> ISD :: NodeType getExtendForAtomicOps ( ) const override { return ISD :: SIGN_EXTEND ; } </s>

Returns how the platform 's atomic operations are extended ( ZERO_EXTEND , SIGN_EXTEND , or ANY_EXTEND ) .


<s> bool sparc_can_use_return_insn_p ( void ) { return sparc_prologue_data_valid_p && ( actual_fsize == 0 || ! sparc_leaf_function_p ) ; } </s>

Return true if it is appropriate to emit ` return ' instructions in the body of a function .


<s> bool MandarinPassConfig :: addInstSelector ( ) { addPass ( createMandarinISelDag ( getMandarinTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool SparcAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printMemOperand ( MI , OpNo , O ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool RISCVPulpHWLoops :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! MF . getSubtarget < RISCVSubtarget > ( ) . hasNonStdExtPulp ( ) ) { return false ; } TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; FindInstrPairs ( MDT -> getRootNode ( ) , nullptr , nullptr ) ; assert ( Setups . size ( ) == Branches . size ( ) && Setups . size ( ) == LoopNums . size ( ) ) ; if ( Setups . empty ( ) ) return false ; while ( ! Setups . empty ( ) ) { ProcessHardwareLoop ( Setups . pop_back_val ( ) , Branches . pop_back_val ( ) , LoopNums . pop_back_val ( ) , MF ) ; } return true ; } </s>

runOnMachineFunction - Emit the function body .


<s>
bool
ARMPassConfig
::
addPreSched2
(
)
{
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
{
addPass
(
createARMLoadStoreOptimizationPass
(
)
)
;
printAndVerify
(
"After ARM load / store optimizer"
)
;
}
if
(
getARMSubtarget
(
)
.
hasNEON
(
)
)
addPass
(
createExecutionDependencyFixPass
(
&
ARM
::
DPRRegClass
)
)
;
}
addPass
(
createARMExpandPseudoPass
(
)
)
;
if
(
getOptLevel
(
)
!=
CodeGenOpt
::
)
{
if
(
!
getARMSubtarget
(
)
.
isThumb1Only
(
)
)
addPass
(
&
IfConverterID
)
;
}
if
(
getARMSubtarget
(
)
.
isThumb2
(
)
)
addPass
(
createThumb2ITBlockPass
(
)
)
;
return
true
;
}
</s>

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass .

ARM
ARM
ARM
ARM
"After ARM load / store optimizer"
ARM
ARM::DPRRegClass
ARM
ARM
ARM


<s> void changingInstr ( MachineInstr & MI ) override { } </s>

This instruction is about to be mutated in some way .


<s> SDNode * NVPTXDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return NULL ; SDNode * ResNode = NULL ; switch ( N -> getOpcode ( ) ) { case ISD :: LOAD : ResNode = SelectLoad ( N ) ; break ; case ISD :: STORE : ResNode = SelectStore ( N ) ; break ; case NVPTXISD :: LoadV2 : case NVPTXISD :: LoadV4 : ResNode = SelectLoadVector ( N ) ; break ; case NVPTXISD :: LDGV2 : case NVPTXISD :: LDGV4 : case NVPTXISD :: LDUV2 : case NVPTXISD :: LDUV4 : ResNode = SelectLDGLDUVector ( N ) ; break ; case NVPTXISD :: StoreV2 : case NVPTXISD :: StoreV4 : ResNode = SelectStoreVector ( N ) ; break ; default : break ; } if ( ResNode ) return ResNode ; return SelectCode ( N ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; return printAsmRegInClass ( MO , & AArch64 :: FPR128RegClass , true , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion .


"Instruction should be in a basic block!"

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> static bool classof ( const ARMMCExpr * ) { return true ; } </s>


<s> CCAssignFn * XtensaTargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC ) const { return RetCC_Xtensa ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addPreserved < MachinePostDominatorTree > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> std :: pair < uint16_t , uint16_t > X86InstrInfo :: getExecutionDomain ( const MachineInstr & MI ) const { uint16_t domain = ( MI . getDesc ( ) . TSFlags >> X86II :: SSEDomainShift ) & 3 ; unsigned opcode = MI . getOpcode ( ) ; uint16_t validDomains = 0 ; if ( domain ) { validDomains = getExecutionDomainCustom ( MI ) ; if ( validDomains ) return std :: make_pair ( domain , validDomains ) ; if ( lookup ( opcode , domain , ReplaceableInstrs ) ) { validDomains = 0xe ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2 ) ) { validDomains = Subtarget . hasAVX2 ( ) ? 0xe : 0x6 ; } else if ( lookup ( opcode , domain , ReplaceableInstrsAVX2InsertExtract ) ) { if ( ! Subtarget . hasAVX2 ( ) ) return std :: make_pair ( 0 , 0 ) ; validDomains = 0xe ; } else if ( lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512 ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) && lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQ ) ) { validDomains = 0xe ; } else if ( Subtarget . hasDQI ( ) ) { if ( const uint16_t * table = lookupAVX512 ( opcode , domain , ReplaceableInstrsAVX512DQMasked ) ) { if ( domain == 1 || ( domain == 3 && table [ 3 ] == opcode ) ) validDomains = 0xa ; else validDomains = 0xc ; } } } return std :: make_pair ( domain , validDomains ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s> static bool tilegx_return_in_msb ( const_tree valtype ) { return ( TARGET_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) ) ; } </s>

Implement TARGET_RETURN_IN_MSB . We return a value in the most significant part of a register if : - the target is big-endian ; and - the value has an aggregate type ( e.g. , structure or union ) .


"Can't store this register to stack slot"

Store the specified register of the given register class to the specified stack frame index .


<s> InstructionCost AArch64TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( ! isa < ScalableVectorType > ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( 1 ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , 0 , CostKind , I ) ; return LT . first * MemOpCost * getMaxNumElements ( LegalVF , I -> getFunction ( ) ) ; } </s>

Calculate the cost of Gather / Scatter operation .


<s> enum direction function_arg_padding ( enum machine_mode mode , tree type ) { if ( TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P ( type ) ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ; } </s>

Handle the FUNCTION_ARG_PADDING macro . For the 64 bit ABI structs are always stored left shifted in their argument slot .


<s> void arc_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx label1 , label2 , x , cond ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ 5 ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ 6 ] ) ; mode = GET_MODE ( mem ) ; gcc_assert ( mode == SImode ) ; arc_pre_atomic_barrier ( mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; emit_insn ( gen_arc_load_exclusivesi ( rval , mem ) ) ; mode = SELECT_CC_MODE ( NE , rval , oldval ) ; cond = gen_rtx_REG ( mode , CC_REG ) ; emit_insn ( gen_rtx_SET ( cond , gen_rtx_COMPARE ( mode , rval , oldval ) ) ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; emit_insn ( gen_arc_store_exclusivesi ( mem , newval ) ) ; if ( ! is_weak ) { cond = gen_rtx_REG ( CC_Zmode , CC_REG ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } if ( mod_f != MEMMODEL_RELAXED ) emit_label ( label2 ) ; arc_post_atomic_barrier ( mod_s ) ; if ( mod_f == MEMMODEL_RELAXED ) emit_label ( label2 ) ; } </s>

Helper function used by the `` atomic_compare_and_swapsi_1 '' pattern .


<s> const PPCMCExpr * PPCMCExpr :: Create ( VariantKind Kind , const MCExpr * Expr , MCContext & Ctx ) { return new ( Ctx ) PPCMCExpr ( Kind , Expr ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> void GCNPassConfig :: addMachineSSAOptimization ( ) { TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( & SIFoldOperandsID ) ; if ( EnableDPPCombine ) addPass ( & GCNDPPCombineID ) ; addPass ( & SILoadStoreOptimizerID ) ; if ( isPassEnabled ( EnableSDWAPeephole ) ) { addPass ( & SIPeepholeSDWAID ) ; addPass ( & EarlyMachineLICMID ) ; addPass ( & MachineCSEID ) ; addPass ( & SIFoldOperandsID ) ; } addPass ( & DeadMachineInstructionElimID ) ; addPass ( createSIShrinkInstructionsPass ( ) ) ; } </s>

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes .


<s> bool M88kAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode ) return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; M88kMCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ; M88kInstPrinter :: printOperand ( MO , MAI , OS ) ; return false ; } </s>


"unexpected return calling convention register assignment"

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> bool HexagonGenInsert :: removeDeadCode ( MachineDomTreeNode * N ) { bool Changed = false ; typedef GraphTraits < MachineDomTreeNode * > GTN ; for ( auto I = GTN :: child_begin ( N ) , E = GTN :: child_end ( N ) ; I != E ; ++ I ) Changed |= removeDeadCode ( * I ) ; MachineBasicBlock * B = N -> getBlock ( ) ; std :: vector < MachineInstr * > Instrs ; for ( auto I = B -> rbegin ( ) , E = B -> rend ( ) ; I != E ; ++ I ) Instrs . push_back ( & * I ) ; for ( auto I = Instrs . begin ( ) , E = Instrs . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) || ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , 2 > Regs ; for ( ConstMIOperands Op ( MI ) ; Op . isValid ( ) ; ++ Op ) { if ( ! Op -> isReg ( ) || ! Op -> isDef ( ) ) continue ; unsigned R = Op -> getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) || ! MRI -> use_nodbg_empty ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ; for ( unsigned I = 0 , N = Regs . size ( ) ; I != N ; ++ I ) MRI -> markUsesInDebugValueAsUndef ( Regs [ I ] ) ; Changed = true ; } return Changed ; } </s>

Remove all dead instructions between the I and E .


<s> bool HexagonTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { switch ( Intrinsic ) { case Intrinsic :: hexagon_L2_loadrd_pbr : case Intrinsic :: hexagon_L2_loadri_pbr : case Intrinsic :: hexagon_L2_loadrh_pbr : case Intrinsic :: hexagon_L2_loadruh_pbr : case Intrinsic :: hexagon_L2_loadrb_pbr : case Intrinsic :: hexagon_L2_loadrub_pbr : { Info . opc = ISD :: INTRINSIC_W_CHAIN ; auto & DL = I . getCalledFunction ( ) -> getParent ( ) -> getDataLayout ( ) ; auto & Cont = I . getCalledFunction ( ) -> getParent ( ) -> getContext ( ) ; Type * ElTy = I . getCalledFunction ( ) -> getReturnType ( ) -> getStructElementType ( 0 ) ; Info . memVT = MVT :: getVT ( ElTy ) ; llvm :: Value * BasePtrVal = I . getOperand ( 0 ) ; Info . ptrVal = getUnderLyingObjectForBrevLdIntr ( BasePtrVal ) ; Info . offset = 0 ; Info . align = DL . getABITypeAlign ( Info . memVT . getTypeForEVT ( Cont ) ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case Intrinsic :: hexagon_V6_vgathermw : case Intrinsic :: hexagon_V6_vgathermw_128B : case Intrinsic :: hexagon_V6_vgathermh : case Intrinsic :: hexagon_V6_vgathermh_128B : case Intrinsic :: hexagon_V6_vgathermhw : case Intrinsic :: hexagon_V6_vgathermhw_128B : case Intrinsic :: hexagon_V6_vgathermwq : case Intrinsic :: hexagon_V6_vgathermwq_128B : case Intrinsic :: hexagon_V6_vgathermhq : case Intrinsic :: hexagon_V6_vgathermhq_128B : case Intrinsic :: hexagon_V6_vgathermhwq : case Intrinsic :: hexagon_V6_vgathermhwq_128B : { const Module & M = * I . getParent ( ) -> getParent ( ) -> getParent ( ) ; Info . opc = ISD :: INTRINSIC_W_CHAIN ; Type * VecTy = I . getArgOperand ( 1 ) -> getType ( ) ; Info . memVT = MVT :: getVT ( VecTy ) ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = MaybeAlign ( M . getDataLayout ( ) . getTypeAllocSizeInBits ( VecTy ) / 8 ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } default : break ; } return false ; } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> void SIInstrInfo :: legalizeOpWithMove ( MachineInstr & MI , unsigned OpIdx ) const { MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineOperand & MO = MI . getOperand ( OpIdx ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned RCID = get ( MI . getOpcode ( ) ) . OpInfo [ OpIdx ] . RegClass ; const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Opcode = AMDGPU :: V_MOV_B32_e32 ; if ( MO . isReg ( ) ) Opcode = AMDGPU :: COPY ; else if ( RI . isSGPRClass ( RC ) ) Opcode = AMDGPU :: S_MOV_B32 ; const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ; if ( RI . getCommonSubClass ( & AMDGPU :: VReg_64RegClass , VRC ) ) VRC = & AMDGPU :: VReg_64RegClass ; else VRC = & AMDGPU :: VGPR_32RegClass ; unsigned Reg = MRI . createVirtualRegister ( VRC ) ; DebugLoc DL = MBB -> findDebugLoc ( I ) ; BuildMI ( * MI . getParent ( ) , I , DL , get ( Opcode ) , Reg ) . addOperand ( MO ) ; MO . ChangeToRegister ( Reg , false ) ; } </s>

Legalize the OpIndex operand of this instruction by inserting a MOV .


<s> int aarch64_epilogue_uses ( int regno ) { if ( epilogue_completed ) { if ( regno == LR_REGNUM ) return 1 ; if ( aarch64_simd_decl_p ( cfun -> decl ) && FP_SIMD_SAVED_REGNUM_P ( regno ) ) return 1 ; } return 0 ; } </s>

Return 1 if the register is used by the epilogue . We need to say the return register is used , but only after epilogue generation is complete . Note that in the case of sibcalls , the values `` used by the epilogue '' are considered live at the start of the called function . For SIMD functions we need to return 1 for FP registers that are saved and restored by a function but are not zero in call_used_regs . If we do not do this optimizations may remove the restore of the register .


"\n%s -G value = %d, Arch = %s, ISA = %d\n"


<s> bool RISCVPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> int nonpic_symbol_mentioned_p ( rtx x ) { const char * fmt ; int i ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == PC ) return 1 ; if ( GET_CODE ( x ) == CONST_DOUBLE ) return 0 ; if ( GET_CODE ( x ) == UNSPEC ) return 0 ; fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( x ) ) - 1 ; i >= 0 ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - 1 ; j >= 0 ; j -- ) if ( nonpic_symbol_mentioned_p ( XVECEXP ( x , i , j ) ) ) return 1 ; } else if ( fmt [ i ] == 'e' && nonpic_symbol_mentioned_p ( XEXP ( x , i ) ) ) return 1 ; } return 0 ; } </s>

Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol is n't protected by a PIC unspec .


<s> void mips_declare_common_object ( FILE * stream , const char * name , const char * init_string , unsigned HOST_WIDE_INT size , unsigned int align , bool takes_alignment_p ) { if ( ! takes_alignment_p ) { size += ( align / BITS_PER_UNIT ) - 1 ; size -= size % ( align / BITS_PER_UNIT ) ; mips_declare_object ( stream , name , init_string , "," HOST_WIDE_INT_PRINT_UNSIGNED "\n" , size ) ; } else mips_declare_object ( stream , name , init_string , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n" , size , align / BITS_PER_UNIT ) ; } </s>

Declare a common object of SIZE bytes using asm directive INIT_STRING . NAME is the name of the object and ALIGN is the required alignment in bytes . TAKES_ALIGNMENT_P is true if the directive takes a third alignment argument .


<s> const LEGRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


"32-bit shift counts ought to be enough for anyone"

"Unable to represent scalar shift amount type"

Return the type to use for a scalar shift opcode , given the shifted amount type .


<s> int emit_cbcond_nop ( rtx_insn * insn ) { rtx next = next_active_insn ( insn ) ; if ( ! next ) return 1 ; if ( NONJUMP_INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) == SEQUENCE ) next = XVECEXP ( PATTERN ( next ) , 0 , 0 ) ; else if ( CALL_P ( next ) && GET_CODE ( PATTERN ( next ) ) == PARALLEL ) { rtx delay = XVECEXP ( PATTERN ( next ) , 0 , 1 ) ; if ( GET_CODE ( delay ) == RETURN ) { if ( sparc_leaf_function_p || TARGET_FLAT ) return 0 ; } } if ( NONJUMP_INSN_P ( next ) ) return 0 ; return 1 ; } </s>

Return nonzero if we should emit a nop after a cbcond instruction . The cbcond instruction does not have a delay slot , however there is a severe performance penalty if a control transfer appears right after a cbcond . Therefore we emit a nop when we detect this situation .


<s> void CJGFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { } </s>


<s> MCSymbol * WebAssemblyMCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { const char * Name = MO . getSymbolName ( ) ; MCSymbol * Sym = Printer . GetExternalSymbolSymbol ( Name ) ; if ( isa < MCSymbolELF > ( Sym ) ) return Sym ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Sym ) ; const WebAssemblySubtarget & Subtarget = Printer . getSubtarget ( ) ; if ( strcmp ( Name , "__stack_pointer" ) == 0 ) { WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_GLOBAL ) ; WasmSym -> setGlobalType ( wasm :: WasmGlobalType { uint8_t ( Subtarget . hasAddr64 ( ) ? wasm :: WASM_TYPE_I64 : wasm :: WASM_TYPE_I32 ) , true } ) ; return WasmSym ; } SmallVector < wasm :: ValType , 4 > Returns ; SmallVector < wasm :: ValType , 4 > Params ; GetSignature ( Subtarget , Name , Returns , Params ) ; WasmSym -> setReturns ( std :: move ( Returns ) ) ; WasmSym -> setParams ( std :: move ( Params ) ) ; WasmSym -> setType ( wasm :: WASM_SYMBOL_TYPE_FUNCTION ) ; return WasmSym ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> unsigned char X86Subtarget :: classifyGlobalReference ( const GlobalValue * GV , const Module & M ) const { if ( TM . getCodeModel ( ) == CodeModel :: Large && ! isPositionIndependent ( ) ) return X86II :: MO_NO_FLAG ; if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( 128 ) ) return X86II :: MO_ABS8 ; else return X86II :: MO_NO_FLAG ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( ! GV ) return X86II :: MO_NO_FLAG ; if ( GV -> hasDLLImportStorageClass ( ) ) return X86II :: MO_DLLIMPORT ; return X86II :: MO_COFFSTUB ; } if ( isOSWindows ( ) ) return X86II :: MO_NO_FLAG ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? X86II :: MO_GOT : X86II :: MO_NO_FLAG ; if ( AllowTaggedGlobals && GV && ! isa < Function > ( GV ) ) return X86II :: MO_GOTPCREL_NORELAX ; return X86II :: MO_GOTPCREL ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return X86II :: MO_DARWIN_NONLAZY ; return X86II :: MO_DARWIN_NONLAZY_PIC_BASE ; } if ( TM . getRelocationModel ( ) == Reloc :: Static ) return X86II :: MO_NO_FLAG ; return X86II :: MO_GOT ; } </s>

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context .


<s> int arc_ccfsm_branch_deleted_p ( void ) { if ( arc_ccfsm_state == 1 || arc_ccfsm_state == 2 ) return 1 ; return 0 ; } </s>

See if the current insn , which is a conditional branch , is to be deleted .


<s> const DataLayout * getDataLayout ( ) const override { return & DL ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> int HexagonMCInst :: getMinValue ( void ) const { const uint64_t F = MCID . TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return - 1U << ( bits - 1 ) ; else return 0 ; } </s>

Return the minimal unsigned value possible given these KnownBits .

Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1U 1 0


<s>
void
MipsDAGToDAGISel
::
Select
(
SDNode
*
Node
)
{
unsigned
Opcode
=
Node
->
getOpcode
(
)
;
if
(
Node
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
Node
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
Node
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
Node
)
)
return
;
switch
(
Opcode
)
{
default
:
break
;
case
ISD
::
GLOBAL_OFFSET_TABLE
:
ReplaceNode
(
Node
,
getGlobalBaseReg
(
)
)
;
return
;
case
ISD
::
LOAD
:
case
ISD
::
STORE
:
assert
(
(
Subtarget
->
systemSupportsUnalignedAccess
(
)
||
cast
<
MemSDNode
>
(
Node
)
->
getMemoryVT
(
)
.
getSizeInBits
(
)
/
8
<=
cast
<
MemSDNode
>
(
Node
)
->
getAlignment
(
)
)
&&
"Unexpected unaligned loads/stores."
)
;
break
;
}
SelectCode
(
Node
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .

Mips
Mips
"== "
"\n"
1
ISD::GLOBAL_OFFSET_TABLE
ISD::LOAD
ISD::STORE
8
"Unexpected unaligned loads/stores."


Return the opcode of the special instruction to be used to load the constant X .


<s> static int epiphany_address_cost ( rtx addr , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ) { rtx reg ; rtx off = const0_rtx ; int i ; if ( speed ) return 0 ; switch ( GET_CODE ( addr ) ) { case PLUS : reg = XEXP ( addr , 0 ) ; off = XEXP ( addr , 1 ) ; break ; case POST_MODIFY : reg = XEXP ( addr , 0 ) ; off = XEXP ( addr , 1 ) ; gcc_assert ( GET_CODE ( off ) == PLUS && rtx_equal_p ( reg , XEXP ( off , 0 ) ) ) ; off = XEXP ( off , 1 ) ; if ( satisfies_constraint_Rgs ( reg ) && satisfies_constraint_Rgs ( off ) ) return 0 ; return 1 ; case REG : default : reg = addr ; break ; } if ( ! satisfies_constraint_Rgs ( reg ) ) return 1 ; if ( ! satisfies_constraint_L ( off ) ) return 1 ; i = INTVAL ( off ) ; switch ( GET_MODE_SIZE ( mode ) ) { default : case 4 : if ( i & 1 ) return 1 ; i >>= 1 ; case 2 : if ( i & 1 ) return 1 ; i >>= 1 ; case 1 : return i < - 7 || i > 7 ; } } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> static bool alpha_in_small_data_p ( const_tree exp ) { if ( TREE_CODE ( exp ) == STRING_CST ) return false ; if ( TREE_CODE ( exp ) == FUNCTION_DECL ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_COMMON ( exp ) ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , ".sdata" ) == 0 || strcmp ( section , ".sbss" ) == 0 ) return true ; } else { HOST_WIDE_INT size = int_size_in_bytes ( TREE_TYPE ( exp ) ) ; if ( size > 0 && size <= g_switch_value ) return true ; } return false ; } </s>

Return true if EXP should be placed in the small data section .


Wrapper around the output_probe_stack_range routines .


<s>
static
bool
pdp11_assemble_integer
(
rtx
x
,
unsigned
int
size
,
int
aligned_p
)
{
if
(
aligned_p
)
switch
(
size
)
{
case
1
:
fprintf
(
asm_out_file
,
"\t.byte\t"
)
;
output_addr_const_pdp11
(
asm_out_file
,
x
)
;
fprintf
(
asm_out_file
,
" /* char */\n"
)
;
return
true
;
case
2
:
fprintf
(
asm_out_file
,
TARGET_UNIX_ASM
"\t"
:
"\t.word\t"
)
;
output_addr_const_pdp11
(
asm_out_file
,
x
)
;
fprintf
(
asm_out_file
,
" /* short */\n"
)
;
return
true
;
}
return
default_assemble_integer
(
x
,
size
,
aligned_p
)
;
}
</s>

Target hook to assemble integer objects . We need to use the pdp-specific version of output_addr_const .


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { struct cl_target_option cl_opts ; if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; cl_target_option_save ( & cl_opts , opts , opts_set ) ; arm_configure_build_target ( & arm_active_target , & cl_opts , false ) ; arm_option_check_internal ( opts ) ; arm_option_reconfigure_globals ( ) ; arm_options_perform_arch_sanity_checks ( ) ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts , opts_set ) ; } </s>

Return a TARGET_OPTION_NODE tree of the target options listed or NULL .


<s>
MachineBasicBlock
*
J2TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
MBB
)
const
{
auto
MF
=
MBB
->
getParent
(
)
;
auto
&
Ctx
=
MF
->
getFunction
(
)
.
getContext
(
)
;
auto
&
TTI
=
*
static_cast
<
const
J2Subtarget
&
>
(
MF
->
getSubtarget
(
)
)
.
getInstrInfo
(
)
;
switch
(
MI
.
getOpcode
(
)
)
{
case
J2
::
MOV32ir
:
{
switch
(
MI
.
getOperand
(
1
)
.
getType
(
)
)
{
case
MachineOperand
::
MO_Immediate
:
{
auto
MBBI
=
MI
.
getIterator
(
)
;
auto
Pool
=
MF
->
getConstantPool
(
)
;
auto
Imm
=
MI
.
getOperand
(
1
)
.
getImm
(
)
;
auto
Constant
=
ConstantInt
::
getSigned
(
IntegerType
::
get
(
Ctx
,
32
)
,
Imm
)
;
auto
CPI
=
Pool
->
getConstantPoolIndex
(
Constant
,
4
)
;
BuildMI
(
*
MBB
,
MBBI
,
MBBI
->
getDebugLoc
(
)
,
TTI
.
get
(
J2
::
MOV32PCR
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addConstantPoolIndex
(
CPI
)
;
(
MBBI
++
)
->
eraseFromParent
(
)
;
return
MBB
;
}
default
:
llvm_unreachable
(
"Unexpected operand type for MOV32ir"
)
;
}
break
;
}
default
:
llvm_unreachable
(
"Unexpected instr type to insert"
)
;
}
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> rtx mips16_gp_pseudo_reg ( ) { if ( mips16_gp_pseudo_rtx == NULL_RTX ) { rtx const_gp ; rtx insn , scan ; mips16_gp_pseudo_rtx = gen_reg_rtx ( Pmode ) ; RTX_UNCHANGING_P ( mips16_gp_pseudo_rtx ) = 1 ; const_gp = gen_rtx ( CONST , Pmode , gen_rtx ( REG , Pmode , GP_REG_FIRST + 28 ) ) ; start_sequence ( ) ; emit_move_insn ( mips16_gp_pseudo_rtx , const_gp ) ; insn = gen_sequence ( ) ; end_sequence ( ) ; push_topmost_sequence ( ) ; for ( scan = get_insns ( ) ; scan != NULL_RTX ; scan = NEXT_INSN ( scan ) ) if ( GET_CODE ( scan ) == NOTE && NOTE_LINE_NUMBER ( scan ) == NOTE_INSN_FUNCTION_BEG ) break ; if ( scan == NULL_RTX ) scan = get_insns ( ) ; insn = emit_insn_after ( insn , scan ) ; pop_topmost_sequence ( ) ; } return mips16_gp_pseudo_rtx ; } </s>

If we can access small data directly ( using gp-relative relocation operators ) return the small data pointer , otherwise return null . For each mips16 function which refers to GP relative symbols , we use a pseudo register , initialized at the start of the function , to hold the $ gp value .


<s> unsigned MipsAsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { switch ( Inst . getOpcode ( ) ) { case Mips :: JALR_HB : case Mips :: JALRC_HB_MMR6 : case Mips :: JALRC_MMR6 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case Mips :: LWP_MM : case Mips :: LWP_MMR6 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 2 ) . getReg ( ) ) return Match_RequiresDifferentSrcAndDst ; return Match_Success ; case Mips :: BLEZC : case Mips :: BLEZC_MMR6 : case Mips :: BGEZC : case Mips :: BGEZC_MMR6 : case Mips :: BGTZC : case Mips :: BGTZC_MMR6 : case Mips :: BLTZC : case Mips :: BLTZC_MMR6 : case Mips :: BEQZC : case Mips :: BEQZC_MMR6 : case Mips :: BNEZC : case Mips :: BNEZC_MMR6 : case Mips :: BLEZC64 : case Mips :: BGEZC64 : case Mips :: BGTZC64 : case Mips :: BLTZC64 : case Mips :: BEQZC64 : case Mips :: BNEZC64 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO || Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO_64 ) return Match_RequiresNoZeroRegister ; return Match_Success ; case Mips :: BGEC : case Mips :: BGEC_MMR6 : case Mips :: BLTC : case Mips :: BLTC_MMR6 : case Mips :: BGEUC : case Mips :: BGEUC_MMR6 : case Mips :: BLTUC : case Mips :: BLTUC_MMR6 : case Mips :: BEQC : case Mips :: BEQC_MMR6 : case Mips :: BNEC : case Mips :: BNEC_MMR6 : case Mips :: BGEC64 : case Mips :: BLTC64 : case Mips :: BGEUC64 : case Mips :: BLTUC64 : case Mips :: BEQC64 : case Mips :: BNEC64 : if ( Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO || Inst . getOperand ( 0 ) . getReg ( ) == Mips :: ZERO_64 ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( 1 ) . getReg ( ) == Mips :: ZERO || Inst . getOperand ( 1 ) . getReg ( ) == Mips :: ZERO_64 ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( 0 ) . getReg ( ) == Inst . getOperand ( 1 ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; default : return Match_Success ; } } </s>

checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not expressible via match classes .


<s> const Function & getFunction ( ) const { return Fn ; } </s>

getFunction - Return this trace 's parent function .


"should only be seeing stack pointer offset relative FrameIndex"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned ShaderType = MF . getInfo < R600MachineFunctionInfo > ( ) -> ShaderType ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; EVT VT = Ins [ i ] . VT ; EVT MemVT = LocalIns [ i ] . VT ; if ( ShaderType != ShaderType :: COMPUTE ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: SEXTLOAD ; SDValue Arg = DAG . getExtLoad ( Ext , DL , VT , Chain , DAG . getConstant ( 36 + VA . getLocMemOffset ( ) , MVT :: i32 ) , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , MemVT , false , false , 4 ) ; InVals . push_back ( Arg ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static unsigned int msp430_hard_regno_nregs ( unsigned int , machine_mode mode ) { if ( mode == PSImode && msp430x ) return 1 ; if ( mode == CPSImode && msp430x ) return 2 ; return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; } </s>

Implements HARD_REGNO_NREGS . MSP430X registers can hold a single PSImode value , but not an SImode value .


<s> bool SIRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , Register BaseReg , int64_t Offset ) const { if ( ! SIInstrInfo :: isMUBUF ( * MI ) && ! SIInstrInfo :: isFLATScratch ( * MI ) ) return false ; int64_t NewOffset = Offset + getScratchInstrOffset ( MI ) ; if ( SIInstrInfo :: isMUBUF ( * MI ) ) return SIInstrInfo :: isLegalMUBUFImmOffset ( NewOffset ) ; const SIInstrInfo * TII = ST . getInstrInfo ( ) ; return TII -> isLegalFLATOffset ( NewOffset , AMDGPUAS :: PRIVATE_ADDRESS , SIInstrFlags :: FlatScratch ) ; } </s>

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .

AMDGPU SI SI SI SI SI SI AMDGPU SIInstrFlags::FlatScratch


<s> static bool ix86_binds_local_p ( const_tree exp ) { bool direct_extern_access = ( ix86_direct_extern_access && ! ( VAR_OR_FUNCTION_DECL_P ( exp ) && lookup_attribute ( "nodirect_extern_access" , DECL_ATTRIBUTES ( exp ) ) ) ) ; if ( ! direct_extern_access ) ix86_has_no_direct_extern_access = true ; return default_binds_local_p_3 ( exp , flag_shlib != 0 , true , direct_extern_access , ( direct_extern_access && ( ! flag_pic || ( TARGET_64BIT && HAVE_LD_PIE_COPYRELOC != 0 ) ) ) ) ; } </s>

For i386 , common symbol is local only for non-PIE binaries . For x86-64 , common symbol is local only for non-PIE binaries or linker supports copy reloc in PIE binaries .


<s> bool AArch64IndirectThunks :: doInitialization ( Module & M ) { initTIs ( M , TIs ) ; return false ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> bool GCNTTIImpl :: collectFlatAddressOperands ( SmallVectorImpl < int > & OpIndexes , Intrinsic :: ID IID ) const { switch ( IID ) { case Intrinsic :: amdgcn_atomic_inc : case Intrinsic :: amdgcn_atomic_dec : case Intrinsic :: amdgcn_ds_fadd : case Intrinsic :: amdgcn_ds_fmin : case Intrinsic :: amdgcn_ds_fmax : case Intrinsic :: amdgcn_is_shared : case Intrinsic :: amdgcn_is_private : OpIndexes . push_back ( 0 ) ; return true ; default : return false ; } } </s>

Return any intrinsic address operand indexes which may be rewritten if they use a flat address space pointer .


<s> Value * X86TargetLowering :: getSSPStackGuardCheck ( const Module & M ) const { if ( Subtarget . getTargetTriple ( ) . isOSMSVCRT ( ) ) return M . getFunction ( "__security_check_cookie" ) ; return TargetLowering :: getSSPStackGuardCheck ( M ) ; } </s>

If the target has a standard stack protection check function that performs validation and error handling , returns the function .


"EBP/ESI restoration only required on win32"

"restoring EBP/ESI on non-32-bit target"

"end of registration object above normal EBP position!"

"32-bit frames with WinEH must use FramePtr or BasePtr"

Sets up EBP and optionally ESI based on the incoming EBP value .


<s>
static
void
nios2_print_operand
(
FILE
*
file
,
rtx
op
,
int
letter
)
{
switch
(
letter
)
{
case
'i'
:
if
(
CONSTANT_P
(
op
)
&&
op
!=
const0_rtx
)
fprintf
(
file
,
"i"
)
;
return
;
case
'o'
:
if
(
GET_CODE
(
op
)
==
MEM
&&
(
(
MEM_VOLATILE_P
(
op
)
&&
TARGET_BYPASS_CACHE_VOLATILE
)
||
TARGET_BYPASS_CACHE
)
)
fprintf
(
file
,
"io"
)
;
return
;
default
:
break
;
}
if
(
comparison_operator
(
op
,
VOIDmode
)
)
{
enum
rtx_code
cond
=
GET_CODE
(
op
)
;
if
(
letter
==
0
)
{
fprintf
(
file
,
"%s"
,
GET_RTX_NAME
(
cond
)
)
;
return
;
}
if
(
letter
==
'R'
)
{
fprintf
(
file
,
"%s"
,
GET_RTX_NAME
(
reverse_condition
(
cond
)
)
)
;
return
;
}
}
switch
(
GET_CODE
(
op
)
)
{
case
REG
:
if
(
letter
==
0
||
letter
==
'z'
)
{
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
op
)
]
)
;
return
;
}
else
if
(
letter
==
'D'
)
{
fprintf
(
file
,
"%s"
,
reg_names
[
REGNO
(
op
)
+
1
]
)
;
return
;
}
break
;
case
CONST_INT
:
if
(
INTVAL
(
op
)
==
0
&&
letter
==
'z'
)
{
fprintf
(
file
,
"zero"
)
;
return
;
}
if
(
letter
==
'U'
)
{
HOST_WIDE_INT
val
=
INTVAL
(
op
)
;
val
=
(
val
>>
16
)
&
0xFFFF
;
output_addr_const
(
file
,
gen_int_mode
(
val
,
SImode
)
)
;
return
;
}
case
CONST
:
case
LABEL_REF
:
case
SYMBOL_REF
:
case
CONST_DOUBLE
:
if
(
letter
==
0
||
letter
==
'z'
)
{
output_addr_const
(
file
,
op
)
;
return
;
}
else
if
(
letter
==
'H'
||
letter
==
'L'
)
{
fprintf
(
file
,
"%%"
)
;
if
(
GET_CODE
(
op
)
==
CONST
&&
GET_CODE
(
XEXP
(
op
,
0
)
)
==
UNSPEC
)
{
rtx
unspec
=
XEXP
(
op
,
0
)
;
int
unspec_reloc
=
XINT
(
unspec
,
1
)
;
gcc_assert
(
nios2_large_offset_p
(
unspec_reloc
)
)
;
fprintf
(
file
,
"%s_"
,
nios2_unspec_reloc_name
(
unspec_reloc
)
)
;
op
=
XVECEXP
(
unspec
,
0
,
0
)
;
}
fprintf
(
file
,
letter
==
'H'
"hiadj("
:
"lo("
)
;
output_addr_const
(
file
,
op
)
;
fprintf
(
file
,
")"
)
;
return
;
}
break
;
case
SUBREG
:
case
MEM
:
if
(
letter
==
0
)
{
output_address
(
op
)
;
return
;
}
break
;
case
CODE_LABEL
:
if
(
letter
==
0
)
{
output_addr_const
(
file
,
op
)
;
return
;
}
break
;
default
:
break
;
}
output_operand_lossage
(
"Unsupported operand for code '%c'"
,
letter
)
;
gcc_unreachable
(
)
;
}
</s>

Print the operand OP to file stream FILE modified by LETTER . LETTER can be one of : i : print `` i '' if OP is an immediate , except 0 o : print `` io '' if OP is volatile z : for const0_rtx print $ 0 instead of 0 H : for % hiadj L : for % lo U : for upper half of 32 bit value D : for the upper 32-bits of a 64-bit double value R : prints reverse condition .


<s> void override_options ( void ) { target_flags &= ~ MASK_GPOPT ; iq2000_isa = IQ2000_ISA_DEFAULT ; iq2000_print_operand_punct [ '?' ] = 1 ; iq2000_print_operand_punct [ '#' ] = 1 ; iq2000_print_operand_punct [ '&' ] = 1 ; iq2000_print_operand_punct [ '!' ] = 1 ; iq2000_print_operand_punct [ '*' ] = 1 ; iq2000_print_operand_punct [ '@' ] = 1 ; iq2000_print_operand_punct [ '.' ] = 1 ; iq2000_print_operand_punct [ '(' ] = 1 ; iq2000_print_operand_punct [ ')' ] = 1 ; iq2000_print_operand_punct [ '[' ] = 1 ; iq2000_print_operand_punct [ ']' ] = 1 ; iq2000_print_operand_punct [ '<' ] = 1 ; iq2000_print_operand_punct [ '>' ] = 1 ; iq2000_print_operand_punct [ '{' ] = 1 ; iq2000_print_operand_punct [ '}' ] = 1 ; iq2000_print_operand_punct [ '^' ] = 1 ; iq2000_print_operand_punct [ '$' ] = 1 ; iq2000_print_operand_punct [ '+' ] = 1 ; iq2000_print_operand_punct [ '~' ] = 1 ; gpr_mode = SImode ; init_machine_status = iq2000_init_machine_status ; } </s>

Set global variables as needed for the options enabled .


<s> static bool ix86_legitimate_combined_insn ( rtx_insn * insn ) { if ( ( INSN_CODE ( insn ) = recog ( PATTERN ( insn ) , insn , 0 ) ) >= 0 ) { int i ; extract_insn ( insn ) ; preprocess_constraints ( insn ) ; int n_operands = recog_data . n_operands ; int n_alternatives = recog_data . n_alternatives ; for ( i = 0 ; i < n_operands ; i ++ ) { rtx op = recog_data . operand [ i ] ; machine_mode mode = GET_MODE ( op ) ; const operand_alternative * op_alt ; int offset = 0 ; bool win ; int j ; if ( ! TARGET_AVX && VECTOR_MODE_P ( GET_MODE ( op ) ) && misaligned_operand ( op , GET_MODE ( op ) ) ) { int min_align = get_attr_ssememalign ( insn ) ; if ( min_align == 0 ) return false ; } if ( UNARY_P ( op ) ) op = XEXP ( op , 0 ) ; if ( GET_CODE ( op ) == SUBREG ) { if ( REG_P ( SUBREG_REG ( op ) ) && REGNO ( SUBREG_REG ( op ) ) < FIRST_PSEUDO_REGISTER ) offset = subreg_regno_offset ( REGNO ( SUBREG_REG ( op ) ) , GET_MODE ( SUBREG_REG ( op ) ) , SUBREG_BYTE ( op ) , GET_MODE ( op ) ) ; op = SUBREG_REG ( op ) ; } if ( ! ( REG_P ( op ) && HARD_REGISTER_P ( op ) ) ) continue ; op_alt = recog_op_alt ; win = ! n_alternatives ; alternative_mask preferred = get_preferred_alternatives ( insn ) ; for ( j = 0 ; j < n_alternatives ; j ++ , op_alt += n_operands ) { if ( ! TEST_BIT ( preferred , j ) ) continue ; if ( op_alt [ i ] . anything_ok || ( op_alt [ i ] . matches != - 1 && operands_match_p ( recog_data . operand [ i ] , recog_data . operand [ op_alt [ i ] . matches ] ) ) || reg_fits_class_p ( op , op_alt [ i ] . cl , offset , mode ) ) { win = true ; break ; } } if ( ! win ) return false ; } } return true ; } </s>

Implement the TARGET_LEGITIMATE_COMBINED_INSN hook .


<s>
bool
ARCFrameLowering
::
assignCalleeSavedSpillSlots
(
MachineFunction
&
MF
,
const
TargetRegisterInfo
*
TRI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
)
const
{
int
CurOffset
=
4
;
unsigned
Last
=
determineLastCalleeSave
(
CSI
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
if
(
hasFP
(
MF
)
)
{
int
StackObj
=
MFI
.
CreateFixedSpillStackObject
(
4
,
CurOffset
,
true
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Creating fixed object ("
<<
StackObj
<<
") for FP at "
<<
CurOffset
<<
"\n"
)
;
(
void
)
StackObj
;
CurOffset
-=
4
;
}
if
(
MFI
.
hasCalls
(
)
||
(
UseSaveRestoreFunclet
&&
Last
>
ARC
::
R14
)
)
{
int
StackObj
=
MFI
.
CreateFixedSpillStackObject
(
4
,
CurOffset
,
true
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Creating fixed object ("
<<
StackObj
<<
") for BLINK at "
<<
CurOffset
<<
"\n"
)
;
(
void
)
StackObj
;
CurOffset
-=
4
;
}
for
(
unsigned
Which
=
Last
;
Which
>
ARC
::
R12
;
Which
)
{
auto
RegI
=
getSavedReg
(
CSI
,
Which
)
;
if
(
RegI
==
CSI
.
end
(
)
||
RegI
->
getFrameIdx
(
)
==
0
)
{
int
FI
=
MFI
.
CreateFixedSpillStackObject
(
4
,
CurOffset
,
true
)
;
if
(
RegI
!=
CSI
.
end
(
)
)
RegI
->
setFrameIdx
(
FI
)
;
}
else
MFI
.
setObjectOffset
(
RegI
->
getFrameIdx
(
)
,
CurOffset
)
;
CurOffset
-=
4
;
}
for
(
auto
&
I
:
CSI
)
{
if
(
I
.
getReg
(
)
>
ARC
::
R12
)
continue
;
if
(
I
.
getFrameIdx
(
)
==
0
)
{
I
.
setFrameIdx
(
MFI
.
CreateFixedSpillStackObject
(
4
,
CurOffset
,
true
)
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Creating fixed object ("
<<
I
.
getFrameIdx
(
)
<<
") for other register at "
<<
CurOffset
<<
"\n"
)
;
}
else
{
MFI
.
setObjectOffset
(
I
.
getFrameIdx
(
)
,
CurOffset
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
"Updating fixed object ("
<<
I
.
getFrameIdx
(
)
<<
") for other register at "
<<
CurOffset
<<
"\n"
)
;
}
CurOffset
-=
4
;
}
return
true
;
}
</s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s> MCSection * ARMElfTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind SK , const TargetMachine & TM ) const { if ( genExecuteOnly && SK . isText ( ) ) SK = SectionKind :: getExecuteOnly ( ) ; return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GO , SK , TM ) ; } </s>

Targets should implement this method to assign a section to globals with an explicit section specfied .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> TargetLowering :: AtomicExpansionKind AMDGPUTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * RMW ) const { if ( RMW -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: CmpXChg ; return AtomicExpansionKind :: None ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> static bool m32c_print_operand_punct_valid_p ( unsigned char c ) { if ( c == '&' || c == '!' ) return true ; return false ; } </s>

Implements PRINT_OPERAND_PUNCT_VALID_P . See m32c_print_operand above for descriptions of what these do .


<s> static bool s390_legitimate_constant_p ( machine_mode mode , rtx op ) { if ( ! SYMBOLIC_CONST ( op ) ) return 1 ; if ( TARGET_CPU_ZARCH && larl_operand ( op , mode ) ) return 1 ; if ( TLS_SYMBOLIC_CONST ( op ) ) return 0 ; if ( flag_pic ) return 1 ; return 0 ; } </s>

Returns true if the constant value OP is a legitimate general operand . It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE .


<s> void func_fma_steering :: analyze ( ) { int i , n_blocks , * bb_dfs_preorder ; basic_block bb ; rtx_insn * insn ; bb_dfs_preorder = XNEWVEC ( int , last_basic_block_for_fn ( cfun ) ) ; n_blocks = pre_and_rev_post_order_compute ( bb_dfs_preorder , NULL , false ) ; for ( i = 0 ; i < n_blocks ; i ++ ) { bb = BASIC_BLOCK_FOR_FN ( cfun , bb_dfs_preorder [ i ] ) ; FOR_BB_INSNS ( bb , insn ) { operand_rr_info * dest_op_info ; struct du_chain * chain = NULL ; unsigned dest_regno ; fma_forest * forest = NULL ; du_head_p head = NULL ; int i ; if ( ! is_fmul_fmac_insn ( insn , true ) ) continue ; dest_op_info = insn_rr [ INSN_UID ( insn ) ] . op_info ; dest_regno = REGNO ( SET_DEST ( PATTERN ( insn ) ) ) ; for ( i = 0 ; i < dest_op_info -> n_chains ; i ++ ) { if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; forest = NULL ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * * fma_slot ; if ( ! is_fmul_fmac_insn ( chain -> insn , true ) ) continue ; if ( chain -> loc != & SET_DEST ( PATTERN ( chain -> insn ) ) ) continue ; if ( chain -> insn == insn ) break ; fma_slot = this -> m_insn_fma_head_map -> get ( chain -> insn ) ; if ( fma_slot && ( * fma_slot ) -> get_children ( ) ) forest = ( * fma_slot ) -> get_forest ( ) ; } if ( chain ) break ; } gcc_assert ( i < dest_op_info -> n_chains ) ; this -> analyze_fma_fmul_insn ( forest , chain , head ) ; } } free ( bb_dfs_preorder ) ; if ( dump_file ) this -> dfs ( dump_forest_info , dump_tree_root_info , dump_tree_node_info , false ) ; } </s>

Count how many times each regno is referenced as base address for a memory access .


<s> bool isReg ( ) const { return Kind == MachineOperand :: MO_Register ; } </s>


<s> static bool ix86_save_reg ( unsigned int regno , bool maybe_eh_return , bool ignore_outlined ) { if ( cfun -> machine -> no_caller_saved_registers ) { rtx reg = crtl -> return_rtx ; if ( reg ) { unsigned int i = REGNO ( reg ) ; unsigned int nregs = REG_NREGS ( reg ) ; while ( nregs -- > 0 ) if ( ( i + nregs ) == regno ) return false ; } return ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } if ( regno == REAL_PIC_OFFSET_TABLE_REGNUM && pic_offset_table_rtx ) { if ( ix86_use_pseudo_pic_reg ( ) ) { if ( ! TARGET_64BIT && flag_pic && crtl -> profile ) return true ; } else if ( df_regs_ever_live_p ( REAL_PIC_OFFSET_TABLE_REGNUM ) || crtl -> profile || crtl -> calls_eh_return || crtl -> uses_const_pool || cfun -> has_nonlocal_label ) return ix86_select_alt_pic_regnum ( ) == INVALID_REGNUM ; } if ( crtl -> calls_eh_return && maybe_eh_return ) { unsigned i ; for ( i = 0 ; ; i ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return true ; } } if ( ignore_outlined && cfun -> machine -> call_ms2sysv ) { unsigned count = cfun -> machine -> call_ms2sysv_extra_regs + xlogue_layout :: MIN_REGS ; if ( xlogue_layout :: is_stub_managed_reg ( regno , count ) ) return false ; } if ( crtl -> drap_reg && regno == REGNO ( crtl -> drap_reg ) && ! cfun -> machine -> no_drap_save_restore ) return true ; return ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] && ! fixed_regs [ regno ] && ( regno != HARD_FRAME_POINTER_REGNUM || ! frame_pointer_needed ) ) ; } </s>


<s>
void
AArch64RegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
assert
(
SPAdj
==
0
&&
"Unexpected"
)
;
MachineInstr
&
MI
=
*
II
;
MachineBasicBlock
&
MBB
=
*
MI
.
getParent
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
AArch64FrameLowering
*
TFI
=
static_cast
<
const
AArch64FrameLowering
*
>
(
MF
.
getSubtarget
(
)
.
getFrameLowering
(
)
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
unsigned
FrameReg
;
int
Offset
;
if
(
MI
.
isDebugValue
(
)
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
STACKMAP
||
MI
.
getOpcode
(
)
==
TargetOpcode
::
PATCHPOINT
)
{
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
,
true
)
;
Offset
+=
MI
.
getOperand
(
FIOperandNum
+
1
)
.
getImm
(
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
FrameReg
,
false
)
;
MI
.
getOperand
(
FIOperandNum
+
1
)
.
ChangeToImmediate
(
Offset
)
;
return
;
}
Offset
=
TFI
->
resolveFrameIndexReference
(
MF
,
FrameIndex
,
FrameReg
)
;
if
(
rewriteAArch64FrameIndex
(
MI
,
FIOperandNum
,
FrameReg
,
Offset
,
TII
)
)
return
;
assert
(
(
!
RS
||
!
RS
->
isScavengingFrameIndex
(
FrameIndex
)
)
&&
"Emergency spill slot is out of reach"
)
;
unsigned
ScratchReg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
&
AArch64
::
GPR64RegClass
)
;
emitFrameOffset
(
MBB
,
II
,
MI
.
getDebugLoc
(
)
,
ScratchReg
,
FrameReg
,
Offset
,
TII
)
;
MI
.
getOperand
(
FIOperandNum
)
.
ChangeToRegister
(
ScratchReg
,
false
,
false
,
true
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


"Must not have more than 6553 virtual functions!"

"Warning: Did not recognize vcall instruction, but I need to make sure it has room!\n"

runOnMachineFunction - Emit the function body .


<s> SDValue MipsTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , SDLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; MipsCC MipsCCInfo ( CallConv , isO32 ( ) , Subtarget -> isFP64bit ( ) , CCInfo ) ; MipsCCInfo . analyzeCallResult ( Ins , Subtarget -> mipsSEUsesSoftFloat ( ) , CallNode , RetTy ) ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( 1 ) ; InFlag = Val . getValue ( 2 ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( ISD :: BITCAST , DL , RVLocs [ i ] . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ; } return Chain ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> void MBlazeAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MBlazeMCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> const SystemZInstrInfo * getInstrInfo ( ) const { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


"passing %qT to argument %d of %qE, which"

" expects a vector of 32-bit or 64-bit elements"

Like infer_vector_type , but also require the element size to be 32 or 64 bits .


<s> const uint16_t * DCPU16RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const Function * F = MF -> getFunction ( ) ; static const uint16_t CalleeSavedRegs [ ] = { DCPU16 :: X , DCPU16 :: Y , DCPU16 :: Z , DCPU16 :: I , DCPU16 :: J , 0 } ; static const uint16_t CalleeSavedRegsIntr [ ] = { DCPU16 :: EX , DCPU16 :: B , DCPU16 :: C , DCPU16 :: X , DCPU16 :: Y , DCPU16 :: Z , DCPU16 :: I , DCPU16 :: J , 0 } ; return ( F -> getCallingConv ( ) == CallingConv :: DCPU16_INTR ? CalleeSavedRegsIntr : CalleeSavedRegs ) ; } </s>


<s> static void m32r_setup_incoming_varargs ( cumulative_args_t cum , const function_arg_info & arg , int * pretend_size , int no_rtl ) { int first_anon_arg ; if ( no_rtl ) return ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) gcc_assert ( arg . mode != BLKmode ) ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) first_anon_arg = ( ROUND_ADVANCE_CUM ( * get_cumulative_args ( cum ) , arg . mode , arg . type ) + ROUND_ADVANCE_ARG ( arg . mode , arg . type ) ) ; else first_anon_arg = * get_cumulative_args ( cum ) ; if ( first_anon_arg < M32R_MAX_PARM_REGS ) { int first_reg_offset = first_anon_arg ; int size = M32R_MAX_PARM_REGS - first_reg_offset ; rtx regblock ; regblock = gen_frame_mem ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( 0 ) ) ) ; set_mem_alias_set ( regblock , get_varargs_alias_set ( ) ) ; move_block_from_reg ( first_reg_offset , regblock , size ) ; * pretend_size = ( size * UNITS_PER_WORD ) ; } } </s>

Do any needed setup for a variadic function . For the M32R , we must create a register parameter block , and then copy any anonymous arguments in registers to memory . CUM has not been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> static int thumb_find_work_register ( unsigned long pushed_regs_mask ) { int reg ; for ( reg = LAST_ARG_REGNUM ; reg >= 0 ; reg -- ) if ( ! df_regs_ever_live_p ( reg ) ) return reg ; if ( cfun -> machine -> uses_anonymous_args && crtl -> args . pretend_args_size > 0 ) return LAST_ARG_REGNUM ; if ( ! cfun -> machine -> uses_anonymous_args && crtl -> args . size >= 0 && crtl -> args . size <= ( LAST_ARG_REGNUM * UNITS_PER_WORD ) && ( TARGET_AAPCS_BASED ? crtl -> args . info . aapcs_ncrn < 4 : crtl -> args . info . nregs < 4 ) ) return LAST_ARG_REGNUM ; for ( reg = LAST_LO_REGNUM ; reg > LAST_ARG_REGNUM ; reg -- ) if ( pushed_regs_mask & ( 1 << reg ) ) return reg ; if ( TARGET_THUMB2 ) { for ( reg = FIRST_HI_REGNUM ; reg < 15 ; reg ++ ) if ( pushed_regs_mask & ( 1 << reg ) ) return reg ; } gcc_unreachable ( ) ; } </s>

Find a spare low register to use during the prolog of a function .


<s> static void function_arg_record_value_2 ( tree type , HOST_WIDE_INT startbitpos , struct function_arg_record_value_parms * parms , bool packed_p ) { tree field ; if ( ! packed_p ) for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL && DECL_PACKED ( field ) ) { packed_p = true ; break ; } } for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { HOST_WIDE_INT bitpos = startbitpos ; if ( DECL_SIZE ( field ) != 0 ) { if ( integer_zerop ( DECL_SIZE ( field ) ) ) continue ; if ( host_integerp ( bit_position ( field ) , 1 ) ) bitpos += int_bit_position ( field ) ; } if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) function_arg_record_value_2 ( TREE_TYPE ( field ) , bitpos , parms , packed_p ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU && parms -> named && ! packed_p ) { int this_slotno = parms -> slotno + bitpos / BITS_PER_WORD ; int regno , nregs , pos ; enum machine_mode mode = DECL_MODE ( field ) ; rtx reg ; function_arg_record_value_3 ( bitpos , parms ) ; if ( TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE && mode == BLKmode ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( field ) ) ; } else if ( TREE_CODE ( TREE_TYPE ( field ) ) == COMPLEX_TYPE ) { mode = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( field ) ) ) ; nregs = 2 ; } else nregs = 1 ; regno = SPARC_FP_ARG_FIRST + this_slotno * 2 ; if ( GET_MODE_SIZE ( mode ) <= 4 && ( bitpos & 32 ) != 0 ) regno ++ ; reg = gen_rtx_REG ( mode , regno ) ; pos = bitpos / BITS_PER_UNIT ; XVECEXP ( parms -> ret , 0 , parms -> stack + parms -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; parms -> nregs += 1 ; while ( -- nregs > 0 ) { regno += GET_MODE_SIZE ( mode ) / 4 ; reg = gen_rtx_REG ( mode , regno ) ; pos += GET_MODE_SIZE ( mode ) ; XVECEXP ( parms -> ret , 0 , parms -> stack + parms -> nregs ) = gen_rtx_EXPR_LIST ( VOIDmode , reg , GEN_INT ( pos ) ) ; parms -> nregs += 1 ; } } else { if ( parms -> intoffset == - 1 ) parms -> intoffset = bitpos ; } } } } </s>

A subroutine of function_arg_record_value . Traverse the structure recursively and assign bits to floating point registers . Track which bits in between need integer registers ; invoke function_arg_record_value_3 to make that happen .


<s> class LLVM_LIBRARY_VISIBILITY LM32MCInstLower { LM32AsmPrinter & AsmPrinter ; const MCExpr * getExpr ( const MachineOperand & MO ) const ; public : LM32MCInstLower ( LM32AsmPrinter & asmPrinter ) ; void lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand lowerOperand ( const MachineOperand & MO ) const ; } </s>

Implementation of the SCEVPredicate interface .


<s> int direct_return ( ) { return ( reload_completed && xstormy16_compute_stack_layout ( ) . frame_size == 0 ) ; } </s>

Return non-zero if this function is known to have a null epilogue .


<s> machine_mode memory_vector_mode ( const function_instance & ) const override { return m_mode ; } </s>

If the function addresses memory , return a vector mode whose GET_MODE_NUNITS is the number of elements addressed and whose GET_MODE_INNER is the mode of a single scalar memory element .


<s> void OR1KInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void Thumb2InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( ARM :: GPRRegClass . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( ARM :: t2STRi12 ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } if ( ARM :: GPRPairRegClass . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & ARM :: GPRPairnospRegClass ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( ARM :: t2STRDi8 ) ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_0 , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , ARM :: gsub_1 , 0 , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) . add ( predOps ( ARMCC :: AL ) ) ; return ; } ARMBaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


"Caller should have handled 0-size case"

Emit target-specific code that performs a memcmp/bcmp , in cases where that is faster than a libcall .


<s> BitVector AArch64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AArch64 :: SP ) ; Reserved . set ( AArch64 :: XZR ) ; Reserved . set ( AArch64 :: WSP ) ; Reserved . set ( AArch64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) { Reserved . set ( AArch64 :: FP ) ; Reserved . set ( AArch64 :: W29 ) ; } if ( STI -> isTargetDarwin ( ) ) { Reserved . set ( AArch64 :: X18 ) ; Reserved . set ( AArch64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( AArch64 :: X19 ) ; Reserved . set ( AArch64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s>
void
XtensaInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
llvm_unreachable
(
"Unimplemented operand"
)
;
}
</s>


<s> bool SparcPassConfig :: addPreEmitPass ( ) { PM . add ( createSparcFPMoverPass ( getSparcTargetMachine ( ) ) ) ; PM . add ( createSparcDelaySlotFillerPass ( getSparcTargetMachine ( ) ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> bool GBZ80FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return false ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


<s> static bool ix86_ok_to_clobber_flags ( rtx_insn * insn ) { basic_block bb = BLOCK_FOR_INSN ( insn ) ; df_ref use ; bitmap live ; while ( insn ) { if ( NONDEBUG_INSN_P ( insn ) ) { FOR_EACH_INSN_USE ( use , insn ) if ( DF_REF_REG_USE_P ( use ) && DF_REF_REGNO ( use ) == FLAGS_REG ) return false ; if ( insn_defines_reg ( FLAGS_REG , INVALID_REGNUM , insn ) ) return true ; } if ( insn == BB_END ( bb ) ) break ; insn = NEXT_INSN ( insn ) ; } live = df_get_live_out ( bb ) ; return ! REGNO_REG_SET_P ( live , FLAGS_REG ) ; } </s>

Return true if it is legal to clobber flags by INSN and false otherwise .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"OR1K Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool AArch64AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { if ( ( uint32_t ) Fixup . getKind ( ) == AArch64 :: fixup_aarch64_pcrel_adrp_imm21 ) return true ; return false ; } </s>

Hook to check if a relocation is needed for some target specific reason .


<s> void TPCPassConfig :: addIRPasses ( ) { addPass ( createTPCIndexGen ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; addPass ( createTPCAAWrapperPass ( ) ) ; addPass ( createExternalAAWrapperPass ( [ ] ( Pass & P , Function & , AAResults & AAR ) { if ( auto * WrapperPass = P . getAnalysisIfAvailable < TPCAAWrapperPass > ( ) ) AAR . addAAResult ( WrapperPass -> getResult ( ) ) ; } ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool AArch64RegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const AArch64FrameLowering * AFI = static_cast < const AArch64FrameLowering * > ( TFI ) ; return AFI -> useFPForAddressing ( MF ) ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> unsigned int UPTInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { return TargetInstrInfo :: isStoreToStackSlot ( MI , FrameIndex ) ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void mips16_rewrite_pool_constant ( struct mips16_constant_pool * pool , rtx * x ) { rtx base , offset ; rtx_code_label * label ; split_const ( * x , & base , & offset ) ; if ( GET_CODE ( base ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( base ) ) { label = mips16_add_constant ( pool , copy_rtx ( get_pool_constant ( base ) ) , get_pool_mode ( base ) ) ; base = gen_rtx_LABEL_REF ( Pmode , label ) ; * x = mips_unspec_address_offset ( base , offset , SYMBOL_PC_RELATIVE ) ; } } </s>

If * X is a symbolic constant that refers to the constant pool , add the constant to POOL and rewrite * X to use the constant 's label .


<s> static int aarch64_sched_variable_issue ( FILE * , int , rtx_insn * insn , int more ) { if ( DEBUG_INSN_P ( insn ) ) return more ; rtx_code code = GET_CODE ( PATTERN ( insn ) ) ; if ( code == USE || code == CLOBBER ) return more ; if ( get_attr_type ( insn ) == TYPE_NO_INSN ) return more ; return more - 1 ; } </s>


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( TM ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } } </s>


<s>
int
HexagonFrameLowering
::
getFrameIndexReference
(
const
MachineFunction
&
MF
,
int
FI
,
unsigned
&
FrameReg
)
const
{
auto
&
MFI
=
MF
.
getFrameInfo
(
)
;
auto
&
HRI
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
int
Offset
=
MFI
.
getObjectOffset
(
FI
)
;
bool
HasAlloca
=
MFI
.
hasVarSizedObjects
(
)
;
bool
HasExtraAlign
=
HRI
.
needsStackRealignment
(
MF
)
;
bool
NoOpt
=
MF
.
getTarget
(
)
.
getOptLevel
(
)
==
CodeGenOpt
::
;
auto
&
HMFI
=
*
MF
.
getInfo
<
HexagonMachineFunctionInfo
>
(
)
;
unsigned
FrameSize
=
MFI
.
getStackSize
(
)
;
unsigned
SP
=
HRI
.
getStackRegister
(
)
;
unsigned
FP
=
HRI
.
getFrameRegister
(
)
;
unsigned
AP
=
HMFI
.
getStackAlignBasePhysReg
(
)
;
if
(
AP
==
0
)
AP
=
FP
;
bool
UseFP
=
false
,
UseAP
=
false
;
if
(
NoOpt
&&
!
HasExtraAlign
)
UseFP
=
true
;
if
(
MFI
.
isFixedObjectIndex
(
FI
)
||
MFI
.
isObjectPreAllocated
(
FI
)
)
{
UseFP
|=
(
HasAlloca
||
HasExtraAlign
)
;
}
else
{
if
(
HasAlloca
)
{
if
(
HasExtraAlign
)
UseAP
=
true
;
else
UseFP
=
true
;
}
}
bool
HasFP
=
hasFP
(
MF
)
;
assert
(
(
HasFP
||
!
UseFP
)
&&
"This function must have frame pointer"
)
;
if
(
Offset
>
0
&&
!
HasFP
)
Offset
-=
8
;
if
(
UseFP
)
FrameReg
=
FP
;
else
if
(
UseAP
)
FrameReg
=
AP
;
else
FrameReg
=
SP
;
int
RealOffset
=
Offset
;
if
(
!
UseFP
&&
!
UseAP
)
RealOffset
=
FrameSize
+
Offset
;
return
RealOffset
;
}
</s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool AMDGPUTTIImpl :: isSourceOfDivergence ( const Value * V ) const { if ( const Argument * A = dyn_cast < Argument > ( V ) ) return ! isArgPassedInSGPR ( A ) ; if ( const LoadInst * Load = dyn_cast < LoadInst > ( V ) ) return Load -> getPointerAddressSpace ( ) == AMDGPUAS :: PRIVATE_ADDRESS ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; return isIntrinsicSourceOfDivergence ( TM . getIntrinsicInfo ( ) , Intrinsic ) ; } if ( isa < CallInst > ( V ) || isa < InvokeInst > ( V ) ) return true ; return false ; } </s>

Returns whether V is a source of divergence .


<s> SDValue AMDGPUTargetLowering :: SplitVectorStore ( SDValue Op , SelectionDAG & DAG ) const { StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; SDValue Val = Store -> getValue ( ) ; EVT VT = Val . getValueType ( ) ; if ( VT . getVectorNumElements ( ) == 2 ) return ScalarizeVectorStore ( Op , DAG ) ; EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( ISD :: ADD , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , BaseAlign ) ; SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT , Store -> isNonTemporal ( ) , Store -> isVolatile ( ) , HiAlign ) ; return DAG . getNode ( ISD :: TokenFactor , SL , MVT :: Other , LoStore , HiStore ) ; } </s>

Split a vector store into 2 stores of half the vector .

AMDGPU AMDGPU 2 ISD::ADD ISD::TokenFactor MVT::Other


<s> MCSymbol * J2MCInstLower :: GetExternalSymbolSymbol ( const MachineOperand & MO ) const { return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } </s>

Return the MCSymbol for the specified ExternalSymbol .


<s> static inline rtx xtensa_expand_mask_and_shift ( rtx val , machine_mode mode , rtx count ) { val = expand_simple_binop ( SImode , AND , val , GEN_INT ( GET_MODE_MASK ( mode ) ) , NULL_RTX , 1 , OPTAB_DIRECT ) ; return expand_simple_binop ( SImode , ASHIFT , val , count , NULL_RTX , 1 , OPTAB_DIRECT ) ; } </s>

Shift VAL of mode MODE left by COUNT bits .


<s> int sh_media_register_for_return ( void ) { int regno ; int tr0_used ; if ( ! crtl -> is_leaf ) return - 1 ; if ( lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( current_function_decl ) ) ) return - 1 ; if ( sh_cfun_interrupt_handler_p ( ) ) return - 1 ; tr0_used = flag_pic && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ; for ( regno = FIRST_TARGET_REG + tr0_used ; regno <= LAST_TARGET_REG ; regno ++ ) if ( call_really_used_regs [ regno ] && ! df_regs_ever_live_p ( regno ) ) return regno ; return - 1 ; } </s>

Choose a call-clobbered target-branch register that remains unchanged along the whole function . We set it up as the return value in the prologue .


<s> bool MOSPassConfig :: addRegBankSelect ( ) { addPass ( new RegBankSelect ( ) ) ; return false ; } </s>

This method should install a register bank selector pass , which assigns register banks to virtual registers without a register class or register banks .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addRequired < MachineBlockFrequencyInfo > ( ) ; AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addRequired < SlotIndexes > ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < LiveStacks > ( ) ; AU . addPreserved < LiveStacks > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; AU . addPreserved < MachineLoopInfo > ( ) ; AU . addRequired < VirtRegMap > ( ) ; AU . addPreserved < VirtRegMap > ( ) ; AU . addRequired < LiveRegMatrix > ( ) ; AU . addPreserved < LiveRegMatrix > ( ) ; AU . addRequired < EdgeBundles > ( ) ; AU . addRequired < SpillPlacement > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


"Instruction use requires option to be enabled"

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> const uint32_t * GBZ80RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CallConv ) const { return CSR_16_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static int reg_plus_index_p ( rtx x , enum machine_mode mode , int strict ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) != PLUS ) return 0 ; xfoo0 = XEXP ( x , 0 ) ; xfoo1 = XEXP ( x , 1 ) ; if ( BASE_REGISTER_P ( xfoo0 , strict ) && index_term_p ( xfoo1 , mode , strict ) ) return 1 ; if ( BASE_REGISTER_P ( xfoo1 , strict ) && index_term_p ( xfoo0 , mode , strict ) ) return 1 ; return 0 ; } </s>

Return 1 if X is the sum of a register and a valid index term for mode MODE .


<s> static int riscv_integer_cost ( HOST_WIDE_INT val ) { struct riscv_integer_op codes [ RISCV_MAX_INTEGER_OPS ] ; return MIN ( riscv_build_integer ( codes , val , VOIDmode ) , riscv_split_integer_cost ( val ) ) ; } </s>

Return the cost of constructing the integer constant VAL .


<s> static bool ix86_scalar_mode_supported_p ( scalar_mode mode ) { if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return default_decimal_float_supported_p ( ) ; else if ( mode == TFmode ) return true ; else if ( mode == HFmode && TARGET_SSE2 ) return true ; else return default_scalar_mode_supported_p ( mode ) ; } </s>

Target hook for scalar_mode_supported_p .


<s> static rtx alignment_mask ( rtx_insn * insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != AND || ! REG_P ( XEXP ( SET_SRC ( body ) , 0 ) ) ) return 0 ; rtx mask = XEXP ( SET_SRC ( body ) , 1 ) ; if ( CONST_INT_P ( mask ) ) { if ( INTVAL ( mask ) == - 16 ) return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; else return 0 ; } if ( ! REG_P ( mask ) ) return 0 ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; rtx real_mask = 0 ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( use ) , mask ) ) continue ; struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return 0 ; rtx_insn * const_insn = DF_REF_INSN ( def_link -> ref ) ; rtx const_body = PATTERN ( const_insn ) ; if ( GET_CODE ( const_body ) != SET ) return 0 ; real_mask = SET_SRC ( const_body ) ; if ( ! CONST_INT_P ( real_mask ) || INTVAL ( real_mask ) != - 16 ) return 0 ; } if ( real_mask == 0 ) return 0 ; return alignment_with_canonical_addr ( SET_SRC ( body ) ) ; } </s>

Check whether an rtx is an alignment mask , and if so , return a fully-expanded rtx for the masking operation .


<s> static unsigned int insn_is_swap_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) != SET ) return 0 ; rtx rhs = SET_SRC ( body ) ; if ( pattern_is_rotate64 ( body ) ) return 1 ; if ( GET_CODE ( rhs ) != VEC_SELECT ) return 0 ; rtx parallel = XEXP ( rhs , 1 ) ; if ( GET_CODE ( parallel ) != PARALLEL ) return 0 ; unsigned int len = XVECLEN ( parallel , 0 ) ; if ( len != 2 && len != 4 && len != 8 && len != 16 ) return 0 ; for ( unsigned int i = 0 ; i < len / 2 ; ++ i ) { rtx op = XVECEXP ( parallel , 0 , i ) ; if ( ! CONST_INT_P ( op ) || INTVAL ( op ) != len / 2 + i ) return 0 ; } for ( unsigned int i = len / 2 ; i < len ; ++ i ) { rtx op = XVECEXP ( parallel , 0 , i ) ; if ( ! CONST_INT_P ( op ) || INTVAL ( op ) != i - len / 2 ) return 0 ; } return 1 ; } </s>

Return 1 iff INSN swaps doublewords . This may be a reg-reg swap , a permuting load , or a permuting store .


"Unconditional branch with multiple successors!"

Insert branch code into the end of the specified MachineBasicBlock .


<s> const OR1KTargetMachine & getTargetMachine ( ) { return static_cast < const OR1KTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> Register LoongArchRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? LoongArch :: R22 : LoongArch :: R3 ; } </s>


<s> OperandMatchResultTy AArch64AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = getLoc ( ) ; auto Res = tryParseScalarRegister ( RegNo ) ; EndLoc = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - 1 ) ; return Res ; } </s>

tryParseRegister - parse one register if possible


<s>
unsigned
WebAssemblyMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
return
MRI
.
getEncodingValue
(
MO
.
getReg
(
)
)
;
if
(
MO
.
isImm
(
)
)
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
assert
(
MO
.
isExpr
(
)
)
;
assert
(
MO
.
getExpr
(
)
->
getKind
(
)
==
MCExpr
::
SymbolRef
)
;
assert
(
false
&&
"FIXME: not implemented yet"
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .

WebAssembly
WebAssembly
"FIXME: not implemented yet"
0


"attribute %<target%> argument not a string"

"malformed %<target()%> pragma or attribute"

"pragma or attribute %<target(\"%s\")%> is not valid"

"malformed %<target(\"%s\")%> pragma or attribute"

Parse the tree in ARGS that contains the target attribute information and update the global target options space . PRAGMA_OR_ATTR is a string to be used in error messages , specifying whether this is processing a target attribute or a target pragma .


<s> void AArch64TargetLowering :: insertSSPDeclarations ( Module & M ) const { if ( Subtarget -> getTargetTriple ( ) . isWindowsMSVCEnvironment ( ) ) { M . getOrInsertGlobal ( "__security_cookie" , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( "__security_check_cookie" , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: Win64 ) ; F -> addAttribute ( 1 , Attribute :: AttrKind :: InReg ) ; } return ; } TargetLowering :: insertSSPDeclarations ( M ) ; } </s>

Inserts necessary declarations for SSP ( stack protection ) purpose .


"Branch insertion not supported, as MBB info not "

"propagated to OpPhi instructions. Try using "


<s> unsigned getNumFixupKinds ( ) const override { return 0 ; } </s>

Get the number of target specific fixup kinds .


<s> void AMDGPUPassConfig :: addIRPasses ( ) { disablePass ( & StackMapLivenessID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerLegacyPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; addPass ( createAMDGPUOpenCLImageTypeLoweringPass ( ) ) ; const AMDGPUTargetMachine & TM = getAMDGPUTargetMachine ( ) ; if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) { addPass ( createAMDGPUPromoteAlloca ( & TM ) ) ; if ( EnableSROA ) addPass ( createSROAPass ( ) ) ; } addStraightLineScalarOptimizationPasses ( ) ; TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


"After expanding ARM pseudo instructions."

runOnMachineFunction - Emit the function body .


<s> unsigned getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) ) { return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo , Args ) ; } </s>

This is an approximation of reciprocal throughput of a math/logic op .


"Unexpected Kind in getPointerRegClass!"

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> static void s390_register_info_stdarg_fpr ( ) { int i ; int min_fpr ; int max_fpr ; if ( ! cfun -> stdarg || ! TARGET_HARD_FLOAT || ! cfun -> va_list_fpr_size || crtl -> args . info . fprs >= FP_ARG_NUM_REG ) return ; min_fpr = crtl -> args . info . fprs ; max_fpr = min_fpr + cfun -> va_list_fpr_size ; if ( max_fpr > FP_ARG_NUM_REG ) max_fpr = FP_ARG_NUM_REG ; for ( i = min_fpr ; i < max_fpr ; i ++ ) cfun_set_fpr_save ( i + FPR0_REGNUM ) ; } </s>

Set the bits in fpr_bitmap for FPRs which need to be saved due to stdarg . This is a helper routine for s390_register_info .


<s> bool nds32_float_mem_operand_p ( rtx op ) { machine_mode mode = GET_MODE ( op ) ; rtx addr = XEXP ( op , 0 ) ; if ( GET_CODE ( addr ) == SYMBOL_REF || GET_CODE ( addr ) == CONST || GET_CODE ( addr ) == LO_SUM ) return false ; if ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , 0 ) ) == SYMBOL_REF ) return false ; if ( GET_CODE ( XEXP ( addr , 1 ) ) == CONST_INT ) { if ( ( mode == SImode || mode == SFmode ) && NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( XEXP ( addr , 1 ) ) ) && ! satisfies_constraint_Is14 ( XEXP ( addr , 1 ) ) ) return false ; if ( ( mode == DImode || mode == DFmode ) && NDS32_DOUBLE_WORD_ALIGN_P ( INTVAL ( XEXP ( addr , 1 ) ) ) && ! satisfies_constraint_Is14 ( XEXP ( addr , 1 ) ) ) return false ; } } return true ; } </s>

Vaild memory operand for floating-point loads and stores


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants .


<s> enum rtx_code s390_reverse_condition ( machine_mode mode , enum rtx_code code ) { if ( mode == CCVFALLmode || mode == CCVFANYmode ) return reverse_condition_maybe_unordered ( code ) ; else if ( mode == CCVIALLmode || mode == CCVIANYmode ) return reverse_condition ( code ) ; else gcc_unreachable ( ) ; } </s>

Invert the comparison CODE applied to a CC mode . This is only safe if we know whether there result was created by a floating point compare or not . For the CCV modes this is encoded as part of the mode .