<s>
void
LanaiFrameLowering
::
emitPrologue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
assert
(
&
MF
.
front
(
)
==
&
MBB
&&
"Shrink-wrapping not yet supported"
)
;
MachineFrameInfo
&
MFI
=
MF
.
getFrameInfo
(
)
;
const
LanaiInstrInfo
&
LII
=
*
static_cast
<
const
LanaiInstrInfo
*
>
(
STI
.
getInstrInfo
(
)
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
begin
(
)
;
DebugLoc
DL
;
determineFrameLayout
(
MF
)
;
unsigned
StackSize
=
MFI
.
getStackSize
(
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
LII
.
get
(
Lanai
::
SW_RI
)
)
.
addReg
(
Lanai
::
FP
)
.
addReg
(
Lanai
::
SP
)
.
addImm
(
4
)
.
addImm
(
LPAC
::
makePreOp
(
LPAC
::
ADD
)
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
BuildMI
(
MBB
,
MBBI
,
DL
,
LII
.
get
(
Lanai
::
ADD_I_LO
)
,
Lanai
::
FP
)
.
addReg
(
Lanai
::
SP
)
.
addImm
(
8
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
if
(
StackSize
!=
0
)
{
BuildMI
(
MBB
,
MBBI
,
DL
,
LII
.
get
(
Lanai
::
SUB_I_LO
)
,
Lanai
::
SP
)
.
addReg
(
Lanai
::
SP
)
.
addImm
(
StackSize
)
.
setMIFlag
(
MachineInstr
::
FrameSetup
)
;
}
if
(
MFI
.
hasVarSizedObjects
(
)
)
replaceAdjDynAllocPseudo
(
MF
)
;
}
</s>

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SGPR102_SGPR103 ) ; const AMDGPUSubtarget & ST = MF . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: VOLCANIC_ISLANDS ) { reserveRegisterTuples ( Reserved , AMDGPU :: SGPR98_SGPR99 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SGPR100_SGPR101 ) ; if ( ST . isXNACKEnabled ( ) ) reserveRegisterTuples ( Reserved , AMDGPU :: SGPR96_SGPR97 ) ; } if ( ST . hasSGPRInitBug ( ) ) { unsigned NumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; unsigned Limit = AMDGPUSubtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - 4 ; if ( ST . isXNACKEnabled ( ) ) Limit -= 2 ; for ( unsigned i = Limit ; i < NumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void RISCVDAGToDAGISel :: PostprocessISelDAG ( ) { doPeepholeLoadStoreADDI ( ) ; doPeepholeBuildPairF64SplitF64 ( ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> virtual bool SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddrIdx ( Op , Op , Op0 , Op1 ) ) SelectAddrImm ( Op , Op , Op0 , Op1 ) ; break ; case 'o' : if ( ! SelectAddrImm ( Op , Op , Op0 , Op1 ) ) { Op0 = Op ; Op1 = getSmallIPtrImm ( 0 ) ; } break ; case 'v' : SelectAddrIdxOnly ( Op , Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool WebAssembly :: mayThrow ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case WebAssembly :: THROW : case WebAssembly :: THROW_S : case WebAssembly :: RETHROW : case WebAssembly :: RETHROW_S : return true ; } if ( isCallIndirect ( MI ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = MI . getOperand ( getCalleeOpNo ( MI ) ) ; assert ( MO . isGlobal ( ) ) ; const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) return true ; if ( F -> doesNotThrow ( ) ) return false ; if ( F -> getName ( ) == CxaBeginCatchFn || F -> getName ( ) == PersonalityWrapperFn || F -> getName ( ) == ClangCallTerminateFn || F -> getName ( ) == StdTerminateFn ) return false ; return true ; } </s>

Return true if this instruction may throw an exception .

WebAssembly WebAssembly::mayThrow WebAssembly::THROW WebAssembly::THROW_S WebAssembly::RETHROW WebAssembly::RETHROW_S


<s> void X86PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & getX86TargetMachine ( ) ) ) ; TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( TM ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> perm . length ( ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ 0 ] + 1 ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = 1 ; i < nelt ; next ++ , i ++ ) { if ( next == 2 * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == 2 ) && ( d -> vmode != V2DImode ) ) return false ; else next = 0 ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ 0 ] ; if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; if ( d -> vmode == E_DImode ) return false ; emit_insn ( gen_neon_vext ( d -> vmode , d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> virtual const MBlazeRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; PPCSubTarget = & MF . getSubtarget < PPCSubtarget > ( ) ; PPCLowering = PPCSubTarget -> getTargetLowering ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; if ( ! PPCSubTarget -> isSVR4ABI ( ) ) InsertVRSaveCode ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned PPCInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case PPC :: LD : case PPC :: LWZ : case PPC :: LFS : case PPC :: LFD : case PPC :: RESTORE_CR : case PPC :: RESTORE_CRBIT : case PPC :: LVX : case PPC :: LXVD2X : case PPC :: QVLFDX : case PPC :: QVLFSXs : case PPC :: QVLFDXb : case PPC :: RESTORE_VRSAVE : if ( MI . getOperand ( 1 ) . isImm ( ) && ! MI . getOperand ( 1 ) . getImm ( ) && MI . getOperand ( 2 ) . isFI ( ) ) { FrameIndex = MI . getOperand ( 2 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> RegisterBankInfo :: InstructionMapping X86RegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } switch ( Opc ) { case TargetOpcode :: G_ADD : return getOperandsMapping ( MI , false ) ; break ; default : return InstructionMapping { } ; } return InstructionMapping { } ; } </s>

Get the mapping of the different operands of MI on the register bank .


<s>
static
bool
isValid
(
ReachingDefAnalysis
&
RDA
)
{
for
(
auto
&
Block
:
Blocks
)
{
if
(
isEntryPredicatedOnVCTP
(
Block
,
false
)
||
hasImplicitlyValidVPT
(
Block
,
RDA
)
)
continue
;
SmallVectorImpl
<
MachineInstr
*
>
&
Insts
=
Block
.
getInsts
(
)
;
for
(
auto
*
MI
:
Insts
)
{
if
(
isVCTP
(
MI
)
&&
getVPTInstrPredicate
(
*
MI
)
!=
ARMVCC
::
Then
)
return
false
;
if
(
MI
->
getOpcode
(
)
==
ARM
::
MVE_VPST
||
isVectorPredicate
(
MI
)
)
continue
;
if
(
!
isPredicatedOnVCTP
(
MI
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops: Can't convert: "
<<
*
MI
)
;
return
false
;
}
}
}
return
true
;
}
</s>

Returns true if this iterator is still pointing at a valid entry .

ARM
ARMVCC::Then
ARM::MVE_VPST
"ARM Loops: Can't convert: "


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign & VA ) override { markPhysRegUsed ( PhysReg ) ; switch ( VA . getLocInfo ( ) ) { default : { unsigned PhysRegSize = MRI . getTargetRegisterInfo ( ) -> getRegSizeInBits ( PhysReg , MRI ) ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) ; unsigned LocSize = VA . getLocVT ( ) . getSizeInBits ( ) ; if ( PhysRegSize > ValSize && LocSize == ValSize ) { auto Copy = MIRBuilder . buildCopy ( LLT :: scalar ( PhysRegSize ) , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg , Copy ) ; return ; } MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; break ; } case CCValAssign :: LocInfo :: SExt : case CCValAssign :: LocInfo :: ZExt : case CCValAssign :: LocInfo :: AExt : { auto Copy = MIRBuilder . buildCopy ( LLT { VA . getLocVT ( ) } , PhysReg ) ; MIRBuilder . buildTrunc ( ValVReg , Copy ) ; break ; } } } </s>

The specified value has been assigned to a physical register , handle the appropriate COPY ( either to or from ) and mark any relevant uses/defines as needed .


<s> static void expand_save_restore ( struct lm32_frame_info * info , int op ) { unsigned int reg_save_mask = info -> reg_save_mask ; int regno ; HOST_WIDE_INT offset ; rtx insn ; offset = info -> args_size + info -> callee_size ; for ( regno = 0 ; regno <= 31 ; regno ++ ) { if ( ( reg_save_mask & ( 1 << regno ) ) != 0 ) { rtx offset_rtx ; rtx mem ; offset_rtx = GEN_INT ( offset ) ; if ( satisfies_constraint_K ( offset_rtx ) ) { mem = gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , offset_rtx ) ) ; } else { rtx r10 ; r10 = gen_rtx_REG ( word_mode , 10 ) ; insn = emit_move_insn ( r10 , offset_rtx ) ; if ( op == 0 ) RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_add ( r10 , r10 , stack_pointer_rtx ) ; if ( op == 0 ) RTX_FRAME_RELATED_P ( insn ) = 1 ; mem = gen_rtx_MEM ( word_mode , r10 ) ; } if ( op == 0 ) insn = emit_move_insn ( mem , gen_rtx_REG ( word_mode , regno ) ) ; else insn = emit_move_insn ( gen_rtx_REG ( word_mode , regno ) , mem ) ; if ( op == 0 ) RTX_FRAME_RELATED_P ( insn ) = 1 ; offset -= UNITS_PER_WORD ; } } } </s>

Generate and emit RTL to save or restore callee save registers .


<s>
bool
A15SDOptimizer
::
runOnMachineFunction
(
MachineFunction
&
Fn
)
{
const
ARMSubtarget
&
STI
=
Fn
.
getSubtarget
<
ARMSubtarget
>
(
)
;
if
(
!
(
STI
.
isCortexA15
(
)
&&
STI
.
hasNEON
(
)
)
)
return
false
;
TII
=
STI
.
getInstrInfo
(
)
;
TRI
=
STI
.
getRegisterInfo
(
)
;
MRI
=
&
Fn
.
getRegInfo
(
)
;
bool
Modified
=
false
;
DEBUG
(
dbgs
(
)
<<
"Running on function "
<<
Fn
.
getName
(
)
<<
"\n"
)
;
DeadInstr
.
clear
(
)
;
Replacements
.
clear
(
)
;
for
(
MachineFunction
::
iterator
MFI
=
Fn
.
begin
(
)
,
E
=
Fn
.
end
(
)
;
MFI
!=
E
;
++
MFI
)
{
for
(
MachineBasicBlock
::
iterator
MI
=
MFI
->
begin
(
)
,
ME
=
MFI
->
end
(
)
;
MI
!=
ME
;
)
{
Modified
|=
runOnInstruction
(
MI
++
)
;
}
}
for
(
std
::
set
<
MachineInstr
*
>
::
iterator
I
=
DeadInstr
.
begin
(
)
,
E
=
DeadInstr
.
end
(
)
;
I
!=
E
;
++
I
)
{
(
*
I
)
->
eraseFromParent
(
)
;
}
return
Modified
;
}
</s>


<s> static int iamcu_alignment ( tree type , int align ) { enum machine_mode mode ; if ( align < 32 || TYPE_USER_ALIGN ( type ) ) return align ; mode = TYPE_MODE ( strip_array_types ( type ) ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_INT : case MODE_COMPLEX_INT : case MODE_COMPLEX_FLOAT : case MODE_FLOAT : case MODE_DECIMAL_FLOAT : return 32 ; default : return align ; } } </s>

Compute the alignment for a variable for Intel MCU psABI . TYPE is the data type , and ALIGN is the alignment that the object would ordinarily have .


<s>
StringRef
getPassName
(
)
const
override
{
return
"SNES Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s>
const
char
*
mmix_data_section_asm_op
(
)
{
return
"\t.data ! mmixal:= 8H LOC 9B"
;
}
</s>


<s> SDValue R600TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; switch ( N -> getOpcode ( ) ) { case ISD :: FP_ROUND : { SDValue Arg = N -> getOperand ( 0 ) ; if ( Arg . getOpcode ( ) == ISD :: UINT_TO_FP && Arg . getValueType ( ) == MVT :: f64 ) { return DAG . getNode ( ISD :: UINT_TO_FP , N -> getDebugLoc ( ) , N -> getValueType ( 0 ) , Arg . getOperand ( 0 ) ) ; } break ; } } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> void ix86_expand_round ( rtx operand0 , rtx operand1 ) { machine_mode mode = GET_MODE ( operand0 ) ; rtx res , TWO52 , xa , xi , half , mask ; rtx_code_label * label ; const struct real_format * fmt ; REAL_VALUE_TYPE pred_half , half_minus_pred_half ; res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; TWO52 = ix86_gen_TWO52 ( mode ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - 1 , mode ) ; REAL_ARITHMETIC ( pred_half , MINUS_EXPR , dconsthalf , half_minus_pred_half ) ; half = force_reg ( mode , const_double_from_real_value ( pred_half , mode ) ) ; xa = expand_simple_binop ( mode , PLUS , xa , half , NULL_RTX , 0 , OPTAB_DIRECT ) ; xi = gen_reg_rtx ( mode == DFmode ? DImode : SImode ) ; expand_fix ( xi , xa , 0 ) ; expand_float ( xa , xi , 0 ) ; ix86_sse_copysign_to_positive ( res , xa , force_reg ( mode , operand1 ) , mask ) ; emit_label ( label ) ; LABEL_NUSES ( label ) = 1 ; emit_move_insn ( operand0 , res ) ; } </s>

Expand SSE sequence for computing round from OPERAND1 storing into OPERAND0 .


<s> static unsigned getFramePointerSaveOffset ( bool isPPC64 , bool isDarwinABI ) { if ( isDarwinABI ) return isPPC64 ? - 8U : - 4U ; return isPPC64 ? - 8U : - 4U ; } </s>

getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer .


<s>
static
std
::
unique_ptr
<
X86Operand
>
CreateMem
(
unsigned
ModeSize
,
unsigned
SegReg
,
const
MCExpr
*
Disp
,
unsigned
BaseReg
,
unsigned
IndexReg
,
unsigned
Scale
,
SMLoc
StartLoc
,
SMLoc
EndLoc
,
unsigned
Size
=
0
,
unsigned
DefaultBaseReg
=
X86
::
NoRegister
,
StringRef
SymName
=
StringRef
(
)
,
void
*
OpDecl
=
nullptr
,
unsigned
FrontendSize
=
0
,
bool
UseUpRegs
=
false
)
{
assert
(
(
SegReg
||
BaseReg
||
IndexReg
||
DefaultBaseReg
)
&&
"Invalid memory operand!"
)
;
assert
(
(
(
Scale
==
1
||
Scale
==
2
||
Scale
==
4
||
Scale
==
8
)
)
&&
"Invalid scale!"
)
;
auto
Res
=
std
::
make_unique
<
X86Operand
>
(
Memory
,
StartLoc
,
EndLoc
)
;
Res
->
Mem
.
SegReg
=
SegReg
;
Res
->
Mem
.
Disp
=
Disp
;
Res
->
Mem
.
BaseReg
=
BaseReg
;
Res
->
Mem
.
DefaultBaseReg
=
DefaultBaseReg
;
Res
->
Mem
.
IndexReg
=
IndexReg
;
Res
->
Mem
.
Scale
=
Scale
;
Res
->
Mem
.
Size
=
Size
;
Res
->
Mem
.
ModeSize
=
ModeSize
;
Res
->
Mem
.
FrontendSize
=
FrontendSize
;
Res
->
UseUpRegs
=
UseUpRegs
;
Res
->
SymName
=
SymName
;
Res
->
OpDecl
=
OpDecl
;
Res
->
AddressOf
=
false
;
return
Res
;
}
</s>


<s> static bool visium_rtx_costs ( rtx x , machine_mode mode , int outer_code ATTRIBUTE_UNUSED , int opno ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { int code = GET_CODE ( x ) ; switch ( code ) { case CONST_INT : * total = COSTS_N_INSNS ( ! satisfies_constraint_J ( x ) ) ; return true ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( 2 ) ; return true ; case CONST_DOUBLE : { rtx high , low ; split_double ( x , & high , & low ) ; * total = COSTS_N_INSNS ( ! satisfies_constraint_J ( high ) + ! satisfies_constraint_J ( low ) ) ; return true ; } case MULT : * total = COSTS_N_INSNS ( 3 ) ; return false ; case DIV : case UDIV : case MOD : case UMOD : if ( mode == DImode ) * total = COSTS_N_INSNS ( 64 ) ; else * total = COSTS_N_INSNS ( 32 ) ; return false ; case PLUS : case MINUS : case NEG : if ( mode == DImode ) * total = COSTS_N_INSNS ( 2 ) ; else * total = COSTS_N_INSNS ( 1 ) ; return false ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( mode == DImode ) * total = COSTS_N_INSNS ( 3 ) ; else * total = COSTS_N_INSNS ( 1 ) ; return false ; case COMPARE : if ( GET_CODE ( XEXP ( x , 0 ) ) == ZERO_EXTRACT && XEXP ( x , 1 ) == const0_rtx && XEXP ( XEXP ( x , 0 ) , 1 ) == const1_rtx && satisfies_constraint_K ( XEXP ( XEXP ( x , 0 ) , 2 ) ) ) * total = COSTS_N_INSNS ( 1 ) ; return false ; default : return false ; } } </s>

Return the relative costs of expression X .


<s> static scalar_int_mode spu_addr_space_pointer_mode ( addr_space_t addrspace ) { switch ( addrspace ) { case ADDR_SPACE_GENERIC : return ptr_mode ; case ADDR_SPACE_EA : return EAmode ; default : gcc_unreachable ( ) ; } } </s>

Return the appropriate mode for a named address pointer .


<s> bool mcore_gen_compare ( enum rtx_code code , rtx op0 , rtx op1 ) { rtx cc_reg = gen_rtx_REG ( CCmode , CC_REG ) ; bool invert ; if ( GET_CODE ( op1 ) == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( op1 ) ; switch ( code ) { case GTU : if ( val == 0 ) code = NE ; break ; case GT : case LE : if ( CONST_OK_FOR_J ( val + 1 ) ) { op1 = GEN_INT ( val + 1 ) ; code = code == LE ? LT : GE ; } break ; default : break ; } } if ( CONSTANT_P ( op1 ) && GET_CODE ( op1 ) != CONST_INT ) op1 = force_reg ( SImode , op1 ) ; invert = false ; switch ( code ) { case EQ : code = NE ; invert = true ; case NE : if ( GET_CODE ( op1 ) == CONST_INT && ! CONST_OK_FOR_K ( INTVAL ( op1 ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : code = GT ; invert = true ; case GT : if ( GET_CODE ( op1 ) == CONST_INT ) op1 = force_reg ( SImode , op1 ) ; break ; case GE : code = LT ; invert = true ; case LT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 && ! CONST_OK_FOR_J ( INTVAL ( op1 ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case GTU : gcc_assert ( GET_CODE ( op1 ) != CONST_INT || INTVAL ( op1 ) != 0 ) ; code = LEU ; invert = true ; case LEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 ) op1 = force_reg ( SImode , op1 ) ; break ; case LTU : code = GEU ; invert = true ; case GEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != 0 ) op1 = force_reg ( SImode , op1 ) ; break ; default : break ; } emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_fmt_ee ( code , CCmode , op0 , op1 ) ) ) ; return invert ; } </s>

Prepare the operands for a comparison . Return whether the branch/setcc should reverse the operands .


<s> const RegisterBankInfo * getRegBankInfo ( ) const override { return RegBankInfo . get ( ) ; } </s>

If the information for the register banks is available , return it .


<s> bool XCoreInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return false ; if ( ! isUnpredicatedTerminator ( * I ) ) return false ; MachineInstr * LastInst = I ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( * -- I ) ) { if ( IsBRU ( LastInst -> getOpcode ( ) ) ) { TBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } XCore :: CondCode BranchCode = GetCondFromBranchOpc ( LastInst -> getOpcode ( ) ) ; if ( BranchCode == XCore :: COND_INVALID ) return true ; TBB = LastInst -> getOperand ( 1 ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; Cond . push_back ( LastInst -> getOperand ( 0 ) ) ; return false ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( * -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; XCore :: CondCode BranchCode = GetCondFromBranchOpc ( SecondLastOpc ) ; if ( BranchCode != XCore :: COND_INVALID && IsBRU ( LastInst -> getOpcode ( ) ) ) { TBB = SecondLastInst -> getOperand ( 1 ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( 0 ) ) ; FBB = LastInst -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( IsBRU ( SecondLastInst -> getOpcode ( ) ) && IsBRU ( LastInst -> getOpcode ( ) ) ) { TBB = SecondLastInst -> getOperand ( 0 ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( IsBR_JT ( SecondLastInst -> getOpcode ( ) ) && IsBRU ( LastInst -> getOpcode ( ) ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return true ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> static unsigned getBasePointerSaveOffset ( bool isPPC64 , bool isDarwinABI ) { if ( isDarwinABI ) return isPPC64 ? - 16U : - 8U ; return isPPC64 ? - 16U : - 8U ; } </s>

getBasePointerSaveOffset - Return the previous frame offset to save the base pointer .


<s> bool isConditionalBranch ( MCInst const & Inst ) const override { return MCInstrAnalysis :: isConditionalBranch ( Inst ) ; } </s>

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block .


"LEG DAG->DAG Pattern Instruction Selection"


<s>
bool
ARMTargetLowering
::
ExpandInlineAsm
(
CallInst
*
CI
)
const
{
if
(
!
Subtarget
->
hasV6Ops
(
)
)
return
false
;
InlineAsm
*
IA
=
cast
<
InlineAsm
>
(
CI
->
getCalledOperand
(
)
)
;
std
::
string
AsmStr
=
IA
->
getAsmString
(
)
;
SmallVector
<
StringRef
,
4
>
AsmPieces
;
SplitString
(
AsmStr
,
AsmPieces
,
";\n"
)
;
switch
(
AsmPieces
.
size
(
)
)
{
default
:
return
false
;
case
1
:
AsmStr
=
std
::
string
(
AsmPieces
[
0
]
)
;
AsmPieces
.
clear
(
)
;
SplitString
(
AsmStr
,
AsmPieces
,
" \t,"
)
;
if
(
AsmPieces
.
size
(
)
==
3
&&
AsmPieces
[
0
]
==
"rev"
&&
AsmPieces
[
1
]
==
"$0"
&&
AsmPieces
[
2
]
==
"$1"
&&
IA
->
getConstraintString
(
)
.
compare
(
0
,
4
,
"=l,l"
)
==
0
)
{
IntegerType
*
Ty
=
dyn_cast
<
IntegerType
>
(
CI
->
getType
(
)
)
;
if
(
Ty
&&
Ty
->
getBitWidth
(
)
==
32
)
return
IntrinsicLowering
::
LowerToByteSwap
(
CI
)
;
}
break
;
}
return
false
;
}
</s>

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to .


"AArch64 pseudo instruction expansion pass"


"Don't know how to assign a value to an address yet"

An overload which takes an ArgInfo if additional information about the arg is needed .


<s> TargetLoweringBase :: LegalizeTypeAction HexagonTargetLowering :: getPreferredVectorAction ( MVT VT ) const { unsigned VecLen = VT . getVectorMinNumElements ( ) ; MVT ElemTy = VT . getVectorElementType ( ) ; if ( VecLen == 1 || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned Action = getPreferredHvxVectorAction ( VT ) ; if ( Action != ~ 0u ) return static_cast < TargetLoweringBase :: LegalizeTypeAction > ( Action ) ; } if ( ElemTy == MVT :: i1 ) return TargetLoweringBase :: TypeWidenVector ; return TargetLoweringBase :: TypeSplitVector ; } </s>

Customize the preferred legalization strategy for certain types .


"rs6000_can_inline_p:, caller %s, callee %s, %s inline\n"

Hook to determine if one function can safely inline another .


"RegScavenger required for long branching"

"new block should be inserted for expanding unconditional branch"

Insert an unconditional indirect branch at the end of MBB to NewDestBB .


<s> void neon_pairwise_reduce ( rtx op0 , rtx op1 , machine_mode mode , rtx ( * reduc ) ( rtx , rtx , rtx ) ) { unsigned int i , parts = GET_MODE_SIZE ( mode ) / GET_MODE_UNIT_SIZE ( mode ) ; rtx tmpsum = op1 ; for ( i = parts / 2 ; i >= 1 ; i /= 2 ) { rtx dest = ( i == 1 ) ? op0 : gen_reg_rtx ( mode ) ; emit_insn ( reduc ( dest , tmpsum , tmpsum ) ) ; tmpsum = dest ; } } </s>

Output a sequence of pairwise operations to implement a reduction . NOTE : We do `` too much work '' here , because pairwise operations work on two registers-worth of operands in one go . Unfortunately we ca n't exploit those extra calculations to do the full operation in fewer steps , I do n't think . Although all vector elements of the result but the first are ignored , we actually calculate the same result in each of the elements . An alternative such as initially loading a vector with zero to use as each of the second operands would use up an additional register and take an extra instruction , for no particular gain .


<s>
bool
X86TargetLowering
::
lowerInterleavedStore
(
StoreInst
*
SI
,
ShuffleVectorInst
*
SVI
,
unsigned
Factor
)
const
{
assert
(
Factor
>=
2
&&
Factor
<=
getMaxSupportedInterleaveFactor
(
)
&&
"Invalid interleave factor"
)
;
assert
(
SVI
->
getType
(
)
->
getNumElements
(
)
%
Factor
==
0
&&
"Invalid interleaved store"
)
;
SmallVector
<
unsigned
,
4
>
Indices
;
auto
Mask
=
SVI
->
getShuffleMask
(
)
;
for
(
unsigned
i
=
0
;
i
<
Factor
;
i
++
)
Indices
.
push_back
(
Mask
[
i
]
)
;
ArrayRef
<
ShuffleVectorInst
*
>
Shuffles
=
makeArrayRef
(
SVI
)
;
IRBuilder
<
>
Builder
(
SI
)
;
X86InterleavedAccessGroup
Grp
(
SI
,
Shuffles
,
Indices
,
Factor
,
Subtarget
,
Builder
)
;
return
Grp
.
isSupported
(
)
&&
Grp
.
lowerIntoOptimizedSequence
(
)
;
}
</s>

Lower interleaved store ( s ) into target specific instructions/intrinsics .


<s> int compute_frame_size ( poly_int64 size , long * p_reg_saved ) { return ( size + compute_register_save_size ( p_reg_saved ) + crtl -> outgoing_args_size ) ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> static int aarch64_reassociation_width ( unsigned opc ATTRIBUTE_UNUSED , enum machine_mode mode ) { if ( VECTOR_MODE_P ( mode ) ) return aarch64_tune_params . vec_reassoc_width ; if ( INTEGRAL_MODE_P ( mode ) ) return aarch64_tune_params . int_reassoc_width ; if ( FLOAT_MODE_P ( mode ) ) return aarch64_tune_params . fp_reassoc_width ; return 1 ; } </s>

Return the reassociation width of treeop OPC with mode MODE .


<s> EVT MipsTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Subtarget . hasMips64 ( ) ) return MVT :: i64 ; return MVT :: i32 ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> static rtx mn10300_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; rtx result = NULL_RTX ; int size ; int nregs = 2 ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; cum -> nbytes = ( cum -> nbytes + 3 ) & ~ 3 ; if ( cum -> nbytes > nregs * UNITS_PER_WORD ) return result ; if ( type == NULL_TREE && cum -> nbytes + size > nregs * UNITS_PER_WORD ) return result ; switch ( cum -> nbytes / UNITS_PER_WORD ) { case 0 : result = gen_rtx_REG ( mode , FIRST_ARGUMENT_REGNUM ) ; break ; case 1 : result = gen_rtx_REG ( mode , FIRST_ARGUMENT_REGNUM + 1 ) ; break ; default : break ; } return result ; } </s>

Return an RTX to represent where a value with mode MODE will be returned from a function . If the result is NULL_RTX , the argument is pushed .


"loadRegFromStackSlot didn't insert any code!"

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
bool
PPCInstrInfo
::
isReallyTriviallyReMaterializable
(
const
MachineInstr
&
MI
,
AliasAnalysis
*
AA
)
const
{
switch
(
MI
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Unknown rematerializable operation!"
)
;
break
;
case
PPC
::
LI
:
case
PPC
::
LI8
:
case
PPC
::
LIS
:
case
PPC
::
LIS8
:
case
PPC
::
QVGPCI
:
case
PPC
::
ADDIStocHA8
:
case
PPC
::
ADDItocL
:
case
PPC
::
LOAD_STACK_GUARD
:
case
PPC
::
XXLXORz
:
case
PPC
::
XXLXORspz
:
case
PPC
::
XXLXORdpz
:
case
PPC
::
XXLEQVOnes
:
case
PPC
::
V_SET0B
:
case
PPC
::
V_SET0H
:
case
PPC
::
V_SET0
:
case
PPC
::
V_SETALLONESB
:
case
PPC
::
V_SETALLONESH
:
case
PPC
::
V_SETALLONES
:
case
PPC
::
CRSET
:
case
PPC
::
CRUNSET
:
return
true
;
}
return
false
;
}
</s>

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set , this hook lets the target specify whether the instruction is actually trivially rematerializable , taking into consideration its operands .


<s> static bool valid_src_p ( rtx src , rtx_insn * insn , struct loop * loop , bool * pre_post , rtx * base , rtx * offset , bool load_pair ) { subrtx_var_iterator :: array_type array ; rtx x = NULL_RTX ; FOR_EACH_SUBRTX_VAR ( iter , array , src , NONCONST ) if ( MEM_P ( * iter ) ) { x = * iter ; break ; } if ( ! x ) return false ; struct aarch64_address_info addr ; machine_mode mode = GET_MODE ( x ) ; if ( ! aarch64_classify_address ( & addr , XEXP ( x , 0 ) , mode , true ) ) return false ; unsigned regno = REGNO ( addr . base ) ; if ( global_regs [ regno ] || fixed_regs [ regno ] ) return false ; if ( addr . type == ADDRESS_REG_WB ) { unsigned code = GET_CODE ( XEXP ( x , 0 ) ) ; * pre_post = true ; * base = addr . base ; if ( code == PRE_MODIFY || code == POST_MODIFY ) * offset = addr . offset ; else { unsigned int_offset = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( load_pair && ( code == POST_INC || code == POST_DEC ) ) int_offset *= 2 ; * offset = GEN_INT ( int_offset ) ; } return true ; } else if ( addr . type == ADDRESS_REG_IMM || addr . type == ADDRESS_REG_REG ) { if ( ! iv_p ( insn , addr . base , loop ) ) return false ; * base = addr . base ; * offset = addr . offset ; return true ; } return false ; } </s>

Return true if SRC is a strided load in the LOOP , false otherwise . If it is a strided load , set the BASE and OFFSET . Also , if this is a pre/post increment load , set PRE_POST to true .


<s> void GCNHazardRecognizer :: AdvanceCycle ( ) { if ( ! CurrCycleInstr ) { EmittedInstrs . push_front ( nullptr ) ; return ; } if ( CurrCycleInstr -> isMetaInstruction ( ) ) { CurrCycleInstr = nullptr ; return ; } if ( CurrCycleInstr -> isBundle ( ) ) { processBundle ( ) ; return ; } unsigned NumWaitStates = TII . getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = 1 , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ; CurrCycleInstr = nullptr ; } </s>

AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled can not issue in the current cycle , either because of latency or resource conflicts .


"sret virtual register not created in the entry block"

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> static void riscv_conditional_register_usage ( void ) { if ( ! TARGET_HARD_FLOAT ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) fixed_regs [ regno ] = call_used_regs [ regno ] = 1 ; } if ( UNITS_PER_FP_ARG == 0 ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = 1 ; } } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Patmos Delay Slot Filler"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> unsigned AVRInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return 0 ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const AVRTargetMachine & TM = static_cast < const AVRTargetMachine & > ( MF . getTarget ( ) ) ; const AVRSubtarget & STI = MF . getSubtarget < AVRSubtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s> bool CAHPInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { TBB = FBB = nullptr ; Cond . clear ( ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return false ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = 0 ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > 2 ) return true ; if ( NumTerminators == 1 && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = I -> getOperand ( 0 ) . getMBB ( ) ; return false ; } if ( NumTerminators == 1 && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == 2 && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = I -> getOperand ( 0 ) . getMBB ( ) ; return false ; } return true ; } </s>

analyzeBranch - Analyze the branching code at the end of MBB , returning true if it can not be understood ( e.g .


<s> bool MipsTargetObjectFile :: IsConstantInSmallSection ( const DataLayout & DL , const Constant * CN , const TargetMachine & TM ) const { return ( static_cast < const MipsTargetMachine & > ( TM ) . getSubtargetImpl ( ) -> useSmallSection ( ) && LocalSData && IsInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ) ; } </s>

Return true if this constant should be placed into small data section .


<s> static unsigned estimateStackSize ( MachineFunction & MF ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; const TargetRegisterInfo * RegInfo = MF . getTarget ( ) . getRegisterInfo ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; int Offset = 0 ; for ( int i = MFI -> getObjectIndexBegin ( ) ; i != 0 ; ++ i ) { int FixedOff = - MFI -> getObjectOffset ( i ) ; if ( FixedOff > Offset ) Offset = FixedOff ; } for ( unsigned i = 0 , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( MFI -> isDeadObjectIndex ( i ) ) continue ; Offset += MFI -> getObjectSize ( i ) ; unsigned Align = MFI -> getObjectAlignment ( i ) ; Offset = ( Offset + Align - 1 ) / Align * Align ; MaxAlign = std :: max ( Align , MaxAlign ) ; } if ( MFI -> adjustsStack ( ) && TFI -> hasReservedCallFrame ( MF ) ) Offset += MFI -> getMaxCallFrameSize ( ) ; unsigned StackAlign ; if ( MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) || ( RegInfo -> needsStackRealignment ( MF ) && MFI -> getObjectIndexEnd ( ) != 0 ) ) StackAlign = TFI -> getStackAlignment ( ) ; else StackAlign = TFI -> getTransientStackAlignment ( ) ; StackAlign = std :: max ( StackAlign , MaxAlign ) ; unsigned AlignMask = StackAlign - 1 ; Offset = ( Offset + AlignMask ) & ~ uint64_t ( AlignMask ) ; return ( unsigned ) Offset ; } </s>

Estimate and return the size of the stack frame .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"AMDGPU Promote Alloca"
;
}
</s>


<s> const TargetRegisterClass * SPURegisterInfo :: getPointerRegClass ( unsigned Kind ) const { return & SPU :: R32CRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


"WebAssembly hasn't implemented computed gotos"

"WebAssembly hasn't implemented __builtin_return_address"

LowerOperation - Provide custom lowering hooks for some operations .


"Requesting 64-bit offset in 32-bit immediate!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> ScheduleHazardRecognizer :: HazardType GCNHazardRecognizer :: getHazardType ( SUnit * SU , int Stalls ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( SIInstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > 0 ) return NoopHazard ; if ( ( SIInstrInfo :: isVMEM ( * MI ) || SIInstrInfo :: isFLAT ( * MI ) ) && checkVMEMHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isVALU ( * MI ) && checkVALUHazards ( MI ) > 0 ) return NoopHazard ; if ( SIInstrInfo :: isDPP ( * MI ) && checkDPPHazards ( MI ) > 0 ) return NoopHazard ; if ( isDivFMas ( MI -> getOpcode ( ) ) && checkDivFMasHazards ( MI ) > 0 ) return NoopHazard ; if ( isRWLane ( MI -> getOpcode ( ) ) && checkRWLaneHazards ( MI ) > 0 ) return NoopHazard ; if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > 0 ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > 0 ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > 0 ) return NoopHazard ; if ( checkAnyInstHazards ( MI ) > 0 ) return NoopHazard ; return NoHazard ; } </s>

getHazardType - Return the hazard type of emitting this node .


<s> void AArch64Subtarget :: mirFileLoaded ( MachineFunction & MF ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) ) MFI . computeMaxCallFrameSize ( MF ) ; } </s>

This is called after a .mir file was loaded .


<s> void setPredicate ( unsigned pred ) { InstrPred . clear ( ) ; for ( auto instr_iter = MBB -> instr_begin ( ) , end = MBB -> instr_end ( ) ; instr_iter != end ; instr_iter ++ ) { MachineInstr * instr = & ( * instr_iter ) ; assert ( InstrPred . find ( instr ) == InstrPred . end ( ) ) ; InstrPred . insert ( std :: make_pair ( instr , pred ) ) ; } for ( auto iter = Successors . begin ( ) , end = Successors . end ( ) ; iter != end ; iter ++ ) { iter -> second = pred ; } } </s>

Set the predicate for this instruction to the specified value .


<s> static rtx aarch64_sve_move_pred_via_while ( rtx target , machine_mode mode , unsigned int vl ) { rtx limit = force_reg ( DImode , gen_int_mode ( vl , DImode ) ) ; target = aarch64_target_reg ( target , mode ) ; emit_insn ( gen_while ( UNSPEC_WHILELO , DImode , mode , target , const0_rtx , limit ) ) ; return target ; } </s>

Use WHILE to set a predicate register of mode MODE in which the first VL bits are set and the rest are clear . Use TARGET for the register if it 's nonnull and convenient .


<s>
void
AArch64Operand
::
print
(
raw_ostream
&
OS
)
const
{
switch
(
Kind
)
{
case
k_FPImm
:
OS
<<
"<fpimm "
<<
getFPImm
(
)
.
bitcastToAPInt
(
)
.
getZExtValue
(
)
;
if
(
!
getFPImmIsExact
(
)
)
OS
<<
" (inexact)"
;
OS
<<
">"
;
break
;
case
k_Barrier
:
{
StringRef
Name
=
getBarrierName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<barrier "
<<
Name
<<
">"
;
else
OS
<<
"<barrier invalid #"
<<
getBarrier
(
)
<<
">"
;
break
;
}
case
k_Immediate
:
OS
<<
*
getImm
(
)
;
break
;
case
k_ShiftedImm
:
{
unsigned
Shift
=
getShiftedImmShift
(
)
;
OS
<<
"<shiftedimm "
;
OS
<<
*
getShiftedImmVal
(
)
;
OS
<<
", lsl #"
<<
AArch64_AM
::
getShiftValue
(
Shift
)
<<
">"
;
break
;
}
case
k_CondCode
:
OS
<<
"<condcode "
<<
getCondCode
(
)
<<
">"
;
break
;
case
k_VectorList
:
{
OS
<<
"<vectorlist "
;
unsigned
Reg
=
getVectorListStart
(
)
;
for
(
unsigned
i
=
0
,
e
=
getVectorListCount
(
)
;
i
!=
e
;
++
i
)
OS
<<
Reg
+
i
<<
" "
;
OS
<<
">"
;
break
;
}
case
k_VectorIndex
:
OS
<<
"<vectorindex "
<<
getVectorIndex
(
)
<<
">"
;
break
;
case
k_SysReg
:
OS
<<
"<sysreg: "
<<
getSysReg
(
)
<<
'>'
;
break
;
case
k_Token
:
OS
<<
"'"
<<
getToken
(
)
<<
"'"
;
break
;
case
k_SysCR
:
OS
<<
"c"
<<
getSysCR
(
)
;
break
;
case
k_Prefetch
:
{
StringRef
Name
=
getPrefetchName
(
)
;
if
(
!
Name
.
empty
(
)
)
OS
<<
"<prfop "
<<
Name
<<
">"
;
else
OS
<<
"<prfop invalid #"
<<
getPrefetch
(
)
<<
">"
;
break
;
}
case
k_PSBHint
:
OS
<<
getPSBHintName
(
)
;
break
;
case
k_Register
:
OS
<<
"<register "
<<
getReg
(
)
<<
">"
;
if
(
!
getShiftExtendAmount
(
)
&&
!
hasShiftExtendAmount
(
)
)
break
;
LLVM_FALLTHROUGH
;
case
k_ShiftExtend
:
OS
<<
"<"
<<
AArch64_AM
::
getShiftExtendName
(
getShiftExtendType
(
)
)
<<
" #"
<<
getShiftExtendAmount
(
)
;
if
(
!
hasShiftExtendAmount
(
)
)
OS
<<
"<imp>"
;
OS
<<
'>'
;
break
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .

AArch64
AArch64
"<fpimm "
" (inexact)"
">"
"<barrier "
">"
"<barrier invalid #"
">"
"<shiftedimm "
", lsl #"
AArch64_AM::getShiftValue
">"
"<condcode "
">"
"<vectorlist "
0
" "
">"
"<vectorindex "
">"
"<sysreg: "
"'"
"'"
"c"
"<prfop "
">"
"<prfop invalid #"
">"
"<register "
">"
"<"
AArch64_AM::getShiftExtendName
" #"
"<imp>"


<s>
const
char
*
output_move_simode_const
(
rtx
*
operands
)
{
if
(
operands
[
1
]
==
const0_rtx
&&
(
DATA_REG_P
(
operands
[
0
]
)
||
GET_CODE
(
operands
[
0
]
)
==
MEM
)
&&
(
(
TARGET_68020
||
TARGET_COLDFIRE
)
||
!
(
GET_CODE
(
operands
[
0
]
)
==
MEM
&&
MEM_VOLATILE_P
(
operands
[
0
]
)
)
)
)
return
"clr%.l %0"
;
else
if
(
(
GET_MODE
(
operands
[
0
]
)
==
SImode
)
&&
valid_mov3q_const
(
operands
[
1
]
)
)
return
"mov3q%.l %1,%0"
;
else
if
(
operands
[
1
]
==
const0_rtx
&&
ADDRESS_REG_P
(
operands
[
0
]
)
)
return
"sub%.l %0,%0"
;
else
if
(
DATA_REG_P
(
operands
[
0
]
)
)
return
output_move_const_into_data_reg
(
operands
)
;
else
if
(
ADDRESS_REG_P
(
operands
[
0
]
)
&&
INTVAL
(
operands
[
1
]
)
<
0x8000
&&
INTVAL
(
operands
[
1
]
)
>=
0x8000
)
{
if
(
valid_mov3q_const
(
operands
[
1
]
)
)
return
"mov3q%.l %1,%0"
;
return
"move%.w %1,%0"
;
}
else
if
(
GET_CODE
(
operands
[
0
]
)
==
MEM
&&
GET_CODE
(
XEXP
(
operands
[
0
]
,
0
)
)
==
PRE_DEC
&&
REGNO
(
XEXP
(
XEXP
(
operands
[
0
]
,
0
)
,
0
)
)
==
STACK_POINTER_REGNUM
&&
INTVAL
(
operands
[
1
]
)
<
0x8000
&&
INTVAL
(
operands
[
1
]
)
>=
0x8000
)
{
if
(
valid_mov3q_const
(
operands
[
1
]
)
)
return
"mov3q%.l %1,%-"
;
return
"pea %a1"
;
}
return
"move%.l %1,%0"
;
}
</s>

Return an instruction to move CONST_INT OPERANDS [ 1 ] into OPERANDS [ 0 ] . I is the value of OPERANDS [ 1 ] .


"Unexpected combination of stack realignment and varsized objects"

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> void expand_fusion_gpr_load ( rtx * operands ) { rtx addis_value = operands [ 1 ] ; rtx target = operands [ 2 ] ; rtx orig_mem = operands [ 3 ] ; rtx new_addr , new_mem , orig_addr , offset ; enum rtx_code plus_or_lo_sum ; machine_mode target_mode = GET_MODE ( target ) ; machine_mode extend_mode = target_mode ; machine_mode ptr_mode = Pmode ; enum rtx_code extend = UNKNOWN ; if ( GET_CODE ( orig_mem ) == ZERO_EXTEND || ( TARGET_P8_FUSION_SIGN && GET_CODE ( orig_mem ) == SIGN_EXTEND ) ) { extend = GET_CODE ( orig_mem ) ; orig_mem = XEXP ( orig_mem , 0 ) ; target_mode = GET_MODE ( orig_mem ) ; } gcc_assert ( MEM_P ( orig_mem ) ) ; orig_addr = XEXP ( orig_mem , 0 ) ; plus_or_lo_sum = GET_CODE ( orig_addr ) ; gcc_assert ( plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM ) ; offset = XEXP ( orig_addr , 1 ) ; new_addr = gen_rtx_fmt_ee ( plus_or_lo_sum , ptr_mode , addis_value , offset ) ; new_mem = replace_equiv_address_nv ( orig_mem , new_addr , false ) ; if ( extend != UNKNOWN ) new_mem = gen_rtx_fmt_e ( ZERO_EXTEND , extend_mode , new_mem ) ; new_mem = gen_rtx_UNSPEC ( extend_mode , gen_rtvec ( 1 , new_mem ) , UNSPEC_FUSION_GPR ) ; emit_insn ( gen_rtx_SET ( target , new_mem ) ) ; if ( extend == SIGN_EXTEND ) { int sub_off = ( ( BYTES_BIG_ENDIAN ) ? GET_MODE_SIZE ( extend_mode ) - GET_MODE_SIZE ( target_mode ) : 0 ) ; rtx sign_reg = simplify_subreg ( target_mode , target , extend_mode , sub_off ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_SIGN_EXTEND ( extend_mode , sign_reg ) ) ) ; } return ; } </s>

During the peephole2 pass , adjust and expand the insns for a load fusion sequence . We adjust the addis register to use the target register . If the load sign extends , we adjust the code to do the zero extending load , and an explicit sign extension later since the fusion only covers zero extending loads . The operands are : operands [ 0 ] register set with addis ( to be replaced with target ) operands [ 1 ] value set via addis operands [ 2 ] target register being loaded operands [ 3 ] D-form memory reference using operands [ 0 ] .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Sparc Assembly Printer"
;
}
</s>


<s>
void
AVRInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
const
DebugLoc
&
DL
,
MCRegister
DestReg
,
MCRegister
SrcReg
,
bool
KillSrc
)
const
{
const
AVRSubtarget
&
STI
=
MBB
.
getParent
(
)
->
getSubtarget
<
AVRSubtarget
>
(
)
;
const
AVRRegisterInfo
&
TRI
=
*
STI
.
getRegisterInfo
(
)
;
unsigned
Opc
;
if
(
AVR
::
DREGSRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
STI
.
hasMOVW
(
)
&&
AVR
::
DREGSMOVWRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AVR
::
MOVWRdRr
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
Register
DestLo
,
DestHi
,
SrcLo
,
SrcHi
;
TRI
.
splitReg
(
DestReg
,
DestLo
,
DestHi
)
;
TRI
.
splitReg
(
SrcReg
,
SrcLo
,
SrcHi
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AVR
::
MOVRdRr
)
,
DestLo
)
.
addReg
(
SrcLo
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
AVR
::
MOVRdRr
)
,
DestHi
)
.
addReg
(
SrcHi
,
getKillRegState
(
KillSrc
)
)
;
}
}
else
{
if
(
AVR
::
GPR8RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
Opc
=
AVR
::
MOVRdRr
;
}
else
if
(
SrcReg
==
AVR
::
SP
&&
AVR
::
DREGSRegClass
.
contains
(
DestReg
)
)
{
Opc
=
AVR
::
SPREAD
;
}
else
if
(
DestReg
==
AVR
::
SP
&&
AVR
::
DREGSRegClass
.
contains
(
SrcReg
)
)
{
Opc
=
AVR
::
SPWRITE
;
}
else
{
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
}
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
}
</s>

AVR
AVR
AVR
AVR
AVR
AVR::DREGSRegClass
AVR::DREGSMOVWRegClass
AVR::MOVWRdRr
AVR::MOVRdRr
AVR::MOVRdRr
AVR::GPR8RegClass
AVR::MOVRdRr
AVR::SP
AVR::DREGSRegClass
AVR::SPREAD
AVR::SP
AVR::DREGSRegClass
AVR::SPWRITE
"Impossible reg-to-reg copy"


<s> static unsigned int ATTRIBUTE_UNUSED x86_64_elf_section_type_flags ( tree decl , const char * name , int reloc ) { unsigned int flags = default_section_type_flags ( decl , name , reloc ) ; if ( ix86_in_large_data_p ( decl ) ) flags |= SECTION_LARGE ; if ( decl == NULL_TREE && ( strcmp ( name , ".ldata.rel.ro" ) == 0 || strcmp ( name , ".ldata.rel.ro.local" ) == 0 ) ) flags |= SECTION_RELRO ; if ( strcmp ( name , ".lbss" ) == 0 || strncmp ( name , ".lbss." , 5 ) == 0 || strncmp ( name , ".gnu.linkonce.lb." , 16 ) == 0 ) flags |= SECTION_BSS ; return flags ; } </s>

Select a set of attributes for section NAME based on the properties of DECL and whether or not RELOC indicates that DECL 's initializer might contain runtime relocations .


<s> enum aarch64_symbol_type aarch64_classify_tls_symbol ( rtx x ) { enum tls_model tls_kind = tls_symbolic_operand_type ( x ) ; switch ( tls_kind ) { case TLS_MODEL_GLOBAL_DYNAMIC : case TLS_MODEL_LOCAL_DYNAMIC : return TARGET_TLS_DESC ? SYMBOL_SMALL_TLSDESC : SYMBOL_SMALL_TLSGD ; case TLS_MODEL_INITIAL_EXEC : switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : case AARCH64_CMODEL_TINY_PIC : return SYMBOL_TINY_TLSIE ; default : return SYMBOL_SMALL_TLSIE ; } case TLS_MODEL_LOCAL_EXEC : if ( aarch64_tls_size == 12 ) return SYMBOL_TLSLE12 ; else if ( aarch64_tls_size == 24 ) return SYMBOL_TLSLE24 ; else if ( aarch64_tls_size == 32 ) return SYMBOL_TLSLE32 ; else if ( aarch64_tls_size == 48 ) return SYMBOL_TLSLE48 ; else gcc_unreachable ( ) ; case TLS_MODEL_EMULATED : case TLS_MODEL_NONE : return SYMBOL_FORCE_TO_MEM ; default : gcc_unreachable ( ) ; } } </s>

Classify a TLS symbol into one of the TLS kinds .


<s> bool enableInterleavedAccessVectorization ( ) { return true ; } </s>

Enable matching of interleaved access groups .


<s> void mips_final_prescan_insn ( rtx_insn * insn , rtx * opvec , int noperands ) { if ( mips_need_noat_wrapper_p ( insn , opvec , noperands ) ) mips_push_asm_switch ( & mips_noat ) ; } </s>


<s> static pad_direction spu_function_arg_padding ( machine_mode , const_tree ) { return PAD_UPWARD ; } </s>


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
Register
&&
"Invalid access!"
)
;
return
Reg
.
RegNo
;
}
</s>

Returns the register associated with this edge .


<s> static rtx frv_legitimize_tls_address ( rtx addr , enum tls_model model ) { rtx dest , tp = gen_rtx_REG ( Pmode , 29 ) ; rtx picreg = get_hard_reg_initial_val ( Pmode , 15 ) ; switch ( model ) { case TLS_MODEL_INITIAL_EXEC : if ( flag_pic == 1 ) { dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_load_gottlsoff12 ( dest , addr , picreg ) ) ; dest = gen_rtx_PLUS ( Pmode , tp , dest ) ; } else { rtx tmp = gen_reg_rtx ( Pmode ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tlsoff_hilo ( tmp , addr , GEN_INT ( R_FRV_GOTTLSOFF_HI ) ) ) ; emit_insn ( gen_tls_tlsoff_ld ( dest , picreg , tmp , addr ) ) ; dest = gen_rtx_PLUS ( Pmode , tp , dest ) ; } break ; case TLS_MODEL_LOCAL_DYNAMIC : { rtx reg , retval ; if ( TARGET_INLINE_PLT ) retval = gen_inlined_tls_plt ( GEN_INT ( 0 ) ) ; else { retval = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_call_gettlsoff ( retval , GEN_INT ( 0 ) , picreg ) ) ; } reg = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , gen_rtx_PLUS ( Pmode , retval , tp ) ) ) ; dest = gen_tlsmoff ( addr , reg ) ; break ; } case TLS_MODEL_LOCAL_EXEC : dest = gen_tlsmoff ( addr , gen_rtx_REG ( Pmode , 29 ) ) ; break ; case TLS_MODEL_GLOBAL_DYNAMIC : { rtx retval ; if ( TARGET_INLINE_PLT ) retval = gen_inlined_tls_plt ( addr ) ; else { retval = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_call_gettlsoff ( retval , addr , picreg ) ) ; } dest = gen_rtx_PLUS ( Pmode , retval , tp ) ; break ; } default : gcc_unreachable ( ) ; } return dest ; } </s>


<s> static rtx mn10300_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED ) { if ( flag_pic && ! mn10300_legitimate_pic_operand_p ( x ) ) x = mn10300_legitimize_pic_address ( oldx , NULL_RTX ) ; if ( GET_CODE ( x ) == PLUS && mn10300_symbolic_operand ( XEXP ( x , 1 ) , VOIDmode ) ) { rtx regx1 , regy1 , regy2 , y ; y = XEXP ( x , 1 ) ; if ( GET_CODE ( y ) == CONST ) y = XEXP ( y , 0 ) ; if ( GET_CODE ( y ) == PLUS || GET_CODE ( y ) == MINUS ) { regx1 = force_reg ( Pmode , force_operand ( XEXP ( x , 0 ) , 0 ) ) ; regy1 = force_reg ( Pmode , force_operand ( XEXP ( y , 0 ) , 0 ) ) ; regy2 = force_reg ( Pmode , force_operand ( XEXP ( y , 1 ) , 0 ) ) ; regx1 = force_reg ( Pmode , gen_rtx_fmt_ee ( GET_CODE ( y ) , Pmode , regx1 , regy2 ) ) ; return force_reg ( Pmode , gen_rtx_PLUS ( Pmode , regx1 , regy1 ) ) ; } } return x ; } </s>

Try machine dependent ways of modifying an illegitimate address to be legitimate . If we find one , return the new valid address . This macro is used in only one place : ` memory_address ' in explow.cc . OLDX is the address as it was before break_out_memory_refs was called . In some cases it is useful to look at this to decide what needs to be done . Normally it is always safe for this macro to do nothing . It exists to recognize opportunities to optimize the output . But on a few ports with segmented architectures and indexed addressing ( mn10300 , hppa ) it is used to rewrite certain problematical addresses .


<s> bool HexagonVExtract :: runOnMachineFunction ( MachineFunction & MF ) { HST = & MF . getSubtarget < HexagonSubtarget > ( ) ; HII = HST -> getInstrInfo ( ) ; const auto & HRI = * HST -> getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; std :: map < unsigned , SmallVector < MachineInstr * , 4 >> VExtractMap ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { unsigned Opc = MI . getOpcode ( ) ; if ( Opc != Hexagon :: V6_extractw ) continue ; unsigned VecR = MI . getOperand ( 1 ) . getReg ( ) ; VExtractMap [ VecR ] . push_back ( & MI ) ; } } for ( auto & P : VExtractMap ) { unsigned VecR = P . first ; if ( P . second . size ( ) <= VExtractThreshold ) continue ; const auto & VecRC = * MRI . getRegClass ( VecR ) ; int FI = MFI . CreateSpillStackObject ( HRI . getSpillSize ( VecRC ) , HRI . getSpillAlignment ( VecRC ) ) ; MachineInstr * DefI = MRI . getVRegDef ( VecR ) ; MachineBasicBlock :: iterator At = std :: next ( DefI -> getIterator ( ) ) ; MachineBasicBlock & DefB = * DefI -> getParent ( ) ; unsigned StoreOpc = VecRC . getID ( ) == Hexagon :: HvxVRRegClassID ? Hexagon :: V6_vS32b_ai : Hexagon :: PS_vstorerw_ai ; BuildMI ( DefB , At , DefI -> getDebugLoc ( ) , HII -> get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addReg ( VecR ) ; unsigned VecSize = HRI . getRegSizeInBits ( VecRC ) / 8 ; for ( MachineInstr * ExtI : P . second ) { assert ( ExtI -> getOpcode ( ) == Hexagon :: V6_extractw ) ; unsigned SR = ExtI -> getOperand ( 1 ) . getSubReg ( ) ; assert ( ExtI -> getOperand ( 1 ) . getReg ( ) == VecR ) ; MachineBasicBlock & ExtB = * ExtI -> getParent ( ) ; DebugLoc DL = ExtI -> getDebugLoc ( ) ; unsigned BaseR = MRI . createVirtualRegister ( & Hexagon :: IntRegsRegClass ) ; BuildMI ( ExtB , ExtI , DL , HII -> get ( Hexagon :: PS_fi ) , BaseR ) . addFrameIndex ( FI ) . addImm ( SR == 0 ? 0 : VecSize / 2 ) ; unsigned ElemR = genElemLoad ( ExtI , BaseR , MRI ) ; unsigned ExtR = ExtI -> getOperand ( 0 ) . getReg ( ) ; MRI . replaceRegWith ( ExtR , ElemR ) ; ExtB . erase ( ExtI ) ; Changed = true ; } } return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> static void loongarch_for_each_saved_reg ( HOST_WIDE_INT sp_offset , loongarch_save_restore_fn fn ) { HOST_WIDE_INT offset ; offset = cfun -> machine -> frame . gp_sp_offset - sp_offset ; for ( int regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . mask , regno - GP_REG_FIRST ) ) { loongarch_save_restore_reg ( word_mode , regno , offset , fn ) ; offset -= UNITS_PER_WORD ; } offset = cfun -> machine -> frame . fp_sp_offset - sp_offset ; for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) if ( BITSET_P ( cfun -> machine -> frame . fmask , regno - FP_REG_FIRST ) ) { machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode ; loongarch_save_restore_reg ( mode , regno , offset , fn ) ; offset -= GET_MODE_SIZE ( mode ) ; } } </s>

Call FN for each register that is saved by the current function . SP_OFFSET is the offset of the current stack pointer from the start of the frame .


<s> WebAssemblySubtarget :: WebAssemblySubtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : WebAssemblyGenSubtargetInfo ( TT , CPU , CPU , FS ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) { } </s>

This constructor initializes the data members to match that of the specified triple .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> static int ia64_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t rclass , bool in ATTRIBUTE_UNUSED ) { if ( rclass == GENERAL_REGS || rclass == FR_REGS || rclass == FP_REGS || rclass == GR_AND_FR_REGS ) return 4 ; else return 10 ; } </s>

Calculate the cost of moving data of MODE from a register to or from memory .


<s>
static
void
aarch64_parse_sve_width_string
(
const
char
*
tune_string
,
struct
tune_params
*
tune
)
{
int
width
=
1
;
int
n
=
sscanf
(
tune_string
,
"%d"
,
&
width
)
;
if
(
n
==
EOF
)
{
error
(
"invalid format for sve_width"
)
;
return
;
}
switch
(
width
)
{
case
SVE_128
:
case
SVE_256
:
case
SVE_512
:
case
SVE_1024
:
case
SVE_2048
:
break
;
default
:
error
(
"invalid sve_width value: %d"
,
width
)
;
}
tune
->
sve_width
=
(
enum
aarch64_sve_vector_bits_enum
)
width
;
}
</s>

Parse the sve_width tuning moverride string in TUNE_STRING . Accept the valid SVE vector widths allowed by aarch64_sve_vector_bits_enum and use it to override sve_width in TUNE .


"Encountered a global variable kind that is "

Emit the specified global variable to the .s file .


<s> MachineBasicBlock :: iterator end ( ) const { return ++ MachineBasicBlock :: iterator ( KillInst ? KillInst : LastInst ) ; } </s>

Get a const_iterator to the end of the symbol table .


<s> void arc_adjust_reg_alloc_order ( void ) { const int arc_default_alloc_order [ ] = REG_ALLOC_ORDER ; memcpy ( reg_alloc_order , arc_default_alloc_order , sizeof ( reg_alloc_order ) ) ; if ( optimize_size ) memcpy ( reg_alloc_order , size_alloc_order , sizeof ( size_alloc_order ) ) ; } </s>

Adjust register allocation order when compiling for size .


<s> void SIMachineFunctionInfo :: removeDeadFrameIndices ( MachineFrameInfo & MFI ) { for ( auto & R : SGPRToVGPRSpills ) { if ( R . first != FramePointerSaveIndex ) MFI . RemoveStackObject ( R . first ) ; } for ( int i = MFI . getObjectIndexBegin ( ) , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( i != FramePointerSaveIndex ) MFI . setStackID ( i , TargetStackID :: Default ) ; for ( auto & R : VGPRToAGPRSpills ) { if ( R . second . FullyAllocated ) MFI . RemoveStackObject ( R . first ) ; } } </s>

If ResetSGPRSpillStackIDs is true , reset the stack ID from sgpr-spill to the default stack .


<s> void CJGAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static void output_deferred_profile_counters ( void ) { unsigned int i ; int align , n ; if ( funcdef_nos . is_empty ( ) ) return ; switch_to_section ( data_section ) ; align = MIN ( BIGGEST_ALIGNMENT , LONG_TYPE_SIZE ) ; ASM_OUTPUT_ALIGN ( asm_out_file , floor_log2 ( align / BITS_PER_UNIT ) ) ; for ( i = 0 ; funcdef_nos . iterate ( i , & n ) ; i ++ ) { targetm . asm_out . internal_label ( asm_out_file , "LP" , n ) ; assemble_integer ( const0_rtx , LONG_TYPE_SIZE / BITS_PER_UNIT , align , 1 ) ; } funcdef_nos . release ( ) ; } </s>


<s>
void
ARMBaseInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
MachineFrameInfo
&
MFI
=
*
MF
.
getFrameInfo
(
)
;
unsigned
Align
=
MFI
.
getObjectAlignment
(
FI
)
;
MachineMemOperand
*
MMO
=
MF
.
getMachineMemOperand
(
PseudoSourceValue
::
getFixedStack
(
FI
)
,
MachineMemOperand
::
MOLoad
,
0
,
MFI
.
getObjectSize
(
FI
)
,
Align
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
)
RC
=
ARM
::
GPRRegisterClass
;
if
(
RC
==
ARM
::
GPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
LDR
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addReg
(
0
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
if
(
RC
==
ARM
::
DPRRegisterClass
||
RC
==
ARM
::
DPR_VFP2RegisterClass
||
RC
==
ARM
::
DPR_8RegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLDRD
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
if
(
RC
==
ARM
::
SPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLDRS
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
)
;
}
else
{
assert
(
(
RC
==
ARM
::
QPRRegisterClass
||
RC
==
ARM
::
QPR_VFP2RegisterClass
||
RC
==
ARM
::
QPR_8RegisterClass
)
&&
"Unknown regclass!"
)
;
if
(
Align
>=
16
&&
(
getRegisterInfo
(
)
.
canRealignStack
(
MF
)
)
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLD1q
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
128
)
.
addMemOperand
(
MMO
)
)
;
}
else
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
VLDMQ
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
ARM_AM
::
getAM5Opc
(
ARM_AM
::
ia
,
4
)
)
.
addMemOperand
(
MMO
)
)
;
}
}
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> static void expand_block_move_2 ( rtx dst , rtx dst_reg , rtx src , rtx src_reg , rtx bytes_rtx ) { const rtx sym = gen_rtx_SYMBOL_REF ( Pmode , "__wrd_memcpy" ) ; unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % 2 ; emit_library_call ( sym , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> 1 ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == 0 ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; src = replace_equiv_address_nv ( src , src_reg ) ; bytes -= rem ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , adjust_address_nv ( src , QImode , bytes ) ) ; } </s>

Generate a call to a library function to move BYTES_RTX bytes from SRC with address SRC_REG to DST with address DST_REG in 2-bytes chunks .


<s> void MipsTargetMachine :: resetSubtarget ( MachineFunction * MF ) { DEBUG ( dbgs ( ) << "resetSubtarget\n" ) ; Subtarget = const_cast < MipsSubtarget * > ( getSubtargetImpl ( MF -> getFunction ( ) ) ) ; MF -> setSubtarget ( Subtarget ) ; } </s>

Reset the subtarget for the Mips target .


<s>
static
void
ia64_asm_unwind_emit
(
FILE
*
out_file
,
rtx_insn
*
insn
)
{
bool
unwind
=
ia64_except_unwind_info
(
&
global_options
)
==
UI_TARGET
;
bool
frame
=
dwarf2out_do_frame
(
)
;
rtx
note
,
pat
;
bool
handled_one
;
if
(
!
unwind
&&
!
frame
)
return
;
if
(
NOTE_INSN_BASIC_BLOCK_P
(
insn
)
)
{
last_block
=
NOTE_BASIC_BLOCK
(
insn
)
->
next_bb
==
EXIT_BLOCK_PTR_FOR_FN
(
cfun
)
;
if
(
need_copy_state
)
{
if
(
unwind
)
{
fprintf
(
out_file
,
"\t.body\n"
)
;
fprintf
(
out_file
,
"\t.copy_state %d\n"
,
cfun
->
machine
->
state_num
)
;
}
need_copy_state
=
false
;
}
}
if
(
NOTE_P
(
insn
)
||
!
RTX_FRAME_RELATED_P
(
insn
)
)
return
;
if
(
INSN_CODE
(
insn
)
==
CODE_FOR_alloc
)
{
rtx
dest
=
SET_DEST
(
XVECEXP
(
PATTERN
(
insn
)
,
0
,
0
)
)
;
int
dest_regno
=
REGNO
(
dest
)
;
if
(
dest_regno
==
current_frame_info
.
r
[
reg_save_ar_pfs
]
)
{
if
(
unwind
)
fprintf
(
out_file
,
"\t.save ar.pfs, r%d\n"
,
ia64_debugger_regno
(
dest_regno
)
)
;
}
else
{
if
(
current_frame_info
.
total_size
==
0
&&
!
frame_pointer_needed
)
process_epilogue
(
out_file
,
insn
,
unwind
,
frame
)
;
if
(
unwind
)
fprintf
(
out_file
,
"\t.prologue\n"
)
;
}
return
;
}
handled_one
=
false
;
for
(
note
=
REG_NOTES
(
insn
)
;
note
;
note
=
XEXP
(
note
,
1
)
)
switch
(
REG_NOTE_KIND
(
note
)
)
{
case
REG_CFA_ADJUST_CFA
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
pat
=
PATTERN
(
insn
)
;
process_cfa_adjust_cfa
(
out_file
,
pat
,
insn
,
unwind
,
frame
)
;
handled_one
=
true
;
break
;
case
REG_CFA_OFFSET
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
pat
=
PATTERN
(
insn
)
;
process_cfa_offset
(
out_file
,
pat
,
unwind
)
;
handled_one
=
true
;
break
;
case
REG_CFA_REGISTER
:
pat
=
XEXP
(
note
,
0
)
;
if
(
pat
==
)
pat
=
PATTERN
(
insn
)
;
process_cfa_register
(
out_file
,
pat
,
unwind
)
;
handled_one
=
true
;
break
;
case
REG_FRAME_RELATED_EXPR
:
case
REG_CFA_DEF_CFA
:
case
REG_CFA_EXPRESSION
:
case
REG_CFA_RESTORE
:
case
REG_CFA_SET_VDRAP
:
gcc_unreachable
(
)
;
default
:
break
;
}
gcc_assert
(
handled_one
)
;
}
</s>

This function looks at a single insn and emits any directives required to unwind this insn .


<s> static tree rs6000_builtin_reciprocal ( tree fndecl ) { switch ( DECL_FUNCTION_CODE ( fndecl ) ) { case VSX_BUILTIN_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_2DF ] ; case VSX_BUILTIN_XVSQRTSP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V4SFmode ) ) return NULL_TREE ; return rs6000_builtin_decls [ VSX_BUILTIN_RSQRT_4SF ] ; default : return NULL_TREE ; } } </s>

Returns a code for a target-specific builtin that implements reciprocal of the function , or NULL_TREE if not available .


<s> static int arc_save_callee_saves ( uint64_t gmask , bool save_blink , bool save_fp , HOST_WIDE_INT offset , bool emit_move ) { rtx reg ; int frame_allocated = 0 ; int i ; if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = 0 ; } if ( gmask ) for ( i = GMASK_LEN ; i >= 0 ; i -- ) { machine_mode save_mode = SImode ; if ( TARGET_LL64 && ( ( i - 1 ) % 2 == 0 ) && ( ( gmask & ( 1ULL << i ) ) != 0 ) && ( ( gmask & ( 1ULL << ( i - 1 ) ) ) != 0 ) ) { save_mode = DImode ; -- i ; } else if ( ( gmask & ( 1ULL << i ) ) == 0 ) continue ; reg = gen_rtx_REG ( save_mode , i ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = 0 ; } if ( save_fp ) { frame_allocated += frame_save_reg ( hard_frame_pointer_rtx , offset ) ; offset = 0 ; } if ( emit_move ) frame_move ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; return frame_allocated ; } </s>

ARC 's prologue , save any needed call-saved regs ( and call-used if this is an interrupt handler ) for ARCompact ISA , using ST/STD instructions .


<s> unsigned X86TTIImpl :: getScalarizationOverhead ( VectorType * Ty , const APInt & DemandedElts , bool Insert , bool Extract ) { unsigned Cost = 0 ; if ( Insert ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ( MScalarTy == MVT :: i16 && ST -> hasSSE2 ( ) ) || ( MScalarTy . isInteger ( ) && ST -> hasSSE41 ( ) ) || ( MScalarTy == MVT :: f32 && ST -> hasSSE41 ( ) ) ) { if ( LT . second . getSizeInBits ( ) <= 128 ) { Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , Insert , false ) ; } else { unsigned NumSubVecs = LT . second . getSizeInBits ( ) / 128 ; Cost += ( PowerOf2Ceil ( NumSubVecs ) - 1 ) * LT . first ; Cost += DemandedElts . countPopulation ( ) ; if ( MScalarTy == MVT :: f32 ) for ( unsigned i = 0 , e = Ty -> getNumElements ( ) ; i < e ; i += 4 ) if ( DemandedElts [ i ] ) Cost -- ; } } else if ( LT . second . isVector ( ) ) { if ( Ty -> isIntOrIntVectorTy ( ) ) Cost += DemandedElts . countPopulation ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned Pow2Elts = PowerOf2Ceil ( Ty -> getNumElements ( ) ) ; Cost += ( std :: min < unsigned > ( NumElts , Pow2Elts ) - 1 ) * LT . first ; } } if ( Extract ) Cost += BaseT :: getScalarizationOverhead ( Ty , DemandedElts , false , Extract ) ; return Cost ; } </s>

Estimate the overhead of scalarizing an instruction .


<s> bool RISCVFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s>
bool
CAHPInstrInfo
::
isBranchOffsetInRange
(
unsigned
BranchOp
,
int64_t
BrOffset
)
const
{
switch
(
BranchOp
)
{
default
:
llvm_unreachable
(
"Unexpected opcode!"
)
;
case
CAHP
::
BEQ
:
case
CAHP
::
BNE
:
case
CAHP
::
BLT
:
case
CAHP
::
BLE
:
case
CAHP
::
BLTU
:
case
CAHP
::
BLEU
:
return
isInt
<
10
>
(
BrOffset
)
;
case
CAHP
::
JSAL
:
case
CAHP
::
JS
:
return
isInt
<
11
>
(
BrOffset
)
;
}
}
</s>

Determine if the branch target is in range .

CAHP
CAHP
"Unexpected opcode!"
CAHP::BEQ
CAHP::BNE
CAHP::BLT
CAHP::BLE
CAHP::BLTU
CAHP::BLEU
10
CAHP::JSAL
CAHP::JS
11


"Unsupported calling conv: only FastCC and CCC is supported"

"Functions with the interrupt attribute cannot have arguments!"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Tile64 Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void SystemZAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>


<s> SDValue ARMTargetLowering :: PerformCMOVCombine ( SDNode * N , SelectionDAG & DAG ) const { SDValue Cmp = N -> getOperand ( 4 ) ; if ( Cmp . getOpcode ( ) != ARMISD :: CMPZ ) return SDValue ( ) ; EVT VT = N -> getValueType ( 0 ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue LHS = Cmp . getOperand ( 0 ) ; SDValue RHS = Cmp . getOperand ( 1 ) ; SDValue FalseVal = N -> getOperand ( 0 ) ; SDValue TrueVal = N -> getOperand ( 1 ) ; SDValue ARMcc = N -> getOperand ( 2 ) ; ARMCC :: CondCodes CC = ( ARMCC :: CondCodes ) cast < ConstantSDNode > ( ARMcc ) -> getZExtValue ( ) ; SDValue Res ; if ( CC == ARMCC :: NE && FalseVal == RHS && FalseVal != LHS ) { Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , TrueVal , ARMcc , N -> getOperand ( 3 ) , Cmp ) ; } else if ( CC == ARMCC :: EQ && TrueVal == RHS ) { SDValue ARMcc ; SDValue NewCmp = getARMCmp ( LHS , RHS , ISD :: SETNE , ARMcc , DAG , dl ) ; Res = DAG . getNode ( ARMISD :: CMOV , dl , VT , LHS , FalseVal , ARMcc , N -> getOperand ( 3 ) , NewCmp ) ; } if ( Res . getNode ( ) ) { APInt KnownZero , KnownOne ; APInt Mask = APInt :: getAllOnesValue ( VT . getScalarType ( ) . getSizeInBits ( ) ) ; DAG . ComputeMaskedBits ( SDValue ( N , 0 ) , Mask , KnownZero , KnownOne ) ; if ( KnownZero == 0xfffffffe ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i1 ) ) ; else if ( KnownZero == 0xffffff00 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i8 ) ) ; else if ( KnownZero == 0xffff0000 ) Res = DAG . getNode ( ISD :: AssertZext , dl , MVT :: i32 , Res , DAG . getValueType ( MVT :: i16 ) ) ; } return Res ; } </s>

PerformCMOVCombine - Target-specific DAG combining for ARMISD : :CMOV .


<s> unsigned LanaiMCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; if ( MCOp . isReg ( ) || MCOp . isImm ( ) ) return getMachineOpValue ( Inst , MCOp , Fixups , SubtargetInfo ) ; Fixups . push_back ( MCFixup :: create ( 0 , MCOp . getExpr ( ) , static_cast < MCFixupKind > ( Lanai :: FIXUP_LANAI_25 ) ) ) ; return 0 ; } </s>

getBranchTargetOpValue - Return binary encoding of the branch target operand .


<s> void h8300_expand_prologue ( void ) { int regno ; int saved_regs ; int n_regs ; if ( h8300_os_task_function_p ( current_function_decl ) ) return ; if ( h8300_monitor_function_p ( current_function_decl ) ) emit_insn ( gen_monitor_prologue ( ) ) ; if ( frame_pointer_needed ) { push ( HARD_FRAME_POINTER_REGNUM , true ) ; F ( emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) , true ) ; } saved_regs = compute_saved_regs ( ) ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno += n_regs ) { n_regs = 1 ; if ( saved_regs & ( 1 << regno ) ) { if ( TARGET_H8300S ) { if ( ( ! TARGET_H8300SX || ( regno & 3 ) == 0 ) && ( ( saved_regs >> regno ) & 0x0f ) == 0x0f ) n_regs = 4 ; else if ( ( ! TARGET_H8300SX || ( regno & 3 ) == 0 ) && ( ( saved_regs >> regno ) & 0x07 ) == 0x07 ) n_regs = 3 ; else if ( ( ! TARGET_H8300SX || ( regno & 1 ) == 0 ) && ( ( saved_regs >> regno ) & 0x03 ) == 0x03 ) n_regs = 2 ; } h8300_push_pop ( regno , n_regs , false , false ) ; } } h8300_emit_stack_adjustment ( - 1 , round_frame_size ( get_frame_size ( ) ) , true ) ; } </s>

Generate RTL code for the function prologue .


<s>
MachineBasicBlock
*
TriCoreTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
Opc
==
TriCore
::
Select8
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
MI
->
dump
(
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
TriCore
::
JNZsbr
)
)
.
addMBB
(
copy1MBB
)
.
addReg
(
MI
->
getOperand
(
4
)
.
getReg
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
TriCore
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> void Finish ( MachineBasicBlock & MBB , MOVEMState & State ) { auto MI = State . GetBegin ( ) ; auto End = State . GetEnd ( ) ; auto DL = MI -> getDebugLoc ( ) ; if ( std :: next ( MI ) == End ) { State = MOVEMState ( ) ; return ; } while ( MI != End ) { auto Next = std :: next ( MI ) ; MBB . erase ( MI ) ; MI = Next ; } if ( State . IsLoad ( ) ) { BuildMI ( MBB , End , DL , TII -> get ( M680x0 :: MOVM32mp ) ) . addImm ( State . GetMask ( ) ) . addImm ( State . GetFinalOffset ( ) ) . addReg ( State . GetBase ( ) ) ; } else { BuildMI ( MBB , End , DL , TII -> get ( M680x0 :: MOVM32pm ) ) . addImm ( State . GetFinalOffset ( ) ) . addReg ( State . GetBase ( ) ) . addImm ( State . GetMask ( ) ) ; } State = MOVEMState ( ) ; } </s>

Finish - Do final processing and write the object to the output stream .


<s>
static
void
ix86_code_end
(
void
)
{
rtx
xops
[
2
]
;
int
regno
;
for
(
regno
=
AX_REG
;
regno
<=
SP_REG
;
regno
++
)
{
char
name
[
32
]
;
tree
decl
;
if
(
!
(
pic_labels_used
&
(
1
<<
regno
)
)
)
continue
;
get_pc_thunk_name
(
name
,
regno
)
;
decl
=
build_decl
(
BUILTINS_LOCATION
,
FUNCTION_DECL
,
get_identifier
(
name
)
,
build_function_type_list
(
void_type_node
,
NULL_TREE
)
)
;
DECL_RESULT
(
decl
)
=
build_decl
(
BUILTINS_LOCATION
,
RESULT_DECL
,
NULL_TREE
,
void_type_node
)
;
TREE_PUBLIC
(
decl
)
=
1
;
TREE_STATIC
(
decl
)
=
1
;
DECL_IGNORED_P
(
decl
)
=
1
;
if
(
TARGET_MACHO
)
{
switch_to_section
(
darwin_sections
[
text_coal_section
]
)
;
fputs
(
"\t.weak_definition\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
fputs
(
"\n\t.private_extern\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
putc
(
'\n'
,
asm_out_file
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
DECL_WEAK
(
decl
)
=
1
;
}
else
if
(
USE_HIDDEN_LINKONCE
)
{
cgraph_node
::
create
(
decl
)
->
set_comdat_group
(
DECL_ASSEMBLER_NAME
(
decl
)
)
;
targetm
.
asm_out
.
unique_section
(
decl
,
0
)
;
switch_to_section
(
get_named_section
(
decl
,
,
0
)
)
;
targetm
.
asm_out
.
globalize_label
(
asm_out_file
,
name
)
;
fputs
(
"\t.hidden\t"
,
asm_out_file
)
;
assemble_name
(
asm_out_file
,
name
)
;
putc
(
'\n'
,
asm_out_file
)
;
ASM_DECLARE_FUNCTION_NAME
(
asm_out_file
,
name
,
decl
)
;
}
else
{
switch_to_section
(
text_section
)
;
ASM_OUTPUT_LABEL
(
asm_out_file
,
name
)
;
}
DECL_INITIAL
(
decl
)
=
make_node
(
BLOCK
)
;
current_function_decl
=
decl
;
init_function_start
(
decl
)
;
first_function_block_is_cold
=
false
;
final_start_function
(
emit_barrier
(
)
,
asm_out_file
,
1
)
;
if
(
TARGET_PAD_SHORT_FUNCTION
)
{
int
i
=
8
;
while
(
i
)
fputs
(
"\tnop\n"
,
asm_out_file
)
;
}
xops
[
0
]
=
gen_rtx_REG
(
Pmode
,
regno
)
;
xops
[
1
]
=
gen_rtx_MEM
(
Pmode
,
stack_pointer_rtx
)
;
output_asm_insn
(
"mov%z0\t{%1, %0|%0, %1}"
,
xops
)
;
output_asm_insn
(
"%!ret"
,
)
;
final_end_function
(
)
;
init_insn_lengths
(
)
;
free_after_compilation
(
cfun
)
;
set_cfun
(
)
;
current_function_decl
=
;
}
if
(
flag_split_stack
)
file_end_indicate_split_stack
(
)
;
}
</s>

This function generates code for -fpic that loads % ebx with the return address of the caller and then returns .


<s>
void
HexagonAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
MCInst
MCB
;
MCB
.
setOpcode
(
Hexagon
::
BUNDLE
)
;
MCB
.
addOperand
(
MCOperand
::
createImm
(
0
)
)
;
const
MCInstrInfo
&
MCII
=
*
Subtarget
->
getInstrInfo
(
)
;
if
(
MI
->
isBundle
(
)
)
{
assert
(
Subtarget
->
usePackets
(
)
&&
"Support for packets is disabled"
)
;
const
MachineBasicBlock
*
MBB
=
MI
->
getParent
(
)
;
MachineBasicBlock
::
const_instr_iterator
MII
=
MI
->
getIterator
(
)
;
for
(
++
MII
;
MII
!=
MBB
->
instr_end
(
)
&&
MII
->
isInsideBundle
(
)
;
++
MII
)
if
(
!
MII
->
isDebugInstr
(
)
&&
!
MII
->
isImplicitDef
(
)
)
HexagonLowerToMC
(
MCII
,
&
*
MII
,
MCB
,
*
this
)
;
}
else
{
HexagonLowerToMC
(
MCII
,
MI
,
MCB
,
*
this
)
;
}
const
MachineFunction
&
MF
=
*
MI
->
getParent
(
)
->
getParent
(
)
;
const
auto
&
HII
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
if
(
MI
->
isBundle
(
)
&&
HII
.
getBundleNoShuf
(
*
MI
)
)
HexagonMCInstrInfo
::
setMemReorderDisabled
(
MCB
)
;
MCContext
&
Ctx
=
OutStreamer
->
getContext
(
)
;
bool
Ok
=
HexagonMCInstrInfo
::
canonicalizePacket
(
MCII
,
*
Subtarget
,
Ctx
,
MCB
,
nullptr
)
;
assert
(
Ok
)
;
(
void
)
Ok
;
if
(
HexagonMCInstrInfo
::
bundleSize
(
MCB
)
==
0
)
return
;
OutStreamer
->
EmitInstruction
(
MCB
,
getSubtargetInfo
(
)
)
;
}
</s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon
Hexagon
Hexagon::BUNDLE
0
"Support for packets is disabled"
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
Hexagon
0


<s> bool PIC16TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createPIC16ISelDag ( * this ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> void HexagonMCShuffler :: init ( MCInst & MCB , MCInst const & AddMI , bool bInsertAtFront ) { if ( HexagonMCInstrInfo :: isBundle ( MCB ) ) { if ( bInsertAtFront ) append ( AddMI , nullptr , HexagonMCInstrInfo :: getUnits ( MCII , STI , AddMI ) ) ; MCInst const * Extender = nullptr ; for ( auto const & I : HexagonMCInstrInfo :: bundleInstructions ( MCB ) ) { assert ( ! HexagonMCInstrInfo :: getDesc ( MCII , * I . getInst ( ) ) . isPseudo ( ) ) ; MCInst & MI = * const_cast < MCInst * > ( I . getInst ( ) ) ; if ( ! HexagonMCInstrInfo :: isImmext ( MI ) ) { append ( MI , Extender , HexagonMCInstrInfo :: getUnits ( MCII , STI , MI ) ) ; Extender = nullptr ; } else Extender = & MI ; } if ( ! bInsertAtFront ) append ( AddMI , nullptr , HexagonMCInstrInfo :: getUnits ( MCII , STI , AddMI ) ) ; } BundleFlags = MCB . getOperand ( 0 ) . getImm ( ) ; } </s>

Initialize the machine model for instruction scheduling .

Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon Hexagon 0


<s>
void
X86FastPreTileConfig
::
spill
(
MachineBasicBlock
::
iterator
Before
,
Register
VirtReg
,
bool
Kill
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"Spilling "
<<
printReg
(
VirtReg
,
TRI
)
<<
" \n"
)
;
int
FI
=
getStackSpaceFor
(
VirtReg
)
;
LLVM_DEBUG
(
dbgs
(
)
<<
" to stack slot #"
<<
FI
<<
'\n'
)
;
const
TargetRegisterClass
&
RC
=
*
MRI
->
getRegClass
(
VirtReg
)
;
TII
->
storeRegToStackSlot
(
*
MBB
,
Before
,
VirtReg
,
Kill
,
FI
,
&
RC
,
TRI
)
;
++
NumStores
;
}
</s>

spill - Spill the LRE.getParent ( ) live interval .


<s> static bool tryAddingSymbolicOperand ( int64_t Value , bool IsBranch , uint64_t Address , uint64_t Offset , uint64_t Width , MCInst & MI , const MCDisassembler * Decoder ) { return Decoder -> tryAddingSymbolicOperand ( MI , Value , Address , IsBranch , Offset , Width , 0 ) ; } </s>

Try to add a symbolic operand instead of Value to the MCInst .


<s> void DCPU16AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { DCPU16MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } </s>


<s> bool isNull ( ) const { return isRegKind ( ) && getReg ( ) == AMDGPU :: SGPR_NULL ; } </s>

Test if the pointer held in the union is null , regardless of which type it is .


<s> void msp430_init_cumulative_args ( CUMULATIVE_ARGS * ca , tree fntype ATTRIBUTE_UNUSED , rtx libname ATTRIBUTE_UNUSED , tree fndecl ATTRIBUTE_UNUSED , int n_named_args ATTRIBUTE_UNUSED ) { const char * fname ; memset ( ca , 0 , sizeof ( * ca ) ) ; ca -> can_split = 1 ; if ( fndecl ) fname = IDENTIFIER_POINTER ( DECL_NAME ( fndecl ) ) ; else if ( libname ) fname = XSTR ( libname , 0 ) ; else fname = NULL ; if ( fname && msp430_special_register_convention_p ( fname ) ) ca -> special_p = 1 ; } </s>


<s>
bool
MipsCodeEmitter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
JTI
=
(
(
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getJITInfo
(
)
;
II
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getInstrInfo
(
)
;
TD
=
(
(
const
MipsTargetMachine
&
)
MF
.
getTarget
(
)
)
.
getTargetData
(
)
;
Subtarget
=
&
TM
.
getSubtarget
<
MipsSubtarget
>
(
)
;
MCPEs
=
&
MF
.
getConstantPool
(
)
->
getConstants
(
)
;
MJTEs
=
0
;
if
(
MF
.
getJumpTableInfo
(
)
)
MJTEs
=
&
MF
.
getJumpTableInfo
(
)
->
getJumpTables
(
)
;
JTI
->
Initialize
(
MF
,
IsPIC
)
;
MCE
.
setModuleInfo
(
&
getAnalysis
<
MachineModuleInfo
>
(
)
)
;
do
{
DEBUG
(
errs
(
)
<<
"JITTing function '"
<<
MF
.
getName
(
)
<<
"'\n"
)
;
MCE
.
startFunction
(
MF
)
;
for
(
MachineFunction
::
iterator
MBB
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
MBB
!=
E
;
++
MBB
)
{
MCE
.
StartMachineBasicBlock
(
MBB
)
;
for
(
MachineBasicBlock
::
instr_iterator
I
=
MBB
->
instr_begin
(
)
,
E
=
MBB
->
instr_end
(
)
;
I
!=
E
;
++
I
)
emitInstruction
(
*
I
)
;
}
}
while
(
MCE
.
finishFunction
(
MF
)
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Mips
Mips
Mips
Mips
Mips
Mips
0
"JITTing function '"
"'\n"


<s> tree function_resolver :: resolve_unary ( type_class_index merge_tclass , unsigned int merge_bits , bool treat_as_merge_p ) { type_suffix_index type ; if ( pred == PRED_m || treat_as_merge_p ) { if ( ! check_num_arguments ( 3 ) ) return error_mark_node ; if ( merge_tclass == SAME_TYPE_CLASS && merge_bits == SAME_SIZE ) { if ( ( type = infer_vector_type ( 0 ) ) == NUM_TYPE_SUFFIXES || ! require_vector_type ( 1 , VECTOR_TYPE_svbool_t ) || ! require_matching_vector_type ( 2 , type ) ) return error_mark_node ; } else { if ( ! require_vector_type ( 1 , VECTOR_TYPE_svbool_t ) || ( type = infer_vector_type ( 2 ) ) == NUM_TYPE_SUFFIXES || ! require_derived_vector_type ( 0 , 2 , type , merge_tclass , merge_bits ) ) return error_mark_node ; } } else { unsigned int i , nargs ; if ( ! check_gp_argument ( 1 , i , nargs ) || ( type = infer_vector_type ( i ) ) == NUM_TYPE_SUFFIXES ) return error_mark_node ; } if ( type_suffix_ids [ 0 ] != NUM_TYPE_SUFFIXES ) return resolve_to ( mode_suffix_id , type_suffix_ids [ 0 ] , type ) ; return resolve_to ( mode_suffix_id , type ) ; } </s>

Resolve a ( possibly predicated ) unary function . If the function uses merge predication or if TREAT_AS_MERGE_P is true , there is an extra vector argument before the governing predicate that specifies the values of inactive elements . This argument has the following properties : - the type class must be the same as for active elements if MERGE_TCLASS is SAME_TYPE_CLASS , otherwise it must be MERGE_TCLASS itself . - the element size must be the same as for active elements if MERGE_BITS is SAME_TYPE_SIZE , otherwise it must be MERGE_BITS itself . Return the function decl of the resolved function on success , otherwise report a suitable error and return error_mark_node .


"cannot set interrupt attribute: no current function"

"cannot set interrupt attribute: no such identifier"

Set the machine specific 'interrupt ' attribute on the current function .


<s> static unsigned char get_content_index ( rtx loc ) { machine_mode mode ; if ( loc == NULL_RTX ) return NOT_KNOWN ; if ( REG_P ( loc ) ) { if ( REGNO ( loc ) < 32 ) return REGNO ( loc ) ; return NOT_KNOWN ; } mode = GET_MODE ( loc ) ; if ( ! rl78_stack_based_mem ( loc , mode ) ) return NOT_KNOWN ; loc = XEXP ( loc , 0 ) ; if ( REG_P ( loc ) ) return 32 ; loc = XEXP ( loc , 1 ) ; if ( INTVAL ( loc ) < NUM_STACK_LOCS ) return 32 + INTVAL ( loc ) ; return NOT_KNOWN ; } </s>

Convert LOC into an index into the content_memory array . If LOC can not be converted , return NOT_KNOWN .


<s>
RISCV
::
FixupKind
RISCVMCExpr
::
getFixupKind
(
RISCVMCExpr
::
VariantKind
Kind
)
{
switch
(
Kind
)
{
default
:
llvm_unreachable
(
"Unhandled RISCVMCExpr::VariantKind"
)
;
case
VK_RISCV_LO12
:
return
RISCV
::
fixup_riscv_lo12
;
case
VK_RISCV_HI20
:
return
RISCV
::
fixup_riscv_hi20
;
case
VK_RISCV_PCREL_LO12
:
return
RISCV
::
fixup_riscv_pcrel_lo12
;
case
VK_RISCV_PCREL_HI20
:
return
RISCV
::
fixup_riscv_pcrel_hi20
;
case
VK_RISCV_TPREL_LO12
:
return
RISCV
::
fixup_riscv_tprel_lo12
;
case
VK_RISCV_TPREL_HI20
:
return
RISCV
::
fixup_riscv_tprel_hi20
;
}
}
</s>

getFixupKind - Get the fixup kind of this expression .


<s>
void
WebAssemblyAsmPrinter
::
EmitInstruction
(
const
MachineInstr
*
MI
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
"EmitInstruction: "
<<
*
MI
<<
'\n'
)
;
switch
(
MI
->
getOpcode
(
)
)
{
case
WebAssembly
::
ARGUMENT_I32
:
case
WebAssembly
::
ARGUMENT_I32_S
:
case
WebAssembly
::
ARGUMENT_I64
:
case
WebAssembly
::
ARGUMENT_I64_S
:
case
WebAssembly
::
ARGUMENT_F32
:
case
WebAssembly
::
ARGUMENT_F32_S
:
case
WebAssembly
::
ARGUMENT_F64
:
case
WebAssembly
::
ARGUMENT_F64_S
:
case
WebAssembly
::
ARGUMENT_v16i8
:
case
WebAssembly
::
ARGUMENT_v16i8_S
:
case
WebAssembly
::
ARGUMENT_v8i16
:
case
WebAssembly
::
ARGUMENT_v8i16_S
:
case
WebAssembly
::
ARGUMENT_v4i32
:
case
WebAssembly
::
ARGUMENT_v4i32_S
:
case
WebAssembly
::
ARGUMENT_v2i64
:
case
WebAssembly
::
ARGUMENT_v2i64_S
:
case
WebAssembly
::
ARGUMENT_v4f32
:
case
WebAssembly
::
ARGUMENT_v4f32_S
:
case
WebAssembly
::
ARGUMENT_v2f64
:
case
WebAssembly
::
ARGUMENT_v2f64_S
:
break
;
case
WebAssembly
::
FALLTHROUGH_RETURN_I32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_I64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_F64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v16i8_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v8i16_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4i32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2i64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2i64_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v4f32_S
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2f64
:
case
WebAssembly
::
FALLTHROUGH_RETURN_v2f64_S
:
{
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return-value"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
}
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID
:
case
WebAssembly
::
FALLTHROUGH_RETURN_VOID_S
:
if
(
isVerbose
(
)
)
{
OutStreamer
->
AddComment
(
"fallthrough-return-void"
)
;
OutStreamer
->
AddBlankLine
(
)
;
}
break
;
default
:
{
WebAssemblyMCInstLower
MCInstLowering
(
OutContext
,
*
this
)
;
MCInst
TmpInst
;
MCInstLowering
.
Lower
(
MI
,
TmpInst
)
;
EmitToStreamer
(
*
OutStreamer
,
TmpInst
)
;
break
;
}
}
}
</s>


<s> static void register_svprfop ( ) { auto_vec < string_int_pair , 16 > values ; values . quick_push ( string_int_pair ( "SV_" # UPPER , VALUE ) ) ; AARCH64_FOR_SVPRFOP ( PUSH ) acle_svprfop = lang_hooks . types . simulate_enum_decl ( input_location , "svprfop" , values ) ; } </s>


<s> static rtx xtensa_function_arg_1 ( cumulative_args_t cum_v , const function_arg_info & arg , bool incoming_p ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regbase , words , max ; int * arg_words ; int regno ; arg_words = & cum -> arg_words ; regbase = ( incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST ) ; max = MAX_ARGS_IN_REGISTERS ; words = ( ( arg . promoted_size_in_bytes ( ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; if ( arg . type && ( TYPE_ALIGN ( arg . type ) > BITS_PER_WORD ) ) { int align = MIN ( TYPE_ALIGN ( arg . type ) , STACK_BOUNDARY ) / BITS_PER_WORD ; * arg_words = ( * arg_words + align - 1 ) & - align ; } if ( * arg_words + words > max ) return ( rtx ) 0 ; regno = regbase + * arg_words ; if ( cum -> incoming && regno <= A7_REG && regno + words > A7_REG ) cfun -> machine -> need_a7_copy = TARGET_WINDOWED_ABI ; return gen_rtx_REG ( arg . mode , regno ) ; } </s>

Return an RTL expression containing the register for the given mode , or 0 if the argument is to be passed on the stack . INCOMING_P is nonzero if this is an incoming argument to the current function .


<s> Register getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) override { LLT p0 = LLT :: pointer ( 0 , 64 ) ; LLT s64 = LLT :: scalar ( 64 ) ; Register SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Register ( AArch64 :: SP ) ) ; Register OffsetReg = MRI . createGenericVirtualRegister ( s64 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; Register AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s> unsigned getPointerSize ( ) const { return 4 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s> static bool offsettable_ok_by_alignment ( rtx op , HOST_WIDE_INT offset , machine_mode mode ) { tree decl , type ; unsigned HOST_WIDE_INT dsize , dalign , lsb , mask ; if ( GET_CODE ( op ) != SYMBOL_REF ) return false ; dsize = GET_MODE_SIZE ( mode ) ; decl = SYMBOL_REF_DECL ( op ) ; if ( ! decl ) { if ( dsize == 0 ) return false ; dalign = BITS_PER_UNIT ; if ( SYMBOL_REF_HAS_BLOCK_INFO_P ( op ) && SYMBOL_REF_ANCHOR_P ( op ) && SYMBOL_REF_BLOCK ( op ) != NULL ) { struct object_block * block = SYMBOL_REF_BLOCK ( op ) ; dalign = block -> alignment ; offset += SYMBOL_REF_BLOCK_OFFSET ( op ) ; } else if ( CONSTANT_POOL_ADDRESS_P ( op ) ) { machine_mode cmode = get_pool_mode ( op ) ; dalign = GET_MODE_ALIGNMENT ( cmode ) ; } } else if ( DECL_P ( decl ) ) { dalign = DECL_ALIGN ( decl ) ; if ( dsize == 0 ) { if ( ! DECL_SIZE_UNIT ( decl ) ) return false ; if ( ! tree_fits_uhwi_p ( DECL_SIZE_UNIT ( decl ) ) ) return false ; dsize = tree_to_uhwi ( DECL_SIZE_UNIT ( decl ) ) ; if ( dsize > 32768 ) return false ; return dalign / BITS_PER_UNIT >= dsize ; } } else { type = TREE_TYPE ( decl ) ; dalign = TYPE_ALIGN ( type ) ; if ( CONSTANT_CLASS_P ( decl ) ) dalign = CONSTANT_ALIGNMENT ( decl , dalign ) ; else dalign = DATA_ALIGNMENT ( decl , dalign ) ; if ( dsize == 0 ) { if ( TREE_CODE ( decl ) == STRING_CST ) dsize = TREE_STRING_LENGTH ( decl ) ; else if ( TYPE_SIZE_UNIT ( type ) && tree_fits_uhwi_p ( TYPE_SIZE_UNIT ( type ) ) ) dsize = tree_to_uhwi ( TYPE_SIZE_UNIT ( type ) ) ; else return false ; if ( dsize > 32768 ) return false ; return dalign / BITS_PER_UNIT >= dsize ; } } mask = dalign / BITS_PER_UNIT - 1 ; lsb = offset & - offset ; mask &= lsb - 1 ; dalign = mask + 1 ; return dalign >= dsize ; } </s>

Return true if a MODE sized memory accesses to OP plus OFFSET is known to not straddle a 32k boundary .


<s> bool MOSLateOptimization :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { Changed |= lowerCMPTermZs ( MBB ) ; Changed |= ldImmToInxyDexy ( MBB ) ; } return Changed ; } </s>


<s> bool arc_legitimate_constant_p ( machine_mode , rtx x ) { if ( ! flag_pic ) return true ; switch ( GET_CODE ( x ) ) { case CONST : x = XEXP ( x , 0 ) ; if ( GET_CODE ( x ) == PLUS ) { if ( GET_CODE ( XEXP ( x , 1 ) ) != CONST_INT ) return false ; x = XEXP ( x , 0 ) ; } if ( GET_CODE ( x ) == UNSPEC ) switch ( XINT ( x , 1 ) ) { case ARC_UNSPEC_PLT : case ARC_UNSPEC_GOTOFF : case ARC_UNSPEC_GOT : case UNSPEC_PROF : return true ; default : gcc_unreachable ( ) ; } if ( arc_raw_symbolic_reference_mentioned_p ( x , false ) ) return false ; break ; case LABEL_REF : case SYMBOL_REF : return false ; default : break ; } return true ; } </s>

Determine if a given RTX is a valid constant . We already know this satisfies CONSTANT_P .


<s> int const_sint32_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { return ( GET_CODE ( op ) == CONST_INT && ( INTVAL ( op ) >= ( - 0x7fffffff - 1 ) && INTVAL ( op ) <= 0x7fffffff ) ) ; } </s>

Accept integer operands in the range -0x80000000 .. 0x7fffffff . We have to check the range carefully since this predicate is used in DImode contexts .


<s>
const
char
*
rs6000_insn_for_insert_mask
(
machine_mode
mode
,
rtx
*
operands
,
bool
dot
)
{
int
nb
,
ne
;
if
(
!
rs6000_is_valid_mask
(
operands
[
3
]
,
&
nb
,
&
ne
,
mode
)
)
gcc_unreachable
(
)
;
if
(
TARGET_POWERPC64
&&
(
!
dot
||
mode
==
DImode
)
&&
GET_CODE
(
operands
[
4
]
)
!=
LSHIFTRT
&&
ne
==
INTVAL
(
operands
[
2
]
)
)
{
operands
[
3
]
=
GEN_INT
(
63
nb
)
;
if
(
dot
)
return
"rldimi. %0,%1,%2,%3"
;
return
"rldimi %0,%1,%2,%3"
;
}
if
(
nb
<
32
&&
ne
<
32
)
{
if
(
GET_CODE
(
operands
[
4
]
)
==
LSHIFTRT
&&
INTVAL
(
operands
[
2
]
)
)
operands
[
2
]
=
GEN_INT
(
32
INTVAL
(
operands
[
2
]
)
)
;
operands
[
3
]
=
GEN_INT
(
31
nb
)
;
operands
[
4
]
=
GEN_INT
(
31
ne
)
;
if
(
dot
)
return
"rlwimi. %0,%1,%2,%3,%4"
;
return
"rlwimi %0,%1,%2,%3,%4"
;
}
gcc_unreachable
(
)
;
}
</s>

Return the instruction template for an insert with mask in mode MODE , with operands OPERANDS . If DOT is true , make it a record-form instruction .


<s> bool TL45AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ; } </s>

ParseDirective - Parse a target specific assembler directive This method is deprecated , use 'parseDirective ' instead .


<s> void mmix_output_quoted_string ( FILE * stream , const char * string , int length ) { const char * string_end = string + length ; static const char * const unwanted_chars = "\"[]\\" ; while ( string < string_end ) { if ( * string && ( unsigned char ) * string < 128 && ! ISCNTRL ( * string ) && strchr ( unwanted_chars , * string ) == NULL ) { fputc ( '"' , stream ) ; while ( * string && ( unsigned char ) * string < 128 && ! ISCNTRL ( * string ) && strchr ( unwanted_chars , * string ) == NULL && string < string_end ) { fputc ( * string , stream ) ; string ++ ; } fputc ( '"' , stream ) ; if ( string < string_end ) fprintf ( stream , "," ) ; } if ( string < string_end ) { fprintf ( stream , "#%x" , * string & 255 ) ; string ++ ; if ( string < string_end ) fprintf ( stream , "," ) ; } } } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"Tile Register Pre-configure"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool SITargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; return TII -> isInlineConstant ( Imm ) ; } </s>

Returns true if it is beneficial to convert a load of a constant to just the constant itself .


<s> void avr_log_set_avr_log ( void ) { bool all = TARGET_ALL_DEBUG != 0 ; if ( all ) avr_log_details = "all" ; if ( all || avr_log_details ) { char * str = ( char * ) alloca ( 3 + strlen ( avr_log_details ) ) ; bool info ; str [ 0 ] = ',' ; strcat ( stpcpy ( str + 1 , avr_log_details ) , "," ) ; all |= strstr ( str , ",all," ) != NULL ; info = strstr ( str , ",?," ) != NULL ; if ( info ) fprintf ( stderr , "\n-mlog=" ) ; do { \ avr_log . S = ( all || strstr ( str , "," # S "," ) != NULL ) ; \ if ( info ) \ fprintf ( stderr , # S "," ) ; \ } while ( 0 ) SET_DUMP_DETAIL ( address_cost ) ; SET_DUMP_DETAIL ( builtin ) ; SET_DUMP_DETAIL ( constraints ) ; SET_DUMP_DETAIL ( insn_addresses ) ; SET_DUMP_DETAIL ( legitimate_address_p ) ; SET_DUMP_DETAIL ( legitimize_address ) ; SET_DUMP_DETAIL ( legitimize_reload_address ) ; SET_DUMP_DETAIL ( progmem ) ; SET_DUMP_DETAIL ( rtx_costs ) ; if ( info ) fprintf ( stderr , "?\n\n" ) ; } } </s>

Called from avr.cc : avr_option_override ( ) . Parse argument of -mlog= and set respective fields in avr_log .


<s> void X86IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\t" ; unsigned Flags = MI -> getFlags ( ) ; if ( Flags & X86 :: IP_HAS_REPEAT_NE ) OS << "\trepne\t" ; else if ( Flags & X86 :: IP_HAS_REPEAT ) OS << "\trep\t" ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .