<s> void AArch64InstPrinter :: printImplicitlyTypedVectorList ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { printVectorList ( MI , OpNum , STI , O , "" ) ; } </s>

Print a list of vector registers where the type suffix is implicit ( i.e .


<s> static inline unsigned long * ia64_rse_rnat_addr ( unsigned long * slot_addr ) { return ( unsigned long * ) ( ( unsigned long ) slot_addr | ( 0x3f << 3 ) ) ; } </s>

Returns the address of the RNAT slot that covers the slot at address SLOT_ADDR .


<s> SDValue NVPTXTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { CodeGenOpt :: Level OptLevel = CodeGenOpt :: Aggressive ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: ADD : case ISD :: FADD : return PerformADDCombine ( N , DCI , nvptxSubtarget , OptLevel ) ; case ISD :: MUL : return PerformMULCombine ( N , DCI , OptLevel ) ; case ISD :: SHL : return PerformSHLCombine ( N , DCI , OptLevel ) ; case ISD :: AND : return PerformANDCombine ( N , DCI ) ; } return SDValue ( ) ; } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .

NVPTX NVPTX ISD::ADD ISD::FADD ISD::MUL ISD::SHL ISD::AND


<s> static void mips_insert_insn_pseudos ( void ) { bool insn_pseudo_needed = TRUE ; rtx_insn * insn ; for ( insn = get_last_insn ( ) ; insn != NULL_RTX ; insn = PREV_INSN ( insn ) ) switch ( GET_CODE ( insn ) ) { case INSN : if ( GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , 1 ) == UNSPEC_CONSTTABLE ) { insn_pseudo_needed = TRUE ; break ; } case JUMP_INSN : case CALL_INSN : case JUMP_TABLE_DATA : insn_pseudo_needed = FALSE ; break ; case CODE_LABEL : if ( insn_pseudo_needed ) { emit_insn_after ( gen_insn_pseudo ( ) , insn ) ; insn_pseudo_needed = FALSE ; } break ; default : break ; } } </s>

Insert a ` .insn ' assembly pseudo-op after any labels followed by a MIPS16 constant pool or no insn at all . This is needed so that targets that have been optimized away are still marked as code and therefore branches that remained and point to them are known to retain the ISA mode and as such can be successfully assembled .


<s>
static
uint16_t
name
(
struct
InternalInstruction
*
insn
,
OperandType
type
,
\
uint8_t
index
,
uint8_t
*
valid
)
{
\
*
valid
=
1
;
\
switch
(
type
)
{
\
default
:
\
debug
(
"Unhandled register type"
)
;
\
*
valid
=
0
;
\
return
0
;
\
case
TYPE_Rv
:
\
return
base
+
index
;
\
case
TYPE_R8
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
if
(
insn
->
rexPrefix
&&
index
>=
4
&&
index
<=
7
)
{
\
return
prefix
##
_SPL
+
(
index
4
)
;
\
}
else
{
\
return
prefix
##
_AL
+
index
;
\
}
\
case
TYPE_R16
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_AX
+
index
;
\
case
TYPE_R32
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_EAX
+
index
;
\
case
TYPE_R64
:
\
index
&=
mask
;
\
if
(
index
>
0xf
)
\
*
valid
=
0
;
\
return
prefix
##
_RAX
+
index
;
\
case
TYPE_ZMM
:
\
return
prefix
##
_ZMM0
+
index
;
\
case
TYPE_YMM
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_XMM
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_VK
:
\
index
&=
0xf
;
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0
+
index
;
\
case
TYPE_VK_PAIR
:
\
if
(
index
>
7
)
\
*
valid
=
0
;
\
return
prefix
##
_K0_K1
+
(
index
/
2
)
;
\
case
TYPE_MM64
:
\
return
prefix
##
_MM0
+
(
index
&
0x7
)
;
\
case
TYPE_SEGMENTREG
:
\
if
(
(
index
&
7
)
>
5
)
\
*
valid
=
0
;
\
return
prefix
##
_ES
+
(
index
&
7
)
;
\
case
TYPE_DEBUGREG
:
\
return
prefix
##
_DR0
+
index
;
\
case
TYPE_CONTROLREG
:
\
return
prefix
##
_CR0
+
index
;
\
case
TYPE_BNDR
:
\
if
(
index
>
3
)
\
*
valid
=
0
;
\
return
prefix
##
_BND0
+
index
;
\
case
TYPE_MVSIBX
:
\
return
prefix
##
_XMM0
+
index
;
\
case
TYPE_MVSIBY
:
\
return
prefix
##
_YMM0
+
index
;
\
case
TYPE_MVSIBZ
:
\
return
prefix
##
_ZMM0
+
index
;
\
}
\
}
</s>

Gets the name of the pass we are mixed into .


<s> RISCV :: FixupKind getFixupKind ( ) const { return getFixupKind ( Kind ) ; } </s>

getFixupKind - Get the fixup kind of this expression .


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> MachineInstrBuilder R600InstrInfo :: buildDefaultInstruction ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned Opcode , unsigned DstReg , unsigned Src0Reg , unsigned Src1Reg ) const { MachineInstrBuilder MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opcode ) , DstReg ) ; if ( Src1Reg ) { MIB . addImm ( 0 ) . addImm ( 0 ) ; } MIB . addImm ( 1 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addReg ( Src0Reg ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( - 1 ) ; if ( Src1Reg ) { MIB . addReg ( Src1Reg ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( 0 ) . addImm ( - 1 ) ; } MIB . addImm ( 1 ) . addReg ( R600 :: PRED_SEL_OFF ) . addImm ( 0 ) . addImm ( 0 ) ; return MIB ; } </s>

buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values .


<s> void MOSRegisterBankInfo :: applyMappingImpl ( const OperandsMapper & OpdMapper ) const { applyDefaultMapping ( OpdMapper ) ; } </s>


Pointer authentication builtins that will become NOP on legacy platform . Currently , these builtins are for internal use only ( libgcc EH unwinder ) .


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ 0 ] + 1 ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = 1 ; i < nelt ; next ++ , i ++ ) { if ( next == 2 * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == 2 ) && ( d -> vmode != V2DImode ) ) return false ; else next = 0 ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ 0 ] ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vextv16qi ; break ; case V8QImode : gen = gen_neon_vextv8qi ; break ; case V4HImode : gen = gen_neon_vextv4hi ; break ; case V8HImode : gen = gen_neon_vextv8hi ; break ; case V2SImode : gen = gen_neon_vextv2si ; break ; case V4SImode : gen = gen_neon_vextv4si ; break ; case V4HFmode : gen = gen_neon_vextv4hf ; break ; case V8HFmode : gen = gen_neon_vextv8hf ; break ; case V2SFmode : gen = gen_neon_vextv2sf ; break ; case V4SFmode : gen = gen_neon_vextv4sf ; break ; case V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


"switch -mcpu=%s conflicts with -march=%s switch"

Parse the TO_PARSE string and put the architecture struct that it selects into RES and the architectural features into ISA_FLAGS . Return an aarch64_parse_opt_result describing the parse result . If there is an error parsing , RES and ISA_FLAGS are left unchanged .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
UPT
::
NumTargetFixupKinds
]
=
{
{
"fixup_upt_mov_hi16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_upt_mov_lo16_pcrel"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
{
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
}
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static int optimal_immediate_sequence_1 ( enum rtx_code code , unsigned HOST_WIDE_INT val , struct four_ints * return_sequence , int i ) { int remainder = val & 0xffffffff ; int insns = 0 ; do { int end ; unsigned int b1 , b2 , b3 , b4 ; unsigned HOST_WIDE_INT result ; int loc ; gcc_assert ( insns < 4 ) ; if ( i <= 0 ) i += 32 ; if ( remainder & ( ( TARGET_ARM ? ( 3 << ( i - 2 ) ) : ( 1 << ( i - 1 ) ) ) ) ) { loc = i ; if ( i <= 12 && TARGET_THUMB2 && code == PLUS ) result = remainder ; else { end = i - 8 ; if ( end < 0 ) end += 32 ; result = remainder & ( ( 0x0ff << end ) | ( ( i < end ) ? ( 0xff >> ( 32 - end ) ) : 0 ) ) ; i -= 8 ; } } else { i -= TARGET_ARM ? 2 : 1 ; continue ; } if ( TARGET_THUMB2 ) { b1 = ( remainder & 0xff000000 ) >> 24 ; b2 = ( remainder & 0x00ff0000 ) >> 16 ; b3 = ( remainder & 0x0000ff00 ) >> 8 ; b4 = remainder & 0xff ; if ( loc > 24 ) { unsigned int tmp = b1 & b2 & b3 & b4 ; unsigned int tmp2 = tmp + ( tmp << 8 ) + ( tmp << 16 ) + ( tmp << 24 ) ; unsigned int matching_bytes = ( tmp == b1 ) + ( tmp == b2 ) + ( tmp == b3 ) + ( tmp == b4 ) ; if ( tmp && ( matching_bytes >= 3 || ( matching_bytes == 2 && const_ok_for_op ( remainder & ~ tmp2 , code ) ) ) ) { result = tmp2 ; i = tmp != b1 ? 32 : tmp != b2 ? 24 : tmp != b3 ? 16 : 8 ; } else if ( b1 == b3 && ( ! b2 || ! b4 || ( remainder & 0x00ff0000 & ~ result ) ) ) { result = remainder & 0xff00ff00 ; i = 24 ; } } else if ( loc > 16 ) { if ( b2 == b4 ) { result = remainder & 0x00ff00ff ; i = 16 ; } } } return_sequence -> i [ insns ++ ] = result ; remainder &= ~ result ; if ( code == SET || code == MINUS ) code = PLUS ; } while ( remainder ) ; return insns ; } </s>

As for optimal_immediate_sequence , but starting at bit-position I .


<s> unsigned getEUsPerCU ( ) const { return 4 ; } </s>

Number of SIMDs/EUs ( execution units ) per `` CU '' ( `` compute unit '' ) , where the `` CU '' is the unit onto which workgroups are mapped .


<s> virtual const SPURegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> bool HexagonHazardRecognizer :: ShouldPreferAnother ( SUnit * SU ) { return UsesDotCur && ( ( SU == UsesDotCur ) ^ ( DotCurPNum == ( int ) PacketNum ) ) ; } </s>

ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard .


<s>
static
void
rs6000_xcoff_file_start
(
void
)
{
rs6000_gen_section_name
(
&
xcoff_bss_section_name
,
main_input_filename
,
".bss_"
)
;
rs6000_gen_section_name
(
&
xcoff_private_data_section_name
,
main_input_filename
,
".rw_"
)
;
rs6000_gen_section_name
(
&
xcoff_read_only_section_name
,
main_input_filename
,
".ro_"
)
;
rs6000_gen_section_name
(
&
xcoff_tls_data_section_name
,
main_input_filename
,
".tls_"
)
;
rs6000_gen_section_name
(
&
xcoff_tbss_section_name
,
main_input_filename
,
".tbss_[UL]"
)
;
fputs
(
"\t.file\t"
,
asm_out_file
)
;
output_quoted_string
(
asm_out_file
,
main_input_filename
)
;
fputc
(
'\n'
,
asm_out_file
)
;
if
(
write_symbols
!=
NO_DEBUG
)
switch_to_section
(
private_data_section
)
;
switch_to_section
(
text_section
)
;
if
(
profile_flag
)
fprintf
(
asm_out_file
,
"\t.extern %s\n"
,
RS6000_MCOUNT
)
;
rs6000_file_start
(
)
;
}
</s>

Output at beginning of assembler file . Initialize the section names for the RS/6000 at this point . Specify filename , including full path , to assembler . We want to go into the TOC section so at least one .toc will be emitted . Also , in order to output proper .bs/.es pairs , we need at least one static [ RW ] section emitted . Finally , declare mcount when profiling to make the assembler happy .


<s> static void mn10300_gen_multiple_store ( unsigned int mask ) { static const unsigned int store_order [ 8 ] = { FIRST_EXTENDED_REGNUM + 4 , FIRST_EXTENDED_REGNUM + 5 , FIRST_EXTENDED_REGNUM + 6 , FIRST_EXTENDED_REGNUM + 7 , FIRST_DATA_REGNUM + 2 , FIRST_DATA_REGNUM + 3 , FIRST_ADDRESS_REGNUM + 2 , FIRST_ADDRESS_REGNUM + 3 , } ; rtx x , elts [ 9 ] ; unsigned int i ; int count ; if ( mask == 0 ) return ; for ( i = count = 0 ; i < ARRAY_SIZE ( store_order ) ; ++ i ) { unsigned regno = store_order [ i ] ; if ( ( ( mask >> regno ) & 1 ) == 0 ) continue ; ++ count ; x = plus_constant ( Pmode , stack_pointer_rtx , count * - 4 ) ; x = gen_frame_mem ( SImode , x ) ; x = gen_rtx_SET ( VOIDmode , x , gen_rtx_REG ( SImode , regno ) ) ; elts [ count ] = F ( x ) ; mask &= ~ ( 1u << regno ) ; } gcc_assert ( mask == 0 ) ; x = plus_constant ( Pmode , stack_pointer_rtx , count * - 4 ) ; x = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , x ) ; elts [ 0 ] = F ( x ) ; x = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( count + 1 , elts ) ) ; F ( emit_insn ( x ) ) ; } </s>

Generate an instruction that pushes several registers onto the stack . Register K will be saved if bit K in MASK is set . The function does nothing if MASK is zero . To be compatible with the `` movm '' instruction , the lowest-numbered register must be stored in the lowest slot . If MASK is the set { R1 , ... , RN } , where R1 ... RN are ordered least first , the generated instruction will have the form : ( parallel ( set ( reg : SI 9 ) ( plus : SI ( reg : SI 9 ) ( const_int -N * 4 ) ) ) ( set ( mem : SI ( plus : SI ( reg : SI 9 ) ( const_int -1 * 4 ) ) ) ( reg : SI RN ) ) ... ( set ( mem : SI ( plus : SI ( reg : SI 9 ) ( const_int -N * 4 ) ) ) ( reg : SI R1 ) ) )


<s> bool ARMTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { if ( ! Subtarget -> isThumb ( ) ) return ARM_AM :: getSOImmVal ( Imm ) != - 1 ; if ( Subtarget -> isThumb2 ( ) ) return ARM_AM :: getT2SOImmVal ( Imm ) != - 1 ; return Imm >= 0 && Imm <= 255 ; } </s>

Return true if the specified immediate is legal icmp immediate , that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register .


<s> const PPCTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> BitVector SIRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: EXEC ) ; reserveRegisterTuples ( Reserved , AMDGPU :: FLAT_SCR ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SGPR102_SGPR103 ) ; const AMDGPUSubtarget & ST = MF . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: VOLCANIC_ISLANDS ) { reserveRegisterTuples ( Reserved , AMDGPU :: SGPR98_SGPR99 ) ; reserveRegisterTuples ( Reserved , AMDGPU :: SGPR100_SGPR101 ) ; } if ( ST . hasSGPRInitBug ( ) ) { unsigned NumSGPRs = AMDGPU :: SGPR_32RegClass . getNumRegs ( ) ; unsigned Limit = AMDGPUSubtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - 4 ; for ( unsigned i = Limit ; i < NumSGPRs ; ++ i ) { unsigned Reg = AMDGPU :: SGPR_32RegClass . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } } const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != AMDGPU :: NoRegister ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> static int avr_no_gccisr_function_p ( tree func ) { return avr_lookup_function_attribute1 ( func , "no_gccisr" ) ; } </s>

Return nonzero if FUNC is a no_gccisr function as specified by the `` no_gccisr '' attribute .


<s> bool X86FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = 0 ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + X86FI -> getTCReturnAddrDelta ( ) ; int64_t TailCallReturnAddrDelta = X86FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( this -> TRI -> hasBasePointer ( MF ) ) { if ( MF . hasEHFunclets ( ) ) { int FI = MFI . CreateSpillStackObject ( SlotSize , SlotSize ) ; X86FI -> setHasSEHFramePtrSave ( true ) ; X86FI -> setSEHFramePtrSaveIndex ( FI ) ; } } if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = 0 ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( ! X86 :: GR64RegClass . contains ( Reg ) && ! X86 :: GR32RegClass . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; } X86FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { unsigned Reg = CSI [ i - 1 ] . getReg ( ) ; if ( X86 :: GR64RegClass . contains ( Reg ) || X86 :: GR32RegClass . contains ( Reg ) ) continue ; MVT VT = MVT :: Other ; if ( X86 :: VK16RegClass . contains ( Reg ) ) VT = STI . hasBWI ( ) ? MVT :: v64i1 : MVT :: v16i1 ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg , VT ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; unsigned Align = TRI -> getSpillAlignment ( * RC ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % Align ; SpillSlotOffset -= Size ; int SlotIndex = MFI . CreateFixedSpillStackObject ( Size , SpillSlotOffset ) ; CSI [ i - 1 ] . setFrameIdx ( SlotIndex ) ; MFI . ensureMaxAlignment ( Align ) ; } return true ; } </s>

This function will assign callee saved gprs to volatile vector registers for prologue spills when applicable .


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrMode3
:
{
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
}
case
ARMII
::
AddrModeT1_s
:
{
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
}
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> const uint32_t * AAPRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool X86InstrInfo :: classifyLEAReg ( MachineInstr * MI , const MachineOperand & Src , unsigned Opc , bool AllowSP , unsigned & NewSrc , bool & isKill , bool & isUndef , MachineOperand & ImplicitOp ) const { MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterClass * RC ; if ( AllowSP ) { RC = Opc != X86 :: LEA32r ? & X86 :: GR64RegClass : & X86 :: GR32RegClass ; } else { RC = Opc != X86 :: LEA32r ? & X86 :: GR64_NOSPRegClass : & X86 :: GR32_NOSPRegClass ; } unsigned SrcReg = Src . getReg ( ) ; if ( Opc != X86 :: LEA64_32r ) { NewSrc = SrcReg ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( NewSrc ) && ! MF . getRegInfo ( ) . constrainRegClass ( NewSrc , RC ) ) return false ; return true ; } if ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { ImplicitOp = Src ; ImplicitOp . setImplicit ( ) ; NewSrc = getX86SubSuperRegister ( Src . getReg ( ) , MVT :: i64 ) ; MachineBasicBlock :: LivenessQueryResult LQR = MI -> getParent ( ) -> computeRegisterLiveness ( & getRegisterInfo ( ) , NewSrc , MI ) ; switch ( LQR ) { case MachineBasicBlock :: LQR_Unknown : return false ; case MachineBasicBlock :: LQR_Live : isKill = MI -> killsRegister ( SrcReg ) ; isUndef = false ; break ; default : isKill = false ; isUndef = true ; break ; } } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , X86 :: sub_32bit ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; } return true ; } </s>

Given an operand within a MachineInstr , insert preceding code to put it into the right format for a particular kind of LEA instruction .


<s>
const
TargetRegisterClass
*
M680x0RegisterInfo
::
getMaximalPhysRegClass
(
unsigned
reg
,
MVT
VT
)
const
{
assert
(
isPhysicalRegister
(
reg
)
&&
"reg must be a physical register"
)
;
const
TargetRegisterClass
*
BestRC
=
nullptr
;
for
(
regclass_iterator
I
=
regclass_begin
(
)
,
E
=
regclass_end
(
)
;
I
!=
E
;
++
I
)
{
const
TargetRegisterClass
*
RC
=
*
I
;
if
(
(
VT
==
MVT
::
Other
||
isTypeLegalForClass
(
*
RC
,
VT
)
)
&&
RC
->
contains
(
reg
)
&&
(
!
BestRC
||
(
BestRC
->
hasSubClass
(
RC
)
&&
RC
->
getNumRegs
(
)
>
BestRC
->
getNumRegs
(
)
)
)
)
BestRC
=
RC
;
}
assert
(
BestRC
&&
"Couldn't find the register class"
)
;
return
BestRC
;
}
</s>

Returns the Register Class of a physical register of the given type , picking the biggest register class of the right type that contains this physreg .


<s> void BPFInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { printInstruction ( MI , Address , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> VESubtarget & VESubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { EnableVPU = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = "ve" ; ParseSubtargetFeatures ( CPUName , CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> bool MBlazeTargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ; if ( Kind . isMergeable1ByteCString ( ) ) return false ; const Type * Ty = GV -> getType ( ) -> getElementType ( ) ; return IsInSmallSection ( TM . getTargetData ( ) -> getTypeAllocSize ( Ty ) ) ; } </s>

Return true if this global address should be placed into small data/bss section .


<s> bool SystemZElimCompare :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; bool CompleteCCUsers = ! isCCLiveOut ( MBB ) ; SmallVector < MachineInstr * , 4 > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && ( MI -> isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareAndBranch ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } if ( MI -> definesRegister ( SystemZ :: CC ) ) { CCUsers . clear ( ) ; CompleteCCUsers = true ; } if ( MI -> readsRegister ( SystemZ :: CC ) && CompleteCCUsers ) CCUsers . push_back ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ 4 SystemZ::CC SystemZ::CC


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { return createMBlazeELFObjectWriter ( OS , OSABI ) ; } </s>

Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file .


<s> bool HexagonTargetLowering :: isLegalAddressingMode ( const AddrMode & AM , Type * Ty ) const { if ( AM . BaseOffs <= - ( 1LL << 13 ) || AM . BaseOffs >= ( 1LL << 13 ) - 1 ) { return false ; } if ( AM . BaseGV ) { return false ; } int Scale = AM . Scale ; if ( Scale < 0 ) Scale = - Scale ; switch ( Scale ) { case 0 : break ; default : return false ; } return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> void ARMPassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandLoadLinkedPass ( TM ) ) ; const ARMSubtarget * Subtarget = & getARMSubtarget ( ) ; if ( Subtarget -> hasAnyDataBarrier ( ) && ! Subtarget -> isThumb1Only ( ) ) if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> int frv_expand_block_clear ( rtx operands [ ] ) { rtx orig_dest = operands [ 0 ] ; rtx bytes_rtx = operands [ 1 ] ; rtx align_rtx = operands [ 3 ] ; int constp = ( GET_CODE ( bytes_rtx ) == CONST_INT ) ; int align ; int bytes ; int offset ; rtx dest_reg ; rtx dest_addr ; rtx dest_mem ; int clear_bytes ; machine_mode mode ; if ( ! constp ) return FALSE ; gcc_assert ( GET_CODE ( align_rtx ) == CONST_INT ) ; align = INTVAL ( align_rtx ) ; bytes = INTVAL ( bytes_rtx ) ; if ( bytes <= 0 ) return TRUE ; if ( bytes > TOTAL_MOVE_REG * align ) return FALSE ; dest_reg = copy_addr_to_reg ( XEXP ( orig_dest , 0 ) ) ; offset = 0 ; for ( ; bytes > 0 ; ( bytes -= clear_bytes ) , ( offset += clear_bytes ) ) { dest_addr = ( ( offset == 0 ) ? dest_reg : plus_constant ( Pmode , dest_reg , offset ) ) ; if ( bytes >= 4 && align >= 4 ) mode = SImode ; else if ( bytes >= 2 && align >= 2 ) mode = HImode ; else mode = QImode ; clear_bytes = GET_MODE_SIZE ( mode ) ; dest_mem = change_address ( orig_dest , mode , dest_addr ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest_mem , const0_rtx ) ) ; } return TRUE ; } </s>

Expand a block clear operation , and return 1 if successful . Return 0 if we should let the compiler generate normal code . operands [ 0 ] is the destination operands [ 1 ] is the length operands [ 3 ] is the alignment


<s> void emitAssemblerFlag ( MCAssemblerFlag Flag ) override { MCELFStreamer :: emitAssemblerFlag ( Flag ) ; switch ( Flag ) { case MCAF_SyntaxUnified : return ; case MCAF_Code16 : IsThumb = true ; return ; case MCAF_Code32 : IsThumb = false ; return ; case MCAF_Code64 : return ; case MCAF_SubsectionsViaSymbols : return ; } } </s>


<s>
StringRef
getPassName
(
)
const
override
{
return
"AMDGPU Attributor"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> Value * ARMTargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent ; if ( ValTy -> getPrimitiveSizeInBits ( ) == 64 ) { Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaexd : Intrinsic :: arm_ldrexd ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; Value * LoHi = Builder . CreateCall ( Ldrex , Addr , "lohi" ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 32 ) ) , "val64" ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; Intrinsic :: ID Int = IsAcquire ? Intrinsic :: arm_ldaex : Intrinsic :: arm_ldrex ; Function * Ldrex = llvm :: Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateTruncOrBitCast ( Builder . CreateCall ( Ldrex , Addr ) , cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ) ; } </s>

Perform a load-linked operation on Addr , returning a `` Value * '' with the corresponding pointee type .


<s> static int moxie_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int bytes_left , size ; if ( * cum >= 8 ) return 0 ; if ( moxie_pass_by_reference ( cum_v , arg ) ) size = 4 ; else if ( arg . type ) { if ( AGGREGATE_TYPE_P ( arg . type ) ) return 0 ; size = int_size_in_bytes ( arg . type ) ; } else size = GET_MODE_SIZE ( arg . mode ) ; bytes_left = ( 4 * 6 ) - ( ( * cum - 2 ) * 4 ) ; if ( size > bytes_left ) return bytes_left ; else return 0 ; } </s>

Some function arguments will only partially fit in the registers that hold arguments . Given a new arg , return the number of bytes that fit in argument passing registers .


"Operand must be a register when you're"

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> TargetPassConfig * XCoreTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new XCorePassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> static rtx cr16_libcall_value ( machine_mode mode , const_rtx func ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , cr16_ret_register ( ) ) ; } </s>

Create an RTX representing the place where a library function returns a value of mode MODE .


<s> int RISCVFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const auto * RVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = 0 ; int MaxCSFI = - 1 ; int Offset = MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ; uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = RISCV :: X2 ; if ( FirstSPAdjustAmount ) Offset += FirstSPAdjustAmount ; else Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } else if ( RI -> needsStackRealignment ( MF ) && ! MFI . isFixedObjectIndex ( FI ) ) { if ( hasBP ( MF ) ) FrameReg = RISCVABI :: getBPReg ( ) ; else FrameReg = RISCV :: X2 ; Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } else { FrameReg = RI -> getFrameRegister ( MF ) ; if ( hasFP ( MF ) ) Offset += RVFI -> getVarArgsSaveSize ( ) ; else Offset += MF . getFrameInfo ( ) . getStackSize ( ) ; } return Offset ; } </s>

getFrameIndexReference - This method should return the base register and offset used to reference a frame index location .


<s> bool HexagonInstrInfo :: isPostIncrement ( const MachineInstr * MI ) const { switch ( MI -> getOpcode ( ) ) { default : return false ; case Hexagon :: POST_LDrib : case Hexagon :: POST_LDrib_cPt : case Hexagon :: POST_LDrib_cNotPt : case Hexagon :: POST_LDrib_cdnPt_V4 : case Hexagon :: POST_LDrib_cdnNotPt_V4 : case Hexagon :: POST_LDriub : case Hexagon :: POST_LDriub_cPt : case Hexagon :: POST_LDriub_cNotPt : case Hexagon :: POST_LDriub_cdnPt_V4 : case Hexagon :: POST_LDriub_cdnNotPt_V4 : case Hexagon :: POST_LDrih : case Hexagon :: POST_LDrih_cPt : case Hexagon :: POST_LDrih_cNotPt : case Hexagon :: POST_LDrih_cdnPt_V4 : case Hexagon :: POST_LDrih_cdnNotPt_V4 : case Hexagon :: POST_LDriuh : case Hexagon :: POST_LDriuh_cPt : case Hexagon :: POST_LDriuh_cNotPt : case Hexagon :: POST_LDriuh_cdnPt_V4 : case Hexagon :: POST_LDriuh_cdnNotPt_V4 : case Hexagon :: POST_LDriw : case Hexagon :: POST_LDriw_cPt : case Hexagon :: POST_LDriw_cNotPt : case Hexagon :: POST_LDriw_cdnPt_V4 : case Hexagon :: POST_LDriw_cdnNotPt_V4 : case Hexagon :: POST_LDrid : case Hexagon :: POST_LDrid_cPt : case Hexagon :: POST_LDrid_cNotPt : case Hexagon :: POST_LDrid_cdnPt_V4 : case Hexagon :: POST_LDrid_cdnNotPt_V4 : case Hexagon :: POST_STbri : case Hexagon :: POST_STbri_cPt : case Hexagon :: POST_STbri_cNotPt : case Hexagon :: POST_STbri_cdnPt_V4 : case Hexagon :: POST_STbri_cdnNotPt_V4 : case Hexagon :: POST_SThri : case Hexagon :: POST_SThri_cPt : case Hexagon :: POST_SThri_cNotPt : case Hexagon :: POST_SThri_cdnPt_V4 : case Hexagon :: POST_SThri_cdnNotPt_V4 : case Hexagon :: POST_STwri : case Hexagon :: POST_STwri_cPt : case Hexagon :: POST_STwri_cNotPt : case Hexagon :: POST_STwri_cdnPt_V4 : case Hexagon :: POST_STwri_cdnNotPt_V4 : case Hexagon :: POST_STdri : case Hexagon :: POST_STdri_cPt : case Hexagon :: POST_STdri_cNotPt : case Hexagon :: POST_STdri_cdnPt_V4 : case Hexagon :: POST_STdri_cdnNotPt_V4 : return true ; } } </s>

Return true for post-incremented instructions .


<s> rtx function_expander :: map_to_rtx_codes ( rtx_code code_for_sint , rtx_code code_for_uint , int unspec_for_fp , unsigned int merge_argno ) { machine_mode mode = vector_mode ( 0 ) ; rtx_code code = ( type_suffix ( 0 ) . unsigned_p ? code_for_uint : code_for_sint ) ; insn_code icode ; if ( type_suffix ( 0 ) . tclass == TYPE_bool ) { gcc_assert ( pred == PRED_z && code_for_uint == code_for_sint ) ; return use_exact_insn ( code_for_aarch64_pred_z ( code , mode ) ) ; } if ( pred == PRED_x ) { if ( type_suffix ( 0 ) . integer_p ) icode = maybe_code_for_aarch64_pred ( code , mode ) ; else icode = maybe_code_for_aarch64_pred ( unspec_for_fp , mode ) ; if ( icode != CODE_FOR_nothing ) return use_pred_x_insn ( icode ) ; } if ( pred == PRED_none || pred == PRED_x ) { icode = direct_optab_handler ( code_to_optab ( code ) , 0 ) ; if ( icode == CODE_FOR_nothing ) icode = code_for_aarch64_sve ( code , mode ) ; return use_unpred_insn ( icode ) ; } if ( type_suffix ( 0 ) . integer_p ) icode = code_for_cond ( code , mode ) ; else icode = code_for_cond ( unspec_for_fp , mode ) ; return use_cond_insn ( icode , merge_argno ) ; } </s>

Implement the call using one of the following strategies , chosen in order : ( 1 ) `` aarch64_pred_ < optab > < mode > _z '' for PRED_z predicate functions ( 2 ) `` aarch64_pred_ < optab > < mode > '' for PRED_x functions ( 3 ) a normal unpredicated optab for PRED_none and PRED_x functions , dropping the predicate in the latter case ( 4 ) an unpredicated `` aarch64_sve_ < code_optab > < mode > '' for PRED_none and PRED_x functions , again dropping the predicate for PRED_x ( 5 ) `` cond_ < optab > < mode > '' otherwise where < optab > corresponds to : - CODE_FOR_SINT for signed integers - CODE_FOR_UINT for unsigned integers - UNSPEC_FOR_FP for floating-point values and where < code_optab > is like < optab > , but uses CODE_FOR_SINT instead of UNSPEC_FOR_FP for floating-point values . MERGE_ARGNO is the argument that provides the values of inactive lanes for _m functions , or DEFAULT_MERGE_ARGNO if we should apply the usual rules .


<s>
static
void
handle_special_swappables
(
swap_web_entry
*
insn_entry
,
unsigned
i
)
{
rtx_insn
*
insn
=
insn_entry
[
i
]
.
insn
;
rtx
body
=
PATTERN
(
insn
)
;
switch
(
insn_entry
[
i
]
.
special_handling
)
{
default
:
gcc_unreachable
(
)
;
case
SH_CONST_VECTOR
:
{
gcc_assert
(
GET_CODE
(
body
)
==
SET
)
;
swap_const_vector_halves
(
&
SET_SRC
(
body
)
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Swapping constant halves in insn %d\n"
,
i
)
;
break
;
}
case
SH_SUBREG
:
adjust_subreg_index
(
body
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Adjusting subreg in insn %d\n"
,
i
)
;
break
;
case
SH_NOSWAP_LD
:
permute_load
(
insn
)
;
break
;
case
SH_NOSWAP_ST
:
permute_store
(
insn
)
;
break
;
case
SH_EXTRACT
:
adjust_extract
(
insn
)
;
break
;
case
SH_SPLAT
:
adjust_splat
(
insn
)
;
break
;
case
SH_XXPERMDI
:
adjust_xxpermdi
(
insn
)
;
break
;
case
SH_CONCAT
:
adjust_concat
(
insn
)
;
break
;
case
SH_VPERM
:
adjust_vperm
(
insn
)
;
break
;
}
}
</s>

The insn described by INSN_ENTRY [ I ] can be swapped , but only with special handling . Take care of that here .

rs6000
"Swapping constant halves in insn %d\n"
"Adjusting subreg in insn %d\n"


<s> static int h8300_interrupt_function_p ( tree func ) { tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return 0 ; a = lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( func ) ) ; return a != NULL_TREE ; } </s>

Return nonzero if FUNC is an interrupt function as specified by the `` interrupt '' attribute .


<s> inline static bool isMem ( const MachineInstr * MI , unsigned Op ) { if ( MI -> getOperand ( Op ) . isFI ( ) ) return true ; return Op + 5 <= MI -> getNumOperands ( ) && MI -> getOperand ( Op + 4 ) . isReg ( ) && isLeaMem ( MI , Op ) ; } </s>


<s> void msp430_output_aligned_decl_common ( FILE * stream , const tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { if ( msp430_data_region == MSP430_REGION_ANY ) { fprintf ( stream , COMMON_ASM_OP ) ; assemble_name ( stream , name ) ; fprintf ( stream , "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n" , size , align / BITS_PER_UNIT ) ; } else { section * sec ; if ( decl ) sec = msp430_select_section ( decl , 0 , align ) ; else switch ( msp430_data_region ) { case MSP430_REGION_UPPER : sec = get_named_section ( NULL , ".upper.bss" , 0 ) ; break ; case MSP430_REGION_LOWER : sec = get_named_section ( NULL , ".lower.bss" , 0 ) ; break ; case MSP430_REGION_EITHER : sec = get_named_section ( NULL , ".either.bss" , 0 ) ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( sec != NULL ) ; switch_to_section ( sec ) ; ASM_OUTPUT_ALIGN ( stream , floor_log2 ( align / BITS_PER_UNIT ) ) ; targetm . asm_out . globalize_label ( stream , name ) ; ASM_WEAKEN_LABEL ( stream , name ) ; ASM_OUTPUT_LABEL ( stream , name ) ; ASM_OUTPUT_SKIP ( stream , size ? size : 1 ) ; } } </s>

Emit a declaration of a common symbol . If a data region is in use then put the symbol into the equivalent .bss section instead . If LOCAL is 1 , then DECL is for a local common variable .


<s> const char * tilepro_asm_output_opcode ( FILE * stream , const char * code ) { bool pseudo = ! strcmp ( code , "pseudo" ) ; if ( ! tilepro_in_bundle && insn_mode == SImode ) { fprintf ( stream , "{\n\t" ) ; tilepro_in_bundle = true ; } if ( tilepro_in_bundle && insn_mode == QImode ) { static char buf [ 100 ] ; gcc_assert ( strlen ( code ) + 3 + 1 < sizeof ( buf ) ) ; strcpy ( buf , pseudo ? "" : code ) ; strcat ( buf , "\n\t}" ) ; tilepro_in_bundle = false ; return buf ; } else { return pseudo ? "" : code ; } } </s>

Implement ASM_OUTPUT_OPCODE . Prepend/append curly braces as appropriate given the bundling information recorded by tilepro_gen_bundles .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { TII = MF . getSubtarget < R600Subtarget > ( ) . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; LLVM_DEBUG ( MF . dump ( ) ; ) ; OrderedBlks . clear ( ) ; Visited . clear ( ) ; FuncRep = & MF ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; LLVM_DEBUG ( dbgs ( ) << "LoopInfo:\n" ; PrintLoopinfo ( * MLI ) ; ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; LLVM_DEBUG ( MDT -> print ( dbgs ( ) , ( const Module * ) nullptr ) ; ) ; PDT = & getAnalysis < MachinePostDominatorTree > ( ) ; LLVM_DEBUG ( PDT -> print ( dbgs ( ) ) ; ) ; prepare ( ) ; run ( ) ; LLVM_DEBUG ( MF . dump ( ) ; ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


"Inserting vccz bug work-around before: "


<s> StackOffset MipsSEFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; if ( MFI . isFixedObjectIndex ( FI ) ) FrameReg = hasFP ( MF ) ? ABI . GetFramePtr ( ) : ABI . GetStackPtr ( ) ; else FrameReg = hasBP ( MF ) ? ABI . GetBasePtr ( ) : ABI . GetStackPtr ( ) ; return StackOffset :: getFixed ( MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) - getOffsetOfLocalArea ( ) + MFI . getOffsetAdjustment ( ) ) ; } </s>


<s>
static
void
frv_function_prologue
(
FILE
*
file
,
HOST_WIDE_INT
size
ATTRIBUTE_UNUSED
)
{
rtx_insn
*
insn
,
*
next
,
*
last_call
;
if
(
frv_stack_info
(
)
->
total_size
==
0
&&
frv_function_contains_far_jump
(
)
)
{
rtx_insn
*
insn
;
gcc_assert
(
!
df_regs_ever_live_p
(
GPR_FIRST
+
3
)
)
;
fprintf
(
file
,
"\tmovsg lr,gr3\n"
)
;
for
(
insn
=
get_insns
(
)
;
insn
!=
;
insn
=
NEXT_INSN
(
insn
)
)
if
(
JUMP_P
(
insn
)
)
{
rtx
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
&&
XVECLEN
(
pattern
,
0
)
>=
2
&&
GET_CODE
(
XVECEXP
(
pattern
,
0
,
0
)
)
==
RETURN
&&
GET_CODE
(
XVECEXP
(
pattern
,
0
,
1
)
)
==
USE
)
{
rtx
address
=
XEXP
(
XVECEXP
(
pattern
,
0
,
1
)
,
0
)
;
if
(
GET_CODE
(
address
)
==
REG
&&
REGNO
(
address
)
==
LR_REGNO
)
SET_REGNO
(
address
,
GPR_FIRST
+
3
)
;
}
}
}
frv_pack_insns
(
)
;
memset
(
frv_nops
,
0
,
sizeof
(
frv_nops
)
)
;
last_call
=
;
for
(
insn
=
get_insns
(
)
;
insn
;
insn
=
next
)
{
next
=
NEXT_INSN
(
insn
)
;
if
(
CALL_P
(
insn
)
||
(
INSN_P
(
insn
)
&&
GET_CODE
(
PATTERN
(
insn
)
)
==
SEQUENCE
&&
CALL_P
(
XVECEXP
(
PATTERN
(
insn
)
,
0
,
0
)
)
)
)
last_call
=
insn
;
if
(
!
NOTE_P
(
insn
)
||
NOTE_KIND
(
insn
)
!=
NOTE_INSN_CALL_ARG_LOCATION
)
continue
;
if
(
NEXT_INSN
(
last_call
)
==
insn
)
continue
;
SET_NEXT_INSN
(
PREV_INSN
(
insn
)
)
=
NEXT_INSN
(
insn
)
;
SET_PREV_INSN
(
NEXT_INSN
(
insn
)
)
=
PREV_INSN
(
insn
)
;
SET_PREV_INSN
(
insn
)
=
last_call
;
SET_NEXT_INSN
(
insn
)
=
NEXT_INSN
(
last_call
)
;
SET_PREV_INSN
(
NEXT_INSN
(
insn
)
)
=
insn
;
SET_NEXT_INSN
(
PREV_INSN
(
insn
)
)
=
insn
;
last_call
=
insn
;
}
}
</s>

For the FRV , this function makes sure that a function with far jumps will return correctly . It also does the VLIW packing .


<s> MachineBasicBlock * canonicalize ( MachineBasicBlock * MBB ) { MachineLoop * InnerLoop = MLI . getLoopFor ( MBB ) ; if ( InnerLoop == Loop ) { return MBB ; } else { if ( ! LoopBlocks . count ( MBB ) ) { return nullptr ; } assert ( InnerLoop ) ; return InnerLoop -> getHeader ( ) ; } } </s>

Form a canonical key for the specified mangling .


<s> int compute_frame_size ( int size , long * p_reg_saved ) { return ( size + compute_register_save_size ( p_reg_saved ) + current_function_outgoing_args_size ) ; } </s>

Typical stack layout should looks like this after the function 's prologue : | | -- ^ | | \ | | | arguments saved | Increasing | | on the stack | addresses PARENT arg pointer - > | | / -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - | | - space for argument split between regs & stack -- CHILD | | \ < -- ( return address here ) | | other call | | saved registers | | / -- frame pointer - > | | \ ___ | | local | | | variables |f | | / |r -- |a | | \ |m | | outgoing |e | | arguments | | Decreasing ( hard ) frame pointer | | / | | addresses and stack pointer - > | | / _|_ | -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- V


<s> bool WebAssemblyTargetLowering :: allowsMisalignedMemoryAccesses ( EVT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ; } </s>

Returns true if the target allows unaligned memory accesses of the specified type .


<s> unsigned AMDGPUInstrInfo :: isLoadFromStackSlotPostFE ( const MachineInstr * MI , int & FrameIndex ) const { return 0 ; } </s>

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Alpha NOP inserter"
;
}
</s>

getPassName - Return a nice clean name for a pass .


"passing %qT to argument %d of %qE, which"

Require argument ARGNO to be a ( possibly variable ) scalar , using EXPECTED as the name of its expected type . Return true if the argument has the right form , otherwise report an appropriate error .


<s> unsigned MipsRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { switch ( RC -> getID ( ) ) { default : return 0 ; case Mips :: CPURegsRegClassID : case Mips :: CPU64RegsRegClassID : case Mips :: DSPRegsRegClassID : { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return 28 - TFI -> hasFP ( MF ) ; } case Mips :: FGR32RegClassID : return 32 ; case Mips :: AFGR64RegClassID : return 16 ; case Mips :: FGR64RegClassID : return 32 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s>
MachineBasicBlock
*
SystemZTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
SystemZInstrInfo
&
TII
=
*
TM
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
SystemZ
::
Select32
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF32
||
MI
->
getOpcode
(
)
==
SystemZ
::
Select64
||
MI
->
getOpcode
(
)
==
SystemZ
::
SelectF64
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
SystemZCC
::
CondCodes
CC
=
(
SystemZCC
::
CondCodes
)
MI
->
getOperand
(
3
)
.
getImm
(
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
getBrCond
(
CC
)
)
.
addMBB
(
copy1MBB
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
SystemZ
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static void emit_frame_save ( rtx frame_reg , rtx frame_ptr , enum machine_mode mode , unsigned int regno , int offset , HOST_WIDE_INT total_size ) { rtx reg , offset_rtx , insn , mem , addr , int_rtx ; rtx replacea , replaceb ; int_rtx = GEN_INT ( offset ) ; if ( ( TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE ( mode ) ) || ( TARGET_E500_DOUBLE && mode == DFmode ) || ( TARGET_SPE_ABI && SPE_VECTOR_MODE ( mode ) && ! SPE_CONST_OFFSET_OK ( offset ) ) ) { offset_rtx = gen_rtx_REG ( Pmode , 11 ) ; emit_move_insn ( offset_rtx , int_rtx ) ; replacea = offset_rtx ; replaceb = int_rtx ; } else { offset_rtx = int_rtx ; replacea = NULL_RTX ; replaceb = NULL_RTX ; } reg = gen_rtx_REG ( mode , regno ) ; addr = gen_rtx_PLUS ( Pmode , frame_reg , offset_rtx ) ; mem = gen_rtx_MEM ( mode , addr ) ; set_mem_alias_set ( mem , rs6000_sr_alias_set ) ; insn = emit_move_insn ( mem , reg ) ; rs6000_frame_related ( insn , frame_ptr , total_size , replacea , replaceb ) ; } </s>

Save a register into the frame , and emit RTX_FRAME_RELATED_P notes . Save REGNO into [ FRAME_REG + OFFSET ] in mode MODE .


"RISCV DAG->DAG Pattern Instruction Selection"


<s> bool GBZ80FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc dl ; if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; i ++ ) BuildMI ( MBB , MI , dl , TII . get ( GBZ80 :: POP16r ) , CSI [ i ] . getReg ( ) ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> void MipsSETargetLowering :: addMSAFloatType ( MVT :: SimpleValueType Ty , const TargetRegisterClass * RC ) { addRegisterClass ( Ty , RC ) ; for ( unsigned Opc = 0 ; Opc < ISD :: BUILTIN_OP_END ; ++ Opc ) setOperationAction ( Opc , Ty , Expand ) ; setOperationAction ( ISD :: LOAD , Ty , Legal ) ; setOperationAction ( ISD :: STORE , Ty , Legal ) ; setOperationAction ( ISD :: BITCAST , Ty , Legal ) ; setOperationAction ( ISD :: EXTRACT_VECTOR_ELT , Ty , Legal ) ; setOperationAction ( ISD :: INSERT_VECTOR_ELT , Ty , Legal ) ; setOperationAction ( ISD :: BUILD_VECTOR , Ty , Custom ) ; if ( Ty != MVT :: v8f16 ) { setOperationAction ( ISD :: FABS , Ty , Legal ) ; setOperationAction ( ISD :: FADD , Ty , Legal ) ; setOperationAction ( ISD :: FDIV , Ty , Legal ) ; setOperationAction ( ISD :: FEXP2 , Ty , Legal ) ; setOperationAction ( ISD :: FLOG2 , Ty , Legal ) ; setOperationAction ( ISD :: FMA , Ty , Legal ) ; setOperationAction ( ISD :: FMUL , Ty , Legal ) ; setOperationAction ( ISD :: FRINT , Ty , Legal ) ; setOperationAction ( ISD :: FSQRT , Ty , Legal ) ; setOperationAction ( ISD :: FSUB , Ty , Legal ) ; setOperationAction ( ISD :: VSELECT , Ty , Legal ) ; setOperationAction ( ISD :: SETCC , Ty , Legal ) ; setCondCodeAction ( ISD :: SETOGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETOGT , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETUGT , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGE , Ty , Expand ) ; setCondCodeAction ( ISD :: SETGT , Ty , Expand ) ; } } </s>

Enable MSA support for the given floating-point type and Register class .

Mips Mips MVT::SimpleValueType 0 ISD::BUILTIN_OP_END ISD::LOAD ISD::STORE ISD::BITCAST ISD::EXTRACT_VECTOR_ELT ISD::INSERT_VECTOR_ELT ISD::BUILD_VECTOR MVT::v8f16 ISD::FABS ISD::FADD ISD::FDIV ISD::FEXP2 ISD::FLOG2 ISD::FMA ISD::FMUL ISD::FRINT ISD::FSQRT ISD::FSUB ISD::VSELECT ISD::SETCC ISD::SETOGE ISD::SETOGT ISD::SETUGE ISD::SETUGT ISD::SETGE ISD::SETGT


<s> bool isMem ( ) const override { return false ; } </s>


<s> std :: pair < MachineBasicBlock * , MachineBasicBlock * > SILowerControlFlow :: splitBlock ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * LoopBB = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF -> CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF -> insert ( MBBI , LoopBB ) ; MF -> insert ( MBBI , RemainderBB ) ; RemainderBB -> transferSuccessors ( & MBB ) ; RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , I , MBB . end ( ) ) ; MBB . addSuccessor ( LoopBB ) ; return std :: make_pair ( LoopBB , RemainderBB ) ; } </s>

splitBlock - BB is split and now it has one successor .


<s> std :: string getDataLayout ( ) const { const char * p ; p = "e-p:32:32:32-i32:32:32" ; return std :: string ( p ) ; } </s>

Return the DataLayout associated with the module this SCEV instance is operating on .


<s> static void sh_override_options_after_change ( void ) { if ( flag_align_loops && ! str_align_loops ) str_align_loops = optimize_size ? "2" : "4" ; parse_alignment_opts ( ) ; if ( flag_align_jumps && ! str_align_jumps ) str_align_jumps = "2" ; else if ( align_jumps . levels [ 0 ] . get_value ( ) < 2 ) str_align_jumps = "2" ; if ( flag_align_functions && ! str_align_functions ) str_align_functions = optimize_size ? "2" : "4" ; if ( TARGET_RELAX ) { parse_alignment_opts ( ) ; int min_align = MAX ( align_loops . levels [ 0 ] . get_value ( ) , align_jumps . levels [ 0 ] . get_value ( ) ) ; if ( min_align < 4 ) min_align = 4 ; if ( align_functions . levels [ 0 ] . get_value ( ) < min_align ) { char * r = XNEWVEC ( char , 16 ) ; sprintf ( r , "%d" , min_align ) ; str_align_functions = r ; } } } </s>


<s> HOST_WIDE_INT rs6000_initial_elimination_offset ( int from , int to ) { rs6000_stack_t * info = rs6000_stack_info ( ) ; HOST_WIDE_INT offset ; if ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? 0 : - info -> total_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { offset = info -> push_p ? 0 : - info -> total_size ; if ( FRAME_GROWS_DOWNWARD ) offset += info -> fixed_size + info -> vars_size + info -> parm_size ; } else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = FRAME_GROWS_DOWNWARD ? info -> fixed_size + info -> vars_size + info -> parm_size : 0 ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = info -> total_size ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? info -> total_size : 0 ; else if ( from == RS6000_PIC_OFFSET_TABLE_REGNUM ) offset = 0 ; else gcc_unreachable ( ) ; return offset ; } </s>

Define the offset between two registers , FROM to be eliminated and its replacement TO , at the start of a routine .


<s> static void output_stack_adjust ( int direction , int size ) { if ( size ) { rtx val = GEN_INT ( size * direction ) ; rtx insn ; insn = ( TARGET_BIG ? gen_addpsi3 : gen_addhi3 ) ( stack_pointer_rtx , stack_pointer_rtx , val ) ; emit_insn ( insn ) ; } } </s>

Adjust the stack and return the number of bytes taken to do it


<s>
void
Thumb1InstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
DebugLoc
::
getUnknownLoc
(
)
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
assert
(
(
RC
==
ARM
::
tGPRRegisterClass
||
(
TargetRegisterInfo
::
isPhysicalRegister
(
SrcReg
)
&&
isARMLowRegister
(
SrcReg
)
)
)
&&
"Unknown regclass!"
)
;
if
(
RC
==
ARM
::
tGPRRegisterClass
)
{
AddDefaultPred
(
BuildMI
(
MBB
,
I
,
DL
,
get
(
ARM
::
tSpill
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
)
;
}
}
</s>

Store the specified register of the given register class to the specified stack frame index .

ARM
ARM::tGPRRegisterClass
ARM
"Unknown regclass!"
ARM::tGPRRegisterClass
ARM::tSpill
0


<s> bool X86AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { if ( isParsingIntelSyntax ( ) ) return MatchAndEmitIntelInstruction ( IDLoc , Opcode , Operands , Out , ErrorInfo , MatchingInlineAsm ) ; return MatchAndEmitATTInstruction ( IDLoc , Opcode , Operands , Out , ErrorInfo , MatchingInlineAsm ) ; } </s>

MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst and emit it to the specified MCStreamer .


<s> const TargetRegisterClass * MipsSETargetLowering :: getRepRegClassFor ( MVT VT ) const { if ( VT == MVT :: Untyped ) return Subtarget -> hasDSP ( ) ? & Mips :: ACC64DSPRegClass : & Mips :: ACC64RegClass ; return TargetLowering :: getRepRegClassFor ( VT ) ; } </s>

Return the 'representative ' register class for the specified value type .


<s> unsigned GCNSubtarget :: getOccupancyWithNumVGPRs ( unsigned VGPRs ) const { if ( VGPRs <= 24 ) return 10 ; if ( VGPRs <= 28 ) return 9 ; if ( VGPRs <= 32 ) return 8 ; if ( VGPRs <= 36 ) return 7 ; if ( VGPRs <= 40 ) return 6 ; if ( VGPRs <= 48 ) return 5 ; if ( VGPRs <= 64 ) return 4 ; if ( VGPRs <= 84 ) return 3 ; if ( VGPRs <= 128 ) return 2 ; return 1 ; } </s>

Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs .


<s>
static
void
rs6000_file_start
(
void
)
{
char
buffer
[
80
]
;
const
char
*
start
=
buffer
;
FILE
*
file
=
asm_out_file
;
rs6000_default_cpu
=
TARGET_CPU_DEFAULT
;
default_file_start
(
)
;
if
(
flag_verbose_asm
)
{
sprintf
(
buffer
,
"\n%s rs6000/powerpc options:"
,
ASM_COMMENT_START
)
;
if
(
rs6000_default_cpu
!=
0
&&
rs6000_default_cpu
[
0
]
!=
'\0'
)
{
fprintf
(
file
,
"%s --with-cpu=%s"
,
start
,
rs6000_default_cpu
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_cpu_index
)
{
fprintf
(
file
,
"%s -mcpu=%s"
,
start
,
processor_target_table
[
rs6000_cpu_index
]
.
name
)
;
start
=
""
;
}
if
(
global_options_set
.
x_rs6000_tune_index
)
{
fprintf
(
file
,
"%s -mtune=%s"
,
start
,
processor_target_table
[
rs6000_tune_index
]
.
name
)
;
start
=
""
;
}
if
(
PPC405_ERRATUM77
)
{
fprintf
(
file
,
"%s PPC405CR_ERRATUM77"
,
start
)
;
start
=
""
;
}
switch
(
rs6000_sdata
)
{
case
SDATA_NONE
:
fprintf
(
file
,
"%s -msdata=none"
,
start
)
;
start
=
""
;
break
;
case
SDATA_DATA
:
fprintf
(
file
,
"%s -msdata=data"
,
start
)
;
start
=
""
;
break
;
case
SDATA_SYSV
:
fprintf
(
file
,
"%s -msdata=sysv"
,
start
)
;
start
=
""
;
break
;
case
SDATA_EABI
:
fprintf
(
file
,
"%s -msdata=eabi"
,
start
)
;
start
=
""
;
break
;
}
if
(
rs6000_sdata
&&
g_switch_value
)
{
fprintf
(
file
,
"%s -G %d"
,
start
,
g_switch_value
)
;
start
=
""
;
}
if
(
*
start
==
'\0'
)
putc
(
'\n'
,
file
)
;
}
if
(
!
(
rs6000_default_cpu
&&
rs6000_default_cpu
[
0
]
)
&&
!
global_options_set
.
x_rs6000_cpu_index
)
{
fputs
(
"\t.machine "
,
asm_out_file
)
;
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MODULO
)
!=
0
)
fputs
(
"power9\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_DIRECT_MOVE
)
!=
0
)
fputs
(
"power8\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTD
)
!=
0
)
fputs
(
"power7\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_CMPB
)
!=
0
)
fputs
(
"power6\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POPCNTB
)
!=
0
)
fputs
(
"power5\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_MFCRF
)
!=
0
)
fputs
(
"power4\n"
,
asm_out_file
)
;
else
if
(
(
rs6000_isa_flags
&
OPTION_MASK_POWERPC64
)
!=
0
)
fputs
(
"ppc64\n"
,
asm_out_file
)
;
else
fputs
(
"ppc\n"
,
asm_out_file
)
;
}
if
(
DEFAULT_ABI
==
ABI_ELFv2
)
fprintf
(
file
,
"\t.abiversion 2\n"
)
;
}
</s>

Do anything needed at the start of the asm file .


"********** Replace Physical Registers **********\n"

"LiveIntervals shouldn't be active yet!"

runOnMachineFunction - Emit the function body .


<s>
void
AArch64InstrInfo
::
suppressLdStPair
(
MachineInstr
*
MI
)
const
{
if
(
MI
->
memoperands_empty
(
)
)
return
;
static_assert
(
MOSuppressPair
<
(
1
<<
MachineMemOperand
::
MOTargetNumBits
)
,
"Too many target MO flags"
)
;
(
*
MI
->
memoperands_begin
(
)
)
->
setFlags
(
MOSuppressPair
<<
MachineMemOperand
::
MOTargetStartBit
)
;
}
</s>

Hint that pairing the given load or store is unprofitable .


<s> rtx s390_load_got ( void ) { rtx insns ; if ( ! got_symbol ) { got_symbol = gen_rtx_SYMBOL_REF ( Pmode , "_GLOBAL_OFFSET_TABLE_" ) ; SYMBOL_REF_FLAGS ( got_symbol ) = SYMBOL_FLAG_LOCAL ; } start_sequence ( ) ; if ( TARGET_CPU_ZARCH ) { emit_move_insn ( pic_offset_table_rtx , got_symbol ) ; } else { rtx offset ; offset = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , got_symbol ) , UNSPEC_LTREL_OFFSET ) ; offset = gen_rtx_CONST ( Pmode , offset ) ; offset = force_const_mem ( Pmode , offset ) ; emit_move_insn ( pic_offset_table_rtx , offset ) ; offset = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , XEXP ( offset , 0 ) ) , UNSPEC_LTREL_BASE ) ; offset = gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , offset ) ; emit_move_insn ( pic_offset_table_rtx , offset ) ; } insns = get_insns ( ) ; end_sequence ( ) ; return insns ; } </s>

Return insn sequence to load the GOT register .


<s> void SparcRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == 0 && "Unexpected" ) ; MachineInstr & MI = * II ; DebugLoc dl = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const SparcSubtarget & Subtarget = MF . getSubtarget < SparcSubtarget > ( ) ; const SparcFrameLowering * TFI = getFrameLowering ( MF ) ; Register FrameReg ; int Offset ; Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; Offset += MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; if ( ! Subtarget . isV9 ( ) || ! Subtarget . hasHardQuad ( ) ) { if ( MI . getOpcode ( ) == SP :: STQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register SrcReg = MI . getOperand ( 2 ) . getReg ( ) ; Register SrcEvenReg = getSubReg ( SrcReg , SP :: sub_even64 ) ; Register SrcOddReg = getSubReg ( SrcReg , SP :: sub_odd64 ) ; MachineInstr * StMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: STDFri ) ) . addReg ( FrameReg ) . addImm ( 0 ) . addReg ( SrcEvenReg ) ; replaceFI ( MF , * StMI , * StMI , dl , 0 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: STDFri ) ) ; MI . getOperand ( 2 ) . setReg ( SrcOddReg ) ; Offset += 8 ; } else if ( MI . getOpcode ( ) == SP :: LDQFri ) { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; Register DestReg = MI . getOperand ( 0 ) . getReg ( ) ; Register DestEvenReg = getSubReg ( DestReg , SP :: sub_even64 ) ; Register DestOddReg = getSubReg ( DestReg , SP :: sub_odd64 ) ; MachineInstr * LdMI = BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( SP :: LDDFri ) , DestEvenReg ) . addReg ( FrameReg ) . addImm ( 0 ) ; replaceFI ( MF , * LdMI , * LdMI , dl , 1 , Offset , FrameReg ) ; MI . setDesc ( TII . get ( SP :: LDDFri ) ) ; MI . getOperand ( 0 ) . setReg ( DestOddReg ) ; Offset += 8 ; } } replaceFI ( MF , II , MI , dl , FIOperandNum , Offset , FrameReg ) ; } </s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
const
static
MCFixupKindInfo
Infos
[
ARM
::
NumTargetFixupKinds
]
=
{
{
"fixup_arm_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_ldst_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_pcrel_10_unscaled"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_pcrel_10"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_thumb_adr_pcrel_10"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_adr_pcrel_12"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
|
MCFixupKindInfo
::
FKF_IsAlignedDownTo32Bits
}
,
{
"fixup_arm_condbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbranch"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_condbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_uncondbranch"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_br"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_uncondbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_condbl"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_blx"
,
0
,
24
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bl"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_blx"
,
0
,
32
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cb"
,
0
,
16
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_cp"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_thumb_bcc"
,
0
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movt_hi16"
,
0
,
20
,
0
}
,
{
"fixup_t2_movw_lo16"
,
0
,
20
,
0
}
,
{
"fixup_arm_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_arm_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movt_hi16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_t2_movw_lo16_pcrel"
,
0
,
20
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static bool avr_print_operand_punct_valid_p ( unsigned char code ) { return code == '~' || code == '!' ; } </s>

Implement ` TARGET_PRINT_OPERAND_PUNCT_VALID_P ' .


<s> bool Error ( SMLoc L , const Twine & Msg ) { return Parser . Error ( L , Msg ) ; } </s>

Return an error at the location L , with the message Msg .


<s> enum calling_abi ix86_cfun_abi ( void ) { if ( ! cfun ) return ix86_abi ; return cfun -> machine -> call_abi ; } </s>

Returns value SYSV_ABI , MS_ABI dependent on cfun , specifying the call abi used .


<s> unsigned getNumFixupKinds ( ) const override { return RISCV :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> void Z80oldPassConfig :: addCodeGenPrepare ( ) { addPass ( createLowerSwitchPass ( ) ) ; TargetPassConfig :: addCodeGenPrepare ( ) ; } </s>

Add pass to prepare the LLVM IR for code generation .


<s> void visium_expand_fp_cstore ( rtx * operands , machine_mode mode ATTRIBUTE_UNUSED ) { enum rtx_code code = GET_CODE ( operands [ 1 ] ) ; rtx op0 = operands [ 0 ] , op1 = operands [ 2 ] , op2 = operands [ 3 ] , slt ; bool reverse = false ; switch ( code ) { case UNLE : case UNGE : code = reverse_condition_maybe_unordered ( code ) ; reverse = true ; case LT : case GT : if ( code == GT ) { rtx tmp = op1 ; op1 = op2 ; op2 = tmp ; } break ; default : gcc_unreachable ( ) ; } slt = gen_rtx_LT ( SImode , op1 , op2 ) ; if ( reverse ) { rtx tmp = copy_to_mode_reg ( SImode , gen_rtx_NEG ( SImode , slt ) ) ; emit_insn ( gen_add3_insn ( op0 , tmp , const1_rtx ) ) ; } else emit_insn ( gen_rtx_SET ( op0 , slt ) ) ; } </s>

Expand a cstore of OPERANDS in MODE for LT/GT/UNGE/UNLE . We generate the result in the C flag and use the ADC/SUBC instructions to write it into the destination register .


This function is used to print CPU tuning information as comment in assembler file . Pointers are not printed for now .


<s>
uint32_t
AMDGPUTargetLowering
::
getImplicitParameterOffset
(
const
MachineFunction
&
MF
,
const
ImplicitParameter
Param
)
const
{
const
AMDGPUMachineFunction
*
MFI
=
MF
.
getInfo
<
AMDGPUMachineFunction
>
(
)
;
const
AMDGPUSubtarget
&
ST
=
MF
.
getSubtarget
<
AMDGPUSubtarget
>
(
)
;
unsigned
ExplicitArgOffset
=
ST
.
getExplicitKernelArgOffset
(
MF
.
getFunction
(
)
)
;
unsigned
Alignment
=
ST
.
getAlignmentForImplicitArgPtr
(
)
;
uint64_t
ArgOffset
=
alignTo
(
MFI
->
getExplicitKernArgSize
(
)
,
Alignment
)
+
ExplicitArgOffset
;
switch
(
Param
)
{
case
GRID_DIM
:
return
ArgOffset
;
case
GRID_OFFSET
:
return
ArgOffset
+
4
;
}
llvm_unreachable
(
"unexpected implicit parameter type"
)
;
}
</s>

Helper function that returns the byte offset of the given type of implicit parameter .

AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
AMDGPU
4
"unexpected implicit parameter type"


<s> unsigned MipsFunctionInfo :: getGlobalBaseReg ( ) { if ( GlobalBaseReg ) return GlobalBaseReg ; const MipsSubtarget & ST = MF . getTarget ( ) . getSubtarget < MipsSubtarget > ( ) ; const TargetRegisterClass * RC ; if ( ST . inMips16Mode ( ) ) RC = ( const TargetRegisterClass * ) & Mips :: CPU16RegsRegClass ; else RC = ST . isABI_N64 ( ) ? ( const TargetRegisterClass * ) & Mips :: GPR64RegClass : ( const TargetRegisterClass * ) & Mips :: GPR32RegClass ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> void aarch64_register_pragmas ( void ) { targetm . target_option . pragma_parse = aarch64_pragma_target_parse ; targetm . resolve_overloaded_builtin = aarch64_resolve_overloaded_builtin ; targetm . check_builtin_call = aarch64_check_builtin_call ; c_register_pragma ( "GCC" , "aarch64" , aarch64_pragma_aarch64 ) ; } </s>


<s> void X86InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { const MachineFunction & MF = * MBB . getParent ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= 16 ) || RI . needsStackRealignment ( MF ) ; unsigned Opc = getStoreRegOpcode ( RC , isAligned ) ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , false , false , isKill ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> unsigned SIInstrInfo :: getNumWaitStates ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { default : if ( MI . isMetaInstruction ( ) ) return 0 ; return 1 ; case AMDGPU :: S_NOP : return MI . getOperand ( 0 ) . getImm ( ) + 1 ; case AMDGPU :: SI_MASKED_UNREACHABLE : case AMDGPU :: WAVE_BARRIER : case AMDGPU :: SCHED_BARRIER : return 0 ; } } </s>

Return the number of wait states that result from executing this instruction .


"PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG."

"PRINT_OPERAND_ADDRESS, invalid insn #2"

"PRINT_OPERAND_ADDRESS, invalid insn #1"

Print the operand address represented by the rtx addr


<s>
bool
ARMLowOverheadLoops
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
!
static_cast
<
const
ARMSubtarget
&
>
(
MF
.
getSubtarget
(
)
)
.
hasLOB
(
)
)
return
false
;
LLVM_DEBUG
(
dbgs
(
)
<<
"ARM Loops on "
<<
MF
.
getName
(
)
<<
" ------------- \n"
)
;
auto
&
MLI
=
getAnalysis
<
MachineLoopInfo
>
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
TII
=
static_cast
<
const
ARMBaseInstrInfo
*
>
(
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
)
;
BBUtils
=
std
::
unique_ptr
<
ARMBasicBlockUtils
>
(
new
ARMBasicBlockUtils
(
MF
)
)
;
BBUtils
->
computeAllBlockSizes
(
)
;
BBUtils
->
adjustBBOffsetsAfter
(
&
MF
.
front
(
)
)
;
bool
Changed
=
false
;
for
(
auto
ML
:
MLI
)
{
if
(
!
ML
->
getParentLoop
(
)
)
Changed
|=
ProcessLoop
(
ML
)
;
}
return
Changed
;
}
</s>

ARM
ARM
ARM
"ARM Loops on "
" ------------- \n"
ARM
ARM
ARM


<s> int GCNTTIImpl :: getIntrinsicInstrCost ( Intrinsic :: ID ID , Type * RetTy , ArrayRef < Type * > Tys , FastMathFlags FMF , unsigned ScalarizationCostPassed , const Instruction * I ) { return getIntrinsicInstrCost < Type > ( ID , RetTy , Tys , FMF , ScalarizationCostPassed , I ) ; } </s>


<s> bool NVPTXLowerAlloca :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; bool Changed = false ; for ( auto & BB : F ) for ( auto & I : BB ) { if ( auto allocaInst = dyn_cast < AllocaInst > ( & I ) ) { Changed = true ; auto ETy = cast < PointerType > ( allocaInst -> getType ( ) ) -> getElementType ( ) ; auto LocalAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_LOCAL ) ; auto NewASCToLocal = new AddrSpaceCastInst ( allocaInst , LocalAddrTy , "" ) ; auto GenericAddrTy = PointerType :: get ( ETy , ADDRESS_SPACE_GENERIC ) ; auto NewASCToGeneric = new AddrSpaceCastInst ( NewASCToLocal , GenericAddrTy , "" ) ; NewASCToLocal -> insertAfter ( allocaInst ) ; NewASCToGeneric -> insertAfter ( NewASCToLocal ) ; for ( Value :: use_iterator UI = allocaInst -> use_begin ( ) , UE = allocaInst -> use_end ( ) ; UI != UE ; ) { const auto & AllocaUse = * UI ++ ; auto LI = dyn_cast < LoadInst > ( AllocaUse . getUser ( ) ) ; if ( LI && LI -> getPointerOperand ( ) == allocaInst && ! LI -> isVolatile ( ) ) { LI -> setOperand ( LI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto SI = dyn_cast < StoreInst > ( AllocaUse . getUser ( ) ) ; if ( SI && SI -> getPointerOperand ( ) == allocaInst && ! SI -> isVolatile ( ) ) { SI -> setOperand ( SI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto GI = dyn_cast < GetElementPtrInst > ( AllocaUse . getUser ( ) ) ; if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; } auto BI = dyn_cast < BitCastInst > ( AllocaUse . getUser ( ) ) ; if ( BI && BI -> getOperand ( 0 ) == allocaInst ) { BI -> setOperand ( 0 , NewASCToGeneric ) ; continue ; } } } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> void init ( Module & M ) { InsertedThunks = false ; getDerived ( ) . doInitialization ( M ) ; } </s>

Initialize the machine model for instruction scheduling .


<s>
MachineBasicBlock
*
RV16KTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
=
MI
.
getDebugLoc
(
)
;
unsigned
MIOpcode
=
MI
.
getOpcode
(
)
;
assert
(
(
MIOpcode
==
RV16K
::
SelectCCrr
||
MIOpcode
==
RV16K
::
SelectCCri
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
HeadMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
TailMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
IfFalseMBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
IfFalseMBB
)
;
F
->
insert
(
I
,
TailMBB
)
;
TailMBB
->
splice
(
TailMBB
->
begin
(
)
,
HeadMBB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
HeadMBB
->
end
(
)
)
;
TailMBB
->
transferSuccessorsAndUpdatePHIs
(
HeadMBB
)
;
HeadMBB
->
addSuccessor
(
IfFalseMBB
)
;
HeadMBB
->
addSuccessor
(
TailMBB
)
;
if
(
MIOpcode
==
RV16K
::
SelectCCrr
)
{
unsigned
LHS
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
unsigned
RHS
=
MI
.
getOperand
(
2
)
.
getReg
(
)
;
BuildMI
(
HeadMBB
,
DL
,
TII
.
get
(
RV16K
::
Bcc
)
)
.
addReg
(
LHS
)
.
addReg
(
RHS
)
.
addMBB
(
TailMBB
)
.
addImm
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
}
else
{
unsigned
LHS
=
MI
.
getOperand
(
1
)
.
getReg
(
)
;
unsigned
RHS
=
MI
.
getOperand
(
2
)
.
getImm
(
)
;
BuildMI
(
HeadMBB
,
DL
,
TII
.
get
(
RV16K
::
BccI
)
)
.
addReg
(
LHS
)
.
addImm
(
RHS
)
.
addMBB
(
TailMBB
)
.
addImm
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
}
IfFalseMBB
->
addSuccessor
(
TailMBB
)
;
BuildMI
(
*
TailMBB
,
TailMBB
->
begin
(
)
,
DL
,
TII
.
get
(
RV16K
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
4
)
.
getReg
(
)
)
.
addMBB
(
HeadMBB
)
.
addReg
(
MI
.
getOperand
(
5
)
.
getReg
(
)
)
.
addMBB
(
IfFalseMBB
)
;
MI
.
eraseFromParent
(
)
;
return
TailMBB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> const TargetSubtargetInfo * R600TargetMachine :: getSubtargetImpl ( const Function & F ) const { StringRef GPU = getGPUName ( F ) ; StringRef FS = getFeatureString ( F ) ; SmallString < 128 > SubtargetKey ( GPU ) ; SubtargetKey . append ( FS ) ; auto & I = SubtargetMap [ SubtargetKey ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < R600Subtarget > ( TargetTriple , GPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> bool R600TargetLowering :: canMergeStoresTo ( unsigned AS , EVT MemVT ) const { if ( ( AS == AMDGPUASI . LOCAL_ADDRESS || AS == AMDGPUASI . PRIVATE_ADDRESS ) ) { return ( MemVT . getSizeInBits ( ) <= 32 ) ; } return true ; } </s>

Returns if it 's reasonable to merge stores to MemVT size .


<s> BitVector ARM64RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( ARM64 :: SP ) ; Reserved . set ( ARM64 :: XZR ) ; Reserved . set ( ARM64 :: WSP ) ; Reserved . set ( ARM64 :: WZR ) ; if ( TFI -> hasFP ( MF ) || STI -> isTargetDarwin ( ) ) { Reserved . set ( ARM64 :: FP ) ; Reserved . set ( ARM64 :: W29 ) ; } if ( STI -> isTargetDarwin ( ) ) { Reserved . set ( ARM64 :: X18 ) ; Reserved . set ( ARM64 :: W18 ) ; } if ( hasBasePointer ( MF ) ) { Reserved . set ( ARM64 :: X19 ) ; Reserved . set ( ARM64 :: W19 ) ; } return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> MINA32Subtarget & MINA32Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { ParseSubtargetFeatures ( CPU , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> static DItype local_fixunssfdi ( SFtype original_a ) { DFtype a = original_a ; USItype hi , lo ; hi = a / ( ( ( UDItype ) 1 ) << ( sizeof ( SItype ) * 8 ) ) ; lo = ( a - ( ( DFtype ) hi ) * ( ( ( UDItype ) 1 ) << ( sizeof ( SItype ) * 8 ) ) ) ; return ( ( UDItype ) hi << ( sizeof ( SItype ) * 8 ) ) | lo ; } </s>

This version is needed to prevent recursion ; fixunssfdi in libgcc calls fixsfdi , which in turn calls calls fixunssfdi .


<s> Value * RISCVTargetLowering :: emitMaskedAtomicCmpXchgIntrinsic ( IRBuilderBase & Builder , AtomicCmpXchgInst * CI , Value * AlignedAddr , Value * CmpVal , Value * NewVal , Value * Mask , AtomicOrdering Ord ) const { unsigned XLen = Subtarget . getXLen ( ) ; Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; Intrinsic :: ID CmpXchgIntrID = Intrinsic :: riscv_masked_cmpxchg_i32 ; if ( XLen == 64 ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = Intrinsic :: riscv_masked_cmpxchg_i64 ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = Intrinsic :: getDeclaration ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ; Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ; if ( XLen == 64 ) Result = Builder . CreateTrunc ( Result , Builder . getInt32Ty ( ) ) ; return Result ; } </s>

Perform a masked cmpxchg using a target-specific intrinsic .


"WebAssembly Restore Stack Pointer for Exception Handling"

getPassName - Return a nice clean name for a pass .


<s> virtual const XCoreFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> unsigned getMaxSupportedInterleaveFactor ( ) const override { return 4 ; } </s>

Get the maximum supported factor for interleaved memory accesses .


<s> bool X86TargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; const Function * CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( GuaranteedTailCallOpt ) { if ( IsTailCallConvention ( CalleeCC ) && CallerF -> getCallingConv ( ) == CalleeCC ) return true ; return false ; } if ( isVarArg ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( MF . getInfo < X86MachineFunctionInfo > ( ) -> getBytesToPopOnReturn ( ) ) return false ; if ( Subtarget -> isTargetWin64 ( ) ) return false ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const X86InstrInfo * TII = ( ( X86TargetMachine & ) getTargetMachine ( ) ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = Outs [ i ] . Val ; ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII ) ) return false ; } } } } return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .


<s> bool runOnMachineFunction ( MachineFunction & F ) override { bool Changed = false ; F . getRegInfo ( ) . invalidateLiveness ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> unsigned SIInstrInfo :: readlaneVGPRToSGPR ( unsigned SrcReg , MachineInstr * UseMI , MachineRegisterInfo & MRI ) const { const TargetRegisterClass * VRC = MRI . getRegClass ( SrcReg ) ; const TargetRegisterClass * SRC = RI . getEquivalentSGPRClass ( VRC ) ; unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = VRC -> getSize ( ) / 4 ; SmallVector < unsigned , 8 > SRegs ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * UseMI -> getParent ( ) , UseMI , UseMI -> getDebugLoc ( ) , get ( AMDGPU :: V_READFIRSTLANE_B32 ) , SGPR ) . addReg ( SrcReg , 0 , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI -> getParent ( ) , UseMI , UseMI -> getDebugLoc ( ) , get ( AMDGPU :: REG_SEQUENCE ) , DstReg ) ; for ( unsigned i = 0 ; i < SubRegs ; ++ i ) { MIB . addReg ( SRegs [ i ] ) ; MIB . addImm ( RI . getSubRegFromChannel ( i ) ) ; } return DstReg ; } </s>

Copy a value from a VGPR ( SrcReg ) to SGPR .


Return a mask of call-preserved registers for the given calling convention on the current function .


<s> unsigned getNumDefs ( unsigned pred ) { unsigned count = 0 ; for ( auto b : Blocks ) { auto defs = b -> getDefinitions ( ) ; if ( std :: find_if ( defs . begin ( ) , defs . end ( ) , [ & ] ( auto def ) { return def . predicate == pred ; } ) != defs . end ( ) ) { count ++ ; } } return count ; } </s>

Return the number of MachineOperands that are register definitions .


<s> void riscv_cpu_cpp_builtins ( cpp_reader * pfile ) { builtin_define ( "__riscv" ) ; if ( TARGET_RVC ) builtin_define ( "__riscv_compressed" ) ; if ( TARGET_RVE ) builtin_define ( "__riscv_32e" ) ; if ( TARGET_ATOMIC ) builtin_define ( "__riscv_atomic" ) ; if ( TARGET_MUL ) builtin_define ( "__riscv_mul" ) ; if ( TARGET_DIV ) builtin_define ( "__riscv_div" ) ; if ( TARGET_DIV && TARGET_MUL ) builtin_define ( "__riscv_muldiv" ) ; builtin_define_with_int_value ( "__riscv_xlen" , UNITS_PER_WORD * 8 ) ; if ( TARGET_HARD_FLOAT ) builtin_define_with_int_value ( "__riscv_flen" , UNITS_PER_FP_REG * 8 ) ; if ( TARGET_HARD_FLOAT && TARGET_FDIV ) { builtin_define ( "__riscv_fdiv" ) ; builtin_define ( "__riscv_fsqrt" ) ; } switch ( riscv_abi ) { case ABI_ILP32E : builtin_define ( "__riscv_abi_rve" ) ; gcc_fallthrough ( ) ; case ABI_ILP32 : case ABI_LP64 : builtin_define ( "__riscv_float_abi_soft" ) ; break ; case ABI_ILP32F : case ABI_LP64F : builtin_define ( "__riscv_float_abi_single" ) ; break ; case ABI_ILP32D : case ABI_LP64D : builtin_define ( "__riscv_float_abi_double" ) ; break ; } switch ( riscv_cmodel ) { case CM_MEDLOW : builtin_define ( "__riscv_cmodel_medlow" ) ; break ; case CM_PIC : builtin_define ( "__riscv_cmodel_pic" ) ; case CM_MEDANY : builtin_define ( "__riscv_cmodel_medany" ) ; break ; } if ( TARGET_MIN_VLEN != 0 ) builtin_define_with_int_value ( "__riscv_v_min_vlen" , TARGET_MIN_VLEN ) ; if ( TARGET_VECTOR_ELEN_64 ) builtin_define_with_int_value ( "__riscv_v_elen" , 64 ) ; else if ( TARGET_VECTOR_ELEN_32 ) builtin_define_with_int_value ( "__riscv_v_elen" , 32 ) ; if ( TARGET_VECTOR_ELEN_FP_64 ) builtin_define_with_int_value ( "__riscv_v_elen_fp" , 64 ) ; else if ( TARGET_VECTOR_ELEN_FP_32 ) builtin_define_with_int_value ( "__riscv_v_elen_fp" , 32 ) ; else if ( TARGET_MIN_VLEN != 0 ) builtin_define_with_int_value ( "__riscv_v_elen_fp" , 0 ) ; if ( TARGET_MIN_VLEN ) builtin_define ( "__riscv_vector" ) ; builtin_define_with_int_value ( "__riscv_arch_test" , 1 ) ; const riscv_subset_list * subset_list = riscv_current_subset_list ( ) ; if ( ! subset_list ) return ; size_t max_ext_len = 0 ; for ( const riscv_subset_t * subset = subset_list -> begin ( ) ; subset != subset_list -> end ( ) ; subset = subset -> next ) max_ext_len = MAX ( max_ext_len , subset -> name . length ( ) ) ; char * buf = ( char * ) alloca ( max_ext_len + 10 ) ; for ( const riscv_subset_t * subset = subset_list -> begin ( ) ; subset != subset_list -> end ( ) ; subset = subset -> next ) { int version_value = ( subset -> major_version * 1000000 ) + ( subset -> minor_version * 1000 ) ; if ( ( subset -> name == "zicsr" || subset -> name == "zifencei" ) && version_value == 0 ) version_value = 2000000 ; sprintf ( buf , "__riscv_%s" , subset -> name . c_str ( ) ) ; builtin_define_with_int_value ( buf , version_value ) ; } } </s>


<s> void ix86_expand_vector_init ( bool mmx_ok , rtx target , rtx vals ) { enum machine_mode mode = GET_MODE ( target ) ; enum machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_var = 0 , one_var = - 1 ; bool all_same = true , all_const_zero = true ; int i ; rtx x ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( ! CONSTANT_P ( x ) ) n_var ++ , one_var = i ; else if ( x != CONST0_RTX ( inner_mode ) ) all_const_zero = false ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( n_var == 0 ) { emit_move_insn ( target , gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ) ; return ; } if ( all_same && ix86_expand_vector_init_duplicate ( mmx_ok , mode , target , XVECEXP ( vals , 0 , 0 ) ) ) return ; if ( n_var == 1 ) { if ( all_const_zero && one_var == 0 && ix86_expand_vector_init_low_nonzero ( mmx_ok , mode , target , XVECEXP ( vals , 0 , 0 ) ) ) return ; if ( ix86_expand_vector_init_one_var ( mmx_ok , mode , target , vals , one_var ) ) return ; } ix86_expand_vector_init_general ( mmx_ok , mode , target , vals ) ; } </s>

Initialize vector TARGET via VALS . Suppress the use of MMX instructions unless MMX_OK is true .


<s> void RISCVAsmPrinter :: emitStartOfAsmFile ( Module & M ) { if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) emitAttributes ( ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s>
SDValue
SHUXITargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
ExternalSymbol
:
return
LowerExternalSymbol
(
Op
,
DAG
)
;
default
:
llvm_unreachable
(
"unimplemented operand"
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

SHUXI
SHUXI
ISD::BR_CC
ISD::SELECT_CC
ISD::GlobalAddress
ISD::ExternalSymbol
"unimplemented operand"


<s>
bool
AArch64FrameLowering
::
restoreCalleeSavedRegisters
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
std
::
vector
<
CalleeSavedInfo
>
&
CSI
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
&
MF
=
*
MBB
.
getParent
(
)
;
const
TargetInstrInfo
&
TII
=
*
MF
.
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
DL
;
SmallVector
<
RegPairInfo
,
8
>
RegPairs
;
if
(
MI
!=
MBB
.
end
(
)
)
DL
=
MI
->
getDebugLoc
(
)
;
computeCalleeSaveRegisterPairs
(
MF
,
CSI
,
TRI
,
RegPairs
)
;
auto
EmitMI
=
[
&
]
(
const
RegPairInfo
&
RPI
)
{
unsigned
Reg1
=
RPI
.
Reg1
;
unsigned
Reg2
=
RPI
.
Reg2
;
unsigned
LdrOpc
;
if
(
RPI
.
IsGPR
)
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPXi
:
AArch64
::
LDRXui
;
else
LdrOpc
=
RPI
.
isPaired
(
)
AArch64
::
LDPDi
:
AArch64
::
LDRDui
;
DEBUG
(
dbgs
(
)
<<
"CSR restore: ("
<<
printReg
(
Reg1
,
TRI
)
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
printReg
(
Reg2
,
TRI
)
;
dbgs
(
)
<<
") -> fi#("
<<
RPI
.
FrameIdx
;
if
(
RPI
.
isPaired
(
)
)
dbgs
(
)
<<
", "
<<
RPI
.
FrameIdx
+
1
;
dbgs
(
)
<<
")\n"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
MI
,
DL
,
TII
.
get
(
LdrOpc
)
)
;
if
(
RPI
.
isPaired
(
)
)
{
MIB
.
addReg
(
Reg2
,
getDefRegState
(
true
)
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
+
1
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
MIB
.
addReg
(
Reg1
,
getDefRegState
(
true
)
)
.
addReg
(
AArch64
::
SP
)
.
addImm
(
RPI
.
Offset
)
.
setMIFlag
(
MachineInstr
::
FrameDestroy
)
;
MIB
.
addMemOperand
(
MF
.
getMachineMemOperand
(
MachinePointerInfo
::
getFixedStack
(
MF
,
RPI
.
FrameIdx
)
,
MachineMemOperand
::
MOLoad
,
8
,
8
)
)
;
}
;
if
(
ReverseCSRRestoreSeq
)
for
(
const
RegPairInfo
&
RPI
:
reverse
(
RegPairs
)
)
EmitMI
(
RPI
)
;
else
for
(
const
RegPairInfo
&
RPI
:
RegPairs
)
EmitMI
(
RPI
)
;
return
true
;
}
</s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s>
static
void
arm_asm_trampoline_template
(
FILE
*
f
)
{
fprintf
(
f
,
"\t.syntax unified\n"
)
;
if
(
TARGET_FDPIC
)
{
if
(
TARGET_ARM
)
fprintf
(
f
,
"\t.arm\n"
)
;
else
if
(
TARGET_THUMB2
)
fprintf
(
f
,
"\t.thumb\n"
)
;
else
gcc_unreachable
(
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #%d]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
,
TARGET_THUMB2
8
:
4
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #%d]\n"
,
PIC_OFFSET_TABLE_REGNUM
,
PC_REGNUM
,
TARGET_THUMB2
8
:
4
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #%d]\n"
,
PC_REGNUM
,
PC_REGNUM
,
TARGET_THUMB2
8
:
4
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
}
else
if
(
TARGET_ARM
)
{
fprintf
(
f
,
"\t.arm\n"
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
if
(
TARGET_THUMB2
)
{
fprintf
(
f
,
"\t.thumb\n"
)
;
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
{
ASM_OUTPUT_ALIGN
(
f
,
2
)
;
fprintf
(
f
,
"\t.code\t16\n"
)
;
fprintf
(
f
,
".Ltrampoline_start:\n"
)
;
asm_fprintf
(
f
,
"\tpush\t{r0, r1}\n"
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tmov\t%r, r0\n"
,
STATIC_CHAIN_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tstr\tr0, [%r, #4]\n"
,
SP_REGNUM
)
;
asm_fprintf
(
f
,
"\tpop\t{r0, %r}\n"
,
PC_REGNUM
)
;
}
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
}
</s>

Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts . On the ARM , ( if r8 is the static chain regnum , and remembering that referencing pc adds an offset of 8 ) the trampoline looks like : ldr r8 , [ pc , # 0 ] ldr pc , [ pc ] .word static chain value .word function 's address XXX FIXME : When the trampoline returns , r8 will be clobbered .


<s>
StringRef
getPassName
(
)
const
override
{
return
"AIX PPC Assembly Printer"
;
}
</s>


<s> HSAILSubtarget & HSAILSubtarget :: initializeSubtargetDependencies ( StringRef GPU , StringRef FS ) { ParseSubtargetFeatures ( GPU , FS ) ; return * this ; } </s>


<s> SDValue WebAssemblyTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { switch ( N -> getOpcode ( ) ) { default : return SDValue ( ) ; case ISD :: VECTOR_SHUFFLE : return performVECTOR_SHUFFLECombine ( N , DCI ) ; case ISD :: SIGN_EXTEND : case ISD :: ZERO_EXTEND : return performVectorExtendCombine ( N , DCI ) ; case ISD :: SINT_TO_FP : case ISD :: UINT_TO_FP : case ISD :: FP_EXTEND : case ISD :: EXTRACT_SUBVECTOR : return performVectorConvertLowCombine ( N , DCI ) ; case ISD :: FP_TO_SINT_SAT : case ISD :: FP_TO_UINT_SAT : case ISD :: FP_ROUND : case ISD :: CONCAT_VECTORS : return performVectorTruncZeroCombine ( N , DCI ) ; } } </s>

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for .


<s> static rtx nds32_expand_binopimm_builtin ( enum insn_code icode , tree exp , rtx target , bool return_p , const char * name ) { rtx pat ; rtx op0 = nds32_read_argument ( exp , 0 ) ; rtx op1 = nds32_read_argument ( exp , 1 ) ; int op0_num = return_p ? 1 : 0 ; int op1_num = return_p ? 2 : 1 ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; if ( ! nds32_check_constant_argument ( icode , op1_num , op1 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; op1 = nds32_legitimize_argument ( icode , op1_num , op1 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ; } </s>

Expand builtins that take two operands and the second is immediate .


<s> void visium_split_cstore ( enum rtx_code op_code , rtx op0 , rtx op1 , enum rtx_code code , rtx op2 , rtx op3 ) { machine_mode cc_mode = visium_select_cc_mode ( code , op2 , op3 ) ; if ( cc_mode == CCFPEmode && ( op_code == NEG || op_code == MINUS ) ) cc_mode = CCFPmode ; rtx flags = gen_rtx_REG ( cc_mode , FLAGS_REGNUM ) ; rtx x = gen_rtx_COMPARE ( cc_mode , op2 , op3 ) ; x = gen_rtx_SET ( flags , x ) ; emit_insn ( x ) ; x = gen_rtx_fmt_ee ( code , SImode , flags , const0_rtx ) ; switch ( op_code ) { case SET : break ; case NEG : x = gen_rtx_NEG ( SImode , x ) ; break ; case PLUS : case MINUS : x = gen_rtx_fmt_ee ( op_code , SImode , op1 , x ) ; break ; default : gcc_unreachable ( ) ; } rtx pat = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; XVECEXP ( pat , 0 , 0 ) = gen_rtx_SET ( op0 , x ) ; flags = gen_rtx_REG ( CCmode , FLAGS_REGNUM ) ; XVECEXP ( pat , 0 , 1 ) = gen_rtx_CLOBBER ( VOIDmode , flags ) ; emit_insn ( pat ) ; visium_flags_exposed = true ; } </s>

Split a compare-and-store with CODE , operands OP2 and OP3 , combined with operation with OP_CODE , operands OP0 and OP1 .


<s> StringRef getType ( ) const { return CurType . Name ; } </s>

Overload to return most specific vector type .


<s> rtx extract_base_reg ( rtx_insn * insn ) { int post_update_rtx_index ; rtx mem_rtx ; rtx plus_rtx ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_SRC ( parallel_element ( insn , 0 ) ) ; break ; case TYPE_STORE_MULTIPLE : post_update_rtx_index = find_post_update_rtx ( insn ) ; if ( post_update_rtx_index != - 1 ) return SET_DEST ( parallel_element ( insn , post_update_rtx_index ) ) ; mem_rtx = SET_DEST ( parallel_element ( insn , 0 ) ) ; break ; case TYPE_LOAD : case TYPE_FLOAD : case TYPE_STORE : case TYPE_FSTORE : mem_rtx = extract_mem_rtx ( insn ) ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( MEM_P ( mem_rtx ) ) ; if ( REG_P ( XEXP ( mem_rtx , 0 ) ) ) return XEXP ( mem_rtx , 0 ) ; if ( GET_CODE ( XEXP ( mem_rtx , 0 ) ) == LO_SUM ) return XEXP ( XEXP ( mem_rtx , 0 ) , 0 ) ; plus_rtx = XEXP ( mem_rtx , 0 ) ; if ( GET_CODE ( plus_rtx ) == SYMBOL_REF || GET_CODE ( plus_rtx ) == CONST ) return NULL_RTX ; gcc_assert ( GET_CODE ( plus_rtx ) == PLUS || GET_CODE ( plus_rtx ) == POST_INC || GET_CODE ( plus_rtx ) == POST_DEC || GET_CODE ( plus_rtx ) == POST_MODIFY ) ; if ( REG_P ( XEXP ( plus_rtx , 0 ) ) ) return XEXP ( plus_rtx , 0 ) ; gcc_assert ( REG_P ( XEXP ( plus_rtx , 1 ) ) ) ; return XEXP ( plus_rtx , 1 ) ; } </s>

Extract the base register from load/store insns . The function returns NULL_RTX if the address is not consist of any registers .


<s> rtx function_value ( tree valtype , tree func ATTRIBUTE_UNUSED ) { enum machine_mode valmode ; if ( AGGREGATE_TYPE_P ( valtype ) || TREE_CODE ( valtype ) == COMPLEX_TYPE || TREE_CODE ( valtype ) == VECTOR_TYPE ) { if ( TARGET_64BIT ) { rtx loc [ 2 ] ; int i , offset = 0 ; int ub = int_size_in_bytes ( valtype ) <= UNITS_PER_WORD ? 1 : 2 ; for ( i = 0 ; i < ub ; i ++ ) { loc [ i ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 + i ) , GEN_INT ( offset ) ) ; offset += 8 ; } return gen_rtx_PARALLEL ( BLKmode , gen_rtvec_v ( ub , loc ) ) ; } else if ( int_size_in_bytes ( valtype ) > UNITS_PER_WORD ) { rtx loc = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( DImode , 28 ) , const0_rtx ) ; return gen_rtx_PARALLEL ( BLKmode , gen_rtvec ( 1 , loc ) ) ; } } if ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) valmode = word_mode ; else valmode = TYPE_MODE ( valtype ) ; if ( TREE_CODE ( valtype ) == REAL_TYPE && ! AGGREGATE_TYPE_P ( valtype ) && TYPE_MODE ( valtype ) != TFmode && ! TARGET_SOFT_FLOAT ) return gen_rtx_REG ( valmode , 32 ) ; return gen_rtx_REG ( valmode , 28 ) ; } </s>

Handle FUNCTION_VALUE , FUNCTION_OUTGOING_VALUE , and LIBCALL_VALUE macros . For v9 , function return values are subject to the same rules as arguments , except that up to 32 bytes may be returned in registers .