<s>
void
ARMTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
SDValue
Res
;
switch
(
N
->
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom expand this!"
)
;
case
ISD
::
READ_REGISTER
:
ExpandREAD_REGISTER
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
BITCAST
:
Res
=
ExpandBITCAST
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SRL
:
case
ISD
::
SRA
:
case
ISD
::
SHL
:
Res
=
Expand64BitShift
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SREM
:
case
ISD
::
UREM
:
Res
=
LowerREM
(
N
,
DAG
)
;
break
;
case
ISD
::
SDIVREM
:
case
ISD
::
UDIVREM
:
Res
=
LowerDivRem
(
SDValue
(
N
,
0
)
,
DAG
)
;
assert
(
Res
.
getNumOperands
(
)
==
2
&&
"DivRem needs two values"
)
;
Results
.
push_back
(
Res
.
getValue
(
0
)
)
;
Results
.
push_back
(
Res
.
getValue
(
1
)
)
;
return
;
case
ISD
::
SADDSAT
:
case
ISD
::
SSUBSAT
:
case
ISD
::
UADDSAT
:
case
ISD
::
USUBSAT
:
Res
=
LowerADDSUBSAT
(
SDValue
(
N
,
0
)
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
READCYCLECOUNTER
:
ReplaceREADCYCLECOUNTER
(
N
,
Results
,
DAG
,
Subtarget
)
;
return
;
case
ISD
::
UDIV
:
case
ISD
::
SDIV
:
assert
(
Subtarget
->
isTargetWindows
(
)
&&
"can only expand DIV on Windows"
)
;
return
ExpandDIV_Windows
(
SDValue
(
N
,
0
)
,
DAG
,
N
->
getOpcode
(
)
==
ISD
::
SDIV
,
Results
)
;
case
ISD
::
ATOMIC_CMP_SWAP
:
ReplaceCMP_SWAP_64Results
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
INTRINSIC_WO_CHAIN
:
return
ReplaceLongIntrinsic
(
N
,
Results
,
DAG
)
;
case
ISD
::
ABS
:
lowerABS
(
N
,
Results
,
DAG
)
;
return
;
case
ISD
::
LOAD
:
LowerLOAD
(
N
,
Results
,
DAG
)
;
break
;
case
ISD
::
TRUNCATE
:
Res
=
LowerTruncate
(
N
,
DAG
,
Subtarget
)
;
break
;
case
ISD
::
SIGN_EXTEND
:
case
ISD
::
ZERO_EXTEND
:
Res
=
LowerVectorExtend
(
N
,
DAG
,
Subtarget
)
;
break
;
}
if
(
Res
.
getNode
(
)
)
Results
.
push_back
(
Res
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .

ARM
ARM
"Don't know how to custom expand this!"
ISD::READ_REGISTER
ISD::BITCAST
ISD::SRL
ISD::SRA
ISD::SHL
ISD::SREM
ISD::UREM
ISD::SDIVREM
ISD::UDIVREM
0
2
"DivRem needs two values"
0
1
ISD::SADDSAT
ISD::SSUBSAT
ISD::UADDSAT
ISD::USUBSAT
0
ISD::READCYCLECOUNTER
ISD::UDIV
ISD::SDIV
"can only expand DIV on Windows"
0
ISD::SDIV
ISD::ATOMIC_CMP_SWAP
ISD::INTRINSIC_WO_CHAIN
ISD::ABS
ISD::LOAD
ISD::TRUNCATE
ISD::SIGN_EXTEND
ISD::ZERO_EXTEND


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = Fn . getSubtarget ( ) . getDataLayout ( ) ; TII = Fn . getSubtarget ( ) . getInstrInfo ( ) ; TRI = Fn . getSubtarget ( ) . getRegisterInfo ( ) ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool SNESTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return true ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s> const AMDGPURegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo -> getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> const AlphaInstrInfo * getInstrInfo ( ) { return getTargetMachine ( ) . getInstrInfo ( ) ; } </s>


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const { for ( uint64_t i = 0 ; i < Count ; i ++ ) OW -> Write8 ( 0 ) ; return true ; } </s>

Write an ( optimal ) nop sequence of Count bytes to the given output .


<s>
const
MCFixupKindInfo
&
getFixupKindInfo
(
MCFixupKind
Kind
)
const
override
{
const
static
MCFixupKindInfo
Infos
[
FISC
::
NumTargetFixupKinds
]
=
{
{
"fixup_fisc_mov_q1_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_mov_q2_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_mov_q3_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_mov_q4_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_call26_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_call19_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_9bit_address"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_6bit_shamt"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_12bit_imm"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_fisc_movrz_pcrel"
,
0
,
64
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind!"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> void SystemZFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; SystemZMachineFunctionInfo * MFI = MF . getInfo < SystemZMachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < SystemZ :: ELFNumArgGPRs ; ++ I ) SavedRegs . set ( SystemZ :: ELFArgGPRs [ I ] ) ; if ( ! MF . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( SystemZ :: R6D ) ; SavedRegs . set ( SystemZ :: R7D ) ; } if ( HasFP ) SavedRegs . set ( SystemZ :: R11D ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( SystemZ :: R14D ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = 0 ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( SystemZ :: GR64BitRegClass . contains ( Reg ) && SavedRegs . test ( Reg ) ) { SavedRegs . set ( SystemZ :: R15D ) ; break ; } } } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


"operation not permitted on type %<bfloat16_t%>"

Return the diagnostic message string if the unary operation OP is not permitted on TYPE , NULL otherwise .


"Should use MaskedValueIsZero if you don't know whether Op"

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets .


<s> const char * SparcTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( SPISD :: NodeType ) Opcode ) { case SPISD :: FIRST_NUMBER : break ; case SPISD :: CMPICC : return "SPISD::CMPICC" ; case SPISD :: CMPFCC : return "SPISD::CMPFCC" ; case SPISD :: BRICC : return "SPISD::BRICC" ; case SPISD :: BRXCC : return "SPISD::BRXCC" ; case SPISD :: BRFCC : return "SPISD::BRFCC" ; case SPISD :: SELECT_ICC : return "SPISD::SELECT_ICC" ; case SPISD :: SELECT_XCC : return "SPISD::SELECT_XCC" ; case SPISD :: SELECT_FCC : return "SPISD::SELECT_FCC" ; case SPISD :: Hi : return "SPISD::Hi" ; case SPISD :: Lo : return "SPISD::Lo" ; case SPISD :: FTOI : return "SPISD::FTOI" ; case SPISD :: ITOF : return "SPISD::ITOF" ; case SPISD :: FTOX : return "SPISD::FTOX" ; case SPISD :: XTOF : return "SPISD::XTOF" ; case SPISD :: CALL : return "SPISD::CALL" ; case SPISD :: RET_FLAG : return "SPISD::RET_FLAG" ; case SPISD :: GLOBAL_BASE_REG : return "SPISD::GLOBAL_BASE_REG" ; case SPISD :: FLUSHW : return "SPISD::FLUSHW" ; case SPISD :: TLS_ADD : return "SPISD::TLS_ADD" ; case SPISD :: TLS_LD : return "SPISD::TLS_LD" ; case SPISD :: TLS_CALL : return "SPISD::TLS_CALL" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const X86RegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; if ( MF -> callsEHReturn ( ) ) return 0 ; const TargetRegisterClass & AvailableRegs = * TRI -> getGPRsForTailCall ( * MF ) ; if ( MBBI == MBB . end ( ) ) return 0 ; switch ( MBBI -> getOpcode ( ) ) { default : return 0 ; case TargetOpcode :: PATCHABLE_RET : case X86 :: RET : case X86 :: RETL : case X86 :: RETQ : case X86 :: RETIL : case X86 :: RETIQ : case X86 :: TCRETURNdi : case X86 :: TCRETURNri : case X86 :: TCRETURNmi : case X86 :: TCRETURNdi64 : case X86 :: TCRETURNri64 : case X86 :: TCRETURNmi64 : case X86 :: EH_RETURN : case X86 :: EH_RETURN64 : { SmallSet < uint16_t , 8 > Uses ; for ( unsigned i = 0 , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != X86 :: RIP ) return CS ; } } return 0 ; } </s>

findDeadCallerSavedReg - Return a caller-saved register that is n't live when it reaches the `` return '' instruction .


<s> unsigned X86RegisterInfo :: getRARegister ( ) const { return Is64Bit ? X86 :: RIP : X86 :: EIP ; } </s>

This method should return the register where the return address can be found .


<s> rtx arm_gen_load_multiple ( int base_regno , int count , rtx from , int up , int write_back , rtx basemem , HOST_WIDE_INT * offsetp ) { HOST_WIDE_INT offset = * offsetp ; int i = 0 , j ; rtx result ; int sign = up ? 1 : - 1 ; rtx mem , addr ; if ( arm_tune_xscale && count <= 2 && ! optimize_size ) { rtx seq ; start_sequence ( ) ; for ( i = 0 ; i < count ; i ++ ) { addr = plus_constant ( from , i * 4 * sign ) ; mem = adjust_automodify_address ( basemem , SImode , addr , offset ) ; emit_move_insn ( gen_rtx_REG ( SImode , base_regno + i ) , mem ) ; offset += 4 * sign ; } if ( write_back ) { emit_move_insn ( from , plus_constant ( from , count * 4 * sign ) ) ; * offsetp = offset ; } seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( write_back ? 1 : 0 ) ) ) ; if ( write_back ) { XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( GET_MODE ( from ) , from , plus_constant ( from , count * 4 * sign ) ) ; i = 1 ; count ++ ; } for ( j = 0 ; i < count ; i ++ , j ++ ) { addr = plus_constant ( from , j * 4 * sign ) ; mem = adjust_automodify_address_nv ( basemem , SImode , addr , offset ) ; XVECEXP ( result , 0 , i ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , base_regno + j ) , mem ) ; offset += 4 * sign ; } if ( write_back ) * offsetp = offset ; return result ; } </s>


<s> MCSection * MipsTargetObjectFile :: getSectionForConstant ( SectionKind Kind , const Constant * C ) const { if ( IsConstantInSmallSection ( C , * TM ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: getSectionForConstant ( Kind , C ) ; } </s>

Given a constant with the SectionKind , return a section that it should be placed in .


<s> void rs6000_sibcall_sysv ( rtx value , rtx func_desc , rtx tlsarg , rtx cookie ) { rtx func = func_desc ; rtx func_addr ; rtx call [ 3 ] ; rtx insn ; rtx abi_reg = NULL_RTX ; if ( global_tlsarg ) tlsarg = global_tlsarg ; if ( ( INTVAL ( cookie ) & CALL_LONG ) != 0 && GET_CODE ( func_desc ) == SYMBOL_REF ) { func = rs6000_longcall_ref ( func_desc , tlsarg ) ; if ( TARGET_PLTSEQ ) abi_reg = func ; } if ( GET_CODE ( func ) != SYMBOL_REF ) { func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; if ( abi_reg ) { rtvec v = gen_rtvec ( 3 , func , func_desc , tlsarg ) ; rtx mark_func = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; emit_insn ( gen_rtx_SET ( func_addr , mark_func ) ) ; v = gen_rtvec ( 2 , func_addr , func_desc ) ; func_addr = gen_rtx_UNSPEC ( Pmode , v , UNSPEC_PLTSEQ ) ; } else emit_move_insn ( func_addr , func ) ; } else func_addr = func ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = gen_rtx_USE ( VOIDmode , cookie ) ; call [ 2 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 3 , call ) ) ; insn = emit_call_insn ( insn ) ; if ( abi_reg ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , abi_reg ) ; } </s>

Expand code to perform a sibling call under the SysV4 ABI .


<s> void EmitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , bool ) override { if ( IsThumb ) EmitThumbMappingSymbol ( ) ; else EmitARMMappingSymbol ( ) ; MCELFStreamer :: EmitInstruction ( Inst , STI ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> static const char * elf_platform ( void ) { int fd ; fd = open ( "/proc/self/auxv" , O_RDONLY ) ; if ( fd != - 1 ) { char buf [ 1024 ] ; ElfW ( auxv_t ) * av ; ssize_t n ; n = read ( fd , buf , sizeof ( buf ) ) ; close ( fd ) ; if ( n > 0 ) { for ( av = ( ElfW ( auxv_t ) * ) buf ; av -> a_type != AT_NULL ; ++ av ) switch ( av -> a_type ) { case AT_PLATFORM : return ( const char * ) av -> a_un . a_val ; default : break ; } } } </s>

Returns the canonical AT_PLATFORM if present , otherwise NULL .


<s> X86TargetMachine :: X86TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , JIT , RM ) , getEffectiveX86CodeModel ( CM , JIT , TT . getArch ( ) == Triple :: x86_64 ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , IsJIT ( JIT ) { if ( TT . isPS4 ( ) || TT . isOSBinFormatMachO ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . NoTrapAfterNoreturn = TT . isOSBinFormatMachO ( ) ; } setMachineOutliner ( true ) ; setSupportsDebugEntryValues ( true ) ; initAsmInfo ( ) ; } </s>


<s> static void loongarch_split_plus ( rtx x , rtx * base_ptr , HOST_WIDE_INT * offset_ptr ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) ) { * base_ptr = XEXP ( x , 0 ) ; * offset_ptr = INTVAL ( XEXP ( x , 1 ) ) ; } else { * base_ptr = x ; * offset_ptr = 0 ; } } </s>

If X is a PLUS of a CONST_INT , return the two terms in * BASE_PTR and * OFFSET_PTR . Return X in * BASE_PTR and 0 in * OFFSET_PTR otherwise .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"Hexagon Split Double Registers"
;
}
</s>

getPassName - Return a nice clean name for a pass .

Hexagon
"Hexagon Split Double Registers"


<s> EVT SITargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Size >= 16 && DstAlign >= 4 ) return MVT :: v4i32 ; if ( Size >= 8 && DstAlign >= 4 ) return MVT :: v2i32 ; return MVT :: Other ; } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s> bool SIInstrInfo :: isAsmOnlyOpcode ( int MCOp ) const { switch ( MCOp ) { case AMDGPU :: V_MOVRELS_B32_dpp_gfx10 : case AMDGPU :: V_MOVRELS_B32_sdwa_gfx10 : case AMDGPU :: V_MOVRELD_B32_dpp_gfx10 : case AMDGPU :: V_MOVRELD_B32_sdwa_gfx10 : case AMDGPU :: V_MOVRELSD_B32_dpp_gfx10 : case AMDGPU :: V_MOVRELSD_B32_sdwa_gfx10 : case AMDGPU :: V_MOVRELSD_2_B32_dpp_gfx10 : case AMDGPU :: V_MOVRELSD_2_B32_sdwa_gfx10 : return true ; default : return false ; } } </s>

Check if this instruction should only be used by assembler .


<s> static bool ix86_eax_live_at_start_p ( void ) { return REGNO_REG_SET_P ( ENTRY_BLOCK_PTR -> il . rtl -> global_live_at_end , 0 ) ; } </s>

Return true if EAX is live at the start of the function . Used by ix86_expand_prologue to determine if we need special help before calling allocate_stack_worker .


<s> static void expand_block_move_4 ( rtx dst , rtx dst_reg , rtx src , rtx src_reg , rtx bytes_rtx ) { unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % 4 ; if ( TARGET_BMI ) { unsigned int i ; rtx insn ; emit_move_insn ( regno_reg_rtx [ 1 ] , dst_reg ) ; emit_move_insn ( regno_reg_rtx [ 2 ] , src_reg ) ; emit_move_insn ( regno_reg_rtx [ 3 ] , bytes_rtx ) ; insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 8 ) ) ; XVECEXP ( insn , 0 , 0 ) = gen_rtx_SET ( replace_equiv_address_nv ( dst , regno_reg_rtx [ 1 ] ) , replace_equiv_address_nv ( src , regno_reg_rtx [ 2 ] ) ) ; XVECEXP ( insn , 0 , 1 ) = gen_rtx_USE ( VOIDmode , regno_reg_rtx [ 3 ] ) ; for ( i = 1 ; i <= 6 ; i ++ ) XVECEXP ( insn , 0 , 1 + i ) = gen_rtx_CLOBBER ( VOIDmode , regno_reg_rtx [ i ] ) ; emit_insn ( insn ) ; } else emit_library_call ( long_int_memcpy_libfunc , LCT_NORMAL , VOIDmode , 3 , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> 2 ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == 0 ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; src = replace_equiv_address_nv ( src , src_reg ) ; bytes -= rem ; if ( rem > 1 ) { emit_move_insn ( adjust_address_nv ( dst , HImode , bytes ) , adjust_address_nv ( src , HImode , bytes ) ) ; bytes += 2 ; rem -= 2 ; } if ( rem > 0 ) emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , adjust_address_nv ( src , QImode , bytes ) ) ; } </s>

Generate a call to a library function to move BYTES_RTX bytes from SRC with address SRC_REG to DST with address DST_REG in 4-byte chunks .


<s> unsigned ARMFastISel :: fastMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( DL , C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return 0 ; MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return ARMMaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return ARMMaterializeGV ( GV , VT ) ; else if ( isa < ConstantInt > ( C ) ) return ARMMaterializeInt ( C , VT ) ; return 0 ; } </s>

Emit a constant in a register using target-specific logic , such as constant pool loads .


<s>
unsigned
ARMTTIImpl
::
getGatherScatterOpCost
(
unsigned
Opcode
,
Type
*
DataTy
,
Value
*
Ptr
,
bool
VariableMask
,
unsigned
Alignment
)
{
if
(
!
ST
->
hasMVEIntegerOps
(
)
||
!
EnableMaskedGatherScatters
)
return
BaseT
::
getGatherScatterOpCost
(
Opcode
,
DataTy
,
Ptr
,
VariableMask
,
Alignment
)
;
assert
(
DataTy
->
isVectorTy
(
)
&&
"Can't do gather/scatters on scalar!"
)
;
VectorType
*
VTy
=
cast
<
VectorType
>
(
DataTy
)
;
unsigned
NumElems
=
VTy
->
getNumElements
(
)
;
unsigned
EltSize
=
VTy
->
getScalarSizeInBits
(
)
;
std
::
pair
<
int
,
MVT
>
LT
=
TLI
->
getTypeLegalizationCost
(
DL
,
DataTy
)
;
unsigned
VectorCost
=
NumElems
*
LT
.
first
;
unsigned
ScalarCost
=
NumElems
*
LT
.
first
+
BaseT
::
getScalarizationOverhead
(
DataTy
,
{
}
)
;
if
(
EltSize
*
NumElems
!=
128
||
NumElems
<
4
)
return
ScalarCost
;
if
(
Alignment
<
EltSize
/
8
)
return
ScalarCost
;
if
(
EltSize
==
32
)
return
VectorCost
;
if
(
EltSize
!=
8
&&
EltSize
!=
16
)
return
ScalarCost
;
if
(
auto
BC
=
dyn_cast
<
BitCastInst
>
(
Ptr
)
)
Ptr
=
BC
->
getOperand
(
0
)
;
if
(
auto
*
GEP
=
dyn_cast
<
GetElementPtrInst
>
(
Ptr
)
)
{
if
(
GEP
->
getNumOperands
(
)
!=
2
)
return
ScalarCost
;
unsigned
Scale
=
DL
.
getTypeAllocSize
(
GEP
->
getResultElementType
(
)
)
;
if
(
Scale
!=
1
&&
Scale
*
8
!=
EltSize
)
return
ScalarCost
;
if
(
auto
ZExt
=
dyn_cast
<
ZExtInst
>
(
GEP
->
getOperand
(
1
)
)
)
if
(
ZExt
->
getOperand
(
0
)
->
getType
(
)
->
getScalarSizeInBits
(
)
<=
EltSize
)
return
VectorCost
;
return
ScalarCost
;
}
return
ScalarCost
;
}
</s>

Calculate the cost of Gather / Scatter operation .


<s> int aarch64_fpconst_pow2_recip ( rtx x ) { REAL_VALUE_TYPE r0 ; if ( ! CONST_DOUBLE_P ( x ) ) return - 1 ; r0 = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( exact_real_inverse ( DFmode , & r0 ) && ! REAL_VALUE_NEGATIVE ( r0 ) ) { int ret = exact_log2 ( real_to_integer ( & r0 ) ) ; if ( ret >= 1 && ret <= 32 ) return ret ; } return - 1 ; } </s>

If X is a positive CONST_DOUBLE with a value that is the reciprocal of a power of 2 ( i.e 1/2^n ) return the number of float bits . e.g . for x== ( 1/2^n ) return n. Otherwise return -1 .


<s>
void
MipsInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
;
if
(
I
!=
MBB
.
end
(
)
)
DL
=
I
->
getDebugLoc
(
)
;
unsigned
Opc
=
0
;
if
(
RC
==
Mips
::
CPURegsRegisterClass
)
Opc
=
IsN64
Mips
::
SW_P8
:
Mips
::
SW
;
else
if
(
RC
==
Mips
::
CPU64RegsRegisterClass
)
Opc
=
IsN64
Mips
::
SD_P8
:
Mips
::
SD
;
else
if
(
RC
==
Mips
::
FGR32RegisterClass
)
Opc
=
IsN64
Mips
::
SWC1_P8
:
Mips
::
SWC1
;
else
if
(
RC
==
Mips
::
AFGR64RegisterClass
)
Opc
=
Mips
::
SDC1
;
else
if
(
RC
==
Mips
::
FGR64RegisterClass
)
Opc
=
IsN64
Mips
::
SDC164_P8
:
Mips
::
SDC164
;
assert
(
Opc
&&
"Register class not handled!"
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s> static bool extract_base_offset_in_addr ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( MEM_P ( mem ) ) ; addr = XEXP ( mem , 0 ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , 0 ) ; if ( REG_P ( addr ) || GET_CODE ( addr ) == SYMBOL_REF ) { * base = addr ; * offset = const0_rtx ; return true ; } if ( GET_CODE ( addr ) == PLUS && ( REG_P ( XEXP ( addr , 0 ) ) || GET_CODE ( XEXP ( addr , 0 ) ) == SYMBOL_REF ) && CONST_INT_P ( XEXP ( addr , 1 ) ) ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return true ; } return false ; } </s>

If MEM is in the form of `` base+offset '' , extract the two parts of address and set to BASE and OFFSET , otherwise return false after clearing BASE and OFFSET .


<s> void view ( ) { ViewGraph ( * this , "agraph" ) ; } </s>

Opens a viewer to show the GraphViz visualization of the regions .


<s> static tree add_attribute ( const char * name , tree attrs ) { return tree_cons ( get_identifier ( name ) , NULL_TREE , attrs ) ; } </s>


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) ) adjustWritemask ( Node , DAG ) ; if ( Opcode == AMDGPU :: INSERT_SUBREG || Opcode == AMDGPU :: REG_SEQUENCE ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } return Node ; } </s>

Fold the instructions after selecting them .

AMDGPU SI SI SI AMDGPU::INSERT_SUBREG AMDGPU::REG_SEQUENCE


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { GlobalBaseReg = 0 ; Subtarget = & MF . getSubtarget < PPCSubtarget > ( ) ; PPCLowering = Subtarget -> getTargetLowering ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const PPCSubtarget & STI = MF . getSubtarget < PPCSubtarget > ( ) ; if ( ! STI . useCRBits ( ) ) return false ; initialize ( MF ) ; collectCRLogicals ( ) ; return simplifyCode ( ) ; } </s>


<s>
void
Mips16InstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
Opc
=
0
,
ZeroReg
=
0
;
if
(
Mips
::
CPURegsRegClass
.
contains
(
DestReg
)
)
{
if
(
Mips
::
CPURegsRegClass
.
contains
(
SrcReg
)
)
Opc
=
Mips
::
Move32R16
;
}
assert
(
Opc
&&
"Cannot copy registers"
)
;
MachineInstrBuilder
MIB
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
Opc
)
)
;
if
(
DestReg
)
MIB
.
addReg
(
DestReg
,
RegState
::
Define
)
;
if
(
ZeroReg
)
MIB
.
addReg
(
ZeroReg
)
;
if
(
SrcReg
)
MIB
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
</s>


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ^ is_swapped ] ; high = nelt / 2 ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vzipv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vzipv4hf_internal ; break ; case V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( is_swapped ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> void MSP430InstPrinter :: printInst ( const MCInst * MI ) { printInstruction ( MI ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> void fr30_setup_incoming_varargs ( cumulative_args_t arg_regs_used_so_far_v , machine_mode mode , tree type ATTRIBUTE_UNUSED , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * arg_regs_used_so_far = get_cumulative_args ( arg_regs_used_so_far_v ) ; int size ; gcc_assert ( mode != BLKmode ) ; if ( targetm . calls . strict_argument_naming ( arg_regs_used_so_far_v ) ) arg_regs_used_so_far += fr30_num_arg_regs ( mode , type ) ; size = FR30_NUM_ARG_REGS - ( * arg_regs_used_so_far ) ; if ( size <= 0 ) return ; * pretend_size = ( size * UNITS_PER_WORD ) ; } </s>

Do any needed setup for a variadic function . We must create a register parameter block , and then copy any anonymous arguments , plus the last named argument , from registers into memory . * copying actually done in fr30_expand_prologue ( ) . ARG_REGS_USED_SO_FAR has * not * been updated for the last named argument which has type TYPE and mode MODE , and we rely on this fact .


<s> VESubtarget & VESubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = "ve" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ; AU . addRequired < MachinePostDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> bool ARMLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { if ( skipFunction ( Fn . getFunction ( ) ) ) return false ; MF = & Fn ; STI = & static_cast < const ARMSubtarget & > ( Fn . getSubtarget ( ) ) ; TL = STI -> getTargetLowering ( ) ; AFI = Fn . getInfo < ARMFunctionInfo > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; RegClassInfoValid = false ; isThumb2 = AFI -> isThumb2Function ( ) ; isThumb1 = AFI -> isThumbFunction ( ) && ! isThumb2 ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) { Modified |= LoadStoreMultipleOpti ( MBB ) ; if ( STI -> hasV5TOps ( ) ) Modified |= MergeReturnIntoLDM ( MBB ) ; if ( isThumb1 ) Modified |= CombineMovBx ( MBB ) ; } Allocator . DestroyAll ( ) ; return Modified ; } </s>


"WebAssembly doesn't support non-C calling conventions"

"WebAssembly doesn't support varargs yet"

"WebAssembly hasn't implemented byval arguments"

"WebAssembly hasn't implemented inalloca arguments"

"WebAssembly hasn't implemented nest arguments"

"WebAssembly hasn't implemented cons regs arguments"

"WebAssembly hasn't implemented cons regs last arguments"

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> static rtx lm32_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( arg . end_marker_p ( ) ) return GEN_INT ( 0 ) ; if ( targetm . calls . must_pass_in_stack ( arg ) ) return NULL_RTX ; if ( ! arg . named || * cum + LM32_NUM_REGS2 ( arg . mode , arg . type ) > LM32_NUM_ARG_REGS ) return NULL_RTX ; return gen_rtx_REG ( arg . mode , * cum + LM32_FIRST_ARG_REG ) ; } </s>

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) .


<s> bool aarch64_sve_bitmask_immediate_p ( rtx x ) { rtx elt ; return ( const_vec_duplicate_p ( x , & elt ) && CONST_INT_P ( elt ) && aarch64_bitmask_imm ( INTVAL ( elt ) , GET_MODE_INNER ( GET_MODE ( x ) ) ) ) ; } </s>

Return true if X is a valid immediate operand for an SVE logical instruction such as AND .


<s> void rs6000_initialize_trampoline ( rtx addr , rtx fnaddr , rtx cxt ) { enum machine_mode pmode = Pmode ; int regsize = ( TARGET_32BIT ) ? 4 : 8 ; rtx ctx_reg = force_reg ( pmode , cxt ) ; switch ( DEFAULT_ABI ) { default : gcc_unreachable ( ) ; gen_rtx_MEM ( pmode , memory_address ( pmode , plus_constant ( addr , offset ) ) ) case ABI_AIX : { rtx fn_reg = gen_reg_rtx ( pmode ) ; rtx toc_reg = gen_reg_rtx ( pmode ) ; emit_move_insn ( fn_reg , MEM_DEREF ( fnaddr ) ) ; emit_move_insn ( toc_reg , MEM_PLUS ( fnaddr , regsize ) ) ; emit_move_insn ( MEM_DEREF ( addr ) , fn_reg ) ; emit_move_insn ( MEM_PLUS ( addr , regsize ) , toc_reg ) ; emit_move_insn ( MEM_PLUS ( addr , 2 * regsize ) , ctx_reg ) ; } break ; case ABI_DARWIN : case ABI_V4 : emit_library_call ( gen_rtx_SYMBOL_REF ( SImode , "__trampoline_setup" ) , FALSE , VOIDmode , 4 , addr , pmode , GEN_INT ( rs6000_trampoline_size ( ) ) , SImode , fnaddr , pmode , ctx_reg , pmode ) ; break ; } return ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline . FNADDR is an RTX for the address of the function 's pure code . CXT is an RTX for the static chain value for the function .


<s> bool isReg ( ) const override { return Kind == k_Register ; } </s>


<s> void LC2200PassConfig :: addPreEmitPass ( ) { } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> static bool chain_contains_only_swaps ( swap_web_entry * insn_entry , struct df_link * link , enum chain_purpose purpose ) { if ( ! link ) return false ; for ( ; link ; link = link -> next ) { if ( ! VECTOR_MODE_P ( GET_MODE ( DF_REF_REG ( link -> ref ) ) ) ) continue ; if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx reached_insn = DF_REF_INSN ( link -> ref ) ; unsigned uid = INSN_UID ( reached_insn ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( reached_insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load || insn_entry [ uid ] . is_store ) return false ; if ( purpose == FOR_LOADS ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( use ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_def_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || ! insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } else if ( purpose == FOR_STORES ) { df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( def ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_use_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_use_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } } return true ; } </s>

Return true if the UD or DU chain headed by LINK is non-empty , and every entry on the chain references an insn that is a register swap . Furthermore , if PURPOSE is FOR_LOADS , each such register swap must have only permuting loads as reaching defs . If PURPOSE is FOR_STORES , each such register swap must have only register swaps or permuting stores as reached uses .


<s>
void
SparcInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
unsigned
numSubRegs
=
0
;
unsigned
movOpc
=
0
;
const
unsigned
*
subRegIdx
=
0
;
const
unsigned
DFP_FP_SubRegsIdx
[
]
=
{
SP
::
sub_even
,
SP
::
sub_odd
}
;
const
unsigned
QFP_DFP_SubRegsIdx
[
]
=
{
SP
::
sub_even64
,
SP
::
sub_odd64
}
;
const
unsigned
QFP_FP_SubRegsIdx
[
]
=
{
SP
::
sub_even
,
SP
::
sub_odd
,
SP
::
sub_odd64_then_sub_even
,
SP
::
sub_odd64_then_sub_odd
}
;
if
(
SP
::
IntRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
ORrr
)
,
DestReg
)
.
addReg
(
SP
::
G0
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
FPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVS
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
else
if
(
SP
::
DFPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
Subtarget
.
isV9
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVD
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
subRegIdx
=
DFP_FP_SubRegsIdx
;
numSubRegs
=
2
;
movOpc
=
SP
::
FMOVS
;
}
}
else
if
(
SP
::
QFPRegsRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
if
(
Subtarget
.
isV9
(
)
)
{
if
(
Subtarget
.
hasHardQuad
(
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
SP
::
FMOVQ
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
}
else
{
subRegIdx
=
QFP_DFP_SubRegsIdx
;
numSubRegs
=
2
;
movOpc
=
SP
::
FMOVD
;
}
}
else
{
subRegIdx
=
QFP_FP_SubRegsIdx
;
numSubRegs
=
4
;
movOpc
=
SP
::
FMOVS
;
}
}
else
llvm_unreachable
(
"Impossible reg-to-reg copy"
)
;
if
(
numSubRegs
==
0
||
subRegIdx
==
0
||
movOpc
==
0
)
return
;
const
TargetRegisterInfo
*
TRI
=
&
getRegisterInfo
(
)
;
MachineInstr
*
MovMI
=
0
;
for
(
unsigned
i
=
0
;
i
!=
numSubRegs
;
++
i
)
{
unsigned
Dst
=
TRI
->
getSubReg
(
DestReg
,
subRegIdx
[
i
]
)
;
unsigned
Src
=
TRI
->
getSubReg
(
SrcReg
,
subRegIdx
[
i
]
)
;
assert
(
Dst
&&
Src
&&
"Bad sub-register"
)
;
MovMI
=
BuildMI
(
MBB
,
I
,
DL
,
get
(
movOpc
)
,
Dst
)
.
addReg
(
Src
)
;
}
MovMI
->
addRegisterDefined
(
DestReg
,
TRI
)
;
if
(
KillSrc
)
MovMI
->
addRegisterKilled
(
SrcReg
,
TRI
)
;
}
</s>


<s> rtx mmix_dynamic_chain_address ( rtx frame ) { return plus_constant ( Pmode , frame , - 8 ) ; } </s>


<s> VariantKind getKind ( ) const { return Kind ; } </s>


<s> SDValue AArch64SelectionDAGInfo :: EmitTargetCodeForMemset ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , MachinePointerInfo DstPtrInfo ) const { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; ConstantSDNode * SizeValue = dyn_cast < ConstantSDNode > ( Size ) ; const AArch64Subtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < AArch64Subtarget > ( ) ; const char * bzeroEntry = ( V && V -> isNullValue ( ) ) ? STI . getBZeroEntry ( ) : nullptr ; if ( bzeroEntry && ( ! SizeValue || SizeValue -> getZExtValue ( ) > 256 ) ) { const AArch64TargetLowering & TLI = * STI . getTargetLowering ( ) ; EVT IntPtr = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , 0 ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } </s>

Emit target-specific code that performs a memset .


<s> bool alpha_const_double_ok_for_letter_p ( rtx value , int c ) { switch ( c ) { case 'G' : return ( GET_MODE_CLASS ( GET_MODE ( value ) ) == MODE_FLOAT && value == CONST0_RTX ( GET_MODE ( value ) ) ) ; case 'H' : return ( GET_MODE ( value ) == VOIDmode && zap_mask ( CONST_DOUBLE_LOW ( value ) ) && zap_mask ( CONST_DOUBLE_HIGH ( value ) ) ) ; default : return false ; } } </s>

Implements CONST_DOUBLE_OK_FOR_LETTER_P . Return true if VALUE matches for C in [ GH ] .


"Wasn't expecting to be able to lower this!"

LowerOperation - Provide custom lowering hooks for some operations .


"WebAssembly does not use MCFixupKindInfo flags"

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s>
bool
AArch64LegalizerInfo
::
legalizeCustom
(
LegalizerHelper
&
Helper
,
MachineInstr
&
MI
)
const
{
MachineIRBuilder
&
MIRBuilder
=
Helper
.
MIRBuilder
;
MachineRegisterInfo
&
MRI
=
*
MIRBuilder
.
getMRI
(
)
;
GISelChangeObserver
&
Observer
=
Helper
.
Observer
;
switch
(
MI
.
getOpcode
(
)
)
{
default
:
return
false
;
case
TargetOpcode
::
G_VAARG
:
return
legalizeVaArg
(
MI
,
MRI
,
MIRBuilder
)
;
case
TargetOpcode
::
G_LOAD
:
case
TargetOpcode
::
G_STORE
:
return
legalizeLoadStore
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_SHL
:
case
TargetOpcode
::
G_ASHR
:
case
TargetOpcode
::
G_LSHR
:
return
legalizeShlAshrLshr
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_GLOBAL_VALUE
:
return
legalizeSmallCMGlobalValue
(
MI
,
MRI
,
MIRBuilder
,
Observer
)
;
case
TargetOpcode
::
G_TRUNC
:
return
legalizeVectorTrunc
(
MI
,
Helper
)
;
case
TargetOpcode
::
G_SBFX
:
case
TargetOpcode
::
G_UBFX
:
return
legalizeBitfieldExtract
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ROTR
:
return
legalizeRotate
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTPOP
:
return
legalizeCTPOP
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_ATOMIC_CMPXCHG
:
return
legalizeAtomicCmpxchg128
(
MI
,
MRI
,
Helper
)
;
case
TargetOpcode
::
G_CTTZ
:
return
legalizeCTTZ
(
MI
,
Helper
)
;
case
TargetOpcode
::
G_BZERO
:
case
TargetOpcode
::
G_MEMCPY
:
case
TargetOpcode
::
G_MEMMOVE
:
case
TargetOpcode
::
G_MEMSET
:
return
legalizeMemOps
(
MI
,
Helper
)
;
}
llvm_unreachable
(
"expected switch to return"
)
;
}
</s>

Called for instructions with the Custom LegalizationAction .


<s> int visium_initial_elimination_offset ( int from , int to ATTRIBUTE_UNUSED ) { const int frame_size = visium_compute_frame_size ( get_frame_size ( ) ) ; const int save_fp = current_frame_info . save_fp ; const int save_lr = current_frame_info . save_lr ; const int lr_slot = current_frame_info . lr_slot ; const int local_frame_offset = ( save_fp + save_lr + lr_slot ) * UNITS_PER_WORD ; int offset ; if ( from == FRAME_POINTER_REGNUM ) offset = local_frame_offset ; else if ( from == ARG_POINTER_REGNUM ) offset = frame_size ; else gcc_unreachable ( ) ; return offset ; } </s>

Helper function for INITIAL_ELIMINATION_OFFSET ( FROM , TO , OFFSET ) . Define the offset between two registers , one to be eliminated , and the other its replacement , at the start of a routine .


<s> static void output_indirect_thunk_function ( enum indirect_thunk_prefix need_prefix , unsigned int regno , bool ret_p ) { char name [ 32 ] ; tree decl ; indirect_thunk_name ( name , regno , need_prefix , ret_p ) ; decl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , build_function_type_list ( void_type_node , NULL_TREE ) ) ; DECL_RESULT ( decl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; TREE_PUBLIC ( decl ) = 1 ; TREE_STATIC ( decl ) = 1 ; DECL_IGNORED_P ( decl ) = 1 ; if ( TARGET_MACHO ) { switch_to_section ( darwin_sections [ picbase_thunk_section ] ) ; fputs ( "\t.weak_definition\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; fputs ( "\n\t.private_extern\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; DECL_WEAK ( decl ) = 1 ; } else if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , 0 ) ; switch_to_section ( get_named_section ( decl , NULL , 0 ) ) ; targetm . asm_out . globalize_label ( asm_out_file , name ) ; fputs ( "\t.hidden\t" , asm_out_file ) ; assemble_name ( asm_out_file , name ) ; putc ( '\n' , asm_out_file ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , name , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl = decl ; allocate_struct_function ( decl , false ) ; init_function_start ( decl ) ; cfun -> is_thunk = true ; first_function_block_is_cold = false ; final_start_function ( emit_barrier ( ) , asm_out_file , 1 ) ; output_indirect_thunk ( regno ) ; final_end_function ( ) ; init_insn_lengths ( ) ; free_after_compilation ( cfun ) ; set_cfun ( NULL ) ; current_function_decl = NULL ; } </s>

Output a funtion with a call and return thunk for indirect branch . If BND_P is true , the BND prefix is needed . If REGNO ! = UNVALID_REGNUM , the function address is in REGNO . Otherwise , the function address is on the top of stack . Thunk is used for function return if RET_P is true .


<s> const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( RISCVISD :: NodeType ) Opcode ) { case RISCVISD :: FIRST_NUMBER : break ; case RISCVISD :: RET_FLAG : return "RISCVISD::RET_FLAG" ; case RISCVISD :: URET_FLAG : return "RISCVISD::URET_FLAG" ; case RISCVISD :: SRET_FLAG : return "RISCVISD::SRET_FLAG" ; case RISCVISD :: MRET_FLAG : return "RISCVISD::MRET_FLAG" ; case RISCVISD :: CALL : return "RISCVISD::CALL" ; case RISCVISD :: SELECT_CC : return "RISCVISD::SELECT_CC" ; case RISCVISD :: BuildPairF64 : return "RISCVISD::BuildPairF64" ; case RISCVISD :: SplitF64 : return "RISCVISD::SplitF64" ; case RISCVISD :: TAIL : return "RISCVISD::TAIL" ; case RISCVISD :: SETVL : return "RISCVISD::SETVL" ; case RISCVISD :: BROADCAST : return "RISCVISD::BROADCAST" ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific


<s> static rtx F ( rtx x ) { RTX_FRAME_RELATED_P ( x ) = 1 ; return x ; } </s>

We use this to wrap all emitted insns in the prologue , so they get the `` frame-related '' ( /f ) flag set .


<s> static rtx mips_strip_unspec_call ( rtx src ) { if ( GET_CODE ( src ) == UNSPEC && XINT ( src , 1 ) == UNSPEC_LOAD_CALL ) return mips_strip_unspec_address ( XVECEXP ( src , 0 , 1 ) ) ; return NULL_RTX ; } </s>

If SRC is the RHS of a load_call < mode > insn , return the underlying symbol reference . Return NULL_RTX otherwise .


<s> void pru_emit_doloop ( rtx * operands , int is_end ) { rtx tag ; if ( cfun -> machine -> doloop_tags == 0 || cfun -> machine -> doloop_tag_from_end == is_end ) { cfun -> machine -> doloop_tags ++ ; cfun -> machine -> doloop_tag_from_end = is_end ; } tag = GEN_INT ( cfun -> machine -> doloop_tags - 1 ) ; machine_mode opmode = GET_MODE ( operands [ 0 ] ) ; gcc_assert ( opmode == HImode || opmode == SImode ) ; if ( is_end ) emit_jump_insn ( gen_doloop_end_internal ( opmode , operands [ 0 ] , operands [ 1 ] , tag ) ) ; else emit_insn ( gen_doloop_begin_internal ( opmode , operands [ 0 ] , operands [ 0 ] , tag ) ) ; } </s>

If IS_END is false , expand a canonical doloop_begin RTL into the PRU-specific doloop_begin_internal . Otherwise expand doloop_end to doloop_end_internal .


<s> bool ARMTargetLowering :: isVectorLoadExtDesirable ( SDValue ExtVal ) const { EVT VT = ExtVal . getValueType ( ) ; if ( ! isTypeLegal ( VT ) ) return false ; if ( ExtVal -> use_empty ( ) || ! ExtVal -> use_begin ( ) -> isOnlyUserOf ( ExtVal . getNode ( ) ) ) return true ; SDNode * U = * ExtVal -> use_begin ( ) ; if ( ( U -> getOpcode ( ) == ISD :: ADD || U -> getOpcode ( ) == ISD :: SUB || U -> getOpcode ( ) == ISD :: SHL || U -> getOpcode ( ) == ARMISD :: VSHL ) ) return false ; return true ; } </s>

Return true if folding a vector load into ExtVal ( a sign , zero , or any extend node ) is profitable .

ARM ARM ISD::ADD ISD::SUB ISD::SHL ARMISD::VSHL


<s> bool ARMTargetLowering :: isShuffleMaskLegal ( ArrayRef < int > M , EVT VT ) const { if ( VT . getVectorNumElements ( ) == 4 && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ 4 ] ; for ( unsigned i = 0 ; i != 4 ; ++ i ) { if ( M [ i ] < 0 ) PFIndexes [ i ] = 8 ; else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ 0 ] * 9 * 9 * 9 + PFIndexes [ 1 ] * 9 * 9 + PFIndexes [ 2 ] * 9 + PFIndexes [ 3 ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> 30 ) ; if ( Cost <= 4 && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= 32 || ShuffleVectorSDNode :: isSplatMask ( & M [ 0 ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , 64 ) || isVREVMask ( M , VT , 32 ) || isVREVMask ( M , VT , 16 ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( VT == MVT :: v8i16 || VT == MVT :: v16i8 ) && isReverseMask ( M , VT ) ) return true ; else if ( Subtarget -> hasMVEIntegerOps ( ) && ( isVMOVNMask ( M , VT , true , false ) || isVMOVNMask ( M , VT , false , false ) || isVMOVNMask ( M , VT , true , true ) ) ) return true ; else return false ; } </s>

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations , those with specific masks .


<s> static unsigned int riscv_min_arithmetic_precision ( void ) { return 32 ; } </s>


<s> std :: pair < uint16_t , uint16_t > ARMBaseInstrInfo :: getExecutionDomain ( const MachineInstr * MI ) const { if ( Subtarget . hasNEON ( ) ) { if ( MI -> getOpcode ( ) == ARM :: VMOVD && ! isPredicated ( MI ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; if ( Subtarget . isCortexA9 ( ) && ! isPredicated ( MI ) && ( MI -> getOpcode ( ) == ARM :: VMOVRS || MI -> getOpcode ( ) == ARM :: VMOVSR || MI -> getOpcode ( ) == ARM :: VMOVS ) ) return std :: make_pair ( ExeVFP , ( 1 << ExeVFP ) | ( 1 << ExeNEON ) ) ; } unsigned Domain = MI -> getDesc ( ) . TSFlags & ARMII :: DomainMask ; if ( Domain & ARMII :: DomainNEON ) return std :: make_pair ( ExeNEON , 0 ) ; if ( ( Domain & ARMII :: DomainNEONA8 ) && Subtarget . isCortexA8 ( ) ) return std :: make_pair ( ExeNEON , 0 ) ; if ( Domain & ARMII :: DomainVFP ) return std :: make_pair ( ExeVFP , 0 ) ; return std :: make_pair ( ExeGeneric , 0 ) ; } </s>

Return the current execution domain and bit mask of possible domains for instruction .


<s>
const
MCFixupKindInfo
&
J2AsmBackend
::
getFixupKindInfo
(
MCFixupKind
Kind
)
const
{
static
const
MCFixupKindInfo
Infos
[
J2
::
NumTargetFixupKinds
]
=
{
{
"fixup_J2_NONE"
,
0
,
0
,
0
}
,
{
"fixup_J2_PC2_12"
,
4
,
12
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_J2_PC2_8"
,
8
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
{
"fixup_J2_PC4_8"
,
8
,
8
,
MCFixupKindInfo
::
FKF_IsPCRel
}
,
}
;
if
(
Kind
<
FirstTargetFixupKind
)
return
MCAsmBackend
::
getFixupKindInfo
(
Kind
)
;
assert
(
unsigned
(
Kind
FirstTargetFixupKind
)
<
getNumFixupKinds
(
)
&&
"Invalid kind"
)
;
return
Infos
[
Kind
FirstTargetFixupKind
]
;
}
</s>


<s> static void do_link ( rtx spreg , HOST_WIDE_INT frame_size , bool all ) { frame_size += arg_area_size ( ) ; if ( all || stack_frame_needed_p ( ) || ( must_save_fp_p ( ) && ! current_function_is_leaf ) ) emit_link_insn ( spreg , frame_size ) ; else { if ( ! current_function_is_leaf ) { rtx pat = gen_movsi ( gen_rtx_MEM ( Pmode , gen_rtx_PRE_DEC ( Pmode , spreg ) ) , bfin_rets_rtx ) ; rtx insn = emit_insn ( pat ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } if ( must_save_fp_p ( ) ) { rtx pat = gen_movsi ( gen_rtx_MEM ( Pmode , gen_rtx_PRE_DEC ( Pmode , spreg ) ) , gen_rtx_REG ( Pmode , REG_FP ) ) ; rtx insn = emit_insn ( pat ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } add_to_sp ( spreg , - frame_size , 1 ) ; } } </s>

Save RETS and FP , and allocate a stack frame . ALL is true if the function must save all its registers ( true only for certain interrupt handlers ) .


"Unexpected base pointer for inline asm memory operand."

"Unexpected offset for inline asm memory operand."

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


"This eliminateFrameIndex does not support Thumb1!"

"Instr doesn't have FrameIndex operand!"

"This code isn't needed if offset already handled!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> void rs6000_sibcall_aix ( rtx value , rtx func_desc , rtx tlsarg , rtx cookie ) { rtx call [ 2 ] ; rtx insn ; gcc_assert ( INTVAL ( cookie ) == 0 ) ; if ( global_tlsarg ) tlsarg = global_tlsarg ; call [ 0 ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_desc ) , tlsarg ) ; if ( value != NULL_RTX ) call [ 0 ] = gen_rtx_SET ( value , call [ 0 ] ) ; call [ 1 ] = simple_return_rtx ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( 2 , call ) ) ; insn = emit_call_insn ( insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , gen_rtx_REG ( Pmode , TOC_REGNUM ) ) ; } </s>

Expand code to perform a sibling call under the AIX or ELFv2 ABI .


<s>
SDValue
XNCMTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_XNCM
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
if
(
RVLocs
[
i
]
.
isRegLoc
(
)
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
unsigned
Opc
=
XNCMISD
::
RET_FLAG
;
if
(
Flag
.
getNode
(
)
)
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
return
DAG
.
getNode
(
Opc
,
dl
,
MVT
::
Other
,
Chain
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> int mmix_dbx_register_number ( int regno ) { regno = MMIX_OUTPUT_REGNO ( regno ) ; return regno >= 224 ? ( regno - 224 ) : ( regno + 48 ) ; } </s>


<s> bool PPCPassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ; } </s>

This method should install a legalize pass , which converts the instruction sequence into one that can be selected by the target .


<s> const SPIRVTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


"%qE attribute doesn%'t apply to functions"


<s> EVT AArch64TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & C , EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i32 ; if ( VT . isScalableVector ( ) ) return EVT :: getVectorVT ( C , MVT :: i1 , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


"MIPS DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


<s> bool AMDGPUInstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INTRINSIC : return selectG_INTRINSIC ( I , CoverageInfo ) ; case TargetOpcode :: G_LOAD : return selectG_LOAD ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; } return false ; } </s>

Select the ( possibly generic ) instruction I to only use target-specific opcodes .


<s> int fldi_ok ( void ) { return ! TARGET_SH4 || TARGET_FMOVD || reload_completed ; } </s>

For -m4 and -m4-single-only , mode switching is used . If we are compiling without -mfmovd , movsf_ie is n't taken into account for mode switching . We could check in machine_dependent_reorg for cases where we know we are in single precision mode , but there is interface to find that out during reload , so we must avoid choosing an fldi alternative during reload and thus failing to allocate a scratch register for the constant loading .


<s> void SITargetLowering :: allocateSpecialInputVGPRs ( CCState & CCInfo , MachineFunction & MF , const SIRegisterInfo & TRI , SIMachineFunctionInfo & Info ) const { const unsigned Mask = 0x3ff ; ArgDescriptor Arg ; if ( Info . hasWorkItemIDX ( ) ) { Arg = allocateVGPR32Input ( CCInfo , Mask ) ; Info . setWorkItemIDX ( Arg ) ; } if ( Info . hasWorkItemIDY ( ) ) { Arg = allocateVGPR32Input ( CCInfo , Mask << 10 , Arg ) ; Info . setWorkItemIDY ( Arg ) ; } if ( Info . hasWorkItemIDZ ( ) ) Info . setWorkItemIDZ ( allocateVGPR32Input ( CCInfo , Mask << 20 , Arg ) ) ; } </s>

Allocate implicit function VGPR arguments at the end of allocated user arguments .


<s> static bool mips_print_operand_punct_valid_p ( unsigned char code ) { return mips_print_operand_punct [ code ] ; } </s>


<s> void rs6000_split_v4si_init ( rtx operands [ ] ) { rtx dest = operands [ 0 ] ; if ( REG_P ( dest ) || SUBREG_P ( dest ) ) { int d_regno = regno_or_subregno ( dest ) ; rtx scalar1 = operands [ 1 ] ; rtx scalar2 = operands [ 2 ] ; rtx scalar3 = operands [ 3 ] ; rtx scalar4 = operands [ 4 ] ; rtx tmp1 = operands [ 5 ] ; rtx tmp2 = operands [ 6 ] ; if ( BYTES_BIG_ENDIAN ) { rtx di_lo = gen_rtx_REG ( DImode , d_regno ) ; rtx di_hi = gen_rtx_REG ( DImode , d_regno + 1 ) ; rs6000_split_v4si_init_di_reg ( di_lo , scalar1 , scalar2 , tmp1 ) ; rs6000_split_v4si_init_di_reg ( di_hi , scalar3 , scalar4 , tmp2 ) ; } else { rtx di_lo = gen_rtx_REG ( DImode , d_regno + 1 ) ; rtx di_hi = gen_rtx_REG ( DImode , d_regno ) ; gcc_assert ( ! VECTOR_ELT_ORDER_BIG ) ; rs6000_split_v4si_init_di_reg ( di_lo , scalar4 , scalar3 , tmp1 ) ; rs6000_split_v4si_init_di_reg ( di_hi , scalar2 , scalar1 , tmp2 ) ; } return ; } else gcc_unreachable ( ) ; } </s>


<s> bool HexagonEarlyIfConversion :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & ST = MF . getSubtarget < HexagonSubtarget > ( ) ; HII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = EnableHexagonBP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ; Changed |= visitLoop ( 0 ) ; return Changed ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; PHINodeSet PromotablePHINodes = getPromotablePHINodes ( F ) ; B2IMap Bool2IntMap ; bool Changed = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { if ( ReturnInst * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( R -> getOperandUse ( 0 ) , PromotablePHINodes , Bool2IntMap ) ; if ( CallInst * CI = dyn_cast < CallInst > ( & I ) ) for ( auto & U : CI -> operands ( ) ) if ( U -> getType ( ) -> isIntegerTy ( 1 ) ) Changed |= runOnUse ( U , PromotablePHINodes , Bool2IntMap ) ; } } return Changed ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> unsigned AMDGPUTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const SelectionDAG & DAG , unsigned Depth ) const { switch ( Op . getOpcode ( ) ) { case AMDGPUISD :: BFE_I32 : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; if ( ! Width ) return 1 ; unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ; if ( ! Offset || ! Offset -> isNullValue ( ) ) return SignBits ; unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; return std :: max ( SignBits , Op0SignBits ) ; } case AMDGPUISD :: BFE_U32 : { ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; return Width ? 32 - ( Width -> getZExtValue ( ) & 0x1f ) : 1 ; } case AMDGPUISD :: CARRY : case AMDGPUISD :: BORROW : return 31 ; default : return 1 ; } } </s>

Determine the number of bits in the operation that are sign bits .


<s>
void
emitDirectiveVariantPCS
(
MCSymbol
*
Symbol
)
override
{
OS
<<
"\t.variant_pcs "
<<
Symbol
->
getName
(
)
<<
"\n"
;
}
</s>

Callback used to implement the .variant_pcs directive .


<s> void X86IntelInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


<s> static void riscv_emit_prologue_components ( sbitmap components ) { riscv_process_components ( components , true ) ; } </s>


<s> const uint32_t * ARMBaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ; if ( CC == CallingConv :: CFGuard_Check ) return CSR_Win_AAPCS_CFGuard_Check_RegMask ; if ( CC == CallingConv :: SwiftTail ) { return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftTail_RegMask : CSR_AAPCS_SwiftTail_RegMask ; } if ( STI . getTargetLowering ( ) -> supportSwiftError ( ) && MF . getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return STI . isTargetDarwin ( ) ? CSR_iOS_SwiftError_RegMask : CSR_AAPCS_SwiftError_RegMask ; if ( STI . isTargetDarwin ( ) && CC == CallingConv :: CXX_FAST_TLS ) return CSR_iOS_CXX_TLS_RegMask ; return STI . isTargetDarwin ( ) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> void s390_expand_logical_operator ( enum rtx_code code , machine_mode mode , rtx * operands ) { machine_mode wmode = mode ; rtx dst = operands [ 0 ] ; rtx src1 = operands [ 1 ] ; rtx src2 = operands [ 2 ] ; rtx op , clob , tem ; if ( ! s390_logical_operator_ok_p ( operands ) ) dst = gen_reg_rtx ( mode ) ; if ( ( mode == QImode || mode == HImode ) && GET_CODE ( dst ) != MEM ) wmode = SImode ; if ( mode != wmode ) { if ( GET_CODE ( dst ) == SUBREG && ( tem = simplify_subreg ( wmode , dst , mode , 0 ) ) != 0 ) dst = tem ; else if ( REG_P ( dst ) ) dst = gen_rtx_SUBREG ( wmode , dst , 0 ) ; else dst = gen_reg_rtx ( wmode ) ; if ( GET_CODE ( src1 ) == SUBREG && ( tem = simplify_subreg ( wmode , src1 , mode , 0 ) ) != 0 ) src1 = tem ; else if ( GET_MODE ( src1 ) != VOIDmode ) src1 = gen_rtx_SUBREG ( wmode , force_reg ( mode , src1 ) , 0 ) ; if ( GET_CODE ( src2 ) == SUBREG && ( tem = simplify_subreg ( wmode , src2 , mode , 0 ) ) != 0 ) src2 = tem ; else if ( GET_MODE ( src2 ) != VOIDmode ) src2 = gen_rtx_SUBREG ( wmode , force_reg ( mode , src2 ) , 0 ) ; } op = gen_rtx_SET ( VOIDmode , dst , gen_rtx_fmt_ee ( code , wmode , src1 , src2 ) ) ; clob = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( CCmode , CC_REGNUM ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , op , clob ) ) ) ; if ( dst != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , gen_lowpart ( mode , dst ) ) ; } </s>

Expand logical operator CODE in mode MODE with operands OPERANDS .


<s> virtual const TeeRISCRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool ARMPreAllocLoadStoreOpt :: runOnMachineFunction ( MachineFunction & Fn ) { TD = Fn . getTarget ( ) . getTargetData ( ) ; TII = Fn . getTarget ( ) . getInstrInfo ( ) ; TRI = Fn . getTarget ( ) . getRegisterInfo ( ) ; STI = & Fn . getTarget ( ) . getSubtarget < ARMSubtarget > ( ) ; MRI = & Fn . getRegInfo ( ) ; MF = & Fn ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ; } </s>


<s> void WebAssemblyPassConfig :: addIRPasses ( ) { if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( TM ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createWebAssemblyOptimizeReturned ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> gen_call_visitor sub ( const value * l ) const { return gen_call_visitor { l , Args } ; } </s>

sub - Return the result of replacing the first match of the regex in String with the Repl string .


<s> MachineRegisterInfo * getMRI ( ) const { return & getParentInst ( ) -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; } </s>


<s> SDValue PPCTargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( ! Subtarget . isPPC64 ( ) ) return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBase ( Table , DAG ) ; default : return DAG . getNode ( PPCISD :: GlobalBaseReg , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } } </s>

Returns relocation base for the given PIC jumptable .


<s> bool AArch64TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size <= 128 ; } </s>

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW , if at all .


<s> void rs6000_emit_cbranch ( machine_mode mode , rtx operands [ ] ) { rtx condition_rtx , loc_ref ; condition_rtx = rs6000_generate_compare ( operands [ 0 ] , mode ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ 3 ] ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ) ; } </s>

Emit a branch of kind CODE to location LOC .


<s>
static
rtx
avr_addr_space_legitimize_address
(
rtx
x
,
rtx
old_x
,
machine_mode
mode
,
addr_space_t
as
)
{
if
(
ADDR_SPACE_GENERIC_P
(
as
)
)
return
avr_legitimize_address
(
x
,
old_x
,
mode
)
;
if
(
avr_log
.
legitimize_address
)
{
avr_edump
(
"\n%?: mode=%m\n %r\n"
,
mode
,
old_x
)
;
}
return
old_x
;
}
</s>

Implement ` TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS ' .


<s> static void arm_compute_frame_layout ( void ) { struct arm_stack_offsets * offsets ; unsigned long func_type ; int saved ; int core_saved ; HOST_WIDE_INT frame_size ; int i ; offsets = & cfun -> machine -> stack_offsets ; frame_size = ROUND_UP_WORD ( get_frame_size ( ) ) ; offsets -> saved_args = crtl -> args . pretend_args_size ; offsets -> frame = ( offsets -> saved_args + arm_compute_static_chain_stack_bytes ( ) + ( frame_pointer_needed ? 4 : 0 ) ) ; if ( TARGET_32BIT ) { unsigned int regno ; offsets -> saved_regs_mask = arm_compute_save_core_reg_mask ( ) ; core_saved = bit_count ( offsets -> saved_regs_mask ) * 4 ; saved = core_saved ; if ( TARGET_REALLY_IWMMXT ) { for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) saved += 8 ; } func_type = arm_current_func_type ( ) ; if ( ! IS_VOLATILE ( func_type ) && TARGET_HARD_FLOAT ) saved += arm_get_vfp_saved_size ( ) ; } else { offsets -> saved_regs_mask = thumb1_compute_save_core_reg_mask ( ) ; core_saved = bit_count ( offsets -> saved_regs_mask ) * 4 ; saved = core_saved ; if ( TARGET_BACKTRACE ) saved += 16 ; } offsets -> saved_regs = offsets -> saved_args + arm_compute_static_chain_stack_bytes ( ) + saved ; offsets -> soft_frame = offsets -> saved_regs + CALLER_INTERWORKING_SLOT_SIZE ; if ( crtl -> is_leaf && frame_size == 0 && ! cfun -> calls_alloca ) { offsets -> outgoing_args = offsets -> soft_frame ; offsets -> locals_base = offsets -> soft_frame ; return ; } if ( ARM_DOUBLEWORD_ALIGN && ( offsets -> soft_frame & 7 ) ) { offsets -> soft_frame += 4 ; if ( frame_size + crtl -> outgoing_args_size == 0 ) { int reg = - 1 ; bool prefer_callee_reg_p = false ; if ( ! any_sibcall_could_use_r3 ( ) && arm_size_return_regs ( ) <= 12 && ( offsets -> saved_regs_mask & ( 1 << 3 ) ) == 0 && ( TARGET_THUMB2 || ! ( TARGET_LDRD && current_tune -> prefer_ldrd_strd ) ) ) { reg = 3 ; if ( ! TARGET_THUMB2 ) prefer_callee_reg_p = true ; } if ( reg == - 1 || prefer_callee_reg_p ) { for ( i = 4 ; i <= ( TARGET_THUMB1 ? LAST_LO_REGNUM : 11 ) ; i ++ ) { if ( ! fixed_regs [ i ] && ( offsets -> saved_regs_mask & ( 1 << i ) ) == 0 ) { reg = i ; break ; } } } if ( reg != - 1 ) { offsets -> saved_regs += 4 ; offsets -> saved_regs_mask |= ( 1 << reg ) ; } } } offsets -> locals_base = offsets -> soft_frame + frame_size ; offsets -> outgoing_args = ( offsets -> locals_base + crtl -> outgoing_args_size ) ; if ( ARM_DOUBLEWORD_ALIGN ) { if ( offsets -> outgoing_args & 7 ) offsets -> outgoing_args += 4 ; gcc_assert ( ! ( offsets -> outgoing_args & 7 ) ) ; } } </s>

Calculate stack offsets . These are used to calculate register elimination offsets and in prologue/epilogue code . Also calculates which registers should be saved .


<s> bool SystemZTargetLowering :: allowTruncateForTailCall ( Type * FromType , Type * ToType ) const { return isTruncateFree ( FromType , ToType ) ; } </s>

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position .


<s> int bfin_return_in_memory ( tree type ) { int size = int_size_in_bytes ( type ) ; return size > 2 * UNITS_PER_WORD || size == - 1 ; } </s>

Decide whether a type should be returned in memory ( true ) or in a register ( false ) . This is called by the macro RETURN_IN_MEMORY .


<s> bool SystemZLongBranch :: runOnMachineFunction ( MachineFunction & F ) { TII = static_cast < const SystemZInstrInfo * > ( F . getTarget ( ) . getInstrInfo ( ) ) ; MF = & F ; uint64_t Size = initMBBInfo ( ) ; if ( Size <= MaxForwardRange || ! mustRelaxABranch ( ) ) return false ; setWorstCaseAddresses ( ) ; relaxBranches ( ) ; return true ; } </s>


<s> bool AArch64TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { EVT VT ; SDValue Ptr ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool IsInc ; if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) return false ; if ( Ptr != Base ) return false ; AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ; return true ; } </s>

Returns true by value , base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store .


<s> bool emit_scc_insn ( rtx operands [ ] ) { rtx tem , x , y ; enum rtx_code code ; machine_mode mode ; if ( GET_MODE ( operands [ 2 ] ) == TFmode && ! TARGET_HARD_QUAD ) { operands [ 1 ] = sparc_emit_float_lib_cmp ( operands [ 2 ] , operands [ 3 ] , GET_CODE ( operands [ 1 ] ) ) ; operands [ 2 ] = XEXP ( operands [ 1 ] , 0 ) ; operands [ 3 ] = XEXP ( operands [ 1 ] , 1 ) ; } code = GET_CODE ( operands [ 1 ] ) ; x = operands [ 2 ] ; y = operands [ 3 ] ; mode = GET_MODE ( x ) ; if ( ( code == EQ || code == NE ) && ( mode == SImode || mode == DImode ) ) { if ( y != const0_rtx ) x = force_reg ( mode , gen_rtx_XOR ( mode , x , y ) ) ; rtx pat = gen_rtx_SET ( operands [ 0 ] , gen_rtx_fmt_ee ( code , GET_MODE ( operands [ 0 ] ) , x , const0_rtx ) ) ; if ( mode == SImode || ( code == NE && TARGET_VIS3 ) ) { rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( mode == SImode ? CCmode : CCXmode , SPARC_ICC_REG ) ) ; pat = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , pat , clobber ) ) ; } emit_insn ( pat ) ; return true ; } if ( TARGET_ARCH64 && mode == DImode && ! ( ( code == LTU || code == GTU ) && TARGET_VIS3 ) && gen_v9_scc ( operands [ 0 ] , code , x , y ) ) return true ; if ( code == GTU || code == LEU ) { if ( ( GET_CODE ( x ) == REG || GET_CODE ( x ) == SUBREG ) && ( GET_CODE ( y ) == REG || GET_CODE ( y ) == SUBREG ) ) { tem = x ; x = y ; y = tem ; code = swap_condition ( code ) ; } } if ( code == LTU || code == GEU ) { emit_insn ( gen_rtx_SET ( operands [ 0 ] , gen_rtx_fmt_ee ( code , GET_MODE ( operands [ 0 ] ) , gen_compare_reg_1 ( code , x , y ) , const0_rtx ) ) ) ; return true ; } if ( TARGET_V9 && gen_v9_scc ( operands [ 0 ] , code , x , y ) ) return true ; return false ; } </s>

Emit an scc insn . For seq , sne , sgeu , and sltu , we can do this without jumps using the addx/subx instructions .


<s> const TargetRegisterClass * AArch64RegisterInfo :: getSubClassWithSubReg ( const TargetRegisterClass * RC , unsigned Idx ) const { if ( RC == & AArch64 :: GPR32allRegClass && Idx == AArch64 :: hsub ) return & AArch64 :: FPR32RegClass ; else if ( RC == & AArch64 :: GPR64allRegClass && Idx == AArch64 :: hsub ) return & AArch64 :: FPR64RegClass ; return AArch64GenRegisterInfo :: getSubClassWithSubReg ( RC , Idx ) ; } </s>

Returns the largest legal sub-class of RC that supports the sub-register index Idx .


<s> const MCExpr * SparcELFTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { MachineModuleInfoELF & ELFMMI = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MCSymbol * SSym = getSymbolWithGlobalValueBase ( GV , ".DW.stub" , TM ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ELFMMI . getGVStubEntry ( SSym ) ; if ( ! StubSym . getPointer ( ) ) { MCSymbol * Sym = TM . getSymbol ( GV ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Sym , ! GV -> hasLocalLinkage ( ) ) ; } MCContext & Ctx = getContext ( ) ; return SparcMCExpr :: create ( SparcMCExpr :: VK_Sparc_R_DISP32 , MCSymbolRefExpr :: create ( SSym , Ctx ) , Ctx ) ; } return TargetLoweringObjectFileELF :: getTTypeGlobalReference ( GV , Encoding , TM , MMI , Streamer ) ; } </s>

The mach-o version of this method defaults to returning a stub reference .


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override { } </s>

Relax the instruction in the given fragment to the next wider instruction .


<s> int h8300_shift_needs_scratch_p ( int count , machine_mode mode , enum rtx_code type ) { enum h8_cpu cpu ; int a , lr , ar ; if ( GET_MODE_BITSIZE ( mode ) <= count ) return 1 ; if ( TARGET_H8300S ) cpu = H8_S ; else cpu = H8_300H ; switch ( mode ) { case E_QImode : a = shift_alg_qi [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_qi [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_qi [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; case E_HImode : a = shift_alg_hi [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_hi [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_hi [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; case E_SImode : a = shift_alg_si [ cpu ] [ SHIFT_ASHIFT ] [ count ] ; lr = shift_alg_si [ cpu ] [ SHIFT_LSHIFTRT ] [ count ] ; ar = shift_alg_si [ cpu ] [ SHIFT_ASHIFTRT ] [ count ] ; break ; default : gcc_unreachable ( ) ; } if ( type == CLOBBER ) return ( a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == 8 ) ) ; else if ( type == ASHIFT ) return ( a == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == 8 ) ) ; else if ( type == LSHIFTRT ) return ( lr == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == 8 ) ) ; else if ( type == ASHIFTRT ) return ( ar == SHIFT_LOOP || ( TARGET_H8300H && mode == SImode && count == 8 ) ) ; gcc_unreachable ( ) ; } </s>

Given COUNT and MODE of a shift , return 1 if a scratch reg may be needed for some shift with COUNT and MODE . Return 0 otherwise .


<s> virtual unsigned getISAEncoding ( ) { if ( ! Subtarget -> isTargetDarwin ( ) ) return 0 ; return Subtarget -> isThumb ( ) ? llvm :: ARM :: DW_ISA_ARM_thumb : llvm :: ARM :: DW_ISA_ARM_arm ; } </s>

Get the value for DW_AT_APPLE_isa . Zero if no isa encoding specified .


<s> int getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { if ( Imm . getBitWidth ( ) <= 64 && isInt < 32 > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; return TTI :: TCC_Basic ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> void NVPTXAsmPrinter :: emitStartOfAsmFile ( Module & M ) { const NVPTXTargetMachine & NTM = static_cast < const NVPTXTargetMachine & > ( TM ) ; const auto * STI = static_cast < const NVPTXSubtarget * > ( NTM . getSubtargetImpl ( ) ) ; SmallString < 128 > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; emitHeader ( M , OS1 , * STI ) ; OutStreamer -> emitRawText ( OS1 . str ( ) ) ; } </s>

This virtual method can be overridden by targets that want to emit something at the start of their file .


<s> bool MipsPassConfig :: addPreEmitPass ( ) { MipsTargetMachine & TM = getMipsTargetMachine ( ) ; const MipsSubtarget & Subtarget = TM . getSubtarget < MipsSubtarget > ( ) ; addPass ( createMipsDelaySlotFillerPass ( TM ) ) ; if ( Subtarget . hasStandardEncoding ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( createMipsLongBranchPass ( TM ) ) ; if ( Subtarget . inMips16Mode ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( createMipsConstantIslandPass ( TM ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips


<s> unsigned AMDGPUAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & Op , unsigned Kind ) { AMDGPUOperand & Operand = ( AMDGPUOperand & ) Op ; switch ( Kind ) { case MCK_addr64 : return Operand . isAddr64 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_gds : return Operand . isGDS ( ) ? Match_Success : Match_InvalidOperand ; case MCK_glc : return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrc32 : return Operand . isSSrc32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; default : return Match_InvalidOperand ; } } </s>

Allow a target to add special case operand matching for things that tblgen doesn't/ca n't handle effectively .


<s> static void mips_print_operand_address ( FILE * file , rtx x ) { struct mips_address_info addr ; if ( mips_classify_address ( & addr , x , word_mode , true ) ) switch ( addr . type ) { case ADDRESS_REG : mips_print_operand ( file , addr . offset , 0 ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_LO_SUM : mips_print_operand_reloc ( file , addr . offset , SYMBOL_CONTEXT_MEM , mips_lo_relocs ) ; fprintf ( file , "(%s)" , reg_names [ REGNO ( addr . reg ) ] ) ; return ; case ADDRESS_CONST_INT : output_addr_const ( file , x ) ; fprintf ( file , "(%s)" , reg_names [ GP_REG_FIRST ] ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , mips_strip_unspec_address ( x ) ) ; return ; } gcc_unreachable ( ) ; } </s>


"256-bit vector operations only available in AVX2"

Change the opcode of MI to execute in Domain .


<s> bool SystemZElimCompare :: processBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; bool CompleteCCUsers = ! isCCLiveOut ( MBB ) ; SmallVector < MachineInstr * , 4 > CCUsers ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && ( MI -> isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareOperations ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; } if ( MI -> definesRegister ( SystemZ :: CC ) ) { CCUsers . clear ( ) ; CompleteCCUsers = true ; } if ( MI -> readsRegister ( SystemZ :: CC ) && CompleteCCUsers ) CCUsers . push_back ( MI ) ; } return Changed ; } </s>

processBlock - If there are any predecessors whose control can be threaded through to a successor , transform them now .

SystemZ SystemZ 4 SystemZ::CC SystemZ::CC


<s> const char * host_detect_local_cpu ( int argc , const char * * argv ) { const char * cpu ; bool arch ; if ( argc < 1 ) return NULL ; arch = strcmp ( argv [ 0 ] , "cpu" ) == 0 ; if ( ! arch && strcmp ( argv [ 0 ] , "tune" ) ) return NULL ; if ( arch ) cpu = "powerpc" ; return concat ( "-m" , argv [ 0 ] , "=" , cpu , NULL ) ; } </s>

This will be called by the spec parser in gcc.cc when it sees a % : local_cpu_detect ( args ) construct . Currently it will be called with either `` cpu '' or `` tune '' as argument depending on if -mcpu=native or -mtune=native is to be substituted . It returns a string containing new command line parameters to be put at the place of the above two options , depending on what CPU this is executed . E.g . `` -mcpu=ultrasparc3 '' on an UltraSPARC III for -mcpu=native . If the routine ca n't detect a known processor , the -mcpu or -mtune option is discarded . ARGC and ARGV are set depending on the actual arguments given in the spec .


<s>
const
char
*
arc_output_libcall
(
const
char
*
fname
)
{
unsigned
len
=
strlen
(
fname
)
;
static
char
buf
[
64
]
;
gcc_assert
(
len
<
sizeof
buf
35
)
;
if
(
TARGET_LONG_CALLS_SET
||
(
TARGET_MEDIUM_CALLS
&&
arc_ccfsm_cond_exec_p
(
)
)
)
{
if
(
flag_pic
)
sprintf
(
buf
,
"add r12,pcl,@%s@pcl\n\tjl%%!%%* [r12]"
,
fname
)
;
else
sprintf
(
buf
,
"jl%%! @%s"
,
fname
)
;
}
else
sprintf
(
buf
,
"bl%%!%%* @%s"
,
fname
)
;
return
buf
;
}
</s>

Output a library call to a function called FNAME that has been arranged to be local to any dso .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> BitVector CSKYRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const CSKYFrameLowering * TFI = getFrameLowering ( MF ) ; const CSKYSubtarget & STI = MF . getSubtarget < CSKYSubtarget > ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , CSKY :: R7 ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , CSKY :: R8 ) ; if ( ! STI . hasE2 ( ) ) { for ( unsigned i = 0 ; i < 6 ; i ++ ) markSuperRegs ( Reserved , CSKY :: R8 + i ) ; } markSuperRegs ( Reserved , CSKY :: R14 ) ; markSuperRegs ( Reserved , CSKY :: R15 ) ; if ( ! STI . hasHighRegisters ( ) ) { for ( unsigned i = 0 ; i < 10 ; i ++ ) markSuperRegs ( Reserved , CSKY :: R16 + i ) ; } markSuperRegs ( Reserved , CSKY :: R26 ) ; markSuperRegs ( Reserved , CSKY :: R27 ) ; markSuperRegs ( Reserved , CSKY :: R28 ) ; markSuperRegs ( Reserved , CSKY :: R29 ) ; markSuperRegs ( Reserved , CSKY :: R30 ) ; markSuperRegs ( Reserved , CSKY :: R31 ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> void rs6000_emit_parity ( rtx dst , rtx src ) { machine_mode mode = GET_MODE ( dst ) ; rtx tmp ; tmp = gen_reg_rtx ( mode ) ; if ( TARGET_CMPB ) { if ( mode == SImode ) { emit_insn ( gen_popcntbsi2 ( tmp , src ) ) ; emit_insn ( gen_paritysi2_cmpb ( dst , tmp ) ) ; } else { emit_insn ( gen_popcntbdi2 ( tmp , src ) ) ; emit_insn ( gen_paritydi2_cmpb ( dst , tmp ) ) ; } return ; } if ( mode == SImode ) { if ( rs6000_cost -> mulsi_const >= COSTS_N_INSNS ( 3 ) ) { rtx tmp1 , tmp2 , tmp3 , tmp4 ; tmp1 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_popcntbsi2 ( tmp1 , src ) ) ; tmp2 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp2 , tmp1 , GEN_INT ( 16 ) ) ) ; tmp3 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_xorsi3 ( tmp3 , tmp1 , tmp2 ) ) ; tmp4 = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp4 , tmp3 , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_xorsi3 ( tmp , tmp3 , tmp4 ) ) ; } else rs6000_emit_popcount ( tmp , src ) ; emit_insn ( gen_andsi3 ( dst , tmp , const1_rtx ) ) ; } else { if ( rs6000_cost -> muldi >= COSTS_N_INSNS ( 5 ) ) { rtx tmp1 , tmp2 , tmp3 , tmp4 , tmp5 , tmp6 ; tmp1 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_popcntbdi2 ( tmp1 , src ) ) ; tmp2 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp2 , tmp1 , GEN_INT ( 32 ) ) ) ; tmp3 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_xordi3 ( tmp3 , tmp1 , tmp2 ) ) ; tmp4 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp4 , tmp3 , GEN_INT ( 16 ) ) ) ; tmp5 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_xordi3 ( tmp5 , tmp3 , tmp4 ) ) ; tmp6 = gen_reg_rtx ( DImode ) ; emit_insn ( gen_lshrdi3 ( tmp6 , tmp5 , GEN_INT ( 8 ) ) ) ; emit_insn ( gen_xordi3 ( tmp , tmp5 , tmp6 ) ) ; } else rs6000_emit_popcount ( tmp , src ) ; emit_insn ( gen_anddi3 ( dst , tmp , const1_rtx ) ) ; } } </s>

Emit parity intrinsic on TARGET_POPCNTB targets . DST is the target , and SRC is the argument operand .


<s> bool sh_cfun_resbank_handler_p ( void ) { return ( ( lookup_attribute ( "resbank" , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ) && ( lookup_attribute ( "interrupt_handler" , DECL_ATTRIBUTES ( current_function_decl ) ) != NULL_TREE ) && TARGET_SH2A ) ; } </s>

Returns true if given tree has the `` resbank '' attribute set .


<s> void xstormy16_expand_epilogue ( void ) { struct xstormy16_stack_layout layout ; rtx mem_pop_rtx ; int regno ; const int ifun = xstormy16_interrupt_function_p ( ) ; mem_pop_rtx = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; mem_pop_rtx = gen_rtx_MEM ( HImode , mem_pop_rtx ) ; layout = xstormy16_compute_stack_layout ( ) ; if ( layout . locals_size ) { if ( frame_pointer_needed && layout . sp_minus_fp == layout . locals_size ) emit_move_insn ( stack_pointer_rtx , hard_frame_pointer_rtx ) ; else emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . locals_size ) ) ; } for ( regno = FIRST_PSEUDO_REGISTER - 1 ; regno >= 0 ; regno -- ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) emit_move_insn ( gen_rtx_REG ( HImode , regno ) , mem_pop_rtx ) ; if ( layout . stdarg_save_size ) emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . stdarg_save_size ) ) ; if ( ifun ) emit_jump_insn ( gen_return_internal_interrupt ( ) ) ; else emit_jump_insn ( gen_return_internal ( ) ) ; } </s>

Called after register allocation to add any instructions needed for the epilogue . Using an epilogue insn is favored compared to putting all of the instructions in the TARGET_ASM_FUNCTION_PROLOGUE macro , since it allows the scheduler to intermix instructions with the saves of the caller saved registers . In some cases , it might be necessary to emit a barrier instruction as the last insn to prevent such scheduling .


<s> rtx ix86_build_signbit_mask ( machine_mode mode , bool vect , bool invert ) { machine_mode vec_mode , imode ; HOST_WIDE_INT hi , lo ; int shift = 63 ; rtx v ; rtx mask ; switch ( mode ) { case V16SImode : case V16SFmode : case V8SImode : case V4SImode : case V8SFmode : case V4SFmode : vec_mode = mode ; mode = GET_MODE_INNER ( mode ) ; imode = SImode ; lo = 0x80000000 , hi = lo < 0 ; break ; case V8DImode : case V4DImode : case V2DImode : case V8DFmode : case V4DFmode : case V2DFmode : vec_mode = mode ; mode = GET_MODE_INNER ( mode ) ; imode = DImode ; if ( HOST_BITS_PER_WIDE_INT >= 64 ) lo = ( HOST_WIDE_INT ) 1 << shift , hi = - 1 ; else lo = 0 , hi = ( HOST_WIDE_INT ) 1 << ( shift - HOST_BITS_PER_WIDE_INT ) ; break ; case TImode : case TFmode : vec_mode = VOIDmode ; if ( HOST_BITS_PER_WIDE_INT >= 64 ) { imode = TImode ; lo = 0 , hi = ( HOST_WIDE_INT ) 1 << shift ; } else { rtvec vec ; imode = DImode ; lo = 0 , hi = ( HOST_WIDE_INT ) 1 << ( shift - HOST_BITS_PER_WIDE_INT ) ; if ( invert ) { lo = ~ lo , hi = ~ hi ; v = constm1_rtx ; } else v = const0_rtx ; mask = immed_double_const ( lo , hi , imode ) ; vec = gen_rtvec ( 2 , v , mask ) ; v = gen_rtx_CONST_VECTOR ( V2DImode , vec ) ; v = copy_to_mode_reg ( mode , gen_lowpart ( mode , v ) ) ; return v ; } break ; default : gcc_unreachable ( ) ; } if ( invert ) lo = ~ lo , hi = ~ hi ; mask = immed_double_const ( lo , hi , imode ) ; mask = gen_lowpart ( mode , mask ) ; if ( vec_mode == VOIDmode ) return force_reg ( mode , mask ) ; v = ix86_build_const_vector ( vec_mode , vect , mask ) ; return force_reg ( vec_mode , v ) ; } </s>

A subroutine of ix86_expand_fp_absneg_operator and copysign expanders . Create a mask for the sign bit in MODE for an SSE register . If VECT is true , then replicate the mask for all elements of the vector register . If INVERT is true , then create a mask excluding the sign bit .


<s>
bool
PIC16AsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
DbgInfo
.
EmitFileDirective
(
M
)
;
O
<<
"\n\t#include P16F1937.INC\n"
;
MachineModuleInfo
*
MMI
=
getAnalysisIfAvailable
<
MachineModuleInfo
>
(
)
;
assert
(
MMI
)
;
DwarfWriter
*
DW
=
getAnalysisIfAvailable
<
DwarfWriter
>
(
)
;
assert
(
DW
&&
"Dwarf Writer is not available"
)
;
DW
->
BeginModule
(
&
M
,
MMI
,
O
,
this
,
TAI
)
;
for
(
Module
::
global_iterator
I
=
M
.
global_begin
(
)
,
E
=
M
.
global_end
(
)
;
I
!=
E
;
++
I
)
{
I
->
setSection
(
TAI
->
SectionForGlobal
(
I
)
->
getName
(
)
)
;
}
EmitFunctionDecls
(
M
)
;
EmitUndefinedVars
(
M
)
;
EmitDefinedVars
(
M
)
;
EmitIData
(
M
)
;
EmitUData
(
M
)
;
EmitRomData
(
M
)
;
DbgInfo
.
PopulateFunctsDI
(
M
)
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < AAResultsWrapperPass > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> bool NVPTXPassConfig :: addPreRegAlloc ( ) { return false ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> static void AnalyzeArguments ( CCState & State , SmallVectorImpl < CCValAssign > & ArgLocs , const SmallVectorImpl < ArgT > & Args ) { static const uint16_t RegList [ ] = { MSP430 :: R15W , MSP430 :: R14W , MSP430 :: R13W , MSP430 :: R12W } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; if ( State . isVarArg ( ) ) { AnalyzeVarArgs ( State , Args ) ; return ; } SmallVector < unsigned , 4 > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; unsigned RegsLeft = NbRegs ; bool UseStack = false ; unsigned ValNo = 0 ; for ( unsigned i = 0 , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; ISD :: ArgFlagsTy ArgFlags = Args [ ValNo ] . Flags ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; if ( LocVT == MVT :: i8 ) { LocVT = MVT :: i16 ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } if ( ArgFlags . isByVal ( ) ) { State . HandleByVal ( ValNo ++ , ArgVT , LocVT , LocInfo , 2 , 2 , ArgFlags ) ; continue ; } unsigned Parts = ArgsParts [ i ] ; if ( ! UseStack && Parts <= RegsLeft ) { unsigned FirstVal = ValNo ; for ( unsigned j = 0 ; j < Parts ; j ++ ) { unsigned Reg = State . AllocateReg ( RegList , NbRegs ) ; State . addLoc ( CCValAssign :: getReg ( ValNo ++ , ArgVT , Reg , LocVT , LocInfo ) ) ; RegsLeft -- ; } SmallVectorImpl < CCValAssign > :: iterator B = ArgLocs . begin ( ) + FirstVal ; std :: reverse ( B , B + Parts ) ; } else { UseStack = true ; for ( unsigned j = 0 ; j < Parts ; j ++ ) CC_MSP430_AssignStack ( ValNo ++ , ArgVT , LocVT , LocInfo , ArgFlags , State ) ; } } } </s>

The function will invoke AnalyzeCallOperands .


"64-bit code requested on a subtarget that doesn't support it!"

This constructor initializes the data members to match that of the specified triple .


<s> void ARMTargetELFStreamer :: emitLabel ( MCSymbol * Symbol ) { ARMELFStreamer & Streamer = getStreamer ( ) ; if ( ! Streamer . IsThumb ) return ; const MCSymbolData & SD = Streamer . getOrCreateSymbolData ( Symbol ) ; if ( MCELF :: GetType ( SD ) & ( ELF :: STT_FUNC << ELF_STT_Shift ) ) Streamer . EmitThumbFunc ( Symbol ) ; } </s>

Emit a label for Symbol into the current section .


<s> static inline CSKYTargetStreamer :: SymbolIndex getEmptyKey ( ) { return { nullptr , CSKYMCExpr :: VK_CSKY_Invalid } ; } </s>

Empty key : no key should be generated that has no DILocalVariable .


<s> bool X86ATTAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; return false ; } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO ) ; else printOperand ( MI , OpNo ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] ) ; printOperand ( MI , OpNo ) ; return false ; case 'P' : print_pcrel_imm ( MI , OpNo ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> void X86FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; X86MachineFunctionInfo * X86FI = MF . getInfo < X86MachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = X86FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < 0 ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; } </s>

This method determines which of the registers reported by TargetRegisterInfo : :getCalleeSavedRegs ( ) should actually get saved .


<s>
bool
HexagonRDFOpt
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
if
(
skipFunction
(
*
MF
.
getFunction
(
)
)
)
return
false
;
if
(
RDFLimit
.
getPosition
(
)
)
{
if
(
RDFCount
>=
RDFLimit
)
return
false
;
RDFCount
++
;
}
MDT
=
&
getAnalysis
<
MachineDominatorTree
>
(
)
;
const
auto
&
MDF
=
getAnalysis
<
MachineDominanceFrontier
>
(
)
;
const
auto
&
HII
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getInstrInfo
(
)
;
const
auto
&
HRI
=
*
MF
.
getSubtarget
<
HexagonSubtarget
>
(
)
.
getRegisterInfo
(
)
;
MRI
=
&
MF
.
getRegInfo
(
)
;
bool
Changed
;
if
(
RDFDump
)
MF
.
print
(
dbgs
(
)
<<
"Before "
<<
getPassName
(
)
<<
"\n"
,
nullptr
)
;
TargetOperandInfo
TOI
(
HII
)
;
DataFlowGraph
G
(
MF
,
HII
,
HRI
,
*
MDT
,
MDF
,
TOI
)
;
G
.
build
(
BuildOptions
::
KeepDeadPhis
)
;
if
(
RDFDump
)
dbgs
(
)
<<
"Starting copy propagation on: "
<<
MF
.
getName
(
)
<<
'\n'
<<
PrintNode
<
FuncNode
*
>
(
G
.
getFunc
(
)
,
G
)
<<
'\n'
;
HexagonCP
CP
(
G
)
;
CP
.
trace
(
RDFDump
)
;
Changed
=
CP
.
run
(
)
;
if
(
RDFDump
)
dbgs
(
)
<<
"Starting dead code elimination on: "
<<
MF
.
getName
(
)
<<
'\n'
<<
PrintNode
<
FuncNode
*
>
(
G
.
getFunc
(
)
,
G
)
<<
'\n'
;
HexagonDCE
DCE
(
G
,
*
MRI
)
;
DCE
.
trace
(
RDFDump
)
;
Changed
|=
DCE
.
run
(
)
;
if
(
Changed
)
{
if
(
RDFDump
)
dbgs
(
)
<<
"Starting liveness recomputation on: "
<<
MF
.
getName
(
)
<<
'\n'
;
Liveness
LV
(
*
MRI
,
G
)
;
LV
.
trace
(
RDFDump
)
;
LV
.
computeLiveIns
(
)
;
LV
.
resetLiveIns
(
)
;
LV
.
resetKills
(
)
;
}
if
(
RDFDump
)
MF
.
print
(
dbgs
(
)
<<
"After "
<<
getPassName
(
)
<<
"\n"
,
nullptr
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Hexagon
Hexagon
Hexagon
Hexagon
"Before "
"\n"
"Starting copy propagation on: "
Hexagon
"Starting dead code elimination on: "
Hexagon
"Starting liveness recomputation on: "
"After "
"\n"


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { MRI = & MF . getRegInfo ( ) ; MFI = MF . getInfo < WebAssemblyFunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ; } </s>


<s> bool PPCDarwinAsmPrinter :: doFinalization ( Module & M ) { bool isPPC64 = getDataLayout ( ) . getPointerSizeInBits ( ) == 64 ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; MachineModuleInfoMachO & MMIMacho = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoMachO :: SymbolListTy Stubs = MMIMacho . GetFnStubList ( ) ; if ( ! Stubs . empty ( ) ) EmitFunctionStubs ( Stubs ) ; if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { for ( const Function * Personality : MMI -> getPersonalities ( ) ) { if ( Personality ) { MCSymbol * NLPSym = getSymbolWithGlobalValueBase ( Personality , "$non_lazy_ptr" ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( Personality ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( 0 , isPPC64 ? 8 : 4 ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( isPPC64 ? 3 : 2 ) ; for ( unsigned i = 0 , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , isPPC64 ? 8 : 4 ) ; } Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; return AsmPrinter :: doFinalization ( M ) ; } </s>

doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run .


<s> bool ARMSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_NONE ; return PostRAScheduler && OptLevel >= CodeGenOpt :: Default ; } </s>

True if the subtarget should run a scheduler after register allocation .