<s> static bool isSplat ( SDValue V ) { if ( V . getOpcode ( ) != ISD :: BUILD_VECTOR ) return false ; SDValue First = V . getOperand ( 0 ) ; for ( unsigned I = 1 , E = V . getNumOperands ( ) ; I != E ; ++ I ) if ( V . getOperand ( I ) != First ) return false ; return true ; } </s>

Returns true if this is a splat constant , meaning that all elements have the same value .


<s> static int arm_save_coproc_regs ( void ) { int saved_size = 0 ; unsigned reg ; unsigned start_reg ; rtx insn ; if ( TARGET_REALLY_IWMMXT ) for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( reg_needs_saving_p ( reg ) ) { insn = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; insn = gen_rtx_MEM ( V2SImode , insn ) ; insn = emit_set_insn ( insn , gen_rtx_REG ( V2SImode , reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; saved_size += 8 ; } if ( TARGET_VFP_BASE ) { start_reg = FIRST_VFP_REGNUM ; for ( reg = FIRST_VFP_REGNUM ; reg < LAST_VFP_REGNUM ; reg += 2 ) { if ( ! reg_needs_saving_p ( reg ) && ! reg_needs_saving_p ( reg + 1 ) ) { if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; start_reg = reg + 2 ; } } if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; } return saved_size ; } </s>

Emit RTL to save coprocessor registers on function entry . Returns the number of bytes pushed .


<s> static rtx ft32_libcall_value ( machine_mode mode , const_rtx fun ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( mode , FT32_R0 ) ; } </s>

Define how to find the value returned by a library function . We always return values in register $ r0 for ft32 .


"Instr doesn't have FrameIndex operand!"

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead .


<s> void xstormy16_expand_call ( rtx retval , rtx dest , rtx counter ) { rtx call , temp ; enum machine_mode mode ; gcc_assert ( GET_CODE ( dest ) == MEM ) ; dest = XEXP ( dest , 0 ) ; if ( ! CONSTANT_P ( dest ) && GET_CODE ( dest ) != REG ) dest = force_reg ( Pmode , dest ) ; if ( retval == NULL ) mode = VOIDmode ; else mode = GET_MODE ( retval ) ; call = gen_rtx_CALL ( mode , gen_rtx_MEM ( FUNCTION_MODE , dest ) , counter ) ; if ( retval ) call = gen_rtx_SET ( VOIDmode , retval , call ) ; if ( ! CONSTANT_P ( dest ) ) { temp = gen_reg_rtx ( HImode ) ; emit_move_insn ( temp , const0_rtx ) ; } else temp = const0_rtx ; call = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , call , gen_rtx_USE ( VOIDmode , temp ) ) ) ; emit_call_insn ( call ) ; } </s>

Expander for the ` call ' patterns . INDEX is the index of the switch statement . LOWER_BOUND is a CONST_INT that is the value of INDEX corresponding to the first table entry . RANGE is the number of table entries . TABLE is an ADDR_VEC that is the jump table . DEFAULT_LABEL is the address to branch to if INDEX is outside the range LOWER_BOUND to LOWER_BOUND+RANGE-1 .


<s> static void m32r_function_arg_advance ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum = ( ROUND_ADVANCE_CUM ( * cum , arg . mode , arg . type ) + ROUND_ADVANCE_ARG ( arg . mode , arg . type ) ) ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE . ( TYPE is null for libcalls where that information may not be available . )


<s> AVRTargetLowering :: ConstraintType AVRTargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { default : break ; case 'a' : case 'b' : case 'd' : case 'l' : case 'e' : case 'q' : case 'r' : case 'w' : return C_RegisterClass ; case 't' : case 'x' : case 'X' : case 'y' : case 'Y' : case 'z' : case 'Z' : return C_Register ; case 'Q' : return C_Memory ; case 'G' : case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : case 'R' : return C_Immediate ; } } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> static int tilegx_issue_rate ( void ) { return 3 ; } </s>


<s> static void unicosmk_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { const char * kind ; fputs ( "\t.endp\n\n" , asm_out_file ) ; if ( flags & SECTION_MAIN ) fputs ( "\t.start\tmain\n" , asm_out_file ) ; if ( flags & SECTION_CODE ) kind = "code" ; else if ( flags & SECTION_PUBLIC ) kind = "common" ; else kind = "data" ; if ( current_section_align != 0 ) fprintf ( asm_out_file , "\t.psect\t%s,%d,%s\n" , name , current_section_align , kind ) ; else fprintf ( asm_out_file , "\t.psect\t%s,%s\n" , name , kind ) ; } </s>

Switch to an arbitrary section NAME with attributes as specified by FLAGS . ALIGN specifies any known alignment requirements for the section ; 0 if the default should be used .


<s> bool TeakTargetLowering :: isNarrowingProfitable ( EVT VT1 , EVT VT2 ) const { return VT2 != MVT :: i8 && VT2 != MVT :: i1 ; } </s>

Return true if it 's profitable to narrow operations of type SrcVT to DestVT .


<s> bool X86TargetLowering :: supportSwiftError ( ) const { return Subtarget . is64Bit ( ) ; } </s>

Return true if the target supports swifterror attribute .


<s> static bool s390_short_displacement ( rtx disp ) { if ( ! disp ) return true ; if ( GET_CODE ( disp ) == CONST_INT ) return INTVAL ( disp ) >= 0 && INTVAL ( disp ) < 4096 ; if ( GET_CODE ( disp ) == CONST && GET_CODE ( XEXP ( disp , 0 ) ) == UNSPEC && ( XINT ( XEXP ( disp , 0 ) , 1 ) == UNSPEC_GOT || XINT ( XEXP ( disp , 0 ) , 1 ) == UNSPEC_GOTNTPOFF ) ) return false ; if ( GET_CODE ( disp ) == CONST ) return true ; return false ; } </s>

Return true if DISP is a valid short displacement .


<s> const uint32_t * VERegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static void rs6000_emit_nmsub ( rtx dst , rtx m1 , rtx m2 , rtx a ) { machine_mode mode = GET_MODE ( dst ) ; rtx r ; gcc_assert ( optab_handler ( fma_optab , mode ) != CODE_FOR_nothing ) ; r = gen_rtx_NEG ( mode , a ) ; r = gen_rtx_FMA ( mode , m1 , m2 , r ) ; r = gen_rtx_NEG ( mode , r ) ; emit_insn ( gen_rtx_SET ( dst , r ) ) ; } </s>

Generate a FNMSUB instruction : dst = -fma ( m1 , m2 , -a ) .


<s> SystemZSubtarget & SystemZSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = "generic" ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


"%q+D:'selectany' attribute applies only to "

Cover function to implement ENCODE_SECTION_INFO .


<s> static void ix86_add_new_builtins ( HOST_WIDE_INT isa , HOST_WIDE_INT isa2 ) { if ( ( isa & deferred_isa_values ) == 0 && ( isa2 & deferred_isa_values2 ) == 0 ) return ; deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = 0 ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != 0 || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != 0 ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = 1 ; if ( ix86_builtins_isa [ i ] . leaf_p ) DECL_ATTRIBUTES ( decl ) = build_tree_list ( get_identifier ( "leaf" ) , NULL_TREE ) ; if ( ix86_builtins_isa [ i ] . nothrow_p ) TREE_NOTHROW ( decl ) = 1 ; } } current_target_pragma = saved_current_target_pragma ; } </s>

Add any new builtin functions for a given ISA that may not have been declared . This saves a bit of space compared to adding all of the declarations to the tree , even if we did n't use them .


<s> Register MSP430RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const MSP430FrameLowering * TFI = getFrameLowering ( MF ) ; return TFI -> hasFP ( MF ) ? MSP430 :: R4 : MSP430 :: SP ; } </s>


<s> bool AArch64InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , Register & SrcReg , Register & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case AArch64 :: SBFMXri : case AArch64 :: UBFMXri : if ( MI . getOperand ( 2 ) . getImm ( ) != 0 || MI . getOperand ( 3 ) . getImm ( ) != 31 ) return false ; SrcReg = MI . getOperand ( 1 ) . getReg ( ) ; DstReg = MI . getOperand ( 0 ) . getReg ( ) ; SubIdx = AArch64 :: sub_32 ; return true ; } } </s>

isCoalescableExtInstr - Return true if the instruction is a `` coalescable '' extension instruction .


<s>
void
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
)
const
override
{
unsigned
Size
=
1
<<
getFixupKindLog2Size
(
Fixup
.
getKind
(
)
)
;
assert
(
Fixup
.
getOffset
(
)
+
Size
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
assert
(
isIntN
(
Size
*
8
+
1
,
Value
)
&&
"Value does not fit in the Fixup field"
)
;
for
(
unsigned
i
=
0
;
i
!=
Size
;
++
i
)
Data
[
Fixup
.
getOffset
(
)
+
i
]
=
uint8_t
(
Value
>>
(
i
*
8
)
)
;
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void AnalyzeReturn ( const SmallVectorImpl < ISD :: OutputArg > & Outs , CCAssignFn Fn ) { PreAnalyzeReturn ( Outs , Fn ) ; CCState :: AnalyzeReturn ( Outs , Fn ) ; } </s>

AnalyzeReturn - Analyze the returned values of a return , incorporating info about the result values into this state .


<s> void Note ( SMLoc L , const Twine & Msg , SMRange Range = None ) { return getParser ( ) . Note ( L , Msg , Range ) ; } </s>

Emit a note at the location L , with the message Msg .


<s>
StringRef
getPassName
(
)
const
override
{
return
"X86 Fixup Store Forward Block"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void MOSPassConfig :: addPreRegBankSelect ( ) { addPass ( createMOSCombiner ( ) ) ; addPass ( createMOSLowerSelectPass ( ) ) ; } </s>

This method may be implemented by targets that want to run passes immediately before the register bank selection .


<s>
const
char
*
getPassName
(
)
const
override
{
return
"BPF Assembly Printer"
;
}
</s>


<s> bool HexagonEarlyIfConversion :: isValid ( const FlowPattern & FP ) const { if ( hasEHLabel ( FP . SplitB ) ) return false ; if ( FP . TrueB && ! isValidCandidate ( FP . TrueB ) ) return false ; if ( FP . FalseB && ! isValidCandidate ( FP . FalseB ) ) return false ; if ( FP . JoinB ) { const MachineBasicBlock & B = * FP . JoinB ; for ( auto & MI : B ) { if ( ! MI . isPHI ( ) ) break ; if ( usesUndefVReg ( & MI ) ) return false ; Register DefR = MI . getOperand ( 0 ) . getReg ( ) ; if ( isPredicate ( DefR ) ) return false ; } } return true ; } </s>

Returns true if this iterator is still pointing at a valid entry .


<s>
unsigned
Mips16InstrInfo
::
getOppositeBranchOpc
(
unsigned
Opc
)
const
{
switch
(
Opc
)
{
default
:
llvm_unreachable
(
"Illegal opcode!"
)
;
case
Mips
::
BeqzRxImmX16
:
return
Mips
::
BnezRxImmX16
;
case
Mips
::
BnezRxImmX16
:
return
Mips
::
BeqzRxImmX16
;
case
Mips
::
BeqzRxImm16
:
return
Mips
::
BnezRxImm16
;
case
Mips
::
BnezRxImm16
:
return
Mips
::
BeqzRxImm16
;
case
Mips
::
BteqzT8CmpX16
:
return
Mips
::
BtnezT8CmpX16
;
case
Mips
::
BteqzT8SltX16
:
return
Mips
::
BtnezT8SltX16
;
case
Mips
::
BteqzT8SltiX16
:
return
Mips
::
BtnezT8SltiX16
;
case
Mips
::
Btnez16
:
return
Mips
::
Bteqz16
;
case
Mips
::
BtnezX16
:
return
Mips
::
BteqzX16
;
case
Mips
::
BtnezT8CmpiX16
:
return
Mips
::
BteqzT8CmpiX16
;
case
Mips
::
BtnezT8SltuX16
:
return
Mips
::
BteqzT8SltuX16
;
case
Mips
::
BtnezT8SltiuX16
:
return
Mips
::
BteqzT8SltiuX16
;
case
Mips
::
Bteqz16
:
return
Mips
::
Btnez16
;
case
Mips
::
BteqzX16
:
return
Mips
::
BtnezX16
;
case
Mips
::
BteqzT8CmpiX16
:
return
Mips
::
BtnezT8CmpiX16
;
case
Mips
::
BteqzT8SltuX16
:
return
Mips
::
BtnezT8SltuX16
;
case
Mips
::
BteqzT8SltiuX16
:
return
Mips
::
BtnezT8SltiuX16
;
case
Mips
::
BtnezT8CmpX16
:
return
Mips
::
BteqzT8CmpX16
;
case
Mips
::
BtnezT8SltX16
:
return
Mips
::
BteqzT8SltX16
;
case
Mips
::
BtnezT8SltiX16
:
return
Mips
::
BteqzT8SltiX16
;
}
assert
(
false
&&
"Implement this function."
)
;
return
0
;
}
</s>

getOppositeBranchOpc - Return the inverse of the specified opcode , e.g .


<s>
MachineBasicBlock
*
MSP430TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
->
getOpcode
(
)
;
if
(
Opc
==
MSP430
::
Shl8
||
Opc
==
MSP430
::
Shl16
||
Opc
==
MSP430
::
Sra8
||
Opc
==
MSP430
::
Sra16
||
Opc
==
MSP430
::
Srl8
||
Opc
==
MSP430
::
Srl16
)
return
EmitShiftInstr
(
MI
,
BB
)
;
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
Opc
==
MSP430
::
Select16
||
Opc
==
MSP430
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
MSP430
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
->
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
MSP430
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static int mn10300_address_cost ( rtx x ) { int s = 0 ; return mn10300_address_cost_1 ( x , & s ) ; } </s>

For addresses , costs are relative to `` MOV ( Rm ) , Rn '' . For AM33 this is the 3-byte fully general instruction ; for MN103 this is the 2-byte form with an address register .


<s> static void mcore_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; rtx mem ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( 2 * UNITS_PER_WORD ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , 8 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , 12 ) ; emit_move_insn ( mem , fnaddr ) ; } </s>

Worker function for TARGET_TRAMPOLINE_INIT .


"NVPTX Proxy Register Instruction Erasure"


<s> CCAssignFn * AArch64TargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC ) const { return CC == CallingConv :: WebKit_JS ? RetCC_AArch64_WebKit_JS : RetCC_AArch64_AAPCS ; } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


<s> void EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = 0 ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * 8 : ( Size - 1 - i ) * 8 ; EmitByte ( ( Val >> Shift ) & 0xff , OS ) ; } } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool GBZ80TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return true ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s>
SDValue
DCPU16TargetLowering
::
LowerCall
(
TargetLowering
::
CallLoweringInfo
&
CLI
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
SelectionDAG
&
DAG
=
CLI
.
DAG
;
DebugLoc
&
dl
=
CLI
.
DL
;
SmallVector
<
ISD
::
OutputArg
,
32
>
&
Outs
=
CLI
.
Outs
;
SmallVector
<
SDValue
,
32
>
&
OutVals
=
CLI
.
OutVals
;
SmallVector
<
ISD
::
InputArg
,
32
>
&
Ins
=
CLI
.
Ins
;
SDValue
Chain
=
CLI
.
Chain
;
SDValue
Callee
=
CLI
.
Callee
;
bool
&
isTailCall
=
CLI
.
IsTailCall
;
CallingConv
::
ID
CallConv
=
CLI
.
CallConv
;
bool
isVarArg
=
CLI
.
IsVarArg
;
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
DCPU16_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> SDValue expand ( SDValue V ) { SDLoc DL ( V ) ; EVT VT = V . getValueType ( ) ; unsigned VectWidth = VT . getVectorNumElements ( ) ; if ( V . getOpcode ( ) == ISD :: BUILD_VECTOR ) { if ( isSplat ( V ) ) return V ; if ( ! isBuildVectorWithUndefs ( V ) ) return SDValue ( ) ; SmallVector < SDValue , 64 > Args ; Args . append ( VectWidth , V . getOperand ( 0 ) ) ; return DAG . getNode ( ISD :: BUILD_VECTOR , DL , VT , Args ) ; } if ( isBinaryVectorOperation ( V ) ) { SDValue Op1 = V . getOperand ( 0 ) ; SDValue Op2 = V . getOperand ( 1 ) ; SDValue NewOp1 = expand ( Op1 ) ; if ( ! NewOp1 ) return SDValue ( ) ; SDValue NewOp2 = expand ( Op2 ) ; if ( ! NewOp2 ) return SDValue ( ) ; return DAG . getNode ( V . getOpcode ( ) , DL , VT , NewOp1 , NewOp2 ) ; } return SDValue ( ) ; } </s>

expand - Expand a record into a set of elements if possible .


<s> static bool pa_print_operand_punct_valid_p ( unsigned char code ) { if ( code == '@' || code == '#' || code == '*' || code == '^' ) return true ; return false ; } </s>

Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook .


<s> static rtx arm_gen_store_multiple_1 ( int count , int * regs , rtx * mems , rtx basereg , HOST_WIDE_INT wback_offset ) { int i = 0 , j ; rtx result ; if ( GET_CODE ( basereg ) == PLUS ) basereg = XEXP ( basereg , 0 ) ; if ( ! multiple_operation_profitable_p ( false , count , 0 ) ) { rtx seq ; start_sequence ( ) ; for ( i = 0 ; i < count ; i ++ ) emit_move_insn ( mems [ i ] , gen_rtx_REG ( SImode , regs [ i ] ) ) ; if ( wback_offset != 0 ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; return seq ; } result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( wback_offset != 0 ? 1 : 0 ) ) ) ; if ( wback_offset != 0 ) { XVECEXP ( result , 0 , 0 ) = gen_rtx_SET ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; i = 1 ; count ++ ; } for ( j = 0 ; i < count ; i ++ , j ++ ) XVECEXP ( result , 0 , i ) = gen_rtx_SET ( mems [ j ] , gen_rtx_REG ( SImode , regs [ j ] ) ) ; return result ; } </s>

Generate a store-multiple instruction . COUNT is the number of stores in the instruction ; REGS and MEMS are arrays containing the operands . BASEREG is the base register to be used in addressing the memory operands . WBACK_OFFSET is nonzero if the instruction should update the base register .


<s> Register ARMBaseRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const ARMSubtarget & STI = MF . getSubtarget < ARMSubtarget > ( ) ; const ARMFrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return STI . getFramePointerReg ( ) ; return ARM :: SP ; } </s>


<s> void M88kAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( I -> isBundle ( ) ) continue ; MCInst LoweredMI ; switch ( I -> getOpcode ( ) ) { case M88k :: RET : LoweredMI = MCInstBuilder ( M88k :: JMP ) . addReg ( M88k :: R1 ) ; break ; case M88k :: RETn : LoweredMI = MCInstBuilder ( M88k :: JMPn ) . addReg ( M88k :: R1 ) ; break ; default : M88kMCInstLower Lower ( MF -> getContext ( ) , * this ) ; Lower . lower ( & * I , LoweredMI ) ; break ; } EmitToStreamer ( * OutStreamer , LoweredMI ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

Targets should implement this to emit instructions .


<s> static void increment_stack ( signed int amount , bool in_prologue ) { rtx inc ; if ( amount == 0 ) return ; inc = GEN_INT ( amount ) ; if ( ! CONST_OK_FOR_K ( amount ) ) { rtx reg = gen_rtx_REG ( Pmode , 12 ) ; inc = emit_move_insn ( reg , inc ) ; if ( in_prologue ) F ( inc ) ; inc = reg ; } inc = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , inc ) ) ; if ( in_prologue ) F ( inc ) ; } </s>

Common code to change the stack pointer .


"can't use non gp relative absolute address"

A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand that is a memory reference whose address is ADDR . ADDR is an RTL expression . On some machines , the syntax for a symbolic address depends on the section that the address refers to . On these machines , define the macro ` ENCODE_SECTION_INFO ' to store the information into the ` symbol_ref ' , and then check for it here .


"@c Copyright (C) 2012-2015 Free Software Foundation, Inc.\n"

"@c For copying conditions, see the file "

"@c This file is generated automatically using\n"

Main program to convert flat files into built-in initialization code .


<s> bool GCNPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; addPass ( createSIAddIMGInitPass ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s>
void
TeakTargetLowering
::
ReplaceNodeResults
(
SDNode
*
N
,
SmallVectorImpl
<
SDValue
>
&
Results
,
SelectionDAG
&
DAG
)
const
{
dbgs
(
)
<<
"Opcode = "
<<
N
->
getOpcode
(
)
;
DAG
.
dump
(
)
;
N
->
dumpr
(
&
DAG
)
;
SDLoc
dl
(
N
)
;
SDValue
Res
=
LowerOperation
(
SDValue
(
N
,
0
)
,
DAG
)
;
for
(
unsigned
I
=
0
,
E
=
Res
->
getNumValues
(
)
;
I
!=
E
;
++
I
)
Results
.
push_back
(
Res
.
getValue
(
I
)
)
;
}
</s>

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s> static bool classof ( const AArch64MCExpr * ) { return true ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


<s> static int num_insns_constant_multi ( HOST_WIDE_INT value , machine_mode mode ) { int nregs = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ; int total = 0 ; while ( nregs -- > 0 ) { HOST_WIDE_INT low = sext_hwi ( value , BITS_PER_WORD ) ; int insns = num_insns_constant_gpr ( low ) ; if ( insns > 2 && rs6000_is_valid_and_mask ( GEN_INT ( low ) , DImode ) ) insns = 2 ; total += insns ; value >>= BITS_PER_WORD ; } return total ; } </s>

Helper for num_insns_constant . Allow constants formed by the num_insns_constant_gpr sequences , plus li -1 , rldicl/rldicr/rlwinm , and handle modes that require multiple gprs .


<s> int fp_high_losum_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { REAL_VALUE_TYPE r ; long i ; REAL_VALUE_FROM_CONST_DOUBLE ( r , op ) ; REAL_VALUE_TO_TARGET_SINGLE ( r , i ) ; return ! SPARC_SIMM13_P ( i ) && ! SPARC_SETHI_P ( i ) ; } return 0 ; } </s>

Nonzero if OP is a floating point constant which can be loaded into an integer register using a high/losum instruction sequence .


<s>
bool
NVPTXAsmPrinter
::
lowerOperand
(
const
MachineOperand
&
MO
,
MCOperand
&
MCOp
)
{
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
"unknown operand type"
)
;
case
MachineOperand
::
MO_Register
:
MCOp
=
MCOperand
::
CreateReg
(
encodeVirtualRegister
(
MO
.
getReg
(
)
)
)
;
break
;
case
MachineOperand
::
MO_Immediate
:
MCOp
=
MCOperand
::
CreateImm
(
MO
.
getImm
(
)
)
;
break
;
case
MachineOperand
::
MO_MachineBasicBlock
:
MCOp
=
MCOperand
::
CreateExpr
(
MCSymbolRefExpr
::
Create
(
MO
.
getMBB
(
)
->
getSymbol
(
)
,
OutContext
)
)
;
break
;
case
MachineOperand
::
MO_ExternalSymbol
:
MCOp
=
GetSymbolRef
(
MO
,
GetExternalSymbolSymbol
(
MO
.
getSymbolName
(
)
)
)
;
break
;
case
MachineOperand
::
MO_GlobalAddress
:
MCOp
=
GetSymbolRef
(
MO
,
getSymbol
(
MO
.
getGlobal
(
)
)
)
;
break
;
case
MachineOperand
::
MO_FPImmediate
:
{
const
ConstantFP
*
Cnt
=
MO
.
getFPImm
(
)
;
APFloat
Val
=
Cnt
->
getValueAPF
(
)
;
switch
(
Cnt
->
getType
(
)
->
getTypeID
(
)
)
{
default
:
report_fatal_error
(
"Unsupported FP type"
)
;
break
;
case
Type
::
FloatTyID
:
MCOp
=
MCOperand
::
CreateExpr
(
NVPTXFloatMCExpr
::
CreateConstantFPSingle
(
Val
,
OutContext
)
)
;
break
;
case
Type
::
DoubleTyID
:
MCOp
=
MCOperand
::
CreateExpr
(
NVPTXFloatMCExpr
::
CreateConstantFPDouble
(
Val
,
OutContext
)
)
;
break
;
}
break
;
}
}
return
true
;
}
</s>

Wrapper for MCInstLowering.lowerOperand ( ) for the tblgen'erated pseudo lowering .

NVPTX
NVPTX
"unknown operand type"
"Unsupported FP type"
NVPTX
NVPTX


<s>
const
char
*
getPassName
(
)
const
override
{
return
"X86 Enqueue Exit Blocks"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> static void emit_and_preserve ( rtx seq , rtx reg , rtx reg2 ) { HOST_WIDE_INT offset = 16 * UNITS_PER_WORD ; HOST_WIDE_INT size = SPARC_STACK_ALIGN ( offset + 2 * UNITS_PER_WORD ) ; rtx slot = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , stack_pointer_rtx , SPARC_STACK_BIAS + offset ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - size ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , slot , reg ) ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( VOIDmode , adjust_address ( slot , word_mode , UNITS_PER_WORD ) , reg2 ) ) ; emit_insn ( seq ) ; if ( reg2 ) emit_insn ( gen_rtx_SET ( VOIDmode , reg2 , adjust_address ( slot , word_mode , UNITS_PER_WORD ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , reg , slot ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; } </s>

Emit the sequence of insns SEQ while preserving the registers .


<s> bool SparcPassConfig :: addInstSelector ( ) { PM . add ( createSparcISelDag ( getSparcTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


"Branch-taken block should post-dominate first candidate"

"Error in code produced by branch coalescing"

runOnMachineFunction - Emit the function body .


<s>
void
machopic_output_stub
(
FILE
*
file
,
const
char
*
symb
,
const
char
*
stub
)
{
unsigned
int
length
;
char
*
symbol_name
,
*
lazy_ptr_name
;
char
*
local_label_0
;
static
int
label
=
0
;
symb
=
(
*
targetm
.
strip_name_encoding
)
(
symb
)
;
length
=
strlen
(
symb
)
;
symbol_name
=
alloca
(
length
+
32
)
;
GEN_SYMBOL_NAME_FOR_SYMBOL
(
symbol_name
,
symb
,
length
)
;
lazy_ptr_name
=
alloca
(
length
+
32
)
;
GEN_LAZY_PTR_NAME_FOR_SYMBOL
(
lazy_ptr_name
,
symb
,
length
)
;
if
(
flag_pic
==
2
)
machopic_picsymbol_stub1_section
(
)
;
else
machopic_symbol_stub1_section
(
)
;
if
(
flag_pic
==
2
)
{
fprintf
(
file
,
"\t.align 5\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
label
++
;
local_label_0
=
alloca
(
sizeof
(
"\"L00000000000$spb\""
)
)
;
sprintf
(
local_label_0
,
"\"L%011d$spb\""
,
label
)
;
fprintf
(
file
,
"\tmflr r0\n"
)
;
fprintf
(
file
,
"\tbcl 20,31,%s\n"
,
local_label_0
)
;
fprintf
(
file
,
"%s:\n\tmflr r11\n"
,
local_label_0
)
;
fprintf
(
file
,
"\taddis r11,r11,ha16(%s-%s)\n"
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtlr r0\n"
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s-%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
,
local_label_0
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
else
{
fprintf
(
file
,
"\t.align 4\n"
)
;
fprintf
(
file
,
"%s:\n"
,
stub
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"\tlis r11,ha16(%s)\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t%s r12,lo16(%s)(r11)\n"
,
(
TARGET_64BIT
"ldu"
:
"lwzu"
)
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\tmtctr r12\n"
)
;
fprintf
(
file
,
"\tbctr\n"
)
;
}
machopic_lazy_symbol_ptr_section
(
)
;
fprintf
(
file
,
"%s:\n"
,
lazy_ptr_name
)
;
fprintf
(
file
,
"\t.indirect_symbol %s\n"
,
symbol_name
)
;
fprintf
(
file
,
"%sdyld_stub_binding_helper\n"
,
(
TARGET_64BIT
DOUBLE_INT_ASM_OP
:
"\t.long\t"
)
)
;
}
</s>

Generate external symbol indirection stubs ( PIC and non-PIC ) .


<s> bool supportSplitCSR ( MachineFunction * MF ) const override { return MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ; } </s>

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies .


<s> bool aarch64_is_extend_from_extract ( machine_mode mode , rtx mult_imm , rtx extract_imm ) { HOST_WIDE_INT mult_val , extract_val ; if ( ! CONST_INT_P ( mult_imm ) || ! CONST_INT_P ( extract_imm ) ) return false ; mult_val = INTVAL ( mult_imm ) ; extract_val = INTVAL ( extract_imm ) ; if ( extract_val > 8 && extract_val < GET_MODE_BITSIZE ( mode ) && exact_log2 ( extract_val & ~ 7 ) > 0 && ( extract_val & 7 ) <= 4 && mult_val == ( 1 << ( extract_val & 7 ) ) ) return true ; return false ; } </s>

Return true if the offsets to a zero/sign-extract operation represent an expression that matches an extend operation . The operands represent the paramters from ( extract : MODE ( mult ( reg ) ( MULT_IMM ) ) ( EXTRACT_IMM ) ( const_int 0 ) ) .


<s> int legitimate_address_p ( enum machine_mode mode , rtx address ) { GO_IF_LEGITIMATE_ADDRESS ( mode , address , win ) ; return 0 ; win : return 1 ; } </s>

legitimate_address_p returns 1 if it recognizes an RTL expression `` x '' that is a valid memory address for an instruction . The MODE argument is the machine mode for the MEM expression that wants to use this address .


<s> TargetPassConfig * rvexTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new rvexPassConfig ( this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> unsigned getNumFixupKinds ( ) const override { return Nios2 :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s>
void
BlackfinRegisterInfo
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
TargetFrameInfo
*
TFI
=
MF
.
getTarget
(
)
.
getFrameInfo
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
!=
0
)
{
assert
(
Amount
%
4
==
0
&&
"Unaligned call frame size"
)
;
if
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKDOWN
)
{
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
else
{
assert
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKUP
&&
"Unknown call frame pseudo instruction"
)
;
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
}
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> void print ( raw_ostream & OS ) const override { switch ( Kind ) { case Token : OS << "Tok:" << Tok . Tok ; break ; case Integer : OS << "Int:" << Int . Val ; break ; case Float : OS << "Flt:" << Flt . Val ; break ; case Symbol : OS << "Sym:" << Sym . Exp ; break ; case BrList : OS << "BrList:" << BrL . List . size ( ) ; break ; } } </s>

print - Print a debug representation of the operand to the given stream .

WebAssembly "Tok:" "Int:" "Flt:" "Sym:" "BrList:"


<s> bool mips_legitimize_move ( enum machine_mode mode , rtx dest , rtx src ) { if ( ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) { emit_move_insn ( dest , force_reg ( mode , src ) ) ; return true ; } if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD && REG_P ( src ) && MD_REG_P ( REGNO ( src ) ) && REG_P ( dest ) && GP_REG_P ( REGNO ( dest ) ) ) { int other_regno = REGNO ( src ) == HI_REGNUM ? LO_REGNUM : HI_REGNUM ; if ( GET_MODE_SIZE ( mode ) <= 4 ) emit_insn ( gen_mfhilo_si ( gen_rtx_REG ( SImode , REGNO ( dest ) ) , gen_rtx_REG ( SImode , REGNO ( src ) ) , gen_rtx_REG ( SImode , other_regno ) ) ) ; else emit_insn ( gen_mfhilo_di ( gen_rtx_REG ( DImode , REGNO ( dest ) ) , gen_rtx_REG ( DImode , REGNO ( src ) ) , gen_rtx_REG ( DImode , other_regno ) ) ) ; return true ; } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { mips_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ; } return false ; } </s>

If ( set DEST SRC ) is not a valid instruction , emit an equivalent sequence that is valid .


<s> void AMDGPUSubtarget :: overrideSchedPolicy ( MachineSchedPolicy & Policy , MachineInstr * begin , MachineInstr * end , unsigned NumRegionInstrs ) const { if ( getGeneration ( ) >= SOUTHERN_ISLANDS ) { Policy . ShouldTrackPressure = true ; Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ; if ( ! enableSIScheduler ( ) ) Policy . ShouldTrackLaneMasks = true ; } } </s>

Override generic scheduling policy within a region .


<s> static std :: unique_ptr < P2Operand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < P2Operand > ( k_Register ) ; Op -> Reg . RegNum = RegNum ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ; } </s>

CreateReg - Allocate a single virtual register for the given type .


<s> void output_profile_hook ( int labelno ATTRIBUTE_UNUSED ) { if ( TARGET_PROFILE_KERNEL ) return ; if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) { if ( NO_PROFILE_COUNTERS ) emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode ) ; else { char buf [ 30 ] ; const char * label_name ; rtx fun ; ASM_GENERATE_INTERNAL_LABEL ( buf , "LP" , labelno ) ; label_name = ggc_strdup ( ( * targetm . strip_name_encoding ) ( buf ) ) ; fun = gen_rtx_SYMBOL_REF ( Pmode , label_name ) ; emit_library_call ( init_one_libfunc ( RS6000_MCOUNT ) , LCT_NORMAL , VOIDmode , fun , Pmode ) ; } } else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LR_REGNO ; crtl -> uses_pic_offset_table = 1 ; if ( MACHOPIC_INDIRECT && crtl -> uses_pic_offset_table ) caller_addr_regno = 0 ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , mcount_name ) , LCT_NORMAL , VOIDmode , gen_rtx_REG ( Pmode , caller_addr_regno ) , Pmode ) ; } } </s>


<s> Value * AArch64TargetLowering :: emitStoreConditional ( IRBuilder < > & Builder , Value * Val , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; bool IsRelease = isAtLeastRelease ( Ord ) ; if ( Val -> getType ( ) -> getPrimitiveSizeInBits ( ) == 128 ) { Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxp : Intrinsic :: aarch64_stxp ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * Lo = Builder . CreateTrunc ( Val , Int64Ty , "lo" ) ; Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , 64 ) , Int64Ty , "hi" ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Stxr , { Lo , Hi , Addr } ) ; } Intrinsic :: ID Int = IsRelease ? Intrinsic :: aarch64_stlxr : Intrinsic :: aarch64_stxr ; Type * Tys [ ] = { Addr -> getType ( ) } ; Function * Stxr = Intrinsic :: getDeclaration ( M , Int , Tys ) ; return Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( 0 ) ) , Addr } ) ; } </s>

Perform a store-conditional operation to Addr .


<s> bool AMDGPUPropagateAttributesEarly :: runOnFunction ( Function & F ) { if ( ! TM || ! AMDGPU :: isEntryFunctionCC ( F . getCallingConv ( ) ) ) return false ; return AMDGPUPropagateAttributes ( TM , false ) . process ( F ) ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .

AMDGPU AMDGPU AMDGPU::isEntryFunctionCC AMDGPU


<s>
Register
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
else
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>

Return the register ID of the name passed in .


<s>
unsigned
TriCoreMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
MO
.
isExpr
(
)
&&
"unknown operand kind in printOperand"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
unsigned
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_TRICORE_LO_OFFSET
:
case
MCSymbolRefExpr
::
VK_TRICORE_HI_OFFSET
:
return
0
;
case
MCSymbolRefExpr
::
VK_TRICORE_LO
:
{
FixupKind
=
TriCore
::
fixup_leg_mov_lo16_pcrel
;
break
;
}
case
MCSymbolRefExpr
::
VK_TRICORE_HI
:
{
FixupKind
=
TriCore
::
fixup_leg_mov_hi16_pcrel
;
break
;
}
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> MachineInstr * WebAssemblyInstrInfo :: commuteInstructionImpl ( MachineInstr & MI , bool NewMI , unsigned OpIdx1 , unsigned OpIdx2 ) const { WebAssemblyFunctionInfo & MFI = * MI . getParent ( ) -> getParent ( ) -> getInfo < WebAssemblyFunctionInfo > ( ) ; if ( MFI . isVRegStackified ( MI . getOperand ( OpIdx1 ) . getReg ( ) ) || MFI . isVRegStackified ( MI . getOperand ( OpIdx2 ) . getReg ( ) ) ) return nullptr ; return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; } </s>

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction 's opcode and/or the immediate value operand .

WebAssembly WebAssembly WebAssembly WebAssembly


<s> void ARM64InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ; } </s>


<s>
Register
MipsTargetLowering
::
getRegisterByName
(
const
char
*
RegName
,
LLT
VT
,
const
MachineFunction
&
MF
)
const
{
if
(
Subtarget
.
isGP64bit
(
)
)
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP_64
)
.
Case
(
"sp"
,
Mips
::
SP_64
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
else
{
Register
Reg
=
StringSwitch
<
Register
>
(
RegName
)
.
Case
(
"$28"
,
Mips
::
GP
)
.
Case
(
"sp"
,
Mips
::
SP
)
.
Default
(
Register
(
)
)
;
if
(
Reg
)
return
Reg
;
}
report_fatal_error
(
"Invalid register name global variable"
)
;
}
</s>


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { TargetTransformInfo :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> static void nds32_init_libfuncs ( void ) { if ( TARGET_LINUX_ABI ) init_sync_libfuncs ( UNITS_PER_WORD ) ; } </s>


<s> void AArch64PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( ) ) ; if ( EnableSVEIntrinsicOpts && TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive ) addPass ( createSVEIntrinsicOptsPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; addPass ( createAArch64StackTaggingPass ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; } if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardCheckPass ( ) ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool MipsPassConfig :: addInstSelector ( ) { addPass ( createMipsModuleISelDagPass ( getMipsTargetMachine ( ) ) ) ; addPass ( createMips16ISelDag ( getMipsTargetMachine ( ) ) ) ; addPass ( createMipsSEISelDag ( getMipsTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> const char * HexagonTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( ( HexagonISD :: NodeType ) Opcode ) { case HexagonISD :: ADDC : return "HexagonISD::ADDC" ; case HexagonISD :: SUBC : return "HexagonISD::SUBC" ; case HexagonISD :: ALLOCA : return "HexagonISD::ALLOCA" ; case HexagonISD :: AT_GOT : return "HexagonISD::AT_GOT" ; case HexagonISD :: AT_PCREL : return "HexagonISD::AT_PCREL" ; case HexagonISD :: BARRIER : return "HexagonISD::BARRIER" ; case HexagonISD :: CALL : return "HexagonISD::CALL" ; case HexagonISD :: CALLnr : return "HexagonISD::CALLnr" ; case HexagonISD :: CALLR : return "HexagonISD::CALLR" ; case HexagonISD :: COMBINE : return "HexagonISD::COMBINE" ; case HexagonISD :: CONST32_GP : return "HexagonISD::CONST32_GP" ; case HexagonISD :: CONST32 : return "HexagonISD::CONST32" ; case HexagonISD :: CP : return "HexagonISD::CP" ; case HexagonISD :: DCFETCH : return "HexagonISD::DCFETCH" ; case HexagonISD :: EH_RETURN : return "HexagonISD::EH_RETURN" ; case HexagonISD :: TSTBIT : return "HexagonISD::TSTBIT" ; case HexagonISD :: EXTRACTU : return "HexagonISD::EXTRACTU" ; case HexagonISD :: INSERT : return "HexagonISD::INSERT" ; case HexagonISD :: JT : return "HexagonISD::JT" ; case HexagonISD :: RET_FLAG : return "HexagonISD::RET_FLAG" ; case HexagonISD :: TC_RETURN : return "HexagonISD::TC_RETURN" ; case HexagonISD :: VASL : return "HexagonISD::VASL" ; case HexagonISD :: VASR : return "HexagonISD::VASR" ; case HexagonISD :: VLSR : return "HexagonISD::VLSR" ; case HexagonISD :: VSPLAT : return "HexagonISD::VSPLAT" ; case HexagonISD :: VEXTRACTW : return "HexagonISD::VEXTRACTW" ; case HexagonISD :: VINSERTW0 : return "HexagonISD::VINSERTW0" ; case HexagonISD :: VROR : return "HexagonISD::VROR" ; case HexagonISD :: READCYCLE : return "HexagonISD::READCYCLE" ; case HexagonISD :: PTRUE : return "HexagonISD::PTRUE" ; case HexagonISD :: PFALSE : return "HexagonISD::PFALSE" ; case HexagonISD :: VZERO : return "HexagonISD::VZERO" ; case HexagonISD :: VSPLATW : return "HexagonISD::VSPLATW" ; case HexagonISD :: D2P : return "HexagonISD::D2P" ; case HexagonISD :: P2D : return "HexagonISD::P2D" ; case HexagonISD :: V2Q : return "HexagonISD::V2Q" ; case HexagonISD :: Q2V : return "HexagonISD::Q2V" ; case HexagonISD :: QCAT : return "HexagonISD::QCAT" ; case HexagonISD :: QTRUE : return "HexagonISD::QTRUE" ; case HexagonISD :: QFALSE : return "HexagonISD::QFALSE" ; case HexagonISD :: TYPECAST : return "HexagonISD::TYPECAST" ; case HexagonISD :: VALIGN : return "HexagonISD::VALIGN" ; case HexagonISD :: VALIGNADDR : return "HexagonISD::VALIGNADDR" ; case HexagonISD :: OP_END : break ; } return nullptr ; } </s>

getTargetNodeName - This method returns the name of a target specific

Hexagon Hexagon HexagonISD::NodeType HexagonISD::ADDC "HexagonISD::ADDC" HexagonISD::SUBC "HexagonISD::SUBC" HexagonISD::ALLOCA "HexagonISD::ALLOCA" HexagonISD::AT_GOT "HexagonISD::AT_GOT" HexagonISD::AT_PCREL "HexagonISD::AT_PCREL" HexagonISD::BARRIER "HexagonISD::BARRIER" HexagonISD::CALL "HexagonISD::CALL" HexagonISD::CALLnr "HexagonISD::CALLnr" HexagonISD::CALLR "HexagonISD::CALLR" HexagonISD::COMBINE "HexagonISD::COMBINE" HexagonISD::CONST32_GP "HexagonISD::CONST32_GP" HexagonISD::CONST32 "HexagonISD::CONST32" HexagonISD::CP "HexagonISD::CP" HexagonISD::DCFETCH "HexagonISD::DCFETCH" HexagonISD::EH_RETURN "HexagonISD::EH_RETURN" HexagonISD::TSTBIT "HexagonISD::TSTBIT" HexagonISD::EXTRACTU "HexagonISD::EXTRACTU" HexagonISD::INSERT "HexagonISD::INSERT" HexagonISD::JT "HexagonISD::JT" HexagonISD::RET_FLAG "HexagonISD::RET_FLAG" HexagonISD::TC_RETURN "HexagonISD::TC_RETURN" HexagonISD::VASL "HexagonISD::VASL" HexagonISD::VASR "HexagonISD::VASR" HexagonISD::VLSR "HexagonISD::VLSR" HexagonISD::VSPLAT "HexagonISD::VSPLAT" HexagonISD::VEXTRACTW "HexagonISD::VEXTRACTW" HexagonISD::VINSERTW0 "HexagonISD::VINSERTW0" HexagonISD::VROR "HexagonISD::VROR" HexagonISD::READCYCLE "HexagonISD::READCYCLE" HexagonISD::PTRUE "HexagonISD::PTRUE" HexagonISD::PFALSE "HexagonISD::PFALSE" HexagonISD::VZERO "HexagonISD::VZERO" HexagonISD::VSPLATW "HexagonISD::VSPLATW" HexagonISD::D2P "HexagonISD::D2P" HexagonISD::P2D "HexagonISD::P2D" HexagonISD::V2Q "HexagonISD::V2Q" HexagonISD::Q2V "HexagonISD::Q2V" HexagonISD::QCAT "HexagonISD::QCAT" HexagonISD::QTRUE "HexagonISD::QTRUE" HexagonISD::QFALSE "HexagonISD::QFALSE" HexagonISD::TYPECAST "HexagonISD::TYPECAST" HexagonISD::VALIGN "HexagonISD::VALIGN" HexagonISD::VALIGNADDR "HexagonISD::VALIGNADDR" HexagonISD::OP_END


<s> static rtx ia64_struct_value_rtx ( tree fntype , int incoming ATTRIBUTE_UNUSED ) { if ( TARGET_ABI_OPEN_VMS || ( fntype && ia64_struct_retval_addr_is_first_parm_p ( fntype ) ) ) return NULL_RTX ; return gen_rtx_REG ( Pmode , GR_REG ( 8 ) ) ; } </s>

Worker function for TARGET_STRUCT_VALUE_RTX .


<s> static void sparc_trampoline_init ( rtx m_tramp , tree fndecl , rtx cxt ) { rtx fnaddr = force_reg ( Pmode , XEXP ( DECL_RTL ( fndecl ) , 0 ) ) ; cxt = force_reg ( Pmode , cxt ) ; if ( TARGET_ARCH64 ) sparc64_initialize_trampoline ( m_tramp , fnaddr , cxt ) ; else sparc32_initialize_trampoline ( m_tramp , fnaddr , cxt ) ; } </s>


<s>
void
m32r_output_block_move
(
rtx
insn
ATTRIBUTE_UNUSED
,
rtx
operands
[
]
)
{
HOST_WIDE_INT
bytes
=
INTVAL
(
operands
[
2
]
)
;
int
first_time
;
int
got_extra
=
0
;
gcc_assert
(
bytes
>=
1
&&
bytes
<=
MAX_MOVE_BYTES
)
;
first_time
=
1
;
while
(
bytes
>
0
)
{
if
(
bytes
>=
8
)
{
if
(
first_time
)
{
output_asm_insn
(
"ld\t%5, %p1"
,
operands
)
;
output_asm_insn
(
"ld\t%6, %p1"
,
operands
)
;
output_asm_insn
(
"st\t%5, @%0"
,
operands
)
;
output_asm_insn
(
"st\t%6, %s0"
,
operands
)
;
}
else
{
output_asm_insn
(
"ld\t%5, %p1"
,
operands
)
;
output_asm_insn
(
"ld\t%6, %p1"
,
operands
)
;
output_asm_insn
(
"st\t%5, %s0"
,
operands
)
;
output_asm_insn
(
"st\t%6, %s0"
,
operands
)
;
}
bytes
-=
8
;
}
else
if
(
bytes
>=
4
)
{
if
(
bytes
>
4
)
got_extra
=
1
;
output_asm_insn
(
"ld\t%5, %p1"
,
operands
)
;
if
(
got_extra
)
output_asm_insn
(
"ld\t%6, %p1"
,
operands
)
;
if
(
first_time
)
output_asm_insn
(
"st\t%5, @%0"
,
operands
)
;
else
output_asm_insn
(
"st\t%5, %s0"
,
operands
)
;
bytes
-=
4
;
}
else
{
int
dst_offset
=
first_time
0
:
4
;
int
dst_inc_amount
=
dst_offset
+
bytes
4
;
int
src_inc_amount
=
bytes
;
int
last_shift
;
rtx
my_operands
[
3
]
;
if
(
!
got_extra
)
output_asm_insn
(
"ld\t%6, @%1"
,
operands
)
;
if
(
bytes
>=
2
)
{
bytes
-=
2
;
output_asm_insn
(
"sra3\t%5, %6, #16"
,
operands
)
;
my_operands
[
0
]
=
operands
[
5
]
;
my_operands
[
1
]
=
GEN_INT
(
dst_offset
)
;
my_operands
[
2
]
=
operands
[
0
]
;
output_asm_insn
(
"sth\t%0, @(%1,%2)"
,
my_operands
)
;
if
(
bytes
>
0
)
{
dst_offset
+=
2
;
last_shift
=
8
;
}
}
else
last_shift
=
24
;
if
(
bytes
>
0
)
{
my_operands
[
0
]
=
operands
[
6
]
;
my_operands
[
1
]
=
GEN_INT
(
last_shift
)
;
output_asm_insn
(
"srai\t%0, #%1"
,
my_operands
)
;
my_operands
[
0
]
=
operands
[
6
]
;
my_operands
[
1
]
=
GEN_INT
(
dst_offset
)
;
my_operands
[
2
]
=
operands
[
0
]
;
output_asm_insn
(
"stb\t%0, @(%1,%2)"
,
my_operands
)
;
}
if
(
dst_inc_amount
&&
!
find_reg_note
(
insn
,
REG_UNUSED
,
operands
[
0
]
)
)
{
my_operands
[
0
]
=
operands
[
0
]
;
my_operands
[
1
]
=
GEN_INT
(
dst_inc_amount
)
;
output_asm_insn
(
"addi\t%0, #%1"
,
my_operands
)
;
}
if
(
src_inc_amount
&&
!
find_reg_note
(
insn
,
REG_UNUSED
,
operands
[
1
]
)
)
{
my_operands
[
0
]
=
operands
[
1
]
;
my_operands
[
1
]
=
GEN_INT
(
src_inc_amount
)
;
output_asm_insn
(
"addi\t%0, #%1"
,
my_operands
)
;
}
bytes
=
0
;
}
first_time
=
0
;
}
}
</s>

Emit load/stores for a small constant word aligned block_move . operands [ 0 ] is the memory address of the destination . operands [ 1 ] is the memory address of the source . operands [ 2 ] is the number of bytes to move . operands [ 3 ] is a temp register . operands [ 4 ] is a temp register .


<s> static enum flt_eval_method ix86_excess_precision ( enum excess_precision_type type ) { switch ( type ) { case EXCESS_PRECISION_TYPE_FAST : return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; case EXCESS_PRECISION_TYPE_STANDARD : case EXCESS_PRECISION_TYPE_IMPLICIT : if ( ! TARGET_80387 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! TARGET_SSE_MATH ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; } return ( type == EXCESS_PRECISION_TYPE_STANDARD ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT : FLT_EVAL_METHOD_UNPREDICTABLE ) ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ; } </s>

Set the value of FLT_EVAL_METHOD in float.h . When using only the FPU , assume that the fpcw is set to extended precision ; when using only SSE , rounding is correct ; when using both SSE and the FPU , the rounding precision is indeterminate , since either may be chosen apparently at random .


<s> static void alpha_pad_function_end ( void ) { rtx_insn * insn , * next ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! CALL_P ( insn ) || ! ( SIBLING_CALL_P ( insn ) || find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) ) continue ; next = next_active_insn ( insn ) ; if ( next ) { rtx pat = PATTERN ( next ) ; if ( GET_CODE ( pat ) == SET && GET_CODE ( SET_SRC ( pat ) ) == UNSPEC_VOLATILE && XINT ( SET_SRC ( pat ) , 1 ) == UNSPECV_LDGP1 ) emit_insn_after ( gen_unop ( ) , insn ) ; } } } </s>

Insert an unop between sibcall or noreturn function call and GP load .


<s> EVT PPCTargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( this -> PPCSubTarget . isPPC64 ( ) ) { return MVT :: i64 ; } else { return MVT :: i32 ; } } </s>

It returns EVT : :Other if the type should be determined using generic target-independent logic .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
Kind
==
KindTy
::
Register
&&
"Invalid type access!"
)
;
return
Reg
.
RegNum
.
id
(
)
;
}
</s>

Returns the register associated with this edge .


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved ( "stack-protector" ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>


<s> unsigned getElementSize ( ) const { return CurType . ElementSize ; } </s>

Return the size of an element read or written by Inst .


<s> bool isTarget64BitLP64 ( ) const { return Is64Bit && ( ! TargetTriple . isX32 ( ) && ! TargetTriple . isOSNaCl ( ) ) ; } </s>

Is this x86_64 with the LP64 programming model ( standard AMD64 , no x32 ) ?


<s> bool MSP430TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createMSP430ISelDag ( * this , OptLevel ) ) ; return false ; } </s>


<s> static reg_class_t ix86_preferred_output_reload_class ( rtx x , reg_class_t regclass ) { machine_mode mode = GET_MODE ( x ) ; if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) return MAYBE_SSE_CLASS_P ( regclass ) ? ALL_SSE_REGS : NO_REGS ; if ( IS_STACK_MODE ( mode ) ) return FLOAT_CLASS_P ( regclass ) ? regclass : NO_REGS ; return regclass ; } </s>

Discourage putting floating-point values in SSE registers unless SSE math is being used , and likewise for the 387 registers .


<s> rtx ia64_expand_compare ( enum rtx_code code , enum machine_mode mode ) { rtx op0 = ia64_compare_op0 , op1 = ia64_compare_op1 ; rtx cmp ; if ( GET_MODE ( op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && op1 == const0_rtx ) ; cmp = op0 ; } else if ( GET_MODE ( op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = 1 , QCMP_UNORD = 2 , QCMP_EQ = 4 , QCMP_LT = 8 , QCMP_GT = 16 } magic ; enum rtx_code ncode ; rtx ret , insns ; gcc_assert ( cmptf_libfunc && GET_MODE ( op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , 0 , LCT_CONST , DImode , 3 , op0 , TFmode , op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , op0 , op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , cmp , gen_rtx_fmt_ee ( code , BImode , op0 , op1 ) ) ) ; code = NE ; } return gen_rtx_fmt_ee ( code , mode , cmp , const0_rtx ) ; } </s>

Emit comparison instruction if necessary , returning the expression that holds the compare result in the proper mode .


"TOC pointer used in a function using PC-Relative addressing!"

runOnMachineFunction - Emit the function body .


"Slot for FPW register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


"X86-64 PIC uses RIP relative addressing"

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool PPCPassConfig :: addInstSelector ( ) { PM . add ( createPPCISelDag ( getPPCTargetMachine ( ) ) ) ; return false ; } </s>


<s> bool AMDGPUCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < unsigned > VRegs ) const { return true ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by VRegs , for GlobalISel .


<s>
unsigned
TriCoreMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
switch
(
MO
.
getReg
(
)
)
{
default
:
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
case
TriCore
::
E0
:
return
0
;
case
TriCore
::
E2
:
return
2
;
case
TriCore
::
E4
:
return
4
;
case
TriCore
::
E6
:
return
6
;
case
TriCore
::
E8
:
return
8
;
case
TriCore
::
E10
:
return
10
;
case
TriCore
::
E12
:
return
12
;
case
TriCore
::
E14
:
return
14
;
}
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
MO
.
isExpr
(
)
&&
"unknown operand kind in printOperand"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
printVariantKind
(
outs
(
)
)
;
unsigned
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_TRICORE_LO_OFFSET
:
case
MCSymbolRefExpr
::
VK_TRICORE_HI_OFFSET
:
return
0
;
case
MCSymbolRefExpr
::
VK_TRICORE_LO
:
{
FixupKind
=
TriCore
::
fixup_leg_mov_lo16_pcrel
;
break
;
}
case
MCSymbolRefExpr
::
VK_TRICORE_HI
:
{
FixupKind
=
TriCore
::
fixup_leg_mov_hi16_pcrel
;
break
;
}
}
Fixups
.
push_back
(
MCFixup
::
create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void alpha_split_compare_and_swap ( rtx operands [ ] ) { rtx cond , retval , mem , oldval , newval ; bool is_weak ; enum memmodel mod_s , mod_f ; machine_mode mode ; rtx label1 , label2 , x ; cond = operands [ 0 ] ; retval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = ( operands [ 5 ] != const0_rtx ) ; mod_s = memmodel_from_int ( INTVAL ( operands [ 6 ] ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ 7 ] ) ) ; mode = GET_MODE ( mem ) ; alpha_pre_atomic_barrier ( mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , 0 ) ) ; } label2 = gen_rtx_LABEL_REF ( DImode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = gen_lowpart ( DImode , retval ) ; if ( oldval == const0_rtx ) { emit_move_insn ( cond , const0_rtx ) ; x = gen_rtx_NE ( DImode , x , const0_rtx ) ; } else { x = gen_rtx_EQ ( DImode , x , oldval ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; } emit_unlikely_jump ( x , label2 ) ; emit_move_insn ( cond , newval ) ; emit_store_conditional ( mode , cond , mem , gen_lowpart ( mode , cond ) ) ; if ( ! is_weak ) { x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label1 ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( XEXP ( label2 , 0 ) ) ; alpha_post_atomic_barrier ( mod_s ) ; if ( is_mm_relaxed ( mod_f ) ) emit_label ( XEXP ( label2 , 0 ) ) ; } </s>


<s> static bool vsetvl_discard_result_insn_p ( rtx_insn * rinsn ) { if ( ! vector_config_insn_p ( rinsn ) ) return false ; return ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_discard_resultdi || INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_discard_resultsi ) ; } </s>

Return true if it is vsetvl zero , rs1 .


<s> const SystemZTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> void M88kInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; MachineMemOperand * MMO = getMachineMemOperand ( MBB , FrameIndex , MachineMemOperand :: MOStore ) ; BuildMI ( MBB , MBBI , DL , get ( M88k :: STriw ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Store the specified register of the given register class to the specified stack frame index .


<s> const M68kRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode , SLOT_TEMP ) ; rtx quot = emit_library_call_value ( libfunc , NULL_RTX , LCT_NORMAL , mode , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) , XEXP ( rem , 0 ) , Pmode ) ; * quot_p = quot ; * rem_p = rem ; } </s>


"function versions cannot be marked as %<gnu_inline%>,"

"virtual function multiversioning not supported"

This function changes the assembler name for functions that are versions . If DECL is a function version and has a `` target '' attribute , it appends the attribute string to its assembler name .


<s> static rtx avr_mem_clobber ( void ) { rtx mem = gen_rtx_MEM ( BLKmode , gen_rtx_SCRATCH ( Pmode ) ) ; MEM_VOLATILE_P ( mem ) = 1 ; return mem ; } </s>


<s> bool HexagonDAGToDAGISel :: hasOneUse ( const SDNode * N ) const { return ! CheckSingleUse || N -> hasOneUse ( ) ; } </s>

Return true if there is exactly one node using value ResNo of Node .


Update incoming stack boundary and estimated stack alignment .


<s> static int mn10300_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t iclass , bool in ATTRIBUTE_UNUSED ) { enum reg_class rclass = ( enum reg_class ) iclass ; if ( rclass == FP_REGS ) return 8 ; return 6 ; } </s>

Implement the TARGET_MEMORY_MOVE_COST hook . Given lack of the form of the address , this must be speed-relative , though we should never be less expensive than a size-relative register move cost above . This is not a problem .


<s> StringRef MetadataStreamerV3 :: getValueType ( Type * Ty , StringRef TypeName ) const { switch ( Ty -> getTypeID ( ) ) { case Type :: IntegerTyID : { auto Signed = ! TypeName . startswith ( "u" ) ; switch ( Ty -> getIntegerBitWidth ( ) ) { case 8 : return Signed ? "i8" : "u8" ; case 16 : return Signed ? "i16" : "u16" ; case 32 : return Signed ? "i32" : "u32" ; case 64 : return Signed ? "i64" : "u64" ; default : return "struct" ; } } case Type :: HalfTyID : return "f16" ; case Type :: FloatTyID : return "f32" ; case Type :: DoubleTyID : return "f64" ; case Type :: PointerTyID : return getValueType ( Ty -> getPointerElementType ( ) , TypeName ) ; case Type :: VectorTyID : return getValueType ( Ty -> getVectorElementType ( ) , TypeName ) ; default : return "struct" ; } } </s>

Return the ValueType of the referenced return value .


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } </s>

Check whether the given instruction may need relaxation .


<s> static bool mips_find_gp_ref ( bool * cache , bool ( * pred ) ( rtx_insn * ) ) { rtx_insn * insn , * subinsn ; if ( ! * cache ) { push_topmost_sequence ( ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) if ( USEFUL_INSN_P ( subinsn ) && pred ( subinsn ) ) { * cache = true ; break ; } pop_topmost_sequence ( ) ; } return * cache ; } </s>

Return true if predicate PRED is true for at least one instruction . Cache the result in * CACHE , and assume that the result is true if * CACHE is already true .


<s> DFAPacketizer * R600InstrInfo :: CreateTargetScheduleState ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { const InstrItineraryData * II = TM -> getSubtargetImpl ( ) -> getInstrItineraryData ( ) ; return TM -> getSubtarget < AMDGPUSubtarget > ( ) . createDFAPacketizer ( II ) ; } </s>

Create machine specific model for scheduling .


<s> static void pa_file_end ( void ) { unsigned int i ; extern_symbol * p ; if ( ! NO_DEFERRED_PROFILE_COUNTERS ) output_deferred_profile_counters ( ) ; output_deferred_plabels ( ) ; for ( i = 0 ; vec_safe_iterate ( extern_symbols , i , & p ) ; i ++ ) { tree decl = p -> decl ; if ( ! TREE_ASM_WRITTEN ( decl ) && SYMBOL_REF_REFERENCED_P ( XEXP ( DECL_RTL ( decl ) , 0 ) ) ) ASM_OUTPUT_EXTERNAL_REAL ( asm_out_file , decl , p -> name ) ; } vec_free ( extern_symbols ) ; if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack ( ) ; } </s>

Output text required at the end of an assembler file . This includes deferred plabels and .import directives for all external symbols that were actually referenced .


<s> static bool arm_cxx_cdtor_returns_this ( void ) { return TARGET_AAPCS_BASED ; } </s>

The EABI says constructors and destructors should return a pointer to the object constructed/destroyed .


<s> rtx cris_gen_movem_load ( rtx src , rtx nregs_rtx , int nprefix ) { int nregs = INTVAL ( nregs_rtx ) ; rtvec vec ; int eltno = 1 ; int i ; rtx srcreg = XEXP ( src , 0 ) ; unsigned int regno = nregs - 1 ; int regno_inc = - 1 ; if ( TARGET_V32 ) { regno = 0 ; regno_inc = 1 ; } if ( GET_CODE ( srcreg ) == POST_INC ) srcreg = XEXP ( srcreg , 0 ) ; CRIS_ASSERT ( REG_P ( srcreg ) ) ; if ( nregs == 1 ) return gen_movsi ( gen_rtx_REG ( SImode , 0 ) , src ) ; vec = rtvec_alloc ( nprefix + nregs + ( GET_CODE ( XEXP ( src , 0 ) ) == POST_INC ) ) ; if ( GET_CODE ( XEXP ( src , 0 ) ) == POST_INC ) { RTVEC_ELT ( vec , nprefix + 1 ) = gen_rtx_SET ( VOIDmode , srcreg , plus_constant ( Pmode , srcreg , nregs * 4 ) ) ; eltno ++ ; } src = replace_equiv_address ( src , srcreg ) ; RTVEC_ELT ( vec , nprefix ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , regno ) , src ) ; regno += regno_inc ; for ( i = 1 ; i < nregs ; i ++ , eltno ++ ) { RTVEC_ELT ( vec , nprefix + eltno ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , regno ) , adjust_address_nv ( src , SImode , i * 4 ) ) ; regno += regno_inc ; } return gen_rtx_PARALLEL ( VOIDmode , vec ) ; } </s>

Worker function for generating movem from mem for load_multiple .


<s> bool X86InstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF ) const { return MF . getFunction ( ) -> hasFnAttribute ( Attribute :: NoRedZone ) ; } </s>

Return true if the function can safely be outlined from .


<s>
void
SystemZPostRASchedStrategy
::
schedNode
(
SUnit
*
SU
,
bool
IsTopNode
)
{
DEBUG
(
dbgs
(
)
<<
"+++ Scheduling SU("
<<
SU
->
NodeNum
<<
")\n"
;
)
;
Available
.
erase
(
SU
)
;
HazardRec
.
EmitInstruction
(
SU
)
;
}
</s>

ScheduleDAGMI has scheduled an instruction - tell HazardRec about it .

SystemZ
SystemZ
"+++ Scheduling SU("
")\n"


<s> unsigned ARMBaseInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; const MCInstrDesc & MCID = MI . getDesc ( ) ; if ( MCID . getSize ( ) ) return MCID . getSize ( ) ; if ( MI . getOpcode ( ) == ARM :: INLINEASM ) { unsigned Size = getInlineAsmLength ( MI . getOperand ( 0 ) . getSymbolName ( ) , * MAI ) ; if ( ! MF -> getInfo < ARMFunctionInfo > ( ) -> isThumbFunction ( ) ) Size = alignTo ( Size , 4 ) ; return Size ; } unsigned Opc = MI . getOpcode ( ) ; switch ( Opc ) { default : return 0 ; case TargetOpcode :: BUNDLE : return getInstBundleLength ( MI ) ; case ARM :: MOVi16_ga_pcrel : case ARM :: MOVTi16_ga_pcrel : case ARM :: t2MOVi16_ga_pcrel : case ARM :: t2MOVTi16_ga_pcrel : return 4 ; case ARM :: MOVi32imm : case ARM :: t2MOVi32imm : return 8 ; case ARM :: CONSTPOOL_ENTRY : case ARM :: JUMPTABLE_INSTS : case ARM :: JUMPTABLE_ADDRS : case ARM :: JUMPTABLE_TBB : case ARM :: JUMPTABLE_TBH : return MI . getOperand ( 2 ) . getImm ( ) ; case ARM :: Int_eh_sjlj_longjmp : return 16 ; case ARM :: tInt_eh_sjlj_longjmp : return 10 ; case ARM :: tInt_WIN_eh_sjlj_longjmp : return 12 ; case ARM :: Int_eh_sjlj_setjmp : case ARM :: Int_eh_sjlj_setjmp_nofp : return 20 ; case ARM :: tInt_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp : case ARM :: t2Int_eh_sjlj_setjmp_nofp : return 12 ; case ARM :: SPACE : return MI . getOperand ( 1 ) . getImm ( ) ; } } </s>

Returns the size in bytes of the specified MachineInstr , or ~0U when this function is not implemented by a target .


<s>
const
char
*
getPassName
(
)
const
{
return
"R600 Handle indirect addressing"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool LoongArchPassConfig :: addInstSelector ( ) { addPass ( createLoongArchISelDag ( getLoongArchTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> const uint16_t * LanaiRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * ) const { return CSR_SaveList ; } </s>


<s> bool SIMachineFunctionInfo :: allocateVGPRSpillToAGPR ( MachineFunction & MF , int FI , bool isAGPRtoVGPR ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; assert ( ST . hasMAIInsts ( ) && FrameInfo . isSpillSlotObjectIndex ( FI ) ) ; auto & Spill = VGPRToAGPRSpills [ FI ] ; if ( ! Spill . Lanes . empty ( ) ) return Spill . FullyAllocated ; unsigned Size = FrameInfo . getObjectSize ( FI ) ; unsigned NumLanes = Size / 4 ; Spill . Lanes . resize ( NumLanes , AMDGPU :: NoRegister ) ; const TargetRegisterClass & RC = isAGPRtoVGPR ? AMDGPU :: VGPR_32RegClass : AMDGPU :: AGPR_32RegClass ; auto Regs = RC . getRegisters ( ) ; auto & SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR ; const SIRegisterInfo * TRI = ST . getRegisterInfo ( ) ; Spill . FullyAllocated = true ; BitVector OtherUsedRegs ; OtherUsedRegs . resize ( TRI -> getNumRegs ( ) ) ; const uint32_t * CSRMask = TRI -> getCallPreservedMask ( MF , MF . getFunction ( ) . getCallingConv ( ) ) ; if ( CSRMask ) OtherUsedRegs . setBitsInMask ( CSRMask ) ; for ( MCPhysReg Reg : SpillAGPR ) OtherUsedRegs . set ( Reg ) ; for ( MCPhysReg Reg : SpillVGPR ) OtherUsedRegs . set ( Reg ) ; SmallVectorImpl < MCPhysReg > :: const_iterator NextSpillReg = Regs . begin ( ) ; for ( unsigned I = 0 ; I < NumLanes ; ++ I ) { NextSpillReg = std :: find_if ( NextSpillReg , Regs . end ( ) , [ & MRI , & OtherUsedRegs ] ( MCPhysReg Reg ) { return MRI . isAllocatable ( Reg ) && ! MRI . isPhysRegUsed ( Reg ) && ! OtherUsedRegs [ Reg ] ; } ) ; if ( NextSpillReg == Regs . end ( ) ) { Spill . FullyAllocated = false ; break ; } OtherUsedRegs . set ( * NextSpillReg ) ; SpillRegs . push_back ( * NextSpillReg ) ; Spill . Lanes [ I ] = * NextSpillReg ++ ; } return Spill . FullyAllocated ; } </s>

Reserve AGPRs or VGPRs to support spilling for FrameIndex FI .


<s> EVT X86TargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return MVT :: i8 ; return VT . changeVectorElementTypeToInteger ( ) ; } </s>

Return the value type to use for ISD : :SETCC .


<s> bool RISCVRemoveRedundancyVSETVL :: runOnMachineFunction ( MachineFunction & MF ) { collectRedundancyVSETVLIInMF ( MF ) ; return removeRedundancy ( ) ; } </s>

runOnMachineFunction - Emit the function body .


<s>
raw_ostream
&
printName
(
raw_ostream
&
OS
,
StringRef
Name
)
{
return
OS
<<
Name
<<
" = "
;
}
</s>


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override { return true ; } </s>

Returns true if the live-ins should be tracked after register allocation .


<s> bool ARMBaseRegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( "no-realign-stack" ) ) return false ; if ( AFI -> isThumb1OnlyFunction ( ) ) return false ; if ( ! MRI -> canReserveReg ( getFramePointerReg ( MF . getSubtarget < ARMSubtarget > ( ) ) ) ) return false ; if ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) ) return true ; return MRI -> canReserveReg ( BasePtr ) ; } </s>

True if the stack can be realigned for the target .


<s> void WebAssemblyTargetWasmStreamer :: emitLocal ( ArrayRef < MVT > Types ) { SmallVector < std :: pair < MVT , uint32_t > , 4 > Grouped ; for ( MVT Type : Types ) { if ( Grouped . empty ( ) || Grouped . back ( ) . first != Type ) Grouped . push_back ( std :: make_pair ( Type , 1 ) ) ; else ++ Grouped . back ( ) . second ; } Streamer . EmitULEB128IntValue ( Grouped . size ( ) ) ; for ( auto Pair : Grouped ) { Streamer . EmitULEB128IntValue ( Pair . second ) ; Streamer . EmitULEB128IntValue ( uint64_t ( WebAssembly :: toValType ( Pair . first ) ) ) ; } } </s>


<s> static void nios2_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; HOST_WIDE_INT param_size ; if ( mode == BLKmode ) { param_size = int_size_in_bytes ( type ) ; gcc_assert ( param_size >= 0 ) ; } else param_size = GET_MODE_SIZE ( mode ) ; param_size = ( UNITS_PER_WORD - 1 + param_size ) / UNITS_PER_WORD ; if ( cum -> regs_used + param_size > NUM_ARG_REGS ) cum -> regs_used = NUM_ARG_REGS ; else cum -> regs_used += param_size ; } </s>

Update the data in CUM to advance over an argument of mode MODE and data type TYPE ; TYPE is null for libcalls where that information may not be available .


<s> void ARMPassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createMLxExpansionPass ( ) ) ; if ( EnableARMLoadStoreOpt ) addPass ( createARMLoadStoreOptimizationPass ( true ) ) ; if ( ! DisableA15SDOptimization ) addPass ( createA15SDOptimizerPass ( ) ) ; } } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s> bool mprocTargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ; return ( VT1 . getSizeInBits ( ) > VT2 . getSizeInBits ( ) ) ; } </s>

Return true if it 's free to truncate a value of type Ty1 to type Ty2 .


<s>
static
void
avr_move_bits
(
rtx
*
xop
,
unsigned
int
map
,
bool
fixp_p
,
int
*
plen
)
{
int
bit_dest
,
b
;
int
t_bit_src
=
1
;
for
(
b
=
0
;
b
<
8
;
b
++
)
for
(
bit_dest
=
0
;
bit_dest
<
8
;
bit_dest
++
)
{
int
bit_src
=
avr_map
(
map
,
bit_dest
)
;
if
(
b
!=
bit_src
||
bit_src
>=
8
||
(
bit_dest
==
bit_src
&&
!
fixp_p
)
)
continue
;
if
(
t_bit_src
!=
bit_src
)
{
t_bit_src
=
bit_src
;
xop
[
3
]
=
GEN_INT
(
bit_src
)
;
avr_asm_len
(
"bst %T1%T3"
,
xop
,
plen
,
1
)
;
}
xop
[
3
]
=
GEN_INT
(
bit_dest
)
;
avr_asm_len
(
"bld %T0%T3"
,
xop
,
plen
,
1
)
;
}
}
</s>

Insert bits from XOP [ 1 ] into XOP [ 0 ] according to MAP . XOP [ 0 ] and XOP [ 1 ] do n't overlap . If FIXP_P = true : Move all bits according to MAP using BLD/BST sequences . If FIXP_P = false : Just move the bit if its position in the destination is different to its source position .


<s> TargetPassConfig * TL45TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TL45PassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> void GCNMaxOccupancySchedStrategy :: initialize ( ScheduleDAGMI * DAG ) { GenericScheduler :: initialize ( DAG ) ; const SIRegisterInfo * SRI = static_cast < const SIRegisterInfo * > ( TRI ) ; MF = & DAG -> MF ; const SISubtarget & ST = MF -> getSubtarget < SISubtarget > ( ) ; const int ErrorMargin = 3 ; SGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & AMDGPU :: SGPR_32RegClass ) - ErrorMargin ; VGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & AMDGPU :: VGPR_32RegClass ) - ErrorMargin ; if ( TargetOccupancy ) { SGPRCriticalLimit = ST . getMaxNumSGPRs ( TargetOccupancy , true ) ; VGPRCriticalLimit = ST . getMaxNumVGPRs ( TargetOccupancy ) ; } else { SGPRCriticalLimit = SRI -> getRegPressureSetLimit ( DAG -> MF , SRI -> getSGPRPressureSet ( ) ) ; VGPRCriticalLimit = SRI -> getRegPressureSetLimit ( DAG -> MF , SRI -> getVGPRPressureSet ( ) ) ; } SGPRCriticalLimit -= ErrorMargin ; VGPRCriticalLimit -= ErrorMargin ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> void ix86_fixup_binary_operands_no_copy ( enum rtx_code code , machine_mode mode , rtx operands [ ] ) { rtx dst = ix86_fixup_binary_operands ( code , mode , operands ) ; gcc_assert ( dst == operands [ 0 ] ) ; } </s>

Similarly , but assume that the destination has already been set up properly .


"********** Fixing Irreducible Control Flow **********\n"


<s> const char * loongarch_output_conditional_branch ( rtx_insn * insn , rtx * operands , const char * branch_if_true , const char * branch_if_false ) { unsigned int length ; rtx taken ; gcc_assert ( LABEL_P ( operands [ 0 ] ) ) ; length = get_attr_length ( insn ) ; if ( length <= 4 ) { return branch_if_true ; } rtx_code_label * not_taken = gen_label_rtx ( ) ; taken = operands [ 0 ] ; operands [ 0 ] = not_taken ; output_asm_insn ( branch_if_false , operands ) ; output_asm_insn ( "b\t%0" , & taken ) ; targetm . asm_out . internal_label ( asm_out_file , "L" , CODE_LABEL_NUMBER ( not_taken ) ) ; return "" ; } </s>

Return the assembly code for INSN , which has the operands given by OPERANDS , and which branches to OPERANDS [ 0 ] if some condition is true . BRANCH_IF_TRUE is the asm template that should be used if OPERANDS [ 0 ] is in range of a direct branch . BRANCH_IF_FALSE is an inverted version of BRANCH_IF_TRUE .


<s> bool X86PassConfig :: addInstSelector ( ) { addPass ( createX86ISelDag ( getX86TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( getX86Subtarget ( ) . isTargetELF ( ) && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createCleanupLocalDynamicTLSPass ( ) ) ; if ( ! getX86Subtarget ( ) . is64Bit ( ) ) addPass ( createGlobalBaseRegPass ( ) ) ; return false ; } </s>


<s> const ARM64MCExpr * ARM64MCExpr :: Create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) ARM64MCExpr ( Expr , Kind ) ; } </s>

Construct a unary instruction , given the opcode and an operand .


<s> static bool ix86_can_eliminate ( const int from , const int to ) { if ( stack_realign_fp ) return ( ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) || ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) ) ; else return to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true ; } </s>

Given FROM and TO register numbers , say whether this elimination is allowed . If stack alignment is needed , we can only replace argument pointer with hard frame pointer , or replace frame pointer with stack pointer . Otherwise , frame pointer elimination is automatically handled and all other eliminations are valid .


<s> static rtx ix86_expand_unop1_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat ; tree arg0 = TREE_VALUE ( arglist ) ; rtx op1 , op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , 0 ) ; enum machine_mode tmode = insn_data [ icode ] . operand [ 0 ] . mode ; enum machine_mode mode0 = insn_data [ icode ] . operand [ 1 ] . mode ; if ( optimize || ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ 0 ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( VECTOR_MODE_P ( mode0 ) ) op0 = safe_vector_operand ( op0 , mode0 ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! ( * insn_data [ icode ] . operand [ 1 ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; op1 = op0 ; if ( ! ( * insn_data [ icode ] . operand [ 2 ] . predicate ) ( op1 , mode0 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; if ( ! pat ) return 0 ; emit_insn ( pat ) ; return target ; } </s>

Subroutine of ix86_expand_builtin to take care of three special unop insns : sqrtss , rsqrtss , rcpss .


<s> static void arc_post_atomic_barrier ( enum memmodel model ) { if ( need_atomic_barrier_p ( model , false ) ) emit_insn ( gen_memory_barrier ( ) ) ; } </s>

Emit a ( post ) memory barrier around an atomic sequence according to MODEL .


<s> unsigned getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return SP :: I1 ; } </s>

If a physical register , this returns the register that receives the exception typeid on entry to a landing pad .


<s> bool AMDGPUInstrInfo :: unfoldMemoryOperand ( SelectionDAG & DAG , SDNode * N , SmallVectorImpl < SDNode * > & NewNodes ) const { return false ; } </s>

unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction .


<s> static reg_class_t loongarch_canonicalize_move_class ( reg_class_t rclass ) { if ( reg_class_subset_p ( rclass , GENERAL_REGS ) ) rclass = GENERAL_REGS ; return rclass ; } </s>

RCLASS is a class involved in a REGISTER_MOVE_COST calculation . Return a `` canonical '' class to represent it in later calculations .


<s> void TriCoreInstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s>
int
BlackfinRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
llvm_unreachable
(
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .

Blackfin
"What is the dwarf register number"
1


<s>
bool
fixupNeedsRelaxation
(
const
MCFixup
&
Fixup
,
uint64_t
Value
,
const
MCRelaxableFragment
*
DF
,
const
MCAsmLayout
&
Layout
)
const
override
{
llvm_unreachable
(
"RelaxInstruction() unimplemented"
)
;
return
false
;
}
</s>

Simple predicate for targets where ! Resolved implies requiring relaxation .


<s> void PPCFrameInfo :: determineFrameLayout ( MachineFunction & MF ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI -> getStackSize ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; unsigned TargetAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - 1 ; bool DisableRedZone = MF . getFunction ( ) -> hasFnAttr ( Attribute :: NoRedZone ) ; if ( ! DisableRedZone && FrameSize <= 224 && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( 0 ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . isPPC64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; MFI -> setStackSize ( FrameSize ) ; } </s>

Determine the frame layout but do not update the machine function .


<s> unsigned Z80RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return getFrameLowering ( MF ) -> hasFP ( MF ) ? Z80 :: IX : Z80 :: SPS ; } </s>


<s> bool CSKYInstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { if ( Opt == "no-aliases" ) { NoAliases = true ; return true ; } if ( Opt == "numeric" ) { ArchRegNames = true ; return true ; } if ( Opt == "debug" ) { DebugFlag = true ; return true ; } if ( Opt == "abi-names" ) { ABIRegNames = true ; return true ; } return false ; } </s>

Customize the printer according to a command line option .

CSKY CSKY "no-aliases" "numeric" "debug" "abi-names"


"ARM hazards don't support scoreboard lookahead"

getHazardType - Return the hazard type of emitting this node .


<s> const uint32_t * PPCRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const PPCSubtarget & Subtarget = MF . getSubtarget < PPCSubtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_RegMask ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_RegMask ; return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isDarwinABI ( ) ) return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_RegMask : CSR_Darwin64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_RegMask : CSR_Darwin32_RegMask ) ; return TM . isPPC64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR464_Altivec_RegMask : CSR_SVR464_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : CSR_SVR432_RegMask ) ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static bool mips_expand_vselect_vconcat ( rtx target , rtx op0 , rtx op1 , const unsigned char * perm , unsigned nelt ) { machine_mode v2mode ; rtx x ; if ( ! GET_MODE_2XWIDER_MODE ( GET_MODE ( op0 ) ) . exists ( & v2mode ) ) return false ; x = gen_rtx_VEC_CONCAT ( v2mode , op0 , op1 ) ; return mips_expand_vselect ( target , x , perm , nelt ) ; } </s>

Similar , but generate a vec_concat from op0 and op1 as well .


<s> MachineBasicBlock * MandarinTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MDCC :: CondCodes CC = ( MDCC :: CondCodes ) MI -> getOperand ( 3 ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII . get ( MD :: JCCi ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( MD :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent ( ) ; return BB ; } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"Small-data allocation is disabled, but symbols "

"may have explicit section assignments...\n"

"Checking if value is in small-data, -G"

"no, small-data allocation is disabled\n"

Return true if this global address should be placed into small data/bss section .


"Can only put epilog before 'retl' or 'tail_call' instruction!"


"-misched-topdown incompatible with -misched-bottomup"

Initialize the strategy after building the DAG for a new region .


<s> static bool arc_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return ( arc_hard_regno_modes [ regno ] & arc_mode_class [ mode ] ) != 0 ; } </s>


<s> int xtensa_emit_move_sequence ( rtx * operands , machine_mode mode ) { rtx src = operands [ 1 ] ; if ( CONSTANT_P ( src ) && ( GET_CODE ( src ) != CONST_INT || ! xtensa_simm12b ( INTVAL ( src ) ) ) ) { rtx dst = operands [ 0 ] ; if ( xtensa_tls_referenced_p ( src ) ) { rtx addend = NULL ; if ( GET_CODE ( src ) == CONST && GET_CODE ( XEXP ( src , 0 ) ) == PLUS ) { addend = XEXP ( XEXP ( src , 0 ) , 1 ) ; src = XEXP ( XEXP ( src , 0 ) , 0 ) ; } src = xtensa_legitimize_tls_address ( src ) ; if ( addend ) { src = gen_rtx_PLUS ( mode , src , addend ) ; src = force_operand ( src , dst ) ; } emit_move_insn ( dst , src ) ; return 1 ; } if ( ! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16 && ! ( CONST_INT_P ( src ) && can_create_pseudo_p ( ) ) ) { src = force_const_mem ( SImode , src ) ; operands [ 1 ] = src ; } if ( mode != SImode ) { if ( register_operand ( dst , mode ) ) { emit_move_insn ( simplify_gen_subreg ( SImode , dst , mode , 0 ) , src ) ; return 1 ; } else { src = force_reg ( SImode , src ) ; src = gen_lowpart_SUBREG ( mode , src ) ; operands [ 1 ] = src ; } } } if ( can_create_pseudo_p ( ) && ! xtensa_valid_move ( mode , operands ) ) operands [ 1 ] = force_reg ( mode , operands [ 1 ] ) ; operands [ 1 ] = xtensa_copy_incoming_a7 ( operands [ 1 ] ) ; if ( reload_in_progress ) { operands [ 0 ] = fixup_subreg_mem ( operands [ 0 ] ) ; operands [ 1 ] = fixup_subreg_mem ( operands [ 1 ] ) ; } return 0 ; } </s>

Emit insns to move operands [ 1 ] into operands [ 0 ] . Return 1 if we have written out everything that needs to be done to do the move . Otherwise , return 0 and the caller will emit the move normally .


<s> static void ix86_emit_leave ( void ) { struct machine_function * m = cfun -> machine ; rtx_insn * insn = emit_insn ( ix86_gen_leave ( ) ) ; ix86_add_queued_cfa_restore_notes ( insn ) ; gcc_assert ( m -> fs . fp_valid ) ; m -> fs . sp_valid = true ; m -> fs . sp_offset = m -> fs . fp_offset - UNITS_PER_WORD ; m -> fs . fp_valid = false ; if ( m -> fs . cfa_reg == hard_frame_pointer_rtx ) { m -> fs . cfa_reg = stack_pointer_rtx ; m -> fs . cfa_offset = m -> fs . sp_offset ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . sp_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } ix86_add_cfa_restore_note ( insn , hard_frame_pointer_rtx , m -> fs . fp_offset ) ; } </s>

Emit code and notes for the LEAVE instruction .


<s> MCELFStreamer & RISCVTargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ; } </s>

Return the output streamer for the assembler .


<s> bool ARMBaseTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { if ( Subtarget . isThumb2 ( ) && ! Subtarget . prefers32BitThumb ( ) ) PM . add ( createThumb2SizeReductionPass ( ) ) ; PM . add ( createARMConstantIslandPass ( ) ) ; return true ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s> rtx cris_gen_movem_load ( rtx src , rtx nregs_rtx , int nprefix ) { int nregs = INTVAL ( nregs_rtx ) ; rtvec vec ; int eltno = 1 ; int i ; rtx srcreg = XEXP ( src , 0 ) ; unsigned int regno = nregs - 1 ; int regno_inc = - 1 ; if ( GET_CODE ( srcreg ) == POST_INC ) srcreg = XEXP ( srcreg , 0 ) ; CRIS_ASSERT ( REG_P ( srcreg ) ) ; if ( nregs == 1 ) return gen_movsi ( gen_rtx_REG ( SImode , 0 ) , src ) ; vec = rtvec_alloc ( nprefix + nregs + ( GET_CODE ( XEXP ( src , 0 ) ) == POST_INC ) ) ; if ( GET_CODE ( XEXP ( src , 0 ) ) == POST_INC ) { RTVEC_ELT ( vec , nprefix + 1 ) = gen_rtx_SET ( VOIDmode , srcreg , plus_constant ( srcreg , nregs * 4 ) ) ; eltno ++ ; } src = replace_equiv_address ( src , srcreg ) ; RTVEC_ELT ( vec , nprefix ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , regno ) , src ) ; regno += regno_inc ; for ( i = 1 ; i < nregs ; i ++ , eltno ++ ) { RTVEC_ELT ( vec , nprefix + eltno ) = gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , regno ) , adjust_address_nv ( src , SImode , i * 4 ) ) ; regno += regno_inc ; } return gen_rtx_PARALLEL ( VOIDmode , vec ) ; } </s>

Worker function for generating movem from mem for load_multiple .


<s> static bool xstormy16_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return mode1 != BImode && mode2 != BImode ; } </s>


"target_clones attribute needs GLIBC (2.23 and newer) that "

"multiversioning needs ifunc which is not supported "

Make a dispatcher declaration for the multi-versioned function DECL . Calls to DECL function will be replaced with calls to the dispatcher by the front-end . Returns the decl of the dispatcher function .


<s> bool HexagonTargetLowering :: IsEligibleForTailCallOptimization ( SDValue Callee , CallingConv :: ID CalleeCC , bool isVarArg , bool isCalleeStructRet , bool isCallerStructRet , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < ISD :: InputArg > & Ins , SelectionDAG & DAG ) const { const Function & CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; if ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) { return false ; } if ( ! CCMatch ) { bool R = ( CallerCC == CallingConv :: C || CallerCC == CallingConv :: Fast ) ; bool E = ( CalleeCC == CallingConv :: C || CalleeCC == CallingConv :: Fast ) ; if ( ! R || ! E ) return false ; } if ( isVarArg ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; return true ; } </s>

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization .

Hexagon Hexagon ISD::OutputArg ISD::InputArg


<s> MCSymbol * X86TargetLowering :: getPICBaseSymbol ( const MachineFunction * MF , MCContext & Ctx ) const { const MCAsmInfo & MAI = * getTargetMachine ( ) . getMCAsmInfo ( ) ; return Ctx . GetOrCreateSymbol ( Twine ( MAI . getPrivateGlobalPrefix ( ) ) + Twine ( MF -> getFunctionNumber ( ) ) + "$pb" ) ; } </s>

getPICBaseSymbol - Return a function-local symbol to represent the PIC base .


<s> void MMIXMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; support :: endian :: write ( OS , Bits , support :: big ) ; ++ MCNumEmitted ; } </s>

Encode the given Inst to bytes and append to CB .


<s> static struct machine_function * rs6000_init_machine_status ( void ) { stack_info . reload_completed = 0 ; return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Functions to init , mark and free struct machine_function . These will be called , via pointer variables , from push_function_context and pop_function_context .


<s> void SIInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; SIMachineFunctionInfo * MFI = MF -> getInfo < SIMachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad , Size , Align ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( Register :: isVirtualRegister ( DestReg ) && SpillSize == 4 ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & AMDGPU :: SReg_32_XM0RegClass ) ; } if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillRestoreOpcode ( SpillSize ) : getVGPRSpillRestoreOpcode ( SpillSize ) ; auto MIB = BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) ; if ( RI . hasAGPRs ( RC ) ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; Register Tmp = MRI . createVirtualRegister ( & AMDGPU :: VGPR_32RegClass ) ; MIB . addReg ( Tmp , RegState :: Define ) ; } MIB . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( 0 ) . addMemOperand ( MMO ) ; } </s>

Load the specified register of the given register class from the specified stack frame index .


<s> DecodeStatus Mips64Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & VStream , raw_ostream & CStream ) const { uint64_t Insn ; DecodeStatus Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTableMips32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = 4 ; return Result ; } return MCDisassembler :: Fail ; } </s>

Returns the disassembly of a single instruction .


<s> bool SIInstrInfo :: isLegalVSrcOperand ( const MachineRegisterInfo & MRI , const MCOperandInfo & OpInfo , const MachineOperand & MO ) const { if ( MO . isReg ( ) ) return isLegalRegOperand ( MRI , OpInfo , MO ) ; assert ( MO . isImm ( ) || MO . isTargetIndex ( ) || MO . isFI ( ) ) ; return true ; } </s>

Check if MO would be a valid operand for the given operand definition OpInfo .


<s> RegisterBankInfo :: InstructionMapping ARMRegisterBankInfo :: getInstrMapping ( const MachineInstr & MI ) const { auto Opc = MI . getOpcode ( ) ; if ( ! isPreISelGenericOpcode ( Opc ) ) { InstructionMapping Mapping = getInstrMappingImpl ( MI ) ; if ( Mapping . isValid ( ) ) return Mapping ; } using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & ARM :: ValueMappings [ 0 ] ; switch ( Opc ) { case G_ADD : case G_LOAD : case G_SEXT : case G_ZEXT : OperandsMapping = & ARM :: ValueMappings [ 0 ] ; break ; case G_FRAME_INDEX : OperandsMapping = getOperandsMapping ( { & ARM :: ValueMappings [ 0 ] , nullptr } ) ; break ; default : return InstructionMapping { } ; } return InstructionMapping { DefaultMappingID , 1 , OperandsMapping , NumOperands } ; } </s>

Get the mapping of the different operands of MI on the register bank .