<s> WebAssemblyTargetMachine :: WebAssemblyTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? "e-m:e-p:64:64-i64:64-n32:64-S128" : "e-m:e-p:32:32-i64:64-n32:64-S128" , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM ? * CM : CodeModel :: Large , OL ) , TLOF ( new WebAssemblyTargetObjectFile ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . FunctionSections = true ; this -> Options . DataSections = true ; this -> Options . UniqueSectionNames = true ; initAsmInfo ( ) ; } </s>

Create an WebAssembly architecture model .

WebAssembly WebAssembly WebAssembly "e-m:e-p:64:64-i64:64-n32:64-S128" "e-m:e-p:32:32-i64:64-n32:64-S128" WebAssembly


<s> bool gprel_constant_p ( rtx op ) { if ( GET_CODE ( op ) == SYMBOL_REF && nios2_symbol_ref_in_small_data_p ( op ) ) return true ; else if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , 0 ) ) == PLUS ) return gprel_constant_p ( XEXP ( XEXP ( op , 0 ) , 0 ) ) ; return false ; } </s>

Return true if this is a GP-relative accessible reference .


<s> static tree gcn_goacc_get_worker_red_decl ( tree type , unsigned offset ) { machine_function * machfun = cfun -> machine ; tree existing_decl ; if ( TREE_CODE ( type ) == REFERENCE_TYPE ) type = TREE_TYPE ( type ) ; tree var_type = build_qualified_type ( type , ( TYPE_QUALS ( type ) | ENCODE_QUAL_ADDR_SPACE ( ADDR_SPACE_LDS ) ) ) ; if ( machfun -> reduc_decls && offset < machfun -> reduc_decls -> length ( ) && ( existing_decl = ( * machfun -> reduc_decls ) [ offset ] ) ) { gcc_assert ( TREE_TYPE ( existing_decl ) == var_type ) ; return existing_decl ; } else { char name [ 50 ] ; sprintf ( name , ".oacc_reduction_%u" , offset ) ; tree decl = create_tmp_var_raw ( var_type , name ) ; DECL_CONTEXT ( decl ) = NULL_TREE ; TREE_STATIC ( decl ) = 1 ; varpool_node :: finalize_decl ( decl ) ; vec_safe_grow_cleared ( machfun -> reduc_decls , offset + 1 , true ) ; ( * machfun -> reduc_decls ) [ offset ] = decl ; return decl ; } return NULL_TREE ; } </s>

Return a temporary variable decl to use for an OpenACC worker reduction .


<s>
static
void
adjust_extract
(
rtx_insn
*
insn
)
{
rtx
pattern
=
PATTERN
(
insn
)
;
if
(
GET_CODE
(
pattern
)
==
PARALLEL
)
pattern
=
XVECEXP
(
pattern
,
0
,
0
)
;
rtx
src
=
SET_SRC
(
pattern
)
;
rtx
sel
=
GET_CODE
(
src
)
==
VEC_DUPLICATE
XEXP
(
src
,
0
)
:
src
;
rtx
par
=
XEXP
(
sel
,
1
)
;
int
half_elts
=
GET_MODE_NUNITS
(
GET_MODE
(
XEXP
(
sel
,
0
)
)
)
>>
1
;
int
lane
=
INTVAL
(
XVECEXP
(
par
,
0
,
0
)
)
;
lane
=
lane
>=
half_elts
lane
half_elts
:
lane
+
half_elts
;
XVECEXP
(
par
,
0
,
0
)
=
GEN_INT
(
lane
)
;
INSN_CODE
(
insn
)
=
1
;
df_insn_rescan
(
insn
)
;
if
(
dump_file
)
fprintf
(
dump_file
,
"Changing lane for extract %d\n"
,
INSN_UID
(
insn
)
)
;
}
</s>

Given OP that contains a vector extract operation , adjust the index of the extracted lane to account for the doubleword swap .


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode || mode == V8HFmode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) ) return true ; if ( TARGET_INT_SIMD && ( mode == V4UQQmode || mode == V4QQmode || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode || mode == V2HAmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .


<s> bool AMDGPUAAResult :: pointsToConstantMemory ( const MemoryLocation & Loc , bool OrLocal ) { const Value * Base = GetUnderlyingObject ( Loc . Ptr , DL ) ; unsigned AS = Base -> getType ( ) -> getPointerAddressSpace ( ) ; if ( AS == AMDGPUAS :: CONSTANT_ADDRESS || AS == AMDGPUAS :: CONSTANT_ADDRESS_32BIT ) { return true ; } if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( Base ) ) { if ( GV -> isConstant ( ) ) return true ; } else if ( const Argument * Arg = dyn_cast < Argument > ( Base ) ) { const Function * F = Arg -> getParent ( ) ; switch ( F -> getCallingConv ( ) ) { default : return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ; case CallingConv :: AMDGPU_LS : case CallingConv :: AMDGPU_HS : case CallingConv :: AMDGPU_ES : case CallingConv :: AMDGPU_GS : case CallingConv :: AMDGPU_VS : case CallingConv :: AMDGPU_PS : case CallingConv :: AMDGPU_CS : case CallingConv :: AMDGPU_KERNEL : case CallingConv :: SPIR_KERNEL : break ; } unsigned ArgNo = Arg -> getArgNo ( ) ; if ( F -> hasParamAttribute ( ArgNo , Attribute :: NoAlias ) && ( F -> hasParamAttribute ( ArgNo , Attribute :: ReadNone ) || F -> hasParamAttribute ( ArgNo , Attribute :: ReadOnly ) ) ) { return true ; } } return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ; } </s>

A convenience wrapper around the primary pointsToConstantMemory interface .

AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU AMDGPU


<s> bool X86TTIImpl :: isLegalMaskedStore ( Type * DataType ) { return isLegalMaskedLoad ( DataType ) ; } </s>

Return true if the target supports masked store .


<s> static bool riscv_secondary_memory_needed ( machine_mode mode , reg_class_t class1 , reg_class_t class2 ) { return ( ! riscv_v_ext_vector_mode_p ( mode ) && GET_MODE_SIZE ( mode ) . to_constant ( ) > UNITS_PER_WORD && ( class1 == FP_REGS ) != ( class2 == FP_REGS ) && ! TARGET_XTHEADFMV ) ; } </s>

Implement TARGET_SECONDARY_MEMORY_NEEDED . When floating-point registers are wider than integer ones , moves between them must go through memory .


<s>
MachineBasicBlock
*
ARCompactTargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
*
MI
,
MachineBasicBlock
*
BB
)
const
{
const
TargetInstrInfo
&
TII
=
*
getTargetMachine
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
->
getDebugLoc
(
)
;
assert
(
(
MI
->
getOpcode
(
)
==
ARC
::
Select
)
&&
"We can only emit SELECT_CC"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
BB
;
++
I
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
llvm
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
ARC
::
BCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
->
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
ARC
::
PHI
)
,
MI
->
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
->
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
->
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
->
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static unsigned rs6000_add_stmt_cost ( void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , int misalign , enum vect_cost_model_location where ) { rs6000_cost_data * cost_data = ( rs6000_cost_data * ) data ; unsigned retval = 0 ; if ( flag_vect_cost_model ) { tree vectype = stmt_info ? stmt_vectype ( stmt_info ) : NULL_TREE ; int stmt_cost = rs6000_builtin_vectorization_cost ( kind , vectype , misalign ) ; if ( where == vect_body && stmt_info && stmt_in_inner_loop_p ( stmt_info ) ) count *= 50 ; retval = ( unsigned ) ( count * stmt_cost ) ; cost_data -> cost [ where ] += retval ; if ( ( kind == vec_to_scalar || kind == vec_perm || kind == vec_promote_demote || kind == vec_construct || kind == scalar_to_vec ) || ( where == vect_body && kind == vector_stmt ) ) rs6000_vect_nonmem = true ; } return retval ; } </s>


<s> unsigned PPCTargetLowering :: combineRepeatedFPDivisors ( ) const { switch ( Subtarget . getDarwinDirective ( ) ) { default : return 3 ; case PPC :: DIR_440 : case PPC :: DIR_A2 : case PPC :: DIR_E500mc : case PPC :: DIR_E5500 : return 2 ; } } </s>

Indicate whether this target prefers to combine FDIVs with the same divisor .


<s> static reg_class_t avr_secondary_reload ( bool in_p , rtx x , reg_class_t reload_class ATTRIBUTE_UNUSED , machine_mode mode , secondary_reload_info * sri ) { if ( in_p && MEM_P ( x ) && ! ADDR_SPACE_GENERIC_P ( MEM_ADDR_SPACE ( x ) ) && ADDR_SPACE_MEMX != MEM_ADDR_SPACE ( x ) ) { switch ( mode ) { default : gcc_unreachable ( ) ; case QImode : sri -> icode = CODE_FOR_reload_inqi ; break ; case QQmode : sri -> icode = CODE_FOR_reload_inqq ; break ; case UQQmode : sri -> icode = CODE_FOR_reload_inuqq ; break ; case HImode : sri -> icode = CODE_FOR_reload_inhi ; break ; case HQmode : sri -> icode = CODE_FOR_reload_inhq ; break ; case HAmode : sri -> icode = CODE_FOR_reload_inha ; break ; case UHQmode : sri -> icode = CODE_FOR_reload_inuhq ; break ; case UHAmode : sri -> icode = CODE_FOR_reload_inuha ; break ; case PSImode : sri -> icode = CODE_FOR_reload_inpsi ; break ; case SImode : sri -> icode = CODE_FOR_reload_insi ; break ; case SFmode : sri -> icode = CODE_FOR_reload_insf ; break ; case SQmode : sri -> icode = CODE_FOR_reload_insq ; break ; case SAmode : sri -> icode = CODE_FOR_reload_insa ; break ; case USQmode : sri -> icode = CODE_FOR_reload_inusq ; break ; case USAmode : sri -> icode = CODE_FOR_reload_inusa ; break ; } } return NO_REGS ; } </s>


<s> static bool arm_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( TARGET_AAPCS_BASED ) return must_pass_in_stack_var_size ( mode , type ) ; else return must_pass_in_stack_var_size_or_pad ( mode , type ) ; } </s>

Return true if a type must be passed in memory . For AAPCS , small aggregates ( padded to the size of a word ) should be passed in a register .


"unknown flag passed in -moverride=%s (%s)"

Parse TOKEN , which has length LENGTH to see if it is an option described in FLAG . If it is , return the index bit for that fusion type . If not , error ( printing OPTION_NAME ) and return zero .


<s> static bool pa_scalar_mode_supported_p ( enum machine_mode mode ) { int precision = GET_MODE_PRECISION ( mode ) ; switch ( GET_MODE_CLASS ( mode ) ) { case MODE_PARTIAL_INT : case MODE_INT : if ( precision == CHAR_TYPE_SIZE ) return true ; if ( precision == SHORT_TYPE_SIZE ) return true ; if ( precision == INT_TYPE_SIZE ) return true ; if ( precision == LONG_TYPE_SIZE ) return true ; if ( precision == LONG_LONG_TYPE_SIZE ) return true ; return false ; case MODE_FLOAT : if ( precision == FLOAT_TYPE_SIZE ) return true ; if ( precision == DOUBLE_TYPE_SIZE ) return true ; if ( precision == LONG_DOUBLE_TYPE_SIZE ) return true ; return false ; default : gcc_unreachable ( ) ; } } </s>

True if MODE is valid for the target . By `` valid '' , we mean able to be manipulated in non-trivial ways . In particular , this means all the arithmetic is supported .


"unrecognised interrupt vector argument of %qE attribute"

"numeric argument of %qE attribute must be in range 0..63"

"argument of %qE attribute is not a string constant or number"

"%qE attribute only applies to functions"


<s> Value * simplify ( Instruction * I ) { return SimplifyInstruction ( I , { * TD , TLI , DT } ) ; } </s>

Go through all the nodes in the graph and collapse any two nodes ' a ' and ' b ' if all of the following are true :


<s> static void s390_reorg ( void ) { struct constant_pool * pool ; rtx_insn * insn ; int hw_before , hw_after ; if ( s390_tune == PROCESSOR_2964_Z13 ) s390_adjust_loops ( ) ; split_all_insns_noflow ( ) ; pool = s390_mainpool_start ( ) ; if ( pool ) { s390_mainpool_finish ( pool ) ; } else { pool = s390_chunkify_start ( ) ; s390_chunkify_finish ( pool ) ; } for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { rtx label ; rtx_insn * target ; label = s390_execute_label ( insn ) ; if ( ! label ) continue ; gcc_assert ( label != const0_rtx ) ; target = emit_label ( XEXP ( label , 0 ) ) ; INSN_ADDRESSES_NEW ( target , - 1 ) ; if ( JUMP_P ( insn ) ) { target = emit_jump_insn ( s390_execute_target ( insn ) ) ; JUMP_LABEL ( target ) = JUMP_LABEL ( insn ) ; } else target = emit_insn ( s390_execute_target ( insn ) ) ; INSN_ADDRESSES_NEW ( target , - 1 ) ; } s390_optimize_prologue ( ) ; if ( s390_tune >= PROCESSOR_2097_Z10 ) { rtx_insn * insn ; bool insn_added_p = false ; shorten_branches ( get_insns ( ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) || INSN_CODE ( insn ) <= 0 ) continue ; if ( JUMP_P ( insn ) ) insn_added_p |= s390_fix_long_loop_prediction ( insn ) ; if ( ( GET_CODE ( PATTERN ( insn ) ) == PARALLEL || GET_CODE ( PATTERN ( insn ) ) == SET ) && s390_tune == PROCESSOR_2097_Z10 ) insn_added_p |= s390_z10_optimize_cmp ( insn ) ; } if ( insn_added_p ) shorten_branches ( get_insns ( ) ) ; } s390_function_num_hotpatch_hw ( current_function_decl , & hw_before , & hw_after ) ; if ( hw_after > 0 ) { rtx_insn * insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( active_insn_p ( insn ) || BARRIER_P ( insn ) || LABEL_P ( insn ) ) break ; while ( insn && hw_after > 0 ) { if ( hw_after >= 3 ) { emit_insn_before ( gen_nop_6_byte ( ) , insn ) ; hw_after -= 3 ; } else if ( hw_after >= 2 ) { emit_insn_before ( gen_nop_4_byte ( ) , insn ) ; hw_after -= 2 ; } else { emit_insn_before ( gen_nop_2_byte ( ) , insn ) ; hw_after -= 1 ; } } } } </s>


<s>
unsigned
PPCVSXSwapRemoval
::
lookThruCopyLike
(
unsigned
SrcReg
,
unsigned
VecIdx
)
{
MachineInstr
*
MI
=
MRI
->
getVRegDef
(
SrcReg
)
;
if
(
!
MI
->
isCopyLike
(
)
)
return
SrcReg
;
unsigned
CopySrcReg
;
if
(
MI
->
isCopy
(
)
)
CopySrcReg
=
MI
->
getOperand
(
1
)
.
getReg
(
)
;
else
{
assert
(
MI
->
isSubregToReg
(
)
&&
"bad opcode for lookThruCopyLike"
)
;
CopySrcReg
=
MI
->
getOperand
(
2
)
.
getReg
(
)
;
}
if
(
!
TargetRegisterInfo
::
isVirtualRegister
(
CopySrcReg
)
)
{
if
(
!
isScalarVecReg
(
CopySrcReg
)
)
SwapVector
[
VecIdx
]
.
MentionsPhysVR
=
1
;
return
CopySrcReg
;
}
return
lookThruCopyLike
(
CopySrcReg
,
VecIdx
)
;
}
</s>

Returns the original SrcReg unless it is the target of a copy-like operation , in which case we chain backwards through all such operations to the ultimate source register .


"Slot for FPW register must be last in order to be found!"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> static bool spe_func_has_64bit_regs_p ( void ) { rtx_insn * insns , * insn ; if ( crtl -> calls_eh_return || cfun -> calls_setjmp || crtl -> has_nonlocal_goto ) return true ; insns = get_insns ( ) ; for ( insn = NEXT_INSN ( insns ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { rtx i ; i = PATTERN ( insn ) ; if ( GET_CODE ( i ) == SET ) { machine_mode mode = GET_MODE ( SET_SRC ( i ) ) ; if ( SPE_VECTOR_MODE ( mode ) ) return true ; if ( TARGET_E500_DOUBLE && ( mode == DFmode || FLOAT128_2REG_P ( mode ) ) ) return true ; } } } return false ; } </s>

Return true if the current function uses any GPRs in 64-bit SIMD mode .


<s>
bool
VEAsmParser
::
ParseInstruction
(
ParseInstructionInfo
&
Info
,
StringRef
Name
,
SMLoc
NameLoc
,
OperandVector
&
Operands
)
{
Operands
.
push_back
(
VEOperand
::
CreateToken
(
Name
,
NameLoc
)
)
;
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
while
(
getLexer
(
)
.
is
(
AsmToken
::
Comma
)
)
{
Parser
.
Lex
(
)
;
if
(
parseOperand
(
Operands
,
Name
)
!=
MatchOperand_Success
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
}
}
if
(
getLexer
(
)
.
isNot
(
AsmToken
::
EndOfStatement
)
)
{
SMLoc
Loc
=
getLexer
(
)
.
getLoc
(
)
;
return
Error
(
Loc
,
"unexpected token"
)
;
}
Parser
.
Lex
(
)
;
return
false
;
}
</s>

ParseInstruction - Parse one assembly instruction .

VE
VE
VEOperand::CreateToken
"unexpected token"
"unexpected token"
"unexpected token"


<s>
unsigned
ARMBaseInstrInfo
::
getPartialRegUpdateClearance
(
const
MachineInstr
*
MI
,
unsigned
OpNum
,
const
TargetRegisterInfo
*
TRI
)
const
{
if
(
!
SwiftPartialUpdateClearance
||
!
Subtarget
.
isSwift
(
)
)
return
0
;
assert
(
TRI
&&
"Need TRI instance"
)
;
const
MachineOperand
&
MO
=
MI
->
getOperand
(
OpNum
)
;
if
(
MO
.
readsReg
(
)
)
return
0
;
unsigned
Reg
=
MO
.
getReg
(
)
;
int
UseOp
=
1
;
switch
(
MI
->
getOpcode
(
)
)
{
case
ARM
::
VLDRS
:
case
ARM
::
FCONSTS
:
case
ARM
::
VMOVSR
:
case
ARM
::
VMOVv8i8
:
case
ARM
::
VMOVv4i16
:
case
ARM
::
VMOVv2i32
:
case
ARM
::
VMOVv2f32
:
case
ARM
::
VMOVv1i64
:
UseOp
=
MI
->
findRegisterUseOperandIdx
(
Reg
,
false
,
TRI
)
;
break
;
case
ARM
::
VLD1LNd32
:
UseOp
=
1
;
break
;
default
:
return
0
;
}
if
(
UseOp
!=
1
&&
MI
->
getOperand
(
UseOp
)
.
readsReg
(
)
)
return
0
;
if
(
TargetRegisterInfo
::
isVirtualRegister
(
Reg
)
)
{
if
(
!
MO
.
getSubReg
(
)
||
MI
->
readsVirtualRegister
(
Reg
)
)
return
0
;
}
else
if
(
ARM
::
SPRRegClass
.
contains
(
Reg
)
)
{
unsigned
DReg
=
TRI
->
getMatchingSuperReg
(
Reg
,
ARM
::
ssub_0
,
&
ARM
::
DPRRegClass
)
;
if
(
!
DReg
||
!
MI
->
definesRegister
(
DReg
,
TRI
)
)
return
0
;
}
return
SwiftPartialUpdateClearance
;
}
</s>

Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update .


<s> static bool unicosmk_must_pass_in_stack ( enum machine_mode mode , tree type ) { if ( type == NULL ) return false ; if ( TREE_CODE ( TYPE_SIZE ( type ) ) != INTEGER_CST ) return true ; if ( TREE_ADDRESSABLE ( type ) ) return true ; return ALPHA_ARG_SIZE ( mode , type , 0 ) > 2 ; } </s>

This evaluates to true if we do not know how to pass TYPE solely in registers . This is the case for all arguments that do not fit in two registers .


<s> bool SIInstrInfo :: isInlineConstant ( const MachineOperand & MO , unsigned OpSize ) const { if ( MO . isImm ( ) ) { unsigned BitSize = 8 * OpSize ; return isInlineConstant ( APInt ( BitSize , MO . getImm ( ) , true ) ) ; } return false ; } </s>

returns true if the operand OpIdx in MI is a valid inline immediate .


<s> static int loongarch_register_move_cost ( machine_mode mode , reg_class_t from , reg_class_t to ) { reg_class_t dregs ; int cost1 , cost2 ; from = loongarch_canonicalize_move_class ( from ) ; to = loongarch_canonicalize_move_class ( to ) ; if ( from == FP_REGS ) { if ( to == FP_REGS && loongarch_mode_ok_for_mov_fmt_p ( mode ) ) return 4 ; } dregs = GENERAL_REGS ; if ( from == dregs ) return loongarch_move_from_gpr_cost ( to ) ; if ( to == dregs ) return loongarch_move_to_gpr_cost ( from ) ; cost1 = loongarch_move_to_gpr_cost ( from ) ; if ( cost1 != 0 ) { cost2 = loongarch_move_from_gpr_cost ( to ) ; if ( cost2 != 0 ) return cost1 + cost2 ; } return 0 ; } </s>

Implement TARGET_REGISTER_MOVE_COST . Return 0 for classes that are the maximum of the move costs for subclasses ; regclass will work out the maximum for us .


<s> bool s390_can_use_return_insn ( void ) { int i ; if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ; if ( TARGET_TPF_PROFILING ) return false ; for ( i = 0 ; i < 16 ; i ++ ) if ( cfun_gpr_save_slot ( i ) != SAVE_SLOT_NONE ) return false ; if ( ! TARGET_64BIT && ( cfun_fpr_save_p ( FPR4_REGNUM ) || cfun_fpr_save_p ( FPR6_REGNUM ) ) ) return false ; if ( cfun -> machine -> base_reg && ! call_really_used_regs [ REGNO ( cfun -> machine -> base_reg ) ] ) return false ; return cfun_frame_layout . frame_size == 0 ; } </s>

Return true if the epilogue is guaranteed to contain only a return instruction and if a direct return can therefore be used instead . One of the main advantages of using direct return instructions is that we can then use conditional returns .


": unsupported initializer for address space"

Emit the specified global variable to the .s file .


<s> void rs6000_split_logical ( rtx operands [ 3 ] , enum rtx_code code , bool complement_final_p , bool complement_op1_p , bool complement_op2_p ) { machine_mode mode = GET_MODE ( operands [ 0 ] ) ; machine_mode sub_mode ; rtx op0 , op1 , op2 ; int sub_size , regno0 , regno1 , nregs , i ; if ( mode == DImode && ! TARGET_POWERPC64 ) { rs6000_split_logical_di ( operands , code , complement_final_p , complement_op1_p , complement_op2_p ) ; return ; } op0 = operands [ 0 ] ; op1 = operands [ 1 ] ; op2 = ( code == NOT ) ? NULL_RTX : operands [ 2 ] ; sub_mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; sub_size = GET_MODE_SIZE ( sub_mode ) ; regno0 = REGNO ( op0 ) ; regno1 = REGNO ( op1 ) ; gcc_assert ( reload_completed ) ; gcc_assert ( IN_RANGE ( regno0 , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; gcc_assert ( IN_RANGE ( regno1 , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; nregs = rs6000_hard_regno_nregs [ ( int ) mode ] [ regno0 ] ; gcc_assert ( nregs > 1 ) ; if ( op2 && REG_P ( op2 ) ) gcc_assert ( IN_RANGE ( REGNO ( op2 ) , FIRST_GPR_REGNO , LAST_GPR_REGNO ) ) ; for ( i = 0 ; i < nregs ; i ++ ) { int offset = i * sub_size ; rtx sub_op0 = simplify_subreg ( sub_mode , op0 , mode , offset ) ; rtx sub_op1 = simplify_subreg ( sub_mode , op1 , mode , offset ) ; rtx sub_op2 = ( ( code == NOT ) ? NULL_RTX : simplify_subreg ( sub_mode , op2 , mode , offset ) ) ; rs6000_split_logical_inner ( sub_op0 , sub_op1 , sub_op2 , code , sub_mode , complement_final_p , complement_op1_p , complement_op2_p ) ; } return ; } </s>

Split the insns that make up boolean operations operating on multiple GPR registers . The boolean MD patterns ensure that the inputs either are exactly the same as the output registers , or there is no overlap . OPERANDS is an array containing the destination and two input operands . CODE is the base operation ( AND , IOR , XOR , NOT ) . If COMPLEMENT_FINAL_P is true , wrap the whole operation with NOT . If COMPLEMENT_OP1_P is true , wrap operand1 with NOT . If COMPLEMENT_OP2_P is true , wrap operand2 with NOT .


<s> void PPCHazardRecognizer970 :: EmitInstruction ( SUnit * SU ) { MachineInstr * MI = SU -> getInstr ( ) ; if ( MI -> isDebugValue ( ) ) return ; unsigned Opcode = MI -> getOpcode ( ) ; LastWasBL8_ELF = ( Opcode == PPC :: BL8_ELF ) ; bool isFirst , isSingle , isCracked , isLoad , isStore ; PPCII :: PPC970_Unit InstrType = GetInstrType ( Opcode , isFirst , isSingle , isCracked , isLoad , isStore ) ; if ( InstrType == PPCII :: PPC970_Pseudo ) return ; if ( Opcode == PPC :: MTCTR || Opcode == PPC :: MTCTR8 ) HasCTRSet = true ; if ( isStore && NumStores < 4 && ! MI -> memoperands_empty ( ) ) { MachineMemOperand * MO = * MI -> memoperands_begin ( ) ; StoreSize [ NumStores ] = MO -> getSize ( ) ; StoreOffset [ NumStores ] = MO -> getOffset ( ) ; StoreValue [ NumStores ] = MO -> getValue ( ) ; ++ NumStores ; } if ( InstrType == PPCII :: PPC970_BRU || isSingle ) NumIssued = 4 ; ++ NumIssued ; if ( isCracked ) ++ NumIssued ; if ( NumIssued == 5 ) EndDispatchGroup ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> bool ARMFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; ARMFunctionInfo * AFI = MF . getInfo < ARMFunctionInfo > ( ) ; unsigned PushOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STMDB_UPD : ARM :: STMDB_UPD ; unsigned PushOneOpc = AFI -> isThumbFunction ( ) ? ARM :: t2STR_PRE : ARM :: STR_PRE_IMM ; unsigned FltOpc = ARM :: VSTMDDB_UPD ; unsigned NumAlignedDPRCS2Regs = AFI -> getNumAlignedDPRCS2Regs ( ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea1Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , PushOpc , PushOneOpc , false , & isARMArea2Register , 0 , MachineInstr :: FrameSetup ) ; emitPushInst ( MBB , MI , CSI , FltOpc , 0 , true , & isARMArea3Register , NumAlignedDPRCS2Regs , MachineInstr :: FrameSetup ) ; if ( NumAlignedDPRCS2Regs ) emitAlignedDPRCS2Spills ( MBB , MI , NumAlignedDPRCS2Regs , CSI , TRI ) ; return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


<s> static int arc_address_cost ( rtx addr , machine_mode , addr_space_t , bool speed ) { switch ( GET_CODE ( addr ) ) { case REG : return speed || satisfies_constraint_Rcq ( addr ) ? 0 : 1 ; case PRE_INC : case PRE_DEC : case POST_INC : case POST_DEC : case PRE_MODIFY : case POST_MODIFY : return ! speed ; case LABEL_REF : case SYMBOL_REF : case CONST : if ( TARGET_NPS_CMEM && cmem_address ( addr , SImode ) ) return 0 ; return COSTS_N_INSNS ( 1 ) ; case PLUS : { rtx plus0 = XEXP ( addr , 0 ) ; rtx plus1 = XEXP ( addr , 1 ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) != MULT || ! CONST_INT_P ( XEXP ( plus0 , 1 ) ) || ( INTVAL ( XEXP ( plus0 , 1 ) ) != 2 && INTVAL ( XEXP ( plus0 , 1 ) ) != 4 ) ) ) break ; switch ( GET_CODE ( plus1 ) ) { case CONST_INT : return ( ! RTX_OK_FOR_OFFSET_P ( SImode , plus1 ) ? COSTS_N_INSNS ( 1 ) : speed ? 0 : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_O ( plus1 ) ) ? 0 : 1 ) ; case REG : return ( speed < 1 ? 0 : ( satisfies_constraint_Rcq ( plus0 ) && satisfies_constraint_Rcq ( plus1 ) ) ? 0 : 1 ) ; case CONST : case SYMBOL_REF : case LABEL_REF : return COSTS_N_INSNS ( 1 ) ; default : break ; } break ; } default : break ; } return 4 ; } </s>

Provide the costs of an addressing mode that contains ADDR . If ADDR is not a valid address , its cost is irrelevant .


<s> static rtx riscv_unspec_offset_high ( rtx temp , rtx addr , enum riscv_symbol_type symbol_type ) { addr = gen_rtx_HIGH ( Pmode , riscv_unspec_address ( addr , symbol_type ) ) ; return riscv_force_temporary ( temp , addr , FALSE ) ; } </s>

If riscv_unspec_address ( ADDR , SYMBOL_TYPE ) is a 32-bit value , add the high part to BASE and return the result . Just return BASE otherwise . TEMP is as for riscv_force_temporary . The returned expression can be used as the first operand to a LO_SUM .


"PPC DAG preprocessing replacing:\nOld:    "

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts .


<s> HOST_WIDE_INT sh_disp_addr_displacement ( rtx x ) { gcc_assert ( satisfies_constraint_Sdd ( x ) ) ; return INTVAL ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ; } </s>

Return the displacement value of a displacement address .


<s>
NVPTXSubtarget
::
NVPTXSubtarget
(
const
std
::
string
&
TT
,
const
std
::
string
&
CPU
,
const
std
::
string
&
FS
,
bool
is64Bit
)
:
NVPTXGenSubtargetInfo
(
TT
,
CPU
,
FS
)
,
Is64Bit
(
is64Bit
)
,
PTXVersion
(
0
)
,
SmVersion
(
20
)
{
Triple
T
(
TT
)
;
if
(
T
.
getOS
(
)
==
Triple
::
NVCL
)
drvInterface
=
NVPTX
::
NVCL
;
else
drvInterface
=
NVPTX
::
CUDA
;
std
::
string
defCPU
=
"sm_20"
;
ParseSubtargetFeatures
(
(
CPU
.
empty
(
)
defCPU
:
CPU
)
,
FS
)
;
if
(
FS
.
empty
(
)
&&
CPU
.
empty
(
)
)
TargetName
=
defCPU
;
else
if
(
!
CPU
.
empty
(
)
)
TargetName
=
CPU
;
else
llvm_unreachable
(
"we are not using FeatureStr"
)
;
if
(
PTXVersion
==
0
)
{
PTXVersion
=
31
;
}
}
</s>

This constructor initializes the data members to match that of the specified module .


<s> void TeakRegisterInfo :: materializeFrameBaseRegister ( MachineBasicBlock * MBB , unsigned BaseReg , int FrameIdx , int64_t Offset ) const { } </s>

Insert defining instruction ( s ) for a pointer to FrameIdx before insertion point I .


<s> static int safe_group_barrier_needed ( rtx_insn * insn ) { int saved_first_instruction ; int t ; saved_first_instruction = first_instruction ; in_safe_group_barrier = 1 ; t = group_barrier_needed ( insn ) ; first_instruction = saved_first_instruction ; in_safe_group_barrier = 0 ; return t ; } </s>

Like group_barrier_needed , but do not clobber the current state .


<s> MachineBasicBlock * MipsSETargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { switch ( MI -> getOpcode ( ) ) { default : return MipsTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case Mips :: BPOSGE32_PSEUDO : return emitBPOSGE32 ( MI , BB ) ; case Mips :: SNZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_B ) ; case Mips :: SNZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_H ) ; case Mips :: SNZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_W ) ; case Mips :: SNZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_D ) ; case Mips :: SNZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BNZ_V ) ; case Mips :: SZ_B_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_B ) ; case Mips :: SZ_H_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_H ) ; case Mips :: SZ_W_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_W ) ; case Mips :: SZ_D_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_D ) ; case Mips :: SZ_V_PSEUDO : return emitMSACBranchPseudo ( MI , BB , Mips :: BZ_V ) ; case Mips :: COPY_FW_PSEUDO : return emitCOPY_FW ( MI , BB ) ; case Mips :: COPY_FD_PSEUDO : return emitCOPY_FD ( MI , BB ) ; case Mips :: INSERT_FW_PSEUDO : return emitINSERT_FW ( MI , BB ) ; case Mips :: INSERT_FD_PSEUDO : return emitINSERT_FD ( MI , BB ) ; case Mips :: INSERT_B_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 1 , false ) ; case Mips :: INSERT_H_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 2 , false ) ; case Mips :: INSERT_W_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 4 , false ) ; case Mips :: INSERT_D_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 8 , false ) ; case Mips :: INSERT_FW_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 4 , true ) ; case Mips :: INSERT_FD_VIDX_PSEUDO : return emitINSERT_DF_VIDX ( MI , BB , 8 , true ) ; case Mips :: FILL_FW_PSEUDO : return emitFILL_FW ( MI , BB ) ; case Mips :: FILL_FD_PSEUDO : return emitFILL_FD ( MI , BB ) ; case Mips :: FEXP2_W_1_PSEUDO : return emitFEXP2_W_1 ( MI , BB ) ; case Mips :: FEXP2_D_1_PSEUDO : return emitFEXP2_D_1 ( MI , BB ) ; } } </s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> SDValue SICTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

LowerOperation - Provide custom lowering hooks for some operations .

SIC SIC ISD::BRCOND ISD::GlobalAddress ISD::BlockAddress ISD::JumpTable ISD::SELECT


<s> static HOST_WIDE_INT m32r_starting_frame_offset ( void ) { return M32R_STACK_ALIGN ( crtl -> outgoing_args_size ) ; } </s>

Implement TARGET_STARTING_FRAME_OFFSET . The frame pointer points at the same place as the stack pointer , except if alloca has been called .


<s> virtual const TMS320C64XSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> void HexagonPassConfig :: addIRPasses ( ) { TargetPassConfig :: addIRPasses ( ) ; bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) { if ( EnableInstSimplify ) addPass ( createInstSimplifyLegacyPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ; } addPass ( createAtomicExpandPass ( ) ) ; if ( ! NoOpt ) { if ( EnableInitialCFGCleanup ) addPass ( createCFGSimplificationPass ( SimplifyCFGOptions ( ) . forwardSwitchCondToPhi ( true ) . convertSwitchRangeToICmp ( true ) . convertSwitchToLookupTable ( true ) . needCanonicalLoops ( false ) . hoistCommonInsts ( true ) . sinkCommonInsts ( true ) ) ) ; if ( EnableLoopPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableVectorCombine ) addPass ( createHexagonVectorCombineLegacyPass ( ) ) ; if ( EnableCommGEP ) addPass ( createHexagonCommonGEP ( ) ) ; if ( EnableGenExtract ) addPass ( createHexagonGenExtract ( ) ) ; } } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s> bool loongarch_symbol_binds_local_p ( const_rtx x ) { if ( LABEL_REF_P ( x ) ) return false ; return ( SYMBOL_REF_DECL ( x ) ? targetm . binds_local_p ( SYMBOL_REF_DECL ( x ) ) : SYMBOL_REF_LOCAL_P ( x ) ) ; } </s>

Return true if SYMBOL_REF X binds locally .


<s> void ARMTargetStreamer :: emitInst ( uint32_t Inst , char Suffix ) { llvm_unreachable ( "unimplemented" ) ; } </s>

Callback used to implement the .inst directive .


<s>
unsigned
LC2200InstrInfo
::
removeBranch
(
MachineBasicBlock
&
MBB
,
int
*
BytesRemoved
)
const
{
assert
(
!
BytesRemoved
&&
"code size not handled"
)
;
MachineBasicBlock
::
reverse_iterator
I
=
MBB
.
rbegin
(
)
,
REnd
=
MBB
.
rend
(
)
;
unsigned
removed
=
0
;
while
(
I
!=
REnd
&&
removed
<
2
)
{
if
(
I
->
isDebugInstr
(
)
)
{
++
I
;
continue
;
}
if
(
!
getAnalyzableBrOpc
(
I
->
getOpcode
(
)
)
)
break
;
I
->
eraseFromParent
(
)
;
I
=
MBB
.
rbegin
(
)
;
++
removed
;
}
return
removed
;
}
</s>

Remove the branching code at the end of the specific MBB .


<s>
unsigned
MipsCodeEmitter
::
getBranchTarget21OpValue
(
const
MachineInstr
&
MI
,
unsigned
OpNo
)
const
{
llvm_unreachable
(
"Unimplemented function."
)
;
return
0
;
}
</s>

getBranchTarget21OpValue - Return binary encoding of the branch target operand .


This method may be implemented by targets that want to run passes immediately before register allocation .


"SIInstrInfo::storeRegToStackSlot - Do not know how to"

Store the specified register of the given register class to the specified stack frame index .


<s> BitVector R600RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const R600InstrInfo * TII = static_cast < const R600InstrInfo * > ( ST . getInstrInfo ( ) ) ; Reserved . set ( AMDGPU :: ZERO ) ; Reserved . set ( AMDGPU :: HALF ) ; Reserved . set ( AMDGPU :: ONE ) ; Reserved . set ( AMDGPU :: ONE_INT ) ; Reserved . set ( AMDGPU :: NEG_HALF ) ; Reserved . set ( AMDGPU :: NEG_ONE ) ; Reserved . set ( AMDGPU :: PV_X ) ; Reserved . set ( AMDGPU :: ALU_LITERAL_X ) ; Reserved . set ( AMDGPU :: ALU_CONST ) ; Reserved . set ( AMDGPU :: PREDICATE_BIT ) ; Reserved . set ( AMDGPU :: PRED_SEL_OFF ) ; Reserved . set ( AMDGPU :: PRED_SEL_ZERO ) ; Reserved . set ( AMDGPU :: PRED_SEL_ONE ) ; Reserved . set ( AMDGPU :: INDIRECT_BASE_ADDR ) ; for ( TargetRegisterClass :: iterator I = AMDGPU :: R600_AddrRegClass . begin ( ) , E = AMDGPU :: R600_AddrRegClass . end ( ) ; I != E ; ++ I ) { Reserved . set ( * I ) ; } TII -> reserveIndirectRegisters ( Reserved , MF ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


"********** Fixing br_table Default Targets **********\n"

runOnMachineFunction - Emit the function body .


<s> bool RISCVCleanupVSETVLI :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const RISCVSubtarget & ST = MF . getSubtarget < RISCVSubtarget > ( ) ; if ( ! ST . hasStdExtV ( ) ) return false ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= runOnMachineBasicBlock ( MBB ) ; return Changed ; } </s>


<s> rtx m68k_function_value ( const_tree valtype , const_tree func ATTRIBUTE_UNUSED ) { machine_mode mode ; mode = TYPE_MODE ( valtype ) ; switch ( mode ) { case SFmode : case DFmode : case XFmode : if ( TARGET_68881 ) return gen_rtx_REG ( mode , FP0_REG ) ; break ; default : break ; } if ( func && POINTER_TYPE_P ( TREE_TYPE ( TREE_TYPE ( func ) ) ) ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , A0_REG ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , D0_REG ) , const0_rtx ) ) ) ; else if ( POINTER_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , A0_REG ) ; else return gen_rtx_REG ( mode , D0_REG ) ; } </s>

Location in which function value is returned . NOTE : Due to differences in ABIs , do n't call this function directly , use FUNCTION_VALUE instead .


<s> int ccr_bit ( rtx op , int scc_p ) { enum rtx_code code = GET_CODE ( op ) ; machine_mode cc_mode ; int cc_regnum ; int base_bit ; rtx reg ; if ( ! COMPARISON_P ( op ) ) return - 1 ; reg = XEXP ( op , 0 ) ; gcc_assert ( GET_CODE ( reg ) == REG && CR_REGNO_P ( REGNO ( reg ) ) ) ; cc_mode = GET_MODE ( reg ) ; cc_regnum = REGNO ( reg ) ; base_bit = 4 * ( cc_regnum - CR0_REGNO ) ; validate_condition_mode ( code , cc_mode ) ; gcc_assert ( ! scc_p || code == EQ || code == GT || code == LT || code == UNORDERED || code == GTU || code == LTU ) ; switch ( code ) { case NE : return scc_p ? base_bit + 3 : base_bit + 2 ; case EQ : return base_bit + 2 ; case GT : case GTU : case UNLE : return base_bit + 1 ; case LT : case LTU : case UNGE : return base_bit ; case ORDERED : case UNORDERED : return base_bit + 3 ; case GE : case GEU : return scc_p ? base_bit + 3 : base_bit ; case LE : case LEU : return scc_p ? base_bit + 3 : base_bit + 1 ; default : gcc_unreachable ( ) ; } } </s>

Given a comparison operation , return the bit number in CCR to test . We know this is a valid comparison . SCC_P is 1 if this is for an scc . That means that % D will have been used instead of % C , so the bits will be in different places . Return -1 if OP is n't a valid comparison for some reason .


<s> int M680x0RegisterInfo :: getRegisterOrder ( unsigned Reg , const TargetRegisterClass & TRC ) const { for ( unsigned i = 0 ; i < TRC . getNumRegs ( ) ; ++ i ) { if ( regsOverlap ( Reg , TRC . getRegister ( i ) ) ) { return i ; } } return - 1 ; } </s>

Return index of a register within a register class , otherwise return -1 .


<s> bool SIRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & Fn ) const { return Fn . getFrameInfo ( ) -> hasStackObjects ( ) ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> unsigned OutgoingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) { LLT p0 = LLT :: pointer ( 0 , 32 ) ; LLT s32 = LLT :: scalar ( 32 ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , Mips :: SP ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ; MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ; return AddrReg ; } </s>

Materialize a VReg containing the address of the specified stack-based object .


<s>
void
rs6000_target_modify_macros
(
bool
define_p
,
HOST_WIDE_INT
flags
,
HOST_WIDE_INT
bu_mask
)
{
if
(
TARGET_DEBUG_BUILTIN
||
TARGET_DEBUG_TARGET
)
fprintf
(
stderr
,
"rs6000_target_modify_macros (%s, "
HOST_WIDE_INT_PRINT_HEX
", "
HOST_WIDE_INT_PRINT_HEX
")\n"
,
(
define_p
)
"define"
:
"undef"
,
flags
,
bu_mask
)
;
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PPC"
)
;
if
(
(
flags
&
OPTION_MASK_PPC_GPOPT
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PPCSQ"
)
;
if
(
(
flags
&
OPTION_MASK_PPC_GFXOPT
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PPCGR"
)
;
if
(
(
flags
&
OPTION_MASK_POWERPC64
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PPC64"
)
;
if
(
(
flags
&
OPTION_MASK_MFCRF
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR4"
)
;
if
(
(
flags
&
OPTION_MASK_POPCNTB
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR5"
)
;
if
(
(
flags
&
OPTION_MASK_FPRND
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR5X"
)
;
if
(
(
flags
&
OPTION_MASK_CMPB
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR6"
)
;
if
(
(
flags
&
OPTION_MASK_MFPGPR
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR6X"
)
;
if
(
(
flags
&
OPTION_MASK_POPCNTD
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR7"
)
;
if
(
(
flags
&
OPTION_MASK_DIRECT_MOVE
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_ARCH_PWR8"
)
;
if
(
(
flags
&
OPTION_MASK_SOFT_FLOAT
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"_SOFT_FLOAT"
)
;
if
(
(
flags
&
OPTION_MASK_RECIP_PRECISION
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__RECIP_PRECISION__"
)
;
if
(
(
flags
&
OPTION_MASK_ALTIVEC
)
!=
0
)
{
const
char
*
vec_str
=
(
define_p
)
"__VEC__=10206"
:
"__VEC__"
;
rs6000_define_or_undefine_macro
(
define_p
,
"__ALTIVEC__"
)
;
rs6000_define_or_undefine_macro
(
define_p
,
vec_str
)
;
if
(
!
flag_iso
)
rs6000_define_or_undefine_macro
(
define_p
,
"__APPLE_ALTIVEC__"
)
;
}
if
(
(
flags
&
OPTION_MASK_VSX
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__VSX__"
)
;
if
(
(
flags
&
OPTION_MASK_HTM
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__HTM__"
)
;
if
(
(
flags
&
OPTION_MASK_P8_VECTOR
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__POWER8_VECTOR__"
)
;
if
(
(
flags
&
OPTION_MASK_QUAD_MEMORY
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__QUAD_MEMORY__"
)
;
if
(
(
flags
&
OPTION_MASK_QUAD_MEMORY_ATOMIC
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__QUAD_MEMORY_ATOMIC__"
)
;
if
(
(
flags
&
OPTION_MASK_CRYPTO
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__CRYPTO__"
)
;
if
(
(
flags
&
OPTION_MASK_UPPER_REGS_DF
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__UPPER_REGS_DF__"
)
;
if
(
(
flags
&
OPTION_MASK_UPPER_REGS_SF
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__UPPER_REGS_SF__"
)
;
if
(
(
bu_mask
&
RS6000_BTM_SPE
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__SPE__"
)
;
if
(
(
bu_mask
&
RS6000_BTM_PAIRED
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__PAIRED__"
)
;
if
(
(
bu_mask
&
RS6000_BTM_CELL
)
!=
0
)
rs6000_define_or_undefine_macro
(
define_p
,
"__PPU__"
)
;
}
</s>

Define or undefine macros based on the current target . If the user does # pragma GCC target , we need to adjust the macros dynamically .


<s> static tree tilegx_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= TILEGX_BUILTIN_max ) return error_mark_node ; return tilegx_builtin_info [ code ] . fndecl ; } </s>


<s> int visium_hard_regno_rename_ok ( unsigned int from ATTRIBUTE_UNUSED , unsigned int to ) { if ( ! current_function_saves_lr ( ) && to == long_branch_regnum ) return 0 ; if ( crtl -> is_leaf && ! df_regs_ever_live_p ( to ) && visium_interrupt_function_p ( ) ) return 0 ; return 1 ; } </s>

Helper function for HARD_REGNO_RENAME_OK ( FROM , TO ) . Return non-zero if it is OK to rename a hard register FROM to another hard register TO .


<s> bool MipsPassConfig :: addInstSelector ( ) { addPass ( createMipsISelDag ( getMipsTargetMachine ( ) ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> bool XNCMDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , char ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' : if ( ! SelectAddr ( Op , Op0 , Op1 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> std :: pair < unsigned , const TargetRegisterClass * > NVPTXTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'c' : return std :: make_pair ( 0U , & NVPTX :: Int8RegsRegClass ) ; case 'h' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'r' : return std :: make_pair ( 0U , & NVPTX :: Int32RegsRegClass ) ; case 'l' : case 'N' : return std :: make_pair ( 0U , & NVPTX :: Int64RegsRegClass ) ; case 'f' : return std :: make_pair ( 0U , & NVPTX :: Float32RegsRegClass ) ; case 'd' : return std :: make_pair ( 0U , & NVPTX :: Float64RegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool X86TargetLowering :: useLoadStackGuardNode ( ) const { return Subtarget . isTargetMachO ( ) && Subtarget . is64Bit ( ) ; } </s>

If this function returns true , SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic : :stackprotector .


"SRetReturnReg should have been set in LowerFormalArguments()."

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s>
SDValue
GBZ80TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_GBZ80
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
i
++
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
GBZ80ISD
::
RET
,
dl
,
MVT
::
Other
)
;
}
</s>


"Expected VPT block to start with a VPST or VPT!"

Returns true if this iterator is still pointing at a valid entry .


<s> void HexagonAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MCInst MCB ; MCB . setOpcode ( Hexagon :: BUNDLE ) ; MCB . addOperand ( MCOperand :: createImm ( 0 ) ) ; if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI ; unsigned IgnoreCount = 0 ; for ( ++ MII ; MII != MBB -> end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) { if ( MII -> getOpcode ( ) == TargetOpcode :: DBG_VALUE || MII -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) ++ IgnoreCount ; else { HexagonLowerToMC ( MII , MCB , * this ) ; } } } else { HexagonLowerToMC ( MI , MCB , * this ) ; HexagonMCInstrInfo :: padEndloop ( MCB ) ; } SmallVector < DuplexCandidate , 8 > possibleDuplexes ; possibleDuplexes = HexagonMCInstrInfo :: getDuplexPossibilties ( * Subtarget -> getInstrInfo ( ) , MCB ) ; HexagonMCShuffle ( * Subtarget -> getInstrInfo ( ) , * Subtarget , OutStreamer -> getContext ( ) , MCB , possibleDuplexes ) ; EmitToStreamer ( * OutStreamer , MCB ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .

Hexagon Hexagon Hexagon::BUNDLE 0 0 Hexagon Hexagon Hexagon 8 Hexagon Hexagon


<s> static bool ck860_rtx_costs ( rtx x , int code , machine_mode mode , int outer_code ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case PLUS : if ( GET_CODE ( XEXP ( x , 0 ) ) == MULT && REG_P ( XEXP ( x , 1 ) ) && speed ) { rtx mul_op0 = XEXP ( XEXP ( x , 0 ) , 0 ) ; rtx mul_op1 = XEXP ( XEXP ( x , 0 ) , 1 ) ; if ( REG_P ( mul_op0 ) && REG_P ( mul_op1 ) ) { * total = COSTS_N_INSNS ( 1 ) ; * total += rtx_cost ( XEXP ( x , 0 ) , mode , ( enum rtx_code ) code , 0 , speed ) ; return true ; } } return false ; case MULT : if ( REG_P ( XEXP ( x , 0 ) ) && CONST_INT_P ( XEXP ( x , 1 ) ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , 1 ) ) ; if ( val % 2 == 0 && val < 0xffffffff && val > 0 ) { * total = COSTS_N_INSNS ( 1 ) ; return true ; } } return false ; case CONST : case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( 3 ) ; return true ; default : return false ; } } </s>

TARGET_RTX_COSTS helper for ck860 arches .


<s> int cr16_const_double_ok ( rtx op ) { if ( GET_MODE ( op ) == SFmode ) { long l ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; return UNSIGNED_INT_FITS_N_BITS ( l , 4 ) ? 1 : 0 ; } return ( ( UNSIGNED_INT_FITS_N_BITS ( CONST_DOUBLE_LOW ( op ) , 4 ) ) && ( UNSIGNED_INT_FITS_N_BITS ( CONST_DOUBLE_HIGH ( op ) , 4 ) ) ) ? 1 : 0 ; } </s>

Check if a const_double is ok for cr16 store-immediate instructions .


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCAssembler
&
Asm
,
const
MCFixup
&
Fixup
,
const
MCValue
&
Target
,
MutableArrayRef
<
char
>
Data
,
uint64_t
Value
,
bool
IsResolved
,
const
MCSubtargetInfo
*
STI
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
MCContext
&
Ctx
=
Asm
.
getContext
(
)
;
int64_t
SignedValue
=
static_cast
<
int64_t
>
(
Value
)
;
Value
=
adjustFixupValue
(
Fixup
,
Target
,
Value
,
Ctx
,
TheTriple
,
IsResolved
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
Data
.
size
(
)
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
Data
.
size
(
)
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
AArch64MCExpr
::
VariantKind
RefKind
=
static_cast
<
AArch64MCExpr
::
VariantKind
>
(
Target
.
getRefKind
(
)
)
;
if
(
AArch64MCExpr
::
getSymbolLoc
(
RefKind
)
==
AArch64MCExpr
::
VK_SABS
)
{
if
(
SignedValue
<
0
)
Data
[
Offset
+
3
]
&=
~
(
1
<<
6
)
;
else
Data
[
Offset
+
3
]
|=
(
1
<<
6
)
;
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> void AMDGPUTargetELFStreamer :: finish ( ) { std :: string Blob ; const char * Vendor = getPALMetadata ( ) -> getVendor ( ) ; unsigned Type = getPALMetadata ( ) -> getType ( ) ; getPALMetadata ( ) -> toBlob ( Type , Blob ) ; if ( Blob . empty ( ) ) return ; EmitNote ( Vendor , MCConstantExpr :: create ( Blob . size ( ) , getContext ( ) ) , Type , [ & ] ( MCELFStreamer & OS ) { OS . EmitBytes ( Blob ) ; } ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


<s> int m32c_expand_movstr ( rtx * operands ) { rtx desta , srca ; rtx desto , srco ; desta = XEXP ( operands [ 1 ] , 0 ) ; srca = XEXP ( operands [ 2 ] , 0 ) ; desto = gen_reg_rtx ( Pmode ) ; srco = gen_reg_rtx ( Pmode ) ; if ( GET_CODE ( desta ) != REG || REGNO ( desta ) < FIRST_PSEUDO_REGISTER ) desta = copy_to_mode_reg ( Pmode , desta ) ; if ( GET_CODE ( srca ) != REG || REGNO ( srca ) < FIRST_PSEUDO_REGISTER ) srca = copy_to_mode_reg ( Pmode , srca ) ; emit_insn ( gen_movstr_op ( desto , srco , desta , srca ) ) ; emit_insn ( gen_addpsi3 ( operands [ 0 ] , desto , GEN_INT ( - 1 ) ) ) ; return 1 ; } </s>

This is a stpcpy ( ) opcode . $ 0 is the destination ( MEM : BLK ) after the copy , which should point to the NUL at the end of the string , $ 1 is the destination ( MEM : BLK ) , and $ 2 is the source ( MEM : BLK ) . Since our opcode leaves the destination pointing * after * the NUL , we must emit an adjustment .


<s> bool AArch64PassConfig :: addILPOpts ( ) { if ( EnableCondOpt ) addPass ( createAArch64ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( createAArch64ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( createAArch64StorePairSuppressPass ( ) ) ; return true ; } </s>

Add passes that optimize instruction level parallelism for out-of-order targets .


<s> static rtx rx_function_value ( const_tree ret_type , const_tree fn_decl_or_type ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { machine_mode mode = TYPE_MODE ( ret_type ) ; if ( GET_MODE_SIZE ( mode ) > 0 && GET_MODE_SIZE ( mode ) < 4 && ! COMPLEX_MODE_P ( mode ) ) return gen_rtx_REG ( SImode , FUNC_RETURN_REGNUM ) ; return gen_rtx_REG ( mode , FUNC_RETURN_REGNUM ) ; } </s>

Return an RTL describing where a function return value of type RET_TYPE is held .


<s>
const
char
*
ix86_output_function_return
(
bool
long_p
)
{
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_keep
)
{
char
thunk_name
[
32
]
;
enum
indirect_thunk_prefix
need_prefix
=
indirect_thunk_need_prefix
(
current_output_insn
)
;
if
(
cfun
->
machine
->
function_return_type
!=
indirect_branch_thunk_inline
)
{
bool
need_thunk
=
(
cfun
->
machine
->
function_return_type
==
indirect_branch_thunk
)
;
indirect_thunk_name
(
thunk_name
,
INVALID_REGNUM
,
need_prefix
,
true
)
;
if
(
need_prefix
==
indirect_thunk_prefix_bnd
)
{
indirect_return_bnd_needed
|=
need_thunk
;
fprintf
(
asm_out_file
,
"\tbnd jmp\t%s\n"
,
thunk_name
)
;
}
else
{
indirect_return_needed
|=
need_thunk
;
fprintf
(
asm_out_file
,
"\tjmp\t%s\n"
,
thunk_name
)
;
}
}
else
output_indirect_thunk
(
need_prefix
,
INVALID_REGNUM
)
;
return
""
;
}
if
(
!
long_p
||
ix86_bnd_prefixed_insn_p
(
current_output_insn
)
)
return
"%!ret"
;
return
"rep%; ret"
;
}
</s>

Output function return . CALL_OP is the jump target . Add a REP prefix to RET if LONG_P is true and function return is kept .

i386
32
"\tbnd jmp\t%s\n"
"\tjmp\t%s\n"
""
"%!ret"
"rep%; ret"


<s> int ix86_attr_length_vex_default ( rtx_insn * insn , bool has_0f_opcode , bool has_vex_w ) { int i ; if ( ! has_0f_opcode || has_vex_w ) return 3 + 1 ; if ( ! TARGET_64BIT ) return 2 + 1 ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - 1 ; i >= 0 ; -- i ) if ( REG_P ( recog_data . operand [ i ] ) ) { if ( GET_MODE ( recog_data . operand [ i ] ) == DImode && GENERAL_REG_P ( recog_data . operand [ i ] ) ) return 3 + 1 ; } else { if ( MEM_P ( recog_data . operand [ i ] ) && x86_extended_reg_mentioned_p ( recog_data . operand [ i ] ) ) return 3 + 1 ; } return 2 + 1 ; } </s>

Compute default value for `` length_vex '' attribute . It includes 2 or 3 byte VEX prefix and 1 opcode byte .


<s> MVT IA64TargetLowering :: getSetCCResultType ( MVT VT ) const { return MVT :: i1 ; } </s>

Return the value type to use for ISD : :SETCC .


This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static struct machine_function * pru_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ; } </s>

Allocate a chunk of memory for per-function machine-dependent data .


<s>
Function
*
AMDGPUIntrinsicInfo
::
getDeclaration
(
Module
*
M
,
unsigned
IntrID
,
Type
*
*
Tys
,
unsigned
numTys
)
const
{
llvm_unreachable
(
"Not implemented"
)
;
}
</s>

Create or insert an LLVM Function declaration for an intrinsic , and return it .


<s> void xstormy16_expand_iorqi3 ( rtx * operands ) { rtx in , out , outsub , val ; out = operands [ 0 ] ; in = operands [ 1 ] ; val = operands [ 2 ] ; if ( xstormy16_onebit_set_operand ( val , QImode ) ) { if ( ! xstormy16_below100_or_register ( in , QImode ) ) in = copy_to_mode_reg ( QImode , in ) ; if ( ! xstormy16_below100_or_register ( out , QImode ) ) out = gen_reg_rtx ( QImode ) ; emit_insn ( gen_iorqi3_internal ( out , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; return ; } if ( GET_CODE ( in ) != REG ) in = copy_to_mode_reg ( QImode , in ) ; if ( GET_CODE ( val ) != REG && GET_CODE ( val ) != CONST_INT ) val = copy_to_mode_reg ( QImode , val ) ; if ( GET_CODE ( out ) != REG ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , 0 ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , 0 ) ; if ( GET_CODE ( val ) != CONST_INT ) val = simplify_gen_subreg ( HImode , val , QImode , 0 ) ; emit_insn ( gen_iorhi3 ( outsub , in , val ) ) ; if ( out != operands [ 0 ] ) emit_move_insn ( operands [ 0 ] , out ) ; } </s>

Expand an 8-bit IOR . This either detects the one case we can actually do , or uses a 16-bit IOR .


<s> static bool riscv_can_change_mode_class ( machine_mode , machine_mode , reg_class_t rclass ) { return ! reg_classes_intersect_p ( FP_REGS , rclass ) ; } </s>


<s> bool isReg ( ) const override { return isGPRAsmReg ( ) && RegIdx . Index == 0 ; } </s>


<s> const MCExpr * AMDGPUAsmPrinter :: lowerConstant ( const Constant * CV ) { if ( const MCExpr * E = lowerAddrSpaceCast ( TM , CV , OutContext ) ) return E ; return AsmPrinter :: lowerConstant ( CV ) ; } </s>

Lower the specified LLVM Constant to an MCExpr .


<s> Register CSKYInstrInfo :: getGlobalBaseReg ( MachineFunction & MF ) const { CSKYMachineFunctionInfo * CFI = MF . getInfo < CSKYMachineFunctionInfo > ( ) ; MachineConstantPool * MCP = MF . getConstantPool ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; Register GlobalBaseReg = CFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != 0 ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL ; CSKYConstantPoolValue * CPV = CSKYConstantPoolSymbol :: Create ( Type :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) , "_GLOBAL_OFFSET_TABLE_" , 0 , CSKYCP :: ADDR ) ; unsigned CPI = MCP -> getConstantPoolIndex ( CPV , Align ( 4 ) ) ; MachineMemOperand * MO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , 4 , Align ( 4 ) ) ; BuildMI ( FirstMBB , MBBI , DL , get ( CSKY :: LRW32 ) , CSKY :: R28 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( MO ) ; GlobalBaseReg = MRI . createVirtualRegister ( & CSKY :: GPRRegClass ) ; BuildMI ( FirstMBB , MBBI , DL , get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( CSKY :: R28 ) ; CFI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ; } </s>

getGlobalBaseReg - Return a virtual register initialized with the the global base register value .


<s> bool NVPTXPrologEpilogPass :: runOnMachineFunction ( MachineFunction & MF ) { const TargetMachine & TM = MF . getTarget ( ) ; const TargetFrameLowering & TFI = * TM . getFrameLowering ( ) ; const TargetRegisterInfo & TRI = * TM . getRegisterInfo ( ) ; bool Modified = false ; calculateFrameObjectOffsets ( MF ) ; for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) { for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) { MachineInstr * MI = I ; for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI -> getOperand ( i ) . isFI ( ) ) continue ; TRI . eliminateFrameIndex ( MI , 0 , i , NULL ) ; Modified = true ; } } } TFI . emitPrologue ( MF ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( ! I -> empty ( ) && I -> back ( ) . isReturn ( ) ) TFI . emitEpilogue ( MF , * I ) ; } return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> bool X86CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { if ( Val ) return false ; MIRBuilder . buildInstr ( X86 :: RET ) . addImm ( 0 ) ; return true ; } </s>

This hook behaves as the extended lowerReturn function , but for targets that do not support swifterror value promotion .


<s> void nds32_expand_prologue ( void ) { int fp_adjust ; int sp_adjust ; int en4_const ; rtx Rb , Re ; rtx fp_adjust_insn , sp_adjust_insn ; nds32_compute_stack_frame ( ) ; if ( cfun -> machine -> va_args_size != 0 ) { Rb = gen_rtx_REG ( SImode , cfun -> machine -> va_args_first_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> va_args_last_regno ) ; nds32_emit_stack_push_multiple ( Rb , Re , GEN_INT ( 0 ) , true ) ; if ( cfun -> machine -> va_args_area_padding_bytes ) { sp_adjust = cfun -> machine -> va_args_area_padding_bytes ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - 1 * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } } if ( cfun -> machine -> naked_p ) return ; Rb = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_first_gpr_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_last_gpr_regno ) ; en4_const = 0 ; if ( cfun -> machine -> fp_size ) en4_const += 8 ; if ( cfun -> machine -> gp_size ) en4_const += 4 ; if ( cfun -> machine -> lp_size ) en4_const += 2 ; if ( ! ( REGNO ( Rb ) == SP_REGNUM && REGNO ( Re ) == SP_REGNUM && en4_const == 0 ) ) { nds32_emit_stack_push_multiple ( Rb , Re , GEN_INT ( en4_const ) , false ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; fp_adjust_insn = gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( fp_adjust ) ) ; fp_adjust_insn = emit_insn ( fp_adjust_insn ) ; RTX_FRAME_RELATED_P ( fp_adjust_insn ) = 1 ; } sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; sp_adjust = nds32_force_addi_stack_int ( ( - 1 ) * sp_adjust ) ; if ( sp_adjust ) { sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - 1 * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = 1 ; } emit_insn ( gen_blockage ( ) ) ; } </s>

Function for normal multiple push prologue .


<s> MCGNode * getNode ( const MachineFunction * MF ) const { for ( MCGNodes :: const_iterator i ( MCG . getNodes ( ) . begin ( ) ) , ie ( MCG . getNodes ( ) . end ( ) ) ; i != ie ; i ++ ) { if ( ( * i ) -> getMF ( ) == MF ) return * i ; } return NULL ; } </s>


<s> void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> inline bool mips_lo_sum_offset_hasher :: equal ( const value_type * entry , const compare_type * value ) { return rtx_equal_p ( entry -> base , value ) ; } </s>


<s> static rtx_insn * emit_new_cond_insn ( rtx_insn * insn , int cond ) { rtx c_insn = 0 ; rtx pat , dst , src ; cond_type num ; if ( ( num = is_cond_candidate ( insn ) ) == COND_NO ) return NULL ; pat = PATTERN ( insn ) ; if ( NONJUMP_INSN_P ( insn ) ) { dst = SET_DEST ( pat ) ; src = SET_SRC ( pat ) ; } else { dst = JUMP_LABEL ( insn ) ; src = NULL_RTX ; } switch ( num ) { case COND_MOV_INSN : case COND_CLR_INSN : if ( cond ) c_insn = gen_movt0 ( dst , src , dst ) ; else c_insn = gen_movt0 ( dst , dst , src ) ; break ; case COND_INC_INSN : if ( cond ) c_insn = gen_incscc ( dst , dst ) ; else c_insn = gen_incscc_false ( dst , dst ) ; break ; case COND_DEC_INSN : if ( cond ) c_insn = gen_decscc ( dst , dst ) ; else c_insn = gen_decscc_false ( dst , dst ) ; break ; case COND_BRANCH_INSN : if ( cond ) c_insn = gen_branch_true ( dst ) ; else c_insn = gen_branch_false ( dst ) ; break ; default : return NULL ; } if ( rtx_length [ GET_CODE ( c_insn ) ] >= 7 && rtx_length [ GET_CODE ( insn ) ] >= 7 ) { REG_NOTES ( c_insn ) = REG_NOTES ( insn ) ; } if ( num == COND_BRANCH_INSN ) { c_insn = emit_jump_insn_before ( c_insn , insn ) ; ++ LABEL_NUSES ( dst ) ; JUMP_LABEL ( c_insn ) = dst ; } else c_insn = emit_insn_after ( c_insn , insn ) ; delete_insn ( insn ) ; return as_a < rtx_insn * > ( c_insn ) ; } </s>

Emit a conditional version of insn and replace the old insn with the new one . Return the new insn if emitted .


"Convert LLVM vector types to their element types"

getPassName - Return a nice clean name for a pass .


<s> Register BPFRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return BPF :: R10 ; } </s>


<s> SDValue Z80TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; Z80MachineFunctionInfo * FuncInfo = MF . getInfo < Z80MachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , getCCAssignFn ( CallConv ) ) ; if ( MFI . hasVAStart ( ) ) FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( 1 , CCInfo . getNextStackOffset ( ) , true ) ) ; SDValue ArgValue ; for ( unsigned I = 0 , E = ArgLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = ArgLocs [ I ] ; int FI = MFI . CreateFixedObject ( VA . getLocVT ( ) . getStoreSize ( ) , VA . getLocMemOffset ( ) , true ) ; SDValue Val = DAG . getLoad ( VA . getLocInfo ( ) == CCValAssign :: AExt ? VA . getValVT ( ) : VA . getLocVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { MFI . setObjectZExt ( FI , true ) ; Val = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { MFI . setObjectSExt ( FI , true ) ; Val = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; } InVals . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s> bool apply_tail_policy_p ( ) const override { return false ; } </s>

We choose to apply tail policy operand by default since most of the intrinsics has tail policy operand .


<s>
void
XCoreFrameLowering
::
emitEpilogue
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
)
const
{
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
MachineBasicBlock
::
iterator
MBBI
=
MBB
.
getLastNonDebugInstr
(
)
;
const
XCoreInstrInfo
&
TII
=
*
static_cast
<
const
XCoreInstrInfo
*
>
(
MF
.
getTarget
(
)
.
getInstrInfo
(
)
)
;
XCoreFunctionInfo
*
XFI
=
MF
.
getInfo
<
XCoreFunctionInfo
>
(
)
;
DebugLoc
dl
=
MBBI
->
getDebugLoc
(
)
;
bool
FP
=
hasFP
(
MF
)
;
if
(
FP
)
{
unsigned
FramePtr
=
XCore
::
R10
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
XCore
::
SETSP_1r
)
)
.
addReg
(
FramePtr
)
;
}
int
FrameSize
=
MFI
->
getStackSize
(
)
;
assert
(
FrameSize
%
4
==
0
&&
"Misaligned frame size"
)
;
FrameSize
/=
4
;
bool
isU6
=
isImmU6
(
FrameSize
)
;
if
(
!
isU6
&&
!
isImmU16
(
FrameSize
)
)
{
report_fatal_error
(
"emitEpilogue Frame size too big: "
+
Twine
(
FrameSize
)
)
;
}
if
(
FP
)
{
int
FPSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getFPSpillSlot
(
)
)
;
FPSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
R10
,
FPSpillOffset
,
dl
,
TII
)
;
}
bool
restoreLR
=
XFI
->
getUsesLR
(
)
;
if
(
restoreLR
&&
(
FrameSize
==
0
||
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
!=
0
)
)
{
int
LRSpillOffset
=
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
;
LRSpillOffset
+=
FrameSize
*
4
;
loadFromStack
(
MBB
,
MBBI
,
XCore
::
LR
,
LRSpillOffset
,
dl
,
TII
)
;
restoreLR
=
false
;
}
if
(
FrameSize
)
{
if
(
restoreLR
)
{
assert
(
MFI
->
getObjectOffset
(
XFI
->
getLRSpillSlot
(
)
)
==
0
)
;
assert
(
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_u6
||
MBBI
->
getOpcode
(
)
==
XCore
::
RETSP_lu6
)
;
int
Opcode
=
(
isU6
)
XCore
::
RETSP_u6
:
XCore
::
RETSP_lu6
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
)
.
addImm
(
FrameSize
)
;
MBB
.
erase
(
MBBI
)
;
}
else
{
int
Opcode
=
(
isU6
)
XCore
::
LDAWSP_ru6
:
XCore
::
LDAWSP_lru6
;
BuildMI
(
MBB
,
MBBI
,
dl
,
TII
.
get
(
Opcode
)
,
XCore
::
SP
)
.
addImm
(
FrameSize
)
;
}
}
}
</s>


<s> static tree gen_stdcall_or_fastcall_decoration ( tree decl , char prefix ) { unsigned total = 0 ; const char * asmname = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ; char * newsym ; tree formal_type = TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ; if ( formal_type != NULL_TREE ) { if ( TREE_VALUE ( tree_last ( formal_type ) ) != void_type_node ) return NULL_TREE ; while ( TREE_VALUE ( formal_type ) != void_type_node && COMPLETE_TYPE_P ( TREE_VALUE ( formal_type ) ) ) { unsigned parm_size = TREE_INT_CST_LOW ( TYPE_SIZE ( TREE_VALUE ( formal_type ) ) ) ; parm_size = ( ( parm_size + PARM_BOUNDARY - 1 ) / PARM_BOUNDARY * PARM_BOUNDARY ) ; total += parm_size ; formal_type = TREE_CHAIN ( formal_type ) ; } } newsym = alloca ( 1 + strlen ( asmname ) + 1 + 10 + 1 ) ; return get_identifier_with_length ( newsym , sprintf ( newsym , "%c%s@%u" , prefix , asmname , total / BITS_PER_UNIT ) ) ; } </s>

Return string which is the former assembler name modified with an underscore prefix and a suffix consisting of an atsign ( @ ) followed by the number of bytes of arguments


<s> static int comparator ( const void * va , const void * vb ) { const char * a = * ( const char * const * ) va ; const char * b = * ( const char * const * ) vb ; while ( * a && * b ) { if ( ISALPHA ( * a ) && ISDIGIT ( * b ) ) return - 1 ; if ( ISDIGIT ( * a ) && ISALPHA ( * b ) ) return 1 ; if ( * a != * b ) return * a - * b ; a ++ ; b ++ ; } return * a - * b ; } </s>

Compare two MCUs and order them for easy lookup .


<s> static reg_class_t arc_secondary_reload ( bool in_p , rtx x , reg_class_t cl , machine_mode mode , secondary_reload_info * sri ) { enum rtx_code code = GET_CODE ( x ) ; if ( cl == DOUBLE_REGS ) return GENERAL_REGS ; if ( code == SUBREG ) { rtx addr = NULL_RTX ; x = SUBREG_REG ( x ) ; if ( REG_P ( x ) ) { int regno = REGNO ( x ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) regno = reg_renumber [ regno ] ; if ( regno != - 1 ) return NO_REGS ; if ( ! lra_in_progress && reg_equiv_mem ( REGNO ( x ) ) ) { rtx mem = reg_equiv_mem ( REGNO ( x ) ) ; addr = find_replacement ( & XEXP ( mem , 0 ) ) ; } } else { gcc_assert ( MEM_P ( x ) ) ; addr = XEXP ( x , 0 ) ; addr = simplify_rtx ( addr ) ; } if ( addr && GET_CODE ( addr ) == PLUS && CONST_INT_P ( XEXP ( addr , 1 ) ) && ( ! RTX_OK_FOR_OFFSET_P ( mode , XEXP ( addr , 1 ) ) ) ) { switch ( mode ) { case E_QImode : sri -> icode = in_p ? CODE_FOR_reload_qi_load : CODE_FOR_reload_qi_store ; break ; case E_HImode : sri -> icode = in_p ? CODE_FOR_reload_hi_load : CODE_FOR_reload_hi_store ; break ; default : break ; } } } return NO_REGS ; } </s>

For ARC base register + offset addressing , the validity of the address is mode-dependent for most of the offset range , as the offset can be scaled by the access size . We do n't expose these as mode-dependent addresses in the mode_dependent_address_p target hook , because that would disable lots of optimizations , and most uses of these addresses are for 32 or 64 bit accesses anyways , which are fine . However , that leaves some addresses for 8 / 16 bit values not properly reloaded by the generic code , which is why we have to schedule secondary reloads for these .


<s> unsigned getNumFixupKinds ( ) const override { return Lanai :: NumTargetFixupKinds ; } </s>

Get the number of target specific fixup kinds .


<s> bool FISCRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { return false ; } </s>

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot .


<s> static int rs6000_reassociation_width ( unsigned int opc ATTRIBUTE_UNUSED , machine_mode mode ) { switch ( rs6000_tune ) { case PROCESSOR_POWER8 : case PROCESSOR_POWER9 : case PROCESSOR_POWER10 : if ( DECIMAL_FLOAT_MODE_P ( mode ) ) return 1 ; if ( VECTOR_MODE_P ( mode ) ) return 4 ; if ( INTEGRAL_MODE_P ( mode ) ) return 1 ; if ( FLOAT_MODE_P ( mode ) ) return 4 ; break ; default : break ; } return 1 ; } </s>

Determine the reassociation width to be used in reassociate_bb . This takes into account how many parallel operations we can actually do of a given type , and also the latency . P8 : int add/sub 6/cycle mul 2/cycle vect add/sub/mul 2/cycle fp add/sub/mul 2/cycle dfp 1/cycle


<s> bool J2FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = 0 , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( J2 :: MOV32mrpop ) , CSI [ i ] . getReg ( ) ) . addReg ( J2 :: R15 ) ; return true ; } </s>

restoreCalleeSavedRegisters - Issues instruction ( s ) to restore all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of load instructions via loadRegToStackSlot ( ) .


<s> static int first_altivec_reg_to_save ( void ) { int i ; if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + 1 ; if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) return FIRST_ALTIVEC_REGNO + 20 ; for ( i = FIRST_ALTIVEC_REGNO + 20 ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( save_reg_p ( i ) ) break ; return i ; } </s>


<s> bool ARMSubtarget :: enableAtomicExpand ( ) const { return hasAnyDataBarrier ( ) ; } </s>

True if the subtarget should run the atomic expansion pass .


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { AArch64MachineFunctionInfo * MFI = MF . getInfo < AArch64MachineFunctionInfo > ( ) ; if ( MFI -> getNumLocalDynamicTLSAccesses ( ) < 2 ) { return false ; } MachineDominatorTree * DT = & getAnalysis < MachineDominatorTree > ( ) ; return VisitNode ( DT -> getRootNode ( ) , 0 ) ; } </s>


<s>
static
char
*
describe_cache
(
unsigned
l1_sizekb
,
unsigned
l1_line
,
unsigned
l1_assoc
ATTRIBUTE_UNUSED
,
unsigned
l2_sizekb
)
{
char
l1size
[
1000
]
,
line
[
1000
]
,
l2size
[
1000
]
;
sprintf
(
l1size
,
"--param l1-cache-size=%u"
,
l1_sizekb
)
;
sprintf
(
line
,
"--param l1-cache-line-size=%u"
,
l1_line
)
;
sprintf
(
l2size
,
"--param l2-cache-size=%u"
,
l2_sizekb
)
;
return
concat
(
l1size
,
" "
,
line
,
" "
,
l2size
,
" "
,
)
;
}
</s>

Returns parameters that describe L1_ASSOC associative cache of size L1_SIZEKB with lines of size L1_LINE , and L2_SIZEKB .


<s> static void mips_multi_set_operand ( unsigned int i , unsigned int op , rtx x ) { mips_multi_members [ i ] . operands [ op ] = x ; } </s>

Change the operand of an existing instruction in the current multi-insn sequence . I is the index of the instruction , OP is the index of the operand , and X is the new value .


<s> poly_int64 m32c_push_rounding ( poly_int64 n ) { if ( TARGET_R8C || TARGET_M16C ) return n ; return ( n + 1 ) & ~ 1 ; } </s>

Implements PUSH_ROUNDING . The R8C and M16C have byte stacks , the M32C has word stacks .


<s> static rtx sparc_builtin_saveregs ( void ) { int first_reg = current_function_args_info . words ; rtx address ; int regno ; for ( regno = first_reg ; regno < SPARC_INT_ARG_MAX ; regno ++ ) emit_move_insn ( gen_rtx_MEM ( word_mode , gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( 0 ) + ( UNITS_PER_WORD * regno ) ) ) ) , gen_rtx_REG ( word_mode , SPARC_INCOMING_INT_ARG_FIRST + regno ) ) ; address = gen_rtx_PLUS ( Pmode , frame_pointer_rtx , GEN_INT ( FIRST_PARM_OFFSET ( 0 ) + UNITS_PER_WORD * first_reg ) ) ; return address ; } </s>

Do what is necessary for ` va_start ' . We look at the current function to determine if stdarg or varargs is used and return the address of the first unnamed parameter .


<s> TargetLoweringBase :: LegalizeTypeAction AArch64TargetLowering :: getPreferredVectorAction ( EVT VT ) const { MVT SVT = VT . getSimpleVT ( ) ; if ( SVT == MVT :: v1i8 || SVT == MVT :: v1i16 || SVT == MVT :: v1i32 || SVT == MVT :: v1f32 ) return TypeWidenVector ; if ( VT . isScalableVector ( ) && ( VT . getVectorNumElements ( ) == 1 ) ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ; } </s>

Customize the preferred legalization strategy for certain types .


<s> static bool isUnconditionalBranch ( const MachineInstr & MI ) { if ( MI . getOpcode ( ) == TPC :: JMPR_u ) return true ; return ( MI . getOpcode ( ) == TPC :: JMPR || MI . getOpcode ( ) == TPC :: JMPA ) && MI . getOperand ( 1 ) . getReg ( ) == TPC :: SP0 && MI . getOperand ( 2 ) . getImm ( ) == 0 ; } </s>

Return true if this is a branch which always transfers control flow to some other block .


<s>
void
AMDGPUAsmPrinter
::
emitEndOfAsmFile
(
Module
&
M
)
{
if
(
!
getTargetStreamer
(
)
)
return
;
if
(
!
IsaInfo
::
hasCodeObjectV3
(
getGlobalSTI
(
)
)
)
{
std
::
string
ISAVersionString
;
raw_string_ostream
ISAVersionStream
(
ISAVersionString
)
;
IsaInfo
::
streamIsaVersion
(
getGlobalSTI
(
)
,
ISAVersionStream
)
;
getTargetStreamer
(
)
->
EmitISAVersion
(
ISAVersionStream
.
str
(
)
)
;
}
if
(
TM
.
getTargetTriple
(
)
.
getOS
(
)
==
Triple
::
AMDHSA
)
{
HSAMetadataStream
->
end
(
)
;
bool
Success
=
HSAMetadataStream
->
emitTo
(
*
getTargetStreamer
(
)
)
;
(
void
)
Success
;
assert
(
Success
&&
"Malformed HSA Metadata"
)
;
}
}
</s>

This virtual method can be overridden by targets that want to emit something at the end of their file .


<s> static rtx rs6000_complex_function_value ( machine_mode mode ) { unsigned int regno ; rtx r1 , r2 ; machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int inner_bytes = GET_MODE_UNIT_SIZE ( mode ) ; if ( TARGET_FLOAT128_TYPE && ( mode == KCmode || ( mode == TCmode && TARGET_IEEEQUAD ) ) ) regno = ALTIVEC_ARG_RETURN ; else if ( FLOAT_MODE_P ( mode ) && TARGET_HARD_FLOAT && TARGET_FPRS ) regno = FP_ARG_RETURN ; else { regno = GP_ARG_RETURN ; if ( TARGET_32BIT && inner_bytes >= 4 ) return gen_rtx_REG ( mode , regno ) ; } if ( inner_bytes >= 8 ) return gen_rtx_REG ( mode , regno ) ; r1 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno ) , const0_rtx ) ; r2 = gen_rtx_EXPR_LIST ( inner , gen_rtx_REG ( inner , regno + 1 ) , GEN_INT ( inner_bytes ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( 2 , r1 , r2 ) ) ; } </s>

Return an RTX representing where to find the function value of a function returning MODE .


<s> static tree pru_builtin_decl ( unsigned code , bool initialize_p ATTRIBUTE_UNUSED ) { switch ( code ) { case PRU_BUILTIN_DELAY_CYCLES : case PRU_BUILTIN_HALT : case PRU_BUILTIN_LMBD : return pru_builtins [ code ] ; default : return error_mark_node ; } } </s>


<s> bool SIPostRABundler :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; TRI = MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) ; bool Changed = false ; const unsigned MemFlags = SIInstrFlags :: MTBUF | SIInstrFlags :: MUBUF | SIInstrFlags :: SMRD | SIInstrFlags :: DS | SIInstrFlags :: FLAT | SIInstrFlags :: MIMG ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: instr_iterator Next ; MachineBasicBlock :: instr_iterator B = MBB . instr_begin ( ) ; MachineBasicBlock :: instr_iterator E = MBB . instr_end ( ) ; for ( auto I = B ; I != E ; I = Next ) { Next = std :: next ( I ) ; if ( I -> isBundled ( ) || ! I -> mayLoadOrStore ( ) || B -> mayLoad ( ) != I -> mayLoad ( ) || B -> mayStore ( ) != I -> mayStore ( ) || ( B -> getDesc ( ) . TSFlags & MemFlags ) != ( I -> getDesc ( ) . TSFlags & MemFlags ) || isDependentLoad ( * I ) ) { if ( B != I ) { if ( std :: next ( B ) != I ) { finalizeBundle ( MBB , B , I ) ; Changed = true ; } Next = I ; } B = Next ; Defs . clear ( ) ; continue ; } if ( I -> getNumExplicitDefs ( ) == 0 ) continue ; Defs . insert ( I -> defs ( ) . begin ( ) -> getReg ( ) ) ; } if ( B != E && std :: next ( B ) != E ) { finalizeBundle ( MBB , B , E ) ; Changed = true ; } Defs . clear ( ) ; } return Changed ; } </s>

runOnMachineFunction - Emit the function body .

AMDGPU SI SIInstrFlags::MTBUF SIInstrFlags::MUBUF SIInstrFlags::SMRD SIInstrFlags::DS SIInstrFlags::FLAT SIInstrFlags::MIMG 0


"-mshared-library-id=%s is not between 0 and %d"


<s> static int rs6000_builtin_vectorization_cost ( enum vect_cost_for_stmt type_of_cost , tree vectype , int misalign ) { unsigned elements ; tree elem_type ; switch ( type_of_cost ) { case scalar_stmt : case scalar_load : case scalar_store : case vector_stmt : case vector_load : case vector_store : case vec_to_scalar : case scalar_to_vec : case cond_branch_not_taken : return 1 ; case vec_perm : if ( TARGET_VSX ) return 3 ; else return 1 ; case vec_promote_demote : if ( TARGET_VSX ) return 4 ; else return 1 ; case cond_branch_taken : return 3 ; case unaligned_load : case vector_gather_load : if ( TARGET_P9_VECTOR ) return 3 ; if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 22 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case unaligned_store : case vector_scatter_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return 1 ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == 2 ) return 2 ; if ( elements == 4 ) { switch ( misalign ) { case 8 : return 2 ; case - 1 : case 4 : case 12 : return 23 ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return 2 ; case vec_construct : elem_type = TREE_TYPE ( vectype ) ; if ( SCALAR_FLOAT_TYPE_P ( elem_type ) && TYPE_PRECISION ( elem_type ) == 32 ) return 5 ; else if ( INTEGRAL_TYPE_P ( elem_type ) ) { if ( TARGET_P9_VECTOR ) return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 2 ; else return TYPE_VECTOR_SUBPARTS ( vectype ) - 1 + 11 ; } else return 2 ; default : gcc_unreachable ( ) ; } } </s>


<s> RCPair ARMTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: tGPRRegClass ) ; return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( 0U , & ARM :: hGPRRegClass ) ; break ; case 'r' : return RCPair ( 0U , & ARM :: GPRRegClass ) ; case 'w' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPRRegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPRRegClass ) ; break ; case 'x' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 64 ) return RCPair ( 0U , & ARM :: DPR_8RegClass ) ; if ( VT . getSizeInBits ( ) == 128 ) return RCPair ( 0U , & ARM :: QPR_8RegClass ) ; break ; case 't' : if ( VT == MVT :: f32 ) return RCPair ( 0U , & ARM :: SPRRegClass ) ; break ; } } if ( StringRef ( "{cc}" ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( ARM :: CPSR ) , & ARM :: CCRRegClass ) ; return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


"Can only insert epilog into returning blocks"


<s> bool doInitialization ( CallGraph & CG ) override { CallGraphResourceInfo . clear ( ) ; return CallGraphSCCPass :: doInitialization ( CG ) ; } </s>

Set up the AsmPrinter when we are working on a new module .


<s> static bool aarch64_fold_builtin_lane_check ( tree arg0 , tree arg1 , tree arg2 ) { if ( TREE_CODE ( arg0 ) != INTEGER_CST ) return false ; if ( TREE_CODE ( arg1 ) != INTEGER_CST ) return false ; if ( TREE_CODE ( arg2 ) != INTEGER_CST ) return false ; auto totalsize = wi :: to_widest ( arg0 ) ; auto elementsize = wi :: to_widest ( arg1 ) ; if ( totalsize == 0 || elementsize == 0 ) return false ; auto lane = wi :: to_widest ( arg2 ) ; auto high = wi :: udiv_trunc ( totalsize , elementsize ) ; return wi :: ltu_p ( lane , high ) ; } </s>

Return true if the lane check can be removed as there is no error going to be emitted .


<s>
void
SIInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
MI
,
Register
DestReg
,
int
FrameIndex
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
MachineFunction
*
MF
=
MBB
.
getParent
(
)
;
SIMachineFunctionInfo
*
MFI
=
MF
->
getInfo
<
SIMachineFunctionInfo
>
(
)
;
MachineFrameInfo
&
FrameInfo
=
MF
->
getFrameInfo
(
)
;
const
DebugLoc
&
DL
=
MBB
.
findDebugLoc
(
MI
)
;
unsigned
SpillSize
=
TRI
->
getSpillSize
(
*
RC
)
;
MachinePointerInfo
PtrInfo
=
MachinePointerInfo
::
getFixedStack
(
*
MF
,
FrameIndex
)
;
MachineMemOperand
*
MMO
=
MF
->
getMachineMemOperand
(
PtrInfo
,
MachineMemOperand
::
MOLoad
,
FrameInfo
.
getObjectSize
(
FrameIndex
)
,
FrameInfo
.
getObjectAlign
(
FrameIndex
)
)
;
if
(
RI
.
isSGPRClass
(
RC
)
)
{
MFI
->
setHasSpilledSGPRs
(
)
;
assert
(
DestReg
!=
AMDGPU
::
M0
&&
"m0 should not be reloaded into"
)
;
assert
(
DestReg
!=
AMDGPU
::
EXEC_LO
&&
DestReg
!=
AMDGPU
::
EXEC_HI
&&
DestReg
!=
AMDGPU
::
EXEC
&&
"exec should not be spilled"
)
;
const
MCInstrDesc
&
OpDesc
=
get
(
getSGPRSpillRestoreOpcode
(
SpillSize
)
)
;
if
(
DestReg
.
isVirtual
(
)
&&
SpillSize
==
4
)
{
MachineRegisterInfo
&
MRI
=
MF
->
getRegInfo
(
)
;
MRI
.
constrainRegClass
(
DestReg
,
&
AMDGPU
::
SReg_32_XM0_XEXECRegClass
)
;
}
if
(
RI
.
spillSGPRToVGPR
(
)
)
FrameInfo
.
setStackID
(
FrameIndex
,
TargetStackID
::
SGPRSpill
)
;
BuildMI
(
MBB
,
MI
,
DL
,
OpDesc
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addMemOperand
(
MMO
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
,
RegState
::
Implicit
)
;
return
;
}
unsigned
Opcode
=
RI
.
hasAGPRs
(
RC
)
getAGPRSpillRestoreOpcode
(
SpillSize
)
:
getVGPRSpillRestoreOpcode
(
SpillSize
)
;
BuildMI
(
MBB
,
MI
,
DL
,
get
(
Opcode
)
,
DestReg
)
.
addFrameIndex
(
FrameIndex
)
.
addReg
(
MFI
->
getStackPtrOffsetReg
(
)
)
.
addImm
(
0
)
.
addMemOperand
(
MMO
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s> MCSymbol * X86AsmPrinter :: GetCPISymbol ( unsigned CPID ) const { if ( Subtarget -> isTargetKnownWindowsMSVC ( ) ) { const MachineConstantPoolEntry & CPE = MF -> getConstantPool ( ) -> getConstants ( ) [ CPID ] ; if ( ! CPE . isMachineConstantPoolEntry ( ) ) { const DataLayout & DL = MF -> getDataLayout ( ) ; SectionKind Kind = CPE . getSectionKind ( & DL ) ; const Constant * C = CPE . Val . ConstVal ; unsigned Align = CPE . Alignment ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( DL , Kind , C , Align ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } } } return AsmPrinter :: GetCPISymbol ( CPID ) ; } </s>

Return the symbol for the specified constant pool entry .


<s> void AMDGPUPassConfig :: addIRPasses ( ) { addPass ( createAMDGPUAlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; TargetPassConfig :: addIRPasses ( ) ; } </s>

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization .


<s>
StringRef
getPassName
(
)
const
override
{
return
"Hexagon Common GEP"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> void riscv_cpu_cpp_builtins ( cpp_reader * pfile ) { builtin_define ( "__riscv" ) ; if ( TARGET_RVC ) builtin_define ( "__riscv_compressed" ) ; if ( TARGET_RVE ) builtin_define ( "__riscv_32e" ) ; if ( TARGET_ATOMIC ) builtin_define ( "__riscv_atomic" ) ; if ( TARGET_MUL ) builtin_define ( "__riscv_mul" ) ; if ( TARGET_DIV ) builtin_define ( "__riscv_div" ) ; if ( TARGET_DIV && TARGET_MUL ) builtin_define ( "__riscv_muldiv" ) ; builtin_define_with_int_value ( "__riscv_xlen" , UNITS_PER_WORD * 8 ) ; if ( TARGET_HARD_FLOAT ) builtin_define_with_int_value ( "__riscv_flen" , UNITS_PER_FP_REG * 8 ) ; if ( ( TARGET_HARD_FLOAT || TARGET_ZFINX ) && TARGET_FDIV ) { builtin_define ( "__riscv_fdiv" ) ; builtin_define ( "__riscv_fsqrt" ) ; } switch ( riscv_abi ) { case ABI_ILP32E : builtin_define ( "__riscv_abi_rve" ) ; gcc_fallthrough ( ) ; case ABI_ILP32 : case ABI_LP64 : builtin_define ( "__riscv_float_abi_soft" ) ; break ; case ABI_ILP32F : case ABI_LP64F : builtin_define ( "__riscv_float_abi_single" ) ; break ; case ABI_ILP32D : case ABI_LP64D : builtin_define ( "__riscv_float_abi_double" ) ; break ; } switch ( riscv_cmodel ) { case CM_MEDLOW : builtin_define ( "__riscv_cmodel_medlow" ) ; break ; case CM_PIC : case CM_MEDANY : builtin_define ( "__riscv_cmodel_medany" ) ; break ; } if ( TARGET_MIN_VLEN != 0 ) builtin_define_with_int_value ( "__riscv_v_min_vlen" , TARGET_MIN_VLEN ) ; if ( TARGET_VECTOR_ELEN_64 ) builtin_define_with_int_value ( "__riscv_v_elen" , 64 ) ; else if ( TARGET_VECTOR_ELEN_32 ) builtin_define_with_int_value ( "__riscv_v_elen" , 32 ) ; if ( TARGET_VECTOR_ELEN_FP_64 ) builtin_define_with_int_value ( "__riscv_v_elen_fp" , 64 ) ; else if ( TARGET_VECTOR_ELEN_FP_32 ) builtin_define_with_int_value ( "__riscv_v_elen_fp" , 32 ) ; else if ( TARGET_MIN_VLEN != 0 ) builtin_define_with_int_value ( "__riscv_v_elen_fp" , 0 ) ; if ( TARGET_MIN_VLEN ) { builtin_define ( "__riscv_vector" ) ; builtin_define_with_int_value ( "__riscv_v_intrinsic" , riscv_ext_version_value ( 0 , 11 ) ) ; } builtin_define_with_int_value ( "__riscv_arch_test" , 1 ) ; const riscv_subset_list * subset_list = riscv_current_subset_list ( ) ; if ( ! subset_list ) return ; size_t max_ext_len = 0 ; for ( const riscv_subset_t * subset = subset_list -> begin ( ) ; subset != subset_list -> end ( ) ; subset = subset -> next ) max_ext_len = MAX ( max_ext_len , subset -> name . length ( ) ) ; char * buf = ( char * ) alloca ( max_ext_len + 10 ) ; for ( const riscv_subset_t * subset = subset_list -> begin ( ) ; subset != subset_list -> end ( ) ; subset = subset -> next ) { int version_value = riscv_ext_version_value ( subset -> major_version , subset -> minor_version ) ; if ( ( subset -> name == "zicsr" || subset -> name == "zifencei" ) && version_value == 0 ) version_value = riscv_ext_version_value ( 2 , 0 ) ; sprintf ( buf , "__riscv_%s" , subset -> name . c_str ( ) ) ; builtin_define_with_int_value ( buf , version_value ) ; } } </s>


<s> LoadInst * X86TargetLowering :: lowerIdempotentRMWIntoFencedLoad ( AtomicRMWInst * AI ) const { unsigned NativeWidth = Subtarget . is64Bit ( ) ? 64 : 32 ; Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SSID = AI -> getSyncScopeID ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; if ( SSID == SyncScope :: SingleThread ) return nullptr ; if ( ! Subtarget . hasMFence ( ) ) return nullptr ; Function * MFence = llvm :: Intrinsic :: getDeclaration ( M , Intrinsic :: x86_sse2_mfence ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( AI -> getType ( ) , AI -> getPointerOperand ( ) , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ; Loaded -> setAtomic ( Order , SSID ) ; AI -> replaceAllUsesWith ( Loaded ) ; AI -> eraseFromParent ( ) ; return Loaded ; } </s>

On some platforms , an AtomicRMW that never actually modifies the value ( such as fetch_add of 0 ) can be turned into a fence followed by an atomic load .


<s> void MipsSEFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MipsFunctionInfo * MipsFI = MF . getInfo < MipsFunctionInfo > ( ) ; const MipsSEInstrInfo & TII = * static_cast < const MipsSEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const MipsRegisterInfo & RegInfo = * static_cast < const MipsRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; MipsABIInfo ABI = STI . getABI ( ) ; unsigned SP = ABI . GetStackPtr ( ) ; unsigned FP = ABI . GetFramePtr ( ) ; unsigned ZERO = ABI . GetNullPtr ( ) ; unsigned MOVE = ABI . GetGPRMoveOp ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; BuildMI ( MBB , I , DL , TII . get ( MOVE ) , SP ) . addReg ( FP ) . addReg ( ZERO ) ; } if ( MipsFI -> callsEhReturn ( ) ) { const TargetRegisterClass * RC = ABI . ArePtrs64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ; MachineBasicBlock :: iterator I = MBBI ; for ( unsigned i = 0 ; i < MFI . getCalleeSavedInfo ( ) . size ( ) ; ++ i ) -- I ; for ( int J = 0 ; J < 4 ; ++ J ) { TII . loadRegFromStackSlot ( MBB , I , ABI . GetEhDataReg ( J ) , MipsFI -> getEhDataRegFI ( J ) , RC , & RegInfo ) ; } } if ( MF . getFunction ( ) -> hasFnAttribute ( "interrupt" ) ) emitInterruptEpilogueStub ( MF , MBB ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( ! StackSize ) return ; TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ; } </s>

Mips Mips Mips Mips Mips Mips Mips Mips Mips Mips 0 Mips Mips::GPR64RegClass Mips::GPR32RegClass 0 0 4 Mips "interrupt"


<s>
MachineBasicBlock
*
MSP430TargetLowering
::
EmitInstrWithCustomInserter
(
MachineInstr
&
MI
,
MachineBasicBlock
*
BB
)
const
{
unsigned
Opc
=
MI
.
getOpcode
(
)
;
if
(
Opc
==
MSP430
::
Shl8
||
Opc
==
MSP430
::
Shl16
||
Opc
==
MSP430
::
Sra8
||
Opc
==
MSP430
::
Sra16
||
Opc
==
MSP430
::
Srl8
||
Opc
==
MSP430
::
Srl16
)
return
EmitShiftInstr
(
MI
,
BB
)
;
const
TargetInstrInfo
&
TII
=
*
BB
->
getParent
(
)
->
getSubtarget
(
)
.
getInstrInfo
(
)
;
DebugLoc
dl
=
MI
.
getDebugLoc
(
)
;
assert
(
(
Opc
==
MSP430
::
Select16
||
Opc
==
MSP430
::
Select8
)
&&
"Unexpected instr type to insert"
)
;
const
BasicBlock
*
LLVM_BB
=
BB
->
getBasicBlock
(
)
;
MachineFunction
::
iterator
I
=
++
BB
->
getIterator
(
)
;
MachineBasicBlock
*
thisMBB
=
BB
;
MachineFunction
*
F
=
BB
->
getParent
(
)
;
MachineBasicBlock
*
copy0MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
MachineBasicBlock
*
copy1MBB
=
F
->
CreateMachineBasicBlock
(
LLVM_BB
)
;
F
->
insert
(
I
,
copy0MBB
)
;
F
->
insert
(
I
,
copy1MBB
)
;
copy1MBB
->
splice
(
copy1MBB
->
begin
(
)
,
BB
,
std
::
next
(
MachineBasicBlock
::
iterator
(
MI
)
)
,
BB
->
end
(
)
)
;
copy1MBB
->
transferSuccessorsAndUpdatePHIs
(
BB
)
;
BB
->
addSuccessor
(
copy0MBB
)
;
BB
->
addSuccessor
(
copy1MBB
)
;
BuildMI
(
BB
,
dl
,
TII
.
get
(
MSP430
::
JCC
)
)
.
addMBB
(
copy1MBB
)
.
addImm
(
MI
.
getOperand
(
3
)
.
getImm
(
)
)
;
BB
=
copy0MBB
;
BB
->
addSuccessor
(
copy1MBB
)
;
BB
=
copy1MBB
;
BuildMI
(
*
BB
,
BB
->
begin
(
)
,
dl
,
TII
.
get
(
MSP430
::
PHI
)
,
MI
.
getOperand
(
0
)
.
getReg
(
)
)
.
addReg
(
MI
.
getOperand
(
2
)
.
getReg
(
)
)
.
addMBB
(
copy0MBB
)
.
addReg
(
MI
.
getOperand
(
1
)
.
getReg
(
)
)
.
addMBB
(
thisMBB
)
;
MI
.
eraseFromParent
(
)
;
return
BB
;
}
</s>

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


"WebAssembly hasn't implemented computed gotos"

"WebAssembly hasn't implemented __builtin_return_address"

LowerOperation - Provide custom lowering hooks for some operations .


<s> bool isMem ( ) const override { return isMEMrr ( ) || isMEMri ( ) ; } </s>


<s>
EVT
AVRTargetLowering
::
getSetCCResultType
(
const
DataLayout
&
DL
,
LLVMContext
&
,
EVT
VT
)
const
{
assert
(
!
VT
.
isVector
(
)
&&
"No AVR SetCC type for vectors!"
)
;
return
MVT
::
i8
;
}
</s>

Return the value type to use for ISD : :SETCC .

AVR
AVR
"No AVR SetCC type for vectors!"
MVT::i8


<s> void Thumb2InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == ARM :: GPRRegisterClass ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , 0 , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( ARM :: t2LDRi12 ) , DestReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ) ; return ; } ARMBaseInstrInfo :: loadRegFromStackSlot ( MBB , I , DestReg , FI , RC ) ; } </s>


<s> const PPCSubtarget * PPCTargetMachine :: getSubtargetImpl ( const Function & F ) const { AttributeSet FnAttrs = F . getAttributes ( ) ; Attribute CPUAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-cpu" ) ; Attribute FSAttr = FnAttrs . getAttribute ( AttributeSet :: FunctionIndex , "target-features" ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < PPCSubtarget > ( TargetTriple , CPU , FS , * this ) ; } return I . get ( ) ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .

PowerPC PPC PPC "target-cpu" "target-features" PPC


<s> bool RV16KUseLWSPSWSP :: runOnMachineFunction ( MachineFunction & MF ) { for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { unsigned Opc = MI . getOpcode ( ) ; if ( Opc == RV16K :: LW && MI . getOperand ( 1 ) . getReg ( ) == RV16K :: X1 && isShiftedUInt < 8 , 1 > ( MI . getOperand ( 2 ) . getImm ( ) ) ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( RV16K :: LWSP ) ) ; } if ( Opc == RV16K :: SW && MI . getOperand ( 1 ) . getReg ( ) == RV16K :: X1 && isShiftedUInt < 8 , 1 > ( MI . getOperand ( 2 ) . getImm ( ) ) ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( RV16K :: SWSP ) ) ; } } } return true ; } </s>