<s> static bool aarch64_vfp_is_call_or_return_candidate ( machine_mode mode , const_tree type , machine_mode * base_mode , int * count , bool * is_ha ) { machine_mode new_mode = VOIDmode ; bool composite_p = aarch64_composite_type_p ( type , mode ) ; if ( is_ha != NULL ) * is_ha = false ; if ( ( ! composite_p && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) || aarch64_short_vector_p ( type , mode ) ) { * count = 1 ; new_mode = mode ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { if ( is_ha != NULL ) * is_ha = true ; * count = 2 ; new_mode = GET_MODE_INNER ( mode ) ; } else if ( type && composite_p ) { int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode ) ; if ( ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS ) { if ( is_ha != NULL ) * is_ha = true ; * count = ag_count ; } else return false ; } else return false ; * base_mode = new_mode ; return true ; } </s>

Return TRUE if an argument , whose type is described by TYPE and MODE , shall be passed or returned in simd/fp register ( s ) ( providing these parameter passing registers are available ) . Upon successful return , * COUNT returns the number of needed registers , * BASE_MODE returns the mode of the individual register and when IS_HAF is not NULL , * IS_HA indicates whether or not the argument is a homogeneous floating-point aggregate or a homogeneous short-vector aggregate .


<s> SDNode * XCoreTargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallSDNode * TheCall , unsigned CallingConv , SelectionDAG & DAG ) { bool isVarArg = TheCall -> isVarArg ( ) ; DebugLoc dl = TheCall -> getDebugLoc ( ) ; SmallVector < CCValAssign , 16 > RVLocs ; CCState CCInfo ( CallingConv , isVarArg , getTargetMachine ( ) , RVLocs ) ; CCInfo . AnalyzeCallResult ( TheCall , RetCC_XCore ) ; SmallVector < SDValue , 8 > ResultVals ; for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; InFlag = Chain . getValue ( 2 ) ; ResultVals . push_back ( Chain . getValue ( 0 ) ) ; } ResultVals . push_back ( Chain ) ; return DAG . getNode ( ISD :: MERGE_VALUES , dl , TheCall -> getVTList ( ) , & ResultVals [ 0 ] , ResultVals . size ( ) ) . getNode ( ) ; } </s>

LowerCallResult - Lower the result values of an ISD : :CALL into the appropriate copies out of appropriate physical registers .


<s> int xtensa_dbx_register_number ( int regno ) { int first = - 1 ; if ( GP_REG_P ( regno ) ) { regno -= GP_REG_FIRST ; first = 0 ; } else if ( BR_REG_P ( regno ) ) { regno -= BR_REG_FIRST ; first = 16 ; } else if ( FP_REG_P ( regno ) ) { regno -= FP_REG_FIRST ; first = 48 ; } else if ( ACC_REG_P ( regno ) ) { first = 0x200 ; regno = 16 ; } if ( first == - 1 ) return 0 ; return first + regno ; } </s>

Return the stabs register number to use for 'regno ' .


<s> static bool expand_vec_perm_broadcast ( struct expand_vec_perm_d * d ) { unsigned i , elt , nelt = d -> nelt ; unsigned char perm2 [ 2 ] ; rtx temp ; bool ok ; if ( ! d -> one_operand_p ) return false ; elt = d -> perm [ 0 ] ; for ( i = 1 ; i < nelt ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; switch ( d -> vmode ) { case E_V2SImode : case E_V2SFmode : perm2 [ 0 ] = elt ; perm2 [ 1 ] = elt + 2 ; ok = expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , perm2 , 2 ) ; gcc_assert ( ok ) ; break ; case E_V8QImode : if ( BYTES_BIG_ENDIAN ) elt = 7 - elt ; elt *= BITS_PER_UNIT ; temp = gen_reg_rtx ( DImode ) ; emit_insn ( gen_extzv ( temp , gen_lowpart ( DImode , d -> op0 ) , GEN_INT ( 8 ) , GEN_INT ( elt ) ) ) ; emit_insn ( gen_mux1_brcst_qi ( d -> target , gen_lowpart ( QImode , temp ) ) ) ; break ; case E_V4HImode : default : gcc_unreachable ( ) ; } return true ; } </s>


<s> static bool classof ( const MCSection * S ) { return S -> getVariant ( ) == SV_GBZ80 ; } </s>

Methods for support type inquiry through isa , cast , and dyn_cast :


Generate compact unwind encoding for the function based on the CFI instructions .


<s> bool AMDGPUCodeGenPrepare :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto * TPC = getAnalysisIfAvailable < TargetPassConfig > ( ) ; if ( ! TPC ) return false ; const AMDGPUTargetMachine & TM = TPC -> getTM < AMDGPUTargetMachine > ( ) ; ST = & TM . getSubtarget < GCNSubtarget > ( F ) ; AC = & getAnalysis < AssumptionCacheTracker > ( ) . getAssumptionCache ( F ) ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; HasFP32Denormals = ST -> hasFP32Denormals ( F ) ; bool MadeChange = false ; for ( BasicBlock & BB : F ) { BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; I = Next ) { Next = std :: next ( I ) ; MadeChange |= visit ( * I ) ; } } return MadeChange ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


<s> bool X86TTIImpl :: hasDivRemOp ( Type * DataType , bool IsSigned ) { EVT VT = TLI -> getValueType ( DL , DataType ) ; return TLI -> isOperationLegal ( IsSigned ? ISD :: SDIVREM : ISD :: UDIVREM , VT ) ; } </s>

Return true if the target has a unified operation to calculate division and remainder .


<s> static bool mep_use_post_modify_p_1 ( rtx_insn * set_insn , rtx reg , rtx offset ) { rtx_insn * insn ; insn = set_insn ; do { insn = PREV_INSN ( insn ) ; if ( INSN_P ( insn ) ) { if ( mep_use_post_modify_for_set_p ( PATTERN ( insn ) , reg , offset ) ) { mep_make_parallel ( insn , set_insn ) ; return true ; } if ( reg_set_p ( reg , insn ) || reg_referenced_p ( reg , PATTERN ( insn ) ) || volatile_insn_p ( PATTERN ( insn ) ) ) return false ; } } while ( ! NOTE_INSN_BASIC_BLOCK_P ( insn ) ) ; return false ; } </s>

SET_INSN is an instruction that adds OFFSET to REG . Go back through the basic block to see if any previous load or store instruction can be persuaded to do SET_INSN as a side-effect . Return true if so .


<s> bool isOSWindows ( ) const { return TargetTriple . isOSWindows ( ) ; } </s>


<s> bool HexagonInstrInfo :: isIndirectCall ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case Hexagon :: J2_callr : case Hexagon :: J2_callrf : case Hexagon :: J2_callrt : return true ; } return false ; } </s>

Return true if the callsite is an indirect call .


<s> bool LanaiDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintCode , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 , AluOp ; switch ( ConstraintCode ) { default : return true ; case InlineAsm :: Constraint_m : if ( ! selectAddrRr ( Op , Op0 , Op1 , AluOp ) && ! selectAddrRi ( Op , Op0 , Op1 , AluOp ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( AluOp ) ; return false ; } </s>

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode , according to the specified constraint .


<s> bool ARMAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { AFI = MF . getInfo < ARMFunctionInfo > ( ) ; MCP = MF . getConstantPool ( ) ; Subtarget = & MF . getSubtarget < ARMSubtarget > ( ) ; SetupMachineFunction ( MF ) ; const Function * F = MF . getFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; for ( auto * GV : AFI -> getGlobalsPromotedToConstantPool ( ) ) PromotedGlobals . insert ( GV ) ; unsigned OptimizationGoal ; if ( F -> hasFnAttribute ( Attribute :: OptimizeNone ) ) OptimizationGoal = 6 ; else if ( F -> optForMinSize ( ) ) OptimizationGoal = 4 ; else if ( F -> optForSize ( ) ) OptimizationGoal = 3 ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = 2 ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = 1 ; else OptimizationGoal = 5 ; if ( OptimizationGoals == - 1 ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = 0 ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } EmitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> EmitAssemblerFlag ( MCAF_Code16 ) ; EmitAlignment ( 1 ) ; for ( unsigned i = 0 , e = ThumbIndirectPads . size ( ) ; i < e ; i ++ ) { OutStreamer -> EmitLabel ( ThumbIndirectPads [ i ] . second ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( ARM :: tBX ) . addReg ( ThumbIndirectPads [ i ] . first ) . addImm ( ARMCC :: AL ) . addReg ( 0 ) ) ; } ThumbIndirectPads . clear ( ) ; } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s>
void
dump
(
const
llvm
::
SelectionDAG
*
DAG
)
{
errs
(
)
<<
"SystemZAddressingMode "
<<
this
<<
'\n'
;
errs
(
)
<<
" Base "
;
if
(
Base
.
getNode
(
)
)
Base
.
getNode
(
)
->
dump
(
DAG
)
;
else
errs
(
)
<<
"null\n"
;
if
(
hasIndexField
(
)
)
{
errs
(
)
<<
" Index "
;
if
(
Index
.
getNode
(
)
)
Index
.
getNode
(
)
->
dump
(
DAG
)
;
else
errs
(
)
<<
"null\n"
;
}
errs
(
)
<<
" Disp "
<<
Disp
;
if
(
IncludesDynAlloc
)
errs
(
)
<<
" + ADJDYNALLOC"
;
errs
(
)
<<
'\n'
;
}
</s>

Dump the plan to stderr ( for debugging ) .

SystemZ
"SystemZAddressingMode "
" Base "
"null\n"
" Index "
"null\n"
" Disp "
" + ADJDYNALLOC"


<s>
void
AArch64AsmBackend
::
applyFixup
(
const
MCFixup
&
Fixup
,
char
*
Data
,
unsigned
DataSize
,
uint64_t
Value
,
bool
IsPCRel
)
const
{
unsigned
NumBytes
=
getFixupKindNumBytes
(
Fixup
.
getKind
(
)
)
;
if
(
!
Value
)
return
;
MCFixupKindInfo
Info
=
getFixupKindInfo
(
Fixup
.
getKind
(
)
)
;
Value
=
adjustFixupValue
(
Fixup
.
getKind
(
)
,
Value
)
;
Value
<<=
Info
.
TargetOffset
;
unsigned
Offset
=
Fixup
.
getOffset
(
)
;
assert
(
Offset
+
NumBytes
<=
DataSize
&&
"Invalid fixup offset!"
)
;
unsigned
FulleSizeInBytes
=
getFixupKindContainereSizeInBytes
(
Fixup
.
getKind
(
)
)
;
if
(
FulleSizeInBytes
==
0
)
{
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
Data
[
Offset
+
i
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
else
{
assert
(
(
Offset
+
FulleSizeInBytes
)
<=
DataSize
&&
"Invalid fixup size!"
)
;
assert
(
NumBytes
<=
FulleSizeInBytes
&&
"Invalid fixup size!"
)
;
for
(
unsigned
i
=
0
;
i
!=
NumBytes
;
++
i
)
{
unsigned
Idx
=
FulleSizeInBytes
1
i
;
Data
[
Offset
+
Idx
]
|=
uint8_t
(
(
Value
>>
(
i
*
8
)
)
&
0xff
)
;
}
}
}
</s>

Apply the Value for given Fixup into the provided data fragment , at the offset specified by the fixup and following the fixup kind as appropriate .


<s> bool loongarch_unsigned_immediate_p ( unsigned HOST_WIDE_INT x , int bits , int shift = 0 ) { return ( x & ( ( 1 << shift ) - 1 ) ) == 0 && x < ( ( unsigned ) 1 << ( shift + bits ) ) ; } </s>

Return true if X fits within an unsigned field of BITS bits that is shifted left SHIFT bits before being used .


<s> rtx m32c_return_addr_rtx ( int count ) { machine_mode mode ; int offset ; rtx ra_mem ; if ( count ) return NULL_RTX ; if ( TARGET_A24 ) { mode = PSImode ; offset = 4 ; } else { mode = HImode ; offset = 2 ; } ra_mem = gen_rtx_MEM ( mode , plus_constant ( Pmode , gen_rtx_REG ( Pmode , FP_REGNO ) , offset ) ) ; return copy_to_mode_reg ( mode , ra_mem ) ; } </s>

Implements RETURN_ADDR_RTX . Note that R8C and M16C push 24 bits ( yes , THREE bytes ) onto the stack for the return address , but we do n't support pointers bigger than 16 bits on those chips . This will likely wreak havoc with exception unwinding . FIXME .


<s> bool MipsSubtarget :: enablePostRAScheduler ( CodeGenOpt :: Level OptLevel , TargetSubtargetInfo :: AntiDepBreakMode & Mode , RegClassVector & CriticalPathRCs ) const { Mode = TargetSubtargetInfo :: ANTIDEP_NONE ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( isGP64bit ( ) ? & Mips :: GPR64RegClass : & Mips :: GPR32RegClass ) ; return OptLevel >= CodeGenOpt :: Aggressive ; } </s>

True if the subtarget should run a scheduler after register allocation .


<s> void PPCPassConfig :: addPreEmitPass ( ) { addPass ( createPPCPreEmitPeepholePass ( ) ) ; addPass ( createPPCExpandISELPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createPPCEarlyReturnPass ( ) , false ) ; addPass ( createPPCBranchSelectionPass ( ) , false ) ; } </s>

This pass may be implemented by targets that want to run passes immediately before machine code is emitted .


<s>
static
void
rs6000_debug_target_options
(
tree
args
,
const
char
*
prefix
)
{
if
(
args
==
NULL_TREE
)
fprintf
(
stderr
,
"%s<NULL>"
,
prefix
)
;
else
if
(
TREE_CODE
(
args
)
==
STRING_CST
)
{
char
*
p
=
ASTRDUP
(
TREE_STRING_POINTER
(
args
)
)
;
char
*
q
;
while
(
(
q
=
strtok
(
p
,
","
)
)
!=
)
{
p
=
;
fprintf
(
stderr
,
"%s\"%s\""
,
prefix
,
q
)
;
prefix
=
", "
;
}
}
else
if
(
TREE_CODE
(
args
)
==
TREE_LIST
)
{
do
{
tree
value
=
TREE_VALUE
(
args
)
;
if
(
value
)
{
rs6000_debug_target_options
(
value
,
prefix
)
;
prefix
=
", "
;
}
args
=
TREE_CHAIN
(
args
)
;
}
while
(
args
!=
NULL_TREE
)
;
}
else
gcc_unreachable
(
)
;
return
;
}
</s>

Print out the target options as a list for -mdebug=target .


<s> unsigned AVRInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { case AVR :: STDPtrQRr : case AVR :: STDWPtrQRr : { if ( ( MI -> getOperand ( 0 ) . isFI ( ) ) && ( MI -> getOperand ( 1 ) . isImm ( ) ) && ( MI -> getOperand ( 1 ) . getImm ( ) == 0 ) ) { FrameIndex = MI -> getOperand ( 0 ) . getIndex ( ) ; return MI -> getOperand ( 2 ) . getReg ( ) ; } break ; } default : break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> void GCNMaxOccupancySchedStrategy :: initialize ( ScheduleDAGMI * DAG ) { GenericScheduler :: initialize ( DAG ) ; MF = & DAG -> MF ; const GCNSubtarget & ST = MF -> getSubtarget < GCNSubtarget > ( ) ; const unsigned ErrorMargin = 3 ; SGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & AMDGPU :: SGPR_32RegClass ) ; VGPRExcessLimit = Context -> RegClassInfo -> getNumAllocatableRegs ( & AMDGPU :: VGPR_32RegClass ) ; SIMachineFunctionInfo & MFI = * MF -> getInfo < SIMachineFunctionInfo > ( ) ; TargetOccupancy = MFI . getOccupancy ( ) ; SGPRCriticalLimit = std :: min ( ST . getMaxNumSGPRs ( TargetOccupancy , true ) , SGPRExcessLimit ) ; VGPRCriticalLimit = std :: min ( ST . getMaxNumVGPRs ( TargetOccupancy ) , VGPRExcessLimit ) ; SGPRCriticalLimit = std :: min ( SGPRCriticalLimit - ErrorMargin , SGPRCriticalLimit ) ; VGPRCriticalLimit = std :: min ( VGPRCriticalLimit - ErrorMargin , VGPRCriticalLimit ) ; SGPRExcessLimit = std :: min ( SGPRExcessLimit - ErrorMargin , SGPRExcessLimit ) ; VGPRExcessLimit = std :: min ( VGPRExcessLimit - ErrorMargin , VGPRExcessLimit ) ; } </s>

Initialize the strategy after building the DAG for a new region .


<s> unsigned ARMFastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 , bool Op0IsKill ) { unsigned ResultReg = createResultReg ( RC ) ; const MCInstrDesc & II = TII . get ( MachineInstOpcode ) ; Op0 = constrainOperandRegClass ( II , Op0 , 1 ) ; if ( II . getNumDefs ( ) >= 1 ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ 0 ] ) ) ; } return ResultReg ; } </s>

Emit a MachineInstr with one register operand and a result register in the given register class .


<s> bool mips_pad_arg_upward ( machine_mode mode , const_tree type ) { if ( ! BYTES_BIG_ENDIAN ) return true ; if ( type != 0 ? ( INTEGRAL_TYPE_P ( type ) || POINTER_TYPE_P ( type ) || FIXED_POINT_TYPE_P ( type ) ) : ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) ) return false ; if ( mips_abi == ABI_O64 ) if ( type != 0 ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return false ; if ( mips_abi != ABI_EABI ) return true ; if ( mode != BLKmode ) return GET_MODE_BITSIZE ( mode ) >= PARM_BOUNDARY ; else return int_size_in_bytes ( type ) >= ( PARM_BOUNDARY / BITS_PER_UNIT ) ; } </s>

Return true if FUNCTION_ARG_PADDING ( MODE , TYPE ) should return upward rather than downward . In other words , return true if the first byte of the stack slot has useful data , false if the last byte does .


<s>
unsigned
LEGMCCodeEmitter
::
getMachineOpValue
(
const
MCInst
&
MI
,
const
MCOperand
&
MO
,
SmallVectorImpl
<
MCFixup
>
&
Fixups
,
const
MCSubtargetInfo
&
STI
)
const
{
if
(
MO
.
isReg
(
)
)
{
return
CTX
.
getRegisterInfo
(
)
->
getEncodingValue
(
MO
.
getReg
(
)
)
;
}
if
(
MO
.
isImm
(
)
)
{
return
static_cast
<
unsigned
>
(
MO
.
getImm
(
)
)
;
}
assert
(
MO
.
isExpr
(
)
&&
"unknown operand kind in printOperand"
)
;
const
MCExpr
*
Expr
=
MO
.
getExpr
(
)
;
MCExpr
::
ExprKind
Kind
=
Expr
->
getKind
(
)
;
if
(
Kind
==
MCExpr
::
Binary
)
{
Expr
=
static_cast
<
const
MCBinaryExpr
*
>
(
Expr
)
->
getLHS
(
)
;
Kind
=
Expr
->
getKind
(
)
;
}
assert
(
Kind
==
MCExpr
::
SymbolRef
)
;
unsigned
FixupKind
;
switch
(
cast
<
MCSymbolRefExpr
>
(
Expr
)
->
getKind
(
)
)
{
default
:
llvm_unreachable
(
"Unknown fixup kind!"
)
;
case
MCSymbolRefExpr
::
VK_LEG_LO
:
{
FixupKind
=
LEG
::
fixup_leg_mov_lo16_pcrel
;
break
;
}
case
MCSymbolRefExpr
::
VK_LEG_HI
:
{
FixupKind
=
LEG
::
fixup_leg_mov_hi16_pcrel
;
break
;
}
}
Fixups
.
push_back
(
MCFixup
::
Create
(
0
,
MO
.
getExpr
(
)
,
MCFixupKind
(
FixupKind
)
)
)
;
return
0
;
}
</s>

getMachineOpValue - Return binary encoding of operand .


<s> void h8300_expand_prologue ( void ) { int regno ; int saved_regs ; int n_regs ; if ( h8300_os_task_function_p ( current_function_decl ) ) return ; if ( h8300_monitor_function_p ( current_function_decl ) ) emit_insn ( gen_monitor_prologue ( ) ) ; if ( frame_pointer_needed ) { push ( HARD_FRAME_POINTER_REGNUM , true ) ; F ( emit_move_insn ( hard_frame_pointer_rtx , stack_pointer_rtx ) , 0 ) ; } saved_regs = compute_saved_regs ( ) ; for ( regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno += n_regs ) { n_regs = 1 ; if ( saved_regs & ( 1 << regno ) ) { if ( TARGET_H8300S ) { if ( ( TARGET_H8300SX || ( regno & 3 ) == 0 ) && ( ( saved_regs >> regno ) & 0x0f ) == 0x0f ) n_regs = 4 ; else if ( ( TARGET_H8300SX || ( regno & 3 ) == 0 ) && ( ( saved_regs >> regno ) & 0x07 ) == 0x07 ) n_regs = 3 ; else if ( ( TARGET_H8300SX || ( regno & 1 ) == 0 ) && ( ( saved_regs >> regno ) & 0x03 ) == 0x03 ) n_regs = 2 ; } h8300_push_pop ( regno , n_regs , false , false ) ; } } h8300_emit_stack_adjustment ( - 1 , round_frame_size ( get_frame_size ( ) ) , true ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = round_frame_size ( get_frame_size ( ) ) + ( __builtin_popcount ( saved_regs ) * UNITS_PER_WORD ) + ( frame_pointer_needed ? UNITS_PER_WORD : 0 ) ; } </s>

Generate RTL code for the function prologue .


<s> static rtx aarch64_expand_builtin_rsqrt ( int fcode , tree exp , rtx target ) { tree arg0 = CALL_EXPR_ARG ( exp , 0 ) ; rtx op0 = expand_normal ( arg0 ) ; rtx ( * gen ) ( rtx , rtx ) ; switch ( fcode ) { case AARCH64_BUILTIN_RSQRT_DF : gen = gen_rsqrtdf2 ; break ; case AARCH64_BUILTIN_RSQRT_SF : gen = gen_rsqrtsf2 ; break ; case AARCH64_BUILTIN_RSQRT_V2DF : gen = gen_rsqrtv2df2 ; break ; case AARCH64_BUILTIN_RSQRT_V2SF : gen = gen_rsqrtv2sf2 ; break ; case AARCH64_BUILTIN_RSQRT_V4SF : gen = gen_rsqrtv4sf2 ; break ; default : gcc_unreachable ( ) ; } if ( ! target ) target = gen_reg_rtx ( GET_MODE ( op0 ) ) ; emit_insn ( gen ( target , op0 ) ) ; return target ; } </s>

Function to expand reciprocal square root builtins .


"CFGuard check mechanism only used on 32-bit X86"

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> static rtx aarch64_add_offset ( machine_mode mode , rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! aarch64_plus_immediate ( GEN_INT ( offset ) , mode ) ) { rtx high ; high = GEN_INT ( offset ) ; offset = 0 ; high = aarch64_force_temporary ( mode , temp , high ) ; reg = aarch64_force_temporary ( mode , temp , gen_rtx_PLUS ( mode , high , reg ) ) ; } return plus_constant ( mode , reg , offset ) ; } </s>

Set DEST to SRC + OFFSET . MODE is the mode of the addition . FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should be set and CFA adjustments added to the generated instructions . TEMP1 , if nonnull , is a register of mode MODE that can be used as a temporary if register allocation is already complete . This temporary register may overlap DEST if ! FRAME_RELATED_P but must not overlap SRC . If TEMP1 is known to hold abs ( OFFSET ) , EMIT_MOVE_IMM can be set to false to avoid emitting the immediate again . TEMP2 , if nonnull , is a second temporary register that does n't overlap either DEST or REG . Since this function may be used to adjust the stack pointer , we must ensure that it can not cause transient stack deallocation ( for example by first incrementing SP and then decrementing when adjusting by a large immediate ) .


<s> enum mask_policy get_prefer_mask_policy ( ) { return MASK_ANY ; } </s>


<s> bool HexagonConstEvaluator :: evaluate ( const MachineInstr & BrI , const CellMap & Inputs , SetVector < const MachineBasicBlock * > & Targets , bool & FallsThru ) { unsigned Opc = BrI . getOpcode ( ) ; bool SimpleBranch = false ; bool Negated = false ; switch ( Opc ) { case Hexagon :: J2_jumpf : case Hexagon :: J2_jumpfnew : case Hexagon :: J2_jumpfnewpt : Negated = true ; case Hexagon :: J2_jumpt : case Hexagon :: J2_jumptnew : case Hexagon :: J2_jumptnewpt : SimpleBranch = true ; break ; case Hexagon :: J2_jump : Targets . insert ( BrI . getOperand ( 0 ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : Undetermined : FallsThru = ! BrI . isUnconditionalBranch ( ) ; return false ; } if ( SimpleBranch ) { const MachineOperand & MD = BrI . getOperand ( 0 ) ; Register PR ( MD ) ; if ( PR . SubReg ) goto Undetermined ; assert ( Inputs . has ( PR . Reg ) ) ; const LatticeCell & PredC = Inputs . get ( PR . Reg ) ; if ( PredC . isBottom ( ) ) goto Undetermined ; uint32_t Props = PredC . properties ( ) ; bool CTrue = false , CFalse = false ; ; if ( Props & ConstantProperties :: Zero ) CFalse = true ; else if ( Props & ConstantProperties :: NonZero ) CTrue = true ; if ( ! CTrue && ! CFalse ) goto Undetermined ; const MachineBasicBlock * BranchTarget = BrI . getOperand ( 1 ) . getMBB ( ) ; FallsThru = false ; if ( ( ! Negated && CTrue ) || ( Negated && CFalse ) ) Targets . insert ( BranchTarget ) ; else if ( ( ! Negated && CFalse ) || ( Negated && CTrue ) ) FallsThru = true ; else goto Undetermined ; } return true ; } </s>

evaluate - Evaluate Expr and append the resulting set to Elts .


<s> std :: pair < unsigned , const TargetRegisterClass * > NVPTXTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == 1 ) { switch ( Constraint [ 0 ] ) { case 'c' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'h' : return std :: make_pair ( 0U , & NVPTX :: Int16RegsRegClass ) ; case 'r' : return std :: make_pair ( 0U , & NVPTX :: Int32RegsRegClass ) ; case 'l' : case 'N' : return std :: make_pair ( 0U , & NVPTX :: Int64RegsRegClass ) ; case 'f' : return std :: make_pair ( 0U , & NVPTX :: Float32RegsRegClass ) ; case 'd' : return std :: make_pair ( 0U , & NVPTX :: Float64RegsRegClass ) ; } } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> bool RISCVExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ; for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ; return Modified ; } </s>

runOnMachineFunction - Emit the function body .


<s> SDValue R600TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , 16 > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; R600MachineFunctionInfo * MFI = MF . getInfo < R600MachineFunctionInfo > ( ) ; SmallVector < ISD :: InputArg , 8 > LocalIns ; getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = 0 , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const ISD :: InputArg & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( AMDGPU :: isShader ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & AMDGPU :: R600_Reg128RegClass ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , AMDGPUAS :: CONSTANT_BUFFER_0 ) ; ISD :: LoadExtType Ext = ISD :: NON_EXTLOAD ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = ISD :: SEXTLOAD ; } unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ; unsigned PartOffset = VA . getLocMemOffset ( ) ; unsigned Offset = Subtarget -> getExplicitKernelArgOffset ( ) + VA . getLocMemOffset ( ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) , PartOffset - ValBase ) ; SDValue Arg = DAG . getLoad ( ISD :: UNINDEXED , Ext , VT , DL , Chain , DAG . getConstant ( Offset , DL , MVT :: i32 ) , DAG . getUNDEF ( MVT :: i32 ) , PtrInfo , MemVT , 4 , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MOInvariant ) ; InVals . push_back ( Arg ) ; MFI -> setABIArgOffset ( Offset + MemVT . getStoreSize ( ) ) ; } return Chain ; } </s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


"X86 Support for return instruction protection"

getPassName - Return a nice clean name for a pass .


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"ARM pseudo instruction expansion pass"
;
}
</s>

ARM
"ARM pseudo instruction expansion pass"


<s> SparcSubtarget & SparcSubtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS ) { IsV9 = false ; IsLeon = false ; V8DeprecatedInsts = false ; IsVIS = false ; HasHardQuad = false ; UsePopc = false ; UseSoftFloat = false ; HasLeonCasa = false ; HasUmacSmac = false ; PerformSDIVReplace = false ; FixCallImmediates = false ; IgnoreZeroFlag = false ; InsertNOPDoublePrecision = false ; FixFSMULD = false ; ReplaceFMULS = false ; PreventRoundChange = false ; FixAllFDIVSQRT = false ; InsertNOPLoad = false ; FlushCacheLineSWAP = false ; InsertNOPsLoadStore = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? "v9" : "v8" ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ; } </s>

initializeSubtargetDependencies - Initializes using a CPU , a TuneCPU , and feature string so that we can use initializer lists for subtarget initialization .


<s> const M68kTargetMachine & getTargetMachine ( ) { return static_cast < const M68kTargetMachine & > ( TM ) ; } </s>

Return the target machine ( if available ) .


<s> static Register buildRSRC ( MachineIRBuilder & B , MachineRegisterInfo & MRI , uint32_t FormatLo , uint32_t FormatHi , Register BasePtr ) { Register RSrc2 = MRI . createVirtualRegister ( & AMDGPU :: SReg_32RegClass ) ; Register RSrc3 = MRI . createVirtualRegister ( & AMDGPU :: SReg_32RegClass ) ; Register RSrcHi = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; Register RSrc = MRI . createVirtualRegister ( & AMDGPU :: SGPR_128RegClass ) ; B . buildInstr ( AMDGPU :: S_MOV_B32 ) . addDef ( RSrc2 ) . addImm ( FormatLo ) ; B . buildInstr ( AMDGPU :: S_MOV_B32 ) . addDef ( RSrc3 ) . addImm ( FormatHi ) ; B . buildInstr ( AMDGPU :: REG_SEQUENCE ) . addDef ( RSrcHi ) . addReg ( RSrc2 ) . addImm ( AMDGPU :: sub0 ) . addReg ( RSrc3 ) . addImm ( AMDGPU :: sub1 ) ; Register RSrcLo = BasePtr ; if ( ! BasePtr ) { RSrcLo = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; B . buildInstr ( AMDGPU :: S_MOV_B64 ) . addDef ( RSrcLo ) . addImm ( 0 ) ; } B . buildInstr ( AMDGPU :: REG_SEQUENCE ) . addDef ( RSrc ) . addReg ( RSrcLo ) . addImm ( AMDGPU :: sub0_sub1 ) . addReg ( RSrcHi ) . addImm ( AMDGPU :: sub2_sub3 ) ; return RSrc ; } </s>

Return a resource descriptor with the 'Add TID ' bit enabled The TID ( Thread ID ) is multiplied by the stride value ( bits [ 61:48 ] of the resource descriptor ) to create an offset , which is added to the resource pointer .


<s> void TeeRISCFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TeeRISCInstrInfo & TII = * static_cast < const TeeRISCInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; int Amount = Old -> getOperand ( 0 ) . getImm ( ) + 4 ; if ( Amount != 0 ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - 1 ) / Align * Align ; MachineInstr * New ; if ( Old -> getOpcode ( ) == TeeRISC :: ADJCALLSTACKDOWN ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( TeeRISC :: ADD_IMM ) , TeeRISC :: SP ) . addReg ( TeeRISC :: SP ) . addImm ( - Amount ) ; } else { assert ( Old -> getOpcode ( ) == TeeRISC :: ADJCALLSTACKUP ) ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( TeeRISC :: ADD_IMM ) , TeeRISC :: SP ) . addReg ( TeeRISC :: SP ) . addImm ( Amount ) ; } MBB . insert ( I , New ) ; } } MBB . erase ( I ) ; } </s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


<s> bool hasFPU ( ) const { return HasFPU ; } </s>


<s> int64_t getOffset ( ) const { return Offset ; } </s>

Get the offest of a string in the string table .


"Only base registers and frame indices are supported."

Returns true if the two given memory operations should be scheduled adjacent .


<s> rtx resolve_reload_operand ( rtx op ) { if ( reload_in_progress ) { rtx tmp = op ; if ( GET_CODE ( tmp ) == SUBREG ) tmp = SUBREG_REG ( tmp ) ; if ( REG_P ( tmp ) && REGNO ( tmp ) >= FIRST_PSEUDO_REGISTER ) { op = reg_equiv_memory_loc ( REGNO ( tmp ) ) ; if ( op == 0 ) return 0 ; } } return op ; } </s>

Used by aligned_memory_operand and unaligned_memory_operand to resolve what reload is going to do with OP if it 's a register .


"Unexpected instruction for custom insertion"

This method should be implemented by targets that mark instructions with the 'usesCustomInserter ' flag .


<s> static unsigned char nds32_class_max_nregs ( reg_class_t rclass ATTRIBUTE_UNUSED , machine_mode mode ) { return ( ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - 1 ) / UNITS_PER_WORD ) ; } </s>


<s> void mips_expand_vec_minmax ( rtx target , rtx op0 , rtx op1 , rtx ( * cmp ) ( rtx , rtx , rtx ) , bool min_p ) { machine_mode vmode = GET_MODE ( target ) ; rtx tc , t0 , t1 , x ; tc = gen_reg_rtx ( vmode ) ; t0 = gen_reg_rtx ( vmode ) ; t1 = gen_reg_rtx ( vmode ) ; emit_insn ( cmp ( tc , op0 , op1 ) ) ; x = gen_rtx_AND ( vmode , tc , ( min_p ? op1 : op0 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t0 , x ) ) ; x = gen_rtx_NOT ( vmode , tc ) ; x = gen_rtx_AND ( vmode , x , ( min_p ? op0 : op1 ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , t1 , x ) ) ; x = gen_rtx_IOR ( vmode , t0 , t1 ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; } </s>


<s> static unsigned int aarch64_adjust_stmt_cost ( vect_cost_for_stmt kind , stmt_vec_info stmt_info , tree vectype , unsigned int stmt_cost ) { if ( vectype ) { const simd_vec_cost * simd_costs = aarch64_simd_vec_costs ( vectype ) ; switch ( aarch64_ld234_st234_vectors ( kind , stmt_info ) ) { case 2 : stmt_cost += simd_costs -> ld2_st2_permute_cost ; break ; case 3 : stmt_cost += simd_costs -> ld3_st3_permute_cost ; break ; case 4 : stmt_cost += simd_costs -> ld4_st4_permute_cost ; break ; } if ( kind == vector_stmt || kind == vec_to_scalar ) if ( tree cmp_type = aarch64_embedded_comparison_type ( stmt_info ) ) { if ( FLOAT_TYPE_P ( cmp_type ) ) stmt_cost += simd_costs -> fp_stmt_cost ; else stmt_cost += simd_costs -> int_stmt_cost ; } } if ( kind == scalar_stmt ) if ( tree cmp_type = aarch64_embedded_comparison_type ( stmt_info ) ) { if ( FLOAT_TYPE_P ( cmp_type ) ) stmt_cost += aarch64_tune_params . vec_costs -> scalar_fp_stmt_cost ; else stmt_cost += aarch64_tune_params . vec_costs -> scalar_int_stmt_cost ; } return stmt_cost ; } </s>

STMT_COST is the cost calculated for STMT_INFO , which has cost kind KIND and which when vectorized would operate on vector type VECTYPE . Add the cost of any embedded operations .


<s> rtx mips_prefetch_cookie ( rtx write , rtx locality ) { if ( INTVAL ( locality ) <= 0 ) return GEN_INT ( INTVAL ( write ) + 4 ) ; if ( INTVAL ( locality ) <= 2 ) return write ; return GEN_INT ( INTVAL ( write ) + 6 ) ; } </s>

Given that we have an rtx of the form ( prefetch ... WRITE LOCALITY ) , return the first operand of the associated `` pref '' or `` prefx '' insn .


<s> void X86ATTInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & X86II :: LOCK ) OS << "\tlock\n" ; if ( MI -> getOpcode ( ) == X86 :: CALLpcrel32 && ( getAvailableFeatures ( ) & X86 :: Mode64Bit ) != 0 ) { OS << "\tcallq\t" ; printPCRelImm ( MI , 0 , OS ) ; } else if ( ! printAliasInstr ( MI , OS ) ) printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ; if ( CommentStream ) EmitAnyX86InstComments ( MI , * CommentStream , getRegisterName ) ; } </s>

Print the specified MCInst to the specified raw_ostream .


<s> CCAssignFn * AVRTargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: AVR_BUILTIN : return RetCC_AVR_BUILTIN ; default : return RetCC_AVR ; } } </s>

Selects the correct CCAssignFn for a given CallingConvention value .


"Trying to fill a register in naked function "

Load the specified register of the given register class from the specified stack frame index .


<s> void Cpu0PassConfig :: addPreRegAlloc ( ) { if ( ! Cpu0ReserveGP ) { addPass ( createCpu0EmitGPRestorePass ( getCpu0TargetMachine ( ) ) ) ; } return ; } </s>

This method may be implemented by targets that want to run passes immediately before register allocation .


<s>
SDValue
MSP430TargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
OutVals
,
Ins
,
dl
,
DAG
,
InVals
)
;
case
CallingConv
::
MSP430_INTR
:
report_fatal_error
(
"ISRs cannot be called directly"
)
;
}
}
</s>

This hook must be implemented to lower calls into the specified DAG .


<s> static rtx bpf_function_arg ( cumulative_args_t ca , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( ca ) ; if ( * cum < 5 ) return gen_rtx_REG ( arg . mode , * cum + 1 ) ; else return NULL_RTX ; } </s>

Return a RTX indicating whether a function argument is passed in a register and if so , which register .


<s> uint32_t find ( T Val ) const { auto F = llvm :: find ( Map , Val ) ; assert ( F != Map . end ( ) ) ; return F - Map . begin ( ) + 1 ; } </s>

Search for the first string Str in the string .


<s> bool canSimplifyCallFramePseudos ( const MachineFunction & MF ) const override { return true ; } </s>

canSimplifyCallFramePseudos - If there is a reserved call frame , the call frame pseudos can be simplified .


"eliminateCallFramePseudoInstr size too big: "


<s> static rtx_insn * mips16_emit_constants_1 ( machine_mode mode , rtx value , rtx_insn * insn ) { if ( SCALAR_INT_MODE_P ( mode ) || ALL_SCALAR_FIXED_POINT_MODE_P ( mode ) ) { rtx size = GEN_INT ( GET_MODE_SIZE ( mode ) ) ; return emit_insn_after ( gen_consttable_int ( value , size ) , insn ) ; } if ( SCALAR_FLOAT_MODE_P ( mode ) ) return emit_insn_after ( gen_consttable_float ( value ) , insn ) ; if ( VECTOR_MODE_P ( mode ) ) { int i ; for ( i = 0 ; i < CONST_VECTOR_NUNITS ( value ) ; i ++ ) insn = mips16_emit_constants_1 ( GET_MODE_INNER ( mode ) , CONST_VECTOR_ELT ( value , i ) , insn ) ; return insn ; } gcc_unreachable ( ) ; } </s>

Output constant VALUE after instruction INSN and return the last instruction emitted . MODE is the mode of the constant .


<s> static rtx swap_selector_for_mode ( machine_mode mode ) { unsigned int swap2 [ 16 ] = { 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 , 15 , 14 , 13 , 12 , 11 , 10 , 9 , 8 } ; unsigned int swap4 [ 16 ] = { 3 , 2 , 1 , 0 , 7 , 6 , 5 , 4 , 11 , 10 , 9 , 8 , 15 , 14 , 13 , 12 } ; unsigned int swap8 [ 16 ] = { 1 , 0 , 3 , 2 , 5 , 4 , 7 , 6 , 9 , 8 , 11 , 10 , 13 , 12 , 15 , 14 } ; unsigned int swap16 [ 16 ] = { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 } ; unsigned int * swaparray , i ; rtx perm [ 16 ] ; switch ( mode ) { case E_V2DFmode : case E_V2DImode : swaparray = swap2 ; break ; case E_V4SFmode : case E_V4SImode : swaparray = swap4 ; break ; case E_V8HImode : swaparray = swap8 ; break ; case E_V16QImode : swaparray = swap16 ; break ; default : gcc_unreachable ( ) ; } for ( i = 0 ; i < 16 ; ++ i ) perm [ i ] = GEN_INT ( swaparray [ i ] ) ; return force_reg ( V16QImode , gen_rtx_CONST_VECTOR ( V16QImode , gen_rtvec_v ( 16 , perm ) ) ) ; } </s>

Return a constant vector for use as a little-endian permute control vector to reverse the order of elements of the given vector mode .


<s> TargetPassConfig * M88kTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new M88kPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s> bool WinEHStatePass :: runOnFunction ( Function & F ) { if ( F . hasAvailableExternallyLinkage ( ) ) return false ; if ( ! F . hasPersonalityFn ( ) ) return false ; PersonalityFn = dyn_cast < Function > ( F . getPersonalityFn ( ) -> stripPointerCasts ( ) ) ; if ( ! PersonalityFn ) return false ; Personality = classifyEHPersonality ( PersonalityFn ) ; if ( ! isFuncletEHPersonality ( Personality ) ) return false ; bool HasPads = false ; for ( BasicBlock & BB : F ) { if ( BB . isEHPad ( ) ) { HasPads = true ; break ; } } if ( ! HasPads ) return false ; Type * Int8PtrType = Type :: getInt8PtrTy ( TheModule -> getContext ( ) ) ; SetJmp3 = TheModule -> getOrInsertFunction ( "_setjmp3" , FunctionType :: get ( Type :: getInt32Ty ( TheModule -> getContext ( ) ) , { Int8PtrType , Type :: getInt32Ty ( TheModule -> getContext ( ) ) } , true ) ) ; emitExceptionRegistrationRecord ( & F ) ; WinEHFuncInfo FuncInfo ; addStateStores ( F , FuncInfo ) ; PersonalityFn = nullptr ; Personality = EHPersonality :: Unknown ; UseStackGuard = false ; RegNode = nullptr ; EHGuardNode = nullptr ; return true ; } </s>

runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass .


Emit code to initialize the REGNO predicate register to indicate whether we are not lane zero on the NAME axis .


<s> void DLXAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( I -> isCall ( ) ) { emitCallInstruction ( & * I ) ; continue ; } customEmitInstruction ( & * I ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s>
int64_t
ARMBaseRegisterInfo
::
getFrameIndexInstrOffset
(
const
MachineInstr
*
MI
,
int
Idx
)
const
{
const
MCInstrDesc
&
Desc
=
MI
->
getDesc
(
)
;
unsigned
AddrMode
=
(
Desc
.
TSFlags
&
ARMII
::
AddrModeMask
)
;
int64_t
InstrOffs
=
0
;
int
Scale
=
1
;
unsigned
ImmIdx
=
0
;
switch
(
AddrMode
)
{
case
ARMII
::
AddrModeT2_i8
:
case
ARMII
::
AddrModeT2_i12
:
case
ARMII
::
AddrMode_i12
:
InstrOffs
=
MI
->
getOperand
(
Idx
+
1
)
.
getImm
(
)
;
Scale
=
1
;
break
;
case
ARMII
::
AddrMode5
:
{
const
MachineOperand
&
OffOp
=
MI
->
getOperand
(
Idx
+
1
)
;
InstrOffs
=
ARM_AM
::
getAM5Offset
(
OffOp
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM5Op
(
OffOp
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
Scale
=
4
;
break
;
}
case
ARMII
::
AddrMode2
:
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM2Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM2Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
case
ARMII
::
AddrMode3
:
ImmIdx
=
Idx
+
2
;
InstrOffs
=
ARM_AM
::
getAM3Offset
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
;
if
(
ARM_AM
::
getAM3Op
(
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
)
==
ARM_AM
::
sub
)
InstrOffs
=
InstrOffs
;
break
;
case
ARMII
::
AddrModeT1_s
:
ImmIdx
=
Idx
+
1
;
InstrOffs
=
MI
->
getOperand
(
ImmIdx
)
.
getImm
(
)
;
Scale
=
4
;
break
;
default
:
llvm_unreachable
(
"Unsupported addressing mode!"
)
;
}
return
InstrOffs
*
Scale
;
}
</s>

Get the offset from the referenced frame index in the instruction , if there is one .


<s> bool AArch64InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns ) const { if ( getMaddPatterns ( Root , Patterns ) ) return true ; if ( getFMAPatterns ( Root , Patterns ) ) return true ; return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ) ; } </s>

Return true when there is potentially a faster code sequence for an instruction chain ending in Root .


<s> static enum rs6000_reg_type register_to_reg_type ( rtx reg , bool * is_altivec ) { HOST_WIDE_INT regno ; enum reg_class rclass ; if ( GET_CODE ( reg ) == SUBREG ) reg = SUBREG_REG ( reg ) ; if ( ! REG_P ( reg ) ) return NO_REG_TYPE ; regno = REGNO ( reg ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { if ( ! lra_in_progress && ! reload_in_progress && ! reload_completed ) return PSEUDO_REG_TYPE ; regno = true_regnum ( reg ) ; if ( regno < 0 || regno >= FIRST_PSEUDO_REGISTER ) return PSEUDO_REG_TYPE ; } gcc_assert ( regno >= 0 ) ; if ( is_altivec && ALTIVEC_REGNO_P ( regno ) ) * is_altivec = true ; rclass = rs6000_regno_regclass [ regno ] ; return reg_class_to_reg_type [ ( int ) rclass ] ; } </s>

Classify a register type . Because the FMRGOW/FMRGEW instructions only work on traditional floating point registers , and the VMRGOW/VMRGEW instructions only work on the traditional altivec registers , note if an altivec register was chosen .


"switch is not supported by the current processor"

"switch is not valid for the used operand type"

"Olny values '0' or '1' are allowed for this switch"

"expected specification in the form 'Switch=VALUE'"


<s> static void find_regmode_weight ( int b , enum machine_mode mode ) { rtx insn , next_tail , head , tail ; get_block_head_tail ( b , & head , & tail ) ; next_tail = NEXT_INSN ( tail ) ; for ( insn = head ; insn != next_tail ; insn = NEXT_INSN ( insn ) ) { if ( ! INSN_P ( insn ) ) continue ; if ( mode == SFmode ) INSN_REGMODE_WEIGHT ( insn , mode ) = find_insn_regmode_weight ( insn , mode ) + 2 * find_insn_regmode_weight ( insn , DFmode ) ; else if ( mode == SImode ) INSN_REGMODE_WEIGHT ( insn , mode ) = find_insn_regmode_weight ( insn , mode ) + 2 * find_insn_regmode_weight ( insn , DImode ) ; } } </s>

Calculate regmode weights for all insns of a basic block .


"Removing insn %d from candidates list\n"

For a given bitmap of insn UIDs scans all instructions and remove insn from CANDIDATES in case it has both convertible and not convertible definitions . All insns in a bitmap are conversion candidates according to scalar_to_vector_candidate_p . Currently it implies all insns are single_set .


<s>
SDValue
SystemZTargetLowering
::
LowerCall
(
SDValue
Chain
,
SDValue
Callee
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
bool
&
isTailCall
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
isTailCall
=
false
;
switch
(
CallConv
)
{
default
:
llvm_unreachable
(
"Unsupported calling convention"
)
;
case
CallingConv
::
Fast
:
case
CallingConv
::
C
:
return
LowerCCCCallTo
(
Chain
,
Callee
,
CallConv
,
isVarArg
,
isTailCall
,
Outs
,
Ins
,
dl
,
DAG
,
InVals
)
;
}
}
</s>

SystemZ
SystemZ
ISD::OutputArg
ISD::InputArg
"Unsupported calling convention"


<s>
bool
PIC16AsmPrinter
::
doInitialization
(
Module
&
M
)
{
bool
Result
=
AsmPrinter
::
doInitialization
(
M
)
;
O
<<
"\n#include p16f1xxx.inc"
;
O
<<
"\n#include stdmacros.inc"
;
for
(
Module
::
global_iterator
I
=
M
.
global_begin
(
)
,
E
=
M
.
global_end
(
)
;
I
!=
E
;
++
I
)
{
if
(
I
->
isDeclaration
(
)
)
{
ExternalVarDecls
.
push_back
(
I
)
;
continue
;
}
if
(
I
->
hasExternalLinkage
(
)
||
I
->
hasCommonLinkage
(
)
)
{
ExternalVarDefs
.
push_back
(
I
)
;
}
if
(
!
I
->
hasAvailableExternallyLinkage
(
)
)
{
const
MCSection
*
S
=
getObjFileLowering
(
)
.
SectionForGlobal
(
I
,
Mang
,
TM
)
;
I
->
setSection
(
(
(
const
PIC16Section
*
)
S
)
->
getName
(
)
)
;
}
}
DbgInfo
.
BeginModule
(
M
)
;
EmitFunctionDecls
(
M
)
;
EmitUndefinedVars
(
M
)
;
EmitDefinedVars
(
M
)
;
EmitIData
(
M
)
;
EmitUData
(
M
)
;
EmitRomData
(
M
)
;
EmitSharedUdata
(
M
)
;
EmitUserSections
(
M
)
;
return
Result
;
}
</s>

Set up the AsmPrinter when we are working on a new module .


<s> unsigned DLXInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TrueBlock , MachineBasicBlock * FalseBlock , ArrayRef < MachineOperand > Condition , const DebugLoc & DL , int * BytesAdded ) const { return 1 ; } </s>

Insert branch code into the end of the specified MachineBasicBlock .


<s> unsigned AArch64InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : break ; case AArch64 :: STRWui : case AArch64 :: STRXui : case AArch64 :: STRBui : case AArch64 :: STRHui : case AArch64 :: STRSui : case AArch64 :: STRDui : case AArch64 :: STRQui : case AArch64 :: LDR_PXI : case AArch64 :: STR_PXI : if ( MI . getOperand ( 0 ) . getSubReg ( ) == 0 && MI . getOperand ( 1 ) . isFI ( ) && MI . getOperand ( 2 ) . isImm ( ) && MI . getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; return MI . getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool alpha_split_const_mov ( machine_mode mode , rtx * operands ) { HOST_WIDE_INT i0 , i1 ; rtx temp = NULL_RTX ; alpha_extract_integer ( operands [ 1 ] , & i0 , & i1 ) ; if ( HOST_BITS_PER_WIDE_INT >= 64 || i1 == - ( i0 < 0 ) ) temp = alpha_emit_set_const ( operands [ 0 ] , mode , i0 , 3 , false ) ; if ( ! temp && TARGET_BUILD_CONSTANTS ) temp = alpha_emit_set_long_const ( operands [ 0 ] , i0 , i1 ) ; if ( temp ) { if ( ! rtx_equal_p ( operands [ 0 ] , temp ) ) emit_move_insn ( operands [ 0 ] , temp ) ; return true ; } return false ; } </s>

Operand 1 is known to be a constant , and should require more than one instruction to load . Emit that multi-part load .


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( Expr == nullptr ) Inst . addOperand ( MCOperand :: createImm ( 0 ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } </s>


<s> bool X86AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const { if ( getRelaxedOpcodeBranch ( Inst . getOpcode ( ) ) != Inst . getOpcode ( ) ) return true ; if ( MCDisableArithRelaxation ) return false ; if ( getRelaxedOpcodeArith ( Inst . getOpcode ( ) ) == Inst . getOpcode ( ) ) return false ; bool hasExp = false ; bool hasRIP = false ; for ( unsigned i = 0 ; i < Inst . getNumOperands ( ) ; ++ i ) { const MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isExpr ( ) ) hasExp = true ; if ( Op . isReg ( ) && Op . getReg ( ) == X86 :: RIP ) hasRIP = true ; } return hasExp && ! hasRIP ; } </s>

Check whether the given instruction may need relaxation .


<s> int X86TTIImpl :: getIntImmCost ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty ) { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; if ( BitSize == 0 ) return TTI :: TCC_Free ; unsigned ImmIdx = ~ 0U ; switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == 0 ) return 2 * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = 0 ; break ; case Instruction :: ICmp : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == 0x100000000ULL || ImmVal == 0xffffffff ) return TTI :: TCC_Free ; } ImmIdx = 1 ; break ; case Instruction :: And : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && isUInt < 32 > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == 1 && Imm . getBitWidth ( ) == 64 && Imm . getZExtValue ( ) == 0x80000000 ) return TTI :: TCC_Free ; ImmIdx = 1 ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = 1 ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == 1 ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast : case Instruction :: PHI : case Instruction :: Call : case Instruction :: Select : case Instruction :: Ret : case Instruction :: Load : break ; } if ( Idx == ImmIdx ) { int NumConstants = divideCeil ( BitSize , 64 ) ; int Cost = X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TTI :: TCC_Basic ) ? static_cast < int > ( TTI :: TCC_Free ) : Cost ; } return X86TTIImpl :: getIntImmCost ( Imm , Ty ) ; } </s>

Calculate the cost of materializing a 64-bit value .


<s> bool RISCVTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { auto & DL = I . getModule ( ) -> getDataLayout ( ) ; switch ( Intrinsic ) { default : return false ; case Intrinsic :: riscv_masked_atomicrmw_xchg_i32 : case Intrinsic :: riscv_masked_atomicrmw_add_i32 : case Intrinsic :: riscv_masked_atomicrmw_sub_i32 : case Intrinsic :: riscv_masked_atomicrmw_nand_i32 : case Intrinsic :: riscv_masked_atomicrmw_max_i32 : case Intrinsic :: riscv_masked_atomicrmw_min_i32 : case Intrinsic :: riscv_masked_atomicrmw_umax_i32 : case Intrinsic :: riscv_masked_atomicrmw_umin_i32 : case Intrinsic :: riscv_masked_cmpxchg_i32 : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . memVT = MVT :: i32 ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . offset = 0 ; Info . align = Align ( 4 ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case Intrinsic :: riscv_masked_strided_load : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / 8 ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case Intrinsic :: riscv_masked_strided_store : Info . opc = ISD :: INTRINSIC_VOID ; Info . ptrVal = I . getArgOperand ( 1 ) ; Info . memVT = getValueType ( DL , I . getArgOperand ( 0 ) -> getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getArgOperand ( 0 ) -> getType ( ) -> getScalarType ( ) ) / 8 ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOStore ; return true ; case Intrinsic :: riscv_seg2_load : case Intrinsic :: riscv_seg3_load : case Intrinsic :: riscv_seg4_load : case Intrinsic :: riscv_seg5_load : case Intrinsic :: riscv_seg6_load : case Intrinsic :: riscv_seg7_load : case Intrinsic :: riscv_seg8_load : Info . opc = ISD :: INTRINSIC_W_CHAIN ; Info . ptrVal = I . getArgOperand ( 0 ) ; Info . memVT = getValueType ( DL , I . getType ( ) -> getStructElementType ( 0 ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getStructElementType ( 0 ) -> getScalarType ( ) ) / 8 ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; } } </s>

Given an intrinsic , checks if on the target the intrinsic will need to map to a MemIntrinsicNode ( touches memory ) .


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { AttributeSet FnAttrs = MF . getFunction ( ) -> getAttributes ( ) ; ForCodeSize = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) || FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; Subtarget = & MF . getSubtarget < AArch64Subtarget > ( ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ; } </s>

runOnMachineFunction - Emit the function body .


<s> int HexagonMCInst :: getMinValue ( void ) const { const uint64_t F = MCID -> TSFlags ; unsigned isSigned = ( F >> HexagonII :: ExtentSignedPos ) & HexagonII :: ExtentSignedMask ; unsigned bits = ( F >> HexagonII :: ExtentBitsPos ) & HexagonII :: ExtentBitsMask ; if ( isSigned ) return - 1U << ( bits - 1 ) ; else return 0 ; } </s>

Return the minimal unsigned value possible given these KnownBits .

Hexagon Hexagon HexagonII::ExtentSignedPos HexagonII::ExtentSignedMask HexagonII::ExtentBitsPos HexagonII::ExtentBitsMask 1U 1 0


"Instr doesn't have FrameIndex operand!"

This method must be overriden to eliminate abstract frame indices from instructions which may use them .


<s> bool PPCAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; assert ( MI -> getOperand ( OpNo ) . isReg ( ) ) ; printOperand ( MI , OpNo ) ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const override { return true ; } </s>

spillCalleeSavedRegisters - Issues instruction ( s ) to spill all callee saved registers and returns true if it is n't possible / profitable to do so by issuing a series of store instructions via storeRegToStackSlot ( ) .


"%qE attribute ignored without -mcmse option."

"%qE attribute only applies to base type of a "

Called upon detection of the use of the cmse_nonsecure_call attribute , this function will check whether the attribute is allowed here and will add the attribute to the function type tree or otherwise issue a diagnostic . The reason we check this at declaration time is to only allow the use of the attribute with declarations of function pointers and not function declarations . This function checks NODE is of the expected type and issues diagnostics otherwise using NAME . If it is not of the expected type * NO_ADD_ATTRS will be set to true .


<s> StringRef ARMALFWriter :: getPassName ( ) const { return "ARMALFWriter" ; } </s>

getPassName - Return a nice clean name for a pass .


<s> const MINA32InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ; } </s>


<s> SDValue X86TargetLowering :: getRecipEstimate ( SDValue Op , SelectionDAG & DAG , int Enabled , int & RefinementSteps ) const { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ( VT == MVT :: f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v4f32 && Subtarget . hasSSE1 ( ) ) || ( VT == MVT :: v8f32 && Subtarget . hasAVX ( ) ) || ( VT == MVT :: v16f32 && Subtarget . useAVX512Regs ( ) ) ) { if ( VT == MVT :: f32 && Enabled == ReciprocalEstimate :: Unspecified ) return SDValue ( ) ; if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 1 ; unsigned Opcode = VT == MVT :: v16f32 ? X86ISD :: RCP14 : X86ISD :: FRCP ; return DAG . getNode ( Opcode , DL , VT , Op ) ; } if ( VT . getScalarType ( ) == MVT :: f16 && isTypeLegal ( VT ) && Subtarget . hasFP16 ( ) ) { if ( RefinementSteps == ReciprocalEstimate :: Unspecified ) RefinementSteps = 0 ; if ( VT == MVT :: f16 ) { SDValue Zero = DAG . getIntPtrConstant ( 0 , DL ) ; SDValue Undef = DAG . getUNDEF ( MVT :: v8f16 ) ; Op = DAG . getNode ( ISD :: SCALAR_TO_VECTOR , DL , MVT :: v8f16 , Op ) ; Op = DAG . getNode ( X86ISD :: RCP14S , DL , MVT :: v8f16 , Undef , Op ) ; return DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , MVT :: f16 , Op , Zero ) ; } return DAG . getNode ( X86ISD :: RCP14 , DL , VT , Op ) ; } return SDValue ( ) ; } </s>

Return a reciprocal estimate value for the input operand .


"failed to spill SGPR to VGPR when allocated"

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> void aarch64_general_init_builtins ( void ) { aarch64_init_fpsr_fpcr_builtins ( ) ; aarch64_init_fp16_types ( ) ; aarch64_init_bf16_types ( ) ; { aarch64_simd_switcher simd ; aarch64_init_simd_builtins ( ) ; } aarch64_init_crc32_builtins ( ) ; aarch64_init_builtin_rsqrt ( ) ; aarch64_init_rng_builtins ( ) ; tree ftype_jcvt = build_function_type_list ( intSI_type_node , double_type_node , NULL ) ; aarch64_builtin_decls [ AARCH64_JSCVT ] = aarch64_general_add_builtin ( "__builtin_aarch64_jcvtzs" , ftype_jcvt , AARCH64_JSCVT ) ; if ( ! TARGET_ILP32 ) aarch64_init_pauth_hint_builtins ( ) ; if ( TARGET_TME ) aarch64_init_tme_builtins ( ) ; if ( TARGET_MEMTAG ) aarch64_init_memtag_builtins ( ) ; } </s>

Initialize all builtins in the AARCH64_BUILTIN_GENERAL group .


<s> ScheduleHazardRecognizer * SIInstrInfo :: CreateTargetMIHazardRecognizer ( const InstrItineraryData * II , const ScheduleDAGMI * DAG ) const { if ( ! DAG -> hasVRegLiveness ( ) ) return new GCNHazardRecognizer ( DAG -> MF ) ; return TargetInstrInfo :: CreateTargetMIHazardRecognizer ( II , DAG ) ; } </s>

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation .


<s> bool TLCS900InstrInfo :: isUnpredicatedTerminator ( const MachineInstr * MI ) const { if ( ! MI -> isTerminator ( ) ) return false ; if ( MI -> isBranch ( ) && ! MI -> isBarrier ( ) ) return true ; if ( ! MI -> isPredicable ( ) ) return true ; return ! isPredicated ( MI ) ; } </s>

Returns true if the instruction is a terminator instruction that has not been predicated .


<s> void nds32_asm_file_start_for_isr ( void ) { int i ; for ( i = 0 ; i < NDS32_N_ISR_VECTORS ; i ++ ) { nds32_isr_vectors [ i ] . category = NDS32_ISR_NONE ; strcpy ( nds32_isr_vectors [ i ] . func_name , "" ) ; nds32_isr_vectors [ i ] . save_reg = NDS32_PARTIAL_SAVE ; nds32_isr_vectors [ i ] . nested_type = NDS32_NOT_NESTED ; nds32_isr_vectors [ i ] . security_level = 0 ; nds32_isr_vectors [ i ] . total_n_vectors = 0 ; strcpy ( nds32_isr_vectors [ i ] . nmi_name , "" ) ; strcpy ( nds32_isr_vectors [ i ] . warm_name , "" ) ; } } </s>

A helper function to handle isr stuff at the beginning of asm file .


<s> bool prefersVectorizedAddressing ( ) { return true ; } </s>

Return true if target does n't mind addresses in vectors .


<s> TargetPassConfig * SNESTargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new SNESPassConfig ( * this , PM ) ; } </s>

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes .


<s>
void
X86IntelInstPrinter
::
printPCRelImm
(
const
MCInst
*
MI
,
unsigned
OpNo
,
raw_ostream
&
O
)
{
const
MCOperand
&
Op
=
MI
->
getOperand
(
OpNo
)
;
if
(
Op
.
isImm
(
)
)
O
<<
formatImm
(
Op
.
getImm
(
)
)
;
else
{
assert
(
Op
.
isExpr
(
)
&&
"unknown pcrel immediate operand"
)
;
const
MCConstantExpr
*
BranchTarget
=
dyn_cast
<
MCConstantExpr
>
(
Op
.
getExpr
(
)
)
;
int64_t
Address
;
if
(
BranchTarget
&&
BranchTarget
->
evaluateAsAbsolute
(
Address
)
)
{
O
<<
formatHex
(
(
uint64_t
)
Address
)
;
}
else
{
O
<<
*
Op
.
getExpr
(
)
;
}
}
}
</s>


<s> void ARMTargetStreamer :: emitCurrentConstantPool ( ) { ConstantPools -> emitForCurrentSection ( Streamer ) ; ConstantPools -> clearCacheForCurrentSection ( Streamer ) ; } </s>

Callback used to implement the .ltorg directive .


<s>
void
MINA32DAGToDAGISel
::
Select
(
SDNode
*
N
)
{
if
(
N
->
isMachineOpcode
(
)
)
{
LLVM_DEBUG
(
errs
(
)
<<
"== "
;
N
->
dump
(
CurDAG
)
;
errs
(
)
<<
"\n"
)
;
N
->
setNodeId
(
1
)
;
return
;
}
if
(
trySelect
(
N
)
)
return
;
SelectCode
(
N
)
;
}
</s>

Main hook for targets to transform nodes into machine nodes .


<s> static unsigned getLinkageSize ( bool isPPC64 , bool isDarwinABI , bool isELFv2ABI ) { if ( isDarwinABI || isPPC64 ) return ( isELFv2ABI ? 4 : 6 ) * ( isPPC64 ? 8 : 4 ) ; return 8 ; } </s>

getLinkageSize - Return the size of the PowerPC ABI linkage area .


<s> const TGSIRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> bool X86InstrInfo :: findCommutedOpIndices ( MachineInstr * MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { switch ( MI -> getOpcode ( ) ) { case X86 :: CMPPDrri : case X86 :: CMPPSrri : case X86 :: VCMPPDrri : case X86 :: VCMPPSrri : case X86 :: VCMPPDYrri : case X86 :: VCMPPSYrri : { unsigned Imm = MI -> getOperand ( 3 ) . getImm ( ) & 0x7 ; switch ( Imm ) { case 0x00 : case 0x03 : case 0x04 : case 0x07 : SrcOpIdx1 = 1 ; SrcOpIdx2 = 2 ; return true ; } return false ; } case X86 :: VFMADDPDr231r : case X86 :: VFMADDPSr231r : case X86 :: VFMADDSDr231r : case X86 :: VFMADDSSr231r : case X86 :: VFMSUBPDr231r : case X86 :: VFMSUBPSr231r : case X86 :: VFMSUBSDr231r : case X86 :: VFMSUBSSr231r : case X86 :: VFNMADDPDr231r : case X86 :: VFNMADDPSr231r : case X86 :: VFNMADDSDr231r : case X86 :: VFNMADDSSr231r : case X86 :: VFNMSUBPDr231r : case X86 :: VFNMSUBPSr231r : case X86 :: VFNMSUBSDr231r : case X86 :: VFNMSUBSSr231r : case X86 :: VFMADDPDr231rY : case X86 :: VFMADDPSr231rY : case X86 :: VFMSUBPDr231rY : case X86 :: VFMSUBPSr231rY : case X86 :: VFNMADDPDr231rY : case X86 :: VFNMADDPSr231rY : case X86 :: VFNMSUBPDr231rY : case X86 :: VFNMSUBPSr231rY : SrcOpIdx1 = 2 ; SrcOpIdx2 = 3 ; return true ; default : return TargetInstrInfo :: findCommutedOpIndices ( MI , SrcOpIdx1 , SrcOpIdx2 ) ; } } </s>

Returns true iff the routine could find two commutable operands in the given machine instruction .


<s> inline void swap ( impl_ptr < T , D , C > & l , impl_ptr < T , D , C > & r ) SPIMPL_NOEXCEPT { l . swap ( r ) ; } </s>

Provide a fast substitute to std : :swap < Use > that also works with less standard-compliant compilers .


<s> void rs6000_xcoff_declare_object_name ( FILE * file , const char * name , tree decl ) { struct declare_alias_data data = { file , false } ; RS6000_OUTPUT_BASENAME ( file , name ) ; fputs ( ":\n" , file ) ; symtab_node :: get ( decl ) -> call_for_symbol_and_aliases ( rs6000_declare_alias , & data , true ) ; } </s>

This macro produces the initial definition of a object ( variable ) name . Because AIX assembler 's .set command has unexpected semantics , we output all aliases as alternative labels in front of the definition .


<s> bool WebAssemblyTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( AM . BaseOffs < 0 ) return false ; if ( AM . Scale != 0 ) return false ; return true ; } </s>

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target , for a load/store of the specified type .


<s> const GBZ80MCExpr * GBZ80MCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool Negated , MCContext & Ctx ) { return new ( Ctx ) GBZ80MCExpr ( Kind , Expr , Negated ) ; } </s>


<s> const TargetRegisterClass * SIInstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ; if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - 1 ) return MRI . getRegClass ( MI . getOperand ( OpNo ) . getReg ( ) ) ; unsigned RCID = Desc . OpInfo [ OpNo ] . RegClass ; return RI . getRegClass ( RCID ) ; } </s>

Return the correct register class for OpNo .


<s> rtx legitimize_pic_address ( rtx orig , machine_mode mode ATTRIBUTE_UNUSED , rtx reg ) { if ( GET_CODE ( orig ) == SYMBOL_REF || GET_CODE ( orig ) == LABEL_REF ) { if ( reg == 0 ) reg = gen_reg_rtx ( Pmode ) ; if ( flag_pic == NEAR_PIC ) { emit_insn ( gen_unspec_bro_addr ( reg , orig ) ) ; emit_insn ( gen_addsi3 ( reg , reg , pic_offset_table_rtx ) ) ; } else if ( flag_pic == FAR_PIC ) { emit_insn ( gen_unspec_got_addr ( reg , orig ) ) ; } return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS && XEXP ( XEXP ( orig , 0 ) , 0 ) == pic_offset_table_rtx ) return orig ; if ( reg == 0 ) { gcc_assert ( can_create_pseudo_p ( ) ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , 0 ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 0 ) , Pmode , reg ) ; offset = legitimize_pic_address ( XEXP ( XEXP ( orig , 0 ) , 1 ) , Pmode , base == reg ? 0 : reg ) ; emit_insn ( gen_addsi3 ( reg , base , offset ) ) ; return reg ; } return orig ; } </s>

Legitimize PIC addresses . If the address is already position-independent , we return ORIG . Newly generated position-independent addresses go into a reg . This is REG if nonzero , otherwise we allocate register ( s ) as necessary .


<s>
void
MCallGraph
::
dump
(
)
const
{
for
(
MCGSites
::
const_iterator
i
(
Sites
.
begin
(
)
)
,
ie
(
Sites
.
end
(
)
)
;
i
!=
ie
;
i
++
)
{
dbgs
(
)
<<
"  "
;
(
*
i
)
->
dump
(
false
)
;
dbgs
(
)
<<
"\n"
;
}
}
</s>

Dump the plan to stderr ( for debugging ) .


<s>
unsigned
getReg
(
)
const
override
{
assert
(
(
Kind
==
k_Register
||
Kind
==
k_WrappedRegister
)
&&
"Invalid access!"
)
;
return
Reg
.
RegNum
;
}
</s>

Returns the register associated with this edge .


<s> unsigned ARMBaseRegisterInfo :: getRegPressureLimit ( const TargetRegisterClass * RC , MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ; switch ( RC -> getID ( ) ) { default : return 0 ; case ARM :: tGPRRegClassID : return TFI -> hasFP ( MF ) ? 4 : 5 ; case ARM :: GPRRegClassID : { unsigned FP = TFI -> hasFP ( MF ) ? 1 : 0 ; return 10 - FP - ( STI . isR9Reserved ( ) ? 1 : 0 ) ; } case ARM :: SPRRegClassID : case ARM :: DPRRegClassID : return 32 - 10 ; } } </s>

Return the register pressure `` high water mark '' for the specific register class .


<s> bool AArch64AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ) return false ; if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'a' : PrintAsmMemoryOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; return false ; case 'w' : case 'x' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ 0 ] , O ) ; if ( MO . isImm ( ) && MO . getImm ( ) == 0 ) { unsigned Reg = ExtraCode [ 0 ] == 'w' ? AArch64 :: WZR : AArch64 :: XZR ; O << AArch64InstPrinter :: getRegisterName ( Reg ) ; return false ; } printOperand ( MI , OpNum , O ) ; return false ; case 'b' : case 'h' : case 's' : case 'd' : case 'q' : if ( MO . isReg ( ) ) { const TargetRegisterClass * RC ; switch ( ExtraCode [ 0 ] ) { case 'b' : RC = & AArch64 :: FPR8RegClass ; break ; case 'h' : RC = & AArch64 :: FPR16RegClass ; break ; case 's' : RC = & AArch64 :: FPR32RegClass ; break ; case 'd' : RC = & AArch64 :: FPR64RegClass ; break ; case 'q' : RC = & AArch64 :: FPR128RegClass ; break ; default : return true ; } return printAsmRegInClass ( MO , RC , false , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } } if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; if ( AArch64 :: GPR32allRegClass . contains ( Reg ) || AArch64 :: GPR64allRegClass . contains ( Reg ) ) return printAsmMRegister ( MO , 'x' , O ) ; return printAsmRegInClass ( MO , & AArch64 :: FPR128RegClass , true , O ) ; } printOperand ( MI , OpNum , O ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s> tree function_resolver :: resolve_uniform ( unsigned int nops , unsigned int nimm ) { unsigned int i , nargs ; type_suffix_index type ; if ( ! check_gp_argument ( nops + nimm , i , nargs ) || ( type = infer_vector_type ( i ) ) == NUM_TYPE_SUFFIXES ) return error_mark_node ; i += 1 ; for ( ; i < nargs - nimm ; ++ i ) if ( ! require_matching_vector_type ( i , type ) ) return error_mark_node ; for ( ; i < nargs ; ++ i ) if ( ! require_integer_immediate ( i ) ) return error_mark_node ; return resolve_to ( mode_suffix_id , type ) ; } </s>

Resolve a ( possibly predicated ) function that takes NOPS like-typed vector arguments followed by NIMM integer immediates . Return the function decl of the resolved function on success , otherwise report a suitable error and return error_mark_node .


<s>
SDValue
AArch64TargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
llvm_unreachable
(
"Don't know how to custom lower this!"
)
;
case
ISD
::
FADD
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
ADD_F128
)
;
case
ISD
::
FSUB
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
SUB_F128
)
;
case
ISD
::
FMUL
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
MUL_F128
)
;
case
ISD
::
FDIV
:
return
LowerF128ToCall
(
Op
,
DAG
,
RTLIB
::
DIV_F128
)
;
case
ISD
::
FP_TO_SINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
true
)
;
case
ISD
::
FP_TO_UINT
:
return
LowerFP_TO_INT
(
Op
,
DAG
,
false
)
;
case
ISD
::
SINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
true
)
;
case
ISD
::
UINT_TO_FP
:
return
LowerINT_TO_FP
(
Op
,
DAG
,
false
)
;
case
ISD
::
FP_ROUND
:
return
LowerFP_ROUND
(
Op
,
DAG
)
;
case
ISD
::
FP_EXTEND
:
return
LowerFP_EXTEND
(
Op
,
DAG
)
;
case
ISD
::
RETURNADDR
:
return
LowerRETURNADDR
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
LowerFRAMEADDR
(
Op
,
DAG
)
;
case
ISD
::
BlockAddress
:
return
LowerBlockAddress
(
Op
,
DAG
)
;
case
ISD
::
BRCOND
:
return
LowerBRCOND
(
Op
,
DAG
)
;
case
ISD
::
BR_CC
:
return
LowerBR_CC
(
Op
,
DAG
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddressELF
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
return
LowerGlobalTLSAddress
(
Op
,
DAG
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
SELECT
:
return
LowerSELECT
(
Op
,
DAG
)
;
case
ISD
::
SELECT_CC
:
return
LowerSELECT_CC
(
Op
,
DAG
)
;
case
ISD
::
SETCC
:
return
LowerSETCC
(
Op
,
DAG
)
;
case
ISD
::
VACOPY
:
return
LowerVACOPY
(
Op
,
DAG
)
;
case
ISD
::
VASTART
:
return
LowerVASTART
(
Op
,
DAG
)
;
case
ISD
::
BUILD_VECTOR
:
return
LowerBUILD_VECTOR
(
Op
,
DAG
,
getSubtarget
(
)
)
;
case
ISD
::
VECTOR_SHUFFLE
:
return
LowerVECTOR_SHUFFLE
(
Op
,
DAG
)
;
}
return
SDValue
(
)
;
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .


<s> const TargetRegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ; } </s>


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { unsigned OpId ; switch ( Inst . getOpcode ( ) ) { default : OpId = 0 ; break ; case ARM :: MVE_WLSTP_8 : case ARM :: MVE_WLSTP_16 : case ARM :: MVE_WLSTP_32 : case ARM :: MVE_WLSTP_64 : case ARM :: t2WLS : case ARM :: MVE_LETP : case ARM :: t2LEUpdate : OpId = 2 ; break ; case ARM :: t2LE : OpId = 1 ; break ; } if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ OpId ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; Target = Addr + Inst . getOperand ( OpId ) . getImm ( ) + 4 ; return true ; } </s>

Given a branch instruction try to get the address the branch targets .


<s> SDNode * LEGDAGToDAGISel :: Select ( SDNode * N ) { switch ( N -> getOpcode ( ) ) { case ISD :: Constant : return SelectMoveImmediate ( N ) ; } return SelectCode ( N ) ; } </s>


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && frame_pointer_needed ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( current_function_pretend_args_size || cfun -> machine -> uses_anonymous_args || current_function_calls_eh_return || current_function_calls_alloca || ! ( stack_adjust == 0 || ( frame_pointer_needed && stack_adjust == 4 ) ) ) return 0 ; saved_int_regs = arm_compute_save_reg_mask ( ) ; if ( stack_adjust == 4 && ! arm_arch5 ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( GET_CODE ( sibling ) == CALL_INSN ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && regs_ever_live [ PIC_OFFSET_TABLE_REGNUM ] ) return 0 ; } if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT && TARGET_FPA ) for ( regno = FIRST_FPA_REGNUM ; regno <= LAST_FPA_REGNUM ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s> bool SIFoldOperands :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; const SIMachineFunctionInfo * MFI = MF . getInfo < SIMachineFunctionInfo > ( ) ; bool IsIEEEMode = ST -> enableIEEEBit ( MF ) ; bool HasNSZ = MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ( ! HasNSZ && ! MI . getFlag ( MachineInstr :: FmNsz ) ) || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( 1 ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ; MachineOperand & Dst = MI . getOperand ( 0 ) ; if ( Dst . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; foldInstOperand ( MI , OpToFold ) ; } } return false ; } </s>

runOnMachineFunction - Emit the function body .


<s> int call26_operand ( rtx op , enum machine_mode mode ATTRIBUTE_UNUSED ) { if ( flag_pic ) return 1 ; if ( GET_CODE ( op ) == SYMBOL_REF ) return SYMBOL_REF_MODEL ( op ) != M32R_MODEL_LARGE ; return TARGET_CALL26 ; } </s>

Return 1 if OP is a function that can be called with the ` bl ' insn .


<s> static rtx load_cr_save ( int regno , rtx frame_reg_rtx , int offset , bool exit_func ) { rtx mem = gen_frame_mem_offset ( SImode , frame_reg_rtx , offset ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx_insn * insn = emit_move_insn ( reg , mem ) ; if ( ! exit_func && DEFAULT_ABI == ABI_V4 ) { rtx cr = gen_rtx_REG ( SImode , CR2_REGNO ) ; rtx set = gen_rtx_SET ( VOIDmode , reg , cr ) ; add_reg_note ( insn , REG_CFA_REGISTER , set ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } return reg ; } </s>

Restoring cr is a two step process : loading a reg from the frame save , then moving the reg to cr . For ABI_V4 we must let the unwinder know that the stack location is no longer valid at or before the stack deallocation , but we ca n't emit a cfa_restore for cr at the stack deallocation like we do for other registers . The trouble is that it is possible for the move to cr to be scheduled after the stack deallocation . So say exactly where cr is located on each of the two insns .


<s> bool SIRegisterInfo :: isFrameOffsetLegal ( const MachineInstr * MI , unsigned BaseReg , int64_t Offset ) const { if ( ! SIInstrInfo :: isMUBUF ( * MI ) ) return false ; int64_t NewOffset = Offset + getMUBUFInstrOffset ( MI ) ; return isUInt < 12 > ( NewOffset ) ; } </s>

Determine whether a given base register plus offset immediate is encodable to resolve a frame index .


<s>
SDValue
LC3TargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
SDLoc
dl
,
SelectionDAG
&
DAG
)
const
{
if
(
isVarArg
)
{
report_fatal_error
(
"VarArg not supported"
)
;
}
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_LC3
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
,
e
=
RVLocs
.
size
(
)
;
i
<
e
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
{
RetOps
.
push_back
(
Flag
)
;
}
return
DAG
.
getNode
(
LC3ISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
RetOps
)
;
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


<s> SDValue Cpu0TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case ISD :: BRCOND : return lowerBRCOND ( Op , DAG ) ; case ISD :: BlockAddress : return lowerBlockAddress ( Op , DAG ) ; case ISD :: JumpTable : return lowerJumpTable ( Op , DAG ) ; case ISD :: GlobalAddress : return lowerGlobalAddress ( Op , DAG ) ; case ISD :: SELECT : return lowerSELECT ( Op , DAG ) ; } return SDValue ( ) ; } </s>

Cpu0 Cpu0 ISD::BRCOND ISD::BlockAddress ISD::JumpTable ISD::GlobalAddress ISD::SELECT


<s> void DLXTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { } </s>

Lower the specified operand into the Ops vector .


<s> bool s390_can_use_simple_return_insn ( void ) { return true ; } </s>

Return true if the function can use simple_return to return outside of a shrink-wrapped region . At present shrink-wrapping is supported in all cases .


"Don't know how to handle that operation"


<s>
void
RISCVRegisterInfo
::
eliminateFrameIndex
(
MachineBasicBlock
::
iterator
II
,
int
SPAdj
,
unsigned
FIOperandNum
,
RegScavenger
*
RS
)
const
{
MachineInstr
&
MI
=
*
II
;
MachineFunction
&
MF
=
*
MI
.
getParent
(
)
->
getParent
(
)
;
DEBUG
(
errs
(
)
<<
"\nFunction : "
<<
MF
.
getName
(
)
<<
"\n"
;
errs
(
)
<<
"<--------->\n"
<<
MI
)
;
int
FrameIndex
=
MI
.
getOperand
(
FIOperandNum
)
.
getIndex
(
)
;
uint64_t
stackSize
=
MF
.
getFrameInfo
(
)
->
getStackSize
(
)
;
int64_t
spOffset
=
MF
.
getFrameInfo
(
)
->
getObjectOffset
(
FrameIndex
)
;
DEBUG
(
errs
(
)
<<
"FrameIndex : "
<<
FrameIndex
<<
"\n"
<<
"spOffset   : "
<<
spOffset
<<
"\n"
<<
"stackSize  : "
<<
stackSize
<<
"\n"
)
;
eliminateFI
(
MI
,
FIOperandNum
,
FrameIndex
,
stackSize
,
spOffset
)
;
}
</s>

This method must be overriden to eliminate abstract frame indices from instructions which may use them .

RISCV
RISCV
"\nFunction : "
"\n"
"<--------->\n"
"FrameIndex : "
"\n"
"spOffset   : "
"\n"
"stackSize  : "
"\n"


"MMIX DAG->DAG Pattern Instruction Selection"

getPassName - Return a nice clean name for a pass .


"unimplemented opcode in encodeInstruction()"

Encode the given Inst to bytes and append to CB .


<s>
CountValue
*
HexagonHardwareLoops
::
getTripCount
(
MachineLoop
*
L
)
const
{
const
MachineInstr
*
IV_Inst
=
getCanonicalInductionVariable
(
L
)
;
if
(
IV_Inst
==
0
)
return
0
;
const
MachineOperand
*
IV_Opnd
;
const
MachineOperand
*
InitialValue
;
if
(
!
L
->
contains
(
IV_Inst
->
getOperand
(
2
)
.
getMBB
(
)
)
)
{
InitialValue
=
&
IV_Inst
->
getOperand
(
1
)
;
IV_Opnd
=
&
IV_Inst
->
getOperand
(
3
)
;
}
else
{
InitialValue
=
&
IV_Inst
->
getOperand
(
3
)
;
IV_Opnd
=
&
IV_Inst
->
getOperand
(
1
)
;
}
while
(
(
IV_Opnd
=
IV_Opnd
->
getNextOperandForReg
(
)
)
)
{
const
MachineInstr
*
MI
=
IV_Opnd
->
getParent
(
)
;
if
(
L
->
contains
(
MI
)
&&
isCompareEqualsImm
(
MI
)
)
{
const
MachineOperand
&
MO
=
MI
->
getOperand
(
2
)
;
assert
(
MO
.
isImm
(
)
&&
"IV Cmp Operand should be 0"
)
;
int64_t
ImmVal
=
MO
.
getImm
(
)
;
const
MachineInstr
*
IV_DefInstr
=
MRI
->
getVRegDef
(
IV_Opnd
->
getReg
(
)
)
;
assert
(
L
->
contains
(
IV_DefInstr
->
getParent
(
)
)
&&
"IV definition should occurs in loop"
)
;
int64_t
iv_value
=
IV_DefInstr
->
getOperand
(
2
)
.
getImm
(
)
;
if
(
ImmVal
==
0
)
{
if
(
iv_value
!=
1
&&
iv_value
!=
1
)
{
return
0
;
}
return
new
CountValue
(
InitialValue
->
getReg
(
)
,
iv_value
>
0
)
;
}
else
{
assert
(
InitialValue
->
isReg
(
)
&&
"Expecting register for init value"
)
;
const
MachineInstr
*
DefInstr
=
MRI
->
getVRegDef
(
InitialValue
->
getReg
(
)
)
;
if
(
DefInstr
&&
DefInstr
->
getOpcode
(
)
==
Hexagon
::
TFRI
)
{
int64_t
count
=
ImmVal
DefInstr
->
getOperand
(
1
)
.
getImm
(
)
;
if
(
(
count
%
iv_value
)
!=
0
)
{
return
0
;
}
return
new
CountValue
(
count
/
iv_value
)
;
}
}
}
}
return
0
;
}
</s>


"Copy one register into another with a different width"


<s> void SystemZMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; MemOpsEmitted = 0 ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = MCII . get ( MI . getOpcode ( ) ) . getSize ( ) ; unsigned ShiftValue = ( Size * 8 ) - 8 ; for ( unsigned I = 0 ; I != Size ; ++ I ) { OS << uint8_t ( Bits >> ShiftValue ) ; ShiftValue -= 8 ; } } </s>


<s> bool insn_defines_reg ( unsigned int regno1 , unsigned int regno2 , rtx_insn * insn ) { df_ref def ; FOR_EACH_INSN_DEF ( def , insn ) if ( DF_REF_REG_DEF_P ( def ) && ! DF_REF_IS_ARTIFICIAL ( def ) && ( regno1 == DF_REF_REGNO ( def ) || regno2 == DF_REF_REGNO ( def ) ) ) return true ; return false ; } </s>

Function checks if instruction INSN defines register number REGNO1 or REGNO2 .


"Constant Island pass failed to converge!"

"Branch Fix Up pass failed to converge!"


<s> bool AArch64TargetLowering :: isLegalInterleavedAccessType ( VectorType * VecTy , const DataLayout & DL ) const { unsigned VecSize = DL . getTypeSizeInBits ( VecTy ) ; unsigned ElSize = DL . getTypeSizeInBits ( VecTy -> getElementType ( ) ) ; if ( VecTy -> getNumElements ( ) < 2 ) return false ; if ( ElSize != 8 && ElSize != 16 && ElSize != 32 && ElSize != 64 ) return false ; return VecSize == 64 || VecSize % 128 == 0 ; } </s>

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal .


<s> static machine_mode maybe_split_mode ( machine_mode mode ) { if ( COMPLEX_MODE_P ( mode ) ) return GET_MODE_INNER ( mode ) ; if ( mode == TImode ) return DImode ; return VOIDmode ; } </s>

Return the number of pieces to use when dealing with a pseudo of * PMODE . Alter * PMODE if we return a number greater than one .


<s> void HexagonSubtarget :: adjustSchedDependency ( SUnit * Src , SUnit * Dst , SDep & Dep ) const { MachineInstr * SrcInst = Src -> getInstr ( ) ; MachineInstr * DstInst = Dst -> getInstr ( ) ; if ( ! Src -> isInstr ( ) || ! Dst -> isInstr ( ) ) return ; const HexagonInstrInfo * QII = getInstrInfo ( ) ; SmallSet < SUnit * , 4 > ExclSrc ; SmallSet < SUnit * , 4 > ExclDst ; if ( QII -> canExecuteInBundle ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( 0 ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == 1 ) { Register DReg = DstInst -> getOperand ( 0 ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ 0 ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - 1 ; for ( unsigned OpNum = 0 ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) { UseIdx = OpNum ; break ; } } int DLatency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcInst , 0 , * DDst , UseIdx ) ) ; DLatency = std :: max ( DLatency , 0 ) ; Dep . setLatency ( ( unsigned ) DLatency ) ; } ExclSrc . clear ( ) ; ExclDst . clear ( ) ; if ( EnableDotCurSched && QII -> isToBeScheduledASAP ( * SrcInst , * DstInst ) && isBestZeroLatency ( Src , Dst , QII , ExclSrc , ExclDst ) ) { Dep . setLatency ( 0 ) ; return ; } updateLatency ( * SrcInst , * DstInst , Dep ) ; } </s>

Perform target specific adjustments to the latency of a schedule dependency .


<s> void ARMTargetELFStreamer :: emitLabel ( MCSymbol * Symbol ) { ARMELFStreamer & Streamer = getStreamer ( ) ; if ( ! Streamer . IsThumb ) return ; const MCSymbolData & SD = Streamer . getOrCreateSymbolData ( Symbol ) ; unsigned Type = MCELF :: GetType ( SD ) ; if ( Type == ELF_STT_Func || Type == ELF_STT_GnuIFunc ) Streamer . EmitThumbFunc ( Symbol ) ; } </s>

Emit a label for Symbol into the current section .


<s> unsigned getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: OperandValueKind Opd1Info = TTI :: OK_AnyValue , TTI :: OperandValueKind Opd2Info = TTI :: OK_AnyValue , TTI :: OperandValueProperties Opd1PropInfo = TTI :: OP_None , TTI :: OperandValueProperties Opd2PropInfo = TTI :: OP_None , ArrayRef < const Value * > Args = ArrayRef < const Value * > ( ) , const Instruction * CxtI = nullptr ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; switch ( ISD ) { default : return BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; case ISD :: MUL : case ISD :: SDIV : case ISD :: UDIV : case ISD :: UREM : return 64 * BaseT :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; } } </s>

This is an approximation of reciprocal throughput of a math/logic op .

Lanai ISD::MUL ISD::SDIV ISD::UDIV ISD::UREM 64


<s> unsigned getPointerSize ( ) const { return 4 ; } </s>

Layout pointer size in bytes , rounded up to a whole number of bytes .


<s>
SDValue
BPFTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
IsVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
const
SDLoc
&
DL
,
SelectionDAG
&
DAG
)
const
{
unsigned
Opc
=
BPFISD
::
RET_FLAG
;
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
CCState
CCInfo
(
CallConv
,
IsVarArg
,
MF
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
if
(
MF
.
getFunction
(
)
.
getReturnType
(
)
->
isAggregateType
(
)
)
{
fail
(
DL
,
DAG
,
"only integer returns supported"
)
;
return
DAG
.
getNode
(
Opc
,
DL
,
MVT
::
Other
,
Chain
)
;
}
CCInfo
.
AnalyzeReturn
(
Outs
,
getHasAlu32
(
)
RetCC_BPF32
:
RetCC_BPF64
)
;
SDValue
Flag
;
SmallVector
<
SDValue
,
4
>
RetOps
(
1
,
Chain
)
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
Chain
=
DAG
.
getCopyToReg
(
Chain
,
DL
,
VA
.
getLocReg
(
)
,
OutVals
[
i
]
,
Flag
)
;
Flag
=
Chain
.
getValue
(
1
)
;
RetOps
.
push_back
(
DAG
.
getRegister
(
VA
.
getLocReg
(
)
,
VA
.
getLocVT
(
)
)
)
;
}
RetOps
[
0
]
=
Chain
;
if
(
Flag
.
getNode
(
)
)
RetOps
.
push_back
(
Flag
)
;
return
DAG
.
getNode
(
Opc
,
DL
,
MVT
::
Other
,
RetOps
)
;
}
</s>


<s> unsigned LEGInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { assert ( 0 && "Unimplemented" ) ; return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s> bool AMDGPUStructurizeCFG :: runOnRegion ( Region * R , RGPassManager & RGM ) { if ( R -> isTopLevelRegion ( ) ) return false ; Func = R -> getEntry ( ) -> getParent ( ) ; ParentRegion = R ; DT = & getAnalysis < DominatorTree > ( ) ; orderNodes ( ) ; collectInfos ( ) ; createFlow ( ) ; insertConditions ( false ) ; insertConditions ( true ) ; setPhiValues ( ) ; rebuildSSA ( ) ; Order . clear ( ) ; Visited . clear ( ) ; DeletedPhis . clear ( ) ; AddedPhis . clear ( ) ; Predicates . clear ( ) ; Conditions . clear ( ) ; Loops . clear ( ) ; LoopPreds . clear ( ) ; LoopConds . clear ( ) ; return true ; } </s>


<s> bool bfin_expand_cpymem ( rtx dst , rtx src , rtx count_exp , rtx align_exp ) { rtx srcreg , destreg , countreg ; HOST_WIDE_INT align = 0 ; unsigned HOST_WIDE_INT count = 0 ; if ( GET_CODE ( align_exp ) == CONST_INT ) align = INTVAL ( align_exp ) ; if ( GET_CODE ( count_exp ) == CONST_INT ) { count = INTVAL ( count_exp ) ; if ( ! TARGET_INLINE_ALL_STRINGOPS && count > 64 ) return false ; } if ( optimize_size ) { if ( count == 2 && align < 2 ) return false ; if ( count == 4 && align < 4 ) return false ; if ( count != 1 && count != 2 && count != 4 ) return false ; } if ( align < 2 && count != 1 ) return false ; destreg = copy_to_mode_reg ( Pmode , XEXP ( dst , 0 ) ) ; if ( destreg != XEXP ( dst , 0 ) ) dst = replace_equiv_address_nv ( dst , destreg ) ; srcreg = copy_to_mode_reg ( Pmode , XEXP ( src , 0 ) ) ; if ( srcreg != XEXP ( src , 0 ) ) src = replace_equiv_address_nv ( src , srcreg ) ; if ( count != 0 && align >= 2 ) { unsigned HOST_WIDE_INT offset = 0 ; if ( align >= 4 ) { if ( ( count & ~ 3 ) == 4 ) { single_move_for_cpymem ( dst , src , SImode , offset ) ; offset = 4 ; } else if ( count & ~ 3 ) { HOST_WIDE_INT new_count = ( ( count >> 2 ) & 0x3fffffff ) - 1 ; countreg = copy_to_mode_reg ( Pmode , GEN_INT ( new_count ) ) ; emit_insn ( gen_rep_movsi ( destreg , srcreg , countreg , destreg , srcreg ) ) ; cfun -> machine -> has_loopreg_clobber = true ; } if ( count & 2 ) { single_move_for_cpymem ( dst , src , HImode , offset ) ; offset += 2 ; } } else { if ( ( count & ~ 1 ) == 2 ) { single_move_for_cpymem ( dst , src , HImode , offset ) ; offset = 2 ; } else if ( count & ~ 1 ) { HOST_WIDE_INT new_count = ( ( count >> 1 ) & 0x7fffffff ) - 1 ; countreg = copy_to_mode_reg ( Pmode , GEN_INT ( new_count ) ) ; emit_insn ( gen_rep_movhi ( destreg , srcreg , countreg , destreg , srcreg ) ) ; cfun -> machine -> has_loopreg_clobber = true ; } } if ( count & 1 ) { single_move_for_cpymem ( dst , src , QImode , offset ) ; } return true ; } return false ; } </s>

Expand a string move operation of COUNT_EXP bytes from SRC to DST , with alignment ALIGN_EXP . Return true if successful , false if we should fall back on a different method .


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved ( "stack-protector" ) ; FunctionPass :: getAnalysisUsage ( AU ) ; } </s>

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this .


<s> const uint32_t * X86RegisterInfo :: getCallPreservedMask ( CallingConv :: ID CC ) const { bool HasAVX = TM . getSubtarget < X86Subtarget > ( ) . hasAVX ( ) ; if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ; if ( CC == CallingConv :: Cold ) return CSR_MostRegs_64_RegMask ; if ( IsWin64 ) return CSR_Win64_RegMask ; return CSR_64_RegMask ; } </s>

Return a mask of call-preserved registers for the given calling convention on the current function .


<s> bool isLiveIn ( int FI ) { for ( unsigned i = 0 , e = LiveInFI . size ( ) ; i < e ; ++ i ) if ( FI == LiveInFI [ i ] ) return true ; return false ; } </s>

Returns true if this VPValue is a live-in , i.e . defined outside the VPlan .


<s> bool RISCVPassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ; } </s>

This method should install a ( global ) instruction selector pass , which converts possibly generic instructions to fully target-specific instructions , thereby constraining all generic virtual registers to register classes .


<s> void neon_pairwise_reduce ( rtx op0 , rtx op1 , machine_mode mode , rtx ( * reduc ) ( rtx , rtx , rtx ) ) { machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int i , parts = GET_MODE_SIZE ( mode ) / GET_MODE_SIZE ( inner ) ; rtx tmpsum = op1 ; for ( i = parts / 2 ; i >= 1 ; i /= 2 ) { rtx dest = ( i == 1 ) ? op0 : gen_reg_rtx ( mode ) ; emit_insn ( reduc ( dest , tmpsum , tmpsum ) ) ; tmpsum = dest ; } } </s>

Output a sequence of pairwise operations to implement a reduction . NOTE : We do `` too much work '' here , because pairwise operations work on two registers-worth of operands in one go . Unfortunately we ca n't exploit those extra calculations to do the full operation in fewer steps , I do n't think . Although all vector elements of the result but the first are ignored , we actually calculate the same result in each of the elements . An alternative such as initially loading a vector with zero to use as each of the second operands would use up an additional register and take an extra instruction , for no particular gain .


<s> virtual const XNCMSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .


<s> static unsigned int rs6000_hard_regno_nregs_hook ( unsigned int regno , machine_mode mode ) { return rs6000_hard_regno_nregs [ mode ] [ regno ] ; } </s>


<s> void lm32_expand_prologue ( void ) { rtx insn ; lm32_compute_frame_size ( get_frame_size ( ) ) ; if ( current_frame_info . total_size > 0 ) { stack_adjust ( - current_frame_info . total_size ) ; if ( current_frame_info . reg_save_mask != 0 ) expand_save_restore ( & current_frame_info , 0 ) ; if ( frame_pointer_needed == 1 ) { insn = emit_move_insn ( frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; insn = emit_add ( frame_pointer_rtx , frame_pointer_rtx , GEN_INT ( current_frame_info . args_size + current_frame_info . callee_size + current_frame_info . locals_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; } emit_insn ( gen_blockage ( ) ) ; } } </s>

Create and emit instructions for a functions prologue .


Generate compact unwind encoding for the function based on the CFI instructions .


<s> int getInstrLatency ( const InstrItineraryData * ItinData , SDNode * Node ) const override { return 1 ; } </s>

Compute the instruction latency of a given instruction .


<s> static int stackSlotSize ( ) { return 4 ; } </s>


<s> static void insn_dependent_p_1 ( rtx x , rtx pat ATTRIBUTE_UNUSED , void * data ) { rtx * pinsn = ( rtx * ) data ; if ( * pinsn && reg_mentioned_p ( x , * pinsn ) ) * pinsn = NULL_RTX ; } </s>

A helper routine for insn_dependent_p called through note_stores .


<s> SDNode * SITargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const SIInstrInfo * TII = static_cast < const SIInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; Node = AdjustRegClass ( Node , DAG ) ; if ( TII -> isMIMG ( Node -> getMachineOpcode ( ) ) ) adjustWritemask ( Node , DAG ) ; return foldOperands ( Node , DAG ) ; } </s>

Fold the instructions after selecting them .


<s> bool isImm ( ) const { return Kind == K_Immediate ; } </s>


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , LLT MemTy , MachinePointerInfo & MPO ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; auto MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ; return MIRBuilder . buildLoad ( Res , Addr , * MMO ) ; } </s>

Build and insert a G_LOAD instruction , while constructing the MachineMemOperand .