The CPU decodes the instructions and generates control words in
A. prefetch stage
B. D1 (first decode) stage
C. D2 (second decode) stage
D. final stage
Answer:A
The CPU decodes the instructions and generates control words in
A. prefetch stage B. D1 (first decode) stage C. D2 (second decode) stage D. final stage
Explanation: In D1 stage, the CPU decodes the instructions and generates control words. For simple RISC instructions, only single control word is enough for starting the execution.