Explanation: The time periods of the sample and hold control voltage during which the voltage across capacitor is equal to the input voltage are called sample period. 10. During which period the op-amps output of sample and hold circuits is processed?
A. None of the mentioned
B. Sample and hold period
C. Sample period
D. Hold period
Answer:A
Explanation: The time periods of the sample and hold control voltage during which the voltage across capacitor is equal to the input voltage are called sample period. 10. During which period the op-amps output of sample and hold circuits is processed?
A. None of the mentioned B. Sample and hold period C. Sample period D. Hold period
Explanation: Hold period is the period during which the voltage across the capacitor is constant and the output of the op-amp is processed or observed during hold periods. 11. Which IC is mostly preferred for sample and hold circuit?