The stage in which the CPU generates address for data memory references in this stage is
A. prefetch stage
B. D1 (first decode) stage
C. D2 (second decode) stage
D. execution stage
Answer:A
The stage in which the CPU generates address for data memory references in this stage is
A. prefetch stage B. D1 (first decode) stage C. D2 (second decode) stage D. execution stage
Explanation: In the D2 (second decode) stage, CPU generates address for data memory references in this stage. This stage is required where the control word from D1 stage is again decoded for final execution.