The number of idle states (Ti), that are allowed between two INTA cycles, to meet the 8259A speed and cascade address output delay is
A. 1
B. 2
C. 3
D. 4
Answer:A
The number of idle states (Ti), that are allowed between two INTA cycles, to meet the 8259A speed and cascade address output delay is
A. 1 B. 2 C. 3 D. 4
Explanation: The 80286 allows three idle states (Ti) between the two INTA cycles, to meet the 8259A speed and cascade address output delay.