In the signal integrate phase, the differential input voltage between IN LO(input low) and IN HI(input high) pins is integrated by the internal integrator for a fixed period of
A. 256 clock cycles
B. 1024 clock cycles
C. 2048 clock cycles
D. 4096 clock cycles
Answer:A
In the signal integrate phase, the differential input voltage between IN LO(input low) and IN HI(input high) pins is integrated by the internal integrator for a fixed period of
A. 256 clock cycles B. 1024 clock cycles C. 2048 clock cycles D. 4096 clock cycles
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference between input low and input high.