The minimum number of clock cycles required in an input pulse width of RESET pin is
A. 4
B. 2
C. 8
D. 16
Answer:A
The minimum number of clock cycles required in an input pulse width of RESET pin is
A. 4 B. 2 C. 8 D. 16
Explanation: The active high RESET input clears the internal logic of 80286, and re-initializes it. The reset input pulse width should be at least 16 clock cycles.