What is/are the necessity/ies of Simulation Process in VHDL?
A. Requirement to test designs before implementation & usage
B. Reduction of development time
C. Decrease the time to market
D. All of the above
Answer:A
What is/are the necessity/ies of Simulation Process in VHDL?
A. Requirement to test designs before implementation & usage B. Reduction of development time C. Decrease the time to market D. All of the above