For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of
A. super pipelined technique
B. multiple instruction issue
C. super pipelined technique and multiple instruction issue
D. none of the mentioned
Answer:A
For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of
A. super pipelined technique B. multiple instruction issue C. super pipelined technique and multiple instruction issue D. none of the mentioned
Explanation: For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of multiple instruction issue.