The anded output of the bits of the interrupt register and the mask register are set as input of:
A. Priority decoder
B. Priority encoder
C. Process id encoder
D. Multiplexer
Answer:A
The anded output of the bits of the interrupt register and the mask register are set as input of:
A. Priority decoder B. Priority encoder C. Process id encoder D. Multiplexer
Explanation: In a parallel priority system, the priority of the device is obtained by anding the contents of the interrupt register and the mask register.