The on-chip cache is controlled by
A. Cache disable(CD)
B. No write through(NW)
C. Cache disable and No write through
D. none of the mentioned
Answer:A
The on-chip cache is controlled by
A. Cache disable(CD) B. No write through(NW) C. Cache disable and No write through D. none of the mentioned
Explanation: Cache disable(CD) and No write through(NW) bits of control register CR0. To completely disable cache, the CD and NW bits must be 11.