The instruction at which the exception is generated, but the processor extension registers contain the address of failing instruction is
A. LTR
B. INS
C. CTS
D. ESC
Answer:A
The instruction at which the exception is generated, but the processor extension registers contain the address of failing instruction is
A. LTR B. INS C. CTS D. ESC
Explanation: At the ESC instruction, the exception is generated, but the processor extension registers contain the address of failing instruction.