2184
Applicable Platforms
Language : VHDL (Prevalence = Undetermined)
Language : Verilog (Prevalence = Undetermined)
Operating_System : Not OS-Specific (Prevalence = Undetermined)
Architecture : Not Architecture-Specific (Prevalence = Undetermined)
Technology : System on Chip (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Confidentiality
Integrity
Availability
Access Control
Accountability
Authentication
Authorization
Non-Repudiation
Varies by Context
CWE Version 4.14
CWE-1252: CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations
CWE-1252: CPU Hardware Not Configured to
Support Exclusivity of Write and Execute Operations 2056
Potential Mitigations
Phase: Architecture and Design
Whenever there are multiple, physically different copies of the same value that might change
and the process to update them is not instantaneous and atomic, it is impossible to assert that
the original and shadow copies will always be in sync - there will always be a time period when
they are out of sync. To mitigate the consequential risk, the recommendations essentially are:
Make this out-of-sync time period as small as possible, and Make the update process as robust
as possible.
Effectiveness = Moderate
Demonstrative Examples
Example 1:
Suppose a processor's Memory Management Unit (MMU) has 5 other shadow MMUs to distribute
its workload for its various cores. Each MMU has the start address and end address of "accessible"
memory. Any time this accessible range changes (as per the processor's boot status), the main
MMU sends an update message to all the shadow MMUs.
Suppose the interconnect fabric does not prioritize such "update" packets over other general traffic
packets. This introduces a race condition. If an attacker can flood the target with enough messages
so that some of those attack packets reach the target before the new access ranges gets updated,
then the attacker can leverage this scenario.
MemberOf Relationships
This MemberOf relationships table shows additional CWE Catgeories and Views that reference this
weakness as a member. This information is often useful in understanding where a weakness fits
within the context of external information sources.
Nature Type ID Name Page
MemberOf 1202 Memory and Storage Issues 1194 2472
MemberOf 1415 Comprehensive Categorization: Resource Control 1400 2544
Notes
Research Gap
Issues related to state and cache - creation, preservation, and update - are a significant gap in
CWE that is expected to be addressed in future versions. It has relationships to concurrency and
synchronization, incorrect behavior order, and other areas that already have some coverage in
CWE, although the focus has typically been on independent processes on the same operating
system - not on independent systems that are all a part of a larger system-of-systems.
CWE-1252: CPU Hardware Not Configured to Support Exclusivity of Write and
Execute Operations
Weakness ID : 1252
Structure : Simple
Abstraction : Base
Description
The CPU is not configured to provide hardware support for exclusivity of write and execute
operations on memory. This allows an attacker to execute data from all of memory.
Extended Description
CPUs provide a special bit that supports exclusivity of write and execute operations. This bit
is used to segregate areas of memory to either mark them as code (instructions, which can be
CWE Version 4.14
CWE-1252: CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations
CWE-1252: CPU Hardware Not Configured to
Support Exclusivity of Write and Execute Operations