title: x86/AMD: missing IOMMU TLB flushing
description: The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.
Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.
affected:
{
defaultStatus: unknown
product: Xen
vendor: Xen
versions:
status: unknown, version: consult Xen advisory XSA-442
}
workarounds: Not passing through physical devices to guests will avoid the vulnerability.