1997
Relevant to the view "Research Concepts" (CWE-1000)
Nature Type ID Name Page
ChildOf 1419 Incorrect Initialization of Resource 2280
Applicable Platforms
Language : Verilog (Prevalence = Undetermined)
Language : VHDL (Prevalence = Undetermined)
Technology : Not Technology-Specific (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Confidentiality
Integrity
Availability
Access Control
Varies by Context
Degradation of system functionality, or loss of access
control enforcement can occur.
Potential Mitigations
Phase: Architecture and Design
During hardware design, all the system parameters and register defaults must be reviewed to
identify security sensitive settings.
Phase: Implementation
The default values of these security sensitive settings need to be defined as part of the design
review phase.
Phase: Testing
Testing phase should use automated tools to test that values are configured per design
specifications.
Demonstrative Examples
Example 1:
Consider example design module system verilog code shown below. The register_example module
is an example parameterized module that defines two parameters, REGISTER_WIDTH and
REGISTER_DEFAULT. Register_example module defines a Secure_mode setting, which when set
makes the register content read-only and not modifiable by software writes. register_top module
instantiates two registers, Insecure_Device_ID_1 and Insecure_Device_ID_2. Generally, registers
containing device identifier values are required to be read only to prevent any possibility of software
modifying these values.
Example Language: Verilog (Bad)
// Parameterized Register module example
// Secure_mode : REGISTER_DEFAULT[0] : When set to 1 register is read only and not writable//
module register_example
#(
parameter REGISTER_WIDTH = 8, // Parameter defines width of register, default 8 bits
parameter [REGISTER_WIDTH-1:0] REGISTER_DEFAULT = 2**REGISTER_WIDTH -2 // Default value of register
computed from Width. Sets all bits to 1s except bit 0 (Secure _mode)
)
(
input [REGISTER_WIDTH-1:0] Data_in,
input Clk,
input resetn,
input write,
output reg [REGISTER_WIDTH-1:0] Data_out
);
reg Secure_mode;
always @(posedge Clk or negedge resetn)
CWE Version 4.14
CWE-1221: Incorrect Register Defaults or Module Parameters
CWE-1221: Incorrect Register Defaults or Module Parameters