2158
MemberOf Relationships
This MemberOf relationships table shows additional CWE Catgeories and Views that reference this
weakness as a member. This information is often useful in understanding where a weakness fits
within the context of external information sources.
Nature Type ID Name Page
MemberOf 1195 Manufacturing and Life Cycle Management Concerns 1194 2469
MemberOf 1396 Comprehensive Categorization: Access Control 1400 2519
Notes
Maintenance
This entry might be subject to CWE Scope Exclusion SCOPE.SITUATIONS (Focus on situations
in which weaknesses may appear); SCOPE.HUMANPROC (Human/organizational process; and/
or SCOPE.CUSTREL (Not customer-relevant).
Maintenance
This entry is still under development and will continue to see updates and content improvements.
Related Attack Patterns
CAPEC-ID Attack Pattern Name
1 Accessing Functionality Not Properly Constrained by ACLs
180 Exploiting Incorrectly Configured Access Control Security Levels
References
[REF-1113]Muhammad Yasin, Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf,
Jeyavijayan (JV) Rajendran and Ozgur Sinanoglu. "Provably-Secure Logic Locking: From Theory
To Practice". < https://dl.acm.org/doi/10.1145/3133956.3133985 >.2023-04-07.
[REF-1114]Muhammad Yasin, Jeyavijayan (JV) Rajendran and Ozgur Sinanoglu. "Trustworthy
Hardware Design: Combinational Logic Locking Techniques". < https://link.springer.com/
book/10.1007/978-3-030-15334-2 >.2023-04-07.
CWE-1298: Hardware Logic Contains Race Conditions
Weakness ID : 1298
Structure : Simple
Abstraction : Base
Description
A race condition in the hardware logic results in undermining security guarantees of the system.
Extended Description
A race condition in logic circuits typically occurs when a logic gate gets inputs from signals that
have traversed different paths while originating from the same source. Such inputs to the gate can
change at slightly different times in response to a change in the source signal. This results in a
timing error or a glitch (temporary or permanent) that causes the output to change to an unwanted
state before settling back to the desired state. If such timing errors occur in access control logic
or finite state machines that are implemented in security sensitive flows, an attacker might exploit
them to circumvent existing protections.
Relationships
The table(s) below shows the weaknesses and high level categories that are related to this
weakness. These relationships are defined as ChildOf, ParentOf, MemberOr and give insight to
CWE Version 4.14
CWE-1298: Hardware Logic Contains Race Conditions
CWE-1298: Hardware Logic Contains Race Conditions