2176
Weakness Ordinalities
Primary :
Applicable Platforms
Language : Not Language-Specific (Prevalence = Undetermined)
Operating_System : Not OS-Specific (Prevalence = Undetermined)
Architecture : Not Architecture-Specific (Prevalence = Undetermined)
Technology : Not Technology-Specific (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Access Control
Authentication
Authorization
Varies by Context
Potential Mitigations
Phase: Implementation
Design checks should be performed to identify any uninitialized flip-flops used for security-critical
functions.
Phase: Architecture and Design
All registers holding security-critical information should be set to a specific value on reset.
Demonstrative Examples
Example 1:
Shown below is a positive clock edge triggered flip-flop used to implement a lock bit for test
and debug interface. When the circuit is first brought out of reset, the state of the flip-flop will be
unknown until the enable input and D-input signals update the flip-flop state. In this example, an
attacker can reset the device until the test and debug interface is unlocked and access the test
interface until the lock signal is driven to a known state by the logic.
Example Language: Verilog (Bad)
always @(posedge clk) begin
if (en) lock_jtag <= d;
end
The flip-flop can be set to a known value (0 or 1) on reset, but requires that the logic explicitly
update the output of the flip-flop if the reset signal is active.
CWE Version 4.14
CWE-1272: Sensitive Information Uncleared Before Debug/Power State Transition
CWE-1272: Sensitive Information Uncleared Before Debug/Power State Transition