2076
Operating_System : Not OS-Specific (Prevalence = Undetermined)
Architecture : Not Architecture-Specific (Prevalence = Undetermined)
Technology : Memory Hardware (Prevalence = Undetermined)
Technology : Processor Hardware (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Confidentiality
Integrity
Availability
Modify Memory
Read Memory
DoS: Instability
High
Detection Methods
Manual Analysis
Create a high privilege memory block of any arbitrary size. Attempt to create a lower privilege
memory block with an overlap of the high privilege memory block. If the creation attempt works,
fix the hardware. Repeat the test.
Effectiveness = High
Potential Mitigations
Phase: Architecture and Design
Ensure that memory regions are isolated as intended and that access control (read/write) policies
are used by hardware to protect privileged software.
Phase: Implementation
For all of the programmable memory protection regions, the memory protection unit (MPU)
design can define a priority scheme. For example: if three memory regions can be programmed
(Region_0, Region_1, and Region_2), the design can enforce a priority scheme, such that, if a
system address is within multiple regions, then the region with the lowest ID takes priority and
the access-control policy of that region will be applied. In some MPU designs, the priority scheme
can also be programmed by trusted software. Hardware logic or trusted firmware can also check
for region definitions and block programming of memory regions with overlapping addresses.
The memory-access-control-check filter can also be designed to apply a policy filter to all of the
overlapping ranges, i.e., if an address is within Region_0 and Region_1, then access to this
address is only granted if both Region_0 and Region_1 policies allow the access.
Effectiveness = High
Demonstrative Examples
Example 1:
For example, consider a design with a 16-bit address that has two software privilege levels:
Privileged_SW and Non_privileged_SW. To isolate the system memory regions accessible by
these two privilege levels, the design supports three memory regions: Region_0, Region_1, and
Region_2.
Each region is defined by two 32 bit registers: its range and its access policy.
• Address_range[15:0]: specifies the Base address of the region
• Address_range[31:16]: specifies the size of the region
• Access_policy[31:0]: specifies what types of software can access a region and which actions
are allowed
Certain bits of the access policy are defined symbolically as follows:
CWE Version 4.14
CWE-1260: Improper Handling of Overlap Between Protected Memory Ranges
CWE-1260: Improper Handling of Overlap Between Protected Memory Ranges