2301
A processor with this weakness will store the value of untrusted_arg (which may be provided by an
attacker) to the stack, which is trusted memory. Additionally, this store operation will save this value
in some microarchitectural buffer, for example, the store buffer.
In this code sequence, trusted_ptr is dereferenced while the attacker forces a page fault. The
faulting load causes the processor to mis-speculate by forwarding untrusted_arg as the (transient)
load result. The processor then uses untrusted_arg for the pointer dereference. After the fault
has been handled and the load has been re-issued with the correct argument, secret-dependent
information stored at the address of trusted_ptr remains in microarchitectural state and can be
extracted by an attacker using a vulnerable code sequence.
Example 2:
Some processors try to predict when a store will forward data to a subsequent load, even when the
address of the store or the load is not yet known. For example, on Intel processors this feature is
called a Fast Store Forwarding Predictor [REF-1392], and on AMD processors the feature is called
Predictive Store Forwarding [REF-1393]. A misprediction can cause incorrect or stale data to be
forwarded from a store to a load, as illustrated in the following code snippet from [REF-1393]:
Example Language: C (Bad)
void fn(int idx) {
unsigned char v;
idx_array[0] = 4096;
v = array[idx_array[idx] * (idx)];
}
In this example, assume that the parameter idx can only be 0 or 1, and assume that idx_array
initially contains all 0s. Observe that the assignment to v in line 4 will be array[0], regardless of
whether idx=0 or idx=1. Now suppose that an attacker repeatedly invokes fn with idx=0 to train
the store forwarding predictor to predict that the store in line 3 will forward the data 4096 to the
load idx_array[idx] in line 4. Then, when the attacker invokes fn with idx=1 the predictor may cause
idx_array[idx] to transiently produce the incorrect value 4096, and therefore v will transiently be
assigned the value array[4096], which otherwise would not have been accessible in line 4.
Although this toy example is benign (it doesn't transmit array[4096] over a covert channel), an
attacker may be able to use similar techniques to craft and train malicious code sequences to, for
example, read data beyond a software sandbox boundary.
Observed Examples
Reference Description
CVE-2020-0551 A fault, microcode assist, or abort may allow transient load operations to
forward malicious stale data to dependent operations executed by a victim,
causing the victim to unintentionally access and potentially expose its own data
over a covert channel.
https://www.cve.org/CVERecord?id=CVE-2020-0551
CVE-2020-8698 A fast store forwarding predictor may allow store operations to forward
incorrect data to transient load operations, potentially exposing data over a
covert channel.
https://www.cve.org/CVERecord?id=CVE-2020-8698
MemberOf Relationships
This MemberOf relationships table shows additional CWE Catgeories and Views that reference this
weakness as a member. This information is often useful in understanding where a weakness fits
within the context of external information sources.
CWE Version 4.14
CWE-1423: Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State
that Influences Transient Execution
CWE-1423: Exposure of Sensitive Information caused by Shared
Microarchitectural Predictor State that Influences Transient Execution 2302
Nature Type ID Name Page
MemberOf 1416 Comprehensive Categorization: Resource Lifecycle
Management
1400 2545
References
[REF-1389]Alyssa Milburn, Ke Sun and Henrique Kawakami. "You Cannot Always Win the Race:
Analyzing the LFENCE/JMP Mitigation for Branch Target Injection". 2022 March 8. < https://
arxiv.org/abs/2203.04277 >.2024-02-22.
[REF-1390]The kernel development community. "Speculation". 2020 August 6. < https://
docs.kernel.org/6.6/staging/speculation.html >.2024-02-04.
[REF-1391]Jo Van Bulck, Daniel Moghimi, Michael Schwarz, Moritz Lipp, Marina Minkin, Daniel
Genkin, Yuval Yarom, Berk Sunar, Daniel Gruss and Frank Piessens. "LVI : Hijacking Transient
Execution through Microarchitectural Load Value Injection". 2020 January 9. < https://lviattack.eu/
lvi.pdf >.2024-02-04.
[REF-1392]Intel Corporation. "Fast Store Forwarding Predictor". 2022 February 8. < https://
www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/
technical-documentation/fast-store-forwarding-predictor.html >.2024-02-04.
[REF-1393]AMD. "Security Analysis Of AMD Predictive Store Forwarding". 2021 March. <
https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
>.2024-02-04.
CWE-1423: Exposure of Sensitive Information caused by Shared
Microarchitectural Predictor State that Influences Transient Execution
Weakness ID : 1423
Structure : Simple
Abstraction : Base
Description
Shared microarchitectural predictor state may allow code to influence transient execution across a
hardware boundary, potentially exposing data that is accessible beyond the boundary over a covert
channel.
Extended Description
Many commodity processors have Instruction Set Architecture (ISA) features that protect software
components from one another. These features can include memory segmentation, virtual memory,
privilege rings, trusted execution environments, and virtual machines, among others. For example,
virtual memory provides each process with its own address space, which prevents processes
from accessing each other's private data. Many of these features can be used to form hardwareenforced
security boundaries between software components.
When separate software components (for example, two processes) share microarchitectural
predictor state across a hardware boundary, code in one component may be able to influence
microarchitectural predictor behavior in another component. If the predictor can cause transient
execution, the shared predictor state may allow an attacker to influence transient execution in
a victim, and in a manner that could allow the attacker to infer private data from the victim by
monitoring observable discrepancies (CWE-203) in a covert channel [REF-1400].
Predictor state may be shared when the processor transitions from one component to another (for
example, when a process makes a system call to enter the kernel). Many commodity processors
have features which prevent microarchitectural predictions that occur before a boundary from
influencing predictions that occur after the boundary.
CWE Version 4.14
CWE-1423: Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State
that Influences Transient Execution
CWE-1423: Exposure of Sensitive Information caused by Shared
Microarchitectural Predictor State that Influences Transient Execution