2057
executed) or data (which should not be executed). In this way, if a user can write to a region of
memory, the user cannot execute from that region and vice versa. This exclusivity provided by
special hardware bit is leveraged by the operating system to protect executable space. While this
bit is available in most modern processors by default, in some CPUs the exclusivity is implemented
via a memory-protection unit (MPU) and memory-management unit (MMU) in which memory
regions can be carved out with exact read, write, and execute permissions. However, if the CPU
does not have an MMU/MPU, then there is no write exclusivity. Without configuring exclusivity of
operations via segregated areas of memory, an attacker may be able to inject malicious code onto
memory and later execute it.
Relationships
The table(s) below shows the weaknesses and high level categories that are related to this
weakness. These relationships are defined as ChildOf, ParentOf, MemberOr and give insight to
similar items that may exist at higher and lower levels of abstraction. In addition, relationships such
as PeerOf and CanAlsoBe are defined to show similar weaknesses that may want to be explored.
Relevant to the view "Research Concepts" (CWE-1000)
Nature Type ID Name Page
ChildOf 284 Improper Access Control 680
Applicable Platforms
Language : Not Language-Specific (Prevalence = Undetermined)
Operating_System : Not OS-Specific (Prevalence = Undetermined)
Architecture : Not Architecture-Specific (Prevalence = Undetermined)
Technology : Microcontroller Hardware (Prevalence = Undetermined)
Technology : Processor Hardware (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Confidentiality
Integrity
Execute Unauthorized Code or Commands
Potential Mitigations
Phase: Architecture and Design
Implement a dedicated bit that can be leveraged by the Operating System to mark data areas
as non-executable. If such a bit is not available in the CPU, implement MMU/MPU (memory
management unit / memory protection unit).
Phase: Integration
If MMU/MPU are not available, then the firewalls need to be implemented in the SoC
interconnect to mimic the write-exclusivity operation.
Demonstrative Examples
Example 1:
MCS51 Microcontroller (based on 8051) does not have a special bit to support write exclusivity. It
also does not have an MMU/MPU support. The Cortex-M CPU has an optional MPU that supports
up to 8 regions.
Example Language: Other (Bad)
The optional MPU is not configured.
If the MPU is not configured, then an attacker will be able to inject malicious data into memory and
execute it.
CWE Version 4.14
CWE-1253: Incorrect Selection of Fuse Values
CWE-1253: Incorrect Selection of Fuse Values