2291
Many commodity processors also share microarchitectural resources that cache (temporarily store)
data, which may be confidential. These resources may be shared across processor contexts,
including across SMT threads, privilege rings, or others.
When transient operations allow access to ISA-protected data in a shared microarchitectural
resource, this might violate users' expectations of the ISA feature that is bypassed. For example,
if transient operations can access a victim's private data in a shared microarchitectural resource,
then the operations' microarchitectural side effects may correspond to the accessed data. If an
attacker can trigger these transient operations and observe their side effects through a covert
channel [REF-1400], then the attacker may be able to infer the victim's private data. Private data
could include sensitive program data, OS/VMM data, page table data (such as memory addresses),
system configuration data (see Demonstrative Example 3), or any other data that the attacker does
not have the required privileges to access.
Relationships
The table(s) below shows the weaknesses and high level categories that are related to this
weakness. These relationships are defined as ChildOf, ParentOf, MemberOr and give insight to
similar items that may exist at higher and lower levels of abstraction. In addition, relationships such
as PeerOf and CanAlsoBe are defined to show similar weaknesses that may want to be explored.
Relevant to the view "Research Concepts" (CWE-1000)
Nature Type ID Name Page
ChildOf 1420 Exposure of Sensitive Information during Transient
Execution