1980
Applicable Platforms
Language : Not Language-Specific (Prevalence = Undetermined)
Operating_System : Not OS-Specific (Prevalence = Undetermined)
Architecture : Not Architecture-Specific (Prevalence = Undetermined)
Technology : Not Technology-Specific (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Confidentiality
Integrity
Access Control
Varies by Context
Potential Mitigations
Phase: Architecture and Design
CWE Version 4.14
CWE-1264: Hardware Logic with Insecure De-Synchronization between Control and Data Channels
CWE-1264: Hardware Logic with Insecure De-
Synchronization between Control and Data Channels 2086
Specific protection requirements depend strongly on contextual factors including the level of
acceptable risk associated with compromise to the product's protection mechanism. Designers
could incorporate anti-tampering measures that protect against or detect when the product has
been tampered with.
Phase: Testing
The testing phase of the lifecycle should establish a method for determining whether the
protection mechanism is sufficient to prevent unauthorized access.
Phase: Manufacturing
Ensure that all protection mechanisms are fully activated at the time of manufacturing and
distribution.
MemberOf Relationships
This MemberOf relationships table shows additional CWE Catgeories and Views that reference this
weakness as a member. This information is often useful in understanding where a weakness fits
within the context of external information sources.
Nature Type ID Name Page
MemberOf 1208 Cross-Cutting Problems 1194 2474
MemberOf 1364 ICS Communications: Zone Boundary Failures 1358 2501
MemberOf 1396 Comprehensive Categorization: Access Control 1400 2519
Notes
Maintenance
This entry is still under development and will continue to see updates and content improvements.
Related Attack Patterns
CAPEC-ID Attack Pattern Name
401 Physically Hacking Hardware
CWE-1264: Hardware Logic with Insecure De-Synchronization between Control
and Data Channels
Weakness ID : 1264
Structure : Simple
Abstraction : Base
Description
The hardware logic for error handling and security checks can incorrectly forward data before the
security check is complete.
Extended Description
Many high-performance on-chip bus protocols and processor data-paths employ separate channels
for control and data to increase parallelism and maximize throughput. Bugs in the hardware
logic that handle errors and security checks can make it possible for data to be forwarded before
the completion of the security checks. If the data can propagate to a location in the hardware
observable to an attacker, loss of data confidentiality can occur. 'Meltdown' is a concrete example
of how de-synchronization between data and permissions checking logic can violate confidentiality
requirements. Data loaded from a page marked as privileged was returned to the cpu regardless
of current privilege level for performance reasons. The assumption was that the cpu could
later remove all traces of this data during the handling of the illegal memory access exception,
but this assumption was proven false as traces of the secret data were not removed from the
microarchitectural state.
CWE Version 4.14
CWE-1264: Hardware Logic with Insecure De-Synchronization between Control and Data Channels
CWE-1264: Hardware Logic with Insecure De-
Synchronization between Control and Data Channels