530
Abstraction : Base
Description
Two separate operations in a product require different amounts of time to complete, in a way that
is observable to an actor and reveals security-relevant information about the state of the product,
such as whether a particular operation was successful or not.
Extended Description
In security-relevant contexts, even small variations in timing can be exploited by attackers to
indirectly infer certain details about the product's internal operations. For example, in some
cryptographic algorithms, attackers can use timing differences to infer certain properties about a
private key, making the key easier to guess. Timing discrepancies effectively form a timing side
channel.
Relationships
The table(s) below shows the weaknesses and high level categories that are related to this
weakness. These relationships are defined as ChildOf, ParentOf, MemberOr and give insight to
similar items that may exist at higher and lower levels of abstraction. In addition, relationships such
as PeerOf and CanAlsoBe are defined to show similar weaknesses that may want to be explored.
Relevant to the view "Research Concepts" (CWE-1000)
Nature Type ID Name Page
ChildOf 203 Observable Discrepancy 518
ParentOf 1254 Incorrect Comparison Logic Granularity 2060
CanPrecede 327 Use of a Broken or Risky Cryptographic Algorithm 799
CanPrecede 385 Covert Timing Channel 940
Relevant to the view "Architectural Concepts" (CWE-1008)
Nature Type ID Name Page
MemberOf 1012 Cross Cutting 2427
Relevant to the view "Software Development" (CWE-699)
Nature Type ID Name Page
MemberOf 199 Information Management Errors 2312
Applicable Platforms
Language : Not Language-Specific (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Confidentiality
Access Control
Read Application Data
Bypass Protection Mechanism
Demonstrative Examples
Example 1:
Consider an example hardware module that checks a user-provided password to grant access to a
user. The user-provided password is compared against a golden value in a byte-by-byte manner.
Example Language: Verilog (Bad)
always_comb @ (posedge clk)
begin
assign check_pass[3:0] = 4'b0;
for (i = 0; i < 4; i++) begin
if (entered_pass[(i*8 - 1) : i] eq golden_pass([i*8 - 1) : i])
assign check_pass[i] = 1;
continue;
CWE Version 4.14
CWE-208: Observable Timing Discrepancy
CWE-208: Observable Timing Discrepancy