1983
else if ( (dm::dtm_op_e'(dmi.op) == dm::DTM_PASS) && (miss_pass_check_cnt_q != 2'b11) )
begin
state_d = Write;
pass_mode = 1'b1;
end
...
end
...
PassChkValid: begin
if(hashValid) begin
if(exp_hash == pass_hash) begin
pass_check = 1'b1;
end else begin
pass_check = 1'b0;
miss_pass_check_cnt_d = miss_pass_check_cnt_q + 1
end
state_d = Idle;
end else begin
state_d = PassChkValid;
end
end
...
Example 3:
The example code below is taken from the JTAG access control mechanism of the HACK@DAC'21
buggy OpenPiton SoC [REF-1364]. Access to JTAG allows users to access sensitive information in
the system. Hence, access to JTAG is controlled using cryptographic authentication of the users.
In this example (see the vulnerable code source), the password checker uses HMAC-SHA256
for authentication. It takes a 512-bit secret message from the user, hashes it using HMAC, and
compares its output with the expected output to determine the authenticity of the user.
Example Language: Verilog (Bad)
...
logic [31-1:0] data_d, data_q;
...
logic [512-1:0] pass_data;
...
Write: begin
...
if (pass_mode) begin
pass_data = { {60{8'h00}}, data_d};
state_d = PassChk;
pass_mode = 1'b0;
...
end
...
The vulnerable code shows an incorrect implementation of the HMAC authentication where it only
uses the least significant 32 bits of the secret message for the authentication (the remaining 480
bits are hard coded as zeros). As a result, the system is susceptible to brute-force attacks on the
access control mechanism of JTAG, where the attacker only needs to determine 32 bits of the
secret message instead of 512 bits.
To mitigate this issue, remove the zero padding and use all 512 bits of the secret message for
HMAC authentication [REF-1365].
Example Language: Verilog (Good)
...
logic [512-1:0] data_d, data_q;
...
logic [512-1:0] pass_data;
...
CWE Version 4.14
CWE-1191: On-Chip Debug and Test Interface With Improper Access Control
CWE-1191: On-Chip Debug and Test Interface With Improper Access Control