2004
Failure to implement write-once restrictions in hardware design can expose such registers to being
re-programmed by software and written multiple times. For example, write-once fields could be
implemented to only be write-protected if they have been set to value "1", wherein they would work
as "write-1-once" and not "write-once".
Relationships
The table(s) below shows the weaknesses and high level categories that are related to this
weakness. These relationships are defined as ChildOf, ParentOf, MemberOr and give insight to
similar items that may exist at higher and lower levels of abstraction. In addition, relationships such
as PeerOf and CanAlsoBe are defined to show similar weaknesses that may want to be explored.
Relevant to the view "Research Concepts" (CWE-1000)
Nature Type ID Name Page
ChildOf 284 Improper Access Control 680
Applicable Platforms
Language : Verilog (Prevalence = Undetermined)
Language : VHDL (Prevalence = Undetermined)
Technology : System on Chip (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Confidentiality
Integrity
Availability
Access Control
Varies by Context
System configuration cannot be programmed in a secure
way.
Potential Mitigations
Phase: Architecture and Design
During hardware design all register write-once or sticky fields must be evaluated for proper
configuration.
Phase: Testing
The testing phase should use automated tools to test that values are not reprogrammable and
that write-once fields lock on writing zeros.
Demonstrative Examples
Example 1:
Consider the example design module system verilog code shown below.
register_write_once_example module is an example of register that has a write-once field defined.
Bit 0 field captures the write_once_status value. This implementation can be for a register that is
defined by specification to be a write-once register, since the write_once_status field gets written by
input data bit 0 on first write.
Example Language: Verilog (Bad)
module register_write_once_example
(
input [15:0] Data_in,
input Clk,
input ip_resetn,
input global_resetn,
input write,
output reg [15:0] Data_out
);
reg Write_once_status;
always @(posedge Clk or negedge ip_resetn)
CWE Version 4.14
CWE-1224: Improper Restriction of Write-Once Bit Fields
CWE-1224: Improper Restriction of Write-Once Bit Fields