2042
The Finite State Machine (FSM) shown in the "bad" code snippet below assigns the output ("out")
based on the value of state, which is determined based on the user provided input ("user_input").
Example Language: Verilog (Bad)
module fsm_1(out, user_input, clk, rst_n);
input [2:0] user_input;
input clk, rst_n;
output reg [2:0] out;
reg [1:0] state;
always @ (posedge clk or negedge rst_n )
begin
if (!rst_n)
state = 3'h0;
else
case (user_input)
3'h0:
3'h1:
3'h2:
3'h3: state = 2'h3;
3'h4: state = 2'h2;
3'h5: state = 2'h1;
endcase
end
out <= {1'h1, state};
endmodule
The case statement does not include a default to handle the scenario when the user provides
inputs of 3'h6 and 3'h7. Those inputs push the system to an undefined state and might cause a
crash (denial of service) or any other unanticipated outcome.
Adding a default statement to handle undefined inputs mitigates this issue. This is shown in the
"Good" code snippet below. The default statement is in bold.
Example Language: Verilog (Good)
case (user_input)
3'h0:
3'h1:
3'h2:
3'h3: state = 2'h3;
3'h4: state = 2'h2;
3'h5: state = 2'h1;
default: state = 2'h0;
endcase
MemberOf Relationships
This MemberOf relationships table shows additional CWE Catgeories and Views that reference this
weakness as a member. This information is often useful in understanding where a weakness fits
within the context of external information sources.
Nature Type ID Name Page
MemberOf 1199 General Circuit and Logic Design Concerns 1194 2471
MemberOf 1412 Comprehensive Categorization: Poor Coding Practices 1400 2538
Related Attack Patterns
CAPEC-ID Attack Pattern Name
74 Manipulating State
References
CWE Version 4.14
CWE-1246: Improper Write Handling in Limited-write Non-Volatile Memories
CWE-1246: Improper Write Handling in Limited-write Non-Volatile Memories