2043
[REF-1060]Farimah Farahmandi and Prabhat Mishra. "FSM Anomaly Detection using Formal
Analysis". < https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8119228&tag=1 >.
CWE-1246: Improper Write Handling in Limited-write Non-Volatile Memories
Weakness ID : 1246
Structure : Simple
Abstraction : Base
Description
The product does not implement or incorrectly implements wear leveling operations in limited-write
non-volatile memories.
Extended Description
Non-volatile memories such as NAND Flash, EEPROM, etc. have individually erasable segments,
each of which can be put through a limited number of program/erase or write cycles. For example,
the device can only endure a limited number of writes, after which the device becomes unreliable.
In order to wear out the cells in a uniform manner, non-volatile memory and storage products
based on the above-mentioned technologies implement a technique called wear leveling. Once a
set threshold is reached, wear leveling maps writes of a logical block to a different physical block.
This prevents a single physical block from prematurely failing due to a high concentration of writes.
If wear leveling is improperly implemented, attackers may be able to programmatically cause the
storage to become unreliable within a much shorter time than would normally be expected.
Relationships
The table(s) below shows the weaknesses and high level categories that are related to this
weakness. These relationships are defined as ChildOf, ParentOf, MemberOr and give insight to
similar items that may exist at higher and lower levels of abstraction. In addition, relationships such
as PeerOf and CanAlsoBe are defined to show similar weaknesses that may want to be explored.
Relevant to the view "Research Concepts" (CWE-1000)
Nature Type ID Name Page
ChildOf 400 Uncontrolled Resource Consumption 964
Applicable Platforms
Language : Not Language-Specific (Prevalence = Undetermined)
Operating_System : Not OS-Specific (Prevalence = Undetermined)
Architecture : Not Architecture-Specific (Prevalence = Undetermined)
Technology : System on Chip (Prevalence = Undetermined)
Technology : Memory Hardware (Prevalence = Undetermined)
Technology : Storage Hardware (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Availability DoS: Instability
Potential Mitigations
Phase: Architecture and Design
Phase: Implementation
Phase: Testing
Include secure wear leveling algorithms and ensure they may not be bypassed.
CWE Version 4.14
CWE-1247: Improper Protection Against Voltage and Clock Glitches
CWE-1247: Improper Protection Against Voltage and Clock Glitches