888
Applicable Platforms
Language : Verilog (Prevalence = Undetermined)
Language : VHDL (Prevalence = Undetermined)
Technology : System on Chip (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Access Control Bypass Protection Mechanism
Gain Privileges or Assume Identity
Alter Execution Logic
Potential Mitigations
Phase: Architecture and Design
Adopting design practices that encourage designers to recognize and eliminate race conditions,
such as Karnaugh maps, could result in the decrease in occurrences of race conditions.
Phase: Implementation
Logic redundancy can be implemented along security critical paths to prevent race conditions. To
avoid metastability, it is a good practice in general to default to a secure state in which access is
not given to untrusted agents.
Demonstrative Examples
Example 1:
The code below shows a 2x1 multiplexor using logic gates. Though the code shown below results
in the minimum gate solution, it is disjoint and causes glitches.
Example Language: Verilog (Bad)
// 2x1 Multiplexor using logic-gates
module glitchEx(
input wire in0, in1, sel,
output wire z
);
wire not_sel;
wire and_out1, and_out2;
assign not_sel = ~sel;
assign and_out1 = not_sel & in0;
assign and_out2 = sel & in1;
// Buggy line of code:
assign z = and_out1 | and_out2; // glitch in signal z
endmodule
The buggy line of code, commented above, results in signal 'z' periodically changing to an
unwanted state. Thus, any logic that references signal 'z' may access it at a time when it is in this
unwanted state. This line should be replaced with the line shown below in the Good Code Snippet
which results in signal 'z' remaining in a continuous, known, state. Reference for the above code,
along with waveforms for simulation can be found in the references below.
CWE Version 4.14
CWE-1298: Hardware Logic Contains Race Conditions
CWE-1298: Hardware Logic Contains Race Conditions