2195
Technology : Processor Hardware (Prevalence = Undetermined)
Technology : Not Technology-Specific (Prevalence = Undetermined)
Common Consequences
Scope Impact Likelihood
Confidentiality
Integrity
Access Control
Availability
DoS: Crash, Exit, or Restart
Bypass Protection Mechanism
Read Memory
Modify Memory
Medium
Detection Methods
Simulation / Emulation
RTL simulation to ensure that bridge-access controls are implemented properly.
Effectiveness = High
Formal Verification
Formal verification of bridge RTL to ensure that access control cannot be bypassed.
Effectiveness = High
Potential Mitigations
Phase: Architecture and Design
Ensure that the design includes provisions for access-control checks in the bridge for both
upstream and downstream transactions.
Phase: Implementation
Implement access-control checks in the bridge for both upstream and downstream transactions.
Demonstrative Examples
Example 1:
This example is from CVE-2019-6260 [REF-1138]. The iLPC2AHB bridge connects a CPU (with
multiple, privilege levels, such as user, super user, debug, etc.) over AHB interface to an LPC bus.
Several peripherals are connected to the LPC bus. The bridge is expected to check the privilege
level of the transactions initiated in the core before forwarding them to the peripherals on the LPC
bus.
The bridge does not implement the checks and allows reads and writes from all privilege levels.
To address this, designers should implement hardware-based checks that are either hardcoded
to block untrusted agents from accessing secure peripherals or implement firmware flows that
configure the bridge to block untrusted agents from making arbitrary reads or writes.
Example 2:
The example code below is taken from the AES and core local interrupt (CLINT) peripherals of
the HACK@DAC'21 buggy OpenPiton SoC. The access to all the peripherals for a given privilege
level of the processor is controlled by an access control module in the SoC. This ensures that
malicious users with insufficient privileges do not get access to sensitive data, such as the AES
keys used by the operating system to encrypt and decrypt information. The security of the entire
system will be compromised if the access controls are incorrectly enforced. The access controls
are enforced through the interconnect-bus fabrics, where access requests with insufficient access
control permissions will be rejected.
Example Language: Verilog (Bad)
...
module aes0_wrapper #(...)(...);
...
CWE Version 4.14
CWE-1317: Improper Access Control in Fabric Bridge
CWE-1317: Improper Access Control in Fabric Bridge