2226
Applicable Platforms
Language : Not Language-Specific (Prevalence = Undetermined)
Operating_System : Not OS-Specific (Prevalence = Undetermined)
Architecture : Not Architecture-Specific (Prevalence = Undetermined)
Technology : Security Hardware (Prevalence = Undetermined)
Technology : Not Technology-Specific (Prevalence = Undetermined)
Background Details
"Network-on-chip" (NoC) is a commonly-used term used for hardware interconnect fabrics used
by multicore Systems-on-Chip (SoC). Communication between modules on the chip uses packetbased
methods, with improved efficiency and scalability compared to bus architectures [REF-1241].
Common Consequences
Scope Impact Likelihood
Confidentiality
Availability
DoS: Resource Consumption (Other)
Varies by Context
Other
Attackers may infer data that belongs to a trusted agent.
The methods used to perform this attack may result in
noticeably increased resource consumption.
Medium
Detection Methods
Manual Analysis
Providing marker flags to send through the interfaces coupled with examination of which users
are able to read or manipulate the flags will help verify that the proper isolation has been
achieved and is effective.
Effectiveness = Moderate
Potential Mitigations
Phase: Architecture and Design
Phase: Implementation
Implement priority-based arbitration inside the NoC and have dedicated buffers or virtual
channels for routing secret data from trusted agents.
Demonstrative Examples
Example 1:
Consider a NoC that implements a one-dimensional mesh network with four nodes. This supports
two flows: Flow A from node 0 to node 3 (via node 1 and node 2) and Flow B from node 1 to node
2. Flows A and B share a common link between Node 1 and Node 2. Only one flow can use the link
in each cycle.
One of the masters to this NoC implements a cryptographic algorithm (RSA), and another master
to the NoC is a core that can be exercised by an attacker. The RSA algorithm performs a modulo
multiplication of two large numbers and depends on each bit of the secret key. The algorithm
examines each bit in the secret key and only performs multiplication if the bit is 1. This algorithm
is known to be prone to timing attacks. Whenever RSA performs multiplication, there is additional
network traffic to the memory controller. One of the reasons for this is cache conflicts.
Since this is a one-dimensional mesh, only one flow can use the link in each cycle. Also, packets
from the attack program and the RSA program share the output port of the network-on-chip. This
contention results in network interference, and the throughput and latency of one flow can be
affected by the other flow's demand.
CWE Version 4.14
CWE-1332: Improper Handling of Faults that Lead to Instruction Skips
CWE-1332: Improper Handling of Faults that Lead to Instruction Skips