1063
The mideleg (machine interrupt delegation) register, also 64-bit wide, enables the delegation of
specific interrupt sources from machine privilege mode to lower privilege levels. By setting specific
bits in the mideleg register, the handling of certain interrupts can be delegated to lower privilege
levels without engaging the machine-level privilege mode. For example, in supervisor mode, the
mie register is limited to a specific register called the sie (supervisor interrupt enable) register. If
delegated, an interrupt becomes visible in the sip (supervisor interrupt pending) register and can be
enabled or blocked using the sie register. If no delegation occurs, the related bits in sip and sie are
set to zero.
The sie register value is computed based on the current value of mie register, i.e., mie_q, and the
mideleg register.
Example Language: Verilog (Bad)
module csr_regfile #(...)(...);
...
// ---------------------------
// CSR Write and update logic
// ---------------------------
...
if (csr_we) begin
unique case (csr_addr.address)
...
riscv::CSR_SIE: begin
// the mideleg makes sure only delegate-able register
//(and therefore also only implemented registers) are written
mie_d = (mie_q & ~mideleg_q) | (csr_wdata & mideleg_q) | utval_q;
end
...
endcase
end
endmodule
The above code snippet illustrates an instance of a vulnerable implementation of the sie register
update logic, where users can tamper with the mie_d register value through the utval (user trap
value) register. This behavior violates the RISC-V specification.
The code shows that the value of utval, among other signals, is used in updating the mie_d value
within the sie update logic. While utval is a register accessible to users, it should not influence or
compromise the integrity of sie. Through manipulation of the utval register, it becomes feasible to
manipulate the sie register's value. This opens the door for potential attacks, as an adversary can
gain control over or corrupt the sie value. Consequently, such manipulation empowers an attacker
to enable or disable critical supervisor-level interrupts, resulting in various security risks such as
privilege escalation or denial-of-service attacks.
A fix to this issue is to remove the utval from the right-hand side of the assignment. That is the
value of the mie_d should be updated as shown in the good code example [REF-1386].
Example Language: Verilog (Good)
module csr_regfile #(...)(...);
...
// ---------------------------
// CSR Write and update logic
// ---------------------------
...
if (csr_we) begin
unique case (csr_addr.address)
...
riscv::CSR_SIE: begin
// the mideleg makes sure only delegate-able register
//(and therefore also only implemented registers) are written
mie_d = (mie_q & ~mideleg_q) | (csr_wdata & mideleg_q);
end
CWE Version 4.14
CWE-441: Unintended Proxy or Intermediary ('Confused Deputy')
CWE-441: Unintended Proxy or Intermediary ('Confused Deputy')