/* reset all core internal registers located in CLK_TX and CLK_RX  */
ErrStatus enet_software_reset(void)
/* reset all core internal registers located in CLK_TX and CLK_RX  */
ErrStatus enet_software_reset(void)
{
    uint32_t timeout = 0U;
    ErrStatus enet_state = ERROR;
    uint32_t dma_flag;
    ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR;
    do {
        dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR);
        timeout++;
    } while((RESET != dma_flag) && (ENET_DELAY_TO != timeout));
    if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)) {
        enet_state = SUCCESS;
    }
    return enet_state;
}