/* This takes 16 cycles and is synchronous to CFCLK, which runs at 200 MHz, so this should take at most 80 nanoseconds.  */
int asd_chip_hardrst(struct asd_ha_struct *asd_ha)
/* This takes 16 cycles and is synchronous to CFCLK, which runs at 200 MHz, so this should take at most 80 nanoseconds.  */
int asd_chip_hardrst(struct asd_ha_struct *asd_ha)
{
	int i;
	int count = 100;
	u32 reg;
	for (i = 0 ; i < 4 ; i++) {
		asd_write_reg_dword(asd_ha, COMBIST, HARDRST);
	}
	do {
		udelay(1);
		reg = asd_read_reg_dword(asd_ha, CHIMINT);
		if (reg & HARDRSTDET) {
			asd_write_reg_dword(asd_ha, CHIMINT,
					    HARDRSTDET|PORRSTDET);
			return 0;
		}
	} while (--count > 0);
	return -ENODEV;
}