/* @pcie: Pointer to the PCI controller state @index: ATU region index @type: ATU accsess type @cpu_addr: the physical address for the translation entry @pci_addr: the pcie bus address for the translation entry @size: the size of the translation entry  */
static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index, int type, u64 cpu_addr, u64 pci_addr, u32 size)
/* @pcie: Pointer to the PCI controller state @index: ATU region index @type: ATU accsess type @cpu_addr: the physical address for the translation entry @pci_addr: the pcie bus address for the translation entry @size: the size of the translation entry  */
static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index, int type, u64 cpu_addr, u64 pci_addr, u32 size)
{
	writel(PCIE_ATU_REGION_OUTBOUND | index,
	       pcie->ctrl_base + PCIE_ATU_VIEWPORT);
	writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
	writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
	writel(lower_32_bits(cpu_addr + size - 1),
	       pcie->ctrl_base + PCIE_ATU_LIMIT);
	writel(lower_32_bits(pci_addr),
	       pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
	writel(upper_32_bits(pci_addr),
	       pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
	writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
	writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
}