/* Get the rate of the H-PLL clock from input clock frequency and the value of the H-PLL Parameter Register.  */
static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
/* Get the rate of the H-PLL clock from input clock frequency and the value of the H-PLL Parameter Register.  */
static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
{
	const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
	const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
			>> SCU_HPLL_DENUM_SHIFT;
	const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
			>> SCU_HPLL_POST_SHIFT;
	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}