/* Using parent clock DPLL data, look up DPLL state. If locked, set our rate to the dpll_clk * 2; otherwise, just use dpll_clk.  */
unsigned long omap3_clkoutx2_recalc(struct clk *clk)
/* Using parent clock DPLL data, look up DPLL state. If locked, set our rate to the dpll_clk * 2; otherwise, just use dpll_clk.  */
unsigned long omap3_clkoutx2_recalc(struct clk *clk)
{
	const struct dpll_data *dd;
	unsigned long rate;
	u32 v;
	struct clk *pclk;
	pclk = clk->parent;
	while (pclk && !pclk->dpll_data)
		pclk = pclk->parent;
	WARN_ON(!pclk);
	dd = pclk->dpll_data;
	WARN_ON(!dd->enable_mask);
	v = __raw_readl(dd->control_reg) & dd->enable_mask;
	v >>= __ffs(dd->enable_mask);
	if (v != OMAP3XXX_EN_DPLL_LOCKED)
		rate = clk->parent->rate;
	else
		rate = clk->parent->rate * 2;
	return rate;
}