/* param base DMA base address. param channel DMA channel number. param config channel configurations structure.  */
void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph)
/* param base DMA base address. param channel DMA channel number. param config channel configurations structure.  */
void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph)
{
    assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS);
    uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
    if (trigger != NULL)
    {
        tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
                  DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK |
                  DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK;
    }
    tmpReg = base->CHANNEL[channel].CFG & (~tmpReg);
    if (trigger != NULL)
    {
        tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
    }
    tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph);
    base->CHANNEL[channel].CFG = tmpReg;
}