/* Verify that the Ethernet clock divider value results in a PHY REF_CLK that does not exceed 2.5 MHz. Apply changes made in PLLCON and PLLCFG */
static void pll_latch(volatile struct lpc178x_pll_regs *pll_regs)
/* Verify that the Ethernet clock divider value results in a PHY REF_CLK that does not exceed 2.5 MHz. Apply changes made in PLLCON and PLLCFG */
static void pll_latch(volatile struct lpc178x_pll_regs *pll_regs)
{
	pll_regs->con = 1;
	pll_regs->feed = LPC178X_PLL_FEED_KEY1;
	pll_regs->feed = LPC178X_PLL_FEED_KEY2;
}