/* This resets pipelines, timers, counters, state machines, etc. Transactions will be terminated immediately, and operational registers will be set to their defaults.  */
int xhci_reset(struct xhci_hcd *xhci)
/* This resets pipelines, timers, counters, state machines, etc. Transactions will be terminated immediately, and operational registers will be set to their defaults.  */
int xhci_reset(struct xhci_hcd *xhci)
{
	u32 command;
	u32 state;
	state = xhci_readl(xhci, &xhci->op_regs->status);
	if ((state & STS_HALT) == 0) {
		xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
		return 0;
	}
	xhci_dbg(xhci, "
	command = xhci_readl(xhci, &xhci->op_regs->command);
	command |= CMD_RESET;
	xhci_writel(xhci, command, &xhci->op_regs->command);
	xhci_to_hcd(xhci)->state = HC_STATE_HALT;
	return handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 250 * 1000);
}