/* Deep sleep: PLL is turned off. Wake is fast. PLL requires a minimum of 3ms to lock. During this time the main clock will be ramping up from ~16 to 24 MHz.  */
void soc_deep_sleep_enable(void)
/* Deep sleep: PLL is turned off. Wake is fast. PLL requires a minimum of 3ms to lock. During this time the main clock will be ramping up from ~16 to 24 MHz.  */
void soc_deep_sleep_enable(void)
{
	SCB->SCR = (1ul << 2);
	PCR_REGS->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY;
}