/* IWDG Set Period in Milliseconds. 
A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds) can occasionally occur if the prescale or preload registers are currently busy loading a previous value. */
void iwdg_set_period_ms(uint32_t period)
/* IWDG Set Period in Milliseconds. 
A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds) can occasionally occur if the prescale or preload registers are currently busy loading a previous value. */
void iwdg_set_period_ms(uint32_t period)
{
	const int PRESCALER_MAX = 6;
	uint8_t prescale = 0;
	uint32_t count = period << 3;
	if (count == 0) {
		count = 1;
	}
	while ((count - 1) >> COUNT_LENGTH) {
		count >>= 1;
		prescale++;
	}
	count--;
	if (prescale > PRESCALER_MAX) {
		count = COUNT_MASK;
		prescale = PRESCALER_MAX;
	}
	while (iwdg_prescaler_busy());
	IWDG_KR = IWDG_KR_UNLOCK;
	IWDG_PR = prescale;
	while (iwdg_reload_busy());
	IWDG_KR = IWDG_KR_UNLOCK;
	IWDG_RLR = count & COUNT_MASK;
	iwdg_reset();
}