/* While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB data arrays, SH-X3 cores with PTEAEX split out the memory-mapped address arrays. In compat mode the second array is inaccessible, while in extended mode, the legacy 8-bit ASID field in address array 1 has undefined behaviour.  */
void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid, unsigned long page)
/* While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB data arrays, SH-X3 cores with PTEAEX split out the memory-mapped address arrays. In compat mode the second array is inaccessible, while in extended mode, the legacy 8-bit ASID field in address array 1 has undefined behaviour.  */
void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid, unsigned long page)
{
	jump_to_uncached();
	__raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
	__raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
	back_to_cached();
}