/* The active part of our cycle counter is only 32-bits wide, and we're treating the difference between two marks as signed. On a 1GHz box, that's about 2 seconds.  */
void __delay(int loops)
/* The active part of our cycle counter is only 32-bits wide, and we're treating the difference between two marks as signed. On a 1GHz box, that's about 2 seconds.  */
void __delay(int loops)
{
	int tmp;
	__asm__ __volatile__(
		"	rpcc %0\n"
		"	addl %1,%0,%1\n"
		"1:	rpcc %0\n"
		"	subl %1,%0,%0\n"
		"	bgt %0,1b"
		: "=&r" (tmp), "=r" (loops) : "1"(loops));
}