/* To read a phy register, mii managements frames are sent to the phy. The frames look like this: pre (32 bits): 0xffff ffff st (2 bits): 01 op (2bits): 10: read 01: write phyad (5 bits): xxxxx regad (5 bits): xxxxx ta (Bus release): data (16 bits): read data  */
static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg)
/* To read a phy register, mii managements frames are sent to the phy. The frames look like this: pre (32 bits): 0xffff ffff st (2 bits): 01 op (2bits): 10: read 01: write phyad (5 bits): xxxxx regad (5 bits): xxxxx ta (Bus release): data (16 bits): read data  */
static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg)
{
	u32 val;
	sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
	sh_eth_mii_write_phy_bits(port, 0x1, 2);
	sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
	sh_eth_mii_write_phy_bits(port, phy_addr, 5);
	sh_eth_mii_write_phy_bits(port, reg, 5);
	sh_eth_mii_bus_release(port);
	sh_eth_mii_read_phy_bits(port, &val, 16);
	return val;
}