/* See the "PLL Configuration Register Description" in the SSD2828 datasheet.  */
static u32 construct_pll_config(u32 desired_pll_freq_kbps, u32 reference_freq_khz)
/* See the "PLL Configuration Register Description" in the SSD2828 datasheet.  */
static u32 construct_pll_config(u32 desired_pll_freq_kbps, u32 reference_freq_khz)
{
	u32 div_factor = 1, mul_factor, fr = 0;
	u32 output_freq_kbps;
	while (reference_freq_khz / (div_factor + 1) >= 5000)
		div_factor++;
	if (div_factor > 31)
		div_factor = 31;
	mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor,
				  reference_freq_khz);
	output_freq_kbps = reference_freq_khz * mul_factor / div_factor;
	if (output_freq_kbps >= 501000)
		fr = 3;
	else if (output_freq_kbps >= 251000)
		fr = 2;
	else if (output_freq_kbps >= 126000)
		fr = 1;
	return (fr << 14) | (div_factor << 8) | mul_factor;
}