/* 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA channels supported in hardware.  */
int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
/* 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA channels supported in hardware.  */
int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
{
	int txq_id = txq->q.id;
	iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
			     txq->q.dma_addr >> 8);
	return 0;
}