/* Intel FPGA PCIe port uses BAR0 of RC's configuration space as the translation from PCI bus to native BUS. Entire DDR region is mapped into PCIe space using these registers, so it can be reached by DMA from EP devices. The BAR0 of bridge should be hidden during enumeration to avoid the sizing and resource allocation by PCIe core.  */
static bool intel_fpga_pcie_hide_rc_bar(struct intel_fpga_pcie *pcie, pci_dev_t bdf, int offset)
/* Intel FPGA PCIe port uses BAR0 of RC's configuration space as the translation from PCI bus to native BUS. Entire DDR region is mapped into PCIe space using these registers, so it can be reached by DMA from EP devices. The BAR0 of bridge should be hidden during enumeration to avoid the sizing and resource allocation by PCIe core.  */
static bool intel_fpga_pcie_hide_rc_bar(struct intel_fpga_pcie *pcie, pci_dev_t bdf, int offset)
{
	if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) == 0 &&
	    PCI_FUNC(bdf) == 0 && offset == PCI_BASE_ADDRESS_0)
		return true;
	return false;
}