/* Configures the SAI clock Divider coming from PLLI2S.  */
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
/* Configures the SAI clock Divider coming from PLLI2S.  */
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
{
  uint32_t tmpreg = 0;
  assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ));
  tmpreg = RCC->DCKCFGR;
  tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ);
  tmpreg |= (RCC_PLLI2SDivQ - 1);
  RCC->DCKCFGR = tmpreg;
}