/* Timer Enable the Output Compare Fast Mode. 
When this is enabled, the output compare signal is forced to the compare state by a trigger input, independently of the compare match. This speeds up the setting of the output compare to 3 clock cycles as opposed to at least 5 in the slow mode. This works in the PWM1 and PWM2 modes only. */
void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
/* Timer Enable the Output Compare Fast Mode. 
When this is enabled, the output compare signal is forced to the compare state by a trigger input, independently of the compare match. This speeds up the setting of the output compare to 3 clock cycles as opposed to at least 5 in the slow mode. This works in the PWM1 and PWM2 modes only. */
void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
	switch (oc_id) {
	case TIM_OC1:
		TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1FE;
		break;
	case TIM_OC2:
		TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2FE;
		break;
	case TIM_OC3:
		TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3FE;
		break;
	case TIM_OC4:
		TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4FE;
		break;
	case TIM_OC1N:
	case TIM_OC2N:
	case TIM_OC3N:
		break;
	}
}