/* Set each stc_canfd_config_t field to a default value. Based on 40MHz CAN clock, TQ clock is CAN clock divided by 1. Bit rate 2Mbps, 1 bit time is 20TQs, primary sample point is 80%, secondary sample point is 80%.  */
int32_t CAN_FD_StructInit(stc_canfd_config_t *pstcCanFd)
/* Set each stc_canfd_config_t field to a default value. Based on 40MHz CAN clock, TQ clock is CAN clock divided by 1. Bit rate 2Mbps, 1 bit time is 20TQs, primary sample point is 80%, secondary sample point is 80%.  */
int32_t CAN_FD_StructInit(stc_canfd_config_t *pstcCanFd)
{
    int32_t i32Ret = LL_ERR_INVD_PARAM;
    if (pstcCanFd != NULL) {
        pstcCanFd->stcBitCfg.u32Prescaler = 1U;
        pstcCanFd->stcBitCfg.u32TimeSeg1  = 16U;
        pstcCanFd->stcBitCfg.u32TimeSeg2  = 4U;
        pstcCanFd->stcBitCfg.u32SJW       = 4U;
        pstcCanFd->u8Mode                 = CAN_FD_MD_ISO;
        pstcCanFd->u8TDC                  = CAN_FD_TDC_ENABLE;
        pstcCanFd->u8SSPOffset            = 16U;
        i32Ret = LL_OK;
    }
    return i32Ret;
}