/* The set source address hold transfer size. The source address hold or loop transfer size is when the DMA transfer data from source address (SA), if the loop size is 4, the DMA will read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, SA + 1 ... and so on.  */
static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
/* The set source address hold transfer size. The source address hold or loop transfer size is when the DMA transfer data from source address (SA), if the loop size is 4, the DMA will read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, SA + 1 ... and so on.  */
static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
{
	switch (size) {
	case 0:
		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
			(~FSL_DMA_MR_SAHE), 32);
		break;
	case 1:
	case 2:
	case 4:
	case 8:
		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
			FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
			32);
		break;
	}
}