/* PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to mask all MSI interrupts by clearing the MSI enable bit does not work reliably as devices without an INTx disable bit will then generate a level IRQ which will never be cleared.  */
static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
/* PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to mask all MSI interrupts by clearing the MSI enable bit does not work reliably as devices without an INTx disable bit will then generate a level IRQ which will never be cleared.  */
static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
{
	u32 mask_bits = desc->masked;
	if (!desc->msi_attrib.maskbit)
		return 0;
	mask_bits &= ~mask;
	mask_bits |= flag;
	pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
	return mask_bits;
}