/* the instruction disassembly implemented here matches the instruction encoding classifications in chapter 3 (C3) of the ARM Architecture Reference Manual (DDI0487A_a)  */
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
/* the instruction disassembly implemented here matches the instruction encoding classifications in chapter 3 (C3) of the ARM Architecture Reference Manual (DDI0487A_a)  */
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
{
    uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
    if (insn & (1 << 31)) {
        tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
    }
    gen_goto_tb(s, 0, addr);
}