/* Check the status of the FIFO buffer of the specified SPI port.  */
unsigned long SPIFIFOStatusGet(unsigned long ulBase)
/* Check the status of the FIFO buffer of the specified SPI port.  */
unsigned long SPIFIFOStatusGet(unsigned long ulBase)
{
    xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE)||
            (ulBase == SPI2_BASE)||(ulBase == SPI3_BASE) );
    return (xHWREG(ulBase + SPI_STATUS) & (SPI_STATUS_TX_FULL) ||
            (SPI_STATUS_RX_FULL) || (SPI_STATUS_TX_EMPTY) || (SPI_STATUS_RX_EMPTY));
}