/* @div_m: 1 2 4 8 16 32 64 128 256  */
void hal_pwm_clk_div_m(uint32_t channel_in, uint32_t div_m)
/* @div_m: 1 2 4 8 16 32 64 128 256  */
void hal_pwm_clk_div_m(uint32_t channel_in, uint32_t div_m)
{
    unsigned long reg_addr = PWM_BASE + PWM_PCCR_BASE;
    uint32_t reg_val;
    uint32_t channel = channel_in / 2;
    reg_addr += 4 * channel;
    reg_val = hal_readl(reg_addr);
    reg_val = SET_REG_VAL(reg_val, PWM_DIV_M_SHIFT, PWM_DIV_M_WIDTH, div_m);
    hal_writel(reg_val, reg_addr);
}