/* RTC Set Operational from the Off state. 
Power up the backup domain clocks, enable write access to the backup domain, select the clock source, clear the RTC registers and enable the RTC. */
void rtc_awake_from_off(enum rcc_osc clock_source)
/* RTC Set Operational from the Off state. 
Power up the backup domain clocks, enable write access to the backup domain, select the clock source, clear the RTC registers and enable the RTC. */
void rtc_awake_from_off(enum rcc_osc clock_source)
{
	uint32_t reg32;
	rcc_periph_clock_enable(RCC_PWR);
	rcc_periph_clock_enable(RCC_BKP);
	pwr_disable_backup_domain_write_protect();
	rcc_set_rtc_clock_source(clock_source);
	RTC_CRH = 0;
	RTC_CRL = 0;
	rcc_enable_rtc_clock();
	rtc_enter_config_mode();
	RTC_PRLH = 0;
	RTC_PRLL = 0;
	RTC_CNTH = 0;
	RTC_CNTL = 0;
	RTC_ALRH = 0xFFFF;
	RTC_ALRL = 0xFFFF;
	rtc_exit_config_mode();
	RTC_CRL &= ~RTC_CRL_RSF;
	while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0);
}