/* Returns PWM_CPR_CLKA, PWM_CPR_CLKB, or negative errno. The allocated clock will run with a period of (2^prescale * div) / MCK, or twice as long if center aligned PWM output is used. The clock must later be deconfigured using pwm_clk_free().  */
int pwm_clk_alloc(unsigned prescale, unsigned div)
/* Returns PWM_CPR_CLKA, PWM_CPR_CLKB, or negative errno. The allocated clock will run with a period of (2^prescale * div) / MCK, or twice as long if center aligned PWM output is used. The clock must later be deconfigured using pwm_clk_free().  */
int pwm_clk_alloc(unsigned prescale, unsigned div)
{
	unsigned long	flags;
	u32		mr;
	u32		val = (prescale << 8) | div;
	int		ret = -EBUSY;
	if (prescale >= 10 || div == 0 || div > 255)
		return -EINVAL;
	spin_lock_irqsave(&pwm->lock, flags);
	mr = pwm_readl(pwm, PWM_MR);
	if ((mr & 0xffff) == 0) {
		mr |= val;
		ret = PWM_CPR_CLKA;
	} else if ((mr & (0xffff << 16)) == 0) {
		mr |= val << 16;
		ret = PWM_CPR_CLKB;
	}
	if (ret > 0)
		pwm_writel(pwm, PWM_MR, mr);
	spin_unlock_irqrestore(&pwm->lock, flags);
	return ret;
}