/* Interrupt handler for legacy INTx interrupts for T3B-based cards. Handles data events from SGE response queues as well as error and other async events as they all use the same interrupt pin. We use one SGE response queue per port in this mode and protect all response queues with queue 0's lock.  */
static irqreturn_t t3b_intr(int irq, void *cookie)
/* Interrupt handler for legacy INTx interrupts for T3B-based cards. Handles data events from SGE response queues as well as error and other async events as they all use the same interrupt pin. We use one SGE response queue per port in this mode and protect all response queues with queue 0's lock.  */
static irqreturn_t t3b_intr(int irq, void *cookie)
{
	u32 map;
	struct adapter *adap = cookie;
	struct sge_rspq *q0 = &adap->sge.qs[0].rspq;
	t3_write_reg(adap, A_PL_CLI, 0);
	map = t3_read_reg(adap, A_SG_DATA_INTR);
	if (unlikely(!map))
		return IRQ_NONE;
	spin_lock(&q0->lock);
	if (unlikely(map & F_ERRINTR))
		t3_slow_intr_handler(adap);
	if (likely(map & 1))
		process_responses_gts(adap, q0);
	if (map & 2)
		process_responses_gts(adap, &adap->sge.qs[1].rspq);
	spin_unlock(&q0->lock);
	return IRQ_HANDLED;
}