/* Configures the main PLL clock source, multiplication and division factors.  */
void RCM_ConfigPLL1(uint32_t pllSelect, uint32_t inputDiv, uint32_t vcoMul, RCM_PLL_SYS_DIV_T sysDiv, uint32_t appDiv)
/* Configures the main PLL clock source, multiplication and division factors.  */
void RCM_ConfigPLL1(uint32_t pllSelect, uint32_t inputDiv, uint32_t vcoMul, RCM_PLL_SYS_DIV_T sysDiv, uint32_t appDiv)
{
    RCM->PLL1CFG_B.PLL1CLKS = pllSelect;
    RCM->PLL1CFG_B.PLLB = inputDiv;
    RCM->PLL1CFG_B.PLL1A = vcoMul;
    RCM->PLL1CFG_B.PLL1C = sysDiv;
    RCM->PLL1CFG_B.PLLD = appDiv;
}