/* The set destination address hold transfer size. The destination address hold or loop transfer size is when the DMA transfer data to destination address (TA), if the loop size is 4, the DMA will write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, TA + 1 ... and so on.  */
static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
/* The set destination address hold transfer size. The destination address hold or loop transfer size is when the DMA transfer data to destination address (TA), if the loop size is 4, the DMA will write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, TA + 1 ... and so on.  */
static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
{
	switch (size) {
	case 0:
		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
			(~FSL_DMA_MR_DAHE), 32);
		break;
	case 1:
	case 2:
	case 4:
	case 8:
		DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
			DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
			FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
			32);
		break;
	}
}