/* The hardware priority mechanism will only look at the upper N bits of the priority level (where N is 3 for the Stellaris family), so any prioritization must be performed in those bits. The remaining bits can be used to sub-prioritize the interrupt sources, and may be used by the hardware priority mechanism on a future part. This arrangement allows priorities to migrate to different NVIC implementations without changing the gross prioritization of the interrupts. */
void xIntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
/* The hardware priority mechanism will only look at the upper N bits of the priority level (where N is 3 for the Stellaris family), so any prioritization must be performed in those bits. The remaining bits can be used to sub-prioritize the interrupt sources, and may be used by the hardware priority mechanism on a future part. This arrangement allows priorities to migrate to different NVIC implementations without changing the gross prioritization of the interrupts. */
void xIntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
{
    xASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
	if(ulInterrupt < 4){
        return ;
    } else if(ulInterrupt < 16){
        xHWREGB(NVIC_SYS_PRI1 + (ulInterrupt - 4)) = ((ucPriority << (8 - NUM_PRIORITY_BITS)) & 0xFF);
    } else {
	    xHWREGB(NVIC_PRI0 + (ulInterrupt - 16)) = ((ucPriority << (8 - NUM_PRIORITY_BITS)) & 0xFF);
    }
}