/* hardware specific access to control-lines ctrl: NAND_CNE: bit 0 -> ! bit 0 & 4 NAND_CLE: bit 1 -> bit 1 NAND_ALE: bit 2 -> bit 2  */
static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
/* hardware specific access to control-lines ctrl: NAND_CNE: bit 0 -> ! bit 0 & 4 NAND_CLE: bit 1 -> bit 1 NAND_ALE: bit 2 -> bit 2  */
static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct sharpsl_nand *sharpsl = mtd_to_sharpsl(mtd);
	struct nand_chip *chip = mtd->priv;
	if (ctrl & NAND_CTRL_CHANGE) {
		unsigned char bits = ctrl & 0x07;
		bits |= (ctrl & 0x01) << 4;
		bits ^= 0x11;
		writeb((readb(sharpsl->io + FLASHCTL) & ~0x17) | bits, sharpsl->io + FLASHCTL);
	}
	if (cmd != NAND_CMD_NONE)
		writeb(cmd, chip->IO_ADDR_W);
}