/* SPI and I2S reset. 
, V1.0.0, firmware for GD32F1x0(x=3,5) , V2.0.0, firmware for GD32F1x0(x=3,5,7,9) , V3.0.0, firmware update for GD32F1x0(x=3,5,7,9) */
void spi_i2s_deinit(uint32_t spi_periph)
/* SPI and I2S reset. 
, V1.0.0, firmware for GD32F1x0(x=3,5) , V2.0.0, firmware for GD32F1x0(x=3,5,7,9) , V3.0.0, firmware update for GD32F1x0(x=3,5,7,9) */
void spi_i2s_deinit(uint32_t spi_periph)
{
    switch(spi_periph){
    case SPI0:
        rcu_periph_reset_enable(RCU_SPI0RST);
        rcu_periph_reset_disable(RCU_SPI0RST);
        break;
    case SPI1:
        rcu_periph_reset_enable(RCU_SPI1RST);
        rcu_periph_reset_disable(RCU_SPI1RST);
        break;
    case SPI2:
        rcu_periph_reset_enable(RCU_SPI2RST);
        rcu_periph_reset_disable(RCU_SPI2RST);
        break;
    default :
        break;
    }
}