/* Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty the same as the CP ring buffer, but in reverse. Rather than the CPU writing to the ring and the GPU consuming, the GPU writes to the ring and host consumes. As the host irq handler processes interrupts, it increments the rptr. When the rptr catches up with the wptr, all the current interrupts have been processed.  */
void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
/* Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty the same as the CP ring buffer, but in reverse. Rather than the CPU writing to the ring and the GPU consuming, the GPU writes to the ring and host consumes. As the host irq handler processes interrupts, it increments the rptr. When the rptr catches up with the wptr, all the current interrupts have been processed.  */
void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
{
	u32 rb_bufsz;
	rb_bufsz = drm_order(ring_size / 4);
	ring_size = (1 << rb_bufsz) * 4;
	rdev->ih.ring_size = ring_size;
	rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
	rdev->ih.rptr = 0;
}