/* Find the best available 7.1 format divisor given a parent clock rate and required child clock rate. This function assumes that a second-stage divisor is available which can divide by powers of 2 from 1 to 256. */
static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, unsigned long rate, int *extra_div)
/* Find the best available 7.1 format divisor given a parent clock rate and required child clock rate. This function assumes that a second-stage divisor is available which can divide by powers of 2 from 1 to 256. */
static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, unsigned long rate, int *extra_div)
{
	int shift;
	int best_divider = -1;
	int best_error = rate;
	for (shift = 0; shift <= 8 && best_error > 0; shift++) {
		unsigned divided_parent = parent_rate >> shift;
		int divider = clk_get_divider(divider_bits, divided_parent,
						rate);
		unsigned effective_rate = get_rate_from_divider(divided_parent,
						divider);
		int error = rate - effective_rate;
		if (divider != -1 && error < best_error) {
			best_error = error;
			*extra_div = 1 << shift;
			best_divider = divider;
		}
	}
	return best_divider;
}