/* configure the PLLT clock multiplication and division factors  */
ErrStatus rcu_pllt_vco_config(uint32_t pllt_psc, uint32_t pllt_mul, uint32_t ppltr_psc)
/* configure the PLLT clock multiplication and division factors  */
ErrStatus rcu_pllt_vco_config(uint32_t pllt_psc, uint32_t pllt_mul, uint32_t ppltr_psc)
{
    uint32_t reg = 0U;
    if((pllt_psc < 2U) || (pllt_psc > 63U)){
        return ERROR;
    }else{
    }
    if((pllt_mul < 49U) || (pllt_mul > 432U)){
        return ERROR;
    }else{
    }
    if((ppltr_psc < 2U) || (ppltr_psc > 7U)){
        return ERROR;
    }else{
    }
    reg = RCU_PLLTCFG;
    reg &= ~(RCU_PLLTCFG_PLLTRPSC | RCU_PLLTCFG_PLLTMF | RCU_PLLTCFG_PLLTPSC);
    reg |= (PLLTCFG_PLLTPSC(pllt_psc) | PLLTCFG_PLLTMF(pllt_mul) | PLLTCFG_PLLTRPSC(ppltr_psc));
    RCU_PLLTCFG = reg;
    return SUCCESS;
}