/* Register a nofault code region which performs a cross-partition PIO read. If the PIO read times out, the MCA handler will consume the error and return to a kernel-provided instruction to indicate an error. This PIO read exists because it is guaranteed to timeout if the destination is down (amo operations do not timeout on at least some CPUs on Shubs <= v1.2, which unfortunately we have to work around).  */
static enum xp_retval xp_register_nofault_code_sn2(void)
/* Register a nofault code region which performs a cross-partition PIO read. If the PIO read times out, the MCA handler will consume the error and return to a kernel-provided instruction to indicate an error. This PIO read exists because it is guaranteed to timeout if the destination is down (amo operations do not timeout on at least some CPUs on Shubs <= v1.2, which unfortunately we have to work around).  */
static enum xp_retval xp_register_nofault_code_sn2(void)
{
	int ret;
	u64 func_addr;
	u64 err_func_addr;
	func_addr = *(u64 *)xp_nofault_PIOR;
	err_func_addr = *(u64 *)xp_error_PIOR;
	ret = sn_register_nofault_code(func_addr, err_func_addr, err_func_addr,
				       1, 1);
	if (ret != 0) {
		dev_err(xp, "can't register nofault code, error=%d\n", ret);
		return xpSalError;
	}
	if (is_shub1())
		xp_nofault_PIOR_target = SH1_IPI_ACCESS;
	else if (is_shub2())
		xp_nofault_PIOR_target = SH2_IPI_ACCESS0;
	return xpSuccess;
}