/* Set write enable latch with Write Enable command. Returns negative if error occurred.  */
static int smi_write_enable(int bank)
/* Set write enable latch with Write Enable command. Returns negative if error occurred.  */
static int smi_write_enable(int bank)
{
	u32 ctrlreg1;
	int timeout = WMODE_TOUT;
	ctrlreg1 = readl(&smicntl->smi_cr1);
	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
	writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
	smi_wait_xfer_finish(XFER_FINISH_TOUT);
	writel(ctrlreg1, &smicntl->smi_cr1);
	while (timeout--) {
		if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT)))
			break;
		udelay(1000);
	}
	if (timeout)
		return 0;
	return -1;
}