/* Get the interrupt status of the SHA/MD5 module. */
uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked)
/* Get the interrupt status of the SHA/MD5 module. */
uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked)
{
    uint32_t ui32Temp;
    uint32_t ui32IrqEnable;
    ASSERT(ui32Base == SHAMD5_BASE);
    if(bMasked)
    {
        ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_MIS);
        ui32IrqEnable = HWREG(ui32Base + SHAMD5_O_IRQENABLE);
        return((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) &
                ui32IrqEnable) | (ui32Temp & 0x00000007) << 16);
    }
    else
    {
        ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_RIS);
        return(HWREG(ui32Base + SHAMD5_O_IRQSTATUS) |
               (ui32Temp & 0x00000007) << 16);
    }
}