/* SPDIF clock configuration. 
Use the default setting as follow: CDCDR(PLL3)->CDCDR(div2)->CDCDR(div8)-> spdif0_clk_root, so the freqency of spdif0_clk should be 480/2/8 = 30MHz.  */
void spdif_clk_cfg(void)
/* SPDIF clock configuration. 
Use the default setting as follow: CDCDR(PLL3)->CDCDR(div2)->CDCDR(div8)-> spdif0_clk_root, so the freqency of spdif0_clk should be 480/2/8 = 30MHz.  */
void spdif_clk_cfg(void)
{
    HW_CCM_CDCDR.B.SPDIF0_CLK_SEL = 3;
    HW_CCM_CDCDR.B.SPDIF0_CLK_PODF = 7;
    HW_CCM_CDCDR.B.SPDIF0_CLK_PRED = 1;
    clock_gating_config(SPDIF_BASE_ADDR, CLOCK_ON);
    return;
}