/* Function to write to the Phy register. The access to phy register is a slow process as the data is moved accross MDI/MDO interface  */
s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data)
/* Function to write to the Phy register. The access to phy register is a slow process as the data is moved accross MDI/MDO interface  */
s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data)
{
    u32 addr;
    u32 loop_variable;
    synopGMACWriteReg(RegBase, GmacGmiiData, data);
    addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) | GmiiWrite;
    addr = addr | GmiiBusy ;
    synopGMACWriteReg(RegBase, GmacGmiiAddr, addr);
    for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++)
    {
        if (!(synopGMACReadReg(RegBase, GmacGmiiAddr) & GmiiBusy))
        {
            break;
        }
        plat_delay(DEFAULT_DELAY_VARIABLE);
    }
    if (loop_variable < DEFAULT_LOOP_VARIABLE)
    {
        return 0;
    }
    else
    {
        TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n");
        return -ESYNOPGMACPHYERR;
    }
}