/* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS  */
static unsigned long calc_pll_rate(u32 config_word)
/* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS  */
static unsigned long calc_pll_rate(u32 config_word)
{
	unsigned long long rate;
	int i;
	rate = clk_xtali.rate;
	rate *= ((config_word >> 11) & 0x1f) + 1;
	rate *= ((config_word >> 5) & 0x3f) + 1;
	do_div(rate, (config_word & 0x1f) + 1);
	for (i = 0; i < ((config_word >> 16) & 3); i++)
		rate >>= 1;
	return (unsigned long)rate;
}