/* FPSR bit field FCC1 | FCC0: 0 = 1 < 2 > 3 unordered  */
static void gen_mov_reg_FCC0(TCGv reg, TCGv src, unsigned int fcc_offset)
/* FPSR bit field FCC1 | FCC0: 0 = 1 < 2 > 3 unordered  */
static void gen_mov_reg_FCC0(TCGv reg, TCGv src, unsigned int fcc_offset)
{
    tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
    tcg_gen_andi_tl(reg, reg, 0x1);
}