/* Reset the SATA port. Algorithm follows AHCI spec 1.3.1 section 10.4.2 */
EFI_STATUS AhciResetPort(IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Port)
/* Reset the SATA port. Algorithm follows AHCI spec 1.3.1 section 10.4.2 */
EFI_STATUS AhciResetPort(IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Port)
{
  UINT32      Offset;
  EFI_STATUS  Status;
  Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
  AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_DET_INIT);
  MicroSecondDelay (1000);
  AhciAndReg (PciIo, Offset, ~(UINT32)EFI_AHCI_PORT_SSTS_DET_MASK);
  Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
  Status = AhciWaitMmioSet (PciIo, Offset, EFI_AHCI_PORT_SSTS_DET_MASK, EFI_AHCI_PORT_SSTS_DET_PCE, ATA_ATAPI_TIMEOUT);
  if (EFI_ERROR (Status)) {
    return Status;
  }
  return AhciWaitDeviceReady (PciIo, Port);
}