/* ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both opcodes are supposed to result in coprocessor unusable exceptions if executed on ll/sc-less processors. That's the theory. In practice a few processors such as NEC's VR4100 throw reserved instruction exceptions instead, so we're doing the emulation thing in both exception handlers.  */
static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
/* ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both opcodes are supposed to result in coprocessor unusable exceptions if executed on ll/sc-less processors. That's the theory. In practice a few processors such as NEC's VR4100 throw reserved instruction exceptions instead, so we're doing the emulation thing in both exception handlers.  */
static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
{
	if ((opcode & OPCODE) == LL)
		return simulate_ll(regs, opcode);
	if ((opcode & OPCODE) == SC)
		return simulate_sc(regs, opcode);
	return -1;
}