/* Normally, the status interrupt is cleared by reading the controller status using  */
void CANIntClear(unsigned long ulBase, unsigned long ulIntClr)
/* Normally, the status interrupt is cleared by reading the controller status using  */
void CANIntClear(unsigned long ulBase, unsigned long ulIntClr)
{
    ASSERT(CANBaseValid(ulBase));
    ASSERT((ulIntClr == CAN_INT_INTID_STATUS) ||
           ((ulIntClr>=1) && (ulIntClr <=32)));
    if(ulIntClr == CAN_INT_INTID_STATUS)
    {
        CANRegRead(ulBase + CAN_O_STS);
    }
    else
    {
        while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
        {
        }
        CANRegWrite(ulBase + CAN_O_IF1CMSK, CAN_IF1CMSK_CLRINTPND);
        CANRegWrite(ulBase + CAN_O_IF1CRQ, ulIntClr & CAN_IF1CRQ_MNUM_M);
        while(CANRegRead(ulBase + CAN_O_IF1CRQ) & CAN_IF1CRQ_BUSY)
        {
        }
    }
}