/* get bit mask of enabled cs return bit mask of enabled cs: 1 - only cs0 enabled, 3 - both cs0 and cs1 enabled  */
u32 mv_ddr_sys_env_get_cs_ena_from_reg(void)
/* get bit mask of enabled cs return bit mask of enabled cs: 1 - only cs0 enabled, 3 - both cs0 and cs1 enabled  */
u32 mv_ddr_sys_env_get_cs_ena_from_reg(void)
{
	return reg_read(DDR3_RANK_CTRL_REG) &
		((CS_EXIST_MASK << CS_EXIST_OFFS(0)) |
		 (CS_EXIST_MASK << CS_EXIST_OFFS(1)) |
		 (CS_EXIST_MASK << CS_EXIST_OFFS(2)) |
		 (CS_EXIST_MASK << CS_EXIST_OFFS(3)));
}