/* After the DRAM is powered up or reset, the DDR3 spec requires to wait at least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct (SDR_IDCR) register appears to configure this delay, which gets applied right at the time when the DRAM initialization is activated in the 'mctl_ddr3_initialize' function.  */
static void mctl_set_cke_delay(void)
/* After the DRAM is powered up or reset, the DDR3 spec requires to wait at least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct (SDR_IDCR) register appears to configure this delay, which gets applied right at the time when the DRAM initialization is activated in the 'mctl_ddr3_initialize' function.  */
static void mctl_set_cke_delay(void)
{
	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
	setbits_le32(&dram->idcr, 0x1ffff);
}