/* Set the PLL clock divisor (from 400MHz) 
USERCC2 must have been set by a call to  */
void rcc_set_pll_divisor(uint8_t div400)
/* Set the PLL clock divisor (from 400MHz) 
USERCC2 must have been set by a call to  */
void rcc_set_pll_divisor(uint8_t div400)
{
	uint32_t reg32;
	SYSCTL_RCC |= SYSCTL_RCC_USESYSDIV;
	reg32 = SYSCTL_RCC2;
	reg32 &= ~SYSCTL_RCC2_SYSDIV400_MASK;
	reg32 |= ((div400 - 1) << 22) & SYSCTL_RCC2_SYSDIV400_MASK;
	reg32 |= SYSCTL_RCC2_DIV400;
	SYSCTL_RCC2 = reg32;
}