/* Memory accesses are permitted and maintenance operation begins. Until this bit is set to a 1, the memory controller will not accept DRAM requests from the MEMORY_MANAGER or HTE.  */
void set_ddr_init_complete(struct mrc_params *mrc_params)
/* Memory accesses are permitted and maintenance operation begins. Until this bit is set to a 1, the memory controller will not accept DRAM requests from the MEMORY_MANAGER or HTE.  */
void set_ddr_init_complete(struct mrc_params *mrc_params)
{
	u32 dco;
	ENTERFN();
	dco = msg_port_read(MEM_CTLR, DCO);
	dco &= ~DCO_PMICTL;
	dco |= DCO_IC;
	msg_port_write(MEM_CTLR, DCO, dco);
	LEAVEFN();
}