/* Read and write, they both share the same lock. We do this to serialize reads and writes on Atheros 802.11n PCI devices only. This is required as the FIFO on these devices can only accept sanely 2 requests. After that the device goes bananas. Serializing the reads/writes prevents this from happening.  */
static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
/* Read and write, they both share the same lock. We do this to serialize reads and writes on Atheros 802.11n PCI devices only. This is required as the FIFO on these devices can only accept sanely 2 requests. After that the device goes bananas. Serializing the reads/writes prevents this from happening.  */
static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
{
	struct ath_hw *ah = (struct ath_hw *) hw_priv;
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
		unsigned long flags;
		spin_lock_irqsave(&sc->sc_serial_rw, flags);
		iowrite32(val, sc->mem + reg_offset);
		spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
	} else
		iowrite32(val, sc->mem + reg_offset);
}