/* Program the DPLL with the supplied M, N values, and wait for the DPLL to lock.. Returns -EINVAL upon error, or 0 upon success.  */
int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
/* Program the DPLL with the supplied M, N values, and wait for the DPLL to lock.. Returns -EINVAL upon error, or 0 upon success.  */
int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
{
	struct dpll_data *dd = clk->dpll_data;
	u32 v;
	_omap3_noncore_dpll_bypass(clk);
	if (!cpu_is_omap44xx()) {
		v = __raw_readl(dd->control_reg);
		v &= ~dd->freqsel_mask;
		v |= freqsel << __ffs(dd->freqsel_mask);
		__raw_writel(v, dd->control_reg);
	}
	v = __raw_readl(dd->mult_div1_reg);
	v &= ~(dd->mult_mask | dd->div1_mask);
	v |= m << __ffs(dd->mult_mask);
	v |= (n - 1) << __ffs(dd->div1_mask);
	__raw_writel(v, dd->mult_div1_reg);
	_omap3_noncore_dpll_lock(clk);
	return 0;
}