/* Configure a FIFOCON register of the CAN controller to be transmit FIFO. */
static int32_t can_ctrl_tx_fifo_config(struct can_ctrl_dev *dev, uint8_t fifo_nr, struct can_ctrl_init_param *init_param)
/* Configure a FIFOCON register of the CAN controller to be transmit FIFO. */
static int32_t can_ctrl_tx_fifo_config(struct can_ctrl_dev *dev, uint8_t fifo_nr, struct can_ctrl_init_param *init_param)
{
	int32_t ret;
	uint32_t temp;
	ret = can_ctrl_sfr_word_read(dev, CAN_CTRL_REG_FIFOCON(fifo_nr), &temp);
	if(ret != 0)
		return ret;
	temp &= ~FIFOCON_PLSIZE_MODE(WORD_MASK);
	temp &= ~FIFOCON_FSIZE_MODE(WORD_MASK);
	temp &= ~FIFOCON_TXPRI_MODE(WORD_MASK);
	temp &= ~FIFOCON_TXEN_MODE(WORD_MASK);
	temp |= FIFOCON_PLSIZE_MODE(init_param->tx_fifo_plsize);
	temp |= FIFOCON_FSIZE_MODE((init_param->tx_fifo_size - 1));
	temp |= FIFOCON_TXPRI_MODE(init_param->tx_fifo_priority);
	temp |= FIFOCON_TXEN_MODE(true);
	return can_ctrl_sfr_word_write(dev, CAN_CTRL_REG_FIFOCON(fifo_nr), temp);
}