/* Sets the LPLU state according to the active flag. For PCH, if OEM write bit are disabled in the NVM, writing the LPLU bits in the MAC will not set the phy speed. This function will manually set the LPLU bit and restart auto-neg as hw would do. D3 and D0 LPLU will call the same function since it configures the same bit.  */
static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
/* Sets the LPLU state according to the active flag. For PCH, if OEM write bit are disabled in the NVM, writing the LPLU bits in the MAC will not set the phy speed. This function will manually set the LPLU bit and restart auto-neg as hw would do. D3 and D0 LPLU will call the same function since it configures the same bit.  */
static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
{
	s32 ret_val = 0;
	u16 oem_reg;
	ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
	if (ret_val)
		goto out;
	if (active)
		oem_reg |= HV_OEM_BITS_LPLU;
	else
		oem_reg &= ~HV_OEM_BITS_LPLU;
	oem_reg |= HV_OEM_BITS_RESTART_AN;
	ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
out:
	return ret_val;
}