/* The transfer end interrupt must read the chcr register to end the hardware interrupt active condition. Besides that it needs to waken any waiting process, which should handle setting up the next transfer.  */
static irqreturn_t dma_tei(int irq, void *dev_id)
/* The transfer end interrupt must read the chcr register to end the hardware interrupt active condition. Besides that it needs to waken any waiting process, which should handle setting up the next transfer.  */
static irqreturn_t dma_tei(int irq, void *dev_id)
{
	struct dma_channel *chan = dev_id;
	u32 chcr;
	chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
	if (!(chcr & CHCR_TE))
		return IRQ_NONE;
	chcr &= ~(CHCR_IE | CHCR_DE);
	ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
	wake_up(&chan->wait_queue);
	return IRQ_HANDLED;
}