/* The active part of our cycle counter is only 32-bits wide, and we're treating the difference between two marks as signed. On a 1GHz box, that's about 2 seconds.  */
void __delay(unsigned long loops)
/* The active part of our cycle counter is only 32-bits wide, and we're treating the difference between two marks as signed. On a 1GHz box, that's about 2 seconds.  */
void __delay(unsigned long loops)
{
	long long dummy;
	__asm__ __volatile__("gettr	tr0, %1\n\t"
			     "pta	$+4, tr0\n\t"
			     "addi	%0, -1, %0\n\t"
			     "bne	%0, r63, tr0\n\t"
			     "ptabs	%1, tr0\n\t":"=r"(loops),
			     "=r"(dummy)
			     :"0"(loops));
}