/* Load DQS settings for Write Group, do not trigger SCC update.  */
static void scc_mgr_load_dqs_for_write_group(struct socfpga_sdrseq *seq, const u32 write_group)
/* Load DQS settings for Write Group, do not trigger SCC update.  */
static void scc_mgr_load_dqs_for_write_group(struct socfpga_sdrseq *seq, const u32 write_group)
{
	const int ratio = seq->rwcfg->mem_if_read_dqs_width /
			  seq->rwcfg->mem_if_write_dqs_width;
	const int base = write_group * ratio;
	int i;
	for (i = 0; i < ratio; i++)
		writel(base + i, &sdr_scc_mgr->dqs_ena);
}