/* The total pulse clock count is an 18 bit pulse width timer count as the most significant part and (up to) 16 bit clock divider count as a modulus. When the Rx clock divider ticks down to 0, it increments the 18 bit pulse width timer count's least significant bit.  */
static u64 ns_to_pulse_clocks(u32 ns)
/* The total pulse clock count is an 18 bit pulse width timer count as the most significant part and (up to) 16 bit clock divider count as a modulus. When the Rx clock divider ticks down to 0, it increments the 18 bit pulse width timer count's least significant bit.  */
static u64 ns_to_pulse_clocks(u32 ns)
{
	u64 clocks;
	u32 rem;
	clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns;
	rem = do_div(clocks, 1000);
	if (rem >= 1000 / 2)
		clocks++;
	return clocks;
}