/* This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers. The sequencer must be disabled before writing to these regsiters. */
int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
/* This function enables the averaging for the specified channels in the ADC Channel Averaging Enable Sequencer Registers. The sequencer must be disabled before writing to these regsiters. */
int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}
	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ02_OFFSET,
				(AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ03_OFFSET,
				(AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
				XADCPS_SEQ03_CH_VALID_MASK);
	return XST_SUCCESS;
}