/* param pll Which PLL of targeting PFD to be operated. param pfd Which PFD clock to enable.  */
void CLOCK_DeinitPfd(clock_pll_t pll, clock_pfd_t pfd)
/* param pll Which PLL of targeting PFD to be operated. param pfd Which PFD clock to enable.  */
void CLOCK_DeinitPfd(clock_pll_t pll, clock_pfd_t pfd)
{
    volatile uint32_t *pfdCtrl = NULL;
    switch (pll)
    {
        case kCLOCK_PllSys2:
        {
            pfdCtrl = &ANADIG_PLL->SYS_PLL2_PFD;
            break;
        }
        case kCLOCK_PllSys3:
        {
            pfdCtrl = &ANADIG_PLL->SYS_PLL3_PFD;
            break;
        }
        default:
        {
            assert(false);
            break;
        }
    }
    *pfdCtrl |= ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK << (8UL * (uint32_t)pfd));
}