/* The ST_CRTR is updated asynchronously to the master clock ... but the updates as seen by the CPU don't seem to be strictly monotonic. Waiting until we read the same value twice avoids glitching.  */
static unsigned long read_CRTR(void)
/* The ST_CRTR is updated asynchronously to the master clock ... but the updates as seen by the CPU don't seem to be strictly monotonic. Waiting until we read the same value twice avoids glitching.  */
static unsigned long read_CRTR(void)
{
	unsigned long x1, x2;
	x1 = at91_sys_read(AT91_ST_CRTR);
	do {
		x2 = at91_sys_read(AT91_ST_CRTR);
		if (x1 == x2)
			break;
		x1 = x2;
	} while (1);
	return x1;
}