/* memSpace = IDMA memory window number from 0 to 7 trg_if = Target interface: 0x0 DRAM 0x1 Device Bus 0x2 Integrated SDRAM (or CPU bus 60x only) 0x3 PCI0 0x4 PCI1 attr = IDMA attributes (see MV datasheet) base_addr = Sets up memory window for transfers  */
int mvDmaSetMemorySpace(ulong, ulong, ulong, ulong, ulong)
/* memSpace = IDMA memory window number from 0 to 7 trg_if = Target interface: 0x0 DRAM 0x1 Device Bus 0x2 Integrated SDRAM (or CPU bus 60x only) 0x3 PCI0 0x4 PCI1 attr = IDMA attributes (see MV datasheet) base_addr = Sets up memory window for transfers  */
int mvDmaSetMemorySpace(ulong, ulong, ulong, ulong, ulong)
{
	ulong temp;
	if (base_addr % size != 0)
		return 0;
	if (size >= 0x10000) {
		size &= 0xffff0000;
		base_addr = (base_addr & 0xffff0000);
		GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
			      (base_addr | trg_if | attr));
		GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
			      (size - 1) & 0xffff0000);
		temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
		GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
			      (temp & ~(BIT0 << memSpace)));
		return 1;
	}
	return 0;
}