/* mtk_pll_calc_values - calculate good values for a given input frequency. @clk: The clk @pcw: The pcw value (output) @postdiv: The post divider (output) @freq: The desired target frequency  */
static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, u32 freq)
/* mtk_pll_calc_values - calculate good values for a given input frequency. @clk: The clk @pcw: The pcw value (output) @postdiv: The post divider (output) @freq: The desired target frequency  */
static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, u32 freq)
{
	struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
	const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
	unsigned long fmin = 1000 * MHZ;
	u64 _pcw;
	u32 val;
	if (freq > pll->fmax)
		freq = pll->fmax;
	for (val = 0; val < 5; val++) {
		*postdiv = 1 << val;
		if ((u64)freq * *postdiv >= fmin)
			break;
	}
	_pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS);
	do_div(_pcw, priv->tree->xtal2_rate);
	*pcw = (u32)_pcw;
}