/* The hardware priority mechanism will only look at the upper N bits of the priority level (where N is 3 for the Stellaris family), so any prioritization must be performed in those bits. The remaining bits can be used to sub-prioritize the interrupt sources, and may be used by the hardware priority mechanism on a future part. This arrangement allows priorities to migrate to different NVIC implementations without changing the gross prioritization of the interrupts. */
void xIntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
/* The hardware priority mechanism will only look at the upper N bits of the priority level (where N is 3 for the Stellaris family), so any prioritization must be performed in those bits. The remaining bits can be used to sub-prioritize the interrupt sources, and may be used by the hardware priority mechanism on a future part. This arrangement allows priorities to migrate to different NVIC implementations without changing the gross prioritization of the interrupts. */
void xIntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
{
    unsigned long ulTemp;
    xASSERT(((ulInterrupt & 0xFF) == 0) || (((ulInterrupt & 0xFF) >= 4) &&
            ((ulInterrupt & 0xFF) < NUM_INTERRUPTS)));
    if((ulInterrupt & 0xFF) != 0)
    {
        ulTemp = xHWREG(g_pulRegs[(ulInterrupt & 0xFF) >> 2]);
        ulTemp &= ~(0xFF << (8 * ((ulInterrupt & 0xFF) & 3)));
        ulTemp |= ucPriority << (8 * ((ulInterrupt & 0xFF) & 3));
        xHWREG(g_pulRegs[(ulInterrupt & 0xFF) >> 2]) = ulTemp;
    }
}