/* enable internal loopback TxCLK and RxCLK are generated from BRG and TxD is looped back to RxD internally.  */
static void enable_loopback(struct slgt_info *info)
/* enable internal loopback TxCLK and RxCLK are generated from BRG and TxD is looped back to RxD internally.  */
static void enable_loopback(struct slgt_info *info)
{
	wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
	if (info->params.mode != MGSL_MODE_ASYNC) {
		wr_reg8(info, CCR, 0x49);
		if (info->params.clock_speed)
			set_rate(info, info->params.clock_speed);
		else
			set_rate(info, 3686400);
	}
}