/* NOTE: it is a must to set ND_RUN first, then write command buffer, otherwise, it does not work. We enable all the interrupt at the same time, and let pxa3xx_nand_irq to handle all logic.  */
static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
/* NOTE: it is a must to set ND_RUN first, then write command buffer, otherwise, it does not work. We enable all the interrupt at the same time, and let pxa3xx_nand_irq to handle all logic.  */
static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
{
	uint32_t ndcr;
	ndcr = info->reg_ndcr;
	if (info->use_ecc) {
		ndcr |= NDCR_ECC_EN;
		if (info->ecc_bch)
			nand_writel(info, NDECCCTRL, 0x1);
	} else {
		ndcr &= ~NDCR_ECC_EN;
		if (info->ecc_bch)
			nand_writel(info, NDECCCTRL, 0x0);
	}
	ndcr &= ~NDCR_DMA_EN;
	if (info->use_spare)
		ndcr |= NDCR_SPARE_EN;
	else
		ndcr &= ~NDCR_SPARE_EN;
	ndcr |= NDCR_ND_RUN;
	nand_writel(info, NDSR, NDSR_MASK);
	nand_writel(info, NDCR, 0);
	nand_writel(info, NDCR, ndcr);
}