/* 1 Mhz <= Fref <= 50 Mhz 200 Mhz <= Fvco <= 400 Mhz  */
void arc_iot_pll_conf_reg(uint32_t val)
/* 1 Mhz <= Fref <= 50 Mhz 200 Mhz <= Fvco <= 400 Mhz  */
void arc_iot_pll_conf_reg(uint32_t val)
{
	sysconf_reg_ptr->CLKSEL = CLKSEL_EXT_16M;
	sysconf_reg_ptr->PLLCON = val | (0x52000000);
	sysconf_reg_ptr->PLLCON = val | (1 << PLLCON_BIT_OFFSET_PLLRST);
	sysconf_reg_ptr->PLLCON = val & (~(1 << PLLCON_BIT_OFFSET_PLLRST));
	while (!(sysconf_reg_ptr->PLLSTAT & (1 << PLLSTAT_BIT_OFFSET_PLLSTB))) {
		;
	}
	sysconf_reg_ptr->CLKSEL = CLKSEL_PLL;
	sysconf_reg_ptr->AHBCLKDIV_SEL |= 1;
	sysconf_reg_ptr->AHBCLKDIV = 0x1;
}