/* Check the status of the FIFO buffer of the specified SPI port.  */
void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulRxTx, unsigned long ulLength)
/* Check the status of the FIFO buffer of the specified SPI port.  */
void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulRxTx, unsigned long ulLength)
{
    xASSERT(ulBase == SPI0_BASE);
    xASSERT((ulRxTx == SPI_FSR_RX) || (ulRxTx == SPI_FSR_TX));
    xASSERT((ulLength >= 0) || (ulLength <= 8));
    if(ulRxTx == SPI_FSR_RX)
    {
	    xHWREG(ulBase + SPI_FCR) &= ~((ulLength << SPI_FCR_RXFTLS_S) & SPI_FCR_RXFTLS_M);
        xHWREG(ulBase + SPI_FCR) |= (ulLength << SPI_FCR_RXFTLS_S) & SPI_FCR_RXFTLS_M;
    }
    else
    {	xHWREG(ulBase + SPI_FCR) &= ~((ulLength << SPI_FCR_TXFTLS_S) & SPI_FCR_TXFTLS_M);
        xHWREG(ulBase + SPI_FCR) |= (ulLength << SPI_FCR_TXFTLS_S) & SPI_FCR_TXFTLS_M;
    } 
}