/* ISR will determine that interrupt arrives either for READ or WRITE command. According to command it will do the appropriate action. It will check transfer length and if it is not zero then dispatch transfer command again. If transfer length is zero then it will indicate the COMPLETION so that davinci_spi_bufs function can go ahead.  */
static void davinci_spi_irq(int irq, void *data)
/* ISR will determine that interrupt arrives either for READ or WRITE command. According to command it will do the appropriate action. It will check transfer length and if it is not zero then dispatch transfer command again. If transfer length is zero then it will indicate the COMPLETION so that davinci_spi_bufs function can go ahead.  */
static void davinci_spi_irq(int irq, void *data)
{
    struct davinci_spi *dspi = data;
    int status;
    status = davinci_spi_process_events(dspi);
    if (unlikely(status != 0))
        clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
    if ((!dspi->rcount && !dspi->wcount) || status)
        rt_completion_done(&dspi->done);
}