/* The following are all MBUS based SRMMU modules, and therefore could be found in a multiprocessor configuration. On the whole, these chips seems to be much more touchy about DVMA and page tables with respect to cache coherency.  */
static void cypress_flush_cache_all(void)
/* The following are all MBUS based SRMMU modules, and therefore could be found in a multiprocessor configuration. On the whole, these chips seems to be much more touchy about DVMA and page tables with respect to cache coherency.  */
static void cypress_flush_cache_all(void)
{
	volatile unsigned long cypress_sucks;
	unsigned long faddr, tagval;
	flush_user_windows();
	for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
		__asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
				     "=r" (tagval) :
				     "r" (faddr), "r" (0x40000),
				     "i" (ASI_M_DATAC_TAG));
		if((tagval & 0x60) == 0x60)
			cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
	}
}