/* Internal function to retrieve the architecture specific spin lock alignment requirements for optimal spin lock performance. */
UINTN InternalGetSpinLockProperties(VOID)
/* Internal function to retrieve the architecture specific spin lock alignment requirements for optimal spin lock performance. */
UINTN InternalGetSpinLockProperties(VOID)
{
  UINT32  RegEax;
  UINT32  RegEbx;
  UINTN   FamilyId;
  UINTN   ModelId;
  UINTN   CacheLineSize;
  AsmCpuid (0x01, &RegEax, &RegEbx, NULL, NULL);
  CacheLineSize = ((RegEbx >> 8) & 0xff) * 8;
  FamilyId = (RegEax >> 8) & 0xf;
  ModelId  = (RegEax >> 4) & 0xf;
  if (FamilyId == 0x0f) {
    ModelId = ModelId | ((RegEax >> 12) & 0xf0);
    if ((ModelId <= 0x04) || (ModelId == 0x06)) {
      CacheLineSize *= 2;
    }
  }
  if (CacheLineSize < 32) {
    CacheLineSize = 32;
  }
  return CacheLineSize;
}