/* compute BRG and DIV bits to setup spi clock based on main input clock rate that was specified in platform data structure according to au1550 datasheet: psc_tempclk = psc_mainclk / (2 << DIV) spiclk = psc_tempclk / (2 * (BRG + 1)) BRG valid range is 4..63 DIV valid range is 0..3  */
static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
/* compute BRG and DIV bits to setup spi clock based on main input clock rate that was specified in platform data structure according to au1550 datasheet: psc_tempclk = psc_mainclk / (2 << DIV) spiclk = psc_tempclk / (2 * (BRG + 1)) BRG valid range is 4..63 DIV valid range is 0..3  */
static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
{
	u32 mainclk_hz = hw->pdata->mainclk_hz;
	u32 div, brg;
	for (div = 0; div < 4; div++) {
		brg = mainclk_hz / speed_hz / (4 << div);
		if (brg < (4 + 1)) {
			brg = (4 + 1);
			break;
		}
		if (brg <= (63 + 1))
			break;
	}
	if (div == 4) {
		div = 3;
		brg = (63 + 1);
	}
	brg--;
	return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
}