/* Check the status of the FIFO buffer of the specified SPI port.  */
unsigned long SPIFIFOStatusGet(unsigned long ulBase)
/* Check the status of the FIFO buffer of the specified SPI port.  */
unsigned long SPIFIFOStatusGet(unsigned long ulBase)
{
    xASSERT((ulBase == SPI0_BASE) || (ulBase == SPI1_BASE)||
            (ulBase == SPI2_BASE)||(ulBase == SPI3_BASE) );
    return (xHWREG(ulBase + SPI_CNTRL) & (SPI_CNTRL_TX_FULL) || 
            (SPI_CNTRL_RX_FULL) || (SPI_CNTRL_TX_EMPTY) || (SPI_CNTRL_RX_EMPTY));
}