/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly when a core is woken up  */
static int pcode_ready(void)
/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly when a core is woken up  */
static int pcode_ready(void)
{
	int wait_count;
	const int delay_step = 10;
	wait_count = 0;
	do {
		if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
				MAILBOX_RUN_BUSY))
			return 0;
		wait_count += delay_step;
		udelay(delay_step);
	} while (wait_count < 1000);
	return -ETIMEDOUT;
}