/* where f is the bus clock frequency in MHz, and f is the MDIO clock frequency in MHz to the PHY. Typically, f should not exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster access. Here is the table to show values to generate MDC, */
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
/* where f is the bus clock frequency in MHz, and f is the MDIO clock frequency in MHz to the PHY. Typically, f should not exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster access. Here is the table to show values to generate MDC, */
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
{
    u32 Reg;
    Xil_AssertVoid(InstancePtr != NULL);
    Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
    Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7);
    Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
                XEMACPS_NWCFG_OFFSET);
    Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
    Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
    XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
               XEMACPS_NWCFG_OFFSET, Reg);
}