/* This function enables the specified channels in the ADC Channel Selection Sequencer Registers. The sequencer must be disabled before writing to these regsiters. */
int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
/* This function enables the specified channels in the ADC Channel Selection Sequencer Registers. The sequencer must be disabled before writing to these regsiters. */
int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}
	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ00_OFFSET,
				(ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ01_OFFSET,
				(ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
				XADCPS_SEQ01_CH_VALID_MASK);
	return XST_SUCCESS;
}