/* Compile time sanity checks for defined board clock setup Verify that the request PLL1 output frequency fits the range of 156 MHz to 320 MHz, so that the PLL1 Direct Mode is applicable. Our clock configuration code ( */
static void cycle_delay(int n)
/* Compile time sanity checks for defined board clock setup Verify that the request PLL1 output frequency fits the range of 156 MHz to 320 MHz, so that the PLL1 Direct Mode is applicable. Our clock configuration code ( */
static void cycle_delay(int n)
{
	volatile int i;
	for (i = 0; i < n; i++);
}