/* get aligned address and the number of cachline to be invalied 
example 2: addr = 0x104 (cacheline unaligned), size = 64 then head = 0x100, number of cache line to be invalidated = 1 + 64 / 32 = 3 which means range [0x100, 0x160) will be invalidated  */
static uint32_t get_n_cacheline(uint32_t addr, uint32_t size, uint32_t *p_head)
/* get aligned address and the number of cachline to be invalied 
example 2: addr = 0x104 (cacheline unaligned), size = 64 then head = 0x100, number of cache line to be invalidated = 1 + 64 / 32 = 3 which means range [0x100, 0x160) will be invalidated  */
static uint32_t get_n_cacheline(uint32_t addr, uint32_t size, uint32_t *p_head)
{
	uint32_t n = 0;
	uint32_t tail;
	*p_head = CACHE_ALIGNED_ADDR(addr);
	tail = addr + size + (CACHE_LINE_SIZE - 1);
	tail = CACHE_ALIGNED_ADDR(tail);
	n = (tail - *p_head) >> CACHE_LINE_SIZE_LOG2;
	return n;
}