/* Find working or non-working DQS enable phase setting.  */
static int sdr_find_phase(struct socfpga_sdrseq *seq, int working, const u32 grp, u32 *work, u32 *i, u32 *p)
/* Find working or non-working DQS enable phase setting.  */
static int sdr_find_phase(struct socfpga_sdrseq *seq, int working, const u32 grp, u32 *work, u32 *i, u32 *p)
{
	const u32 end = seq->misccfg->read_valid_fifo_size + (working ? 0 : 1);
	int ret;
	for (; *i < end; (*i)++) {
		if (working)
			*p = 0;
		ret = sdr_find_phase_delay(seq, working, 0, grp, work,
					   seq->iocfg->delay_per_opa_tap, p);
		if (!ret)
			return 0;
		if (*p > seq->iocfg->dqs_en_phase_max) {
			rw_mgr_incr_vfifo(grp);
			if (!working)
				*p = 0;
		}
	}
	return -EINVAL;
}