/* On paper, memory read barriers may be needed here to prevent out of order LOADs by the CPU from having prefetched stale data prior to DMA having occurred.  */
static int sym_wakeup_done(struct sym_hcb *np)
/* On paper, memory read barriers may be needed here to prevent out of order LOADs by the CPU from having prefetched stale data prior to DMA having occurred.  */
static int sym_wakeup_done(struct sym_hcb *np)
{
	struct sym_ccb *cp;
	int i, n;
	u32 dsa;
	n = 0;
	i = np->dqueueget;
	while (1) {
		dsa = scr_to_cpu(np->dqueue[i]);
		if (!dsa)
			break;
		np->dqueue[i] = 0;
		if ((i = i+2) >= MAX_QUEUE*2)
			i = 0;
		cp = sym_ccb_from_dsa(np, dsa);
		if (cp) {
			MEMORY_READ_BARRIER();
			sym_complete_ok (np, cp);
			++n;
		}
		else
			printf ("%s: bad DSA (%x) in done queue.\n",
				sym_name(np), (u_int) dsa);
	}
	np->dqueueget = i;
	return n;
}