/* Invoked from macros defined in mmu_context.h which must already have disabled interrupts and done a DVPE or DMT as appropriate.  */
void smtc_flush_tlb_asid(unsigned long asid)
/* Invoked from macros defined in mmu_context.h which must already have disabled interrupts and done a DVPE or DMT as appropriate.  */
void smtc_flush_tlb_asid(unsigned long asid)
{
	int entry;
	unsigned long ehi;
	entry = read_c0_wired();
	while (entry < current_cpu_data.tlbsize) {
		write_c0_index(entry);
		ehb();
		tlb_read();
		ehb();
		ehi = read_c0_entryhi();
		if ((ehi & ASID_MASK) == asid) {
		    write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
		    write_c0_entrylo0(0);
		    write_c0_entrylo1(0);
		    mtc0_tlbw_hazard();
		    tlb_write_indexed();
		}
		entry++;
	}
	write_c0_index(PARKED_INDEX);
	tlbw_use_hazard();
}