/* Configure the link capabilities and speed in the PCIe root complex.  */
static void pcie_dw_configure(struct pcie_dw_ti *pci, u32 cap_speed)
/* Configure the link capabilities and speed in the PCIe root complex.  */
static void pcie_dw_configure(struct pcie_dw_ti *pci, u32 cap_speed)
{
	u32 val;
	dw_pcie_dbi_write_enable(pci, true);
	val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY);
	val &= ~TARGET_LINK_SPEED_MASK;
	val |= cap_speed;
	writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY);
	val = readl(pci->dbi_base + PCIE_LINK_CTL_2);
	val &= ~TARGET_LINK_SPEED_MASK;
	val |= cap_speed;
	writel(val, pci->dbi_base + PCIE_LINK_CTL_2);
	dw_pcie_dbi_write_enable(pci, false);
}