/*  
Switch performance level to PL2 and GCLK0 is running at 48MHz.  */
static void performance_level_switch_test(void)
/*  
Switch performance level to PL2 and GCLK0 is running at 48MHz.  */
static void performance_level_switch_test(void)
{
	struct system_gclk_gen_config gclk_conf;
	system_switch_performance_level(SYSTEM_PERFORMANCE_LEVEL_2);
	system_flash_set_waitstates(2);
	system_gclk_gen_get_config_defaults(&gclk_conf);
	gclk_conf.source_clock = SYSTEM_CLOCK_SOURCE_DFLL;
	gclk_conf.division_factor = 1;
	gclk_conf.run_in_standby  = false;
	gclk_conf.output_enable   = true;
	system_gclk_gen_set_config(GCLK_GENERATOR_0, &gclk_conf);
}