/* lcdif pixel clock is derived from PLL3(480MHz) and set as 33.5MHz  */
void lcdif_clock_enable(void)
/* lcdif pixel clock is derived from PLL3(480MHz) and set as 33.5MHz  */
void lcdif_clock_enable(void)
{
	HW_CCM_CSCDR2.B.LCDIF_PIX_CLK_SEL = 0x01;
	HW_CCM_CSCDR2.B.LCDIF_PIX_PRED = 2 - 1;
	HW_CCM_CSCMR1.B.LCDIF_PIX_PODF = (7 - 1) ^ 0x6;
	HW_CCM_CCGR3.B.CG4 = 0x3;
	HW_CCM_CCGR3.B.CG3 = 0x3;
}