/* Converts encoded control register address into a full address On error, the return value (parent_div) will be 0.  */
static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, u32 *field_val)
/* Converts encoded control register address into a full address On error, the return value (parent_div) will be 0.  */
static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, u32 *field_val)
{
	const struct clksel *clks;
	const struct clksel_rate *clkr;
	clks = omap2_get_clksel_by_parent(clk, src_clk);
	if (!clks)
		return 0;
	for (clkr = clks->rates; clkr->div; clkr++) {
		if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
			break;
	}
	if (!clkr->div) {
		printk(KERN_ERR "clock: Could not find default rate for "
		       "clock %s parent %s\n", clk->name,
		       src_clk->parent->name);
		return 0;
	}
	WARN_ON(clk->clksel_mask == 0);
	*field_val = clkr->val;
	return clkr->div;
}