/* Maximum drive strength is 24mA. This value can be lowered using DRVCTRLx registers, some pins have 8 steps (3 bits size encoded) some have 4 steps (2 bits size encoded).  */
static int pfc_rcar_set_drive_strength(uintptr_t pfc_base, uint16_t pin, uint8_t strength)
/* Maximum drive strength is 24mA. This value can be lowered using DRVCTRLx registers, some pins have 8 steps (3 bits size encoded) some have 4 steps (2 bits size encoded).  */
static int pfc_rcar_set_drive_strength(uintptr_t pfc_base, uint16_t pin, uint8_t strength)
{
	uint8_t offset, size, step;
	uint32_t reg, val;
	reg = pfc_rcar_get_drive_reg(pin, &offset, &size);
	if (reg == 0U) {
		return -EINVAL;
	}
	step = PFC_RCAR_DRIVE_STEP(size);
	if ((strength < step) || (strength > PFC_RCAR_DRIVE_MAX)) {
		return -EINVAL;
	}
	strength = (strength / step) - 1U;
	val = sys_read32(pfc_base + reg);
	val &= ~GENMASK(offset + size - 1U, offset);
	val |= strength << offset;
	pfc_rcar_write(pfc_base, reg, val);
	return 0;
}