/* Return: a positive integer DIVQ value to be programmed into the hardware upon success, or 0 upon error (since 0 is an invalid DIVQ value)  */
static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
/* Return: a positive integer DIVQ value to be programmed into the hardware upon success, or 0 upon error (since 0 is an invalid DIVQ value)  */
static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
{
	u64 s;
	u8 divq = 0;
	if (!vco_rate) {
		WARN_ON(1);
		goto wcd_out;
	}
	s = div_u64(MAX_VCO_FREQ, target_rate);
	if (s <= 1) {
		divq = 1;
		*vco_rate = MAX_VCO_FREQ;
	} else if (s > MAX_DIVQ_DIVISOR) {
		divq = ilog2(MAX_DIVQ_DIVISOR);
		*vco_rate = MIN_VCO_FREQ;
	} else {
		divq = ilog2(s);
		*vco_rate = (u64)target_rate << divq;
	}
wcd_out:
	return divq;
}