/* Given desired divider ratio, return the value that needs to be set in Clock and AC Timing Control register  */
static u32 get_clk_reg_val(ulong divider_ratio)
/* Given desired divider ratio, return the value that needs to be set in Clock and AC Timing Control register  */
static u32 get_clk_reg_val(ulong divider_ratio)
{
	ulong inc = 0, div;
	ulong scl_low, scl_high, data;
	for (div = 0; divider_ratio >= 16; div++) {
		inc |= (divider_ratio & 1);
		divider_ratio >>= 1;
	}
	divider_ratio += inc;
	scl_low = (divider_ratio >> 1) - 1;
	scl_high = divider_ratio - scl_low - 2;
	data = I2CD_CACTC_BASE
			| (scl_high << I2CD_TCKHIGH_SHIFT)
			| (scl_low << I2CD_TCKLOW_SHIFT)
			| (div << I2CD_BASE_DIV_SHIFT);
	return data;
}