/* Set the fields of structure stc_ctc_ct_init_t to default values.  */
int32_t CTC_CT_StructInit(stc_ctc_ct_init_t *pstcCtcInit)
/* Set the fields of structure stc_ctc_ct_init_t to default values.  */
int32_t CTC_CT_StructInit(stc_ctc_ct_init_t *pstcCtcInit)
{
    int32_t i32Ret = LL_ERR_INVD_PARAM;
    if (NULL != pstcCtcInit) {
        pstcCtcInit->u32RefClockFreq = 0UL;
        pstcCtcInit->u32RefClockSrc = CTC_REF_CLK_SRC_CTCREF;
        pstcCtcInit->u32RefClockDiv = CTC_REF_CLK_DIV8;
        pstcCtcInit->f32TolerantErrRate = 0.0F;
        pstcCtcInit->u8TrimValue = 0U;
        i32Ret = LL_OK;
    }
    return i32Ret;
}