/* This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers. The sequencer must be disabled before writing to these regsiters. */
int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
/* This function sets the number of Acquisition cycles in the ADC Channel Acquisition Time Sequencer Registers. The sequencer must be disabled before writing to these regsiters. */
int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
{
	Xil_AssertNonvoid(InstancePtr != NULL);
	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
			XADCPS_SEQ_MODE_SAFE)) {
		return XST_FAILURE;
	}
	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ06_OFFSET,
				(AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
	XAdcPs_WriteInternalReg(InstancePtr,
				XADCPS_SEQ07_OFFSET,
				(AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
				XADCPS_SEQ07_CH_VALID_MASK);
	return XST_SUCCESS;
}