/* This function set HCLK clock source and HCLK clock divider.  */
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
/* This function set HCLK clock source and HCLK clock divider.  */
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
{
    uint32_t u32HIRCSTB;
    u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
    CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
    CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
    CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
    CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
    SystemCoreClockUpdate();
    if (u32HIRCSTB == 0UL) {
        CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
    }
}