/* Timestamp register resolution setting. Configuration of this bit affects TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h), TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h), STEP_TIMESTAMP_H(4Ah) and STEP_COUNT_DELTA(15h) registers..  */
int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t *val)
/* Timestamp register resolution setting. Configuration of this bit affects TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h), TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h), STEP_TIMESTAMP_H(4Ah) and STEP_COUNT_DELTA(15h) registers..  */
int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t *val)
{
  lsm6dsl_wake_up_dur_t wake_up_dur;
  int32_t ret;
  ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1);
  switch (wake_up_dur.timer_hr) {
    case LSM6DSL_LSB_6ms4:
      *val = LSM6DSL_LSB_6ms4;
      break;
    case LSM6DSL_LSB_25us:
      *val = LSM6DSL_LSB_25us;
      break;
    default:
      *val = LSM6DSL_TS_RES_ND;
      break;
  }
  return ret;
}