/* Perform lazy FPU context switching by simply granting or denying access to FP regs based on FPU ownership before leaving the last exception level in case of exceptions, or during a thread context switch with the exception level of the new thread being 0. If current thread doesn't own the FP regs then it will trap on its first access and then the actual FPU context switching will occur.  */
static void fpu_access_update(unsigned int exc_update_level)
/* Perform lazy FPU context switching by simply granting or denying access to FP regs based on FPU ownership before leaving the last exception level in case of exceptions, or during a thread context switch with the exception level of the new thread being 0. If current thread doesn't own the FP regs then it will trap on its first access and then the actual FPU context switching will occur.  */
static void fpu_access_update(unsigned int exc_update_level)
{
	__ASSERT(read_daif() & DAIF_IRQ_BIT, "must be called with IRQs disabled");
	uint64_t cpacr = read_cpacr_el1();
	if (arch_exception_depth() == exc_update_level) {
		if (atomic_ptr_get(&_current_cpu->arch.fpu_owner) == _current) {
			write_cpacr_el1(cpacr | CPACR_EL1_FPEN_NOTRAP);
		} else {
			write_cpacr_el1(cpacr & ~CPACR_EL1_FPEN_NOTRAP);
		}
	} else {
		write_cpacr_el1(cpacr & ~CPACR_EL1_FPEN_NOTRAP);
	}
	barrier_isync_fence_full();
}