/* As a side effect of the way this is implemented we're limited to interrupt handlers in the address range from KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...  */
void* set_except_vector(int n, void *addr)
/* As a side effect of the way this is implemented we're limited to interrupt handlers in the address range from KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...  */
void* set_except_vector(int n, void *addr)
{
	unsigned long handler = (unsigned long) addr;
	unsigned long old_handler = exception_handlers[n];
	exception_handlers[n] = handler;
	if (n == 0 && cpu_has_divec) {
		*(u32 *)(ebase + 0x200) = 0x08000000 |
					  (0x03ffffff & (handler >> 2));
		local_flush_icache_range(ebase + 0x200, ebase + 0x204);
	}
	return (void *)old_handler;
}