/* Prepare a DMA transfer. We build the DMA table, adjust the timings for a read on KeyLargo ATA/66 and mark us as waiting for DMA completion  */
static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
/* Prepare a DMA transfer. We build the DMA table, adjust the timings for a read on KeyLargo ATA/66 and mark us as waiting for DMA completion  */
static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
{
	ide_hwif_t *hwif = drive->hwif;
	pmac_ide_hwif_t *pmif =
		(pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
	u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4);
	u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
	if (pmac_ide_build_dmatable(drive, cmd) == 0)
		return 1;
	if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
		writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL),
			PMAC_IDE_REG(IDE_TIMING_CONFIG));
		(void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
	}
	return 0;
}