/* ALE bit 4 autcpu12_pedr CLE bit 5 autcpu12_pedr NCE bit 0 fio_ctrl  */
static void autcpu12_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
/* ALE bit 4 autcpu12_pedr CLE bit 5 autcpu12_pedr NCE bit 0 fio_ctrl  */
static void autcpu12_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;
	if (ctrl & NAND_CTRL_CHANGE) {
		void __iomem *addr;
		unsigned char bits;
		addr = CS89712_VIRT_BASE + AUTCPU12_SMC_PORT_OFFSET;
		bits = (ctrl & NAND_CLE) << 4;
		bits |= (ctrl & NAND_ALE) << 2;
		writeb((readb(addr) & ~0x30) | bits, addr);
		addr = autcpu12_fio_base + AUTCPU12_SMC_SELECT_OFFSET;
		writeb((readb(addr) & ~0x1) | (ctrl & NAND_NCE), addr);
	}
	if (cmd != NAND_CMD_NONE)
		writeb(cmd, chip->IO_ADDR_W);
}