/* Legacy PDC guarantees to set: Map Memory BAR's into PA IO space. Map Expansion ROM BAR into one common PA IO space per bus. Map IO BAR's into PCI IO space. Command (see below) Cache Line Size Latency Timer Interrupt Line PPB: secondary latency timer, io/mmio base/limit, bus numbers, bridge control  */
void pcibios_set_master(struct pci_dev *dev)
/* Legacy PDC guarantees to set: Map Memory BAR's into PA IO space. Map Expansion ROM BAR into one common PA IO space per bus. Map IO BAR's into PCI IO space. Command (see below) Cache Line Size Latency Timer Interrupt Line PPB: secondary latency timer, io/mmio base/limit, bus numbers, bridge control  */
void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat >= 16) return;
	pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
			      (0x80 << 8) | pci_cache_line_size);
}