/* deinitialize DMA a channel registers 
, V1.0.0, firmware for GD32F1x0(x=3,5) , V2.0.0, firmware for GD32F1x0(x=3,5,7,9) , V3.0.0, firmware update for GD32F1x0(x=3,5,7,9) */
void dma_deinit(dma_channel_enum channelx)
/* deinitialize DMA a channel registers 
, V1.0.0, firmware for GD32F1x0(x=3,5) , V2.0.0, firmware for GD32F1x0(x=3,5,7,9) , V3.0.0, firmware update for GD32F1x0(x=3,5,7,9) */
void dma_deinit(dma_channel_enum channelx)
{
    DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN;
    DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE;
    DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE;
    DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE;
    DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE;
    DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx);
}