/* Returns: 0 upon success or -ERANGE if the reference clock rate is out of range.  */
static int __wrpll_update_parent_rate(struct wrpll_cfg *c, unsigned long parent_rate)
/* Returns: 0 upon success or -ERANGE if the reference clock rate is out of range.  */
static int __wrpll_update_parent_rate(struct wrpll_cfg *c, unsigned long parent_rate)
{
	u8 max_r_for_parent;
	if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
		return -ERANGE;
	c->parent_rate = parent_rate;
	max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
	c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
	c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
	return 0;
}