/* Switch the DPLL clock on the HPT3xxN devices. This is a right mess.  */
static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
/* Switch the DPLL clock on the HPT3xxN devices. This is a right mess.  */
static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
{
	unsigned long base = hwif->extra_base;
	u8 scr2 = inb(base + 0x6b);
	if ((scr2 & 0x7f) == mode)
		return;
	outb(0x80, base + 0x63);
	outb(0x80, base + 0x67);
	outb(mode, base + 0x6b);
	outb(0xc0, base + 0x69);
	outb(inb(base + 0x60) | 0x32, base + 0x60);
	outb(inb(base + 0x64) | 0x32, base + 0x64);
	outb(0x00, base + 0x69);
	outb(0x00, base + 0x63);
	outb(0x00, base + 0x67);
}