/* Adjust peripheral PLL to use the given divider and source. */
static int adjust_periph_pll(enum periph_id periph_id, int source, int mux_bits, unsigned divider)
/* Adjust peripheral PLL to use the given divider and source. */
static int adjust_periph_pll(enum periph_id periph_id, int source, int mux_bits, unsigned divider)
{
	u32 *reg = get_periph_source_reg(periph_id);
	clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
			divider << OUT_CLK_DIVISOR_SHIFT);
	udelay(1);
	if (source < 0)
		return -1;
	clock_ll_set_source_bits(periph_id, mux_bits, source);
	udelay(2);
	return 0;
}