/* This enet related pin-muxing and GPIO handling is done in SPL U-Boot. For early initialization. And to give the PHY some time to come out of reset before the U-Boot ethernet driver tries to access its registers via MDIO.  */
int platinum_setup_enet(void)
/* This enet related pin-muxing and GPIO handling is done in SPL U-Boot. For early initialization. And to give the PHY some time to come out of reset before the U-Boot ethernet driver tries to access its registers via MDIO.  */
int platinum_setup_enet(void)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
	unsigned phy_reset = IMX_GPIO_NR(1, 19);
	imx_iomux_v3_setup_pad(phy_reset_pad);
	gpio_direction_output(phy_reset, 0);
	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
	mdelay(10);
	gpio_set_value(phy_reset, 1);
	udelay(100);
	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
	return enable_fec_anatop_clock(0, ENET_50MHZ);
}