/* Set the dividers for the PLLI2S clock outputs  */
void rcc_plli2s_config(uint16_t n, uint8_t r)
/* Set the dividers for the PLLI2S clock outputs  */
void rcc_plli2s_config(uint16_t n, uint8_t r)
{
	RCC_PLLI2SCFGR = (
	  ((n & RCC_PLLI2SCFGR_PLLI2SN_MASK) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) |
	  ((r & RCC_PLLI2SCFGR_PLLI2SR_MASK) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT));
}