/* Load SERCOM registers to init for SPI master mode The settings will be applied with default master mode, unsupported things are ignored.  */
static void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs)
/* Load SERCOM registers to init for SPI master mode The settings will be applied with default master mode, unsupported things are ignored.  */
static void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs)
{
	ASSERT(hw && regs);
	hri_sercomspi_write_CTRLA_reg(
	    hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
	hri_sercomspi_write_CTRLB_reg(
	    hw,
	    (regs->ctrlb
	     & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN))
	        | (SERCOM_SPI_CTRLB_RXEN));
	hri_sercomspi_write_BAUD_reg(hw, regs->baud);
	hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
}