/* Although this is an FIQ handler, the FIQ is processed in monitor mode, which means there's no FIQ banked registers. This is the same as IRQ mode, so use the IRQ attribute to ask the compiler to handler entry and return.  */
void __secure __irq psci_fiq_enter(void)
/* Although this is an FIQ handler, the FIQ is processed in monitor mode, which means there's no FIQ banked registers. This is the same as IRQ mode, so use the IRQ attribute to ask the compiler to handler entry and return.  */
void __secure __irq psci_fiq_enter(void)
{
	u32 scr, reg, cpu;
	scr = cp15_read_scr();
	cp15_write_scr(scr & ~BIT(0));
	reg = readl(GICC_BASE + GICC_IAR);
	if (reg == 1023 || reg == 1022)
		goto out;
	writel(reg, GICC_BASE + GICC_EOIR);
	dsb();
	cpu = (reg >> 10) & 0x7;
	sunxi_cpu_power_off(cpu);
out:
	cp15_write_scr(scr);
}