/* On SN2, we wait for the PIO_WRITE_STATUS SHub register to clear. See PV 871084 for details about the WAR about zero value.  */
void __sn_mmiowb(void)
/* On SN2, we wait for the PIO_WRITE_STATUS SHub register to clear. See PV 871084 for details about the WAR about zero value.  */
void __sn_mmiowb(void)
{
	volatile unsigned long *adr = pda->pio_write_status_addr;
	unsigned long val = pda->pio_write_status_val;
	while ((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != val)
		cpu_relax();
}