/* Get the rate of the M-PLL clock from input clock frequency and the value of the M-PLL Parameter Register.  */
static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
/* Get the rate of the M-PLL clock from input clock frequency and the value of the M-PLL Parameter Register.  */
static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
{
	const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
	const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
			>> SCU_MPLL_DENUM_SHIFT;
	const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
			>> SCU_MPLL_POST_SHIFT;
	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}