/* HFXO output 48Mhz and core running at 48Mhz  */
void cmu_clock_setup_in_hfxo_out_48mhz(void)
/* HFXO output 48Mhz and core running at 48Mhz  */
void cmu_clock_setup_in_hfxo_out_48mhz(void)
{
	CMU_HFCORECLKDIV = CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV
			   | CMU_HFCORECLKDIV_HFCORECLKLEDIV;
	CMU_CTRL = (CMU_CTRL
		    & ~(CMU_CTRL_HFCLKDIV_MASK | CMU_CTRL_HFXOBUFCUR_MASK))
		    | (CMU_CTRL_HFCLKDIV_NODIV
		       | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ);
	cmu_osc_on(HFXO);
	cmu_wait_for_osc_ready(HFXO);
	MSC_READCTRL = (MSC_READCTRL & ~MSC_READCTRL_MODE_MASK)
			| MSC_READCTRL_MODE_WS2;
	cmu_set_hfclk_source(HFXO);
	while (cmu_get_hfclk_source() != HFXO);
}