Cache coherence
Suppose there are two processors, P1 and P2, and P1 wrote a value X1, and afterwards, P2 wrote a value X2, if P1 reads the value, it must get the value written by P2, X2, and not the value it wrote, X1, if there are no other writes between the two. This means that the view of memory is coherent. If processors can read the same old value after the write made by P2, the memory would not be coherent.