Stanford builds first complex computer chip out of carbon nanotubes
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Researchers at Stanford University have become the first group to publicly demonstrate a computer chip fashioned entirely out of carbon nanotube transistors.
When silicon finally reaches the end of the road — when transistor features become so small that there aren’t enough silicon atoms to actually act like silicon — carbon nanotubes, along with silicon-germanium (SiGe) and gallium arsenide (GaAs), are the most likely candidates to take over. Carbon nanotubes (CNTs) are fantastically conductive, very small (just a few nanometers across), and are capable of switching at very high speeds. Unlike graphene, which also has very desirable electrical properties, it is much easier to create CNTs that are semiconducting. It is for this reason that CNTs, rather than graphene, are generally considered a more appropriate material for replacing silicon — at least in the short term. (See: IBM creates 9nm carbon nanotube transistor that outperforms silicon.)
Up until now, the barrier that has prevented research groups (such as IBM) from building chips out of carbon nanotubes is that it has proven very hard to produce purified, semiconducting CNTs. Depending on minute variations in CNT construction, they can be either metallic or semiconducting — and we haven’t yet discovered a large-scale method of producing (or isolating) 100%-semiconducting CNTs. Researchers only want the semiconducting variety, because the introduction of just a few metallic CNTs can cause a transistor to misbehave or burn out. CNTs also have a tendency to tangle up, again causing unpredictable electrical behavior.
Rather than trying to produce pure semiconducting CNTs, though, or finding a way to force CNTs to line up neatly, the Stanford researchers took the easy route: They built a chip that can tolerate all of the errors produced by imperfect CNTs. Unfortunately we don’t have the details on how they made their chips fault-tolerant, but it’s most likely a matter of redundant transistors and pathways, and making each feature larger and more rugged than normal. The chip, incidentally, which is an analog-to-digital converter, consists of 44 CNT transistors, seemingly fashioned on a silicon wafer (pictured right), and was demonstrated at the International Solid-State Circuits Conference in San Francisco.
As you can probably imagine, current silicon chips with billions of transistors have a fault tolerance of almost zero. With a minimum feature size of 20nm, you are talking about tiny slivers of silicon or high-k metals that are just a few dozen atoms thick; get more than a few atoms out of place, and you’ve just lost a few hundred dollars. Moving forward, as feature sizes creep towards 5nm or less, and there simply won’t be a fault tolerance — nothing less than perfect will do.
As Stanford shows with its CNT chip, though, there is an alternative: Chip designs that intrinsically account for fault tolerance. “Variation and imperfection are going to be the air we breathe in semiconductor technology,” Philip Wong, a Stanford engineer who worked on the CNT chip, tells Technology Review. “Error-tolerant design has to be part of the way forward, because we will never get the materials completely perfect.” For a company like Intel, which has spent hundreds of billions of dollars on building the most exacting and intricate processes ever devised by humans, such an idea may not go down very well.