text: 1. Field
  This invention pertains to the field of memory systems, and more particularly, to the field of memory systems employing error correction decoding.
  2. Description
  In some flash memory systems, a multi-channel error correction coder (ECC) architecture is employed with buffer memories for encoding/decoding the data from the host system to and from the flash memory.
  FIG. 1 shows a block diagram of such a flash memory system 10. Flash memory system 10 includes a flash memory controller 100 and a memory block 200. Memory controller 100 includes a host interface 190, a user data buffer 120, a system data buffer 130, a NAND interface 140, and a central processing unit 150, all connected together by a system bus 160. NAND interface 140 includes a direct memory access (DMA) controller 144 and an error correction coder (ECC) block 145. ECC block 145 includes a plurality (N) of ECC modules, including ECC modules 141, 142 and 143. Memory block 200 includes a plurality (N) of NAND memory devices, including memory devices 211, 212 and 213. Connected between each of the ECC modules 141, 142 and 143 and a corresponding one of the memory devices 211, 212 and 213 is a channel 0, 1, N, etc. Another embodiment of NAND interface 140 may include a plurality (M) of direct memory access (DMA) controller 144. Here, M is integer greater than 1. M may be same as N or not.
  FIG. 2 illustrates in greater detail interconnections between ECC block 145 and memory devices 211, 212 and 213 in flash memory system 10. As seen in FIG. 2, ECC module 141 includes encoder 161, and decoder block 165, which further comprises detector 162 and corrector 163. Likewise, ECC module 142 includes encoder 171, and decoder block 175, which further comprises detector 172 and corrector 173; and ECC module 143 includes encoder 181, and decoder block 185, which further comprises detector 182 and corrector 183.
  In operation, data from a host device (e.g., a processor) destined to be stored in a memory device 211, for example, is sent by DMA controller 144 to ECC module 141. In ECC module 141, the data is first encoded by the encoder 161 and then transmitted to memory device 211 via channel 0. When data is to be read from memory device 211 and provided to a host device, it is first decoded by decoder 165 and then the decoded data is supplied to DMA controller 144. In decoder 165, detector 162 detects whether any errors are present in the data received from memory device 211, and if there are any errors, then corrector 163 corrects the errors.
  There is a trend for flash memory systems to have more and more memory devices. There is also a trend for flash memory systems to employ multi-level cell (MLC) NAND memory devices for increased storage capacity. As a result, flash memory systems also require more and more ECC modules. However, adding more ECC modules enlarges the size of the integrated circuit, and increases the number of ECC IP core gates, for the flash memory controller. This increases the complexity and cost of the flash memory system.
  Accordingly, it would be desirable to provide a memory system that can provide robust error detection and correction with a more efficient utilization of area and circuitry in a memory controller. It would also be desirable to provide a method of processing data in a memory system that supports a more efficient utilization of area and circuitry in a memory controller.
  The present invention is directed to a memory system, and a method of processing data in a memory system.
  In one aspect of the inventive concept, a memory system comprises: at least two memory devices; and a memory controller having at least first and second communication channels each for communicating data with at least one of the memory devices. The memory controller comprises: at least first and second error detectors corresponding to the first and second communication channels and each adapted to detect errors in data sets received via the corresponding communication channel from at least one of the memory devices; and an error corrector adapted to correct errors detected by each of the at least first and second error detectors.
  In another aspect of the inventive concept, a memory system comprises: a memory controller having a first input port for communication with a first memory device via a first communication channel, a second input port for communication with a second memory device via a second communication channel, and an error decoder that is multiplexed for decoding data received from both the first and the second communication channels.
  In yet another aspect of the inventive concept, a method of processing data received from at least two memory devices via at least two corresponding communication channels, comprises: detecting errors in a first data set received via a first communication channel while detecting errors in a second data set received via a second communication channel; and correcting the detected errors in the first data set and then subsequently correcting errors in the second data set.
  In still another aspect of the inventive concept, an error decoder comprises: at least first and second error detectors corresponding to first and second communication channels and each adapted to detect errors in data sets received via the corresponding communication channel from at least one of memory devices; and an error corrector adapted to correct errors detected by each of the at least first and second error detectors