text: 1. Field of the Invention
  The present invention relates generally to a substrate for a semiconductor device, a manufacturing method thereof, a semiconductor device, and a frame main body. More particularly, it relates to the substrate for a semiconductor device and the like wherein an insulating substrate body for mounting the semiconductor device has a cut-away portion cut away from a side surface thereof and the wiring for surface treatment extends on the insulating substrate body with an end thereof gathering in a portion of a side surface of the insulating substrate body, the portion being opposed to the cut-away portion, thereby preventing the wiring for surface treatment from extending through the side surface of the insulating substrate body, so that even when the substrate gets static electricity during the transfer thereof, the semiconductor chip can avoid electrostatic damage.
  2. Description of Related Art
  In recent years, there have been demands for higher speed and downsizing of semiconductor devices. As semiconductor devices capable of meeting the higher speed and downsizing requirements, Land Grid Array (LGA), Ball Grid Array (BGA), and the like are known.
  Out of these, the LGA is configured as shown in FIGS. 1 and 2. FIG. 1 is a sectional side elevation of the semiconductor device 1, and FIG. 2 shows a segment of a lead frame 10, which is a substrate for a semiconductor device used in the semiconductor device 1 as shown in FIG. 1.
  The lead frame 10 comprises a lead frame body 12, which is an insulating substrate body. A die pad 12a disposed on a top surface of the lead frame body 12 mounts a semiconductor chip 14, which is included in the semiconductor device 1. Around the die pad portion 12a, a plurality of bonding electrodes (lands) 16 is deposited and formed so as to surround it as shown in FIG. 2. Electrodes of the semiconductor chip 14 connect the bonding electrodes 16 with gold wires 18 as shown in FIG. 1. The top surface side of the lead frame body 12 is molded (sealed) by a resin 20 so that the semiconductor chip 14, the gold wires 18, and the bonding electrodes 16 are respectively covered thereby.
  On the bottom surface of the lead frame body 12, external electrodes 22 for allowing the lead frame 10 to be mounted are deposited and formed. Each of the external electrodes 22 is electrically connected to the bonding electrode 16. As is well known, the electrical conduction between the bonding electrodes 16 and the external electrodes 22 is accomplished by through holes, or the like.
  Each of the surfaces of the bonding electrodes 16 and the external electrodes 22 is subjected to surface treatment for satisfactorily ensuring bonding with the semiconductor chip 14 and joint with soldering paste applied onto a substrate for mounting.
  The surface treatment is generally plating treatment. The plating treatment is carried out in the following manner. First, for example, the surface is subjected to a nickel-plating treatment for the undercoat and then subjected to a gold-plating treatment. As is well known, an electroplating process is often used as the process for performing the plating treatment. As shown in FIGS. 1 and 2, both the bonding electrodes 16 and the external electrodes 22 have wiring for plating treatment (wiring 24 for surface treatment), respectively. The wiring 24 for surface treatment passes a current to carry out the electroplating process.
  FIG. 3 shows a frame main body 30 prior to cutting it into the lead frames 10 for use for semiconductor chips. The frame main body 30 is an insulating substrate having a size capable of providing several lead frames 10. All the wiring 24 for surface treatment extend on the frame main body 30 with the ends thereof being led through the opposite side surfaces 31a and 31b. Solder resist layer generally insulates the upper and lower opposite surfaces of the lead frame body 12 except for an area including the bonding electrodes 16. Namely, an area 32 and the die pad 12a which mounts the semiconductor chip 14, are insulated in a case shown in FIG. 2.
  Herein, the cut ends of the wiring 24 for surface treatment are exposed from the side surfaces 31a and 31b of the frame main body 30. This is apparent from the configuration of FIG. 4.
  As shown in FIG. 4, an original plate 40 for providing the lead frame main bodies 30 is an insulating substrate having a size capable of forming therein a plurality of frame main bodies 30. The original plate 40 has secondary lines 26, which are the lines obtained by extending the wiring 24 for surface treatment, from the opposite side surfaces (the portions which will be the side surfaces 31a, 31b after cutting) of each of the frame main bodies 30. A large number of these secondary lines 26 are all connected to buses La and Lb wired at upper and lower sections, respectively, of the frame main body 30.
  Then, the wiring 24 for surface treatment, the secondary lines 26, and a pair of the buses La and Lb of the frame main body 30 are patterned so that the buses La and Lb are led through openings 42, 42 provided on the left and right side faces 41a and 41b of the original plate 40. Further, connection terminals (electrode terminals) 43, 43 for the buses La and Lb are deposited and formed on a portion of the original plate 40 opposed the opening 42. The connection terminals 43, 43 are the electrodes to be used for the plating treatment.
  Then, applying a prescribed voltage to the buses La and Lb while immersing the original plate 40 in a prescribed plating bath allows the bonding electrodes 16 and the external electrodes 22 to be subjected to the plating treatment. After the plating treatment, the original plate 40 is cut along the dot-dash lines shown in FIG. 4 to obtain a plurality of the frame main bodies 30 shown in FIG. 3. Therefore, when the original plate 40 is divided into the frame main bodies 30, the wiring 24 for surface treatment and their respective secondary lines 26 are separated from each other. The wiring 24 for surface treatment leads through the opposite side surfaces 31a and 31b of the frame main body 30. As the result thereof, the respective cut ends of the wiring 24 for surface treatment are exposed from the opposite side surfaces 31a and 31b of the frame main body 30.
  Incidentally, after completion of the division into frame main bodies 30 as shown in FIG. 3, generally, no frame main body 30 is cut into lead frames (segments) each having a size corresponding to each semiconductor chip. Thus, the fixing of the semiconductor chip 14, the wire bonding, and the mold treatment by a resin are performed on the frame main body 30. The frame main body 30 is transferred to respective processing steps, or subjected to a chucking process while remaining the same size as the frame main body 30.
  During the transfer process and the chucking process, a transfer unit and a chucking unit often come into contact with the insulating substrate body, which is the lead-frame body 12. Accordingly, when the lead frame body 12 is rubbed, a surface of the lead frame body 12 may be electrostatically charged. If the surface of the lead frame body 12 is electrostatically charged, discharge occurs when the surface of the lead frame body 12 moves closer to a metallic portion of the transfer unit or the chucking unit. Discharge current at this step flows in the semiconductor chip 14 via the wiring 24 for surface treatment. Alternatively, discharge occurs between the metallic portion of the transfer unit or the chucking unit and the wiring 24 for surface treatment. In this case, discharge current flows into the semiconductor chip 14. By such a repetition of charging and discharging, the semiconductor chip may be damaged by static electricity.
  As the semiconductor devices having a high possibility of being damaged by static electricity, mention may be made of higher density-, and downsizing-oriented LGA, BGA, and the like. As described above, with the semiconductor device having a higher speed of processing and a higher density, the reduction in size of a single semiconductor element and the reduction in thickness of an oxide film with miniaturization in wafer processing are remarkable. Therefore, such a semiconductor device is susceptible to static electricity. As a result, the semiconductor element in the semiconductor device has a high possibility of undergoing electrostatic damage (ESD damage) also due to slight charging and discharging.
  One object of the present invention is to improve the capacity for effective protection against electrostatic damage of the substrate for a semiconductor device, the semiconductor device, and the like.
  Another object of the invention is to provide a substrate for a semiconductor device, a semiconductor device, and the like, which are capable of effectively preventing electrostatic damage by achieving an electrically disconnected state.
  A further object of the invention is to provide a manufacturing method for manufacturing the substrate for a semiconductor device, which is capable of effectively preventing electrostatic damage to a semiconductor device.