text: 1. Field of the Invention
  The present invention relates to dynamic random access memories (DRAMs), and more particularly to a dynamic random access memory with an improved layout in which essential elements may be efficiently arranged in a limited area so as to be suitable for a DRAM device of a mega-bit grade or greater, and also to a method of arranging memory cells in such a memory device.
  2. Description of the Prior Art
  As is well-known, the degree of integration in DRAMs generally has quadrupled every three years, and this tendency appears to be continuing. Although the memory capacity increases by a factor of four, the chip size typically increases by only about a factor of two as a result of highly sophisticated processing technology.
  The capacitance of the capacitor serving as the location for storing information in a memory cell (in the form of millions of electrons), however, typically cannot be reduced with each subsequent generation due to the operational characteristics of DRAM circuits. Most of the currently available commercial products typically are designed to have a capacitance of about 20 femto Farads or more per cell. In order to reduce the area per cell and yet maintain the capacitance of the capacitors, most commercial DRAMs having four mega-bits or greater data storage use three-dimensional capacitors.
  A conventional method of making a CMOS DRAM of four or sixteen mega-bits data storage capacity employing stacked capacitors will now be described with reference to FIG. 1.
  In accordance with this conventional method, on silicon substrate 1-1 is first formed well 1-2 of a predetermined conductivity type (in a CMOS type device, P and N type wells). Thereafter, active regions 1-3 and field regions 1-4 are formed on silicon substrate 1-1 by what is known as a LOCOS (local oxidation of silicon) method. Over active regions 1-3 on the entire surface of silicon substrate 1-1 gate oxide film 1-5 is formed to have a uniform thickness. Subsequently, a polysilicon layer functioning as word line 1-6 is formed on gate oxide film 1-5 through the use of well-known LPCVD (low pressure chemical vapor deposition) and anisotropic dry etching methods. Over the entire surface of silicon substrate 1-1 silicon oxide film 1-7 (or nitride or other suitable insulation film) is then formed by a CVD (chemical vapor deposition) method. First contact holes are formed in insulation film 1-7 above first impurity diffusion regions 1-8, which are located in active regions 1-3 of switching transistors that are present in every memory cell, and which will be electrically connected to stacked capacitors. Thereafter, as storage electrode 1-9, which is one of two electrodes of each stacked capacitor, and which will be connected to each corresponding impurity diffusion region 1-8, a polysilicon electrode is formed by using a well-known LPCVD method and an anisotropic dry etching method. As an insulation film for the stacked capacitors, oxide film 1-10 (which may be a nitride film, oxinitride film or a composite film thereof) is formed. As plate electrode 1-11, which is the other electrode of each stacked capacitor, a polysilicon electrode is formed by using a well-known LPCVD method and an anisotropic dry etching method. Another oxide film (or an nitride film or a composite film .thereof) also is formed as insulation film 1-12, by using a CVD method. Insulation film 1-12 functions to electrically insulate the stacked capacitors from bit lines or other metal wiring formed thereon. Second contact holes are formed on insulation film 1-12 above second impurity diffusion regions 1-13, which are located in active regions 1-3 of the switching transistors that are present in every memory cell, and which will be electrically connected to bit lines. As pad conductor layer 1-14 for bit lines, another polysilicon (or polycide) layer is formed over and in the second contact holes as shown. Pad layer 14 could have been formed before the deposition of insulation film 1-12. Thereafter, a polycide or metal film serving as bit lines 1-15 is formed using an LPCVD method and an anisotropic dry etching method.
  Although not shown, in the case of adding metal wiring to the structure formed as above-mentioned, additional oxide films (or nitride films or composite films thereof) are formed using a CVD method for insulating the metal wiring from the underlying structure. In this case, additional contact holes for selectively connecting bit lines, word lines, core circuits or peripheral circuits also are formed using an anisotropic dry-etching method. Thereafter, metal wiring for selectively connecting the memory capacitors with core circuits or peripheral circuits are formed by using a coating achieved by a sputtering or CVD method and then a dry etching method. At this time, in the case of using a double metal wiring, a subsequent process required for forming a double metal wiring is carried out. Thus, all processes are completed. Additional processes such as lithography, cleaning and other associated processes or the like for improving the accuracy and ease in performing the processes described above may be performed as well. As the trend of further decreasing the entire chip area is continued in an effort to improve productivity and reduce cost, the area per cell could be reduced even more in the case of 16-mega-bit DRAMs or 64-mega-bit DRAMs. As a result, it is impossible to obtain a sufficiently large capacitance of stacked capacitors by using the above-mentioned method. Of course, the capacitance may be increased by an increase in the surface area of the capacitor obtained by increasing the height of the three-dimensional capacitor. However, this method has found limited use because of process difficulties resulting therefrom.
  Accordingly, it is necessary to provide a method of making a stacked capacitor which is capable of increasing the surface area of the capacitor, without increasing the height.
  FIG. 2 is a layout diagram of a DRAM obtained by a method for increasing the capacitance of a stacked capacitor. This layout is disclosed in U.S. Pat. No. 4,970,564 (issued Nov. 13, 1990 to Hitachi, Ltd.).
  The method will now be described in conjunction with FIGS. 3(A) to 3(H) and FIG. 4.
  In accordance with this method, well 3-2 of a predetermined conductivity type (in CMOS devices, P type and N type wells) is first formed on silicon substrate 3-1, as shown in FIG. 3(A). Active regions 3-3 and field regions 3-4 are then formed on silicon substrate 3-1 by use of the improved LOCOS (local oxidation of silicon) method. Thereafter, gate oxide film 3-5 is formed over active regions 3-3. As shown in FIG. 3(B), a polysilicon layer functioning as word lines 3-6, and insulation film 3-7 for insulating adjacent layers from each other, are then formed on gate oxide film 3-5 by use of a well-known LPCVD method and a well-known anisotropic dry etching method. Over the entire surface of silicon substrate 3-1, a silicon oxide film (or nitride film or other insulation film) serving as insulation film 3-8 is then formed by use of a CVD method. Second contact holes are formed on insulation film 3-8 above second impurity diffusion regions 3-9, which are located in active regions of switching transistors that are present in every memory cell, and which will be electrically connected to bit lines, as shown in FIG. 3(C). Thereafter, a polysilicon (or polycide) wiring for providing bit lines 3-10, and insulation film 3-11 lying thereon are formed using an LPCVD method and a dry etching method, as shown in FIG. 3(D). Bit lines 3-10 are isolated from a layer which will be subsequently formed thereon, by using a conventional method of forming side wall oxide film 3-12, as shown in FIG. 3(E). Thereafter, another insulation film 3-13 is formed. On insulation film 3-13, first contact holes 3-19 are formed above first impurity diffusion regions 3-14, which are located in active regions 3-3 of the switching transistors that are present in every memory cell as shown in FIG. 3(F). Thereafter, as storage electrode 3-15, which is one of two electrodes of each stacked capacitor 3-21, and which is connected to each first impurity diffusion region 3-14, a polysilicon electrode is formed by using an LPCVD method and a dry etching method, as shown in FIG. 3(G). Insulation film 3-16 for stacked capacitors 3-21, which may be an oxide film (or a nitride film or a composite film thereof), is formed. As plate electrode 3-17 of each stacked capacitor 3-21, a polysilicon electrode is then formed by using an LPCVD method and a dry etching method, as shown in FIG. 3(H). Another oxide film 3-18 (or a nitride film or a composite film thereof) also is formed as an insulation film by using a CVD method. Oxide film 3-18 functions to electrically insulate stacked capacitors 3-21 from metal wiring, which will be formed thereon. The resulting structure is illustrated in FIG. 4.
  Although not shown, additional contact holes are then formed at proper positions. Also, metal wiring for connecting circuits is formed over stacked capacitors 3-21 by use of a sputtering or CVD method and then defined by use of an anisotropic dry etching method. At this time, in cases in which double metal wiring is used, a subsequent process required for forming such double metal wiring is carried out. Thus, all processes are completed.
  Other processes such as lithography, cleaning and other associated processes or the like for improving the accuracy and ease in performing the processes described above may be performed as well.
  The memory cell having the above-mentioned structure of a stacked capacitor is very advantageous in extending the area of the capacitor, in that the first electrode of each stacked capacitor may be formed even above each second contact hole connecting the bit line and the second diffusion region of the corresponding switching transistor, because the stacked capacitor is formed after the formation of the bit lines as well as the word lines. Accordingly, the memory cell having the improved structure of stacked capacitors may be advantageously used in 16-mega bit DRAMs or higher density DRAMs.
  With reference to FIG. 2, the memory cell will be described in further detail.
  Below storage electrode 3-15 of stacked capacitor 3-21, first contact hole 3-19 is disposed, which connects storage electrode 3-15 with first impurity diffusion region 3-14 of the switching transistor. On the other hand, second contact hole 3-20 connecting bit line 3-10 with second impurity diffusion region 3-9 of the switching transistor is located at the lower left side of rectangular region 3-22. Between first contact hole 3-19 and second contact hole 3-20, word line 3-6 which functions as the gate of the switching transistor is vertically disposed. In this case, word line 3-6 should be positioned away from both first and second contact holes 3-19 and 3-20 by a proper distance so as to prevent the occurrence of electric short-circuiting therebetween. It is required that word line 3-6 be properly bent so that it can be disposed within the limited rectangular region under the condition that the proper distance is maintained. On the other hand, bit line 3-10 used for the input and output of information stored in the memory cell is disposed perpendicular to word line 3-6. Accordingly, entire active region 3-3, wherein three regions of the switching transistor are formed, that is, first impurity diffusion region 3-14, channel forming region 3-23 and second impurity diffusion region 3-9, are obliquely arranged with respect to bit line 3-10 and word line 3-6. There is no need for the three regions in the active regions to be linearly positioned. Arrangements having a curved or bent shape may be possible in order to obtain a desired process margin.
  Common in all devices having a folded bit line structure, another word line 3-6 is disposed at the right side of first contact hole 3-19 within rectangular region 3-22 and in parallel to left word line 3-6, while maintaining a proper distance from first contact hole 3-19. Right word line 3-6 is not connected directly to the memory cell shown.
  The positions of word lines 3-6 should be determined such that they keep a proper distance from other word lines in adjacent memory cells to be disposed at the left and right sides of rectangular region 3-22. Also, they should be positioned to be accurately connected with word lines in adjacent memory cells to be disposed above and below rectangular region 3-22. On the other hand, an adjacent bit line connected to an adjacent memory cell above rectangular region 3-22 is disposed in parallel to bit line 3-10 in rectangular region 3-22. Both the former and latter bit lines should be positioned to maintain a proper distance from first contact hole 3-19.
  In considering the above-mentioned various arrangement conditions to obtain an optimum arrangement of the memory cell, it can be found that the arrangement of the memory cell shown in FIG. 2 encounters the following limitations.
  First, second contact hole 3-20 for bit line 3-10 does not have a sufficient size, since the gap between adjacent word lines at which second contact holes 3-20 are located is small. This may cause a limitation in performance or it may become a limitation in achieving a high yield.
  Second, since a self-aligning etching method using a word line side wall forming process is used, in case of forming second contact hole 3-20 for bit line 3-10, the separation between the subsequently formed bit line 3-10 and word line 3-6 is very small. As a result, the capacitance of bit line 3-10 becomes relatively large, thereby adversely affecting the operation of data sensing.
  Third, since channel forming region 3-23 of the switching transistor forms an angle of 45.degree. with respect to word line 3-6 (namely, the gate), it is difficult to determine the appropriate modeling of its characteristics. When the alignment of the gate and the active region is changed, the transistor characteristics may be affected.
  Considering these limitations, another memory cell arrangement according to the layout of FIG. 5 seems to have an advantage, in that the limitations pointed out are eliminated by this arrangement. The layout is disclosed in U.S. Pat. No. 5,014,103 (issued on May 7, 1991 to Fujitsu, Ltd.).
  Referring to FIG. 5, there is shown a layout in which four memory cells are arranged. In FIG. 5, reference character AR denotes active regions, reference character AR' denotes the bent portion of each active region AR, reference character WL denotes word lines, reference character BH denotes bit line contact holes, reference character BL denotes bit lines, reference character SH denotes storage electrode contact holes, reference character SE denotes storage electrodes, reference character Z' denotes the bent portion of each word line, reference character CBH denotes the center of each bit line contact hole, and reference character CSH denotes the center of each storage electrode contact hole.
  As shown in FIG. 5, bent portion AR' of each active region AR is located under the corresponding word line WL. Bent portion Z' of each word line WL which crosses bit lines BL is curved as shown. The imaginary line connecting center CBH of each bit line contact hole BH and center CSH of the corresponding storage electrode contact hole SH is perpendicular to curved portion Z' of each word line WL. All of the memory cell patterns can be formed by arranging repeatedly the layout shown in FIG. 5.
  In both cell arrangements shown in FIGS. 2 and 5, however, the centers of bit line contact holes 3-20 and BH should correspond to lower left corner points P1 of rectangular regions 3-22 and 5-1, respectively. This reason can be easily understood, considering the arrangement of memory cells at front, rear, left and right of a memory array.
  However, this technique also has a limitation in the efficient arrangement of memory cells as will hereinafter be described in conjunction with FIG. 6.