text: This invention relates to a fault simulator and a simulation method which are for use in simulating a logic circuit model.
  A conventional simulation has been proposed by M. A. Breuer and A. D. Friedman in "Diagnosis & Reliable Design of Digital Systems", pages 25-162 and pages 224-241, published by Computer Science Press, Inc. (Maryland) and is carried out by the use of software. When a logic circuit of a large scale is simulated by software in a manner mentioned by M. A. Breuer et al, a very long time is necessary because a simulation time for the simulation is proportional to a square of the scale of the logic circuit, as known in the art.
  In U.S. Pat. No. 4,725,975 issued to Tohru Sasaki, assignor to NEC Corporation, a logic simulator simulates a logic circuit model by dividing the model into logic blocks and classifying the blocks by levels according to flow of signals in the model. The simulations are successively carried out by logic operations of the blocks on each level.
  However, the simulation is carried out one by one by supplying a single kind of input logic values or signals to a single model. This means that the single kind of the input logic signals alone is given to simulate the single model. Accordingly, it takes an extremely long time to simulate the fault simulation operations of each model because a wide variety of faults take place at each model.