text: 1. FIELD OF THE INVENTION
  This invention relates to a semiconductor capacitance element and more particularly to a MIS capacitance element adapted for use in a complementary metal-insulator-semiconductor integrated circuit (MIS IC) for a wristwatch.
  2. DESCRIPTION OF THE PRIOR ART
  Conventionally, capacitive elements have been formed in the semiconductor integrated circuit utilizing (a) the MIS gate capacitance using directly the MIS structure which includes the metal-oxide-semiconductor (MOS) structure, (b) the junction capacitance using the diffused layer-substrate junction, and (c) the junction capacitance using the diffused layer-well region capacitance. An example of the MIS capacitance element is proposed by W. G. Pfann and C. G. B. Garrett in Proc. IRE 47, p 2011 (1959). A problem in the MIS capacitance element lies in the property of an insulator-semiconductor interface which tends to collect carriers of one polarity to form a channel region thereunder. A modification of the MIS capacitance element to be integrated into a semiconductor integrated circuit is proposed in Japanese Patent Publication No. 44-30537, in which a metal layer is evaporated on part of the oxide layer formed on a p-type silicon body, the structure is heat-treated at a temperature of 300.degree. C. to 500.degree. C. in a gas atmosphere including hydrogen or moisture and then the unnecessary oxide layer is removed from the silicon surface so as to allow an n-type inversion layer to be formed only in the silicon surface below the remaining oxide layer. In the above capacitances, the voltage is applied in the reverse bias direction and hence the width of the inversion layer or depletion layer formed at the semiconductor surface or the junction interface is varied depending on the applied voltage. Thus, the value of capacitance is also changed. Namely, the capacitance has a voltage or field dependency. For this reason, these capacitive elements cannot be used as stable capacitance elements.
  The present inventors have studied the possibilities of obtaining capacitive elements free of field-dependence in the semiconductor integrated circuits. In a complementary silicon gated IC device, the well region, the p.sup.+ -type (or n.sup.+ -type) diffused layer, the polycrystalline silicon layer and the aluminium layer can be used as the wiring layer. The present inventors have found that the capacitIve element of almost no field dependence can be formed by appropriately selecting one or two from the above-mentioned four wiring materials. Further, particular consideration is paid to the utilization of the gate oxide film from the point of capacitance per unit area.