text: The design methodology for complex integrated circuit (IC) designs has evolved with the advancement in process technologies. Currently, hardware description languages (HDL) are widely used to describe the behavior of a circuit at different levels of abstraction. The most commonly used approach is using HDL, such as Verilog or VHDL, to describe the circuit at register-transfer level (RTL). A computer-aided design (CAD) tool, generally called logic synthesizer, is then used to transform the above HDL design description into a technology dependent gate-level netlist, taking into account user-specified constraints on timing, power, area, etc.
  Integrated circuits need to be tested in order to verify the correctness of their functionality. With the ever-growing complexity of integrated circuits, the testing cost has become a significant portion of the total manufacturing cost. Hence, testability issues should be taken seriously in the design process. The reason that a design with better testability usually results in lower test generation and test application costs.
  There are many techniques to improve the testability of a design and reduce the costs for test generation and test application. These techniques are generally referred to as DFT (design-for-test) techniques. Among various DFT techniques, the scan-based DFT technique is the most widely used. In a scan-based design, scan storage elements, called scan cells, are used to replace original storage elements (flip-flops and latches). Some additional logic may also be added to the original design. As a result, the controllability and observability of the design will be greatly enhanced. In addition, test points, both control points and observation points, can be inserted into the original design to further improve its controllability and observability. The process of repairing scan-based DFT rule violations, inserting test points, replacing original storage elements with scan cells, and stitching the scan cells together as scan chains forms the basis of a scan synthesis CAD system.
  Prior-art scan synthesis solutions start with a technology-dependent gate-level netlist. This means that, even though a modern IC design is often coded at RTL, it must be first synthesized into a gate-level netlist in order to conduct scan synthesis. This Scan-after-Logic-Synthesis design flow is time-consuming, inefficient, and difficult to meet design constraints. In such a design flow, when an integrated circuit design contains any DFT rule violations, they must be repaired at gate-level. In addition, replacing an original storage element with a scan cell and adding test points are also conducted on the gate-level netlist. However, the logic added to fix DFT rule violations and to improve fault coverage may violate user-specified design constraints, be it power, timing, or area. Although designers may choose to rewrite RTL codes to fix such problems, it requires re-compilation and re-synthesis, which consumes a lot of time and effort. Moreover, it has to be repeated multiple times until all DFT rule violations are fixed. The product life cycle of a modern IC design is very short. Fixing DFT problems at such a late stage in a design flow may cause the product to miss the market window and incur huge revenue losses.
  An alternative prior-art approach, aimed at eliminating or reducing the number of iterations in a design flow, is to perform scan synthesis during logic synthesis. Logic synthesis generally contains two major steps: generic transformation and technology mapping (including logic optimization). Generic transformation is to synthesize RTL codes into a generic technology-independent gate-level model. Technology mapping is to map the generic gate-level model into a technology dependent gate-level netlist, based on user-specified constraints and a given cell library. Scan synthesis now can be performed between generic transformation and technology mapping. This Scan-within-Logic-Synthesis is also called one-pass scan synthesis or one-pass test synthesis. In principle, this approach still works at gate-level and solely relies on designers to fix most, if not all, DFT rule violations at RTL first. The main advantage of the Scan-within-Logic-Synthesis approach over the Scan-after-Logic-Synthesis approach is that it does not need to go through the lengthy technology mapping to locate DFT rule violations, if any. The disadvantage of the Scan-within-Logic-Synthesis approach, however, is that designers must guarantee their RTL codes to be testable before one-pass scan synthesis is performed.
  In order to solve the problem with the current Scan-within-Logic-Synthesis approach, three prior-art solutions are available: one for test point insertion in an unmapped gate-level netlist (prior-art solution #1), one for test point insertion at RTL (prior-art solution #2), and one for scan insertion at RTL (prior-art solution #3) as summarized bellow:
  Prior-art solution #1 is described in U.S. Pat. No. 6,311,317 by Khoche, et al. (2001). This solution adds test points to an unmapped gate-level netlist, removing the need of adding test points to a gate-level netlist obtained after logic synthesis. This solution, however, suffers from a major disadvantage. That is, this solution does not perform any analysis on an unmapped gate-level netlist to guide designers in choosing test points. As a result, user inputs should be provided to specify test points. This is not only time-consuming but also inefficient in some cases when less-effective test points are specified.
  Prior-art solution #2 is described in U.S. Pat. No. 6,301,688 by Roy, et al. (2001). This solution selects test points at RTL based on a cost function derived from the controllability and observability measures. A list of candidate test points is first constructed. For each test point candidate, the solution computes a cost function that models the average number of pseudorandom patterns required to detect a fault, over the complete fault set. The candidate test point, which results in the largest reduction in the cost function, is then selected. This test point selection process is repeated until the estimated fault coverage meets the user-specified requirement, or the number of selected test points exceeds the user-specified limit. The disadvantage of this solution is that it solely relies on a computed cost function to guide test point selection, which is not always accurate. As a result, this solution may yield a less-effective set of test points since no interactive test point selection is supported.
  Prior-art solution #3 is described in U.S. Pat. No. 6,256,770 by Pierce, et al. (2001). This solution performs scan insertion, including scan replacement and scan stitching, at RTL. This solution, however, suffers from several disadvantages: First, this solution does not take the concept of multiple clock domains into consideration. It basically assumes that all RTL modules will be implemented on a single clock domain. This is not a practical assumption since most modern IC designs consist of multiple clock domains, operating at a signal frequency or multiple frequencies. Second, this solution does not take the concept of hierarchical scan synthesis into consideration. Given the fact that modern IC designs are growing rapidly in size and complexity, any non-scalable solution without supporting hierarchical scan synthesis will be of only limited use. Third, this solution does not support scan repair, which is indispensable in preparing a design for scan synthesis. In fact, a complex RTL design may contain many scan DFT rule violations, such as asynchronous set/reset signals, generated clocks, constant clocks, clocks connected to data inputs of storage elements, gated clocks, latches, bi-directional ports, combinational feedback loops, pulse generators, tri-state busses, etc. Such violations must be fixed before scan insertion. Fourth, this solution does not support scan extraction, which is often needed to extract scan information from a scanned RTL design. Fifth, this solution does not support interactive scan debug and interactive scan repair, which are important when scan chains do not operate as intended.
  In order to solve the disadvantages of prior-art solution, the present invention employs a new approach called Scan-before-Logic-Synthesis to move scan synthesis completely to the register-transfer level (RTL). The present invention will perform scan synthesis completely before logic synthesis, based on testability analysis, clock domain analysis, and user constraints. This Scan-before-Logic-Synthesis approach will allow designers to find all DFT rule violations at RTL and fix them by hand or by software. The present invention performs scan insertion and test point insertion at RTL and generate testable RTL codes for synthesis and verification. With the present invention, designers can verify scanned codes at RTL. The verified RTL codes can then be synthesized using any commercially available logic synthesis tool, based on original design constraints. The present invention can avoid costly iterations caused by scan chain insertion, test point insertion, and DFT violation repair at gate-level. In one embodiment of the present invention, the CAD system supports hierarchical RTL scan synthesis by allowing designers to conduct RTL scan synthesis module-by-module, and then stitching the scanned RTL modules hierarchically up to the top-level module.
  Accordingly, what is needed in this present invention is a computer-aided design (CAD) system for effectively automating RTL scan synthesis or Scan-before-Logic-Synthesis, whose advantages are listed above. The CAD system can generate flush and random test benches to verify and debug scanned RTL codes. In addition, hierarchical test benches can also be generated to verify and debug the scanned RTL design at top-level.
  The following table summarizes the results of analyzing different synthesis approaches:
  SynthesisScan-FeatureScan-after-LogicScan-within-Logicbefore-LogicInput ModelGate-LevelRTLRTLOutput ModelGate-LevelGate-LevelRTLTiming ClosureDifficultMediumEasySynthesis TimeLongMediumShort