text: (1) Field of the Invention
  The present invention relates to a resin-encapsulated semiconductor device in which a semiconductor chip and a lead frame are encapsulated with a resin encapsulant. In particular, the present invention relates to a resin-encapsulated semiconductor device with the back face of a die pad exposed to radiate heat from a power semiconductor element.
  (2) Description of Related Art
  In recent years, in response to downsizing of electronic units, it has become increasingly necessary to assemble semiconductor components for those electronic units at a higher and higher density. Correspondingly, sizes and thicknesses of the semiconductor components, such as resin-encapsulated semiconductor devices, in which a semiconductor chip and a lead frame are encapsulated with a resin encapsulant, have also been noticeably reduced. Examples of resin-encapsulated semiconductor devices accomplishing these objects include a so-called “quad flat non-leaded (QFN)” package. From the QFN package, outer leads, which are usually provided to protrude laterally out of a package, are eliminated. Instead, external electrodes to be electrically connected to a motherboard are provided on the back face of the QFN package.
  A power semiconductor element produces a larger amount of heat than a normal semiconductor element. Therefore, when power semiconductor elements are built in a semiconductor chip, the resin-encapsulated semiconductor device should have its size or thickness reduced while its heat radiation properties are taken into account. Thus, a QFN package for a power semiconductor element (hereinafter, simply referred to as a “power QFN package”) has intentionally exposed the back face of a die pad, on which a semiconductor chip is mounted, not covered with a resin encapsulant. Hereinafter, the structure and fabrication method of a known power QFN package will be described.
  FIGS. 8A and 8B are perspective views of a known power QFN package when seen from above and below, respectively. FIG. 8C is a cross-sectional view taken along the line VIIIc-VIIIc of the known power QFN package in FIG. 8A.
  As illustrated in FIGS. 8A through 8C, the known QFN package includes a die pad 102, a semiconductor chip 104 mounted on the top face of the die pad 102 and formed with an electrode pad and power semiconductor elements, a plurality of signal leads 101 provided around the die pad 102, support leads 103 for supporting the die pad 102, thin metal wires 105 through which the signal leads 101 or the die pad 102 are connected to an electrode pad (not shown) placed on the semiconductor chip 104, and a resin encapsulant 106 with which the top face of the die pad 102, the thin metal wires 105, the support leads 103, and the top faces of the signal leads 101 are encapsulated. The signal leads 101, the die pad 102, and the support leads 103 form a lead frame.
  The semiconductor chip 104 is bonded, with an adhesive 107, onto the die pad 102 while its face on which power semiconductor elements are formed is oriented upward.
  The above-mentioned members are encapsulated with the resin encapsulant 106 such that the back face of the die pad 102 and the back faces of the signal leads 101 are exposed. Since the back face of the die pad 102 is exposed, this allows the die pad 102 to function as a heat-radiating plate. By bringing the die pad 102 into contact with a heat-radiating portion of a motherboard, heat emitted from a power semiconductor element consuming a lot of power is dissipated to outside, thereby suppressing a rise in temperature within the package. The respective lower parts of the signal leads 101 including the exposed surfaces thereof are used as external electrodes 109.
  According to a known power QFN package, the lower part of an outer edge portion of the die pad 102 is removed such that the outer edge portion thereof forms a thin part 102c. This allows the resin encapsulant 106 to reach under the thin part 102c. This can enhance the adhesion level between the die pad 102 and the resin encapsulant 106.
  Such a power QFN package is formed, for example, in the following process steps.
  First, a lead frame including the signal leads 101, die pad 102, support leads 103, and other components is prepared. It should be noted that the prepared lead frame is often provided with dam bars for preventing the overflow of a resin encapsulant during resin encapsulation.
  Next, the back face of the semiconductor chip 104 is bonded, with the adhesive 108, onto the top face of the die pad 102 of the prepared lead frame. This process step is called “die bonding”.
  Then, an electrode pad of the semiconductor chip 104 mounted on the die pad 102 is electrically connected to the signal leads 101 or the die pad 102 through the thin metal wires 105. This process step is called “wire bonding”. As the thin metal wires 105, thin aluminum (Al) or gold (Au) wires may be appropriately used.
  Subsequently, the part of the die pad 102 other than the back face thereof, the semiconductor chip 104, the part of signal leads 101 other than the back faces thereof, the support leads 103, and the thin metal wires 105 are encapsulated with the resin encapsulant 106, such as an epoxy resin. In this case, the lead frame on which the semiconductor chip 104 has been mounted is introduced into a molding die assembly and transfer-molded.
  Finally, respective outer end portions of the signal leads 101 protruding outward from the resin encapsulant 106 are cut off after the resin encapsulation. By performing this cutting process step, the resultant outer end faces of the signal leads 101 are substantially flush with the lateral side faces of the resin encapsulant 106. That is to say, this structure does not include any outer lead, which is ordinarily provided as an external terminal. Furthermore, the outer electrodes 109 and the back face of the die pad 102 which are exposed without being covered with a resin encapsulant are placed on the motherboard.