Binary digits in a delay line memory pass through the line and are fed back to the beginning. Accessing data in a delay line imposes a time penalty while waiting for the desired data to come around again. After analyzing these timing issues, he proposes organizing the delay line memory into 256 delay line "organs" (DLAs) each storing 1024 bits, or 32 minor cycles, called a "major cycle." A memory access first selects the DLA (8 bits) and then the minor cycle within the DLA (5 bits), for a total of 13 address bits.