The effects of this modulation on voltage magnitude and phase angle is illustrated using phasor diagrams that map VR, VS, and the resistive and inductive components of Vline drop. Three power factor scenarios are shown, where (a) the line serves an inductive load so the current lags receiving end voltage, (b) the line serves a completely real load so the current and receiving end voltage are in phase, and (c) the line serves a capacitive load so the current leads receiving end voltage. In all cases the line resistance R causes a voltage drop that is in phase with current, and the reactance of the line X causes a voltage drop that leads current by 90 degrees. These successive voltage drops are summed to the receiving end voltage, tracing backward from VR to VS in the short line approximation circuit. The vector sum of VR and the voltage drops equals VS, and it is apparent in the diagrams that VS does not equal VR in magnitude or phase angle.