Describing the system in November 1988, Cray stated that the 12 times performance increase would be made up of a three times increase due to GaAs circuits, and four times due to the use of more processors. One of the problems with the Cray-2 had been poor multiprocessing performance due to limited bandwidth between the processors, and to address this the Cray-3 would adopt the much faster architecture used in the Cray Y-MP. This would provide a design performance of 8000 MIPS, or 16 GFLOPS.