The Alpha 21264 (EV6), for instance, was the first large micro-architecture to implement "Shadow Register File Architecture". It had two copies of the integer register file and two copies of floating point register that locate in its front end (future and scaled file, each contain 2 read and 2 write port), and took an extra cycle to propagate data between the two during context switch. The issue logic attempted to reduce the number of operations forwarding data between the two and greatly improved its integer performance and help reduce the impact of limited number of GPR in superscalar and speculative execution. The design was later adapted by SPARC, MIPS and some later x86 implementations.