The SPARC uses "Shadow Register File Architecture" as well for its high end line. It had up to 4 copies of integer register files (future, retired, scaled, scratched, each containing 7 read 4 write port) and 2 copies of the floating point register file. However, unlike Alpha and x86, they are located in backend as retire unit right after its Out of Order Unit and renaming register files and do not load instruction during instruction fetch and decoding stage and context switch is needless in this design.