The ULA mediates access to 32 KB of addressable RAM using 4 64-kilobit RAM chips (4164), sharing the RAM between the CPU and the video signal generation (or screen refresh) performed by the ULA itself. Two accesses have to be made to the RAM to get each byte (albeit with a single RAS), delivering a maximum transfer rate to or from RAM of one byte per 2 MHz cycle. In generating the video signal, the ULA is able to take advantage of this 2 MHz bandwidth when producing the picture for the high-bandwidth screen modes. Due to signalling constraints, the CPU can only access RAM at 1 MHz, even when it is not competing with the video system.