The "Status" register is used to report which features are supported and whether certain kinds of errors have occurred. The "Command" register contains a bitmask of features that can be individually enabled and disabled. The "Header Type" register values determine the different layouts of remaining 48 bytes (64-16) of the header, depending on the function of the device. That is, Type 1 headers for Root Complex, switches, and bridges. Then Type 0 for endpoints. The "Cache Line Size" register must be programmed before the device is told it can use the memory-write-and-invalidate transaction. This should normally match the CPU's cache line size, but the correct setting is system dependent. This register does not apply to PCI Express.