The minimum configuration for a 1110 system was two CAUs and one IOAU. The largest configuration, 6x4 was only used by NASA. The 1110 CAU was the first pipelined processor to be designed by UNIVAC. The CAU could have as many as four instructions in various stages of execution at any given instant. The IOAU was completely separate, both physically and logically from the CAU, and had its own access path to the various Main and Extended Memory Modules. This allowed I/O operations to be independent from the compute operations, no longer "stealing" memory cycles from CAU(s). The IOAU included 8 (optionally 16 or 24) 1108/1106 compatible 36-bit Word Channels, and also included the Hardware Maintenance Panel. Pictures/illustrations of a 1110 system typical showed the IOAU Maintenance Panel, as the CAU cabinet had no indicator lights. The IOAU Maintenance Panel could display the various CAU registers from one or two associated CAU(s). The 1110 CAU also introduced an extension to the instruction set of 'Byte Instructions'. The major components of the 1110 system, the CAU, IOAU and Main Memory cabinets were designed using the same 55-pin high density card connectors, and machine wire wrapped backplane(s) as the 1108/1106. The discrete component logic used by the older systems was replaced by transistor–transistor logic (TTL) integrated circuits (see Note, below). The CAU was an extremely complex unit, utilizing over 1000 cards.