Since 2005/2006, considering an architecture in which 4 processors share a chipset, the DIB is composed by two buses, each of them is shared among two CPUs. The theoretical bandwidth is doubled compared to a shared front-side bus up to 12.8 GB/s in the best case. However, the snoop information useful to guarantee the cache coherence of shared data located in different caches have to be sent in broadcast, reducing the available bandwidth. To mitigate this limitation, a snoop filter was inserted in the chipset, in order to cache the snoop information.