The use of reflection causes wafer exposure position to be extremely sensitive to the reticle flatness and the reticle clamp. Reticle clamp cleanliness is therefore required to be maintained. Small (mrad-scale) deviations in mask flatness in the local slope, coupled with wafer defocus. More significantly, mask defocus has been found to result in large overlay errors. In particular, for a 10 nm node metal 1 layer (including 48 nm, 64 nm, 70 nm pitches, isolated, and power lines), the uncorrectable pattern placement error was 1 nm for 40 nm mask z-position shift. This is a global pattern shift of the layer with respect to previously defined layers. However, features at different locations will also shift differently due to different local deviations from mask flatness, e.g., from defects buried under the multilayer. It can be estimated that the contribution of mask non-flatness to overlay error is roughly 1/40 times the peak-to-valley thickness variation. With the blank peak-to-valley spec of 50 nm, ~1.25 nm image placement error is possible. Blank thickness variations up to 80 nm also contribute, which lead to up to 2 nm image shift.