Because it was not possible to run Itanium McKinley chips with clock-level lock stepping, the Integrity NonStop machines instead use comparisons between chip states at longer time scales, at interrupt points and at various software sync points in between interrupts. The intermediate sync points are automatically triggered at every n'th taken branch instruction, and are also explicitly inserted into long loop bodies by all NonStop compilers. The machine design supports both dual and triple redundancy, with either two or three physical microprocessors per logical Itanium processor. The triple version is sold to customers needing the utmost reliability. This new checking approach is called NSAA, NonStop Advanced Architecture.