A nanolayer-base metal–semiconductor junction (M–S junction) transistor was initially proposed by A. Rose in 1960, and fabricated by L. Geppert, Mohamed Atalla and Dawon Kahng in 1962. Decades later, advances in multi-gate technology enabled the scaling of metal–oxide–semiconductor field-effect transistor (MOSFET) devices down to nano-scale levels smaller than 20 nm gate length, starting with the FinFET (fin field-effect transistor), a three-dimensional, non-planar, double-gate MOSFET. At UC Berkeley, a team of researchers including Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor and others fabricated FinFET devices down to a 17nm process in 1998, then 15nm in 2001, and then 10nm in 2002.