In this example, the codice_1 instruction on line 2 is dependent on the codice_1 instruction on line 1 because the register R1 is a source operand of the addition operation on line 2. The codice_1 on line 2 cannot execute until the codice_1 on line 1 completes. In this case, the dependence is static and easily determined by a microprocessor, because the sources and destinations are registers. The destination register of the codice_1 instruction on line 1 (codice_6) is part of the instruction encoding, and so can be determined by the microprocessor early on, during the decode stage of the pipeline. Similarly, the source registers of the codice_1 instruction on line 2 (codice_6 and codice_9) are also encoded into the instruction itself and are determined in decode. To respect this true dependence, the microprocessor's scheduler logic will issue these instructions in the correct order (instruction 1 first, followed by instruction 2) so that the results of 1 are available when instruction 2 needs them.