In the beginning, the capacitor C1 is fully charged (in the previous State 2) to the power supply voltage "V" with the polarity shown in Figure 1. Q1 is "on" and connects the left-hand positive plate of C1 to ground. As its right-hand negative plate is connected to Q2 base, a maximum negative voltage (-"V") is applied to Q2 base that keeps Q2 firmly "off". C1 begins discharging (reverse charging) via the high-value base resistor R2, so that the voltage of its right-hand plate (and at the base of Q2) is rising from below ground (-"V") toward +"V". As Q2 base-emitter junction is reverse-biased, it does not conduct, so all the current from R2 goes into C1. Simultaneously, C2 that is fully discharged and even slightly charged to 0.6 V (in the previous State 2) quickly charges via the low-value collector resistor R4 and Q1 forward-biased base-emitter junction (because R4 is less than R2, C2 charges faster than C1). Thus C2 restores its charge and prepares for the next State C2 when it will act as a time-setting capacitor. Q1 is firmly saturated in the beginning by the "forcing" C2 charging current added to R3 current. In the end, only R3 provides the needed input base current. The resistance R3 is chosen small enough to keep Q1 (not deeply) saturated after C2 is fully charged.