An XDR RAM chip's high-speed signals are a differential clock input (clock from master, CFM/CFMN), a 12-bit single-ended request/command bus (RQ11..0), and a bidirectional differential data bus up to 16 bits wide (DQ15..0/DQN15..0). The request bus may be connected to several memory chips in parallel, but the data bus is point to point; only one RAM chip may be connected to it. To support different amounts of memory with a fixed-width memory controller, the chips have a programmable interface width. A 32-bit-wide DRAM controller may support 2 16-bit chips, or be connected to 4 memory chips each of which supplies 8 bits of data, or up to 16 chips configured with 2-bit interfaces.