The CPU had a 60 ns clock cycle (16.67 MHz clock frequency) and its logic was built from 20-gate emitter-coupled logic integrated circuits originally developed by TI for the ILLIAC IV supercomputer. The CPU had an extremely advanced architecture and organization for its era, supporting microcoded arithmetic and mathematical instructions that operated on scalars, vectors, or matrices. The vector processing facilities had a memory-to-memory architecture; where the vector operands were read from, and the resulting vector written to, memory. The CPU could be have one, two, or four vector lanes, allowing the CPU to produce one to four vector results every cycle, depending on the number of vector lanes installed. The vector lanes were also used for scalar instructions, and each lane could keep up to 12 scalar instructions in-flight simultaneously. The CPU, with four lanes, allowed up to 36 instructions in total across the entire CPU.