Now, the capacitor C2 is fully charged (in the previous State 1) to the power supply voltage "V" with the polarity shown in Figure 1. Q2 is "on" and connects the right-hand positive plate of C2 to ground. As its left-hand negative plate is connected to Q1 base, a maximum negative voltage (-"V") is applied to Q1 base that keeps Q1 firmly "off". C2 begins discharging (reverse charging) via the high-value base resistor R3, so that the voltage of its left-hand plate (and at the base of Q1) is rising from below ground (-"V") toward +"V". Simultaneously, C1 that is fully discharged and even slightly charged to 0.6 V (in the previous State 1) quickly charges via the low-value collector resistor R1 and Q2 forward-biased base-emitter junction (because R1 is less than R3, C1 charges faster than C2). Thus C1 restores its charge and prepares for the next State 1 when it will act again as a time-setting capacitor...and so on... (the next explanations are a mirror copy of the second part of State 1).