If the processor has the 5 steps listed in the initial illustration, instruction 1 would be fetched at time "t"1 and its execution would be complete at "t5". Instruction 2 would be fetched at "t2" and would be complete at "t6". The first instruction might deposit the incremented number into R5 as its fifth step (register write back) at "t5". But the second instruction might get the number from R5 (to copy to R6) in its second step (instruction decode and register fetch) at time "t3". It seems that the first instruction would not have incremented the value by then. The above code invokes a hazard.