When clock formula_1 is low transistor Q2 is turned off. At the same time clock formula_2 is high turning on transistor Q1 resulting in capacitor C1 being charged to "V"in. When formula_1 goes high the top plate of C1 is pushed up to twice "V"in. At the same time switch S1 closes so this voltage appears at the output. At the same time Q2 is turned on allowing C2 to charge. On the next half cycle the roles will be reversed: formula_1 will be low, formula_2 will be high, S1 will open and S2 will close. Thus, the output is supplied with 2"V"in alternately from each side of the circuit.Peluso "et al.", p.36</ref>