Being able to pause a system at any time for any duration can also be used to synchronize the CPU to an asynchronous event. (While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins RDY on the 6502, or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is simpler, is more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting. In a basic design, to start waiting, the CPU would write to a register to set a binary latch bit which would be ANDed or ORed with the processor clock, stopping the processor. A signal from a peripheral device would reset this latch, resuming CPU operation. hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal.)