Also, when both "A" and "B" are high, so that the output is low, the circuit will pump one capacitor-load of charge from Vdd to ground for each clock cycle, by first charging and then discharging the capacitor in each clock cycle. This makes the circuit (with its output connected to a high impedance) less efficient than the static version (which theoretically should not allow any current to flow except through the output), and when the "A" and "B" inputs are constant and both high, the dynamic NAND gate uses power in proportion to the clock rate, as long as it functions correctly. The power dissipation can be minimized by keeping the load capacitance low, but this in turn reduces the maximum cycle time, requiring a higher minimum clock frequency; the higher frequency then increases power consumption by the relation just mentioned. Therefore, it is impossible to reduce the idle power consumption (when both inputs are high) below a certain limit which derives from an equilibrium between clock speed and load capacitance.