The R18000 improved the floating-point instruction queues and revised the floating-point unit to feature two multiply–add units, quadrupling the peak FLOPS count. Division and square-root would be performed in separate non-pipelined units in parallel to the multiply–add units. The system interface and memory hierarchy was also significantly reworked. It would have a 52-bit virtual address and a 48-bit physical address. The bidirectional multiplexed address and data system bus of the earlier models would be replaced by two unidirectional DDR links, a 64-bit multiplexed address and write path and a 128-bit read path. The paths could be shared with another R18000 through multiplexing. The bus could also be configured in the SysAD or Avalanche configuration for backwards compatibility with R10000 systems.