The R18000 would have a 1 MB four-way set-associative secondary cache to be included on-die; supplemented by an optional tertiary cache built from single data rate (SDR) or double data rate (DDR) SSRAM or DDR SDRAM with capacities of 2 to 64 MB. The L3 cache would have its cache tags, equivalent to 400 KB, located on-die to reduce latency. The L3 cache would be accessed via a 144-bit bus, of which 128 bits are for data and 16 bits for ECC. The L3 cache's clock rate would be programmable.