A multi-processor system consists of four processors - P1, P2, P3 and P4, all containing cached copies of a shared variable "S" whose initial value is 0. Processor P1 changes the value of "S" (in its cached copy) to 10 following which processor P2 changes the value of "S" in its own cached copy to 20. If we ensure only write propagation, then P3 and P4 will certainly see the changes made to "S" by P1 and P2. However, P3 may see the change made by P1 after seeing the change made by P2 and hence return 10 on a read to "S". P4 on the other hand may see changes made by P1 and P2 in the order in which they are made and hence return 20 on a read to "S". The processors P3 and P4 now have an incoherent view of the memory.