DSLOT-NN: Digit-Serial Left-to-Right Neural Network Accelerator
We propose a Digit-Serial Left-tO-righT (DSLOT) arithmetic based processing
technique called DSLOT-NN with aim to accelerate inference of the convolution
operation in the deep neural networks (DNNs). The proposed work has the ability
to assess and terminate the ineffective convolutions which results in massive
power and energy savings. The processing engine is comprised of low-latency
most-significant-digit-first (MSDF) (also called online) multipliers and adders
that processes data from left-to-right, allowing the execution of subsequent
operations in digit-pipelined manner. Use of online operators eliminates the
need for the development of complex mechanism of identifying the negative
activation, as the output with highest weight value is generated first, and the
sign of the result can be identified as soon as first non-zero digit is
generated. The precision of the online operators can be tuned at run-time,
making them extremely useful in situations where accuracy can be compromised
for power and energy savings. The proposed design has been implemented on
Xilinx Virtex-7 FPGA and is compared with state-of-the-art Stripes on various
performance metrics. The results show the proposed design presents power
savings, has shorter cycle time, and approximately 50% higher OPS per watt.
Muhammad Sohail Ibrahim, Muhammad Usman, Malik Zohaib Nisar, Jeong-A Lee
# DSLOT-NN: Digit-Serial Left-to-Right Neural Network Accelerator

###### Abstract

We propose a Digit-Serial Left-to-right (DSLOT) arithmetic based processing technique called _DSLOT-NN_ with aim to accelerate inference of the convolution operation in the deep neural networks (DNNs). The proposed work has the ability to assess and terminate the ineffective convolutions which results in massive power and energy savings. The processing engine is comprised of low-latency most-significant-digit-first (MSDF) (also called _online_) multipliers and adders that processes data from left-to-right, allowing the execution of subsequent operations in digit-pipelined manner. Use of online operators eliminates the need for the development of complex mechanism of identifying the negative activation, as the output with highest weight value is generated first, and the sign of the result can be identified as soon as first non-zero digit is generated. The precision of the online operators can be tuned at run-time, making them extremely useful in situations where accuracy can be compromised for power and energy savings. The proposed design has been implemented on Xilinx Virtex-7 FPGA and is compared with state-of-the-art Stripes on various performance metrics. The results show the proposed design presents power savings, has shorter cycle time, and approximately \(50\%\) higher OPS per watt.

 Online arithmetic, most-significant-digit first, convolution neural network, CNN acceleration.

## I Introduction

In the recent years, deep neural networks have shown impressive performance and are considered as state-of-the-art classification algorithms, achieving near-human performance in applications including image processing, natural language processing, object detection, and bio-informatics etc., [1, 2, 3]. The performance of the DNNs is related to their computational complexity. It is commonly observed that the number of layers has a significant impact on the network's performance [4]. Specifically, a greater number of layers often results in superior feature extraction capabilities. However, it is important to note that deeper networks typically require a larger number of parameters and, consequently, more extensive computational resources and memory capacity to be effectively trained. The main computation is the multiply-accumulate (MAC) operation that account for \(99\%\) of the total computations in convolution neural networks (CNN) [5]. The arrangement of MAC units are dependent on the size and shape of DNN. For example, the first entry DNN in ImageNet challenge to surpass human-level accuracy named ResNet model with \(152\) layers requires \(11.3\) GMAC operations and \(60\) million weights [6]. As such, there exists a trade-off between the benefits of increased network depth and the associated costs in terms of model size and resource requirements.

### _Related Works_

The aforementioned challenges led the research into designing domain specific architectures to accelerate the computation of convolution operations in deep neural networks [7, 8]. Moreover, such designs perform the CNN inference in a layer-by-layer fashion, which substantially increases the flow of data to and from the external memory. During the past few years, there has been an emerging trend towards the implementation of DNN acceleration and evaluation designs using bit-serial arithmetic circuits [9, 10]. This trend has been motivated due to various reasons such as: (1) reduce the computational complexity and the required communication bandwidth (2) the requirement of variable data precision by various deep learning networks as well as the requirement of variable precision within the layers of a network, (3) the compute precision can be varied easily using bit-serial designs simply by adjusting the number of compute cycles in a DNN model evaluation, and (4) the need to improve the energy and resource utilization by early detection of negative results, hence terminating such ineffectual computations yielding negative results. Stripes [9] is considered among the pioneering works employing bit-serial multipliers instead of conventional parallel multipliers in their accelerator architecture to address the challenges such
as power and throughput. In the similar context, UNPU [10] enhanced the Stripes architecture by incorporating look-up tables (LUTs) to store the inputs to be reused multiple times during the computation of an input feature map.

Most modern CNNs use rectified linear unit (ReLU) as an activation function which filters the negative results of the convolution and replaces them with zero. Studies [11, 12, 13], show that about \(42\%\)-\(68\%\) of the modern CNN produce a negative output, suggesting a significant wastage of power on unnecessary computation. Most conventional CNN acceleration designs perform the ReLU activation separately, after the completion of the convolution operations. Recently, some researchers have proposed methods of early detection and termination of the negative results [11, 12, 13]. Early detection of the negative activations results in reduced computations and improvement in energy requirements of the hardware designs. Existing solutions either involve special digit encoding schemes [12, 13] or designing sophisticated circuits [11] to predict if the result is negative. In [11], the algorithm requires significant software complicity to re-order the operation, limiting the deployment of such techniques.

In this research, we propose to use _Online arithmetic_ for early detection of negative input to the ReLU activation function and terminate ineffective convolution. We develop online arithmetic-based multiplier and adders to perform multiply and accumulate operation.

### _Organization and Specific Contributions of the Paper_

The specific contributions of this work are as follows:

* DNN accelerator design based on MSDF arithmetic scheme.
* A novel and straight-forward mechanism for the detection of negative activation during the computation of the convolution operation.
* Energy efficient design resulting in \(50\%\) higher OPS per watt compared to SIP [9].

The rest of the paper is organized as follows. Section II presents the details of proposed online arithmetic based convolution computation and early termination technique. The evaluation and results of the proposed methodology has been presented in Section III, followed by conclusion in Section IV.

## II Materials and Methods

A convolution layer processes an input image by applying \(M\) 3D kernels in a sliding window fashion. Typically, convolution layers in CNNs perform a series of multiply-accumulate (MAC) operations to compute the output feature maps. Each MAC operation involves multiplying corresponding elements of the kernel and input feature maps and summing up the results. The convolution operation carried out in a CNN layer can be outlined by a simple weighted sum or SOP equation as follows;

\[y_{ij}=\sum_{a=0}^{m-1}\sum_{b=0}^{m-1}w_{ab}x_{(i+a)(j+b)} \tag{1}\]

where, \(y_{ij}\) is the \(ij^{th}\) output of layer \(l\), \(w\) is the kernel of dimensions \(m\times m\), and \(x\) represents the input of the convolution. It can be observed from the equation that for any \((i,j)\), the kernel \(w\) remains the same while the input changes according to the sliding window operation. This characteristic of the convolution brings the opportunity of weight stationarity in the dataflow architecture of convolution layers.

### _Online Artihemtic_

The online arithmetic is essentially a computing paradigm that works serially in most-significant digit first (MSDF) manner, i.e., the inputs are fed, and output is generated digit-by-digit from left-to-right (LR) [14]. Digit level pipelining stands out as a key feature of this computing paradigm, among several other characteristics. Since all the computation is done in LR manner, it is possible to pipeline subsequent operations at digit level i.e., as soon as first digit of the preceding operation is obtained, the succeeding operation regardless of data dependency, can start computation after a small fixed delay called _online delay_, denoted by \(\delta\) as shown in Fig. 1.

Owing to this property, the intermediate results need not be stored, rather they are consumed in the successive computation, resulting in a decreased number of read/write operation from/to memory, hence low bandwidth requirements and consequent energy savings. In order to generate the output on the basis of partial input information, the online computation requires flexibility in computing digits. This is done by employing redundant digit number system. To this end, signed digit (SD) redundant number system in which number representation is done in radix (\(r\)) format is usually employed which has more than \(r\) values for the representation of a given value. In this study, we use symmetric radix-\(2\) redundant digit set of \(-1,0,1\). For compatibility, the online modules use fractional numbers, this also simplifies the alignment of the operands. The first digit of the operand has weight of \(r^{-1}\), and at a given iteration \(j\), the digit \(x_{j}\) is represented by two bits \(x^{+}\) and \(x^{-}\), and the numerical value is given by (2).

\[x_{j}=SUB(x^{+},x^{-}) \tag{2}\]

The input and outputs are given as (3) and (4) respectively.

\[x[j]=\sum_{i=1}^{j+\delta}x_{i}r^{-i} \tag{3}\]

\[z[j]=\sum_{i=1}^{j}z_{i}r^{-i}, \tag{4}\]

Fig. 1: Timing characteristics of online operation with \(\delta=3\).
where the square brackets represent the iteration index and subscript denote the digit index. A given online algorithm executes for \(n+\delta\) cycles. The single digit input is fed for \(n\) iterations, and after \(\delta\) cycles a single output digit is generated in each iteration.

#### Iii-A1 Online Multiplier (OLM)

In most CNN designs, the convolution during inference is carried out by multiplying a constant weight kernel with the input image in a sliding window fashion. This particular characteristic of CNNs suggests that the kernel matrix must be used multiple times for the convolution operation. In this context, an online multiplier, with one operand in parallel and the other in serial manner, can be useful, where the weight kernel can be employed in parallel and input can be fed in serial manner. In this study, we use the non-pipelined serial-parallel multiplier presented in [15], and depicted in the following Fig. 2(a). The multiplier generates its output in MSDF fashion after an online delay of \(\delta=2\) cycles. The serial input and and output in each cycle are represented as (3) and (4) respectively, while the constant weight is represented as:

\[Y[j]=Y=-y_{0}\cdot r^{0}+\sum_{i=1}^{n}y_{i}r^{-i} \tag{5}\]

Further derivations related to the recurrence and selection function of the serial-parallel online multiplier can be found in [15].

#### Iii-A2 Online Adder (OLA)

Since the multipliers used in this study generate their outputs in an MSDF fashion, an adder with similar capability is needed to compute the sum-of-product (SOP). In this context, a digit-serial online adder that takes both its inputs and generates its output in an MSDF fashion, is employed. This enables digit-level pipelining in the proposed SOP design and also helps in the early determination and subsequently termination of negative activations. The online adder with an online delay of \(\delta=2\), follows a simple construction as presented in Fig. 2(b). Further details and relevant derivations can be found in [16].

### _Proposed Design_

This section details the architecture of the proposed DSLOT-NN based on online computation units with early termination capability. The arrangement of computation units in the processing engine (PE) of DSLOT-NN and the techniques for terminating ineffectual convolutions (resulting as negative) are discussed.

#### Iii-B1 Processing Engine and DSLOT-NN Architecture

The architecture of the proposed DSLOT-NN is presented in Fig. 4. Each PE, presented in Fig. 3 contains \(k\times k\) online serial-parallel multipliers followed by a reduction tree to generate one output pixel. The input pixel is fed serially while the kernel pixel is fed in parallel, depicted by the thickness of the arrows in Fig. 4. The arrangement of PEs is done in such a way that the outputs of the \(4\) PEs will directly be fed to the ensuing pooling layer. It is worth noting that the architecture presented in Fig. 4 is designed for a CNN with single input feature map. A similar approach can be followed for a CNN with multiple input feature maps. A generic representation of the DSLOT-NN is also presented in the following sections.

Each multiplier in the PE is responsible for the multiplication of one pixel in the convolution window with the corresponding pixel in the same feature map of the convolution kernel. Therefore, all the \((k\times k)\) pixels are processed in parallel. The number of cycles required for a PE to generate its output can be calculated as follows

\[\begin{split} Num_{Cycles}=\delta_{\times}+\delta_{+}\times\lceil log _{2}(k\times k)\rceil+\\ \delta_{+}\times\lceil log_{2}(N)\rceil+p_{out}\end{split} \tag{6}\]

where \(\delta_{\times}\) and \(\delta_{+}\) are the online delays of online multiplier and adder respectively, \(\lceil log_{2}(k\times k)\rceil\) is the number of reduction tree stages required to generate the SOP of the \(k\times k\) multipliers, \(\lceil log_{2}(N)\rceil\) is the number of reduction tree stages required to add the SOP results of \(N\) input feature maps, and \(p_{out}\) is the precision of the SOP result. \(p_{out}\) is calculated as follows.

\[p_{out}=p_{out}^{Mult}+\lceil log_{2}(k\times k)\rceil \tag{7}\]

#### Iii-B2 Early Termination of Negative Computations

Most CNN accelerator designs put emphasis on the faster or efficient generation of the sum-of-product (SOP), but only a few works discuss the possibility of early assessment of negative values

Fig. 3: processing engine Architecture

Fig. 2: Basic Components (a) Online Serial-Parallel Multiplier [15], where \(x\) is the serial input and \(Y\) is the parallel output, (b) Online Adder [16]
for the activation layer (ReLU). The early determination of negative activations is a challenging problem in accelerators based on conventional arithmetic. For instance, the bit-serial multipliers takes _multiplicand_ in parallel and the _multiplier_ is processed serially. In each iteration a partial product is generated and stored in register, which is then shifted into appropriate positions before being added to other partial products to obtain the final product. Typically a series of adders, such as carry save adders, ripple-carry adders, etc., are employed to perform this reduction. In convolution, another level of reduction is required to get the output pixel. Furthermore, another level of reduction is needed, if there are more than \(1\) input feature maps, to compute the SOP. In conventional bit-serial multipliers, the determination of the most significant bit and the identification of the result's polarity require waiting until all partial products have been generated and added to the previous partial sums. Among the few works that aim to solve the early detection of the negative activations, use either a digit encoding scheme or an estimation technique for early negative detection [12, 13, 17].

The challenge of early detection and termination of negative activations can be addressed by the intrinsic ability of online arithmetic to generate output digits in an MSDF manner. The proposed design supports the termination of negative activation computation in \(p\) cycles, where \(p<\mathbb{N}\), and \(\mathbb{N}\) is the number of cycles to compute complete result. This is done by observing and comparing the output digits. The process of detecting the negative activations and subsequently terminating the relevant computation is summarized in Algorithm 1.

```
1:\(z^{+}[j]\), \(z^{-}[j]\) bits
2:for j : l to \(Num_{cycles}\)do
3:\(z^{+}[j]\gets z^{+}[j]\)\(\frown z^{+}_{j}\)
4:\(z^{-}[j]\gets z^{-}[j]\)\(\frown z^{-}_{j}\)
5:if\(z^{\uparrow}[j]<z^{-}[j]\)then
6: Terminate
7:else
8: Continue
9:endif
10:endfor
```

**Algorithm 1** Early detection and termination of negative activations

The ReLU unit is equipped with registers to store redundant output \(z^{+}[j]\) and \(z^{-}[j]\) bits, which are the positive and negative output digits of the SOP representing the output SOP in redundant number representation. During each iteration, the new digits are concatenated, indicated by "\(\frown\)" in Algorithm 1, with their corresponding pre logits and as soon as the value of \(z^{+}[j]\) goes below the value of \(z^{-}[j]\) indicating a negative output, a termination signal is generated by the control unit and the computation of the SOP is terminated. Fig. 4, shows the block diagram of the proposed DSLOT-NN considering one input feature map. This simple procedure of early negative detection can save upto \(45-50\%\) of the computation cycles for a convolution operation resulting in a negative number subsequently resulting in an energy efficient design. According to (6), the number of cycles required by the proposed design to process one convolution is found to be \(33\), where \(\delta_{\times}=\delta_{+}=2\), \(k=5\), \(N=1\), and \(p_{out}=21\) considering the bit growth in the reduction tree stages. Where \(p_{out}\) is calculated by eq. 7 as, \(p_{out}^{Mult}=16\) and \(\lceil log_{2}(k\times k)\rceil=5\), with \(k\times k=5\times 5=25\) as the convolution kernel dimensions.

#### Iii-B3 General DSLOT-NN Design

A general extension of the proposed DSLOT-NN for larger networks is presented in Fig. 5. The number of PEs in a processing block (PB) depend upon the number of input feature maps for a particular convolution layer in a CNN. This generic architecture can be repeated multiple times depending upon the number of output feature maps if more parallelism is required.

The PBs are responsible for the computation of one of the pixels belonging to a pooling (or maxpooling) window. In Fig. 5, we presented an example of a \(2\times 2\) pool window hence the 4 PBs. Each PB consists of multiple PEs followed by an online adder tree. The number of PEs in a PB represents

Fig. 4: DSLOT-NN block diagram
the input tiling and it has a range of \((1,N)\), where \(N\) is the number of input feature maps. The output digits of the adder tree are forwarded to a simple comparator circuit to perform the detection of negative activations for ReLU. The structure of a PE is presented in Fig. 3.

Section III contains further details on the experiments conducted to determine the amount of clock cycles and the subsequent energy savings achieved due to the early detection and the termination of the negative activations.

## III Experimental Results

To show the effectiveness of DSLOT-NN both in-terms of latency as well as the early determination of negative activations, we consider a pre-trained CNN as shown in Fig. 6.

As an initial study, we opt to accelerate the first three layers i.e., convolution, ReLU and maxpooling only as presented in Fig. 7. With one input feature map, and generating one output pixel after a maxpooling of \(2\times 2\), we employ the configuration of DSLOT-NN as shown in Fig. 5. Four PEs equipped with \(25\) multipliers and reduction tree each, compute the sum-of-product of one of the convolution window shown in different colors of Fig. 7, in parallel. The rectified linear unit (ReLU) operation has been integrated as an inherent characteristic of the design, whereby each PE in the system detects the sign of its output. In the event of a negative sign detection, the further computation process is terminated following Algorithm 1. An experiment was conducted on the MNIST handwritten digit classification database [18].

### _Results and Analysis of the Proposed Early Negative Detection and Termination_

During inference of the proposed design, it is found that on average, \(12.5\%\) of output pixels result in negative values for each MNIST test set image. Fig. 8 presents a graphical representation of the average percentage of negative activations in each MNIST class. This is calculated by counting the number of negative activations resulting in each convolution performed on MNIST test set. The reason for only \(12.5\%\) predicted negative activations, compared to the statistics explained in studies such as [11, 12, 13], is mainly because these works report the statistics for popular DNNs such as VGG-16, AlexNet, ResNet50, etc., while the proposed work uses a relatively simple CNN design. Another reason is that for the proposed implementation, the adopted CNN design was trained and implemented without the inclusion of the bias term. In general CNN architectures handling MNIST database, a substantial number of activations are rendered negative due to the reason that in MNIST database, a large number of input pixels are zero due to the presence of massive black regions in the image. In most networks trained on MNIST database, these bias terms are usually very small, and mostly negative, values. Therefore, the absence of the bias term in the proposed CNN implementation causes lesser negative values. This problem can also be catered by exploiting the sparsity in the input feature maps. This can lead to significant computational savings in terms of the number of cycles required to calculate an entire convolution. For simplicity, a randomly selected batch of 1000 images (100 images per class) from the MNIST test set was used.

The average number of computation cycles being saved per digit can be seen in Fig. 9, where, the x-axis represent the digit classes in the MNIST database and y-axis represent the percentage of average number of computation cycles being

Fig. 5: General DSLOT-NN architecture

Fig. 8: Average number of negative output activations (\(\%\)) (after CNN layer) per image in each MNIST digit class

Fig. 6: CNN for MNIST handwritten digit classification

Fig. 7: Simultaneous computation of first three layers of the CNN
saved during the convolution computation using the proposed design.

### _FPGA Implementation_

For comparison, we consider the bit-serial inner product units (SIP) from Stripes [9], presented in Fig. 10, for a similar configuration as the proposed design. The SIP unit design is extended to perform 8-bit multiplication and subsequently the SIP processing engines are designed for computing the (\(k\times k\)) convolution. This results in a similar configuration as the proposed design presented in Fig. 4.

A detailed description of the SIP design is presented in Fig. 11. The partial product generator (PPG) presented in Fig. 11(a) is the AND gate array responsible for generating the partial products for the multiplication of a pixel of kernel matrix with the corresponding input pixel fed in a bit-serial manner. Where \(w[0],w[1],\ldots w[n]\) represent the bits of a \(n\)-bit kernel pixel, while \(x[i]\) is the input bit at iteration \(i\). This input bit is ANDed with \(n\)-bits of the kernel pixel to generate the \(i^{th}\) partial product. For a fair comparison, \((k\times k)\) PPGs are used in the SIP design whose outputs, the \((k\times k)\) partial products are forwarded to a reduction tree which generates the sum of these partial products. This reduction tree is followed by an accumulator which accumulates the incoming sum of partial products (SOPP) by shifting and adding the previous sum with the incoming SOP. This process is iterated \(n\) times, keeping the input and kernel precision the same (\(n\)).

The critical path of the SIP design can be represented by the following equation

\[t_{SIP}=t_{AND}+5\times t_{CPA-8}+t_{CPA-21} \tag{8}\]

Similarly, the critical path of the proposed design can be calculated as the sum of the critical path of online multiplier and the subsequent reduction tree.

\[t_{OLM}=t_{[2:1]MUX}+t_{[3:2]Adder}+t_{CPA-4}+t_{SELM}+t_{XOR} \tag{9}\]

The critical path of an online adder (OLA) is found to be

\[t_{OLA}=2\times t_{FA}+t_{FF} \tag{10}\]

Therefore, the critical path for the reduction tree can be calculated as the product of the number of stages and \(t_{OLA}\). So, the critical path of the proposed DSLOT-NN can be calculated as

\[t_{DSLOT}=t_{OLM}+5\times t_{OLA} \tag{11}\]

The input and weight are represented by fixed point 8-bits. However, for the proposed design the fixed point-8 is converted to redundant representation. The effect of precision of the input on the model accuracy is not considered in the scope of this work. SIP uses simple implementation for multiplication where the weights bits are fed in parallel and ANDed with the input which is fed serially. Both the SIP and the proposed design have been implemented on Virtex-7 FPGA and the results of the implementation are presented in Table. I. In terms of area, the proposed design has marginally higher consumption than SIP in terms of look-up tables (LUT). The proposed design shows savings in power consumption. In particular, the design has \(9.1\%\) and \(33.22\%\) low power and energy consumption than SIP, respectively. The proposed design has smaller critical path and shows approximately \(48.6\%\) shorter than SIP. Besides the significant improvement in critical path delay, in this implementation, the experiments were conducted on FPGA and the primary issues considered for the scope of this work were the challenge of early termination of negative activations and the subsequent computational efficiency. The results of performance density in-terms of \(GOPS/W\) showcase the effectiveness of the proposed method. Moreover, in future works, more experiments

Fig. 11: SIP design, (a) Partial product generator (PPG), (b) Overall SIP design

Fig. 10: A general bit-serial inner product unit (SIP) [9]

Fig. 9: Average number of computation cycles (\(\%\)) saved per class in MNIST hand-written digit classification database
on professional design tools will be conducted where various design optimizations, including the timing optimization will be included to assess the robustness and flexibility of the proposed design. The effect of early termination is observed in the significant improvement in performance of the proposed design. DSLOT-NN has approximately \(49.7\%\) higher \(OPS/W\) than SIP.

The LUTs used by the proposed design are slightly higher in number compared to the SIP design. In particular, the proposed design uses \(56.86\%\) more number of LUTs compared to the SIP design, however, given the lower critical path delay, dynamic power, and the capability of energy and computation savings owing to the early detection and termination of negative activations, it can be observed from the results that the proposed design has superior performance compared to SIP design.

Although, the proposed design has been tested on a relatively simple and small benchmark, however, the general design presented in Fig. 5 shows the overall scheme of the implementation which can handle arbitrary kernel size and the number of input feature maps to construct the convolution layer of various dimensions for any given network and database.

## IV Conclusion

In this paper we presented DSLOT-NN which utilize online arithmetic based arithmetic operators for the acceleration of convolution layers in deep neural networks. The online arithmetic presents various benefits including shorter latency, variable precision and digit-level pipelining. We implemented a mechanism to detect and terminate the ineffective convolutions which resulted in power savings and increased performance. In particular, the proposed design has approximately \(50\%\) higher performance compared to the state-of-the-art approach for convolution computation. In future, we plan to analyze the behavior of online arithmetic in DNN acceleration with variable input and kernel precision in an inter-layer as well as intra-layer setting. Furthermore, the sparsity in the input and kernels will also be exploited to further improve the performance and energy efficiency of the proposed design.
