SOT-MRAM-Enabled Probabilistic Binary Neural Networks for Noise-Tolerant
  and Fast Training
We report the use of spin-orbit torque (SOT) magnetoresistive random-access
memory (MRAM) to implement a probabilistic binary neural network (PBNN) for
resource-saving applications. The in-plane magnetized SOT (i-SOT) MRAM not only
enables field-free magnetization switching with high endurance (> 10^11), but
also hosts multiple stable probabilistic states with a low device-to-device
variation (< 6.35%). Accordingly, the proposed PBNN outperforms other neural
networks by achieving an 18* increase in training speed, while maintaining an
accuracy above 97% under the write and read noise perturbations. Furthermore,
by applying the binarization process with an additional SOT-MRAM dummy module,
we demonstrate an on-chip MNIST inference performance close to the ideal
baseline using our SOT-PBNN hardware.
Puyang Huang, Yu Gu, Chenyi Fu, Jiaqi Lu, Yiyao Zhu, Renhe Chen, Yongqi Hu, Yi Ding, Hongchao Zhang, Shiyang Lu, Shouzhong Peng, Weisheng Zhao, Xufeng Kou
# SOT-MRAM-Enabled Probabilistic Binary Neural Networks for Noise-Tolerant and Fast Training

###### Abstract

We report the use of spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) to implement a probabilistic binary neural network (PBNN) for resource-saving applications. The in-plane magnetized SOT (i-SOT) MRAM not only enables field-free magnetization switching with high endurance (\(>10^{11}\)), but also hosts multiple stable probabilistic states with a low device-to-device variation (\(<6.35\%\)). Accordingly, the proposed PBNN outperforms other neural networks by achieving an 18\(\times\) increase in training speed, while maintaining an accuracy above 97% under the write and read noise perturbations. Furthermore, by applying the binarization process with an additional SOT-MRAM dummy module, we demonstrate an on-chip MNIST inference performance close to the ideal baseline using our SOT-PBNN hardware.

## I Introduction

With the advent of artificial intelligence, a seismic shift is observed in computing paradigms. As we move towards handling larger volumes of data and higher task complexities, new architectures for artificial neural networks (ANNs) have sprung up in numerous applications [1]. Conventionally, ANNs have relied on high-precision floating-point arithmetic to obtain optimal computational results. However, these approaches always require substantial computing and memory resources. Therefore, as the number of operations and data volume increase, the training process inevitably slows. In addition, the performance of these deterministic networks is heavily affected by discrepancies between standard training datasets and actual input data, which invariably result in reduced accuracy [2]. Alternatively, probabilistic-featured PBNNs, which introduce stochasticity within the network to enhance robustness, have been proposed to facilitate the convergence to global optima [3]. Consequently, the noise-tolerant PBNNs could offer accelerated training, robustness, and resource-saving capabilities for image/video classification and natural language processing.

In principle, the key of PBNNs relies on the conversion of probabilities into deterministic outcomes via data sampling [4]. This necessitates that the PBNN hardware withstands a large number of sampling operations, while the power consumption for each operation needs to be as low as possible. In this context, the non-destructive electrical manipulation of magnetic moments inherently allows MRAM to possess high endurance and energy-efficient write/read characteristics. More importantly, the magnetization switching probability can be well-controlled by the injection current level via spin-orbit torque, therefore making MRAM a suitable building block to construct PBNNs.

Inspired by the above scenario (Fig. 1), we utilize the SOT-MRAM platform to harness the PBNN advantages. The device across the 8-inch wafer exhibits highly consistent performance in terms of low resistance variation and identical probabilistic switching curves with repeatable state variables. By implementing both the vector-matrix multiplication (VMM) and the binarization operations with SOT-MRAM, we demonstrate a noise-tolerant and fast-training PBNN with an on-chip MNIST digit recognition accuracy of 90%.

## II Field-Free Probabilistic Switching of In-Plane Magnetized SOT-MRAM

### _Device characterizations and SOT-driven probabilistic magnetization switching_

High-quality magnetic tunnel junction (MTJ)/heavy metal (HM) thin films were prepared on 8-inch Si/SiO\({}_{2}\) wafers by magnetron sputtering. To enable field-free operation, we adopted the i-SOT MRAM configuration, in which an elliptical-shaped MTJ design warrants in-plane magnetic anisotropy. Accordingly, the spin current generated in the HM layer is parallel to the magnetization direction (\(M\)) of the free layer; therefore, the SOT is inserted to directly switch \(M\) without the presence of an assisted magnetic field (Fig. 2). After film growth, large-scale SOT-MRAM array was fabricated, with typical device size of 0.7 \(\upmu\)m \(\times\) 2 \(\upmu\)m. High-resolution transmission electron microscope (HR-TEM) images in Fig. 3 visualize the sharp hetero-interfaces. Subsequently, reliable field-free SOT-driven magnetization switching was demonstrated (Fig. 4), where the response time of the SOT-MRAM is below 400 ps, and the hysteresis window (_i.e._, switching voltage of 400 ps pulse is \(V_{\text{C}}\)) of the \(R\)-\(V\) curve is modulated by the pulse width. Moreover, because of the non-destructive SOT switching mechanism, the recorded parallel resistance (\(R_{\text{P}}\)) and antiparallel resistance (\(R_{\text{AP}}\)) in Fig. 5 did not experience any distortion after \(10^{11}\) write/read cycles (_i.e._, the tunneling magnetoresistance ratio of \(\sim\)70% is sufficient for the VMM operation in PBNNs). Besides, by changing the input voltage around \(V_{0}\) (voltage of 50% switching probability), multiple switching probability states (_i.e._, network weights) are obtained (Fig. 6), and their corresponding probabilities are repeatable (_i.e._, whose values were deduced by counting the number of \(R_{\text{P}}\)-to-\(R_{\text{AP}}\) switching during 500 samplings per voltage).

Apart from single SOT device characterizations, device-to
device variations also play an important role in determining the overall network functionality. In this regard, Fig. 7 confirms that 8 randomly selected SOT-MRAM devices from the array all yielded 11 well-defined intermediate probabilistic states, with an average variation of 6.35% in the examined operating range. In the meantime, the standard deviation of the \(R_{\text{P}}\) (\(R_{\text{AP}}\)) normal distribution curve, which was collected from 100+ devices across the 8-inch wafer, is found to be 4.72% (4.79%), as shown in Fig. 8. Besides, we need to point out that such a small resistance variation has a negligible impact on the MNIST classification accuracy of the subsequent simulations and PBNN on-chip validation. Consequently, the proposed SOT-MRAM provides stable and uniform probabilistic switching states, thereby laying a solid foundation for the design and implementation of PBNN.

## III SOT-MRAM-Enabled PBNN Implementation

### PBNN network structure and process flow for MNIST test

To demonstrate the SOT-MRAM-enabled PBNN, we developed a network that consists of two convolutional layers, two max-pooling layers, and three fully connected layers (_i.e._, all layers are constructed by SOT-MRAM) for standard MNIST handwritten digit recognition test (Fig. 9). Utilizing the faster training speed of PBNN, our PyTorch simulation results in Fig. 10 show that the ideal classification accuracy of PBNN quickly exceeds 98% after only 4 epochs, whereas other networks require at least 20 epochs under full-precision conditions [5, 6, 7]. Equivalently, the PBNN system can realize a significant training time reduction of 6\(\times\) to 18\(\times\) (Fig. 11). Another advantage of PBNN is its resource-saving feature. For instance, the entire network needs only eight quantized states for both weights and activations to achieve an accuracy above 98% at 30 epochs (Fig. 12). Furthermore, the PBNN displays a salient noise-tolerant property against the write and read errors. According to the error-awareness simulation data in Fig. 13, it is seen that the training result remains almost constant with respect to the write error, which may benefit from the natural stochasticity of probabilistic switching. On the other hand, even though the increase of the read error lowers the classification accuracy of PBNN to 90%, its performance is still better than that of other neural network counterparts [8]. Considering that the measured write and read errors of the SOT-MRAM devices are less than 6.35% (Fig. 7) and 4.8% (Fig. 8) respectively, the overall accuracy of our SOT-PBNN can reach the 97.33% benchmark in the ideal scenario.

### Hardware implementation of SOT-MRAM PBNN

Guided by the PyTorch simulation, we further designed an on-chip PBNN system based on the in-plane magnetized SOT-MRAM array. As illustrated in Fig. 14, the row devices are selected through an SWL decoder, while the column devices are selected by write and read voltages from a digital-to-analog converter (DAC). Afterwards, a transimpedance amplifier (TIA) converts the current accumulated during the VMM operation into a voltage signal, which is binarized before passing to the next network layer. Given that the SOT-MRAM resistance changes with the read voltage, the binarization process in our SOT-PBNN system cannot be performed using a fixed-value resistor. Instead, to enable on-chip current comparison, we allocated an additional [2 \(\times\) n] dummy cell corresponding to the [m \(\times\) n] MRAM array cell. As a result, the binarization is achieved by writing \(R_{\text{AP}}\) and \(R_{\text{P}}\) into two MRAM devices along the same column of the dummy cell, and then determining the resistance state of a single MRAM using half of the summed currents under the same read voltage. The overview of the integrated SOT-MRAM PBNN chip is shown in Fig. 15.

As a proof-of-concept, the VMM operation was validated experimentally in a [16 \(\times\) 1] array. Specifically, after all 16 serial-connected SOT-MRAM devices were initialized in the anti-parallel state (_i.e._, weight assignment), the accumulated current (\(I_{\text{out}}\)) measured at the output port is highly consistent with the ideal value (\(I_{\text{sum}}=\sum_{i=1:6}I_{\text{so},i}\)) under different read voltages (Fig. 16). It is also noted that with a maximum read voltage of 0.54 V, the average output current variation is only 4.31%, again demonstrating the low read error of our SOT-MRAM devices. Concurrently, the on-chip comparator function was evaluated from 9 randomly selected devices. Although the difference between \(R_{\text{P}}\) and \(R_{\text{AP}}\) becomes narrower as the read voltage increases, the reference resistance \(R_{\text{ref}}\) of the dummy cell is continuously kept within the resistance gap, hence verifying a wide operating range of the SOT-MRAM dummy cell (Fig. 17). Finally, we selected an 8-level activation quantization and 3-level weight quantization for handwritten digit recognition. After transferring the weight values to MRAM, we conducted inference using the MNIST dataset. From the measured and simulated results in Fig. 18, it is seen that the inference currents distributions share the same feature versus the assigned weight information, therefore yielding the correct digit judgement. Based on the inference results after 100 training sessions, we have obtained an on-chip classification accuracy over 90% in our integrated SOT-PBNN chip (Fig. 19).

## IV Conclusion

Compared with other memristive devices and neural networks, the SOT-MRAM-enabled PBNN elaborated in this work shows advantages including long endurance, stable states, fast training, and robustness against input variations (Table 1). Our work provides a compelling framework for the design of reliable neural networks for low-power applications with limited computational resources.

## Acknowledgment

This work is supported by the National Key R&D Program of China (2021YFA0715503), the NSFC Programs (11904230, 62004013), the Shanghai Rising-Star Program (21QA1406000), and the Young Elite Scientists Sponsorship Program by CAST (2021QNRC001).
