The Sparsity Roofline: Understanding the Hardware Limits of Sparse
  Neural Networks
We introduce the Sparsity Roofline, a visual performance model for evaluating
sparsity in neural networks. The Sparsity Roofline jointly models network
accuracy, sparsity, and theoretical inference speedup. Our approach does not
require implementing and benchmarking optimized kernels, and the theoretical
speedup becomes equal to the actual speedup when the corresponding dense and
sparse kernels are well-optimized. We achieve this through a novel analytical
model for predicting sparse network performance, and validate the predicted
speedup using several real-world computer vision architectures pruned across a
range of sparsity patterns and degrees. We demonstrate the utility and
ease-of-use of our model through two case studies: (1) we show how machine
learning researchers can predict the performance of unimplemented or
unoptimized block-structured sparsity patterns, and (2) we show how hardware
designers can predict the performance implications of new sparsity patterns and
sparse data formats in hardware. In both scenarios, the Sparsity Roofline helps
performance experts identify sparsity regimes with the highest performance
potential.
Cameron Shinn, Collin McCarthy, Saurav Muralidharan, Muhammad Osama, John D. Owens
# The Sparsity Roofline: Understanding the Hardware Limits of Sparse Neural Networks

###### Abstract

We introduce the Sparsity Roofline, a visual performance model for evaluating sparsity in neural networks. The Sparsity Roofline jointly models network accuracy, sparsity, and theoretical inference speedup. Our approach does not require implementing and benchmarking optimized kernels, and the theoretical speedup becomes equal to the actual speedup when the corresponding dense and sparse kernels are well-optimized. We achieve this through a novel analytical model for predicting sparse network performance, and validate the predicted speedup using several real-world computer vision architectures pruned across a range of sparsity patterns and degrees. We demonstrate the utility and ease-of-use of our model through two case studies: (1) we show how machine learning researchers can predict the performance of unimplemented or unoptimized block-structured sparsity patterns, and (2) we show how hardware designers can predict the performance implications of new sparsity patterns and sparse data formats in hardware. In both scenarios, the Sparsity Roofline helps performance experts identify sparsity regimes with the highest performance potential.

## 1 Introduction

Deep neural networks are often over-parameterized (Howard et al., 2019; Tan and Le, 2019) and their weights or parameters can be eliminated (_pruned_) to improve inference latency and/or decrease network size (LeCun et al., 1989; Han et al., 2015; Molchanov et al., 2017; Zhu and Gupta, 2018) without affecting accuracy. Depending on the _pattern_ and _degree_ of sparsity, which together constitute a _sparsity configuration_, networks exhibit widely different accuracy and runtime behavior. This presents major problems for machine learning practitioners who wish to find the best sparsity pattern and degree that balances accuracy loss and performance constraints for their specific application. Obtaining the accuracy corresponding to a sparsity pattern and degree typically requires some form of network fine-tuning (Frankle and Carbin, 2019), making it highly inefficient to estimate the impact of different sparsity configurations by trying hundreds of combinations of hyperparameters.

Thus we hope to predict which sparsity combinations might be most fruitful without fine-tuning them all. But accurately estimating the effects that a specific sparsity configuration has on inference runtime poses a different set of challenges: (1) which metric should we use to estimate runtime performance, and (2) how do we obtain the runtime performance of sparsity patterns that are either unimplemented or have unoptimized implementations? To illustrate the challenge of identifying the right metric, consider the total floating point operations (FLOPs) performed during sparse matrix operations such as matrix multiplication (a common operation in neural networks (Chetlur et al., 2014)). FLOPs are frequently used to evaluate the performance of pruned models (Han et al., 2015; Molchanov et al., 2017; Zhu and Gupta, 2018; Frankle and Carbin, 2019; Lee et al., 2019; Hoefler et al., 2021; Blalock et al., 2020). Table 1 illustrates the limitations of this metric. Here, we show two weight matrices that provide a counterexample to the notion that FLOPs are positively correlated with measured runtime. The structured weight matrix shown on the left side of the table has 1.57\(\times\) more FLOPs than the unstructured matrix on the right, but runs nearly 6\(\times\) faster.

Addressing the challenge of _estimating_ optimized runtime performance is even harder. While performance experts have implemented computation kernels specifically targeting sparse neural networks (Gale et al., 2020; Sarkar et al., 2020; Chen et al., 2021; Vooturi and Kothapalli, 2019), there are significant gaps. For example, NVIDIA's cuSparse library provides optimized GPU kernels for block-sparse matrices, but they are primarily optimized for larger block sizes such as 16\(\times\)16 and 32\(\times\)32 (Yamaguchi and Busato, 2021).

As discussed in Section 4.1, using smaller block sizes often leads to higher accuracies; however, in the absence of computation kernels optimized for these sizes, it is impossible
to estimate their effect on runtime via benchmarking.

To help practitioners better understand the complex relationship between sparsity configuration, accuracy, and inference performance (both current and potential), we introduce a novel visual model named the _Sparsity Roofline_. Our work builds upon the well-known Roofline model (Williams et al., 2009), which provides a visual representation of the performance of a given computation kernel.

In the Roofline model, users compute the _arithmetic intensity_ of the given kernel, and plot it against one or more hardware-specific upper limits (the Rooflines) defined by the peak memory bandwidth and peak floating-point throughput of that hardware architecture. In a similar vein, the Sparsity Roofline plots network accuracy against the theoretical speedup of sparse over dense models, with additional sparsity information. This clearly shows the two most important aspects of weight pruning to a machine learning practitioner--accuracy and performance--and can be analyzed across any model architecture, sparsity hyperparameters, or hardware accelerator. Plotting the Sparsity Roofline requires sampling the accuracy values corresponding to the sparsity configurations being analyzed, which can be easily done with masking-based approaches and existing software libraries (Paszke et al., 2019; Joseph et al., 2020). The only other metrics needed are the arithmetic intensity, which can be either profiled or computed by hand, and the hardware-specific peak computational throughput (in FLOPs/s) and memory bandwidth (in bytes/s).

We validate and demonstrate the usefulness of the Sparsity Roofline by analyzing several real-world computer vision models, including convolutional neural networks (CNNs), vision transformers (ViT), and multi-layer perceptron (MLP)-based networks. We investigate which sparsity characteristics have the greatest impact on accuracy and GPU performance, and point out promising areas to focus on for kernel optimization. Finally, we present two case studies: (1) analyzing tradeoffs associated with block-structured sparsity for deep learning practitioners, and (2) efficient sparsity patterns for future hardware architectures.

This paper makes the following contributions:

1. It introduces the Sparsity Roofline visual model for understanding accuracy vs. latency trade-offs for currently unoptimized and unimplemented kernel designs.
2. It uses the Sparsity Roofline to benchmark and analyze several real-world computer vision architectures pruned to a range of sparsity patterns and levels.
3. It demonstrates the use of the Sparsity Roofline in two distinct use cases: to analyze block-sparsity structures for DL practitioners, and to help inform future sparse hardware implementations.

## 2 Background

In this Section, we provide a brief overview of neural network pruning, followed by a description of the traditional Roofline model.

### Neural Network Pruning

Weight pruning involves setting a subset of neural network weights to zero, followed by a training or fine-tuning stage that attempts to recover any lost accuracy (Hoefler et al., 2021). Pruning can be unstructured (fine-grained), where individual non-zero values are eliminated, or structured (coarse-grained), where groups of non-zero values are removed instead, each resulting in a different _sparsity pattern_. The _sparsity level_ refers to the fraction of zero weights to total weights and is expressed as a percentage in this paper. Structured pruning has been demonstrated to achieve better runtime performance, typically at the cost of decreased accuracy (Narang et al., 2017; Vooturi et al., 2018; Li et al., 2022). A number of algorithms have been proposed in the literature for accuracy recovery of pruned models (Deng et al., 2021; Renda et al., 2020; Hoefler et al., 2021). In this paper, we use the learning rate rewinding approach proposed by Renda et al. (2020).

### The Roofline Model

The Roofline model (Williams et al., 2009) is a visual performance model that shows how well a computational kernel

\begin{table}
\begin{tabular}{c c c} \hline \hline Matrix Heatmap & & \\ \hline
**Runtime (ms)** & **6.613** & **3.526** \\
**GFLOPs** & **24.4** & **15.5** \\ TFLOPs/s & 39.9 & 4.4 \\ Number of Nonzeros & 1.95M & 1.23M \\ \(m\times k\)-dimensions & & \\ (sparse operand) & 3072\(\times\)768 & 3072\(\times\)768 \\ \(n\)-dimension & & \\ (dense operand) & 6272 & 6272 \\ \hline \hline \end{tabular}
\end{table}
Table 1: **Runtime vs. GFLOPs: SpMM performance on (32\(\times\)32) block sparsity vs. unstructured with a similar amount of nonzeros. White indicates zero-valued weights, blue non-zero. The block sparse matrix has more FLOPs but has a nearly 6\(\times\) better runtime latency vs. unstructured.**
utilizes the hardware. The Roofline model plots the arithmetic intensity (FLOPs computed / bytes read and written) on the x-axis and the throughput (FLOPs per second) on the y-axis. This enables users to visually observe if their program is memory-bound or compute-bound, and to what extent. The upper bound (Roofline) of the model is determined by both the hardware's peak compute throughput and peak memory bandwidth. Although there are variants that consider cache hierarchies (Ilic et al., 2014), the traditional Roofline model that we discuss in this paper assumes perfect caching is necessary (including user-managed caching such as shared memory and local registers) to achieve peak memory bandwidth utilization; we thus use DRAM memory bandwidth. The hardware throughput component can be increased with additional hardware acceleration for a specific application (e.g., Tensor Cores for deep learning (Jia et al., 2018)). The utility of the Roofline model comes from its ability to succinctly show potential improvement for a given program with respect to the hardware speed-of-light.

### Evaluating Sparse Neural Networks

Figure 1 plots the Roofline for individual SpMM matrices across all  benchmarked computer vision models. The line in each plot is the "Roofline", which slopes upwards during the memory-bound region where the arithmetic intensity (AI) is too low to saturate the compute resources, and flattens out once the AI reaches a hardware-specific point, called the _knee_. The dashed line is for Tensor Cores and the solid line for CUDA cores, where the Tensor Core knee has almost 10x the AI of CUDA cores.

The points that are closest to the Roofline are utilizing the GPU the best, with higher sparsities being more memory bound and lower sparsities approaching and becoming compute bound in some situations, such as when the inner-dimension of the matrix product is higher. The Roofline model is a significant improvement over analyzing FLOPs, but it has three major drawbacks in optimizing sparse deep learning models:

1. The Roofline model lacks any concept of accuracy, and GFLOPs/s is challenging to use to compare the relative performance between sparse and dense layers.
2. The Roofline model is only meaningful per-layer instead of per-model. An entire model is almost always a combination of layers, where some are memory-bound and others are likely compute-bound. Therefore calling the entire model "compute bound" or "memory bound" is misleading at best.
3. The Roofline model requires benchmarking to compute GFLOPs/s. Even if optimal kernels exist, such as cuBLAS for dense GEMM operations, the surrounding benchmarking framework is time-consuming to implement, test, and maintain.

Our proposed solution, the Sparsity Roofline, directly addresses these concerns. It is not meant to replace the Roofline model, but instead _complement_ it for the specific use case of designing and optimizing sparse deep-learning kernels.

## 3 The Sparsity Roofline

The Sparsity Roofline is designed to be an easy-to-use tool for deep learning practitioners interested in sparsity, performance experts, and hardware designers. It achieves this goal by addressing the three major issues with the existing Roofline model described in Section 2.3.

The Sparsity Roofline plots accuracy vs. theoretical speedup, as opposed to the traditional Roofline's GFLOPs/s vs. arithmetic intensity. Accuracy is almost always the most important optimization metric in DNNs, and therefore we place it on the \(y\) axis. Similarly, replacing GFLOPs/s with theoretical speedup makes it far easier to understand relative performance differences of a sparse and dense layer or model. Further, the sparsity configuration is encoded into the point and/or line style in order to easily compare different sparsity design decisions, which are crucial for optimal performance.

The Sparsity Roofline converts per-layer peak GFLOPs/s to per-model minimum or _speed-of-light_ (SoL) latency. We first calculate a per-layer SoL latency, then sum the layer-wise latencies for the model SoL latency. This represents

Figure 1: **Roofline, Sparse vs. Dense**: Roofline model measuring throughput of SpMM on unstructured sparse layers and GEMM on dense layers from all  trained models, on a single NVIDIA A100. The solid line is the CUDA core peak throughput, the dashed line the Tensor core peak throughput. Unstructured sparsity kernels in cuSPARSE do not use Tensor cores.
the true performance metric that practitioners care about: end-to-end latency of the entire model.

Like the traditional Roofline, the Sparsity Roofline does not require benchmarking. We only need to look up the hardware peak GFLOPs/s and peak GB/s of a hardware architecture, and compute the per-layer GFLOPs and GBs read/written by hand in order to calculate arithmetic intensity.

The Sparsity Roofline for unstructured sparsity is shown in Figure 2, and for ConvNeXt-Tiny and Swin-Tiny in Figures 3 and 4, respectively. We will now describe how these Sparsity Rooflines are constructed.

Given our model uses accuracy metrics, the model being used in the Sparsity Roofline needs to be fine-tuned to a given sparsity from a pre-trained dense model. Fine-tuning for sparsification is a standard practice in deep learning, and the only way to quantify accuracy. We use the learning-rate rewinding technique proposed by Renda et al. (2020) and the Condensa library by Joseph et al. (2020). Our model is most accurate when the sparse kernels are well optimized, and thus approaching the speed-of-light. This doesn't mean the sparse kernel needs to be compute bound, but if it is memory bound the closer it is to the device peak memory throughput, the more accurate our model is. This is discussed in detail in Section 3.4.

### Use Cases

The Sparsity Roofline is designed to quantify the performance-accuracy tradeoff for a specific combination of hardware, model architecture and sparsity configuration, such as sparsity pattern, sparsity level or percent, and sparse data format. Thus it can be used by both software and hardware engineers who want to understand how an optimized kernel would perform, but do not want to go through the trouble of implementing and benchmarking sub-optimal scenarios. In Section 4.1, we show how a deep-learning practitioner may use this tool to investigate optimal block-structure sparsity patterns, and in Section 4.2 we show how a hardware engineer can investigate different N:M sparsity patterns and sparse data formats to implement in hardware, e.g., for new sparse Tensor core formats.

In contrast, the Sparsity Roofline is not meant for engineers who already have a specific sparsity-configuration optimization target. In that scenario, a combination of the Roofline model, benchmarking / profiling, and lower-level optimizations are likely the correct tools to understand detailed performance statistics that would inform kernel design, such as load balancing and caching.

### Constructing the Sparsity Roofline

The Sparsity Roofline plots accuracy vs. theoretical speedup from sparsity. We start by deriving the theoretical speedup.

First, we need to define the kernel's GFLOPs and GBs read/written to global memory. Equation 1 shows this for SpMM (\(\text{Sparse}\times\text{Dense}=\text{Dense}\) matrix multiply); the index data depends on the sparse data format. For compressed row format (CSR), it is \(\textit{nnz}+m+1\).

\[\begin{split}\text{SpMM FLOPs}&=\textit{nnz}\times n \\ \text{SpMM GB}&=\textit{nnz}+n\times k+m\times n+ \text{index data}\end{split} \tag{1}\]

Next, we define the per-layer speed-of-light latency as the maximum runtime for the kernel's given GFLOPs and GBs read/written to global memory. Using the device's peak GFLOPs and GB/s, this is computed as

\[\text{Per-Layer SoL}=\text{max}\bigg{(}\frac{\text{GFLOP}}{\text{ Peak GFLOP/s}},\frac{\text{GB}}{\text{Peak GB/s}}\bigg{)} \tag{2}\]

Finally, we sum the \(L\) per-layer runtimes for the dense model and the same corresponding sparse model, and take their runtime ratio as the speedup, using the dense computation as the baseline. For example, if the sparse latency is 1 ms and the dense latency is 2 ms, the speedup would be 2x.

Figure 2: **Per-Model Sparsity Roofline**: The Sparsity Roofline for several computer vision models on ImageNet-100 pruned with global magnitude pruning. Speedup is calculated per-layer using the maximum compute or memory bound latency, and then summed per model. The machine learning engineer can choose the architecture that provides the optimal balance of accuracy, speedup, and implementation difficulty.
\[\text{Speedup at SoL}=\frac{\sum_{l=1}^{L_{\text{dense}}}\text{SoL Runtime}_{l}}{ \sum_{l=1}^{L_{\text{dense}}}\text{SoL Runtime}_{l}} \tag{3}\]

These equations make the same assumption as the Roofline model: the maximum achievable FLOPs/s is the hardware's peak compute throughput, and each byte of data may be read from or written to global memory once, at the hardware's peak memory throughput, with perfect caching (including shared memory or local registers) for any intermediate reads.

### Evaluating Accuracy

To compute accuracy for each model and sparsity configuration, we start by pre-training one baseline model per architecture. We pre-train without sparsity for 300 epochs on ImageNet-100 (Vinyals et al., 2016). This dataset is a subset of the ImageNet-1K dataset (Deng et al., 2009) created by sampling 100 of the 1000 classes in ImageNet-1K, which allows us to train a larger number of models, sparsity patterns, and sparsity levels.

All model definitions are from the _timm_ library (Wightman, 2019) and each is trained with the same set of data augmentations, hyperparameters, and training schedules based on modern architectures such as DeiT (Touvron et al., 2021), Swin (Liu et al., 2021) and ConvNeXt (Liu et al., 2022). This includes data augmentations RandAugment (Cubuk et al., 2020), MixUp (Zhang et al., 2018) and CutMix (Yun et al., 2019), a cosine decay learning rate schedule (Loshchilov and Hutter, 2017), and the AdamW optimizer (Loshchilov and Hutter, 2019) with a base learning rate of \(10^{-3}\) and 20 epochs of warm up. Using these uniform settings across all models ensures a fair comparison with an identical training procedure. We store the checkpoint with the minimum validation loss and use this for fine-tuning.

We apply an incremental fine-tuning algorithm based on learning rate rewinding (Renda et al., 2020) to the baseline model to obtain the accuracy values corresponding to the following sparsity levels: 50%, 75%, 87.5%, 93.75% and 96.875%. This pattern involves halving the number of nonzeros per iteration, which ends up slightly biasing the results towards higher sparsities where sparse kernels are typically more performant.

For a given combination of model and sparsity pattern, e.g., ConvNeXt-Tiny with unstructured sparsity, we prune the weights with global magnitude pruning to the lowest sparsity level of 50%. We rewind the learning rate schedule but with a shorter 60 epoch total decay rather than 300 epochs. After 60 epochs we increase the sparsity level by \((1-\text{Sparsity})/2\), prune the additional weights, and rewind the learning rate again. We repeat this a total of five times within a single run to fine-tune five sparsity levels for our model / sparsity pattern combination in 300 epochs total, which is the same number as during training. We find this process to be simple and efficient, and quantitatively works well for ImageNet-100. For more challenging datasets such as ImageNet-1k or ImageNet-22k, the fine-tuning schedule would likely need to be increased.

### Validation

It is important to understand the cases where speed-of-light (SoL) speed-up equals the actual measured speed-up, without having to implement and optimize a specific sparse kernel. We can easily show that the speedup at SoL is precisely equal to the measured speed-up when the sparse and dense kernels are _equally optimized_. Specifically, at a per-layer level this occurs when the percentage of the per-layer SoL latency for dense and sparse are equal. For example, if a given GEMM kernel is compute bound and obtains 90% of the SoL GFLOPs/s, and the corresponding SpMM kernel is memory bound and also obtains 90% of the SoL GB/s, then the percent of SoL is identical and our model will predict a SoL speedup that is equal to the measured speedup. More formally:

\[\text{Per-Layer Speedup at SoL} \stackrel{{?}}{{=}}\text{Per-Layer Speedup Meas.}\] \[\frac{\text{Dense SoL Runtime}}{\text{Sparse SoL Runtime}} =\frac{\text{Dense Meas. Runtime}}{\text{Sparse Meas. Runtime}}\] \[\frac{\text{Dense SoL Runtime}}{\text{Dense Meas. Runtime}} =\frac{\text{Sparse SoL Runtime}}{\text{Sparse Meas. Runtime}}\]

Dense Per-Layer % of SoL

In the last equation, note that the percent of speed-of-light (or fraction of speed-of-light) is defined as the ratio between the SoL latency to the measured latency. The measured latency can take on values as small as the SoL latency but no smaller, by definition. Therefore this is bounded between 0-1 (or 0-100%).

The same equation holds for per-model aggregation, but in this case each individual term is a summation of all layers.

\[\text{Per-Model Speedup at SoL} \stackrel{{?}}{{=}}\text{Per-Model Speedup Meas.}\] \[\frac{\sum_{l=1}^{L_{\text{dense}}}\text{SoL Runtime}_{l}}{\sum_{l= 1}^{L_{\text{dense}}}\text{Meas. Runtime}_{l}} =\frac{\sum_{l=1}^{L_{\text{dense}}}\text{SoL Runtime}_{l}}{\sum_{l= 1}^{L_{\text{dense}}}\text{Meas. Runtime}_{l}}\]

Dense Per-Model % of SoL \(=\text{Sparse Per-Model }\%\) of SoL

At the aggregated per-model level, the SoL speedup is equal to the measured speedup when the sparse and dense models are equally optimized, such that the percentage of the per-model SoL latency for dense and sparse are equal.
## 4 Case Study

### DL Practitioner

Suppose Alice is researching pruning algorithms and wants to find out whether block sparsity can provide effective inference latency improvements on NVIDIA GPUs for ConvNext () and Swin (), two state-of-the-art computer vision models. She would typically start by training, pruning and then fine-tuning these models for various block sizes, say, 2\(\times\)2, 4\(\times\)4, 8\(\times\)8, 16\(\times\)16 and 32\(\times\)32, to capture a sufficiently large sample of the search space.

Alice would like to compare the speedups that her block pruning scheme achieves w.r.t. unstructured global magnitude pruning, but she would prefer to avoid implementing a custom block-sparse GPU kernel until she is sure it's the right approach. She then considers using existing kernels from a vendor-optimized library such as cuSparse (), but backs off due to two reasons: (1) writing a custom operator for a deep learning framework is not trivial, and (2) she notices in the documentation for the vendor-optimized library that it achieves poor performance for smaller block sizes, and may thus not provide a fair comparison across block sizes.

Rather than trying to measure actual latency numbers, Alice now plans to use some simple metrics to estimate potential speedups. She starts by counting the FLOPs of each sparse model. However, since her blocked SpMM and unstructured SpMM kernels would be running on NVIDIA Tensor Cores and CUDA cores, respectively, the former will end up achieving higher throughput than the latter. Additionally, since Tensor Cores necessitate more efficient memory bandwidth utilization, she would also need to account for the reads and writes that her sparse models perform during inference.

To address the above concerns, Alice instead generates the Sparsity Roofline for the block-sparse models she has trained to quickly approximate the speedups she would achieve for various block sizes. Figures 3a and 3b show the Sparsity Roofline models Alice would generate for ConvNext and Swin with a batch size of 1. By observing the accuracy and performance tradeoffs that the Sparsity Roofline depicts, Alice is now able to determine that her models achieve higher speedups using larger block sizes, but they only maintain accuracy with smaller block sizes of 2\(\times\)2 and 4\(\times\)4. _Importantly, Alice was able to arrive at this conclusion without needing to go to the effort of writing her own optimized sparse kernels for a variety of block sizes._ She now realizes that if she invests her time in optimizing for smaller block sizes, she will get reasonable speedups without sacrificing accuracy.

### Hardware Architect

Bob is a hardware architect designing next-generation Tensor Cores for future GPUs and is investigating alternative N:M patterns for future hardware support. He would like to quickly assess the accuracy and performance implications of the new N:M patterns before he puts in any effort into design and simulation. His goal is to find patterns that achieve accuracy numbers similar to the currently supported 2:4 pattern, but are at least 30% faster given the same Tensor Core throughput.

Bob's target workload for these N:M patterns is inference with a batch size of 1 on ConvNeXt and Swin. These two network architectures, in addition to providing state-of-the-art accuracies on their tasks, are also comprised of a variety of layer types, and involve matrix operations of various shapes and sizes, making them fairly representative. The N:M schemes he chooses to investigate are 1:4, 2:8 and 2:16, in addition to the pre-existing 2:4 pattern.

Bob works with a machine learning engineer to get these two networks trained, pruned, and fine-tuned for each of the above sparsity patterns, and then obtains the corresponding accuracy numbers. He now needs to determine how these models would perform if hardware support for the new N:M patterns was available.

Instead of developing RTL code for these new hardware units and simulating the workloads, which would be labor-intensive and time-consuming, Bob would prefer a quicker way of estimating the runtime performance of each of these pruned models on their respective hypothetical hardware units. Bob could simply use FLOPs to estimate speedups for each pattern (e.g., going from 2:4 to 1:4 is a 2x speedup); however, note that Bob would also need to account for the memory system's ability to keep up with the Tensor Core's throughput to get a more accurate performance estimation.

To address these concerns, Bob constructs the Sparsity Roofline for the N:M pruned models to quickly estimate the speedups he would achieve w.r.t. the accuracy. The resulting Sparsity Roofline plots are shown in Figures 4a and 4b. From the Sparsity Roofline, Bob notices that at the same Tensor Core throughput, 2:16 sparsity achieves nearly a 1.8\(\times\) speedup over dense and is over 30% faster than the 2:4 sparsity pattern, meeting his original goal. He also notices that the 1:4 and 2:8 patterns are promising in cases where accuracy preservation is more important than raw speedup. Similar to Alice (see Section 4.1), Bob was able to estimate his performance metrics significantly faster using the Sparsity Roofline.
## 5 Discussion

### Unstructured Sparsity

Global magnitude pruning with re-training has become a widely applicable technique due to its simplicity and effectiveness. Figure 5 shows how this technique can reach almost 90% sparsity with minimal accuracy loss. In the context of small computer vision models, Figure 2 indicates that accuracy can only be preserved to about a \(1.5\times\) speedup over dense. While a 50% speedup would be somewhat substantial, the time cost of fine-tuning may not be worthwhile in every scenario. Additionally, a 50% speedup is far less than what FLOP counts would suggest. At 87.5% sparsity, a network requires only \(1/8\) the FLOPs of the original, yet Figure 2 tells us that a \(8\times\) speedup is infeasible in any case. To make sparsity generally viable from a performance perspective, we need to understand and alleviate the underlying factors that inhibit SpMM from achieving the speedups suggested by the FLOP reduction. Despite the wide range of factors that affect SpMM kernel performance on GPUs, such as load balancing and efficient data reuse Gale et al. (2020); Bell and Garland (2009), we only consider the factors that make up the Sparsity Roofline. Thus, in our analysis, we account for FLOPs, bytes read/written, hardware peak throughput, and hardware peak memory bandwidth (the same as the Roofline model).

One of the most glaring downsides of unstructured sparsity is its inability to leverage the GPU's tensor cores that are effectively leveraged by dense models.1 The Roofline model

Figure 4: **N:M Sparsity Roofline: The Sparsity Roofline for (a) ConvNext-Tiny and (b) Swin-Tiny on ImageNet-100 pruned with various N:M patterns. Calculations are done using a batch size of 1 and NVIDIA A100 hardware specs.**

Figure 3: **Block-Sparsity Roofline: The Sparsity Roofline for (a) ConvNext-Tiny and (b) Swin-Tiny on ImageNet-100 pruned with various block pruning sizes. Calculations are done using a batch size of 1 and NVIDIA A100 hardware specs.**
in figure 1 shows the elevated peak tensor core throughput above the peak CUDA core throughput. For the A100, the tensor core throughput is 16x faster than the CUDA core throughput (NVIDIA, 2020). To address the hardware discrepancy and put sparse and dense on a level playing field, we opt to investigate sparsity structures that can leverage the tensor cores.

### Block Sparsity

The Sparsity Roofline shows two benefits of block sparsity: (1) the ability to use the high-throughput sparse tensor cores, and (2) the reduced index data from the block sparse format. The reduced index data results from the sparsity pattern's more coarse-grained structure, where a single block index refers to multiple nonzeros. The index data is reduced by a factor of the block size.

Despite the reduction in reads and writes from block sparsity, Figure 6 shows that the vast majority of block-pruned weights are still memory bound. Because of this, the Sparsity Rooflines for different block sizes in figure 2(a) and figure 2(b) see only a small improvement compared to unstructured sparsity. The accuracy-speedup tradeoff is slightly better than unstructured sparsity at best, and only just as good in the worst case.

While the heatmap in Table 1 suggests that block sparsity should perform much better than unstructured, we observe that the accuracy loss from large block sizes (16\(\times\)16 and 32\(\times\)32) is too significant to be viable. When we therefore restrict our analysis to smaller block sizes, we see that we can't achieve the full throughput from the tensor cores due to the memory bottleneck seen in Figure 6. The smaller block sizes are completely memory-bound, whilst the larger block sizes are less so, and can thus get more throughput from the tensor cores.

### N:M Sparsity

NVIDIA's sparse tensor cores provide an interesting alternative to block sparsity, allowing adopters to leverage the throughput of the tensor cores whilst being able to prune weights in a fine-grained manner. While the coarse-grained structure of block sparsity restricts the freedom of pruning algorithms' weight selection and hurts accuracy, the fine-grained structured sparsity for the N:M patterns should theoretically hurt accuracy less.

In addition to the accuracy benefits of a fine-grained structure, the N:M formats can reduce the memory overhead for indexing data. With dedicated hardware support, N:M formats only need \(\log_{2}(M)\) bits to store the index of each nonzero inside the \(M\)-wide blocks; for 2:4, that's only 2 bits per nonzero.

Figures 3(a) and 3(b) show the Sparsity Roofline for N:M formats. We see that the various N:M patterns achieve a better performance-accuracy tradeoff over unstructured than what

Figure 5: **Accuracy vs. Sparsity and FLOPs: A common but misleading means of evaluating sparse models. Plotting accuracy (here ImageNet-100 top-1 accuracy) vs. sparsity (top) and FLOPs (bottom) for various models implies higher sparsity means higher GPU performance, which does not take memory bandwidth into account.**

Figure 6: **Roofline, Block Sparse vs. Dense: Roofline model measuring throughput of SpMM on all block sparse layers and GEMM on dense layers from all trained models, on a single NVIDIA A100.**
block sparsity was able to achieve. N:M is an improvement over block sparsity in our pruned networks due to the reduced accuracy degradation and minimal index data overhead.

### Feature Overhead

Finally, we have not yet mentioned the read and write overhead of the input and output features of each layer. Equation 1 shows the data for the input and output features as \(n\times k\) and \(m\times n\) (respectively). Akin to Amdahl's law, we can only expect to reduce the number of memory accesses for pruned matrices. Therefore, regardless of our pruning strategy, the input and output features will always incur a fixed number of reads and writes as overhead. Figure 7 shows the severity of this problem. For a batch size of 1, the feature memory accesses, which cannot be reduced via pruning, account for half of all accesses. For a batch size of 32, the feature memory accesses heavily dominate the overall number of accesses, making it difficult to decrease the memory bottleneck of our sparse models.

The \(n\) dimension in equation 1 is shared by the input and output feature matrices and is not one of the weight matrix dimensions. The size of \(n\) relative to \(m\) and \(k\) is determines the appearance of the graphs in Figure 7. The \(n\) dimension scales linearly with both the batch size and the number of spatial locations in the feature data (for both convolution and transformer FFN layers). This suggests that we will see larger speedups from pruning when the model size (\(m\) and \(k\)) is large relative to the batch size and feature sizes (\(n\)).

## 6 Related Work

Automated Model CompressionRecent work has explored various approaches for automatically inferring optimal sparsity levels using approaches such as Bayesian Optimization (Joseph et al., 2020) and reinforcement learning (He et al., 2018). Our work differs in two ways: we focus on providing (1) a _visual_ representation of the accuracy and performance landscape for different sparsity patterns and levels, and (2) meaningful estimates of potential inference runtimes to aid deep learning practitioners, performance experts and hardware designers.

Deep Learning Roofline ModelsThe Roofline model has been applied to the deep learning problem space in the past (Yang et al., 2020; Wang et al., 2020; Czaja et al., 2020). However, this work primarily focuses on dense neural networks. Specifically, Wang et al. (2020) extend the Roofline model to deep learning by using latency and compute/bandwidth complexity. Yang et al. (2020) provide a toolkit extension for deep learning to support new precisions, tensor cores, and a tool for measuring performance metrics. Czaja et al. (2020) perform a Roofline analysis of DNNs accounting for non-uniform memory access (NUMA) systems.
