Evaluation of Convolution Primitives for Embedded Neural Networks on
  32-bit Microcontrollers
Deploying neural networks on constrained hardware platforms such as 32-bit
microcontrollers is a challenging task because of the large memory, computing
and energy requirements of their inference process. To tackle these issues,
several convolution primitives have been proposed to make the standard
convolution more computationally efficient. However, few of these primitives
are really implemented for 32-bit microcontrollers. In this work, we collect
different state-of-the-art convolutional primitives and propose an
implementation for ARM Cortex-M processor family with an open source deployment
platform (NNoM). Then, we carry out experimental characterization tests on
these implementations. Our benchmark reveals a linear relationship between
theoretical MACs and energy consumption. Thus showing the advantages of using
computationally efficient primitives like shift convolution. We discuss about
the significant reduction in latency and energy consumption due to the use of
SIMD instructions and highlight the importance of data reuse in those
performance gains. For reproducibility purpose and further experiments, codes
and experiments are publicly available.
Baptiste Nguyen, Pierre-Alain Moellic, Sylvain Blayac
# Evaluation of Convolution Primitives for Embedded Neural Networks on 32-bit Microcontrollers

###### Abstract

Deploying neural networks on constrained hardware platforms such as 32-bit microcontrollers is a challenging task because of the large memory, computing and energy requirements of their inference process. To tackle these issues, several convolution primitives have been proposed to make the standard convolution more computationally efficient. However, few of these primitives are really implemented for 32-bit microcontrollers. In this work, we collect different state-of-the-art convolutional primitives and propose an implementation for ARM Cortex-M processor family with an open source deployment platform (NNoM). Then, we carry out experimental characterization tests on these implementations. Our benchmark reveals a linear relationship between theoretical MACs and energy consumption. Thus showing the advantages of using computationally efficient primitives like shift convolution. We discuss about the significant reduction in latency and energy consumption due to the use of SIMD instructions and highlight the importance of data reuse in those performance gains. For reproducibility purpose and further experiments, codes and experiments are publicly available1.

Footnote 1: [https://gitlab.emse.fr/b.nguyen/primitive_of_convolution](https://gitlab.emse.fr/b.nguyen/primitive_of_convolution)

Keywords:Deep Learning Architecture optimization Embedded systems Convolutional neural network.

## 1 Introduction

The demand for edge inference is growing and neural networks are prime candidates due to their success across a large variety of application domains. However, state-of-the-art deep neural network models, especially convolution neural networks, require a large amount of memory and computational resources. For example, the standard ResNet-18 model [3] for image classification on ImageNet
has around 11M parameters and requires approximately 1 GMACs for an inference which is prohibitive for ARM Cortex-M microcontrollers. Thus, designing efficient neural network architectures is a major topic in the embedded AI community. In the search for efficient neural network architectures, several alternatives to convolution have been proposed, but few of them are practically implemented on deployment libraries for 32-bit microcontrollers. This work focuses on the implementation and characterization of state-of-the-art convolution primitives for ARM Cortex-M MCUs. **Our contributions are as follow:**

* We implement three state-of-the-art convolution primitives for ARM Cortex-M MCUs and when possible, we propose another implementation which makes use of the SIMD1 instructions (_Single Instruction, Multiple Data_). Footnote 1: [https://www.keil.com/pack/doc/CMSIS/Core/html/group__intrinsic__SIMD__gr.html](https://www.keil.com/pack/doc/CMSIS/Core/html/group__intrinsic__SIMD__gr.html)
* We characterize the latency and energy consumption of five primitives, including the standard convolution, against different parameters such as kernel or input size.
* We provide insights on the performance of different primitives, especially for our implementations using SIMD instructions to help machine learning practitioners to design, develop and deploy efficient models according to their requirements.

## 2 Background

### Preliminaries and notation

We consider the typical case of a 2D-convolution layer with padding and a square input tensor \(X\) of dimensions of \(H_{x}\times H_{x}\times C_{x}\) with \(H_{x}\) the spatial width and \(C_{x}\) the number of channels. The convolution layer produces an output tensor \(Y\) of dimensions \(H_{y}\times H_{y}\times C_{y}\) with \(H_{y}\) the spatial width (equal to \(H_{x}\)) and \(C_{y}\) the number of channels. The convolution is performed thanks to convolutional kernels represented by a weight tensor \(W\) of size \(H_{k}\times H_{k}\times C_{x}\times C_{y}\) with \(H_{k}\) the spatial dimension of a kernel (assumed to be square), \(C_{x}\) the number of input channels and \(C_{y}\) the number of output channels (i.e. the number of filters) as defined previously. The output for standard convolution is as follows:

\[Y_{k,l,n}=\sum_{m=1}^{C_{x}}\sum_{i=1}^{H_{k}}\sum_{j=1}^{H_{k}}W_{i,j,m,n} \cdot X_{k+i-1,l+j-1,m}\quad\forall k,l\in[1,H_{y}],\quad\forall n\in[1,C_{y}] \tag{1}\]

On modern CNN architectures, convolution layers are often coupled with batch-normalization layers that normalize (recentering and rescaling) the inputs of layers to make training faster and improve stability.

### Convolution primitives

We detail the different convolution primitives evaluated in this work. Table 1 sums up performance features compared to the standard convolution.
#### 2.0.1 Grouped convolution

was first introduced in the AlexNet paper from Krizhevsky _et al_. [7] for practical issues, then several works such as Ioannou _et al_. [4] have studied its effect on the performance of a neural network model. For the standard convolution, all input channels are used to compute an output channel. For a grouped convolution with G groups, each channel of the input and output are associated with a group \(G_{i}\). Then, to compute an output channel of the group \(G_{i}\), only the corresponding input channels are processed, as depicted in Fig. 1. Thus, grouped convolutions (also referred as _filter groups_) reduce the number of parameters and MAC operations of the layer by a factor G.

#### 2.0.2 Depthwise separable convolution

Szegedy _et al_. [9] introduce depthwise separable convolutions with the _Inception_ architecture. Depthwise separable convolution replaces the standard convolution by two convolutions: _depthwise_ and _pointwise_. Depthwise convolution is an extreme version of grouped convolution where \(G=C_{x}=C_{y}\). The problem is that each filter only handles information passed down from one input channel. Pointwise convolution is applied to linearly combine the output channels of the depthwise convolution thanks to \(1\times 1\) kernels. It also acts as a reduction of the depth of the output tensor \(Y\).

#### 2.0.3 Shift convolution

Even though pointwise convolution is more computationally expensive than depthwise convolution in theory, Jeon _et al_. [6] notice, with a hardware implementation, that depthwise convolution is more time-consuming

\begin{table}
\begin{tabular}{c c c c c} \hline \hline Convolution type & Parameters & Theoretical MACs & Parameters gain Complexity gain \\ \hline Standard & \(H_{k}^{2}\cdot C_{x}\cdot C_{y}\) & \(H_{k}^{2}\cdot C_{x}\cdot H_{y}^{2}\cdot C_{y}\) & - & - \\ Grouped & \(H_{k}^{2}\cdot\frac{C_{x}}{G}\cdot C_{y}\) & \(H_{k}^{2}\cdot\frac{C_{x}}{G^{2}}\cdot H_{y}^{2}\cdot C_{y}\) & \(\frac{1}{G}\) & \(\frac{1}{G}\) \\ Depthwise separable & \(C_{x}\cdot(H_{k}^{2}+C_{y})\) & \(C_{x}\cdot H_{y}^{2}\cdot(H_{k}^{2}+C_{y})\) & \(\frac{1}{C_{y}}+\frac{1}{H_{k}^{2}}\) & \(\frac{1}{C_{y}}+\frac{1}{H_{k}^{2}}\) \\ Shift & \(C_{x}\cdot(2+C_{y})\) & \(C_{x}\cdot C_{y}\cdot H_{y}^{2}\) & \(\frac{2}{C_{y}\cdot H_{k}^{2}}+\frac{1}{H_{k}^{2}}\) & \(\frac{1}{H_{k}^{2}}\) \\ Add & \(H_{k}^{2}\cdot C_{x}\cdot C_{y}\) & \(H_{k}^{2}\cdot C_{x}\cdot H_{y}^{2}\cdot C_{y}\) & \(1\) & \(1\) \\ \hline \hline \end{tabular}
\end{table}
Table 1: Summary of the different primitives. Parameters gain is the ratio between the primitive’s number of parameters and the standard convolution. The same applies for theoretical MACs with complexity gain.

Figure 1: From [4], standard vs. grouped convolutions: the grouped convolution with 2 groups applies half of the filters to each half of the input channels in order to compute each half of the output channels.
than point convolution. They replace depthwise convolution by a shift operation which requires extremely few parameters and less computational power to produce the intermediate feature map \(I\):

\[I_{k,l,m}=X_{k+\alpha_{m},l+\beta_{m},m}\ \forall k,l\in[1,H_{x}],\quad\forall m \in[1,C_{x}] \tag{2}\]

where \(\alpha_{m}\) and \(\beta_{m}\) denote the horizontal and vertical shift assigned to the \(m^{th}\) channel of the input feature map.

#### 2.2.2 Add convolution

Multiplication operation consumes, in most cases, more energy than addition operation. Chen _et al._[2] exploit the fact that convolutions in deep neural networks are cross-correlation measuring the similarity between input and convolution kernel. They propose to replace cross-correlation by \(L1\)-norm as a similarity measure to perform an _add convolution_ as in Eq.3.

\[Y_{k,l,n}=-\sum_{m=1}^{C_{x}}\sum_{i=1}^{H_{k}}\sum_{j=1}^{H_{k}}|W_{i,j,m,n}-X _{k+i-1,l+j-1,m}|\quad\forall k,l\in[1,H_{y}],\quad\forall n\in[1,C_{y}] \tag{3}\]

The output of an add convolution is always negative. Thus, in order to make add convolution compatible with standard activation functions like ReLu, a batch normalization layer following the add convolution layer is needed.

### Neural network library for Cortex-M MCU

The challenge of porting neural networks to constrained platforms such as microcontrollers has led to the creation of embedding tools (e.g. TFLM6, N2D27, STM32Cube MX-AI8 or NNoM9). Those tools support standard convolution as well as depthwise separable convolutions layers. TFLM and STM32Cube MX-AI support floating point operations, 16 and 8 bits integer operations while NNoM supports only 8 bits integer operations. Furthermore, for Cortex-M4 and Cortex-M7 MCUs (with Digital Signal Processing extensions), SIMD instructions can be used for the computation of different primitives by integrating the middleware CMSIS-NN [8] to those tools. For our study, the open source NNoM library was chosen due to its good performance and its ease of customization.

Footnote 6: [https://www.tensorflow.org/lite/microcontrollers](https://www.tensorflow.org/lite/microcontrollers)

Footnote 7: [https://github.com/CEA-LIST/N2D2](https://github.com/CEA-LIST/N2D2)

Footnote 8: [https://www.st.com/en/embedded-software/x-cube-ai.html](https://www.st.com/en/embedded-software/x-cube-ai.html)

Footnote 9: [https://github.com/majianjia/nnom](https://github.com/majianjia/nnom)

## 3 Implementation

In this section, we present the implementation details of NNoM and CMSIS-NN convolution on which our implementations of the different primitives are based. Furthermore, we detail the differences of implementation between the standard convolution and the optimized primitives.
### Quantization

Quantization is the process of reducing the precision of weights, biases, and activations in order to reduce the memory footprint. NNoM library uses 8 bits quantization for the weights, biases, and activations with a uniform symmetric powers-of-two quantization scheme as in Eq. 4.

\[dec=ceil\Big{(}log_{2}\big{(}max(|X_{f}|))\Big{)}\ ;\,x_{i}=floor\big{(}x_{f} \cdot 2^{(8-1)-dec}\big{)} \tag{4}\]

where \(X_{f}\) is a 32 bits floating point tensor, \(x_{f}\) a value of \(X_{f}\), \(x_{i}\) its 8 bits quantized version and \(2^{dec}\) is the scale of quantization. Because this scale is a power of 2, the convolution operation only requires integer addition, multiplication and bit shifting, but no division (see Algorithm 1, left). This computation process is used for grouped and shift convolutions because of their similarity to standard convolution. We adapt it to add convolutions as presented in Algorithm 1 (right).

```
1:\(output\gets i\cdot w\)
2:\(shift_{output}\leftarrow\mathit{dec}_{weight}+dec_{input}-dec_{output}\)
3:\(output\gets output>>shift_{output}\)
4:Return output
5:\(shift\leftarrow|dec_{input}-dec_{weight}|\)
6:\(shift_{output}\gets dec_{weight}\)then
7:\(output\leftarrow-|i-w|\)
8:\(shift_{output}\gets dec_{weight}-dec_{output}\)
9:\(shift_{output}\gets dec_{weight}-dec_{output}\)
10:endif
12:\(output\gets output>>shift_{output}\)
13:Return output
```

**Algorithm 1** Inner loop of convolution (left) and add convolution (right) without bias

### Batch normalization folding

For convolutions, NNoM library uses the batch normalization folding proposed by Jacob _et al_. [5]. By merging convolution layers and batch normalization layers, this method accelerates the inference without accuracy drop. Batch normalization folding can be applied for the computation of grouped and shift convolutions but is not suitable fot add convolution.
### Im2col algorithm with SIMD instructions

In order to accelerate convolutions, the CMSIS-NN middleware [8] use the image to column (im2col) algorithm [1]. A first step is to sample patches from the input, flatten and stack them as columns of a matrix \(M\). Each filters of the convolution weight \(W\) are also flattened and stacked as rows of a matrix \(N\). In the second step, the output is computed with the matrix multiplication \(Y=M.N\). To deal with the increased memory footprint of im2col, Lai _et al._[8] limit the number of patches processed at the same time to 2. The matrix multiplication is computed using 2 filters simultaneously to maximize the data reuse at the register file level on ARM Cortex-M. Furthermore, Lai _et al._[8] use the parallelized multiply-accumulate instruction __SMLAD to speed up the matrix multiplication.

For grouped convolution, we apply Lai _et al._[8] algorithm to each group. For shift convolution, we modify the first step of im2col to sample a patch with different shifts for each input channel. We did not implement a SIMD version of add convolutions because there is no instructions similar to __SMLAD adapted to add convolutions.

## 4 Experimental characterisations

The experiments are carried out on a typical 32-bit MCU platform, the Nucleo STM32F401-RE, based on Cortex-M4 that supports SIMD instructions. Unless specified, the compiler is arm-none-eabi-gcc (version 10.3) with the optimization level sets to Os and the MCU's frequency is fixed at 84 MHz. The software STM32CubeMonitor-Power10 is used to measure the electric current of the MCU. We multiply it by the supply voltage (i.e. 3.3 V) and integrate it over the duration of an inference to obtain the inference's energy consumption.

Footnote 10: [https://www.st.com/en/development-tools/stm32cubemonpwr.html](https://www.st.com/en/development-tools/stm32cubemonpwr.html)

### Influence of the primitive parameters

#### 4.1.1 Protocol

To evaluate the influence of a parameter (i.e. kernel size, input width...), we consider a layer with every other parameters fixed excepted the concerned one. The experiment plan is defined in table 3. We measure the latency and energy consumption over 50 inferences (average) with randomized inputs. Results are presented in Fig.2.

#### 4.1.2 Results without SIMD instructions

We observe in Fig. 2.a-c that our implementation fits the theory (Table 1). For example, the theoretical MACs, latency and energy consumption increase quadratically with the kernel size (Fig 2.a, Fig 2.b and Fig 2.c). More specifically, there is a linear relationship between the MACs, latency and consumption. A linear regression leads to scores of 0.995 and 0.999 respectively. Add convolutions are slightly less efficient than convolutions despite the same number of MACs. This is explained by the quantization scheme of add convolution and the additional batch normalization layer.
Figure 2: Influence of the 1) number of groups, 2) kernel size, 3) input width, 4) number of input channels and 5) filters on a) theoretical MACs, b) latency without SIMD instructions, c) energy consumption without SIMD instructions, d) latency with SIMD instructions and e) energy consumption with SIMD instructions and f) speedup for different primitives. The different implementations fit the theory. Using SIMD instructions enables faster and less energy consuming inferences. The speedup of the im2col algorithm varies according to the primitives and their parameters.
#### 4.1.2 Effect of SIMD instructions

Using SIMD instructions decreases the latency (Fig 2.d) and energy consumption (Fig 2.e) of the different primitives. Our implementation with SIMD instructions also fits the theory. But latency is more relevant to estimate the layer's energy consumption (regression score of 0.999) than theoretical MACS (regression score of 0.932). This loss of linearity is related to the varying speedup of the im2col algorithm with respect to the primitives and their parameters (Fig 2.f). A possible explanation is in the data reuse exploitation by the im2col algorithm. To verify this, we measure the number of memory access in those programs. Fig. 3 shows the variation of the ratio of memory access without SIMD instructions by the memory access with SIMD instructions (normalized by MAC) for different parameters and primitives. We observe in Fig. 3 the same variations as in Fig. 2.f. Thus, data reuse contributes strongly to the speed up of algorithms using SIMD instructions. However, convolutions and grouped convolutions have similar ratio in Fig. 3 but different speedup in Fig. 2.f. Other factors such as memory access continuity and padding are to be taken into account to explain the performance of these programs.

### Influence of other factors

For the following experiments, we fix the number of groups at 2, the kernel size at 3, the input width at 32, the input channel at 3 and the filters at 32.

\begin{table}
\begin{tabular}{c c c c c c} \hline \hline \multicolumn{5}{c}{Experiment Groups Kernel size Input width Input channel Filters} \\ \hline
1 & 1-32 & 3 & 10 & 128 & 64 \\
2 & 2 & 1-11 & 32 & 16 & 16 \\
3 & 2 & 3 & 8-32 & 16 & 16 \\
4 & 2 & 3 & 32 & 4-32 & 16 \\
5 & 2 & 3 & 32 & 16 & 4-32 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Primitive parameters for the different experiments.

Figure 3: Influence of the a) number of groups, b) kernel size, c) input width, d) number of input channels and e) filters on the ratio of memory access without SIMD instructions by the memory access with SIMD instructions (normalized by MACs) for different primitives.
Influence of optimization levelWe perform a convolution inference with two different optimization levels (O0 and Os). As seen in table 4, the compiler optimization has an important effect on the layer performance. Using Os level accelerates the inference by a factor 1.52. This impact is emphasized with the use of SIMD instructions (factor 9.81). Without optimization, the use of SIMD instructions can even increase the layer's energy consumption as using SIMD instructions increases the average power consumption.

## 5 Conclusion

In this paper, we implement and benchmark several state-of-the-art convolution primitives for ARM Cortex-M microcontrollers. Our benchmark shows that for microcontrollers which cannot use SIMD instructions, theoretical MACs is a relevant indicator to estimate the layer energy consumption. For microcontrollers

\begin{table}
\begin{tabular}{l c c c c c} \hline \hline \multicolumn{5}{c}{Optimization level Latency (s) Consumption (mJ) Optimization Speedup SIMD Speedup} \\ \hline No SIMD & O0 & 1.26 & 63.9 & - & - \\  & Os & 0.83 & 45.7 & 1.52 & - \\ \hline \multirow{2}{*}{SIMD} & O0 & 1.08 & 82.0 & - & 1.17 \\  & Os & 0.11 & 7.2 & 9.81 & 7.55 \\ \hline \end{tabular}
\end{table}
Table 4: Effect of optimization level on inference performance for convolution.

Figure 4: Influence of the MCU frequency on latency, energy consumption without SIMD instructions (a and b) and with SIMD instructions (c and d).
which use SIMD instructions, latency is preferred over theoretical MACS to estimate the layer energy consumption while using SIMD instructions. We explain this by the varying efficiency of the im2col algorithm, from CMSIS-NN, depending on the layers and highlight the role of data reuse in this performance gap. Furthermore, we study the influence of external parameters to the convolution algorithms such as the compiler optimization and the MCU frequency. Our experiments highlight the major impact of the compiler optimization on the layers performance while using SIMD instructions, and show that running the inference at maximum frequency decreases the layer's energy consumption. Our work opens up new possibilities for neural architecture search algorithms.

#### 4.0.1 Author Contribution

Nguyen, Moellic and Blayac conceived and planned the study. Nguyen carried out the experiments and performed the analysis. Nguyen and Moellic wrote the manuscript with inputs from all authors.

Part of this work was done with the support of ID-Fab (Prototyping platform: project funded by the European Regional Development Fund, the French state and local authorities). This work benefited from the French Jean Zay supercomputer thanks to the _AI dynamic access_ program. This collaborative work is partially supported by the IPCEI on Microelectronics and Nano2022 actions and by the European project InSecTT11 and by the French National Research Agency (ANR) in the framework of the _Investissements d'Avenir_ program (ANR-10-AIRT-05, irtanoelec).

Footnote 11: www.insectt.eu: ECSEL Joint Undertaking (876038). The JU receives support from the European Union’s H2020 program and Au, Sw, Sp, It, Fr, Po, Ir, Fi, Sl, Po, Nl, Tu. The document reflects only the author’s view and the Commission is not responsible for any use that may be made of the information it contains.
