Number Systems for Deep Neural Network Architectures: A Survey
Deep neural networks (DNNs) have become an enabling component for a myriad of
artificial intelligence applications. DNNs have shown sometimes superior
performance, even compared to humans, in cases such as self-driving, health
applications, etc. Because of their computational complexity, deploying DNNs in
resource-constrained devices still faces many challenges related to computing
complexity, energy efficiency, latency, and cost. To this end, several research
directions are being pursued by both academia and industry to accelerate and
efficiently implement DNNs. One important direction is determining the
appropriate data representation for the massive amount of data involved in DNN
processing. Using conventional number systems has been found to be sub-optimal
for DNNs. Alternatively, a great body of research focuses on exploring suitable
number systems. This article aims to provide a comprehensive survey and
discussion about alternative number systems for more efficient representations
of DNN data. Various number systems (conventional/unconventional) exploited for
DNNs are discussed. The impact of these number systems on the performance and
hardware design of DNNs is considered. In addition, this paper highlights the
challenges associated with each number system and various solutions that are
proposed for addressing them. The reader will be able to understand the
importance of an efficient number system for DNN, learn about the widely used
number systems for DNN, understand the trade-offs between various number
systems, and consider various design aspects that affect the impact of number
systems on DNN performance. In addition, the recent trends and related research
opportunities will be highlighted
Ghada Alsuhli, Vasileios Sakellariou, Hani Saleh, Mahmoud Al-Qutayri, Baker Mohammad, Thanos Stouraitis
# Number Systems for Deep Neural Network Architectures: A Survey

###### Abstract

Deep neural networks (DNNs) have become an enabling component for a myriad of artificial intelligence applications. DNNs have shown sometimes superior performance, even compared to humans, in cases such as self-driving, health applications, etc. Because of their computational complexity, deploying DNNs in resource-constrained devices still faces many challenges related to computing complexity, energy efficiency, latency, and cost. To this end, several research directions are being pursued by both academia and industry to accelerate and efficiently implement DNNs. One important direction is determining the appropriate data representation for the massive amount of data involved in DNN processing. Using conventional number systems has been found to be sub-optimal for DNNs. Alternatively, a great body of research focuses on exploring suitable number systems. This article aims to provide a comprehensive survey and discussion about alternative number systems for more efficient representations of DNN data. Various number systems (conventional/unconventional) exploited for DNNs are discussed. The impact of these number systems on the performance and hardware design of DNNs is considered. In addition, this paper highlights the challenges associated with each number system and various solutions that are proposed for addressing them. The reader will be able to understand the importance of an efficient number system for DNN, learn about the widely used number systems for DNN, understand the trade-offs between various number systems, and consider various design aspects that affect the impact of number systems on DNN performance. In addition, the recent trends and related research opportunities will be highlighted.

 Number Systems, Artificial Intelligence Accelerators, Deep neural networks, floating point, fixed point, logarithmic number system, residue number system, block floating point number system, dynamic fixed point Number System, Posit Number System.

## I Introduction

During the past decade, Deep Neural Networks (DNNs) have shown outstanding performance in a myriad of Artificial Intelligence (AI) applications. Since their success in speech recognition [1] and image recognition [2], great attention has been drawn to DNNs from academia and industry [3]. Although DNNs are inspired by the deep hierarchical structures of the human brain, they have exceeded the human accuracy in a number of domains [4]. Nowadays, the contribution of DNNs is notable in many fields including self-driving cars [5], speech recognition [6], computer vision [7], natural language processing [8], and medical applications [9]. This DNN revolution is helped by the massive accumulation of data and the rapid growth in computing power [10].

Because of their high computational complexity and memory space requirements, general-purpose compute engines (like powerful central processing units (CPUs) and Graphics Processing Units (GPUs)), or customized hardware (e.g., using FPGAs or ASICs) have been used to accelerate DNN processing [11]. While general-purpose compute engines remain dominant for processing DNNs within academia, the industrial applications of DNNs often require implementation on resource-constrained edge devices ( e.g., smartphones or wearable devices) [3]. Whether DNNs are run on GPUs or dedicated accelerators, speeding up and/or increasing DNN hardware efficiency without sacrificing their accuracy continues to be a demanding task. The literature includes a large number of survey papers that have been dedicated to highlighting the directions that can be followed to reach these goals [3, 4, 12, 13, 14]. Some examples of these directions are DNN model compression [15], quantization [12], and DNN efficient processing [4]. One of the directions that have a great impact on the performance of DNNs, but has not been comprehensively surveyed yet is the DNN number representation.

As the compute engines use a limited number of bits to represent values, real numbers cannot be infinitely represented. The mapping between a real number and the bits that represent it is called number representation [16]. Generally speaking, number representation has a great impact on the performance of both general-purpose and customized compute engines. Recalling the huge amount of data that need to be processed in the context of DNNs, the choice of the format used to represent these data is a key factor in determining the precision of DNN data, storage requirements, memory communication, and arithmetic hardware implementation [17]. This in turn shapes different metrics of the DNN architecture performance; mainly the accuracy, power consumption, throughput, latency, and cost [18].

To this end, there is a significant body of literature that has focused on assessing the suitability of specific number systems for DNNs, modifying conventional number systems to fit DNN workloads, or proposing new number systems tailored for DNNs. Some of the leading companies, such as Google [19], NVIDIA [20], Microsoft [17], IBM [21], and Intel [22, 23, 24], have contributed in advancing the research in this field. A comprehensive survey of these works will be helpful to furthering the research in this field.

While conventional number systems like Floating Point
(FLP) and Fixed Point (FXP) representations are frequently used for DNN engines, several unconventional number systems are found to be more efficient for DNN implementation. Such alternative number systems are presented in this survey and they are the Logarithmic Number System (LNS), Residue Number System (RNS), Block Floating Point Number System (BFP), Dynamic Fixed Point Number System (DFXP), and Posit Number System (PNS). Figure 1 shows the bit visualization of conventional and unconventional number systems used in DNN implementation. The structure of the survey is summarized as follows.

* Section II gives an overview of conventional number systems and their utilization for DNNs.
* Section III classifies the DNNs that adopt the logarithmic number system.
* Section IV describes the concepts behind the residue number system and its employment for DNNs.
* Section V describes the block floating point representation and the efforts done to make it suitable for DNNs implementation.
* Section VI discusses the dynamic fixed point format and the work done to calibrate the parameters associated with this format.
* Section VII explains various DNN architectures that utilize Posits and the advantages and disadvantages associated with these architectures.
* Section VIII provides an insight into recent trends and research opportunities in the field of DNN number systems.

## II Conventional Number Systems for DNN architectures

The two conventional number systems, mainly the floating point and the fixed point, are the common choice for almost all general-purpose DNN engines. While the FLP representation is usually used for modern computation platforms (e.g., CPUs and GPUs), where high precision is a must, FXP is more common in low-cost computation platforms that are used in applications that demand high speed, low power consumption, and small chip area. In this section, these two representations are introduced and their utilization for implementing DNN hardware is briefly discussed, in order to facilitate the comparison between conventional and unconventional number systems.

### _FLP for DNN Architectures_

In the FLP number system, a number \(n\) is represented using a sign (1 bit), an exponent \(e\) (unsigned integer of length \(es\)) and a mantissa \(m\) (unsigned integer of length \(ms\)) (Figure 1a) and its value is given by

\[n=(-1)^{s}\times 2^{e-e_{max}}\times(1+\frac{m}{2^{ms}}), \tag{1}\]

where \(e_{max}=2^{es-1}-1\) is a bias used to ease the representation of both negative and Positive exponents. Although there are several FLP formats [25], the IEEE 754 FLP format [26] is the most common representation used by modern computing platforms [18, 27]. According to IEEE 754, the FLP can be of single, double, or quad-precision depending on the used bit-widths (e.g., for the single-precision FLP the bit-width is 32 bits and \(es=8\)). The single-precision FLP, also called FLP32, is commonly used as a baseline to evaluate the efficiency of other number representations. Unless otherwise stated, the performance degradation or enhancement is presented in comparison to the FLP32 format in this survey as well.

Multiplication of two FLP numbers is implemented in hardware by adding their exponents, multiplying the mantissas, normalizing the resultant mantissa, and adjusting the exponent of the product [28]. FLP addition involves comparing the operand exponents, shifting their mantissas (if the exponents are different), adding the mantissas, normalizing the sum mantissa, and adjusting the sum exponent [25]. Usually, the increased complexity of the FLP32 arithmetic requires using a separate unit called Floating Point Unit (FPU) to perform the FLP calculations [29]. The high power consumption and cost of this unit limits its usage within embedded processing units such as FPGAs [30]. Consequently, the standard FLP32 is rarely used for building efficient DNN architectures [28]. To increase the efficiency of the FLP in DNN architectures several custom FLP formats [19, 20, 31, 32] have been proposed. Also new designs of the FLP arithmetic hardware (mainly the multiplier) have been investigated [28, 33].

The 32-bit FLP representation has a wide dynamic range, beyond what is usually required for DNNs [28], resulting in a low information-per-bit metric, which means an unnecessary increase in power consumption, area, and delay. For this reason, the proposed custom FLP representations mainly have reduced bit-width and a different allocation of the bits to mantissa and exponent, than IEEE 754. The bit-width is reduced to 19 bits in Nvidia's TensorFloat32 [20] and 16 bits in Google's Brain FLP (bfloat16) [19] formats used in DNN training engines. 8-bit FLP has been proposed to target the DNN inference in [31, 32]. These reduced FLP formats proved their efficiency in replacing FLP32 with comparable accuracy, higher throughput, and smaller hardware footprint. It is worth noting that most of these custom FLP formats are used to represent data stored in memory (i.e., weights and activations), whereas, for internal calculations (e.g., accumulation and weight updates), FLP32 is used instead to avoid accuracy degradation [19, 32, 34].

In summary, the standard FLP representation has a massive dynamic range, which makes it a good choice for computationally intensive algorithms that include a wide range of values and require high precision. At the same time, the complex and power-hungry FLP calculations make FLP less attractive for DNN accelerators. This leads to using narrower custom FLP formats which require less hardware and memory footprint while preserving the performance of the standard FLP32. However, the utilization of the FLP format for DNN accelerators is relatively limited and it loses ground to fixed point and other alternative representations.
## I Introduction

Fig. 1: Conventional [(a) FP, (b) KXP] and unconventional [(c) BFP, (d) DEXP, (e) Posit, (f) LNS, (g) RNS] number systems for DNNs
### _FXP for DNN Architectures_

The power inefficiency of the FLP arithmetic is the main motivation to replace it with the FXP format for designing energy-constrained DNN accelerators. A real number \(n\) is represented in FXP with the sign, the integer, and the fraction parts. The fixed point format is usually indicated by \(<I,F>\) where \(I\) and \(F\) correspond to the number of bits allocated to the integer and the fractional parts, respectively. In this paper, we use the notations FXP8, for example, to denote the FXP representation with bit-width equal to 8, i.e., \(I+F+1=8\).

In FXP format, the separation between the integer and the fractional parts is implicit and usually done by specifying a scaling factor that is common for all data. Thus, the FXP number can be treated as an integer and, hence, integer arithmetic is used. Integer arithmetic requires substantially fewer logic gates to be implemented and consumes much less chip area and power, compared to FLP arithmetic. This makes FXP attractive to be used for DNN accelerators on the edge. Moreover, the FXP allows for more reduction in the number of bits resulting in a significant reduction in the power consumption, storage requirements, and memory bandwidth [4].

On the other hand, the dynamic range1 of data represented by low precision FXP is limited. This makes FXP suitable to represent data with only narrow range of values. Since this is not the case for most DNNs, using low precision FXP for DNNs is challenging. To enable this, various approaches were adopted such as quantization [12]. For instance, uniform quantization includes scaling weights and activations of DNN and mapping them to a restricted range of values. These values can be represented by low-bit-width FXP. This allows lowering the number of bits to be less than 8 bits [35, 36, 37], and even as low as 2 bits (i.e., ternary DNNs [38, 39, 40]) or 1 bit (i.e., binary DNNs [41, 42, 43, 44, 45]). For more information about the FXP quantization, precision reduction, and binary DNNs the interested reader is referred to [4, 12, 46].

Footnote 1: The dynamic range of a number system is the ratio of the largest value that can be represented with this system to the smallest one.

In short, the FXP for DNN implementation offers great hardware efficiency at the expense of some accuracy degradation. Between the two extreme representations (FLP and FXP), there are several number systems that offer different trade-offs (Pareto optimal points) between the hardware efficiency and the acquired accuracy. These number systems and their usage for DNN implementation are presented in subsequent sections of this paper.

## III LNS for DNN Architectures

Proposals for LNS first emerged in the 1970s to implement the arithmetic operations of digital signal processing. The utilization of LNS for neural computing was first proposed in the late 90's [47]. Since then, using LNS to implement efficient hardware for DNN has become more popular. The main benefit of using LNS is in simplifying the implementation of the costly arithmetic operations required for DNN inference and/or training [48]. In addition, representing the data in LNS enables a reduction of the number of bits required to obtain the same DNN accuracy as with conventional number systems [49, 50]. In LNS, a real number \(n\) is represented with a logarithm of radix \(a\) of its absolute value (\(\tilde{n}=\log_{a}(|n|)\)) and a sign bit \({s_{n}}^{2}\)[48]. The number \(\tilde{n}\) is represented using two's complement fixed point format [51], as shown in Figure 1f. The radix \(a\) of the logarithm is usually selected to be 2 for simpler hardware implementation. Throughout this survey, we will use \(a=2\) as well.

The main DNN operation that can be dramatically simplified using LNS is the multiplication by transforming it into linear (i.e., fixed point) addition. The LNS product \(\tilde{p}\) of two real numbers \(n_{1},\text{ and }n_{2}\) is calculated as follows

\[\tilde{p} =\tilde{n_{1}}\odot\tilde{n_{2}}, \tag{2}\] \[=\log_{2}(|n_{1}|\times|n_{2}|),\] \[=\tilde{n_{1}}+\tilde{n_{2}},\]

\[s_{\tilde{p}}=s_{n_{1}}XOR\ s_{n_{2}}, \tag{3}\]

where \(\odot\) is the multiplication operation in LNS domain that can be implemented with a simple integer adder, and \(s_{\tilde{p}}\) is the product sign, which is calculated by XORing the signs (\(s_{n_{1}}\) and \(s_{n_{2}}\)) of the two operands.

Existing proposals for LNS-based DNNs are for either using LNS for the whole DNN architecture from end-to-end, just for using the LNS-based multipliers, or for using logarithmic quantization for DNN weights and/or layer inputs. Based on this classification, LNS-based DNN architectures are discussed next by highlighting the challenges associated with each architecture and the solutions presented in the related work.

### _End-to-end LNS-based DNN Architectures_

End-to-end-LNS implementation utilizes the LNS for all blocks of the architecture, and thus, no conversion from or to conventional systems takes place. For this, the inputs (i.e., the dataset) and the weights3 are assumed to be fed to DNN in LNS format. This task is usually performed offline and has no overhead on the implemented architecture. In this section, we review LNS-domain implementation of the main operations that are needed for DNN training and inference. The two types of DNNs that were implemented using LNS from end to end are convolutional neural networks (CNNs) [49, 50] and recurrent neural networks (RNNs) [52]. These two types of DNN have different architectures, but they share the same basic operations which are multiplication, addition, and activation functions. Since the multiplication operation becomes a linear addition in LNS-domain, the challenging part of this architecture is implementing LNS-addition and LNS-activation functions, which are discussed next.

Footnote 3: When the architecture targets DNN inference.

#### Iii-A1 Addition in LNS

As opposed to multiplication, performing addition in LNS is not straightforward. Let \(\tilde{n_{1}}\) and \(\tilde{n_{2}}\) be the two operands to be added in LNS. This LNS addition \(\oplus\) is usually defined as follows
\[\begin{split} s\tilde{u}m&=\tilde{n_{1}}\oplus\tilde{n_{2 }},\\ &=\log_{2}|(-1)^{s_{n_{1}}}\times 2^{\tilde{n_{1}}}+(-1)^{s_{n_{2}}} \times 2^{\tilde{n_{2}}}|,\end{split} \tag{4}\]

where \(s\tilde{u}m\) is the LNS domain summation of the two operands, and \(s_{n_{1}}\) and \(s_{n_{2}}\) are their signs. As these operands can be negative or Positive, \(\tilde{u}m\) is derived from 4 [50] such that

\[\begin{split} s\tilde{u}m=\left\{\begin{array}{ll}\max(\tilde{ n_{1}},\tilde{n_{2}})+\log_{2}(1+2^{-|\tilde{n_{1}}-\tilde{n_{2}}|}),\\ \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad\qquad \qquad\
Multiplier that receives linear operands and produces a linear product as well.

#### Iii-B1 LNS-based Multiplier

To simplify the discussion and comparisons between various LNS multipliers proposed for DNN, some notations are introduced for the next subsections. Let \(n\) be a Positive integer and its \(w\)-bit binary representation is \(B_{n}=b_{w-1}\)\(b_{w-2}\ldots b_{0}\). Let \(b_{k}\) be the most significant \({}^{\prime}1^{\prime}\) in \(B_{n}\) (\(k\) is called the characteristic number of \(n\)). The linear number \(n\) and its logarithm can be represented by

\[n =2^{k}(1+x), \tag{13}\] \[\log_{2}(n) =k+\log_{2}(1+x), \tag{14}\]

where \(0\leq x<1\) is called the mantissa of \(n\). Let \(n_{1}=2^{k_{1}}(1+x_{1})\) and \(n_{2}=2^{k_{2}}(1+x_{2})\) be the multiplier and multiplicand, respectively. The product of these operands and its logarithm are given by

\[n_{1}\times n_{2}=2^{k_{1}+k_{2}}(1+x_{1})(1+x_{2}), \tag{15}\] \[\log_{2}(n_{1}\times n_{2})=k_{1}+k_{2}+\log_{2}(1+x_{1})+\log_{2 }(1+x_{2}), \tag{16}\]

The main idea of the logarithmic multiplier is to use a specific approximation based on the characteristics of the logarithms to simplify the product calculation by mainly using shift and add operations instead of hardware-intensive conventional multiplication. Given their effectiveness, many logarithmic multipliers have been proposed for image processing and neural computing [53, 54, 55, 56, 57, 58]. Several of these multipliers were utilized to also build efficient DNN architectures. They are classified in this survey into multipliers that use Mitchell's approximation, iterative logarithmic multipliers, double-sided error multipliers, and multipliers with explicit logarithm and antialgorithm modules.

Mitchell's MultiplierAccording to Mitchell's algorithm [54], the logarithm of a number \(n\) is approximated with piece-wise straight lines as in (7). Thus, the logarithm of the product in (16) is approximated by the sum of the characteristic numbers and the mantissas of the operands as follows

\[\log_{2}(n_{1}\times n_{2})\approx k_{1}+k_{2}+x_{1}+x_{2}. \tag{17}\]

The final product is obtained in (18) by applying the antilogarithm on (17) using the approximation in (7). Then, the product of two integers is calculated using add and shift operations, as

\[n_{1}\times n_{2}\approx\left\{\begin{array}{ll}2^{k_{1}+k_{2}}(1+x_{1}+x_{ 2}),&x_{1}+x_{2}<1\\ 2^{k_{1}+k_{2}+1}(x_{1}+x_{2}),&x_{1}+x_{2}\geq 1\end{array}\right. \tag{18}\]

Even though the error introduced by Mitchell's approximation is relatively high (up to 11% [55]), this multiplier showed no accuracy degradation for CNN architecture with 32- bit precision [59], while being 26.8% more power-efficient compared to conventional multipliers of the same number of bits.

To gain additional power efficiency over the one achieved by Mitchell's multiplier, a truncated-operand approach has been proposed [60]. Instead of using the whole operands, these operands are truncated and only their \(\omega\) most significant bits are used to calculate the approximated product. For instance, selecting \(\omega=8\) allows for a more efficient multiplier that saves up to 88% and 56% of power when compared to an exact 32-bit FXP multiplier and a Mitchell's multiplier, respectively. The additional error introduced by this truncation caused an accuracy degradation of 0.2% for the ImageNet dataset. The significant power saving associated with the negligible performance degradation of this approach comes from the fact that the most significant part of the operand can be sufficient to provide an acceptable approximation [61, 62].

Iterative Logarithmic MultiplierThe iterative logarithmic multiplier aims to reduce the error introduced by the approximation in (18) by adding correction terms. The calculation of these terms usually requires iterative multiplications that can be calculated in the same way as calculating the approximate product ( see Figure 3). These correction terms can be biased (always Positive) or unbiased (negative/Positive).

The product of two numbers in (15) can be written using biased correction terms [55] as

\[n_{1}\times n_{2}=P_{approx}+E, \tag{19}\]

where \(P_{approx}=2^{k_{1}+k_{2}}(1+x_{1}+x_{2})\) is an approximate product that can be calculated using shift and add operations. \(E=2^{k_{1}+k_{2}}x_{1}x_{2}\) is a correction term that is ignored in (18). Estimating the term \(E\) requires calculating the product \((2^{k_{1}}x_{1})(2^{k_{2}}x_{2})=(n_{1}-2^{k_{1}})(n_{2}-2^{k_{2}})\) iteratively, in the same way of calculating \(P_{approx}\). Then,

\[n_{1}\times n_{2} =P_{approx}^{(0)} +E^{(0)}, \tag{20}\] \[=P_{approx}^{(0)} +P_{approx}^{(1)}+E^{(1)},\] \[=P_{approx}^{(0)} +P_{approx}^{(1)}+\cdots+P_{approx}^{(i-1)}+E^{(i-1)},\]

where \(i\) is the number of iterations and \(E^{(i-1)}\) is the error to be ignored after the \(i^{th}\) iteration. Notice that when \(i\) equals the number of bits that have the value of '1' in the operands, then \(E^{(i-1)}=0\), and the exact product is produced. For each iteration, the new operands to be multiplied are obtained by removing the leading 'ones' from the original operands. For this reason, the correction terms can be calculated in parallel using one additional circuit for each iteration. Hence, there is a trade-off between the accuracy of the multiplication and the area and power overhead due to adding these correction circuits. For example, this iterative logarithmic multiplier with one iteration (i.e., one correction circuit) was able to save 10% on area and 20% on power consumption without any notable impact on the learning accuracy when it was used to implement the hardware of a relatively simple neural network and compared with the case of using floating point multiplier [63].

On the other hand, using unbiased iterative correction terms of (21) shows a better area and power reduction by up to 44.6% and 48.1%, respectively, compared to the multiplier designed with the error terms of (19) [64].
\[E=\left\{\begin{array}{ll}((1-x_{1})2^{k_{1}}-1)((1-x_{2})2^{k_{2}}-1),&\\ &\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad \
approximated using a LUT. The LUT maps \(f\) to \(Q_{\alpha}(2^{f}-1)\), where \(Q_{\alpha}\) is the applied quantization to limit the number of bits to \(\alpha\).

LUT-approximation is usually used to escape from the errors introduced by the approximation in (7). However, to keep the size of the required LUTs reasonable, the value of \(\alpha,\gamma,\text{ and }\beta\) should be kept as small as possible. This introduces a loss in accuracy. In addition, this approach is expected to be less hardware-friendly because of the needed overhead to implement these LUTs. Nevertheless, experimental results showed that integrating 16-bit LUT-based multiplier with a wide FXP accumulator results in a reduction in power consumption and area by up to 59% and 68%, respectively, in comparison to 16-bit FLP multiplier [67]. This comes in addition to achieving a negligible accuracy degradation (\(<1\%\)) for the CNN ResNet50 network trained on the ImageNet dataset.

Another approach for approximating log/antilog modules is using bit-level manipulation to innovate area and speed efficient logarithm or antilogarithm operations [68, 69]. Among these works, the two-region manipulation-based logarithm converter and bit correction-based antilogarithm converter [70] are used to implement an LNS multiplier that is exploited to build an efficient CNN accelerator design from area and delay point of view [68]. When this design is compared to conventional multiplier implementation, it saves up to 60% of the area-delay product. However, neither the accuracy of the CNN nor a comparison with other logarithmic multipliers has been reported for this design.

Summary and Discussion of LNS-based MultipliersLNS-based multipliers use the characteristics of the logarithm to transform the multiplication into simpler operations. Most of the proposed logarithmic multipliers for DNN architecture started from Mitchell's approximation to innovate their logarithmic multipliers. Table I compares various architectures that use LNS multipliers. We notice that these multipliers are used to implement efficient CNN architectures suitable for DNN inference rather than training. In addition, this table depicts that using the vanilla Mitchell's multiplier offers power-efficient hardware with comparable accuracy to the FLP32 multiplier of the same number of bits. However, reducing the number of bits requires a more accurate approximation with less average error than Mitchell's. When the LNS multiplier is designed with the characteristics of DNN in mind, such as the double-sided-error multiplier, the outcome is further reduction in the number of bits with significant power savings, while preserving and even enhancing the classification accuracy of the reported CNNs.

### _Logarithmic quantization for DNN architectures_

Logarithmic quantization involves representing a real number \(n\) with a sign and an integer exponent (integer power of two). The integer is usually an approximation of the logarithm \(\log_{2}|n|\) of the real number after applying the clipping and rounding [71, 72]. Logarithmic quantization has been employed in order to achieve efficient hardware implementation of CNNs [71, 72]. The main idea behind this is the that the multiplication by this integer exponent can be
easily implemented in hardware by bit shifting. In CNNs, both the convolutional and fully-connected layers include matrix multiplication, i.e., dot product between the weights \(w\) of each layer and the input activation \(x\), which is the output of the previous layer after applying the non-linearity (e.g., ReLU). This matrix multiplication is usually performed using a number of multiply-and-accumulate operations when the conventional data representation is used to implement digital hardware, as shown in Figure 5(a). However, this dot product can be implemented more efficiently when Logarithmic quantization is utilized. Due to the non-uniform distribution of the weights and inputs, using nonuniform quantization, such as logarithmic quantization, is preferred over the uniform quantization, such as when FXP is used [72].

Existing CNN architectures that use logarithmic quantization assume that weights and/or the inputs of the layer are quantized. When logarithmic quantization is applied to inputs only (i.e activations), Figure 5(b), or to weights only, Figure 5(c), the dot product becomes a simple bit shift operation followed by an accumulation. applying logarithmic quantization on the weights only shows insignificant accuracy degradation [73, 74] and significant power and area savings [75, 76], see Table II. Quantizing the inputs only in LNS results in the same performance from an accuracy point of view [49, 77], however, with an additional linear-to-LNS module to be added. This module is responsible for transforming output activations to LNS before storing them in memory. This scheme has the advantage of requiring a smaller memory bandwidth as the stored activation is represented in LNS [49].

The works that apply logarithmic quantization to weights as well as to activations usually use a logarithm radix different from '2' [71, 72]. Then, the multiplication becomes an addition of the LNS quantized weights and activations followed by an approximation to decode this sum into the linear domain before implementing the accumulation. This add-decode-accumulate scheme adds a complication to hardware implementation, however, with comparable accuracy to the aforementioned logarithmic quantization schemes, as illustrated in Table II.

## IV RNS for DNN Architectures

The Residue Number System (RNS) can be an attractive choice for DNN accelerators due to its arithmetic properties. In this Section, a brief overview of the RNS is given, and several RNS-based architectures for AI applications reported in literature are presented. Architectures are classified to _partially RNS-based_, where intermediate conversions to conventional representations between successive layers are used, and _end-to-end_ RNS-based architectures, where the entire processing takes place in the RNS domain. The typical computation flow of these two types of systems is shown in Fig. 6.

The number representation scheme utilized in realizing DNN architectures directly impacts the accuracy, speed, area, and energy dissipation. Modern Deep Learning models keep growing in depth and number of parameters and require a huge amount of elementary arithmetic operations, the majority of which are multiply-add operations (MAC).

In the Residue Number System, each number is represented as a tuple of residues with respect to a modulus set \(\{m_{1},m_{2},\ldots,m_{n}\}\), which is called the _base_ of the representation. The dynamic range of the representation is given by

\[R=\prod_{i=1}^{N}m_{i}. \tag{27}\]

If the moduli are _co-prime_, i.e.,

\[\operatorname*{gcd}_{\begin{subarray}{c}1\leq i,j\leq N\\ i\neq j\end{subarray}}(m_{i},m_{j})=1, \tag{28}\]

where \(\gcd(\cdot)\) denotes the greatest common divisor operation, each integer inside the range \([0,R)\) has a unique RNS representation

\[X\mapsto(x_{1},x_{2},\ldots,x_{n}),\ x_{i}=\langle X\rangle_{m_{i}}, \tag{29}\]

where \(\langle\cdot\rangle_{m}\) is the modulo-\(m\) operator. Inverse transformation is generally harder and can be realized by means of the _Mixed Radix Conversion_ or the _Chinese Remainder Theorem_[78].

### _RNS Addition and Multiplication_

Due to the properties of the modulo operation, addition and multiplication can be done independently and in parallel for each residue channel, i.e., without inter-channel propagation of information. Suppose \(A=(a_{1},a_{2},\ldots,a_{n})\) and \(B=(b_{1},b_{2},\ldots,b_{n})\), then

\[a\oplus b=((a_{1}\oplus b_{1})_{m_{1}},\langle a_{2}\oplus b_{2} \rangle_{m_{2}},\ldots,\langle a_{n}\oplus b_{n}\rangle_{m_{n}}), \tag{30}\]

where \(\oplus\) can be either the addition or the multiplication operator. This property is what makes RNS very efficient in applications that require a large number of these operations, such as DSP applications and, more recently, Neural Network inference. This is because, by decomposing the computations into independent channels, long carry propagation chains are eliminated, thus arithmetic circuits can operate at higher frequencies, or with reduced power dissipation.

The general architecture of a modulo adder is shown in Fig 7[79]. The design consists of an \(n\)-bit, adder, where n is the size of the channel, that performs the addition of two numbers \(a+b\), and a CSA adder which performs the computation of \(a+b-m_{i}\) (modulo operation). The sign of the CSA result is used to select the correct result of the two adders.

The selection of moduli can significantly simplify the design of modulo arithmetic circuits. In case of moduli of the form \(2^{k}\) the modulo operation translates into just keeping the \(k\) least significant bits, whereas in the case of \(2^{k}-1\), the output carry of the addition simply needs to be added to the result. In this case, end-around-carry adders can be used. For channels of the form \(2^{k}+1\), diminished-1 arithmetic can be used [80], which basically involves an inverted end-around logic. If the size of the channel is large, then fast adder designs such as prefix adders must be utilized within each channel.

Modulo multiplication is a trickier operation, however the benefits of RNS can be greater. This is because of the (approximately) quadratic scaling of a multiplier with the input size. This means that, by decomposing a large multiplication into smaller ones, the energy and delay savings
can be significant, providing that the overhead of the modulo is diminished. One approach for RNS multiplication is to perform regular multiplication of the two \(n\)-bit numbers and then use a reduction circuit to obtain the final result modulo \(m_{i}\). This approach introduces, however, considerable overhead to the design, as the reduction of a \(2n\)-bit number to a \(n\)-bit number modulo \(m_{i}\) is not as straightforward as in the case of addition. A low complexity adder-based combinatorial multiplier has been proposed in [81], where the number of FAs required is minimized. Other multiplication techniques are based on intermediate RNS transformations, such as _core functions_[82] and _isomorphisms_[79], which are transformations that convert multiplication into addition. These transformations utilize look-up tables to convert RNS to an intermediate representation where multiplication is translated into addition.

In the case of modulo \(2^{k}\) multiplication, regular multipliers operating only on the \(k\) LSBs can be used, whereas in the case of modulo-\((2^{k}+1)\) diminished-1 arithmetic can be applied [83]. A end-around-carry multiplier which can be used for \(2^{k}-1\) channels is shown in Fig. 8. Due to the properties of the particular channel, the modulo operation is translated into simple bit re-ordering, thus no overhead is introduced.

Based on the above, most of the RNS designs reported in literature utilize the low-cost forms of moduli, which allow

Fig. 5: Arithmetic processing elements of CNNs utilizing linear and various logarithmic quantization schemes (a) Linear quantization (b) Inputs logarithmic quantization (c) Weights logarithmic quantization (d) Inputs and weights logarithmic quantization, adapted from [76]

Fig. 6: Computation flow of RNS accelerators. Partially RNS-based accelerators utilize binary converters between successive layers for non-trivial RNS operations, while end-to-end systems perform all NN operations, including activation functions, in the RNS domain. Base-extension is usually required to increase the dynamic range before the accumulation of the partial products.

Fig. 7: Modulo adder [79]
to fully exploit the RNS benefits (elimination of long carry chains) with minimal hardware overhead.

#### Iv-B1 Conversions and Non-trivial Operations

While addition and multiplication are very efficiently implemented in RNS, other operations such as sign detection, comparison and division, or the realization of non-linear activation functions are not straightforward to implement, as the require the combination of the RNS channels. A common approach is to use RNS-to-binary converters and then perform the operation in the binary domain. Conversion to and from an RNS representation is a crucial for the performance of any RNS-based processing system. Especially for the architectures that perform frequent intermediate conversions (partially RNS-based) the overhead can be significant. The complexity of these converters largely depends on the particular base selection, namely the size, number and format of the moduli.

While _Binary-to-RNS_ or _forward_ converters can have a relative simple hardware realization, following Eq. 29, especially if particular forms of moduli are used, _RNS-to-binary_ or _inverse_ converters are generally harder to implement. Extensive bibliography exists for this topic. The most commonly used approaches are the Chinese Remainder Theorem (CRT) and the Mixed Radix Conversion (MRC) [84]. The CRT is expressed as

\[X=\left\langle\bigg{(}\sum_{i=1}^{n}\overline{m}_{i}\langle x_{i}\overline{m} _{i}^{-1}\rangle_{m_{i}}\bigg{)}\right\rangle_{M} \tag{31}\]

where \(\langle\cdot\rangle\) denotes the modulo operation, \(X\) is the binary representation of the number, \(x_{i}\) are its residues, \(m_{i}\) are the moduli, \(M\) is the dynamic range, \(\overline{m}_{i}=M/m_{i}\), and \(\overline{m}_{i}\)\({}^{-1}\) is the modulo inverse of \(\overline{m}_{i}\). CRT requires the pre-computation of \(\overline{m}_{i}\), and \(\overline{m}_{i}\)\({}^{-1}\), additions of potentially large products, as well as the final modulo operation with the \(M\), which can be very large. It can be computed, however, in a single cycle. In the other hand, MRC requires the computations

Fig. 8: Array multiplier for calculating \(x\cdot y\) mod \(15\). At each level \(i\), the full adders corresponding to the \(i\) most significant positions (dashed squares) are moved to the \(i\) least significant positions. This is possible because \(2^{n+k}\) mod \((2^{n}-1)=2^{k}\). A modulo-\(15\) carry-propagation adder is used to obtain the final result.
of some intermediate coefficients and is a sequential process which requires several steps, but these steps only include small bit-width operations. The Mixed Radix Conversion finds the coefficients \(k_{1},k_{2},\ldots,k_{n}\), such that

\[X=k_{1}+k_{2}m_{1}+k_{3}m_{1}m_{2}+\ldots+k_{n}m_{1}m_{2}\ldots m_{n-1} \tag{32}\]

The coefficients are calculated one by one in a number of steps [84], each of which requires the previously calculated coefficients. The modulo inverses can be pre-calculated and pipelining stages can be introduced to make this computation efficient.

Sign detection is one of the most critical and frequent operation required by NNs, as the Rectified Linear Unit (ReLU), which maps negative values to zero, is the most common activation function. In an RNS representation, numbers in the range \(0<X<R/2\) are positive, whereas numbers in the range \(R/2\leq x<M\) are negative. Magnitude comparison of two RNS numbers which is required for the MaxPooling layers, is also difficult to directly to implement in the RNS domain. Comparison algorithms for particular moduli sets (\(2^{k}-1,2^{k},2^{k}+1\)) [85], or more complex general ones have been proposed [86], that can eliminate the overhead of the conversion. If the choice of moduli is restricted to some specific bases, simple and efficient algorithms have been reported for sign detection [87] and comparison. Finally, division, which is necessary after the multiplication and accumulation operations of a convolutional layer for example, in order to bring the result in the original dynamic range, also requires special handling. Methods that use special form of moduli, such as powers of two [88] or a product of the moduli [89] as divisors can simplify the hardware implementation. Some methods rely on using small (only one-channel wide) lookup-tables and typically relay on base extension methods, during which an RNS base with \(k\) channels is extended to \(k+r\) channels.

### _Partially RNS-based Architectures_

A common approach in RNS-based DNN implementations is to perform all multiply-add operations of a single convolutional or dense layer in the RNS representation and then use a converter to obtain a partial result in normal positional binary representation [90, 91, 92, 93]. With this intermediate result, the non-linear activation functions (_ReLU_, \(\tanh\), _softmax_) can be computed and the results can be again converted to RNS format to be fed to the next layer.

Many application-specific AI accelerator designs, as well as more general purpose architectures, such as TPUs or GPUs, perform DNN computations by decomposing them into matrix or vector multiplication primitives. Thus, by utilizing efficient hardware matrix multipliers, performance can be orders of magnitude better than CPUs. An RNS TPU (Tensor Processing Unit) is proposed in [90]. In the core of this architecture there is a RNS matrix multiplier implemented as a two dimensional systolic array. Each processing element performs one operation (MAC) at each cycle, and passes the result to neighboring processing elements. Systolic arrays are an efficient way of increasing throughput and dealing with the limited memory bandwidth problem. In this particular RNS systolic array, each processing element decomposes the larger MAC operation (typically 8 or 16 bits), into smaller, each within the range of the respective channel, that can be performed in parallel. Using an FPGA implementation the RNS matrix multiplier is reported to perform a \(32\times 32\) fixed point matrix multiplication up to \(9\times\) more efficiently than a binary matrix multiplier for large matrices.

In [92] the authors extend the RNS usage to the implementation of the convolution operation. Individual layers are executed on an RNS-based FPGA accelerator. However results are sent to a CPU, which performs the non-trivial RNS operations, such as applying the activation functions, before being sent back to the FPGA for the execution of the next layer. RNS results in a \(7.86\%-37.78\%\) reduction of the hardware costs of a single convolutional layer compared to the two's-complement implementation, depending on the RNS base selection.

A variant of the Residue Number System, called the _Nested RNS_ (NRNS) is proposed in [91]. NRNS applies a recursive decomposition of the residue channels into smaller ones. Adder and multipliers can be thus implemented by using smaller and faster circuits. Assuming that a number \(X\) has a RNS representation of \((x_{1},x_{2},\ldots,x_{n})\), then the nested RNS representation will be of the form

\[X=(x_{1},x_{2},\ldots,(x_{i1},x_{i2},\ldots,x_{im}),\ldots,x_{n}) \tag{33}\]

where \((x_{i1},x_{i2},\ldots,x_{im})\) is the RNS decomposition of the \(i-th\) channel This technique introduces an additional complexity, as any operation must be recursively applied to each level of the representation, however it manages to handle large dynamic ranges with very small channels. The authors use a 48-bit equivalent dynamic range composed only of 4-bit MAC units which can be realized by look-up tables of the FPGA. Contrary to [92], which relies on an external CPU, in this work binary-to NRNS and NRNS-to-binary conversions are realized by DSP blocks and on-chip BRAMs. After Input data are converted into the NRNS representation, a number of parallel convolutional units perform all the necessary computations of a single convolutional layer. The results are then converted to binary using a tree-based NRNS-to-binary converter. The authors report a performance per area improvement of \(5.86\times\) compared to state-of-the-art FPGA implementations for the ImageNet benchmark. In a different approach the RNS arithmetic costs are reduced by restricting the RNS base selection to low-cost moduli of the form \(2^{k}\pm 1\)[93]. This way, modified fast prefix adders and CSA trees using end-around-carry propagation can be used, diminishing any overhead of the modulo operator.

In another category of RNS-based architectures, the usage of very small channels allows the realization of multiplier-free CNN architectures. The authors utilize a small RNS base of (3,4,5) and reduce the implementation of the multiplications to shifts and additions [94]. Despite the reduced dynamic range of the representation, the authors report minimal accuracy loss, while achieving \(36\%\) and \(23\%\) reduction in power and area, respectively. A method to drastically reduce the number of multiplications in CNN RNS-bases accelerators is proposed
in [95]. It utilizes a modified hardware mapping of the convolution algorithm where the order of operations is rearranged. Because of the small dynamic range of each RNS channel, there is an increased number of common factors inside the weight kernels during convolution. By first executing the additions of the input feature map terms that correspond to the same factors, and then performing the multiplications with the common weight factors, a \(97\%\), reduction of the total multiplications is reported for state-of-the-art CNN models.

### _End-to-end RNS Architectures_

While the above circuits manage to achieve some performance gain in the implementation of a single convolutional layer, they require significant amounts of extra hardware to perform the conversions which can become the bottleneck for some of these designs. More recent approaches focus on overcoming the difficulties of performing operations such as sign detection, comparison, and scaling which is usually required following multiplication. In these approaches, input data are initially converted to an RNS representation and then the entire processing takes place in the RNS domain.

#### Vi-C1 State-of-the-art End-to-end RNS Architectures

The system in [96] introduces some novel mechanisms for dealing with this problem and proposes an efficient fully RNS-based architecture. The authors of this work choose to work with moduli of the form \(2^{k}-1\), \(2^{k}\), \(2^{k+1}-1\). In particular they select (31,32,63) as the basis of their representation, as it is found to provide a sufficient dynamic range (16-bit equivalent), that results in no accuracy loss, for state-of-the-art networks and benchmarks. For the design of the modulo adders, which are simplified due to the particular selection of the moduli, parallel-prefix Sklansky adders with an end around carry are utilized. For the multiplications, a radix-4 Booth encoding is adopted within each channel. An optimized sign detection unit for this set of moduli is used, based on an approach proposed in [87]. which can be further transformed and result in a relatively hardware-friendly implementation. Using a similar logic to the work proposed in [85], the comparison of two RNS numbers can also be implemented by calculating auxiliary partitioning functions.

The authors also introduce a base extension mechanism which is necessary in order to avoid potential overflow when accumulating the partial sums. In this work, a base extension method proposed in [97] is used, where the middle channel is extended from \(2^{k}\) to \(2^{k+e}\). This way the convenient properties of the chosen moduli are maintained. Base extension takes places once before each multiplication to ensure that the product lies within the dynamic range and then again before the accumulation. The authors define the number of extra bits that are added each time based on extensive simulation on benchmark networks and on a per-layer basis. RNS circuits result in significant delay and energy efficiency improvement, especially in the case of multiplication at the cost of larger overall area. Comparisons in terms of various performance metrics against the Eyeriss [98] accelerator are reported for various networks. Up to 61% reduction in energy consumption compared to the conventional positional binary representation has been achieved. The system can also support an increased clock frequency as high as \(1.20\) GHz versus \(667\) MHz in the case of the positional binary system, indicating a 1.8\(\times\) improvement in computational latency.

#### Vi-C2 In-Memory Computing RNS Architectures

Recently, there has been a growing focus of AI accelerator design research on in-memory computing. This is because of the paradigm-shifting effect that emerging memory technologies can have on processing systems. It is known that the largest part of the energy consumption of any DNN accelerator is due to the memory accesses and data transferring, particularly to and from the off-chip RAM. In-memory computing (IMC) aims to diminish data transfer costs by bringing the computing inside or near the memory elements.

Efforts have been made to bring the benefits of the RNS to IMC systems. In these (mainly digital) IMC designs, the benefit of the usage of RNS over binary representation stems from the speedup of the bitwise serial addition operations, due to the inherent parallel operations of the RNS channels.

RNS has been utilized in the design of an in-memory computing system [99]. In this work, the selected moduli are of the form \(2^{k}-1\), \(2^{k}\), \(2^{k}+1\). A sign detection mechanism similar to [87], is developed, in order to implement the ReLU and MaxPooling operations without having to convert to a binary representation. Addition and multiplication within each RNS channel, take place inside the memory elements. Multiplication of two numbers, \(a,b\) is implemented through addition and memory accesses by calculating the quantity \(\frac{(a+b)^{2}}{4}-\frac{(a-b)^{2}}{4}\), where squaring is implemented using look-up-tables. A single crossbar memory is assigned to each neuron and supports in-memory addition in a tree-based structure. For this purpose, a Memristor Aided loGIC (MAGIC) is used. Based on experimental results, the proposed RNS in-memory architecture consumes 145.5\(\times\) less energy and leads to a speedup of \(35.4\times\) compared to NVIDIA GPU GTX 1080.

An near-memory RNS-based processing architecture is proposed in [100]. Instead of memristor-based memory macros, a DRAM computational sub-array is utilized for the implementation of the MAC operations in the RNS domain, combined with parallel-prefix adders, to implement bitwise multiplication and accumulation. Unlike [96], where multiplication is directly implemented in memory (by mapping to additions and squaring), here they are implemented by combining elementary bit-wise operations (AND, OR, XOR) between the operands. The authors also design a more flexible activation function unit which is based on a Mixed-Radix conversion. Similar to [96], an RNS base of \((2^{k}-1\), \(2^{k}\), \(2^{k+1}-1)\) is utilized. Gains in the order of \(331-897\times\) in terms of energy efficiency compared to GPU platforms are reported, and \(2\times\) compared to other IMC designs.

### _Summary of RNS-based DNN architectures_

RNS-based architectures targeting DNN applications are summarized in Table III. The majority of these approaches utilize low cost moduli of the form \(2^{k}-1\), \(2^{k}\), \(2^{k}+1\) to reduce the overhead of the modulo operator and are targeting CNNs. Most of these RNS accelerators can achieve speedups
in the order of \(1.5-3\times\) and can also me more energy efficient. IMC RNS-based systems exhibit the largest energy savings. Among conventional systems, [96] illustrates more clearly the applicability of the RNS in DNN architectures by proposing a fully RNS system which outperforms the binary state-of-the-art counterpart. The RNS usage is also extended to LSTM networks, by designing hardware friendly RNS activation units for the implementation of \(tanh\) and \(sigmoid\) functions [101].

In conclusion, the Residue Number System (RNS) can be an attractive number representation choice for DNN accelerators, and several RNS-based architectures have been reported recently targeting AI applications, due to its various advantages. RNS exhibits inherent parallelism at the residue channel processing level. It utilizes parallel computations along separate residue channels, where operations in each of them are performed modulo a specific modulus, with no need for information (carry or other) to be shared between residue channels.

The main challenge in designing an efficient RNS-based accelerator is to minimize or, possibly, eliminate the overhead introduced due to the implementation of the non-linear operations. Another key factor is the optimization of the moduli selection and the corresponding arithmetic circuits, to meet the accuracy requirements.

Some of the RNS systems proposed in recent literature only perform the multiply-add (MAC) or matrix multiplication operation, required by the convolutional layers, in the RNS representation, and use intermediate converters between number systems for the non-linear operations. More recently, completely RNS-based approaches have been proposed that eliminate the overhead introduced by these intermediate conversions to and from a traditional positional binary representation.

## V BFP for DNN Architectures

BFP representation offers a middle ground between FLP and FXP formats. This representation is proposed to preserve accuracy comparable to full precision FLP and hardware efficiency comparable to FXP. This is achieved by representing numbers with an exponent and a mantissa similar to FLP to guarantee a wide dynamic range. However, instead of representing each value separately, a group (called here a block) of values has a common exponent while maintaining private mantissa. Let \(N\) be a tensor that represent a block of \(t\) elements initially represented in FLP as

\[N =(n_{1},\ldots n_{i},\ldots n_{t}), \tag{34}\] \[=((-1)^{s_{1}}\ m_{1}\ 2^{e_{1}},\ldots(-1)^{s_{i}}\ m_{i}\ 2^{e_{i}},\ldots(-1)^{s_{t}}\ m_{t}\ 2^{e_{i}}).\]

This block is represented with BFP format as \(\hat{N}\) such that

\[\hat{N} =(\hat{n_{1}},\ldots\hat{n_{i}},\ldots\hat{n_{t}}), \tag{35}\] \[=((-1)^{s_{1}}\ \hat{m_{1}},\ldots(-1)^{s_{i}}\ \hat{m_{i}},\ldots(-1)^{s_{t}}\ \hat{m_{t}})\times 2^{e_{N}},\]

where \(\epsilon_{N}\) is a shared exponent between the elements of block \(N\), and \(\hat{m_{t}}\) is the aligned mantissa of element \(i\) such that \(\hat{m_{i}}=\mathbf{BS}(m_{i},e_{i}-\epsilon_{N})\), where \(\mathbf{BS}\) is the bit-shift operation. For large difference between the Private and shared exponents (\(e_{i}-\epsilon_{N}\)), this shifting causes some of the least-significant bits of the mantissa to be truncated. The truncation happens frequently when there are many outliers in a block, which in turn depends on the size of the block and the way the shared exponent is selected.

Since the dot product is the basic operation involved in DNN inference and training, the main target of BFP is to simplify the complex hardware required to perform this operation when FLP is used. For two blocks \(\hat{N_{1}}\) and \(\hat{N_{2}}\) represented in BFP, the dot product is calculated as

\[\hat{N_{1}}.\hat{N_{2}}^{T} =((-1)^{s_{1,1}}\ m_{1,1}^{\prime},\ldots(-1)^{s_{t,1}}\ m_{t,1} )\times 2^{e_{N_{1}}}. \tag{36}\] \[((-1)^{s_{1,2}}\ m_{1,2}^{\prime},\ldots(-1)^{s_{t,2}}\ m_{t,2} ^{\prime})^{T}\times 2^{e_{N_{2}}}\] \[=2^{e_{N_{1}}+\epsilon_{N_{2}}}\sum_{i=1}^{t}(-1)^{s_{i,12}}\hat{ m_{i,1}}\times\hat{m_{i,2}},\]

where \(s_{i,j}\) and \(m_{i,j}\) are the sign and mantissa of the \(i^{th}\) element in the \(j^{th}\) block, respectively, \(\epsilon_{N_{j}}\) is the shared
exponent of the \(j^{th}\) block, \(s_{i,12}\) results from XORing \(s_{i,1}\) and \(s_{i,2}\), and \(T\) stands for transportation. Equation (36) shows that the dot product of two blocks of size \(t\) represented in BFP involves \(t\) FXP multiplications of mantissa, \(t-1\) FXP additions of the products, and one addition of the two shared exponents. The additional overhead compared to FXP representation comes from the hardware required to handle the shared exponent which mainly depends on the number of the blocks [17]. As a result, the performance of DNN in presence of BFP representation is determined by block partition scheme, shared exponent selection, and the bit-width of the mantissa and shared exponent, which will be discussed next.

### _BFP Block Design_

Determining how the blocks are partitioned is essential to achieving good DNN performance with BFP [102, 103]. Usually, the input activation of each layer is considered as one block, whereas the weight matrix needs a specific scheme to be divided into blocks. There are two known blocking approaches, filter-based blocking [102, 103, 104, 105, 23, 106, 23] and tile-based blocking [108, 109, 71, 110, 111], illustrated in Figure 9(a) and Figure 9(b), respectively. In the filter-based blocking, each filter of weights along the input channels is considered a block. Then the total number of blocks equals to the number of filters. This blocking is usually called coarse-grain blocking and it is the most hardware-friendly blocking approach as the accumulation of each output activation is done with the same shared exponent. Thus, it can be done using the FXP arithmetic [102]. However, this approach may end up with severe accuracy degradation due to the increased number of outliers that need to be truncated within these large blocks.

On the other hand, the tile-based blocking is proposed to strike a compromise between accuracy and hardware efficiency. This approach relies on breaking large matrices of the filters down into small tiles to fit into limited hardware resources. Each tile is considered as a block with a shared exponent. The size of these tiles is a metric that need to be optimized. For example, a large tile of size 576 is used in [110] which requires a 12-bit mantissa to obtain acceptable accuracy. However, the authors in [109] showed that 12-bit FXP can achieve similar accuracy with simpler hardware implementation. This indicates that BFP may has no advantage over FXP for such large tiles. Smaller tiles of 16 elements are used in [71, 17] seeking better accuracy, but with an added hardware complication comes from the need to convert to FLP before the accumulation.

### _Shared Exponent Selection_

One shared exponent for each block need to be selected after partitioning the blocks4 and whenever a new block is created with multiple shared exponents. For example, this exponent is aligned after performing the calculation of each DNN layer as the calculation of the output activation usually ends up with a matrix of multiple exponents [103]. To this end, most of DNN accelerators that adopt BFP calculate the shared exponent dynamically during DNN training or inference. Static shared exponent selection can be utilized prior to DNN inference.

Footnote 4: As the case of partitioning the weight blocks prior to DNN inference, which is usually performed offline.

One of two schemes is usually used for this dynamic shared exponent selection; maximal exponent-based or statistics-based schemes. The dynamic maximal exponent selection scheme is more popular [112, 113, 114]. In this scheme, for each block of (34), different floating point numbers \(n_{i}\) are compared and the maximum exponent is selected as follows

\[\epsilon_{N}=\max_{e^{i}}:i\in 1,\ldots,t. \tag{37}\]

To find this maximal exponent before performing the dot product between weights and activations result from previous layer, the output activations represented in BFP with several exponents need to be converted back into FLP, which adds large overhead on the performance and the resources.

To keep the advantage of the dynamic calculation of the shared exponent while avoiding frequent conversion between BFP and FLP the statistics-based scheme is proposed to predict the shared exponent during DNN training [115, 23]. In this scheme, the optimal exponent for each block is predicted based on statistics collected in the previous learning iteration. For example, in [23] the maximum value recorded within each block is stored for the last \(i\) iterations. Then, the maximum and the standard deviation of the stored values are used to calculate the shared exponent for the next iteration. This scheme works because the values within each block change slowly during the training. However, although this scheme avoids the conversion to FLP to calculate the exponent, some additional overhead is required to store the recorded statistics for each block. Thus, this scheme is suitable for the case when the number of blocks is relatively small.

The static shared exponent scheme is presented to get rid of exponent calculation overhead when the BFP is employed for CNN inferences rather than training [105, 106, 116, 117]. Instead of dynamically calculating the shared exponent during run-time, the shared exponent can be set to a constant value estimated offline. The common approach to determine the shared exponent offline is to minimize the Kullback-Leibler (K-L) divergence [117] between FLP32 distribution and BFP distribution of all blocks before the inference. By doing so, the extra memory and computational resources used for the exponent and the conversion between BFP and FLP are eliminated [17]. Because the input and output activations may

Fig. 9: Different blocking Schemes, different colors indicate differed blocks
have different shared exponents, a bit shifting is needed after each layer calculation, Figure 10(c). Figure 10 summarizes the dataflow of the BFP when each of the three shared exponent determination schemes is adopted.

### _BFP Precision_

The precision of BPF is determined by the number of bits allocated for both the shared exponent and mantissa. Reducing this precision is an objective to increase the arithmetic efficiency and memory bandwidth. At the same time, the over-reduced bit-width of the mantissa results in what is known as zero setting problem [118]. This problem occurs when all the bits of the mantissa are shifted out resulting in a zero number representation, despite the presence of the exponent value. The over-reduction of the shared exponent number of bits is much worse. This is because of insufficiency to represent the actual exponent of the block, and thus the caused truncation ruins the correct representation of all numbers in the block.

This precision is usually either static [102, 103, 104, 105, 106, 107, 111, 112, 113, 114, 115, 116, 119] or dynamic [109, 118]. In the static precision, the number of bits is fixed and selected offline. To select the best precision, usually few experiments are performed using different number of bits [105, 104, 115]. This gives an insight on the impact of this metric on the performance of DNN and allows for picking the minimum number of bits that preserve acceptable accuracy or the one that gives the best trade of between hardware efficiency and accuracy. Reducing the mantissa bit-width was paid attention in the literature because the performance of DNN is less sensitive to mantissa reduction compared to shared exponent. For example, 23-bit mantissa, same as the case of FLP, is required to guarantee the convergence of the Q-learning in [115], whereas 8-bit mantissa, or even less, was found to be sufficient for other CNN accelerator designs [109, 116, 117, 102, 103, 104, 105, 106, 107, 111, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 22, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 282, 284, 286, 287, 288, 289, 291, 285, 289, 286, 288, 289, 292, 287, 288, 289, 293, 288, 289, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 325, 33, 34, 35, 36, 37, 38, 39, 311, 32, 34, 36, 38, 39, 32, 35, 37, 39, 33, 36, 38, 39, 33, 39, 34, 37, 39, 35, 39, 36, 37, 39, 38, 39, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 82, 84, 85, 87, 89, 91, 80, 83, 84, 85, 86, 88, 89, 92, 85, 87, 88, 89, 93, 94, 88, 89, 95, 89, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 111, 116, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 211, 212, 213, 214, 215, 216, 217, 218, 219, 22, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 251, 252, 253, 254, 255, 256, 257, 258, 259, 261, 259, 270, 272, 274, 275, 276, 277, 278, 279, 289, 290, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 291, 289, 292, 293, 285, 286, 287, 288, 289, 294, 295, 288, 289, 296, 297, 298, 300, 311, 320, 31, 325, 34, 35, 36, 37, 38, 39, 301, 33, 34, 36, 38, 39, 31, 35, 37, 39, 31, 36, 38, 39, 302, 303, 31, 325, 34, 36, 38, 39, 31, 304, 305, 306, 307, 308, 309, 310, 325, 34, 36, 38, 39, 31, 33, 34, 35, 36, 39, 31, 34, 37, 39, 31, 35, 36, 39, 31, 304, 305, 306, 307, 308, 311, 325, 34, 36, 39, 31, 308, 31, 309, 32, 309, 33, 31, 34, 309, 32, 35, 36, 37, 39, 31, 37, 39, 31, 38, 39, 31, 39, 32, 33, 34, 35, 37, 39, 31, 39, 33, 34, 36, 39, 32, 37, 39, 33, 34, 38, 39, 35, 39, 303, 310, 32, 34, 36, 39, 32, 35, 36, 39, 37, 39, 31, 38, 39, 304, 305, 306, 307, 308, 310, 32, 34, 39, 31, 34, 39, 32, 35, 36, 39, 31, 39, 33, 34, 39, 33, 35, 37, 39, 31, 39, 34, 35, 36, 39, 31, 37, 39, 32, 34, 39, 35, 37, 39, 31, 39, 33, 36, 39,
efficient hardware capable of performing CNN training phase without ruining the accuracy, this representation got the same amount of attention for highly accurate inference hardware implementation. Most of these architectures achieved negligible accuracy degradation compared to FLP even with less than 8-bit mantissa [17, 109, 120]. Different implementations make use of different combinations of the discussed design choices, thus, the reported results of these works can't be used to prove the superiority of a specific design choice over the others. However, we can conclude that there is no clear trend in the accuracy enhancement when tile-based blocking is used instead of a filter-based one.

## VI DFXP for DNN Architectures

DFXP representation shares the same concept of BFP discussed in Section V and sometimes the notations DFXP and BFP are used interchangeably. As in the case of BFP, in DFXP, the values are grouped and different scaling factors (i.e., shared exponents) are used for different groups. Thus, a scaling factor is unique for each group (e.g., layer). In some cases, it can be changed from time to time (i.e., dynamic). This is compared to the case of FXP which assigns a single global scaling factor for the whole DNN architecture all the time. To this end, Equations (34,35,36) are applicable to DFXP. Although several works use the term DFXP to indicate a representation similar to BFP [113, 124, 123, 114], the majority of works use DFXP to indicate FXP representation provided with flexibility to change the place of the decimal point, that specifies the length of the integer and fraction parts for each group of values, Figure 1d. This requires that a scaling factor \(\epsilon_{N}\) of a group \(N\), (35), to be in the range \([-w_{N},0]\), where \(w_{N}\) is the bit-width used to represent elements of a group \(N\)[125, 126, 127]. Hence, DFXP representation can be reduced to \(<I_{N},F_{N}>\) format where \(I_{N},~{}F_{N}\) are the number of bits allocated to the integer and fractional parts, respectively, for all values within a group. Such that \(w_{N}=I_{N}+F_{N}\) and \(\epsilon_{N}=-F_{N}\). Thus, the zero setting problem frequently happens with BFP will not appear for the DFXP at the expense of limited dynamic range, but still better than the one of FXP. We will limit our discussion on these works in this section, whereas the other works that use DFXP notation to indicate BFP are discussed in Section V although they use the term DFXP.

A notable difference between DNN architectures that use BFP and DFXP is that the latter gives less attention to the way that the groups (i.e., blocks) are partitioned. The common grouping approach for DNN architecture based on DFXP is to consider the weights, biases, input activation, and gradients vectors (when DFXP is used to accelerate training) for each layer as separate groups and thus associated with different scaling factors [128, 129, 130, 131, 132, 133, 134]. Only one architecture presented in [40] statically clusters the filters (i.e., weights) that accumulate to the same output activation of each layer. Then, each cluster represents a group that has its unique scaling factor. The quantization error is effectively reduced with smaller clusters (e.g., when a cluster contains 4 filters) since smaller groups tend to have smaller range of values.

The main differences between the DFXP representation in different works are the way of finding the best scaling factor \(F_{N}\) and determining the bit-width \(w_{N}\). The approaches used to optimize the decimal point Position and specify the precision of DFXP are classified in the next subsections.

### _Group Scaling Factor Selection_

The scaling factor (i.e., \(F_{N}\)) assignment to each group in DFXP is usually performed in an offline or online manner. The offline assignment is usually used when the architecture is implemented for inference purpose [128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140]. The common approach for the offline assignment depends on finding the minimum integer bit-width \(I_{N}\) that accommodates the maximum value within a group as in

\[I_{N}=\log_{2}(\max(|n_{max}|,|n_{min}|)), \tag{38}\]

where \(n_{max}\), \(n_{min}\) are the maximum and minimum values within a group \(N\). The remaining bits \(w_{N}-I_{N}\) are allocated to the fractional part \(F_{N}\). This approach is used for example in [126, 128]. However, as the presence of outliers in a group results in an unnecessary increase in the integer bit-width, the outliers can be excluded before calculating the bit-width \(I_{N}\)[126]. Several works minimize the impact of the outliers by selecting a scaling factor that minimizes the error between computed and real values [127, 130, 135]. For instance, K-L divergence between FLP32 and DFXP weight distributions is used in [127], whereas a greedy algorithm is utilized in [130] to determine the best scaling factor.

The online scaling factor selection is needed for the training phase in which the values within each group change frequently [123, 127, 129, 133, 141, 142, 143, 142, 143]. Usually, the scaling factor is updated at a given frequency based on the rate of overflow during the training. When the current integer part fails to handle a value in a group, the overflow rate increases. The overflow rate is compared to a threshold to decide whether this scaling factor should be increased or decreased. This threshold can be deterministic and predefined [129, 133, 141, 142], or stochastic [143].

Fig. 11: Example of how the distribution of weights (a), activations (b) and weight updates (c) changes during different DNN training iterations [23]
\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|} \hline Ref. & Phase & DNN & \begin{tabular}{c} Exponent \\ selection \\ \end{tabular} & \begin{tabular}{c} Block \\ design \\ \end{tabular} & \multirow{2}{*}{Dataset} & \multirow{2}{*}{Model} & \multirow{2}{*}{
\begin{tabular}{c} Mainissa \\ bits \\ \end{tabular} } & Accuracy & Area & Power & Speed \\  & & & & & & & & & & \\ \hline
[23] & \begin{tabular}{c} Training, \\ inference \\ \end{tabular} & \begin{tabular}{c} CNN, \\ \end{tabular} & \begin{tabular}{c} Dynamic, \\ GANs \\ \end{tabular} & \begin{tabular}{c} Filter-based \\ statistics \\ \end{tabular} & \begin{tabular}{c} CIFAR-10, \\ LSUN \\ \end{tabular} & 
\begin{tabular}{c} AlexNet, \\ WGAN \\ \end{tabular} & 16 & \(\thicksim 0\) & - & - & - \\ \hline
[112] & \begin{tabular}{c} Inference \\ \end{tabular} & \begin{tabular}{c} CNN \\ \end{tabular} & \begin{tabular}{c} Dynamic, \\ max \\ \end{tabular} & \begin{tabular}{c} Tile-based \\ \end{tabular} & \begin{tabular}{c} ILSVRC \\ \end{tabular} & \begin{tabular}{c} AlexNet \\ DenseNet \\ \end{tabular} & 10 & \(\thicksim 0\) & - & - & - & 
\begin{tabular}{c} 10 \\ (\(\{\)121\(\}\)) \\ \end{tabular} \\ \hline
[103] & \begin{tabular}{c} Inference \\ \end{tabular} & \begin{tabular}{c} CNN \\ \end{tabular} & \begin{tabular}{c} Dynamic, \\ max \\ \end{tabular} & \begin{tabular}{c} Filter-based \\ CIFAR10 \\ \end{tabular} & 
\begin{tabular}{c} MNIST, \\ ResNet-18, \\ ResNet-50, \\ GoogLeNet \\ \end{tabular} & 8 & \(<\)0.3 & - & - & - \\ \hline
[110] & \begin{tabular}{c} Training, \\ inference \\ \end{tabular} & \begin{tabular}{c} CNN, \\ RNN \\ \end{tabular} & \begin{tabular}{c} Dynamic, \\ max \\ \end{tabular} & Tile-based & \begin{tabular}{c} CIFAR-100, \\ SVHN, \\ ImageNet \\ \end{tabular} & \begin{tabular}{c} ResNet, \\ WideResNet, \\ DenseNet \\ \end{tabular} & 8 & \(<\)1 & - & - & 
\begin{tabular}{c} 8.5 \\ (\(\{\)PLP16\(\}\)) \\ \end{tabular} \\ \hline
[108] & \begin{tabular}{c} Inference \\ \end{tabular} & \begin{tabular}{c} CNN \\ \end{tabular} & \begin{tabular}{c} Dynamic, \\ max \\ \end{tabular} & Tile-based & Sports-1M & Custom & 15 & 0.4 & - & \begin{tabular}{c} 92 \\ (\(\)Intel 17.950) \\ \end{tabular} & 
\begin{tabular}{c} 8.2 \\ (\(\)Intel 17.950) \\ \end{tabular} \\ \hline
[107] & \begin{tabular}{c} Inference \\ \end{tabular} & \begin{tabular}{c} CNN \\ \end{tabular} & \begin{tabular}{c} Dynamic, \\ max \\ \end{tabular} & \begin{tabular}{c} Filter-based \\ \end{tabular} & \begin{tabular}{c} ImageNet \\ ResNet-50 \\ \end{tabular} & 8 & \(<\)0.14 & - & 
\begin{tabular}{c} 31 \\ (\(\)PLP16\(\{\)122\(\}\)) \\ \end{tabular} & - \\ \hline
[102] & \begin{tabular}{c} Inference \\ \end{tabular} & \begin{tabular}{c} CNN \\ \end{tabular} & \begin{tabular}{c} Dynamic, \\ max \\ \end{tabular} & \begin{tabular}{c} Filter-based \\ CIFAR10 \\ \end{tabular} & \begin{tabular}{c} ImageNet, \\ VGG16, \\ GoogLeNet, \\ ResNet-50 \\ \end{tabular} & 8 & 0.12 & - & 
\begin{tabular}{c} 15 \\ (\(\)PLP16\(\{\)122\(\}\)) \\ \end{tabular} & 3.76 \\ \hline
[104] & \begin{tabular}{c} Training, \\ inference \\ \end{tabular} & \begin{tabular}{c} CNN \\ \end{tabular} & \begin{tabular}{c} Dynamic, \\ max \\ \end{tabular} & \begin{tabular}{c} Filter-based \\ Filter-based \\ CIFAR10 \\ \end{tabular} & 
\begin{tabular}{c} ImageNet, \\ CIFAR-164 \\ \end{tabular} & 8 & \(<\)3 & - & - & - \\ \hline
[119] & \begin{tabular}{c} Training, \\ inference \\ \end{tabular} & \begin{tabular}{c} CNN \\ \end{tabular} & \begin{tabular}{c} Dynamic, \\ max \\ \end{tabular} & \begin{tabular}{c} Filter-based \\ Filter-based \\ CIFAR-10 \\ \end{tabular} & \begin{tabular}{c} MNIST, \\ CIFAR-164 \\ \end{tabular} & 8 & 0.1 & - & - & 
\begin{tabular}{c} 17 \\ (\(\)ARM AS3\(\}\) \\ \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\) \(\(\) \(\)
The stochastic thresholding is presented because the lower deterministic threshold results in inaccurate representation for small values while the higher threshold causes large clipping error [143], Figure 12. The random shuffling between higher and lower thresholds is found to be effective in compensating for the accuracy degradation of the low-precision training (less than 6 bits).

### _DFXP Precision_

The bit-precision of DFXP (i.e., \(w_{N}\)) can be static, mixed, or dynamic with different trade-offs between accuracy and hardware efficiency. The static precision, which is used in [126, 127, 134, 136, 139, 141], indicates that the number of bits is statically specified prior and is kept fixed for all groups during the training or inference, i.e., \(w_{N_{i}}=w_{c}\) for \(i=1,\ldots,N_{t}\), where \(N_{t}\) is the total number of groups associated with a specific DNN architecture. The advantage of this scheme is its simplicity from the hardware efficiency point of view. However, the selected precision is not optimal for all groups, layers, and architectures [143].

On the other hand, in the mixed-precision scheme, the bit-width, which is determined offline as well, can be different for different groups [125, 40]. The need for mixed-precision mainly comes from the fact that different groups (such as weights and activations) have different required dynamic ranges and thus different required number of bits [138]. As the activation results from the convolution accumulation, it is usually allocated more bits. For instance, using DFXP with 4-bit wights and 8-bit activations gives an accuracy degradation within 2% of the full precision using the Resnet-50 CNN model on the ImageNet dataset [40]. In other works, different precision is allocated to different groups in different layers [135, 125]. The authors in [125] stated that a specific fully connected layer activation is more sensitive to bit reduction and it is better to be allocated 16 bits while the activation bit-width of the other layers can be shrink to 8 bits. This mixed-precision allows them to achieve a 55.64% saving for weights' storage and 69.17% for activations' memory traffic with less than 2.5% loss in the accuracy when the Alexnet model and ImageNet dataset are used. The experiments in [135] show similar results. They found that the groups in shallower layers are less robust to bit reduction than the ones in deeper layers. In addition, the computation of the first and the last network layers should use high bit-precision to achieve better performance. To optimize the mixed-precision for different groups and to reach the above conclusions, the authors in [135] adopted an iterative bit-precision reduction scheme that aims to discover the groups for which the bit precision can be reduced without causing noticeable performance degradation. When DFXP with mixed-precision is used for training, sometimes different bit-widths are used for the weights during the updates than during the forward and backward propagations [27]. Using higher precision for the weight updates allows for the small changes in the weights to be accumulated precisely.

The use of DFXP with dynamic precision is presented to adjust the bit-width on-the-fly during training to enable speeding up this process [129, 143, 142]. The scheme in [129, 142] suggests starting with an aggressive initial target bit-width and monitoring the training loss as a feedback from the training process. If the training becomes unstable, the bit-width is increased to its maximum value. Afterward, the target bit-width is gradually increased by a unit step for the next trial. This procedure is repeated until reaching the minimum target bit-width that allows for stable training. To maintain the low overhead of this algorithm, it is activated once after each forward/backward computation to find the global bit-width of DNN architecture. A simpler search-based scheme to adapt the bit-width of each layer is suggested in [143]. In this scheme, the convolution is calculated in presence of low and high bit-widths at the same time for several iterations per epoch. If the difference between the high and low precisions is higher than a predefined threshold, the bit-width increases starting from the next iteration till the end of the epoch. After applying this scheme to different datasets and different CNN models, an interesting conclusion was that different datasets require different average bit-widths even if the same model is used.

One added complication of utilizing the dynamic bit-width is the need to design a configurable processing unit that can be configured to compute with various bit-widths during run-time. Thus, the efficiency of the dynamic precision scheme is highly affected by the hardware's supportability of the bit-width levels. Two relatively high bit-width levels (32 bits and 64 bits) are adopted in [129]. The baseline precision to prove the efficiency of their proposed approach is 64 bits which is relatively high training precision compared to other works. On the other hand, [143] could train the CNN with negligible loss of training and testing accuracy using an average bit-width less than 8. This is because they were able to use finer bit-width levels thanks to the bit-slice serial architecture they proposed.

### _Summary and Discussion of DFXP-based DNN Architectures_

DFXP and BFP are very similar representations. DFXP can be considered as a subset of BFP with less dynamic range and less hardware complication at the same time. For example, when the DFXP representation is used for CNN inference, the only additional hardware required over the FXP is a simple bit-shifter to align the output activation with the scale factor of the next layer input activation [136, 138]. This simplicity makes it appealing for many DNN architectures [27, 40, 113, 123, 144, 124, 125, 145, 146]. By considering the number of accelerators in the literature that utilize each representation, DFXP can be considered the most widely used alternative number system. The widespread of DFXP can be attributed

Fig. 12: Comparing the deterministic and stochastic thresholds for online scaling factor selection [143]
to its simplicity and to implementing it in some of publicly available DNN frameworks, such as Ristretto [128]. Several of the DFXP-based DNN architectures used this representation without much contribution to the proposed vanilla DFXP. Other works used different approaches to select the scaling factor of each group and to optimize the bit-width of this representation. Different approaches used for these design metrics are discussed and compared above.

## VII Posit for DNN Architectures

Posit number system, also known as type III universal number (Unum) system [147, 148, 149], is a floating-like format that is proposed to overcome several shortcomings of FLP representation [148]. Compared to FLP, Posit uses the bits more efficiently (allows for better accuracy with the same number of bits) [150], and has better accuracy and dynamic range [148, 151]. Figure 1e illustrates Posit representation. The \(w\) bits Posit number representation consists of four fields; a sign (1 bit), a regime (of variable length \(rs\in[1,w-1]\)), an exponent \(e\) (unsigned integer of fixed length \(es\)) and a mantissa (of variable length \(ms=w-rs-es-1\)). The regime field contains \(d\) consecutive identical bits and an inverted terminating bit (i.e., \(rrr\ldots r\))5.

Footnote 5: This is the general case when \(rs<(w-1)\). Otherwise, the regime pattern can be \(rrr\ldots r\) when it is terminated by the end of the \(w\) bits [152].

The numerical value of a real number \(n\) is represented in the Posit format (by \(\hat{n}\) ) as follows:

\[\hat{n}=(-1)^{s}\times u^{k}\times 2^{e}\times(1+\frac{m}{2^{ms}}), \tag{39}\]

where \(s,\,e,\,\text{and}\,\,m\) are the values of the sign bit, exponent and mantissa, respectively. The used \(u\), and \(k\) are calculated in (40) and (41) with the same order.

\[u=2^{2^{es}}, \tag{40}\]

\[k=\left\{\begin{array}{ll}-d,&\text{if }r=0.\\ d-1,&\text{if }r=1,\end{array}\right. \tag{41}\]

Posit representation is commonly characterized by two parameters, mainly \(w\) and \(es\), and defined as Posit(\(w\),\(es\)) [147, 153]. The parameter \(es\) is used to control the trade-off between the precision and the dynamic range [147]. When the Posit is intended to be used for DNN, these parameters are usually specified in an offline manner regardless of whether this architecture targets DNN training or inference [147, 148, 153, 154]. The selection of these parameters is done usually by experimenting with different parameters and selecting the parameters that give the best accuracy [154] or the parameters that offer the best balance between the accuracy and hardware efficiency. For instance, when the exponent length is set to \(es=1\) in [155] a better trade-off between accuracy and energy-delay-product is obtained for \(w=7\) and \(w=5\). On the other hand, the author in [153] decided to eliminate the exponent part (i.e., \(es=0\)) as the Posit, in this case, better represents the dynamic range of the used DNN weights.

There are two main differences between Posit and FLP representations, Figure 1e and 1a. The first difference is the presence of the regime field, and the second is the variability of the mantissa bit-length. Indeed, the innovation in the Posit format comes from its ability to allocate more bits to the mantissa when the represented number is very small (i.e., higher precision) and fewer bits for large numbers (i.e., larger magnitude) without changing the total bit-width of the format [150]. The Posit is usually known for its _tapered-accuracy_, i.e., small magnitude numbers around the '1' have more accuracy than extremely large or extremely small numbers [156]. The authors in [147] compared the decimal accuracy ( \(-\log_{10}|\log_{10}(\frac{\hat{x}}{\hat{x}})|\), where \(x\) is the actual real number value and \(\hat{x}\) is the represented number value [149]) of different Posit representations to the FLP8 and FXP8, see Figure 13. Their experiment showed that: i) the FXP representation has a peak accuracy so it is suitable to represent data with a narrow range, ii) the floating point has almost constant accuracy and it should be used to represent data that are uniformly distributed to exploit its efficiency, iii) and the Posit has tapered accuracy which makes it suitable to represent the normally distributed data efficiently. Since data in DNNs usually are normally distributed, see for example Figure 11, Posit is expected to be the most attractive number system for DNN [147].

DNN architectures that use Posit number system are usually either rely on Posit format from end-to-end [150, 151, 157, 158, 159] or partially utilize this format and a conversion from and to other formats is required within this architecture [153, 160]. These two approaches of using Posit are discussed next. In addition, to increase the efficiency of Posit number system for DNNs, several Posit variants are proposed. These variants are reported below as well.

### _End-to-end Posit-based Architectures_

When DNN data are represented in Posit from end-to-end new hardware that is able to perform all operations on these data must be used. In this case, the most fundamental arithmetic operations that need to be carefully designed in hardware are MAC operation and activation functions [150].

Fig. 13: The decimal accuracy of the Posit representation compared to the FLP8 and FXP8 [147]
Different designs of the Posit-based MAC (or multiplier) are proposed in [16, 147, 148, 155, 159, 161, 162, 163, 164]. In most of these works, the MAC design mainly follows the standard FLP MAC as in [147, 148, 155, 161, 162, 163, 164]. The main additional steps over the FLP MAC design are the decoding to extract Posit fields of the operands and encoding the result to Posit format [159]. Indeed, Posit MAC hardware implementation is more complicated and less efficient than the FLP MAC with the same number of bits because of the length-variability of the regime and mantisas fields. It is shown in [16] that Posit(32, 6) multiplier has 78% more area and consumes 94% more power than the FLP32 multiplier. This is attributed to the fact that the multiplier should be designed to handle the extreme lengths of mantissa, which is \(w-es-2\), and regime, which is \(w-1\). In addition, the critical path of this Posit multiplier is found to be longer than FLP32 due to the sequential bit decoding required for Posit. By making the fields of Posit format fixed, the area and power efficiency increased by 47%, and 38.5%, respectively, over the variable length fields Posit at the expense of negligible accuracy loss. Similar results are shown in [165] as well.

Alternatively, to design a more power and area-efficient multiplier, the authors in [159] proposed a Posit-LNS-Approximate multiplication. This combination allows for exploiting the advantages of Posit accuracy and LNS hardware efficiency. The general concept of performing LNS multiplications is similar to Mitchell's approximation discussed in section III-B1a, however, by considering Posit format instead. For example, the logarithm of a Posit number is given in (42) by taking the logarithm of both sides of (39) and applying the approximation in (7).

\[\log_{2}(|\hat{n}|)=2^{es}\times k+e+\frac{m}{2^{ms}}. \tag{42}\]

Consequently, Posit multiplication is performed using fixed point addition. The experiments in [159] showed significant reduction in the multiplier area by 72.86%, power by 81.79%, and delay by 17.01% compared to Posit multipliers in [158].

The implementation of several activation functions of Posit represented data is discussed in [147, 157, 166]. The Sigmoid activation function in (11) is found to be easy to be implemented in hardware for Posit represented data [149]. Few simple bit-cloning and masking is adequate to approximate this function. Similarly, a fast implementation of the \(\tanh\) and the Extended Linear Unit (ELU) activation functions are presented in [166] and [167], respectively.

### _Partial Posit-based Architectures_

Several architectures aimed to benefit from the high accuracy and dynamic range of Posit while avoiding its hardware inefficiency by representing only the weights with Posit prior to the inference process [153, 160]. This enables significant decrease in both the storage and communication overheads. These weights are then converted back to another format, such as FLP in [153] or FXP in [160], during the computation. The only overhead over the hardware of the standard architectures are modules to convert from Posit to the other formats and vice versa. The penalty of converting Posit to FXP is the increase in critical path delay and power consumption of the MAC by 22.8% and 5%, respectively [160].

### _Posit Variants_

Two Posit variants are proposed for DNNs; the fixed-Posit representation [16], and the generalized Posit representation [152, 156]. As its name indicates, the fixed-Posit representation proposes using a fixed length of the regime \(rs=constant\) instead of using a variable length in the vanilla Posit. Although the dynamic range and the accuracy of this representation are expected to be less than that of Posit, using this representation results in much more efficient hardware, in terms of power, area, and delay, with negligible loss in classification accuracy (0.12 %) when it used for ResNet-18 on ImageNet [16].

The generalized Posit representation [152, 156] proposed a modification to the vanilla Posit format to better represent the dynamic range and data distribution of DNNs. They relied on the fact that Posit with \(w<8\) and a specific \(es\) is observed to be unable to accommodate the variability in parameter distributions and dynamic range of different DNN layers and various DNN models. Instead of using mixed-precision Posits which requires a very large search space (as huge as \(4^{110}\) for ResNet-110 when 4 different \(w\) values are searched [152]), Posit format is modified by inserting two hyper-parameters that can be adjusted per-layer to enable a parameterized tapered accuracy and dynamic range. These two hyper-parameters are the exponent bias and the maximum regime bit-width that can be applied by replacing \(e\) in (39) with \(e+sc\), where \(sc\) is the exponent bias, and restricting the number of bits allocated to the regime \(rs\leq rs_{max}\). The exponent bias is used to scale the zone of maximum accuracy (i.e., minimum and maximum magnitude values) downward or upward in order to track the data distribution of different layers. The maximum regime bit-width \(rs_{max}\) controls the maximum and minimum Positive representable values. When \(rs_{max}=1\), the generalized Posits becomes a FLP-like format, whereas it turns into vanilla Posit format with \(rs_{max}=w-1\). Various tapered-precision representations can be obtained by selecting the \(rs_{max}\) between these two bounds. The experimental results on several datasets and CNN models showed that the generalized Posit offers considerable accuracy improvement when \(w<8\) bits compared to the vanilla Posit at the expense of a relatively moderate increase in energy consumption.

### _Summary and Discussion of Posit-based DNN Architectures_

Posit representation can be considered as a variant of FLP. This representation offers better accuracy and wider dynamic range than FLP. Thus, Posit can represent DNN data more efficiently with the same number of bits. However, in general, the hardware implementation of Posit is found to be more complicated compared to FLP hardware, as it relies on the FLP hardware in addition to the hardware needed to convert from and to FLP. Several trials have been made to enhance Posit hardware efficiency discussed above such as combining Posit with other representations (FXP and LNS) or modifying Posit by fixing or limiting the regime field.
## VIII Future Directions and Open Research Issues

Next, we briefly highlight several issues and opportunities for future research in DNN number systems. This includes dynamic number representations, hybrid number systems, and utilization of DNN statistics.

### _Dynamic Number Systems_

The main challenge of using low-precision number systems for training DNNs is the dynamic distribution of weights, activation, and gradients during training. In addition, several works show that optimal parameters of the number system (e.g., bit-widths) can be different for different datasets. This makes a dynamic number system (i.e., a number system that can adjust its parameters either offline or during run-time) highly desirable, especially for training DNNs. However, implementing such a system with online adaptation adds complications to the hardware which should be re-configurable to adapt to the changes in the number system format. Several works that adopt a format with a dynamic bit-width, for example [168], discussed the worthiness of this approach from a software (accuracy and speed gain) point of view. it seems worthy to investigate the effectiveness of a dynamic number system from the hardware efficiency perspective.

### _Hybrid Number Systems_

Several hybrid number systems have been investigated. Some examples of hybrid representations include DFXP with binary FXP [127], DFXP with ternary FXP [40], DFXP with FLP [132], dual DFXP with DFXP [136], FXP with Posit [16], BFP with LNS [106], Posit with LNS [159], and RNS with LNS [169]. Combining two number systems allows for gaining from the benefits offered by both systems. The hybrid representations are found to be more efficient, a hardware and accuracy point of view, than using each representation separately. More combinations of these representations can be investigated in the future. For example, applying the same concept of BFP (i.e., each block shares the same exponent) to Posit number system is expected to relieve the hardware complication compared to the vanilla Posit number system.

### _Utilization of DNN Characteristics_

DNN has special characteristics that should be considered when searching for more efficient representations dedicated to DNNs. For example, the ability of the neural networks to tolerate the noise is exploited in [66] to design an efficient LNS multiplier by reducing the average rather than the absolute error introduced by the multiplier. This results in enhancing the accuracy of DNN instead of ruining it as would be anticipated when using approximate multipliers. Another example of utilizing the noise tolerance of DNNs is using stochastic rounding (i.e., rounding the number up or down at random) when the real number is mapped to a specific representation. This kind of rounding allowed for training DNNs with lower precision when it is integrated with FXP [170, 21, 171], BFP [109], Posit [150], or DFXP [128]. Similarly, the ability to cluster DNN data into groups with narrower dynamic ranges gave birth to BFP and DFP representations. Moreover, realizing that DNN data are normally distributed shed light on the effectiveness of using the Posit number system, which has tapered accuracy. For future work on DNN number systems, these and other DNN characteristics should be paid attention to achieve more efficient representations.

## IX Summary and Conclusions

Deep neural networks have become an enabling component for a myriad of artificial intelligence applications. Being successful in providing great performance and even exceeding human accuracy, they have attracted the attention of academia and industry. The great performance of DNNs comes at the expense of high computational complexity and intensive memory requirements. Thus, increased attention is paid to redesigning DNN algorithms and hardware, in an effort to enhance their performance and/or enable their deployment on edge devices. A research direction that has a great impact on the performance of DNNs is their number representation. A great body of research has been focused on finding more suitable number systems, than FLP and FXP, tailored for DNNs.

The standard FLP representation has a massive dynamic range which makes it a good choice for computationally intensive algorithms that include a wide range of values and require high precision. At the same time, the complex and power-hungry FLP calculations make it less attractive for DNN architecture implementation. On the other hand, the FXP for DNN implementation offers great hardware efficiency at the expense of accuracy degradation. Between the two extreme representations (FLP and FXP), there are several number systems that are used for DNNs and offer different trade-offs between energy efficiency and acquired accuracy. The surveyed alternative number systems for DNNs are LNS, RNS, BFP, DFXP, and Posit number systems.

The main objective of using LNS is to simplify the implementation of the costly multiplication operation and have a multiplication-free DNN accelerators. This hardware simplification allows for significant savings in the area, power consumption, and cost, with some accuracy degradation 6 resulting from logarithmic approximation. This makes LNS a good choice when DNNs are deployed on source-constrained devices for accuracy-resilience applications.

Footnote 6: This is the common case. However, several works that adopted LNS showed no accuracy degradation. See Table I and Table II.

The RNS can be an attractive number representation choice for DNN accelerators. RNS exhibits inherent parallelism at the residue-processing level. It utilizes parallel computations along separate residue channels, where operations in each of them are performed modulo a specific modulus, with no need for information to be shared between residue channels. The main challenge in designing an efficient RNS-based accelerator is to minimize or, possibly, eliminate the overhead introduced when implementing the non-linear DNN operations. Another key factor is the optimization of the moduli selection and the corresponding arithmetic circuits, to meet the accuracy requirements.
The BFP strikes a balance between FLP and FXP format. Consequently, different trade-offs can be obtained by specifying different BFP design choices represented by the block size, shared exponent selection, and bit-width choice. Most of the surveyed DNN architectures that depend on BFP achieved negligible accuracy degradation compared to FLP even with less than 8 bits, with varying levels of speed, power, and area efficiency. DFXP can be considered as a subset of BFP with less dynamic range and less hardware complication at the same time. While BFP is closer to FLP, the DFXP is more like the FXP (as their names indicate). This results in different trade-offs between DNNs metrics (accuracy, power consumption, speed up, etc.)

Finally, Posit representation can be considered as a variant of FLP. offering better accuracy and a wider dynamic range, Posit can represent DNN data more efficiently with the same number of bits as FLP. This allows for more reduction in the number of bits compared to FLP implementations with similar accuracy. However, Posit has complex hardware, due to the hardware needed to convert Posit numbers to another number system (basically FLP) to do the arithmetic operations in the other domain before returning back to Posit domain. The efforts made to enhance its hardware efficiency have been discussed in this survey.

For all aforementioned alternative number systems, their impact on the performance and hardware design of DNN has been reported in details. In addition, this article highlighted the challenges associated with the implementation of each number system and the different solutions proposed to address these challenges.

## Acknowledgments

This work was supported by the Khalifa University of Science and Technology under Award CIRA-2020-053.
