ColibriES: A Milliwatts RISC-V Based Embedded System Leveraging
  Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency
  Closed-loop Control Applications
End-to-end event-based computation has the potential to push the envelope in
latency and energy efficiency for edge AI applications. Unfortunately,
event-based sensors (e.g., DVS cameras) and neuromorphic spike-based processors
(e.g., Loihi) have been designed in a decoupled fashion, thereby missing major
streamlining opportunities. This paper presents ColibriES, the first-ever
neuromorphic hardware embedded system platform with dedicated event-sensor
interfaces and full processing pipelines. ColibriES includes event and frame
interfaces and data processing, aiming at efficient and long-life embedded
systems in edge scenarios. ColibriES is based on the Kraken system-on-chip and
contains a heterogeneous parallel ultra-low power (PULP) processor, frame-based
and event-based camera interfaces, and two hardware accelerators for the
computation of both event-based spiking neural networks and frame-based ternary
convolutional neural networks. This paper explores and accurately evaluates the
performance of event data processing on the example of gesture recognition on
ColibriES, as the first step of full-system evaluation. In our experiments, we
demonstrate a chip energy consumption of 7.7 \si{\milli\joule} and latency of
164.5 \si{\milli\second} of each inference with the DVS Gesture event data set
as an example for closed-loop data processing, showcasing the potential of
ColibriES for battery-powered applications such as wearable devices and UAVs
that require low-latency closed-loop control.
Georg Rutishauser, Robin Hunziker, Alfio Di Mauro, Sizhen Bian, Luca Benini, Michele Magno
ColibriiES: A Milliwatts RISC-V Based Embedded System Leveraging Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency Closed-loop Control Applications

###### Abstract

End-to-end event-based computation has the potential to push the envelope in latency and energy efficiency for edge AI applications. Unfortunately, event-based sensors (e.g., DVS cameras) and neuromorphic spike-based processors (e.g., Loihi) have been designed in a decoupled fashion, thereby missing major streamlining opportunities. This paper presents ColibriiES, the first-ever neuromorphic hardware embedded system platform with dedicated event-sensor interfaces and full processing pipelines. ColibriiES includes event and frame interfaces and data processing, aiming at efficient and long-life embedded systems in edge scenarios. ColibriiES is based on the Kraken system-on-chip and contains a heterogeneous parallel ultra-low power (PULP) processor, frame-based and event-based camera interfaces, and two hardware accelerators for the computation of both event-based spiking neural networks and frame-based ternary convolutional neural networks. This paper explores and accurately evaluates the performance of event data processing on the example of gesture recognition on ColibriiES, as the first step of full-system evaluation. In our experiments, we demonstrate a chip energy consumption of 7.7 \(\mathrm{mJ}\) and latency of 164.5 \(\mathrm{ms}\) of each inference with the DVS Gesture event data set as an example for closed-loop data processing, showcasing the potential of ColibriiES for battery-powered applications such as wearable devices and UAVs that require low-latency closed-loop control.

## I Introduction

Neuromorphic computing is a promising paradigm for low latency, energy-efficient artificial intelligence [1] for a wide range of embedded applications [2]. Complementing this novel processing paradigm, event-based sensors have the potential to unlock the full potential of neuromorphic hardware for applications such as intelligent sensing and ultra-fast robotics [3]. On the other hand, frame-based processing using deep neural networks (DNNs) is currently offering impressive performance and is being heavily tuned for low-power, and energy-efficient embedded platforms [4].

Combining the advantages of event-based image sensors, neuromorphic processing, traditional image sensors, and deep neural networks yields hybrid hardware and software systems that can outperform the current state of the art in low-latency, energy-efficient systems like unmanned vehicles. For instance, optical flow estimation is one of the most used methods for autonomous navigation. Improving its speed and accuracy will improve the entire autonomous vehicles field [5]. Our work aims at building the first hybrid system combining frame information with DNN-based processing and event information with SNN-based processing for autonomous vehicles and robots [6].

### _Motivation_

Most current systems using visual sensing to perform intelligent tasks rely on frame-based cameras [12]. Conventional video sensors record the entire image at a fixed rate and resolution. These vision systems use sequences of RGB frames, which are heavily redundant and inefficient to process. Event-based cameras (silicon retinas) have introduced a new vision paradigm by mimicking the biological retina. Instead of measuring the intensity of every pixel at fixed time intervals, they report events of significant pixel intensity changes. Each such event is represented by its position, the sign of change, and timestamp in microsecond resolution. Because of their asynchronous operation principle, they are a natural match for spiking neural networks (SNNs) [13] rather than DNNs.

State-of-the-art DNN approaches in machine learning provide excellent results for vision tasks with standard cameras. In contrast, asynchronous event sequences require special handling, and SNNs can take advantage of this asynchronicity, offering very low detection latency in the order of microseconds [14]. However, SNN-based algorithms are still evolving, and current SNNs are still not comparable in terms of accuracy to DNN-based approaches.

Another aspect limiting the employment of energy-proportional event-based cameras in real application scenarios requiring ultra-low-power devices is the high power consumption spent at such sensors' interfaces. Event cameras often expose non-standard communication protocols, and data acquisition is commonly carried out with a high-power field-programmable gate array (FPGA), and a USB interface [15].

Neuromorphic processors execute SNNs on large-scale integrated circuits [16] by mimicking the natural biological structures of the nervous system, implementing neurons and synapses directly in silicon. A typical neuromorphic processor can simulate hundreds of thousands or even millions of spiking neurons in real time. However, to achieve truly power-efficient
real-time operation, such platforms should also be equipped with microcontroller subsystems capable of performing actuation and closed-loop control. Even advanced prototypes, e.g., the Loihi Kapoho Bay board, do not present such features as they are generally conceived as research and evaluation testbeds. Kraken, a novel RISC-V-based system-on-chip (SoC) addressing this challenge, has been recently proposed [17]. Kraken includes a heterogeneous parallel ultra-low power (PULP) processor [18] and two hardware accelerators for both spiking neural networks and frame-based convolutional neural networks. A key feature of the Kraken SoC is that both RGB camera and event-based camera interfaces are present, as well as the general-purpose input output pins useful for direct control of motors and other devices. Kraken can deliver up to 2TOP/s/W 2bit SIMD on the RISC-V cluster and 1.1TSynOP/s/W on the neuromorphic accelerator, which makes it suitable for embedded battery-operated devices requiring low-latency closed-loop control. Table I compares our proposed ColibriES system with previous works implementing advanced tasks on neuromorphic processors. The only published works implementing true end-to-end neuromorphic applications are based on IBM's TrueNorth platform [19], a purely neuromorphic processor that lacks the advanced compute and control capabilities enabled by the Kraken SoC, relying solely on SNNs for all processing tasks, which in turn restricts the range of tasks that can be solved on the platform.

### _Contribution_

This paper presents ColibriES, the first-ever neuromorphic truly embedded evaluation platform hosting the Kraken SoC. The ColibriES board was designed to accurately measure the complete processing pipeline's power consumption, energy, and latency. ColibriES can connect to both event- and frame-based cameras that directly interface with the Kraken SoC. The platform is designed for battery-powered applications requiring low-latency closed-loop control feedback, such as wearable electronics, unmanned aerial vehicles (UAVs), and other applications that impose stringent requirements on the computational and energy resources available to perform the processing. Figure 1 shows the high-level architecture of the proposed platform and provides an overview of how the system could be used as a high-speed closed-loop controller. Evaluations of power consumption, functionality, and energy efficiency are presented with experimental measurements, demonstrating the versatility and low power of ColibriES.

The rest of this paper is organized as follows: Section II describes the proposed ColibriES platform with a particular focus on Kraken's architectural features. Section III shows the experimental results, and section IV concludes the paper.

## II System Architecture

In this section, we present the heart of ColibriES, the heterogeneous Kraken SoC, and the evaluation board used in our experiments.

### _Kraken SoC_

The Kraken SoC has a heterogeneous architecture composed of three main subsystems. Fig. 2 shows a block diagram representation of the Kraken chip. The first subsystem, the fabric controller (FC), is built around a 32-bit RISC-V core

Fig. 1: Architecture of the embedded platform developed as evaluation board hosting the novel Kraken SoC, which includes PWM pins for high-speed control.

\begin{table}
\begin{tabular}{l|c|c|c|c|c|c}  & [7] & [8] & [9] & [10] & [11] & **ColibriES (ours)** \\ \hline Platform & Loihi & TrueNorth & Loihi & Loihi & TrueNorth & Kraken (SNE) \\ Application \({}^{\text{a}}\) & KWS & KWS & GR & GR & GR & GR \\ Input Data & MFCC \({}^{\text{d}}\) & Audio & DVS + sEMG Evts. \({}^{\text{d}}\) & DVS Evts. & DVS Evts. & DVS Evts. \\ Dataset & Custom & TIDIGITS & Custom & DVS128 & DVS128 & DVS128 \\ \# of Classes & 2 & 11 & 5 & 11 & 11 \\ Network \({}^{\text{b}}\) & 2L SMLP & 7L SCNN & 6L SCNN + 4L SMLP & 5L SCNN & 16L SCNN & 7L SCNN \\ Accuracy & \(95.9\%\) & \(90.8\%\)-\(95.1\%\)\({}^{\text{e}}\) & \(96\%\) & \(90.5\%\) & \(86.5\%\)-\(94.6\%\)\({}^{\text{e}}\) & \(83\%\) \\ End-to-End? & ✗ & ✓ & ✗ & ✓ & ✓ & ✓ \\ \(P_{proc,inf}\) (mW) \({}^{\text{b}}\) & 110 & 14.4 (85)-38.6 (91) \({}^{\text{e}}\) & 141.9 & N/A & 88.5 - 178.8 & 35.6 \\ \(P_{proc,inf}\) (mW) \({}^{\text{b}}\) & 29.2 & 12.1 (82.7) - 30.3 (82.7) \({}^{\text{e}}\) & 29.2 [7] & 29.2 [7] & 68.8 - 134.4 \({}^{\text{f}}\) & 17.7 \\ \(E_{proc,inf}\) (mJ) \({}^{\text{d}}\) & 0.371 & 15.9 (93.6) - 42.5 (100.1) \({}^{\text{g}}\) & 5.9 & N/A & 29.8 & **7.7** \\ \end{tabular}

* \({}^{\text{a}}\)**KWS:** Keyword Spotting, **GR:** Gesture Recognition
* \({}^{\text{b}}\)**N/L SCNN:** \(N\)-layer spiking convolutional neural network, _N_**L** **SMLP:**\(N\)-layer spiking multi-layer perceptron
* \({}^{\text{c}}\)\(P_{proc,inf,idle}\):** Processor chip/full system chip power during inference/while idle
* \({}^{\text{d}}\)\(E_{proc,inf}\):** Processor chip/full system energy per inference. Energy normalized to 6 inf/s for GR.
* \({}^{\text{e}}\)\({}^{\text{f}}\)\({}^{\text{c}}\)\({}^{\text{b}}\)\({}^{\text{e}}\)\({}^{\text{f}}\) Lowest-power and highest-accuracy implementations. Numbers in parentheses are energy/power omit scaling for resource usage.
* \({}^{\text{g}}\) We assume the preprocessing and classification pipeline needs to run for the entire length of a sample (\(1104\,\text{ms}\)).

\end{table} TABLE I: Comparison of ColibriES to recent work
which acts as the central programmable control unit for the whole SoC. The FC hosts the main interconnection busses to the main L2 memory and the advanced peripheral bus (APB), which controls all the SoC peripherals. The FC domain also contains a full set of on-chip peripherals such as a RISC-V compliant debug unit, four programmable timer-counters and a power management unit.

The second subsystem is a RISC-V-based general-purpose accelerator called the _cluster_. The cluster domain hosts eight RISC-V cores enhanced with specialized instruction set architecture (ISA) extensions like hardware loops, multiply and accumulate, and vectorial instructions for low-precision machine learning (ML) workloads. Each RISC-V core of the cluster accelerator is equipped with a private floating point unit (FPU) and implements the full 32-bit RISC-V floating-point ISA extension. The cluster also features a \(128\,\mathrm{K}\mathrm{b}\) L1 tightly coupled data memory (TCDM). The L1 memory can serve memory requests from all cluster cores in parallel with single-cycle access latency and a low average contention rate (\(<\)10% even on the most data-intensive kernels). Fast event management, parallel thread dispatching, and synchronization are supported by a dedicated hardware block (HW Sync), enabling very fine-grained parallelism and high energy efficiency in parallel workloads. The cluster can be clock-gated at single-core granularity, reducing the dynamic power consumption while waiting for core synchronization.

The third domain, the external hardware processing engine (EHWPE), hosts two accelerators. One is the sparse neural engine (SNE) neuromorphic accelerator presented in [17], and the other is CUTIE, a ternary weight neural network accelerator presented in [20]. The EHWPE domain operates on two independent clock domains. One clock is generated by the FC frequency locked loop (FLL), which is used to clock the interface logic at the boundary between the accelerators and the main system interconnect. The other clock is generated by a dedicated EHWPE FLL, which is used to clock the accelerator's computing engines. Like many peripherals of the SoC, the accelerators are programmed via memory-mapped register interfaces. The FC domain hosts a vast set of IO peripherals commonly adopted on microcontroller-like SoCs. The chip features 76 digital pads, 44 of which can be used to arbitrarily map any pin of the peripherals mentioned above to a chip pad in an all-to-all crossbar configuration, providing high IO mapping flexibility. The pin mapping is configurable via a memory-mapped register interface connected to the APB. Each peripheral can generate interrupts depending on data transmission events; such events can then be routed to the interrupt controller of the RISC-V core.

An autonomous IO subsystem, the _\(\mu\)DMA_[21], hosts all the IO peripherals. This system can be programmed to autonomously orchestrate data transfers from the peripherals to the L2 memory and vice versa, freeing the RISC-V core from micro-managing such data transfers. Moreover, Kraken's \(\mu\)DMA is equipped with a dedicated hardware interface for the ultra-low power dynamic visual sensor (DVS) presented in [22]. Such an interface was presented in [23] and allows streaming events directly from the event camera to Kraken.

To carefully control the chip's overall power consumption and enable a versatile application-specific power management scheme, Kraken is subdivided into three independent power domains. Such power domain partitioning allows to switch-off of unused parts of the system that the running application might not require. The power-up/down of the controllable domains can be performed at run time. Figure 2 also shows the chip power domain partitioning, SoC, Cluster, and EHWPE, respectively. The FC domain is always on because it hosts essential components needed for SoC management tasks such as the boot procedure, clock generator initialization, or accelerator reset and programming.

### _Kraken evaluation board_

The Kraken evaluation board integrates the Kraken chip with the external components needed to implement complete applications. A USB-C connector is used for JTAG and UART data transfer and supplies a \(5\,\mathrm{V}\) rail from which all other power supplies are derived. Kraken's three power domains are supplied by individually runtime-configurable buck converters, allowing for application-controlled dynamic voltage and frequency scaling (DVFS). Connectivity to the DVS camera is provided through an 80-pin low-profile board-to-board connector, which also supplies the camera board with the required \(1.2\,\mathrm{V}\) and \(5\,\mathrm{V}\) rails. Off-chip memory is present in the form of a combined HyperFlash/HyperRAM chip and a quad-SPI flash memory chip, which can also be used to store application code for standalone booting. Arduino headers and a camera parallel interface (CPI) ribbon connector provide additional connectivity, with level shifters between every off-chip connector and Kraken's I/O pins. An annotated photograph of the board is shown in Fig. 3.

## III Evaluation

\begin{table}
\begin{tabular}{c|c|c|c|c|c}  & Type & Size & Feature Size & Features & Stride \\ \hline
0 & Input & 128x128x2 & - & - & - \\
1 & Pool & 32x32x2 & 4x4x1 & 2 & 4 \\
2 & Conv & 32x32x16 & 3x3x32 & 16 & 1 \\
3 & Pool & 16x16x16 & 2x2x1 & 16 & 2 \\
4 & Conv & 16x16x32 & 3x3x1 & 32 & 1 \\
5 & Pool & 8x8x32 & 2x2x1 & 32 & 2 \\
6 & Full & 512 & 2048 & 512 & - \\
7 & Full & 11 & 512 & 11 & - \\ \end{tabular}
\end{table} TABLE II: DVS Gesture Network Parameters

Fig. 2: Kraken SoC block diagram
In this section, we evaluate the end-to-end performance of ColibriES when executing SNN inference as the first step of the full-system evaluation. We used the IBM DVS Gesture event data set [24], which contains 11 hand gestures from 29 subjects under three illumination conditions from a DVS128 event camera. Six subjects' data are used for testing and the remaining for training. The SNN used for our experiments is reported in Table II. The network is composed of two convolutional layers and two fully-connected layers. To train the network, we used a supervised learning approach based on back-propagation, derived from the one presented in [25], which has been implemented in PyTorch. In this framework, the Neuron dynamic of the leaky-integrate and fire (LIF) neurons implemented in SNE is accurately modeled to closely reflect the hardware implementation and minimize the mismatch between the accuracy achieved during training and the one achieved on the real hardware platform.

We break down the closed loop into three distinct parts: data acquisition on the FC through the dedicated DVS interface, data processing on the engines, which includes a spike preprocessing step in the cluster and a spike train inference step in the SNE, and actuators control using PWM signals. For advanced processing tasks, neural networks that exceed SNE's output neuron capacity are executed on the accelerator in a tiled way, and the SNE is used in a time-domain-multiplexing fashion. The preprocessing step performed on the cluster is necessary to assemble a single input event stream from multiple output tiles and create the tiled input streams for the tiles of the successive layer. Note that the main system clock of Kraken can vary from a few \(\mathrm{kHz}\) to \(200\,\mathrm{MHz}\), and the typical operating frequency is \(50\,\mathrm{MHz}\). In typical operating conditions, the latency of changing an output actuation signal like a PWM signal is a few system clock cycles, i.e., below 1 \(\upmu\)s. Therefore, we considered this latency negligible compared to data acquisition and processing. Table III reports the energy and latency metrics of the ColibriES system for the gesture recognition task execution. Using a 300 milliseconds window input, Kraken requires 164.5 \(\mathrm{ms}\) and 7.7 \(\mathrm{mJ}\) to perform a DVS-to-label prediction, meeting real-time processing constraints. The inference execution on SNE takes only 32 \(\mathrm{ms}\) and 1.4 \(\mathrm{mJ}\).

## IV Conclusion

This paper presented ColibriES, an energy-efficient heterogeneous platform including an event-based camera interface and an RGB interface, together with the control features of a standard microcontroller. The platform core is the Kraken system-on-chip, a PULP processor with eight RISC-V cores and two dedicated hardware accelerators for machine learning: a neuromorphic processor and a frame base machine learning accelerator. As the first step of system evaluation on ColibriES, this paper reports the evaluation of end-to-end gesture recognition from event camera data with the dedicated DVS interface and the neuromorphic core. Thanks to the direct access to the stream of events from the event camera, ColibriES can achieve real-time event processing by executing SNN inference on sensor data. Experimental results show that our platform can perform low-latency tasks under stringent power constraints, and it is suitable for battery-powered operation and low-latency applications. On the IBM DVS Gesture event data set, ColibriES achieves real-time 164ms processing on 300ms time window samples, consuming only 7.7mJ of total energy and meeting the severe latency and energy constraints of emerging high-speed closed-loop control applications, such as autonomous drones and wearable control embedded systems, while keeping the power in the mW range.

## Acknowledgment

The authors would like to thank _armasuisse Science & Technology_ for funding this research.

Fig. 3: Kraken evaluation board

\begin{table}
\begin{tabular}{l r r r r} \hline \hline \multirow{2}{*}{Proc. Stage} & \multirow{2}{*}{Time (ms)} & \multicolumn{2}{c}{Power (\(\mathrm{mW}\))\({}^{\mathrm{a}}\)} & \multirow{2}{*}{Energy (\(\mathrm{mJ}\))\({}^{\mathrm{c}}\)} \\ \cline{3-4}  & & Idle & Active & \\ \hline Data Acquisition (FC) & 1.5 & 3.5 & 3.8 & 0.006 \\ \hline Preprocessing & 131 & 6.5 & 34 & 4.6 \\ (Cluster)\({}^{\mathrm{a}}\), & & & & \\ \hline SNN Inference (SNE) & 32 & 7.7 & 44 & 1.4 \\ \hline \hline \multicolumn{4}{l}{**Total**} \\ \hline \hline \multicolumn{4}{l}{All power numbers measured at \(V_{DD}=0.65\,\mathrm{V}\)} \\ \multicolumn{4}{l}{\({}^{\mathrm{a}}\) Idle power measured with respective components clock-gated.} \\ \multicolumn{4}{l}{\({}^{\mathrm{b}}\) Total energy is computed as the sum of active energy contributions and idle energy of inactive components.} \\ \multicolumn{4}{l}{\({}^{\mathrm{c}}\) Average total power consumption during inference} \\ \end{tabular}
\end{table} TABLE III: Performance metrics of ColibriES on DVS-HandGesture Dataset with accuracy of 83%