RRNet: Towards ReLU-Reduced Neural Network for Two-party Computation
  Based Private Inference
The proliferation of deep learning (DL) has led to the emergence of privacy
and security concerns. To address these issues, secure Two-party computation
(2PC) has been proposed as a means of enabling privacy-preserving DL
computation. However, in practice, 2PC methods often incur high computation and
communication overhead, which can impede their use in large-scale systems. To
address this challenge, we introduce RRNet, a systematic framework that aims to
jointly reduce the overhead of MPC comparison protocols and accelerate
computation through hardware acceleration. Our approach integrates the hardware
latency of cryptographic building blocks into the DNN loss function, resulting
in improved energy efficiency, accuracy, and security guarantees. Furthermore,
we propose a cryptographic hardware scheduler and corresponding performance
model for Field Programmable Gate Arrays (FPGAs) to further enhance the
efficiency of our framework. Experiments show RRNet achieved a much higher ReLU
reduction performance than all SOTA works on CIFAR-10 dataset.
Hongwu Peng, Shanglin Zhou, Yukui Luo, Nuo Xu, Shijin Duan, Ran Ran, Jiahui Zhao, Shaoyi Huang, Xi Xie, Chenghong Wang, Tong Geng, Wujie Wen, Xiaolin Xu, Caiwen Ding
# RRNet: Towards ReLU-Reduced Neural Network for Two-party Computation Based Private Inference

###### Abstract

The proliferation of deep learning (DL) has led to the emergence of privacy and security concerns. To address these issues, secure Two-party computation (2PC) has been proposed as a means of enabling privacy-preserving DL computation. However, in practice, 2PC methods often incur high computation and communication overhead, which can impede their use in large-scale systems. To address this challenge, we introduce RRNet, a systematic framework that aims to jointly reduce the overhead of MPC comparison protocols and accelerate computation through hardware acceleration. Our approach integrates the hardware latency of cryptographic building blocks into the DNN loss function, resulting in improved energy efficiency, accuracy, and security guarantees. Furthermore, we propose a cryptographic hardware scheduler and corresponding performance model for Field Programmable Gate Arrays (FPGAs) to further enhance the efficiency of our framework. Experiments show RRNet achieved a much higher ReLU reduction performance than all SOTA works on CIFAR-10 dataset.

## I Introduction

Machine-Learning-as-a-Service (MLaaS) has emerged as a popular solution for accelerating inference in various applications [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11]. The challenges of MLaaS comes from several folds: inference latency and privacy. To accelerate the MLaaS training and inference application, accelerated gradient sparsification [12, 13] and model compression methods [14, 15, 16, 17, 18, 19, 20, 21, 22] are proposed. On the other side, a major limitation of MLaaS is the requirement for clients to reveal raw input data to the service provider, which may compromise the privacy of users. This issue has been highlighted in previous studies such as [23]. In this work, we aim to address this challenge by proposing a novel approach for privacy-preserving MLaaS. Our method enables clients to maintain the confidentiality of their input data while still allowing for efficient and accurate inference. Homomorphic Encryption (HE) is a powerful tool for securing small to medium-scale deep neural networks (DNNs) without incurring the high costs associated with bootstrapping or significant communication overhead. Other secure multiparty computation (MPC) protocols such as secret-sharing [24] and Yao's Garbled Circuits (GC) [25] have also been proposed to support the evaluation of operator blocks in large-scale networks. However, our focus in this work is on the use of secure two-party computation (2PC) [24] as a means of protecting DNN models.

The main challenge in 2PC-based private inference (PI) is the overhead associated with the comparison protocol for non-linear operators [26]. To address this challenge, existing works have focused on optimizing the cost of the ReLU operator by minimizing ReLU counts (e.g., DeepReduce [27], CryptoNAS [28]) or replacing ReLUs with polynomials (e.g., CryptoNets [29], Delphi [30], SAFENet [31]). Another trend in the field has been the use of hardware acceleration for PI, such as using Graphics Processing Units (GPUs) [24, 32] to speed up MPC-based DNNs. However, both of these approaches have limitations in effectively exploring the design space of 2PC-based PI. In this work, we aim to address these limitations by proposing a novel approach for optimizing the cost of non-linear operators and hardware acceleration for PI that can effectively perform design exploration.

Current approaches for optimizing the performance of 2PC-based private inference (PI) rely on heuristic methods for evaluating the impact of different non-linear operators on system performance. In this work, we propose a novel approach, the **ReLU-Reduced Neural Architecture Search (RRNet)** framework, that jointly optimizes the structure of the deep neural network (DNN) model and the hardware architecture to support high-performance MPC-based PI. Our framework eliminates the need for manual heuristic analysis by automating the process of exploring the design space and identifying the optimal configuration of DNN models and hardware architectures for 2PC-based PI. We use FPGA accelerator design as a demonstration and summarize our contributions:

1. We propose a novel approach to addressing the high computational cost of non-linear operators in 2PC-based PI. We introduce a trainable _straight-through polynomial activation initialization_ method that utilizes a trainable polynomial activation function as an alternative to the computationally expensive ReLU operator.
2. We develop a cryptographic hardware scheduler and performance model for FPGA platform. We also construct a latency lookup table to optimize scheduling of cryptographic operations for improved performance and energy efficiency.
3. We propose a differentiable NAS framework that takes into account the constraints and latencies of cryptographic operators. Our framework enables the selection of appropriate polynomial or non-polynomial activation functions based on the specific needs of the task and
the computational resources available. By integrating cryptographic considerations into the NAS process, our framework ensures that the resulting DNN models are both accurate and secure, while also being optimized for the target hardware platform.

## II **Basic of Cryptographic Operators**

### _Secret Sharing_

**2PC setup.** We consider a similar scheme involving two semi-honest in a MLaaS applications [33], where two servers receive the confidential inputs from each other and invoke evaluation.

**Additive Secret Sharing.** In this work, we evaluate 2PC secret sharing. As a symbolic representation, for a secret value \(x\in\mathbb{Z}_{m}\), \(\llbracket x\rrbracket\leftarrow(x_{S_{0}},x_{S_{1}})\) denotes the two shares, where \(x_{S_{i}},i\in\{0,1\}\) belong to server \(S_{i}\). Other notations are as below:

* _Share Generation_\(\text{shr}(x)\): A random value \(r\) in \(\mathbb{Z}_{m}\) is sampled, and shares are generated as \(\llbracket x\rrbracket\leftarrow(r,x-r)\).
* _Share Recovering_\(\text{rec}(\llbracket x\rrbracket)\): Given shares \(\llbracket x\rrbracket\leftarrow(x_{S_{0}},x_{S_{1}})\), it computes \(x\gets x_{S_{0}}+x_{S_{1}}\) to recover \(x\).

An example of plaintext vs. secret shared based ciphertext evaluation is given in Fig. 1, where ring size is 4 and \(\mathbb{Z}_{m}=\{-8,-7,...7\}\). Details are given in following sections.

### _Polynomial Operators Over Secret-Shared Data_

**Scaling and Addition.** We denote secret shared matrices as \(\llbracket X\rrbracket\) and \(\llbracket Y\rrbracket\). The encrypted evaluation is given in Eq. 1.

\[\llbracket aX+Y\rrbracket\leftarrow(aX_{S_{0}}+Y_{S_{0}},aX_{S_{1}}+Y_{S_{1}}) \tag{1}\]

**Multiplication.** We consider the matrix multiplicative operations \(\llbracket R\rrbracket\leftarrow\llbracket X\rrbracket\otimes\llbracket Y\rrbracket\) in the secret-sharing pattern. We use oblivious transfer (OT) [34] based approach. To make the multiplicative computation secure, an extra Beaver triples [35] should be generated as \(\llbracket Z\rrbracket=\llbracket A\rrbracket\otimes\llbracket B\rrbracket\), where \(A\) and \(B\) are randomly initialized. Specifically, their secret shares are denoted as \(\llbracket Z\rrbracket=(Z_{S_{0}},Z_{S_{1}})\), \(\llbracket A\rrbracket=(A_{S_{0}},A_{S_{1}})\), and \(\llbracket B\rrbracket=(B_{S_{0}},B_{S_{1}})\). Later, two matrices are derived from given shares: \(E_{S_{i}}=X_{S_{i}}-A_{S_{i}}\) and \(F_{S_{i}}=Y_{S_{i}}-B_{S_{i}}\), in each party end separately. The intermediate shares are jointly recovered as \(E\leftarrow\text{rec}(\llbracket E\rrbracket)\) and \(F\leftarrow\text{rec}(\llbracket F\rrbracket)\). Finally, each party, i.e, server \(S_{i}\), will calculate the secret-shared \(R_{S_{i}}\) locally:

\[R_{S_{i}}=-i\cdot E\otimes F+X_{S_{i}}\otimes F+E\otimes Y_{S_{i}}+Z_{S_{i}} \tag{2}\]

**Square.** For the element-wise square operator shown \(\llbracket R\rrbracket\leftarrow\llbracket X\rrbracket\otimes \llbracket X\rrbracket\), we need to generate a Beaver pair \(\llbracket Z\rrbracket\) and \(\llbracket A\rrbracket\) where \(\llbracket Z\rrbracket=\llbracket A\rrbracket\otimes\llbracket A\rrbracket\), and \(\llbracket A\rrbracket\) is randomly initialized. Then parties evaluate \(\llbracket E\rrbracket=\llbracket X\rrbracket-\llbracket A\rrbracket\) and jointly recover \(E\leftarrow\text{rec}(\llbracket E\rrbracket)\). The result \(R\) can be obtained through Eq. 3.

\[R_{S_{i}}=Z_{S_{i}}+2E\otimes A_{S_{i}}+E\otimes E \tag{3}\]

### _Non-Polynomial Operator Modules_

Non-polynomial operators such as ReLU and MaxPool are evaluated using secure comparison protocol.

**Secure 2PC Comparison.** The 2PC comparison, a.k.a. millionaires protocol, is committed to determine whose value held by two parties is larger, without disclosing the exact value to each other. We adopt work [26] for 2PC comparison.

## III **The RRNet Framework**

The overview of the framework is given in Fig. 2. This section introduces the new cryptographic-friendly activation function and its initialization method. The modeling of DNN operators is conducted under 2PC setup on FPGA. As last, the hardware-aware NAS framework is proposed to find proper DNN architecture.

### _Trainable \(X^{2}act\) Non-linear Function._

We use a hardware friendly trainable second order polynomial activation function as an non-linear function candidate, shown in Eq. 4, where \(w_{1}\), \(w_{2}\) and \(b\) are all trainable parameters. We propose _straight through polynomial activation initialization_ (**STPAI**) method to set the \(w_{1}\) and \(b\) to be small enough and \(w_{2}\) to be near to 1 in Eq. 4 for initialization.

\[\delta(x)=\frac{c}{\sqrt{N_{x}}}w_{1}x^{2}+w_{2}x+b \tag{4}\]

### _Search Space of Hardware-aware NAS._

We focus on convolutional neural networks (CNNs) in our study. CNNs are mostly composed of Conv-Act-Pool and Conv-Act blocks. In work, we use the regular backbone model as a search baseline, such as the VGG family, mobilenetV3, and ResNet family. A toy example is shown in Fig. 2, where a two-layer supernet is constructed, and the first layer is Conv-Act-Pool, and the second layer is Conv-Act. The first layer has four combinations which are Conv-ReLU-Pool\({}_{\text{m}}\), Conv-ReLU-Pool\({}_{\text{a}}\), Conv-\(X^{2}act\)-Pool\({}_{\text{m}}\), and Conv-\(X^{2}act\)-Pool\({}_{\text{a}}\). The second layer has two combinations: Conv-ReLU and Conv-\(X^{2}act\). The Conv block's parameters can be either shared among candidates or separately trained during the search.

### _Differentiable Harware Aware NAS Algorithm_

In this work, we incorporate latency constraint into the target loss function of the DARTS framework [36], and develop a differentiable cryptographic hardware-aware micro-architecture search framework. We firstly determine a supernet model for NAS, and introduces gated operators \(OP_{l}(x)\) which parametrizes the candidate operators \(OP_{l,j}(x)\) selection with a trainable weight \(\alpha_{l,k}\) (Eq. 5). For example, a gated pooling operator consists of MaxPool and AvgPool operators and 2 trainable parameters for pooling selection. The latency of the operators could be determined based on performance predictor. A parameterized latency constraint is given as \(Lat(\alpha)=\sum_{l=1}^{n}\sum_{j=1}^{m}\theta_{l,j}Lat(OP_{l,j})\), where the latency of gated operators are weighted by \(\theta_{l,j}\). We incorporate the latency constraint into the loss function as \(\zeta(\omega,\alpha)=\zeta_{CE}(\omega,\alpha)+\lambda Lat(\alpha)\), and penalize the latency \(Lat(\alpha)\) by \(\lambda\).

Fig. 1: A example of 4 bit plaintext vs. ciphertext evaluation.
\[\theta_{l,j}=\frac{\exp(\alpha_{l,j})}{\sum_{k=1}^{m}\exp(\alpha_{l,k})},\;OP_{l}( x)=\sum_{k=1}^{m}\theta_{l,k}OP_{l,k}(x) \tag{5}\]

The optimization objective of our design is shown in Eq. 6, we aim to minimize the validation loss \(\zeta_{val}(\omega^{*},\alpha)\) with regard to architecture parameter \(\alpha\). The optimal weight \(\omega^{*}\) is obtained through minimize the training loss. The second order approximation of the optimal weight is given as \(\omega^{*}\approx\omega^{\prime}=\omega-\xi\,\delta\zeta_{trn}(\omega,\alpha)/ \delta\omega\), the approximation is based on current weight parameter and its' gradient. The virtual learning rate \(\xi\) can be set equal to that of weight optimizer.

\[\text{argmin}_{\alpha}\;\zeta_{val}(\omega^{*},\alpha),\;s.t.\;\omega^{*}= \text{argmin}_{\omega}\;\zeta_{trn}(\omega,\alpha) \tag{6}\]

Eq. 7 gives the approximate \(\alpha\) gradient using chain rule, the second term of \(\alpha\) gradient can be further approximated using small turbulence \(\varepsilon\), where weights are \(\omega^{\pm}=\omega\pm\varepsilon\,\delta\zeta_{val}(\omega^{\prime},\alpha)/ \delta\omega^{\prime}\) and Eq. 8 is used for final \(\alpha\) gradient.

\[\delta\zeta_{val}(\omega^{\prime},\alpha)/\delta\alpha-\xi\,\delta\zeta_{val} (\omega^{\prime},\alpha)/\delta\omega^{\prime}\,\delta\delta\zeta_{trn}( \omega,\alpha)/\delta\omega\delta\alpha \tag{7}\]

\[\frac{\delta\delta\zeta_{trn}(\omega,\alpha)}{\delta\omega\delta\alpha}= \delta(\zeta_{trn}(\omega^{+},\alpha)-\zeta_{trn}(\omega^{-},\alpha))/(2 \varepsilon\delta\alpha) \tag{8}\]

With the help of analytical modeling of optimization objective, we are able to derive the differentiable polynomial architecture search framework in Algo. 1. The input of search framework includes backbone model \(M_{b}\), dataset \(D\), latency loop up table \(Lat(OP)\), and hardware resource \(H\). The algorithm returns a searched polynomial model \(M_{p}\). The algorithm iteratively trains the architecture parameter \(\alpha\) and weight \(\omega\) parameter till the convergence. Each \(\alpha\) update requires 4 forward paths and 5 backward paths according to Eq. 6 to Eq. 8, and each \(\omega\) update needs 1 forward paths and 1 backward paths. After the convergence of training loop, the algorithm returns a deterministic model architecture by applying \(OP_{l}(x)=OP_{l,k^{*}}(x),\;s.t.\;k^{*}=\text{argmax}_{k}\;\alpha_{l,k}\). The returned architecture is then used for 2PC based PI evaluation.

## IV Evaluation

**Hardware setup.** Our experiment platform is based on two ZCU104 MPSoCs, both are connected to a router with \(Rt_{bw}=1GB/s\) through LAN. The load/store bus width is 128-bit and our data is 32-bit, thus, we simultaneously load and store four data and implement the kernel on \(freq=200MHz\). Fixed point ring size is set as 32 bits for 2PC inference.

**Datasets and Backbone Models.** We evaluate RRNet on two public datasets: CIFAR-10 [37] and ImageNet [38] for image classification tasks.

Fig. 2: Overview of RRNet framework for 2PC DNN based private inference setup.
**Systems Setup.** All polynomial architecture search experiments are conducted in plaintext domain on Ubuntu 18.04 and Nvidia Quadro RTX 6000 GPU with 24 GB GPU memory. The cryptographic DNN inference experiment is conducted on an FPGA-based accelerator for 2PC DNN setup. Two ZCU104 boards are used for server 0 and server 1, which are equipped with XCZU7EV MPSoC for the PS-PL system. Two boards are connected to a router with the Ethernet LAN setup. The FPGA accelerators are optimized with coarse-grained and fine-grained pipeline structures.

### **Hardware-aware NAS Evaluation**

Our hardware-aware NAS experiment (algorithm described in Sec. III-C) was conducted on CIFAR-10 training dataset. A new training & validation dataset is randomly sampled from the CIFAR-10 training dataset with 50%-50% split ratio.

The hardware latency is modeled through FPGA performance predictor, and the \(\lambda\) for latency constraint in loss function is tuned to generate architectures with different latency-accuracy trade-off. Prior search starts, the major model parameters are randomly initialized, and the polynomial activation function is initialized through **STPAI** method. We use VGG-16 [39], ResNet-18, ResNet-34, ResNet-50 [40], and MobileNetV2 [41] as backbone model structure to evaluate our RRNet framework.

The finetuned model accuracy under 2PC setting with regard to \(\lambda\) setting can be found in Fig. 3(a). The baseline model with all ReLU setting and all-polynomial operation based model are also included in the figure for comparison. Generally, a higher polynomial replacement ratio leads to a lower accuracy. The VGG-16 model is the most vulnerable model in the study, while the complete polynomial replacement leads to a 3.2% accuracy degradation (baseline 93.5%). On the other side, ResNet family are very robust to full polynomial replacement and there are only \(0.26\%\) to \(0.34\%\) accuracy drop for ResNet-18 (baseline 93.7%), ResNet-34 (baseline 93.8%) and ResNet-50 (baseline 95.6%). MobileNetV2's is in between the performance of VGG and ResNet, in which a full polynomial replacement leads to \(1.27\%\) degradation (baseline 94.09%).

On the other hand, Fig. 3(b) presents the latency profiling result of searched models performance on CIFAR-10 dataset under 2PC setting. All polynomial replacement leads to 20 times speedup on VGG-16 (baseline 382 ms), 15 times speedup on MobileNetV2 (baseline 1543 ms), 26 times speedup, ResNet-18 (baseline 324 ms), 19 times speedup on ResNet-34 (baseline 435 ms), and 25 times on speedup ResNet-50 (baseline 922 ms). With most strict constraint \(\lambda\), the searched model latency is lower.

### **Cross-work ReLU Reduction Performance Comparison**

A further accuracy-ReLU count analysis is conducted and compared with SOTA works with ReLU reduction: DeepRe-Duce [27], DELPHI [30], CryptoNAS [28], and SNI [42]. As shown in Fig. 4, we generate the pareto frontier with best accuracy-ReLU count trade-off from our architecture search result. We name the selected models as **RRNet**, and compare it with other works. The accuracy-ReLU count comparison is show in Fig. 5. Our work achieves a much better accuracy vs. ReLU comparison than existing works, especially at the situation with extremely few ReLU counts.

## V **Conclusion**

In the work, to reduce the high comparison protocol overhead from the non-linear operators in 2PC-based privacy-preserving DL implementation, we propose the RRNet framework that enables low latency, high energy efficiency & accuracy 2PC-DL. Experiments show RRNet achieved a much higher ReLU reduction performance than all SOTA works on CIFAR-10 dataset.

Fig. 4: Accuracy-ReLU count trade-off on CIFAR-10.

Fig. 5: ReLU reduction comparison on CIFAR-10.

Fig. 3: RRNet framework evaluation under 2PC PI setup. Network bandwidth: 1 GB/s. Device: ZCU104.