GNNHLS: Evaluating Graph Neural Network Inference via High-Level
  Synthesis
With the ever-growing popularity of Graph Neural Networks (GNNs), efficient
GNN inference is gaining tremendous attention. Field-Programming Gate Arrays
(FPGAs) are a promising execution platform due to their fine-grained
parallelism, low-power consumption, reconfigurability, and concurrent
execution. Even better, High-Level Synthesis (HLS) tools bridge the gap between
the non-trivial FPGA development efforts and rapid emergence of new GNN models.
In this paper, we propose GNNHLS, an open-source framework to comprehensively
evaluate GNN inference acceleration on FPGAs via HLS, containing a software
stack for data generation and baseline deployment, and FPGA implementations of
6 well-tuned GNN HLS kernels. We evaluate GNNHLS on 4 graph datasets with
distinct topologies and scales. The results show that GNNHLS achieves up to
50.8x speedup and 423x energy reduction relative to the CPU baselines. Compared
with the GPU baselines, GNNHLS achieves up to 5.16x speedup and 74.5x energy
reduction.
Chenfeng Zhao, Zehao Dong, Yixin Chen, Xuan Zhang, Roger D. Chamberlain
# GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis

###### Abstract

With the ever-growing popularity of Graph Neural Networks (GNNs), efficient GNN inference is gaining tremendous attention. Field-Programming Gate Arrays (FPGAs) are a promising execution platform due to their fine-grained parallelism, low-power consumption, reconfigurability, and concurrent execution. Even better, High-Level Synthesis (HLS) tools bridge the gap between the non-trivial FPGA development efforts and rapid emergence of new GNN models. In this paper, we propose GNNHLS, an open-source framework to comprehensively evaluate GNN inference acceleration on FPGAs via HLS, containing a software stack for data generation and baseline deployment, and FPGA implementations of 6 well-tuned GNN HLS kernels. We evaluate GNNHLS on 4 graph datasets with distinct topologies and scales. The results show that GNNHLS achieves up to \(50.8\times\) speedup and \(423\times\) energy reduction relative to the CPU baselines. Compared with the GPU baselines, GNNHLS achieves up to \(5.16\times\) speedup and \(74.5\times\) energy reduction.

 field-programmable gate arrays, graph neural networks, high-level synthesis

## I Introduction

Graphs are widely adopted to model the relational-structured data in social networks, bioinformatics, etc [26]. Machine learning (ML) on graphs has experienced a surge of popularity in the past decade, since traditional ML models, which are designed to process Euclidean data with regular structures, are ineffective at performing prediction tasks on graphs. Due to their simplicity and superior representation learning ability, Graph Neural Networks (GNNs) [6, 12, 19, 23, 25] have achieved impressive performance on various graph learning tasks, such as node classification, graph classification, etc.

To implement GNNs, a set of widespread libraries, such as PyTorch Geometric (PYG) [8] and Deep Graph Library (DGL) [20], are built upon general-purpose ML frameworks (e.g. PyTorch [17]) targeting CPU and GPU platforms. However, the performance and energy consumption of GNN implementations are hindered by both hardware platforms and software frameworks: (1) Distinct from traditional NNs, GNNs combine the irregular communication-intensive patterns of graph processing and the regular computation-intensive patterns of NNs. This feature can lead to ineffectual computation on CPUs and GPUs. (2) Since these frameworks assemble functions in a sequential way, one function will not start until the previous one finishes. This execution model leads to extra memory accesses, footprint, and implicit barriers for intermediate results, limiting the potential performance, energy consumption and the scale of graph datasets.

Field-Programmable Gate Arrays (FPGAs) are potentially an attractive approach to GNN inference acceleration. FPGAs' massive fixed-grained parallelism provides opportunities to exploit GNNs' inherent parallelism. They also deliver better performance per watt than general-purpose computing platforms. In addition, FPGAs' reconfigurability and concurrency provide great flexibility to solve the challenges of hybrid computing patterns and ineffectual execution. Most of the prior works investigating FPGAs focus on accelerating a specific GNN model implemented using Hardware Description Languages (HDL). AWB-GCN [9], as one of the earliest FPGA-based works, proposes a GCN accelerator using HDL to solve the workload imbalance problem due to the distinct sparsity of different components. BoostGCN [24] proposes a graph partition algorithm in a preprocessing step to address workload imbalance issues. Despite these promising results, HDL design methodology is not suitable for widespread adoption for GNN implementations due to the conflict between the non-trivial development efforts with HDL and the rapid emergence of new GNN models. To address this challenge, High-Level Synthesis (HLS) tools are proposed to create GNN kernels using popular languages such as C/C++. With the help of HLS, development time is substantially shortened relative to HDL designs. Lin et al. [15], as one of the first works, proposes an HLS-based accelerator for GCN with separated sparse-dense matrix multiplication units and dense matrix multiplication units which are connected by shared memory and execute sequentially. GenGNN [1] proposes a framework to accelerate GNNs for real-time requirements where the whole graph and corresponding intermediate results are stored in on-chip resources on the FPGA. Despite these promising results, this work is limited to small-scale graphs with low edge-to-node ratio due to on-chip memory usage being proportional to graph scale and feature dimensions.

Distinct from pure software programming, HLS developers need to adopt multiple optimization pragmas and follow certain coding styles to achieve best performance and energy cost. As reported in [3], the performance difference between a well-optimized version and a non-optimized version of the same kernel can be two to three orders of magnitude. This invites an open question: _how effectively can modern HLS tools_
accelerate GNN inference?_

In this paper, we introduce GNNHLS1 an open-source framework for comprehensive evaluation of GNN kernels on FPGAs via HLS. GNNHLS contains a software stack extended from a prior GNN benchmark [7] based on PyTorch and DGL for input data generation and conventional platform baseline deployments (i.e., CPUs and GPUs). It also contains six well-optimized general-purpose GNN applications. These kernels can be classified into 2 classes: (1) isotropic GNNs in which every neighbor contributes equally to the update of the target vertex, and (2) anisotropic GNNs in which edges and neighbors contribute differently to the update due to the adoption of operations such as attention and gating mechanisms. In this paper, we make several contributions:

Footnote 1: Released as a benchmark suite [28] and also available at [https://github.com/Chernfeng/Zhao/GNNHLS](https://github.com/Chernfeng/Zhao/GNNHLS)

* We propose GNNHLS, a framework to evaluate GNN inference acceleration via HLS, containing: (a) a software stack based on PyTorch and DGL for data generation and baseline deployment, and (b) FPGA implementation including 6 well-tuned GNN HLS kernels with host and configuration files which can also be used as benchmarks.
* We characterize the GNN kernels in terms of locality scores and instruction mix to obtain insight into their memory access and computational properties.
* We provide a comprehensive evaluation of our GNN HLS implementations on 4 graph datasets, assessing both performance improvement and energy reduction.

Our evaluation results show that GNNHLS provides up to \(50.8\times\) speedup and \(423\times\) energy reduction relative to the multicore CPU baseline. Compared with the GPU baselines, GNNHLS achieves up to \(5.16\times\) speedup and \(74.5\times\) energy reduction.

## II Framework Description

### _GNNHLS Overview_

The GNNHLS framework, as depicted in Figure 1, comprises two primary components: data generation and HLS FPGA. The former is designed to generate input and output files and measure baselines on a CPU and a GPU, while the latter is designed to implement the optimized HLS applications on an FPGA. The data generation component mainly consists of the training system and the inference system, which are based on PyTorch and DGL. To account for the impact of graph topology on GNN model performance, it uses graph datasets with various topologies, including those from Open Graph Benchmarks [11]. In addition, six commonly used DGL GNN models obtained from a previous GNN benchmark [7] are incorporated. Thus, realistic model parameters, generated in the training phase, are utilized in inference.

The HLS FPGA component implements the GNN kernels on the FPGA. These kernels match the functionality of the DGL baselines and are optimized with several optimization techniques [4]. The optimized HLS kernels, with associated host files, data header files, and configuration files, are compiled by Vitis and executed on the FPGA. The optimization techniques applied in GNNHLS are described as follows:

**Pipeline**: Enable instruction-level concurrent execution to improve overall throughput. **Loop Merge**: Optimize the finite state machine (FSM) of nested loops to remove the impact of inner loop latency on the overall throughput. **Burst Memory Access & Memory Port Widening**: access large chunks of data in contiguous addresses and increase memory port width to improve memory bandwidth. **Loop Unroll**: Leverage instruction-level parallelism by executing multiple copies of loop iterations in parallel to increase throughput at the cost of resource utilization. **Dataflow**: Enable task-level parallelism by connecting multiple functions with FIFOs to form a pipeline-style architecture and executing them concurrently. **Multiple Compute Units (CUs)**: Execute multiple kernel instances as CUs in parallel for different data portions at the cost of resource usage.

Figure 2 illustrates the Dataflow diagrams of the GNNHLS kernels, in which memory and computation operations are divided and pipelined based on the complexity of each kernel. To mitigate the cost of Dataflow, we also (1) tune the location of FIFO accesses to achieve better throughput, (2) apply vectors for FIFO widening and associated operations, and (3) split loops to optimize the FIFO properties of loop indices.

### _Graph Convolutional Network (GCN)_

Graph Convolutional Network (GCN) [12] is one of the earliest GNN models and has a simple structure. It updates node features by aggregating neighboring node features and performing linear projection. The formula is given as follows:

\[h_{i}^{l+1}=\mathrm{ReLU}\left(U^{l}\sum_{j\in N_{i}}h_{j}^{l}\right) \tag{1}\]

Where \(U^{l}\in\mathbb{R}^{d\times d}\) is the learnable weight matrix of the linear projection, which performs vector-matrix multiplication. \(h_{i}^{l}\in\mathbb{R}^{d\times 1}\) is the feature vector of vertex \(i\) in layer \(l\), and \(N_{i}\) represents the neighboring vertices of vertex \(i\).

Based on the above equation, we create the GCN HLS implementation, the Dataflow diagram of which is depicted in Figure 2(a). In addition to the memory access modules for input graphs and \(h\), we split the computation operations into

Fig. 1: Diagram of the GNNHLS framework.
two modules: Aggregation of neighbor node vectors \(h_{j}\) and vector-matrix multiplication (VMM) for linear projection. We perform all the optimization techniques described previously to the GCN kernel. The memory burst length vector \(h\) is \(d\), limited by the irregularity of the graph topology. The initiation interval (II) of the aggregation module is \(4\left|N_{i}\right|+2\). Since Vitis is not good at synthesizing tree-structured floating-point operations, we separate VMM into 2 functions in the Dataflow scope for grouped VMM and sum, respectively. The II of VMM is thereby reduced from \(d^{2}\) to \(d+36\). All these modules are reused in the following GNN models. Due to its simplicity, we create 2 CUs to process distinct vertices in parallel.

### _GraphSage (GS)_

GraphSage (GS) [10] introduces an inductive framework to improve the scalability over GCN by aggregating information from the fixed-size set of neighbors via uniform sampling, explicitly incorporating feature vectors of both the target vertex and its source neighbors. The mathematical expression of GraphSage with a mean aggregator is formulated as follows:

\[\begin{split} h_{i}^{l+1}&=\mathrm{ReLU}\left(U^{l }\mathrm{Concat}\left(h_{i}^{l},\frac{1}{\left|N_{i}\right|}\sum_{j\in N_{i}}h _{j}^{l}\right)\right)\\ &=\mathrm{ReLU}\left(V^{l}h_{i}^{l}+W^{l}\frac{1}{\left|N_{i} \right|}\sum_{j\in N_{i}}h_{j}^{l}\right)\end{split} \tag{2}\]

Where \(N_{i}\) is the set of source neighbors of vertex \(i\), and \(h_{i}^{l}\in\mathbb{R}^{d\times 1}\) is the feature vector of vertex \(i\) in layer \(l\). The learnable weight matrix of the linear projection, \(U^{l}\in\mathbb{R}^{d\times 2d}\), is stored in on-chip memory. Given that distinct weight parameters are used for the target vertex and source neighbors, \(U^{l}\) is divided into \(V^{l}\in\mathbb{R}^{d\times d}\) and \(W^{l}\in\mathbb{R}^{d\times d}\), enabling parallel execution of both paths to hide the latency of linear projection for the target vertex. Figure 2(b) illustrates the Dataflow structure of GraphSage. The memory read accesses and linear projection of the target feature, and neighbors' feature aggregation are executed simultaneously, and then summed up to update \(h_{i}\).

### _Graph Isomorphism Network (GIN)_

Graph Isomorphism Network (GIN) [23] employs the Weisfeiler-Lehman Isomorphism Test [22] as its foundation to investigate the discriminative ability of GNNs. The formula of GIN is described as follows:

\[h_{i}^{l+1}=\mathrm{ReLU}\left(U^{l}\mathrm{ReLU}\left(V^{l}\left((1+\epsilon )h_{i}^{l}+\sum_{j\in N_{i}}h_{j}^{l}\right)\right)\right) \tag{3}\]

where \(\epsilon\) is a learnable scalar weight, \(U^{l}\) and \(V^{l}\in\mathbb{R}^{d\times d}\) denote learnable weight matrices of cascaded VMM modules, \(h_{i}^{l}\in\mathbb{R}^{d\times 1}\) again refers to the feature vector of vertex \(i\) in layer \(l\), and \(N_{i}\) is again the source neighbors of vertex \(i\). In contrast to GraphSage, GIN illustrated in Figure 2(c) first sums up the aggregated vector of neighbors \(h_{j}\) and the target vertex vector \(h_{i}\), hiding the latency of reading \(h_{i}\), then performs two cascaded VMM modules with weight matrices \(U^{l}\) and \(V^{l}\), respectively. This framework avoids the generation of long critical paths and achieves a higher clock frequency.

### _Graph Attention Network (GAT)_

Graph Attention Network (GAT) [19] is an anisotropic GNN model that uses self-attention mechanisms to weight and learn representations of neighbor vertices unequally. The equation is described as follows:

Fig. 2: Dataflow diagrams of GNN HLS kernels in GNNHLS.
\[h_{i}^{l+1} =\mathrm{Concat}_{k=1}^{K}\left(\mathrm{ELU}\left(\sum_{j\in N_{i}} \alpha_{ij}^{k,l}U^{k,l}h_{j}^{l}\right)\right) \tag{4}\] \[\alpha_{ij}^{k,l} =\mathrm{Softmax}(e_{ij}^{k,l})=\frac{\exp(e_{ij}^{k,l})}{\sum_{j^ {\prime}\in N_{i}}\exp(e_{ij^{\prime}}^{k,l})}\] (5) \[e_{ij}^{k,l} =\mathrm{LeakyReLU}(\vec{a}^{T}Concat(U^{k,l}h_{i}^{l},U^{k,l}h_{ j}^{l}))\] \[=\mathrm{LeakyReLU}(a_{src}^{k,l}U^{k,l}h_{i}^{l}+a_{dest}^{k,l}U ^{k,l}h_{j}^{l}) \tag{6}\]

where \(\alpha_{ij}^{l}\in\mathbb{R}^{K}\) is the attention score between vertex \(i\) and vertex \(j\) of layer \(l\), \(U^{k,l}\in\mathbb{R}^{d\times d}\) and \(\vec{a}\in\mathbb{R}^{2d}\) are learnable parameters. Note that the weight parameter \(\vec{a}^{T}\) is decomposed into \(a_{src}^{l}\) and \(a_{dest}^{l}\in\mathbb{R}^{d}\) in the DGL library, because it is more efficient in terms of performance and memory footprint by transferring VMM between \(U^{k,l}\) and \(h^{l}\) from edge-wise to node-wise operations, especially for sparse graphs where the edge number is larger than the vertex number.

Figure 2(d) depicts the Dataflow framework of GAT. Due to the unbalanced workload of the numerator and the denominator in (5), the results of \(\exp(e_{ij})\), size \(O(|N_{i}|)\), need to be temporarily stored prior to being accumulated. Considering the irregularity and large maximum \(|N_{i}|\) of graphs, we divide the GAT model into 2 HLS kernels linked to the same memory banks for shared intermediate results: kernel 1 is designed to perform VMM with \(U\) and \(h\), and multi-headed element-wise multiplication (MHEWM) with \(a_{src}\) and \(a_{dest}\), respectively, in (6). After being optimized, the II of MHEWM is \(k+112\). The intermediate results are written back to memory and then read by kernel 2 to implement (4) and (5). Note that \(e_{ij}\) is computed twice in parallel to avoid performance degradation and deadlock issues. The II of aggregation, softmax, and MHEWM is \(k\cdot|N_{i}|+2k+38\), \(k\cdot|N_{i}|+k+17\), and \(k\cdot|N_{i}|+k+14\), respectively.

### _Mixture Model Networks (MoNet)_

Mixture Model Networks (MoNet) [16] is a general anisotropic GNN framework designed for graph and node classification tasks using Baysian Gaussian Mixture Model (GMM) [5]. The model is formulated as follow:

\[h_{i}^{l+1} =\mathrm{ReLU}\left(\sum_{k=1}^{K}\sum_{j\in N_{i}}w_{k}(u_{ij})U ^{k,l}h_{j}^{l}\right)\] \[=\mathrm{ReLU}\left(\sum_{k=1}^{K}U^{k,l}\sum_{j\in N_{i}}w_{k}(u _{ij})h_{j}^{l}\right) \tag{7}\] \[w_{k}(u_{ij}) =\exp\left(-\frac{1}{2}(u_{ij}^{l}-\mu_{k}^{l})^{T}(\sum_{k}^{l} )^{-1}(u_{ij}^{l}-\mu_{k}^{l})\right)\] (8) \[u_{ij}^{l} =\mathrm{Tanh}(V^{l}pseudo_{ij}^{l}+v^{l})\] (9) \[pseudo_{ij}^{l} =\mathrm{Concat}(deg_{i}^{-0.5},deg_{j}^{0.5}) \tag{10}\]

where \(v^{l}\in\mathbb{R}^{2}\), \(V^{l}\in\mathbb{R}^{2\times 2}\), \(\mu\in\mathbb{R}^{K\times 2}\), \((\sum_{k}^{l})^{-1}\in\mathbb{R}^{K\times 2}\), and \(U^{l}\in\mathbb{R}^{d\times d}\) are learnable parameters of GMM. \(v^{l}\) and \(V^{l}\) represent the pseudo-coordinates between the target vertex and its neighbors, \(\mu\in\mathbb{R}^{K\times 2}\) and \((\sum_{k}^{l})^{-1}\in\mathbb{R}^{K\times 2}\) denote the mean vector and covariance matrix. \(U^{k,l}\) is the weight matrix.

The Dataflow diagram of MoNet is depicted in Figure 2(e). In our HLS implementation, \(pseudo_{ij}\) of each edge is processed by a small VMM module with \(V^{l}\) and \(v^{l}\) in (9) and the Gaussian Weight Computation module with \(\mu\) and \((\sum_{k}^{l})^{-1}\) in (8). Meanwhile, \(h_{j}\) is read from memory for the subsequent MHEWM with aggregation, MHVMM with \(U\), and MH Aggregation modules. Note that we perform the MH VMM with \(U\) after aggregation in (7), transferring it from an edge-wise to node-wise operation to reduce its occurrence. After optimization, the II of the VMM for \(u_{ij}\), Gaussian computation, MHEWM with aggregation, MHVMM with \(U\), and MH Aggregation are 1, 1, 4, \(d+k+28\), and \(7k+10\), respectively. We create 2 CUs for the HLS kernel to process vertices with distinct indices.

### _Gated Graph ConvNet (GatedGCN)_

The Gated Graph ConvNet (GatedGCN) [2] is a type of anisotropic graph neural network (GNN) model that employs a gating mechanism to regulate the flow of information during message passing, allowing the model to emphasize relevant information and filter out irrelevant one. The gating mechanism utilizes gate functions (e.g., sigmoid) to control the flow of messages at each layer. The mathematical expression for GatedGCN is provided below:

\[h_{i}^{l+1} =\mathrm{ReLU}\left(A^{l}h_{i}^{l}+\frac{\sum_{j^{\prime}\in N_{i} }B^{l}h_{j^{\prime}}^{l}\odot\sigma(e_{ij^{\prime}}^{l+1})}{\sum_{j^{\prime} \in N_{i}}\sigma(e_{ij^{\prime}}^{l+1})+\epsilon}\right) \tag{11}\] \[e_{ij}^{l+1} =E^{l}h_{i}^{l}+D^{l}h_{j}^{l}+C^{l}e_{ij}^{l} \tag{12}\]

where \(A^{l}\), \(B^{l}\), \(D^{l}\), \(E^{l}\) and \(C^{l}\in\mathbb{R}^{d\times d}\) are learnable matrix parameters, \(e_{ij}^{l}\in\mathbb{R}^{1\times d}\) denote the edge features from vertex \(i\) to \(j\) layer \(l\), \(h_{i}^{l}\) represents node features of vertex \(i\) in layer \(l\), \(\odot\) denotes Hadamard product, \(\sigma\) denotes the sigmoid function, and \(\epsilon\) is a constant for numerical stability.

Since the soft attention of GatedGCN shown in (11) is distinct from GAT, performing accumulation operations for \(e_{ij}\) on both the numerator and denominator, we implement a single pipeline to build the HLS kernel. Figure 2(f) illustrates the Dataflow framework of GatedGCN. To hide the latency of multiple VMM modules in GatedGCN, we perform all of them in parallel with parameters \(A\), \(B\), \(D\), \(E\), and \(C\), respectively. Then the soft attention module is implemented to update \(h_{i}\). After optimization, the II of the soft attention and sum modules to generate \(h_{i}^{l+1}\) are \(10\cdot|N_{i}|+72\) and 31, respectively.

## III Experimental Methodology

**Datasets:** Table I shows the graph datasets used in our evaluation. All these graphs are collected from Open Graph Benchmark [11], a widely-used graph library for GNNs, and have a wide range of fields and scales. These graphs represent two classes of graphs with distinct topologies used in the GNN community: MH and MT consist of multiple small dense graphs, while AX and PT each consist of one single sparse
graph. The maximum and average degree shown in Table I indicates their varying distributions ranging from regular-like to powerlaw-like. In addition, we set feature dimensions for the kernels: GCN, GraphSage, and GIN have the same input and output dimensions at 128. The input, head, and output dimensions of GAT and MoNet are (128, 8, 16) and (64, 2, 64), respectively. All the dimensions of GatedGCN are 32.

**Evaluation methods:** To perform evaluation, we use a Xilinx Alveo U280 FPGA card, provided by the Open Cloud Testbed [13], to execute the HLS kernels. This FPGA card provides 8 GB of HBM2 with 32 memory banks at 460 GB/s total bandwidth, 32 GB of DDR memory at 38 GB/s, and 3 super logic regions (SLRs) with 1205K look-up tables (LUTs), 2478K registers, 1816 BRAMs, and 9020 DSPs. We adopt 32-bit floating point as the data format. We use Vitis 2020.2 for synthesis and hardware linkage with the power-profile option enabled to perform power profiling during runtime, and Vitis Analyzer to view resource utilization, execution time and power consumption. We compare our HLS implementation with CPU and GPU baselines with PyTorch and the highly-optimized DGL library. We perform CPU baseline runs on an Intel Xeon Silver 4114 at 2.2 GHz with 10 cores, 20 threads, and 13.75 MB L3 cache. The GPU baseline is implemented on an Nvidia RTX 2080 Ti with 2994 CUDA cores at 1.5 GHz and 8 GB GDDR6 at 448 GB/s total bandwidth. We measure the energy consumption of the CPU and GPU baselines using the same technique as prior work [15].

## IV Characterization

To capture insight into the properties of GNNHLS, we first characterize the GNN kernels using instruction mix, spatial locality, and temporal locality. We use Workload ISA-Independent Characterization (WIICA) [18], a workload characterization tool, to capture ISA-independent properties by generating and parsing a dynamic trace of runtime information. Due to the limits of disk and processing time, profiling the the full trace is impractical. Thus we use uniform random node sampling [14] to select a sequence of 500 nodes for evaluation.
induces non-contiguous memory references, limiting memory burst transfer and prefetching to the length of feature sizes. Next examining the temporal locality, we observe that the score stays in the range of \(0.5-0.7\), indicating the potential performance benefit of cacheing mechanisms, regardless of the graph topology. In addition, we observe anisotropic kernels show a higher temporal locality than isotropic kernels, due to them having more edge-wise operations.

## V Evaluation

### _Resource Utilization_

We first examine the resource utilization and clock frequency after place & route. FPGA resources include look-up tables (LUT), flip-flops (FF), BRAM, and digital-signal-processors (DSP). Table II shows these results. From the table, we observe that the frequency of all the kernels is lower than the target frequency, which is not unusual in FPGA designs. Among these kernels, GraphSage achieves a low frequency due to some critical paths which are unresolvable by the tool. In addition, we observe that the resources on the FPGA are not over-utilized.

### _Performance_

We next examine the performance improvement by showing the overall speedup, defined as the execution time of the GNN HLS kernels relative to CPU-DGL (using all 10 cores on the CPU), in Figure 5. Table III shows the execution time of baselines and HLS kernels. Note that GPU results of GAT, MN, and GGCN on PT cannot be obtained because of running out of memory (OoM). Examining each kernel in Figure 5, we observe that the HLS implementation is not always outperforming corresponding CPU baselines. Compared with DGL-CPU, the speedup ranges from \(0.47\times\) to \(50.8\times\).

Among isotropic GNN kernels, GCN achieves better performance than GraphSage and GIN, ranging from \(1.08\times\) to \(1.98\times\) because its simpler structure enables us to create two CUs to leverage spatial data parallelism. In contrast, we can only create one CU for GraphSage and GIN each because of their complex structure and heavy resource usage. In addition, we observe that the execution time of GraphSage and GIN are close. Thus, we conclude that the distinction on the structure of these two GNN models will not substantially affect HLS implementation results.

Among anisotropic kernels, MoNet achieves highest performance improvement ranging from \(6.04\times\) to \(50.8\times\) due to (1) its single pipeline structure with computation order optimization where the node-wise operations are placed behind the edge-wise operations, and (2) well-designed MHVMM modules with lower II, especially MHVMM whose II is \(O(d+k)\) instead of \(O(dk)\). In spite of the 2-pipeline structure of GAT, we observe that it still achieves \(4.31\times\) to \(6.61\times\) speedup relative to multi-core CPU baselines. In addition, since the feature size of GatedGCN is smaller, leading to more performance improvement for CPU baselines with time complexity of \(O(d^{2})\), its speedup is not comparable to other anisotropic kernels, ranging from \(0.5\times\) to \(1.16\times\).

Turning our attention to how the performance benefit of HLS implementations varies across graph datasets, we observe that the speedup of isotropic kernels relative to DGL-CPU on regular-like graphs (i.e., MT and MH) is higher than powerlaw-like graphs (i.e., AX and PT) because (1) the edge-wise operations are less computation-intensive than node-wise operations in these kernels, making the baselines more computationally efficient on powerlaw-like graphs containing more edges than nodes; and (2) the edge-wise aggregation operations in HLS implementations are executed sequentially without leveraging edge-level parallelism, making these HLS kernels less computationally efficient for powerlaw-like graphs. Distinct from isotropic kernels, the speedup of anisotropic kernels on powerlaw-like graphs is higher than regular-like graphs because the edge-wise operations of these kernels are more computation-intensive than isotropic kernels, making baselines less efficient on powerlaw-like graphs.

Focusing on the second and the third bar, we observe that DGL-GPU outperforms HLS implementations in many cases, due to the high-performance fixed-function accelerators in the GPU. The speedup of HLS kernels relative to the GPU baselines ranges from \(0.13\times-5.16\times\). In spite of the promising GPU performance, there are still some drawbacks of GPU compared with HLS implementations. For the execution of isotropic GNN models, DGL-GPU achieves lower speedup than HLS on small-scale graphs such as MT and AX. It is speculated that the GPU is designed to achieve high throughput in the cost of latency which plays a more important role for small-scale graphs than large-scale graphs. In addition, compared with HLS implementations on FPGA, GPU is also not suitable for the execution of anisotropic GNN models on large-scale, especially powerlaw-like graphs (e.g., PT) due to (1) the non-trivial memory footprint caused by its sequential execution paradigm to store intermediate results of edge-wise operations, and (2) insufficient memory capacity on the GPU board. That is why we failed to execute anisotropic GNNs on PT with GPU. It is solved by the HLS implementations' pipeline structure not storing the intermediate results.

Since GenGNN [1] also discusses 3 of the GNN models included in this paper (GCN, GIN, and GAT), we can make a limited comparison of our GNN HLS implementations with theirs. The two are not directly comparable for a number of reasons: (1) the feature dimensions of our GNN HLS kernels are higher, (2) we use off-chip memory instead of on-chip memory, (3) our general-purpose GNN HLS kernels focus
more on throughput rather than real-time latency, and (4) the FPGAs are from the same family, but are not same part. The performance of our HLS kernels exceeds that of GenGNN, achieving overall speedup of \(35\times\), \(5\times\), and \(6\times\) over GCN, GIN, and GAT, on MT, respectively.

### _Optimization Techniques_

As described in Section II, we apply multiple optimization techniques to the HLS kernels. In order to evaluate the efficacy of these techniques, we use GraphSage on MT as a case study. Table IV presents the execution time of GraphSage with the combined impact of optimization techniques applied. The reported execution time of each technique represents the effect of both the current technique and above techniques listed in the table. In the table, No Pragma means we don't intentionally apply any pragmas to the HLS code, except for those automatically applied by Vitis (i.e., Pipeline, Loop Merge, and Memory optimizations). Dataflow denotes that we apply dataflow pragma and FIFO streams to exploit the task-level parallelism of each application. Loop Unroll means we apply loop unroll pragmas to completely or partially unroll for loops, keeping II as low as possible while exploiting instruction parallelism. Vectorization means using vector data types to widen the width of FIFO streams and corresponding operations to decrease the cost of FIFO accesses. Split Loops means splitting the outer-most node loop and putting it inside each function connected by streams to further optimize FIFO properties inferred from loop indices.

We observe that Loop Unroll achieves the highest performance improvement. Therefore, exploiting instruction parallelism is still the primary choice for GNN HLS optimization. In order to further improve performance, exploiting task-level parallelism is necessary. Focusing on the first and second row in the table, we observe that only performing the dataflow pragma and streams in a naive way obtains \(1.99\times\) performance improvement. By applying Vectorization and Split Loops as complementary techniques of Dataflow, performance is further improved by \(2.5\times\) and \(3.9\times\), respectively. After applying all the optimization techniques together we observe that the performance of GraphSage is improved by \(132\times\).

### _Energy Consumption_

We next present a quantitative analysis of the energy consumption. Figure 6 displays the energy reduction of both DGL-GPU and HLS implementations relative to DGL-CPU in logarithmic scale. Energy reduction is calculated as the energy consumption of DGL-GPU or HLS divided by that of DGL-CPU. Examining the final bar of each application and dataset, we observe that HLS implementations consume less energy than CPU and GPU baselines in all cases. The energy reduction ranges from \(2.95\times\) to \(423\times\) relative to DGL-CPU and from \(2.38\times\) to \(74.5\times\) relative to DGL-GPU. It is because of the low power of FPGA logic, low clock frequency, and efficient pipeline structure of HLS implementations.

Fig. 5: Speedup of HLS kernels relative to DGL-CPU. The higher the better.
Focusing on the first and last bar, we observe a similar tendency in energy reduction as in performance: for isotropic GNN models, denser graphs result in lower energy reduction, whereas for anisotropic GNN models, denser graphs result in higher energy reduction. This leads us to conclude that improving GNN applications generally will require some degree of graph topology awareness.

## VI Conclusions

In this paper, we propose GNNHLS, an open-source framework to comprehensively evaluate GNN inference acceleration on FPGAs via HLS. GNNHLS consists of a software stack for data generation and baseline deployment, and 6 well-tuned GNN HLS kernels. We characterize the HLS kernels in terms of instruction mix and memory locality scores, and evaluate them on 4 graph datasets with various topologies and scales. Results show up to \(50.8\times\) speedup and \(423\times\) energy reduction relative to the multi-core CPU baselines. Compared with GPU baselines, GNNHLS achieves up to \(5.16\times\) speedup and \(74.5\times\) energy reduction. In the future, we will extend GNNHLS to more GNN models and graph datasets. It can also be useful as a benchmark or baseline for HLS researchers to explore the potential of HLS tools on GNN inference acceleration. GNNHLS has been released for use as a benchmark suite [28].

## Acknowledgment

This work is supported by NSF under grants CNS-1739643 and CNS-1763503 and a gift from BECS Technology, Inc. The authors are grateful for the use of the Open Cloud Testbed [13] as an experimentation platform.
