Leveraging Residue Number System for Designing High-Precision Analog
  Deep Neural Network Accelerators
Achieving high accuracy, while maintaining good energy efficiency, in analog
DNN accelerators is challenging as high-precision data converters are
expensive. In this paper, we overcome this challenge by using the residue
number system (RNS) to compose high-precision operations from multiple
low-precision operations. This enables us to eliminate the information loss
caused by the limited precision of the ADCs. Our study shows that RNS can
achieve 99% FP32 accuracy for state-of-the-art DNN inference using data
converters with only $6$-bit precision. We propose using redundant RNS to
achieve a fault-tolerant analog accelerator. In addition, we show that RNS can
reduce the energy consumption of the data converters within an analog
accelerator by several orders of magnitude compared to a regular fixed-point
approach.
Cansu Demirkiran, Rashmi Agrawal, Vijay Janapa Reddi, Darius Bunandar, Ajay Joshi
Leveraging Residue Number System for Designing High-Precision Analog Deep Neural Network Accelerators

###### Abstract

Achieving high accuracy, while maintaining good energy efficiency, in analog DNN accelerators is challenging as high-precision data converters are expensive. In this paper, we overcome this challenge by using the residue number system (RNS) to compose high-precision operations from multiple low-precision operations. This enables us to eliminate the information loss caused by the limited precision of the ADCs. Our study shows that RNS can achieve \(99\%\) FP32 accuracy for state-of-the-art DNN inference using data converters with only \(6\)-bit precision. We propose using redundant RNS to achieve a fault-tolerant analog accelerator. In addition, we show that RNS can reduce the energy consumption of the data converters within an analog accelerator by several orders of magnitude compared to a regular fixed-point approach.

 analog design, accelerators, residue number system, deep neural networks

## I Introduction

Deep Neural Networks (DNNs) are commonly used today in a variety of applications including financial, healthcare, and transportation. The pervasive usage of these DNN models, whose sizes are continuously increasing, forces us to use more compute, communication, and memory resources. Unfortunately, with Moore's Law and Dennard Scaling slowing down [1], we can no longer rely on technology scaling. As a result, these ever-growing DNNs come with higher and higher costs in terms of energy, time, money, and environmental impact.

For performing efficient DNN inference, several works have explored analog accelerator designs. These analog designs accelerate general matrix-matrix multiplication (GEMM) operations that make up more than \(90\%\) of the operations in DNN inference. The prior art have explored several analog technologies such as photonic cores [2, 3, 4, 5, 6],, resistive arrays [7, 8, 9, 10, 11], switched capacitor arrays [12, 13], PCM [14], STT-RAM [15, 16], etc., to enable highly parallel, fast, and efficient matrix-vector multiplications (MVMs) in the analog domain.

The success of this analog approach is, however, constrained by the limited precision of the digital-to-analog and analog-to-digital data converters (i.e., DACs and ADCs) which typically dominate the energy consumption in analog accelerators [17, 9, 18]. Concretely, during MVM, a dot product between a \(b_{\text{w}}\)-bit signed weight vector and a \(b_{\text{in}}\)-bit signed input vector--each with \(h\) elements--produces an output scalar with \(b_{\text{out}}\) bits of information, where \(b_{\text{out}}=b_{\text{in}}+b_{w}+\log_{2}(h)-1\). Therefore, an ADC with precision greater than \(b_{\text{out}}\) is required to guarantee no loss of information when capturing the output. Unfortunately, the energy consumption of ADCs increases exponentially with the effective number of bits (ENOB) (roughly \(4\times\) increase for each additional output bit) [19]. So for energy-efficient analog accelerator designs, it is typical to use ADCs with a lower precision (\(b_{\text{ADC}}<b_{\text{out}}\)) and only read the most significant bits (MSBs) of the output [17].

Rekhi et al. [17] showed that while this limited precision does not cause a significant accuracy drop in small networks with small datasets, it can drastically degrade the accuracy in larger networks. To better understand this, we analyzed (see Fig. 1) how the precision of DACs (i.e., \(b_{\text{in}}\) and \(b_{w}\)) and ADCs (i.e., \(b_{\text{ADC}}\)), and the number of elements within a single vector (i.e., \(h\)) affect the accuracy in two tasks: (1) a two-layer convolutional neural network (CNN) for classifying the MNIST dataset [20]: a simpler task with only 10 classes, and (2) ResNet50 [21], a CNN with 50 layers, for classifying the ImageNet dataset [22]: a more difficult task with 1000 classes. As the vector size \(h\) increases, \(b_{\text{out}}\) increases, therefore, higher precision is needed to maintain the accuracy. At all bit precisions, the accuracy of ResNet50 degrades at smaller values of \(h\) than the two-layer CNN. Essentially, to efficiently execute large DNNs using analog accelerators while maintaining high accuracy, we need a cheaper way to increase the computation precision than simply increasing the bit precision of the data converters.

In this paper, we propose to leverage the residue number system (RNS) to design analog accelerators, to enable the use of low-precision ADCs while performing high-precision arithmetic. We take advantage of the fact that RNS can represent high-precision values using low-precision integer residues for a chosen set of moduli. As RNS is closed under multiplication and addition, a full dot-product can be performed without switching between numeral systems. The modulo operation in the RNS ensures that the bit width of the residues does not grow to be larger than the bit width of the chosen moduli. This keeps the output residues at the same bit precision as the input residues after a dot product. Therefore, the low-precision output residues can be captured by low-precision ADCs without any information loss and eventually be used to generate a high-precision GEMM output.

Fig. 1: Accuracy of a two-layer CNN classifying handwritten digits from the MNIST dataset and ResNet50 classifying images from the ImageNet dataset evaluated in an analog core with varying precision \(b\) and vector sizes \(h\). For all evaluations, \(b\)-bit precision means we set \(b_{\text{in}}=b_{w}=b_{\text{ADC}}=b\).
Our contributions in this work are as follows:

We present a dataflow for a generic analog RNS-based accelerator. We evaluate the effectiveness of the proposed RNS approach by comparing the accuracy of an RNS-based analog hardware against a regular fixed-point-based analog hardware using state-of-the-art MLPerf (datacenters) DNN benchmarks [23]. To improve the fault tolerance of the analog accelerator, we incorporate the Redundant RNS (RRNS) error-correcting code [24] in the analog RNS-based accelerator. We use redundant residues to detect and correct errors at the output of a dot product. We evaluate the fault tolerance of the error-corrected analog accelerator by injecting noise and investigating its effects on the accuracy of the MLPerf benchmarks.

We investigate the energy efficiency advantage of using our RNS approach over regular fixed-point number system in analog accelerators. Our results show that, thanks to the use of low-precision data converters enabled by our RNS-based approach, the energy consumed by data converters (that dominate the energy consumption in analog accelerators) can be reduced by multiple orders of magnitude compared to the same precision regular analog approach.

## II Related Work

Prior works have investigated several analog technologies such as photonic cores [2, 3, 4, 5, 6], resistive arrays [7, 8, 9, 10, 11], switched capacitor arrays [12, 13], PCM cells [14], STT-RAM [15, 16], etc., for DNN acceleration. Many of these analog DNN accelerator works [2, 3, 7] have mainly reported accuracy results only for easy tasks such as classification of small datasets (e.g., MNIST, CIFAR) that work well with very low precision. A few other works [5, 6] used larger and more recent networks in their evaluation but solely focused on hardware performance and architectural design without reporting accuracy with the assumption that 8-bit DACs and ADCs provide adequate precision for high-accuracy DNN inference. However, as shown in Figure 1, this assumption may not be valid for all DNNs and hardware configurations. _In our work, we focus on state-of-the-art networks instead of small tasks that are practically obsolete._

RNS has been used in the analog domain for building optical adders and multipliers for reducing the optical critical path [25] and increasing efficiency in DNNs [4]. However, this requires a number of optical devices that increases quadratically with the modulus value--degrading their efficiency for large moduli. _In our work, the number of analog devices is independent of the size of the moduli._

There also exist digital DNN accelerators [26, 27] that use RNS for energy-efficient computation. These works show that it is possible to stay in the RNS domain (without reverting back to binary or decimal) for the entire inference. However, this approach requires overflow detection and scaling and also uses approximations for non-linear operations. Most state-of-the-art DNNs today comprise a wide variety of non-linear operations. Using approximations and fixed-point-only arithmetic for these operations can severely degrade the accuracy. Therefore, _in our work, we use RNS only for MVM operations and switch back to floating-point arithmetic for non-linear operations._

Bit-partitioned arithmetic [28] is another way to build high-precision results from low-precision operations and eliminate the need for costly high-precision ADCs. Shafiee et al. [9] use an iterative process where 16-bit inputs are represented as 16 1-bit values to eliminate the DACs and reduce the required precision of ADCs. However, their iterative approach takes more than one cycle to compute the dot products. In addition, both the RNS and the bit-partitioning approaches are susceptible to noise as small errors in the residues/partitions grow larger during output reconstruction. Thus, error correction methods are required for such designs. _So in our work, we provide a complete fault-tolerant dataflow that uses redundant RNS to detect and correct errors that are introduced by the noisy behavior of analog designs._

## III RNS-based Analog Core

### _RNS Basics_

The RNS represents an integer as a set of smaller integer residues. These residues are calculated by performing a modulo operation on the said integer using a selected set of \(n\)_co-prime_ moduli. Let \(A\) be an integer. \(A\) can be represented in the RNS with \(n\) residues as \(\{a_{1},\ldots,a_{n}\}\) for a set of moduli \(\mathcal{M}=\{m_{1},\ldots,m_{n}\}\) where \(a_{i}=|A|_{m_{i}}\equiv A\mod m_{i}\) for \(i\in\{1\ldots n\}\)1. \(A\) can be uniquely reconstructed using the Chinese Remainder Theorem (CRT):

Footnote 1: Hereinafter, we refer to the integer \(A\) as the _standard representation_, while we refer to the integers \(\{a_{1},\ldots,a_{n}\}\) simply as the residues.

\[A=\sum_{i=1}^{n}|a_{i}M_{i}T_{i}|_{M}, \tag{1}\]

if all the moduli are relatively prime and \(A\) is within the range \([0,M)\) where \(M=\prod_{i}m_{i}\). Here, \(M_{i}=M/m_{i}\) and \(T_{i}\) is the multiplicative

Fig. 2: Dataflow for the RNS-based analog GEMM operation for a moduli set \(m=\{m_{1},\ldots,m_{n}\}\). The \(n\)\(h\times h\) analog MVM units are represented as generic blocks. The MAC units can be resistive memory (RRAM) arrays, photonic GEMM cores, etc. The dataflow is agnostic to the technology.
inverse of \(M_{i}\), i.e., \(\left.\left|M_{i}T_{i}\right|_{m_{i}}\right.\equiv 1\). The RNS is closed under addition and multiplication operations, thus enabling dot products and GEMM operations in the RNS space.

### _DNN Inference Using RNS_

A DNN consists of a sequence of \(L\) layers. The input \(\vec{X}\) to the \(\ell\)-th layer of a DNN inference is the output generated by the previous \((\ell-1)\)-th layer:

\[\vec{X}_{k}^{(\ell)}=f^{(\ell-1)}\left(\sum_{j}W_{jk}^{(\ell-1)}\vec{X}_{j}^{ (\ell-1)}\right), \tag{2}\]

where \(W\cdot\vec{X}\) is an MVM and \(f(\cdot)\) is an element-wise nonlinear function.

In both digital and analog designs, the precision of MVM is limited by the precision of the inputs and weights, as well as the amount of information kept at the output. In digital accelerators that use low precision, when performing an MVM, costly multiplications are performed with low-precision datatypes (e.g., INT8) and accumulations are performed with high-precision datatypes (e.g., INT32/FP32), as accumulation is cheaper. The final result of the MVM can then be stored as a low-precision number. In contrast, in analog accelerators, the inputs and weights are both multiplied and accumulated with low-precision datatypes. This is because the fixed size of the analog compute array typically does not let the whole GEMM operation (a full DNN layer) be performed at once and each MVM produces a partial output vector which needs to be captured by the ADCs before being stored in a digital memory unit, i.e., SRAM or DRAM, and being accumulated with the rest of the partial output vectors. Here, the ADC precision directly determines how precisely we can capture these partial outputs. While using low-precision ADCs will lead to a higher information loss compared to digital hardware that can severely impact the accuracy of DNN, using a high-precision ADC is not feasible as it is power-hungry. However, this extra loss of information due to using low-precision ADCs can be eliminated by using RNS. Using RNS, Eq. (2) can be rewritten as:

\[\vec{X}_{k}^{(\ell)}=f^{(\ell-1)}\Bigg{(}\text{CRT}\bigg{(}\Big{|}\sum_{j} \big{|}W_{jk}^{(\ell-1)}\big{|}_{\mathcal{M}}\big{|}\vec{X}_{j}^{(\ell-1)} \big{|}_{\mathcal{M}}\Big{|}_{\mathcal{M}}\bigg{)}\Bigg{)}. \tag{3}\]

Here \(\mathcal{M}=\{m_{1},\ldots,m_{n}\}\) represents the set of moduli. The moduli must be chosen to ensure that the outputs of the MVM operations are smaller than \(M=\prod_{i}m_{i}\), which means we need

\[\log_{2}M\geq b_{\text{out}}=b_{\text{in}}+b_{w}+\log_{2}(h)-1, \tag{4}\]

for a dot-product between two vectors with \(h\)-elements. This constraint prevents overflow in the computation. Operations for different residues can be performed independently and in parallel without any carry propagation.

Fig. 2 shows the dataflow for the RNS-based analog hardware when performing MVM as part of the DNN inference. Here, \(\overrightarrow{X}_{\text{iIP}}\) represents a high-precision (e.g., FP32) \(h\times 1\) input vector and \(\overrightarrow{W}_{\text{iIP}}\) represents a high-precision \(h\times h\) weight matrix.2 The input vector and the weight matrix have to be mapped to integers to work with RNS. To reduce the quantization effects, we scale both inputs and weights before quantization. We scale \(\overrightarrow{X}_{\text{iIP}}\) by dividing each element of the vector by \(s_{\text{in}}=\text{max}(\big{|}\overrightarrow{X}_{\text{iIP}}\big{|})\). For the \(h\times h\) weight matrix, we scale each row separately. The scaling factors for the \(h\) rows form a vector \(\vec{s}_{w}=[s_{w}[\underline{1}],s_{w}[2],\ldots,s_{w}[h]]=[\text{max}(| \overrightarrow{W}_{\text{iIP}}[1]),\text{max}(|\overrightarrow{W}_{\text{iIP }}[2]|),\ldots,\text{max}(|\overrightarrow{W}_{\text{iIP}}[h]|)]\). In total, there are \(h+1\) floating-point scaling factors: \(h\) for the weight matrix and one for the input vector. These scaled elements are then quantized and mapped to (symmetric) signed integers between \([-2^{b-1}-1,2^{b-1}-1]\) with \(b=b_{\text{in}}\) and \(b=b_{w}\) to obtain the low-precision input vector (\(\overrightarrow{X}_{\text{iLP}}\)) and weight matrix (\(\overrightarrow{W}_{\text{iLP}}\)), respectively. We then perform the modulo operation on each element of the \(\overrightarrow{X}_{\text{iLP}}\) and \(\overrightarrow{W}_{\text{iLP}}\) with respect to each of the \(n\) moduli. This gives us \(n\) pairs of \(\overrightarrow{X}_{\text{iLP},i}\) and \(\overrightarrow{W}_{\text{iLP},i}\) containing the corresponding residues as its elements, where \(i\in\{1,\ldots,n\}\).

Footnote 2: For inputs and weights with dimensions larger than \(h\), one can use standard tilting methods.

In the RNS-based analog core, we have a dedicated analog MVM unit for each modulus. Each analog MVM unit has a set of DACs for converting the associated input vector and weight matrix into the analog domain. An analog MVM is performed (i.e., \(h\) dot products in parallel) between the input vector and the weight matrix, followed by a modulo operation on each output residue vector in the analog domain. Thanks to the modulo operation, the output residues are reduced back to \([0,m_{i})\) range. These output residues are captured

Fig. 3: Distribution of the error in the dot product performed with regular fixed-point analog core and RNS-based analog core. The error is the difference between the dot product calculated in FP32 (FP32 being the ground truth), and dot product calculated in fixed-point and RNS. Both fixed-point and RNS-based analog cores use the same input, weight, DAC, and ADC precision which varies from 4 to 8 in the plot. In the fixed-point core, only the 4-8 MSBs of the output are kept. The RNS-based core uses moduli within the same number of bits of range (see Table I). The results are shown for randomly generated 10,000 vector pairs for each case.
by ADCs. An ENOB of \(\lceil\log_{2}m_{i}\rceil\) (instead of the larger \(b_{\text{out}}\)-bits) is adequate for both DACs and ADCs to perform input and output conversions without any information loss.

The output residues are then converted back to the standard representation in the digital domain via CRT (Eq. (1)) to generate the signed integer output vector, i.e., \(\overrightarrow{Y}_{\text{SI}}\). The elements of the output vector are then scaled back up using the scaling factors calculated before the MVM operation, i.e., \(Y[k]=Y_{\text{SI}}[k]\cdot s_{\text{in}}\cdot s_{w}[k]\). The non-linear function \(f\) (e.g., ReLU, sigmoid, etc.) is performed digitally on the MVM output using floating-point datatypes (e.g., FP32).

### _Precision in the RNS-based Analog Core_

To obtain a desired output precision, we need to find a set of moduli that meets Eq. (4). The RNS range (\(M\)) depends on both the number of moduli (\(n\)) and the values of these moduli. The number of moduli determines the number of operations that we need to perform in the RNS-based core along with the required number of MVM units. Similarly, the bit width of these moduli determine the required precision of the data converters. Both of these in turn determine the efficiency of the RNS-based analog core and should be chosen carefully to find a balance between the energy efficiency and \(M\).

Table I shows the comparison of our RNS-based analog core with example moduli sets and a regular fixed-point analog core3. For the RNS-based core, we picked ADC and DAC precision to be the same as the precision of the input vector and the weight matrix, i.e., \(b=b_{\text{in}}=b_{w}=b_{\text{ADC}}=b_{\text{DAC}}=\lceil\log_{2}m_{i}\rceil\). The moduli sets shown in Table I are created by using the minimum number of moduli that guarantees Eq. (4) for \(h=128\) while keeping the moduli under the chosen bit width \(b\)4. In this case, for \(n\) moduli, \(M\) is \(\approx n\cdot b\) bits. It should be noted that the values of \(h\) and \(\mathcal{M}\) are representative values and our methods can be generalized for any \(h\) and \(\mathcal{M}\). In a regular fixed-point analog core, similar to the RNS-based core, we set \(b=b_{\text{in}}=b_{w}=b_{\text{DAC}}=b_{\text{ADC}}\). However, the bit-precision required to represent the output produced by the dot product (\(b_{\text{out}}\)) is much larger than \(b_{\text{ADC}}\). Therefore, \(b_{\text{out}}-b_{\text{ADC}}\) bits of information (from LSB and up) are lost after every MVM operation.

Footnote 3: Here both cores use fixed-point numbers to represent data. We use the term ‘regular fixed-point core’ for referring to a typical analog core that uses fixed-point numbers for computation and do not use RNS, whereas the RNS-based core uses integers as residues and performs computations in the RNS space.

Footnote 4: We choose \(h\) to be 128 considering the common layer sizes in the evaluated MLPerf benchmarks. The chosen \(h\) provides high throughput with a high utilization of the GEMM core.

Fig. 3 reports the absolute errors (FP32 being the ground truth) observed when performing dot-products (sub-operations in MVMs) with the RNS-based and fixed-point analog cores. Both cores use the configurations described in Table I for the example vector size \(h=128\). In the regular fixed-point core, information loss due to the dropped bits causes a 9-15\(\times\) larger error compared to the RNS-based dot product with the same input and weight bit precision.

We next compare the performance of an RNS-based analog core against a fixed-point analog core for different MLPerf benchmarks as shown in Fig. 4. We report accuracy normalized to the accuracy of a FP32 hardware. Our results show that the RNS approach significantly ameliorates the accuracy drop caused by the low-precision ADCs in the fixed-point analog core for all the benchmark networks. We observe that it is possible to achieve \(\geq\)99\(\%\) of FP32 accuracy (this cut-off is defined in the MLPerf benchmark [23]) for all MLPerf networks when using residues with as low as \(6\) bits.

## IV Redundant RNS for Fault Tolerance

Any analog compute core is sensitive to noise. Furthermore, in the case of RNS, even small errors in the residues result in a large error in the corresponding integer the residues represent. We use the Redundant Residue Number System (RRNS) [29] to perform error detection and correction to improve the fault tolerance of the RNS-based analog core. RRNS uses a total of \(n\) moduli: \(k\) non-redundant and \(n-k\) redundant. An RRNS(\(n,k\)) code can detect up to \(n-k+1\) errors and can correct up to \(\lfloor\frac{n-k}{2}\rfloor\) errors. In particular, the error in the codeword (i.e., the \(n\) residues representing an integer in the RRNS space) can be one of the following cases:

* **Case 1:** No error or correctable error (fewer than \(\lfloor\frac{n-k}{2}\rfloor\) residues have errors),
* **Case 2:** Detectable but not correctable error (more than \(\lfloor\frac{n-k}{2}\rfloor\) residues have errors, and the erroneous codeword does not overlap with another codeword in the RRNS space),
* **Case 3:** Undetectable error (more than \(n-k+1\) residues have errors, the erroneous codeword overlaps with another codeword in the RRNS space).

By using RRNS, errors can be detected by using a voting mechanism wherein we divide the total \(n\) output residues into \(C_{k}^{n}\) groups with \(k\) residues per group. One simple way of voting is to convert the residues in each group back to the standard representation via CRT to generate an output vector for each group5. Then, we compare the results of the \(C_{k}^{n}\) groups. If more than \(50\%\) of the groups have same result in the standard representation, then the generated codeword is correct. This corresponds to **Case 1**. In contrast, not having a majority indicates that the generated codeword is erroneous and cannot be corrected. This corresponds to **Case 2**. In this case, the detected errors

Fig. 4: Accuracy of regular fixed-point and RNS-based cores on MLPerf datacenter benchmarks. The accuracy numbers are normalized to the FP32 accuracy. Both \(b\)-bit fixed-point cores and \(b\)-bit RNS-based cores use \(b\)-bit input and weight DACs and \(b\)-bit output ADCs. The RNS-based cores use \(b\)-bit moduli to represent numbers (see Table I). All experiments use FP32 as the intermediate datatype for non-GEMM operations.
can be eliminated by repeating the dot product and voting steps, and recalculating the result. In **Case 3**, there are more than \(n-k+1\) erroneous residues and the erroneous codeword generated by majority of the groups overlaps with another codeword. As a result, the voting mechanism incorrectly determines that the generated codeword is the correct codeword, i.e., the errors in the residues go undetected.

To understand this better, for a single codeword and a single attempt, assume \(p_{c}\) is the probability that there are no errors or the errors are correctable (**Case 1**), \(p_{d}\) is the probability that errors are detectable but not correctable (**Case 2**), and \(p_{u}\) is the probability that the errors are undetectable (**Case 3**). In this case, \(p_{c}+p_{d}+p_{u}=1\). The error probabilities \(p_{c},p_{d}\) and \(p_{u}\) for a probability of error in a single residue \((p)\) can be computed using equations formulated by James et al. [24] and Peng et al. [29].6 For \(R\) repeated attempts of performing a dot product to correct the error, the probability of having an erroneous output codeword (\(p_{\text{err}}\)) is

Footnote 6: The detailed equations not shown in this paper due to space constraints.

\[p_{\text{err}}(R)=1-p_{c}\sum_{k=1}^{R}(p_{d})^{k}. \tag{5}\]

As we increase the number of attempts, the output error probability decreases and converges to: \(\lim_{R\rightarrow\infty}p_{\text{err}}(R)=p_{u}/(p_{u}+p_{c})\).

The values of \(p_{\text{err}}\) for different numbers of redundant moduli \((n-k)\), numbers of attempts \((R)\), and moduli sets (with different number of bits) are plotted in Fig. 5. Broadly, as the probability of a single residue error \(p\) increases, the output error probability tends to \(1\). For a given number of attempts, increasing bit-precision and the number of redundant moduli decreases \(p_{\text{err}}\). For a fixed number of redundant moduli and a fixed number of bits per moduli, \(p_{\text{err}}\) decreases as the number of attempts increases.

We investigated the impact of the noise on the accuracy of the MLPerf benchmarks when using RRNS. We observe similar behavior in different networks, thus we only show the accuracy results for ResNet50 and BERT-large in Figure 6. Broadly, adding extra moduli and increasing the number of attempts decrease \(p_{\text{err}}\) and help maintain the accuracy for higher \(p\) values.

ResNet50 requires \(\sim\)\(3.9\) GigaMAC operations (GOp) for one inference on a single input image. For a \(128\times 128\) MVM unit, the total number of MVM outputs is \(\sim\)\(29.4\)M. For all output values to be correct, \(p_{\text{err}}\leq 1/29.4\)M = \(3.4\times 10^{-8}\). This \(p_{\text{err}}\) value needs to be \(\leq 1/358.6\)M = \(2.8\times 10^{-9}\) for BERT-large. However, from Fig. 6, we observe that the DNNs are resilient to noise and the tolerable \(p_{\text{err}}\) is much higher than the calculated numbers. The accuracy of ResNet50 only starts degrading (below \(99\%\) FP32) when \(p_{\text{err}}\approx 4.9\times 10^{-5}\) (\(\sim\)\(10^{3}\times\) higher than the estimated value) on average amongst the experiments shown in Figure 6. This cut-off probability is \(p_{\text{err}}\)\(\approx\)\(4\times 10^{-4}\) for BERT-large (on average \(\sim\)\(10^{5}\times\) higher than the estimated value).

Fig. 5: Output error probability (\(p_{\text{err}}\)) for varying number of error correction attempts and number of redundant moduli \((n-k)\) used

Fig. 6: ResNet-50 (top row) and BERT-large (bottom row) accuracy for varying number of attempts and number of redundant moduli used.
## V Energy Efficiency of RNS-Based Core

In this section, we show that an RNS-based analog core is more energy efficient than their fixed-point counterparts _for the same precision_. High-precision data converters--particularly ADCs--dominate the power consumption in analog DNN accelerators [17, 18]. Our RNS approach alleviates this high power consumption of ADCs without compromising accuracy. To quantify our findings, we estimate the energy consumption of a DAC per conversion as:

\[E_{\text{DAC}}=\text{ENOB}^{2}C_{u}V_{\text{DD}}^{2}, \tag{6}\]

where \(C_{u}=0.5\) fF is a typical unit capacitance and \(V_{\text{DD}}\) = 1V is the supply voltage [19]. The energy consumption of an ADC per conversion is estimated as:

\[E_{\text{ADC}}=k_{1}\text{ENOB}+k_{2}4^{\text{ENOB}}, \tag{7}\]

where \(k_{1}{\approx}100\) fJ and \(k_{2}{\approx}1\) aJ [19, 31]. The exponential term (i.e., \(k_{2}4^{\text{ENOB}}\)) dominates at large ENOB (after \({\sim}10\)-bits).

Fig. 7 shows total \(E_{\text{DAC}}\) and \(E_{\text{ADC}}\) for both the RNS-based and the regular fixed-point analog hardware configurations that were shown previously in Table I. Here, different from Table I, \(b_{\text{ADC}}=b_{\text{out}}\) for the regular fixed-point core to achieve the same precision as the RNS approach. To achieve the same MVM throughput in both cores, the RNS-based core with \(n\) moduli must use \(n\) MVM units--leading to \(n\) DACs and \(n\) ADCs. From Figure 7, we observe that ADCs have approximately three orders of magnitude higher energy-consumption compared to DACs with the same ENOB. Energy of an ADC is exponentially dependent on ENOB, and so even with \(n\) ADCs in the RNS-based core, its energy consumption is still \(168{\times}\) to \(6.8\)M\({\times}\) lower than the regular fixed-point core.

Moreover, besides data converters, RNS reduces the required signal-to-noise ratio (SNR) in the analog MVM units. The energy consumption of the analog MVM unit depends on the SNR for the analog signals, and this SNR increases exponentially with the desired compute precision. Thus, RNS brings additional savings by allowing the MVM units to work with lower SNR in the analog domain.

In the case of using RRNS, the number of DACs, ADCs, and analog MVM units will increase linearly with each added redundant moduli. Although this increases \(n\) and the energy consumption of data converters linearly, considering the high energy efficiency gains (up to six orders of magnitude) over the fixed-point cores, this extra cost for extra moduli is tolerable. Here, the number of redundant moduli and number of attempts required to achieve fault-tolerant computing is dependent on the the noise distribution in the chosen technology and the DNN model.

Different from the regular fixed-point hardware, the use of RNS requires forward and reverse conversion between the RNS and the standard representation, and modulo operation in the analog domain. The forward conversion is simply a modulo operation whereas reverse conversion is performed via CRT (See Eq. (1)). We synthesized the RTL design of these conversion circuits using ASAP 7nm technology library [32]. The modulo operations are optimized using Barrett Reduction [33]. These converters consume up to \({\leq}0.1\) pJ per conversion (forward and reverse in total), which is negligible. Analog modulo can be performed in different ways depending on the analog technology used. One can use ring oscillators [34] to perform modulo operation electrically. This approach uses an odd number of \(m\) inverters to oscillate the signal. The location of the falling/rising signal winds back after each \(m\) cycles as the signal oscillates. By keeping track of the start and the end location of the signal between a specific time interval proportional to the value \(x\), the modulo operation of \(x\) against \(m\) can be obtained. As a set of inverters is a trivial circuitry, the ring oscillator does not add much to the energy consumption. Alternatively, one can perform modulo optically by using the phase in the optical domain. Addition with phases is effectively a modular addition against \(2\pi\) as the phase values wind back at every \(2\pi\). The phase of a signal at the output of a row of \(h\) phase shifters will be \(|\Sigma_{h=0}^{h}\phi_{l}|_{2\pi}\). Multiplying the values with \(2\pi/m\) before the modular addition enables one to perform modulo against arbitrary \(m\) instead of only \(2\pi\). Modulo operation can thus be performed along with accumulation without any additional cost.

## VI Conclusion

In this paper, we present a generic dataflow framework for an RNS-based analog accelerator that is agnostic of the analog technology. We show that an RNS-based analog core provides \(99\%\) FP32 accuracy for state-of-the-art DNNs by using 6-bit arithmetic with RNS. We provide an error detection and correction method using RRNS that improves the fault-tolerance of the analog core against noise. We also show that our RNS-based analog hardware can reduce the data conversion energy by multiple orders of magnitude compared to a fixed-point analog hardware at the same precision. While we provide a generic perspective, for a desired analog technology, one can explore the various trade-offs discussed in this paper to optimize the accelerator micro-architecture for further energy efficiency. Overall, we believe that RNS is a promising numeral system for the development of the next-generation energy-efficient fault-tolerant analog accelerators.
