PASNet: Polynomial Architecture Search Framework for Two-party
  Computation-based Secure Neural Network Deployment
Two-party computation (2PC) is promising to enable privacy-preserving deep
learning (DL). However, the 2PC-based privacy-preserving DL implementation
comes with high comparison protocol overhead from the non-linear operators.
This work presents PASNet, a novel systematic framework that enables low
latency, high energy efficiency & accuracy, and security-guaranteed 2PC-DL by
integrating the hardware latency of the cryptographic building block into the
neural architecture search loss function. We develop a cryptographic hardware
scheduler and the corresponding performance model for Field Programmable Gate
Arrays (FPGA) as a case study. The experimental results demonstrate that our
light-weighted model PASNet-A and heavily-weighted model PASNet-B achieve 63 ms
and 228 ms latency on private inference on ImageNet, which are 147 and 40 times
faster than the SOTA CryptGPU system, and achieve 70.54% & 78.79% accuracy and
more than 1000 times higher energy efficiency.
Hongwu Peng, Shanglin Zhou, Yukui Luo, Nuo Xu, Shijin Duan, Ran Ran, Jiahui Zhao, Chenghong Wang, Tong Geng, Wujie Wen, Xiaolin Xu, Caiwen Ding
PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment

###### Abstract

Two-party computation (2PC) is promising to enable privacy-preserving deep learning (DL). However, the 2PC-based privacy-preserving DL implementation comes with high comparison protocol overhead from the non-linear operators. This work presents PASNet, a novel systematic framework that enables low latency, high energy efficiency & accuracy, and security-guaranteed 2PC-DL by integrating the hardware latency of the cryptographic building block into the neural architecture search loss function. We develop a cryptographic hardware scheduler and the corresponding performance model for Field Programmable Gate Arrays (FPGA) as a case study. The experimental results demonstrate that our light-weighted model PASNet-A and heavily-weighted model PASNet-B achieve 63 ms and 228 ms latency on private inference on ImageNet, which are 147 and 40 times faster than the SOTA CryptGPU system, and achieve 70.54% & 78.79% accuracy and more than 1000 times higher energy efficiency. The pretrained PASNet models and test code can be found on Github1.

Footnote 1: [https://github.com/HarveyP123/PASNet-DAC2023](https://github.com/HarveyP123/PASNet-DAC2023)

 Privacy-Preserving in Machine Learning, Multi Party Computation, Neural Architecture Search, Polynomial Activation Function, Software/Hardware Co-design, FPGA

## I Introduction

Machine-Learning-As-A-Service (MLaaS) has been an emerging solution nowadays, to provide accelerated inference for diverse applications. However, most MLaaS require clients to reveal the raw input to the service provider [1] for evaluation, which may leak the privacy of users. Privacy-preserving deep learning (PPDL) and private inference (PI) have emerged to protect sensitive data in deep learning (DL). The current popular techniques include multi-party computation (MPC) [2] and homomorphic encryption (HE) [3]. HE is mainly used to protect small to medium-scale DNN models without involving costly bootstrapping and large communication overhead. MPC protocols such as secret-sharing [2] and Yao's Garbled Circuits (GC) [4] can support large-scale networks by evaluating operator blocks. This work mainly focuses on secure two-party computation (2PC), which represents the minimized system for multi-party computing (MPC) and is easy to extend [5].

The primary challenge in 2PC-based PI is the comparison protocol overhead [6] for non-linear operators. As shown in Fig. 1, ReLU contributes over 99% of latency in a ciphertext setting for deep neural network (DNN), despite negligible overhead in plaintext. Replacing ReLU with second-order polynomial activation could yield 50\(\times\) speedup.

To achieve high performance, good scalability, and high energy efficiency for _secure_ deep learning systems, two orthogonal research directions have attracted enormous interest. The first one is the nonlinear operations overhead reduction algorithms. Existing works focus on _ReLU cost optimization_, e.g., minimizing ReLU counts (DeepReduce [7], CryptoNAS [8]) or replacing ReLUs with polynomials (CryptoNets [9], Delphi [10], SAFENT [11]), and _extremely low-bit_ weights and activations (e.g., Binary Neural Network (BNN) [12]). However, these works neglect the accuracy impact. They often sacrifice the model comprehension capability, resulting in several accuracy losses on large networks and datasets such as ImageNet, hence are not scalable. The second trend is _hardware acceleration for PI_ to speed up the MPC-based DNN through GPUs [2, 13]. Since no hardware characteristic is captured during DNN design, this top-down ("algorithm \(\rightarrow\) hardware") approach can not effectively perform design space

Fig. 1: Latency of operators under 2PC PI setup. Network bandwidth: 1 GB/s. Device: ZCU104. Dataset: ImageNet.
exploration, resulting in sub-optimal solutions.

We focus on three observations: 1) preserving **prediction accuracy** for substantial benefits; 2) scalable **cryptographic overhead reduction** for various network sizes; 3) cohesive **algorithm/hardware optimizations** using closed loop "algorithm \(\leftrightarrow\) hardware" with design space exploration capturing hardware characteristics.

We introduce the **Polynomial Architecture Search (PASNet)** framework, which jointly optimizes DNN model structure and hardware architecture for high-performance MPC-based PI. Considering cryptographic DNN operators, data exchange, and factors like encoding format, network speed, hardware architecture, and DNN structure, PASNet effectively enhances the performance of MPC-based PI.

Our key design principle is to _enforce_ exactly what is assumed in the DNN design--training a DNN that is both hardware efficient and secure while maintaining high accuracy.

To evaluate the effectiveness of our framework, we use FPGA accelerator design as a demonstration due to its predictable performance, low latency, and high energy efficiency for MLaaS applications (e.g., Microsoft Azure [14]). We summarize our contributions as follows:

1. We propose a trainable _straight through polynomial activation initialization_ method for cryptographic hardware-friendly trainable polynomial activation function to replace the expensive ReLU operators.
2. Cryptographic hardware scheduler and the corresponding performance model are developed for the FPGA platform. The latency loop-up table is constructed.
3. We propose a differentiable cryptographic hardware-aware NAS framework to selectively choose the proper polynomial or non-polynomial activation based on given constraint and latency of cryptographic operators.

## II **Basic of Cryptographic Operators**

### **Secret Sharing**

**2PC setup.** We consider a similar scheme involving two semi-honest in a MLaaS applications [5], where two servers receive the confidential inputs from each other and invoke a two party computing protocol for secure evaluation.

**Additive Secret Sharing.** In this work, we evaluate 2PC secret sharing. As a symbolic representation, for a secret value \(x\in\mathbb{Z}_{m}\), \(\llbracket x\rrbracket\leftarrow(x_{S_{0}},x_{S_{1}})\) denotes the two shares, where \(x_{S_{i}},i\in\{0,1\}\) belong to server \(S_{i}\). Other notations are as below:

* _Share Generation_\(\text{shr}(x)\): A random value \(r\) in \(\mathbb{Z}_{m}\) is sampled, and shares are generated as \(\llbracket x\rrbracket\leftarrow(r,x-r)\).
* _Share Recovering_\(\text{rec}(\llbracket x\rrbracket)\): Given shares \(\llbracket x\rrbracket\leftarrow(x_{S_{0}},x_{S_{1}})\), it computes \(x\gets x_{S_{0}}+x_{S_{1}}\) to recover \(x\).

An example of plaintext vs. secret shared based ciphertext evaluation is given in Fig. 2, where ring size is 4 and \(\mathbb{Z}_{m}=\{-8,-7,...7\}\). The integer overflow mechanism naturally ensures the correctness of ciphertext evaluation. Evaluation in the example involves secure multiplication, addition and comparison, and details are given in following sections.

### **Polynomial Operators Over Secret-Shared Data**

**Scaling and Addition.** We denote secret shared matrices as \(\llbracket X\rrbracket\) and \(\llbracket Y\rrbracket\). The encrypted evaluation is given in Eq. 1.

\[\llbracket aX+Y\rrbracket\leftarrow(aX_{S_{0}}+Y_{S_{0}},aX_{S_{1}}+Y_{S_{1}}) \tag{1}\]

**Multiplication.** We consider the matrix multiplicative operations \(\llbracket R\rrbracket\leftarrow\llbracket X\rrbracket\otimes\llbracket Y\rrbracket\) in the secret-sharing pattern. where \(\otimes\) is a general multiplication, such as Hadamard product, matrix multiplication, and convolution. We use oblivious transfer (OT) [15] based approach. To make the multiplicative computation secure, an extra Beaver triples [16] should be generated as \(\llbracket Z\rrbracket=\llbracket A\rrbracket\otimes\llbracket B\rrbracket\), where \(A\) and \(B\) are randomly initialized. Specifically, their secret shares are denoted as \(\llbracket Z\rrbracket=(Z_{S_{0}},Z_{S_{1}})\), \(\llbracket A\rrbracket=(A_{S_{0}},A_{S_{1}})\), and \(\llbracket B\rrbracket=(B_{S_{0}},B_{S_{1}})\). Later, two matrices are derived from given shares: \(E_{S_{i}}=X_{S_{i}}-A_{S_{i}}\) and \(F_{S_{i}}=Y_{S_{i}}-B_{S_{i}}\), in each party end separately. The intermediate shares are jointly recovered as \(E\leftarrow\text{rec}(\llbracket E\rrbracket)\) and \(F\leftarrow\text{rec}(\llbracket F\rrbracket)\). Finally, each party, i.e, server \(S_{i}\), will calculate the secret-shared \(R_{S_{i}}\) locally:

\[R_{S_{i}}=-i\cdot E\otimes F+X_{S_{i}}\otimes F+E\otimes Y_{S_{i}}+Z_{S_{i}} \tag{2}\]

**Square.** For the element-wise square operator shown \(\llbracket R\rrbracket\leftarrow\llbracket X\rrbracket\otimes \llbracket X\rrbracket\), we need to generate a Beaver pair \(\llbracket Z\rrbracket\) and \(\llbracket A\rrbracket\) where \(\llbracket Z\rrbracket=\llbracket A\rrbracket\otimes\llbracket A\rrbracket\), and \(\llbracket A\rrbracket\) is randomly initialized. Then parties evaluate \(\llbracket E\rrbracket=\llbracket X\rrbracket-\llbracket A\rrbracket\) and jointly recover \(E\leftarrow\text{rec}(\llbracket E\rrbracket)\). The result \(R\) can be obtained through Eq. 3.

\[R_{S_{i}}=Z_{S_{i}}+2E\otimes A_{S_{i}}+E\otimes E \tag{3}\]

### **Non-Polynomial Operator Modules**

Non-polynomial operators such as ReLU and MaxPool are evaluated using secure comparison protocol.

**Secure 2PC Comparison.** The 2PC comparison, a.k.a. millionaires protocol, is committed to determine whose value held by two parties is larger, without disclosing the exact value to each other. We adopt work [6] for 2PC comparison. Detailed modeling is given in Section III-C.

Fig. 2: A example of 4 bit plaintext vs. ciphertext evaluation.
## III **The PASNet Framework**

The framework (Fig. 3) takes inputs like optimization target, hardware pool, network information, and 2PC operator candidates for cryptographic operator modeling, benchmarking, and automated design space optimization in PI using hardware-aware NAS. This section presents a new cryptographic-friendly activation function, its initialization method, DNN operator modeling under 2PC, and a hardware-aware NAS framework for optimizing DNN accuracy and latency. While evaluated on FPGA accelerators, the method can be easily adapted to other platforms like mobile and cloud.

### **Trainable \(X^{2}act\) Non-linear Function.**

We use a hardware friendly trainable second order polynomial activation function as an non-linear function candidate, shown in Eq. 4, where \(w_{1}\), \(w_{2}\) and \(b\) are all trainable parameters. We propose _straight through polynomial activation initialization_ (**STPAI**) method to set the \(w_{1}\) and \(b\) to be small enough and \(w_{2}\) to be near to 1 in Eq. 4 for initialization.

\[\delta(x)=\frac{c}{\sqrt{N_{x}}}w_{1}x^{2}+w_{2}x+b \tag{4}\]

**Convergence.** Layer-wise second-order polynomial activation functions preserve the convexity of single-layer neural network [17]. Higher order polynomial activation function or channel-wise fine-grained polynomial replacement proposed in SAFENet [11] may destroy the neural network's convexity and lead to a deteriorated performance.

**Learning rate.** The gradient of \(w_{1}\) must be balanced to match the update speed of other model weights. As such, we add a new scaling \(\frac{c}{\sqrt{N_{x}}}\) prior to \(w_{1}\) parameter. In the function, \(c\) is a constant, \(N_{x}\) is the number of elements in feature map.

### **Search Space of Hardware-aware NAS.**

We focus on convolutional neural networks (CNNs) in our study. CNNs are mostly composed of Conv-Act-Pool and Conv-Act blocks. In work, we use the regular backbone model as a search baseline, such as the VGG family, mobilenetV3, and ResNet family. Each layer of supernet is composed of the layer structure obtained from baseline and its possible combination with \(X^{2}act\) and \(Pool_{a}\) replacement. A toy example is shown in Fig. 3, where a two-layer supernet is constructed, and the first layer is Conv-Act-Pool, and the second layer is Conv-Act. The first layer has four combinations which are Conv-ReLU-Pool\({}_{\text{m}}\), Conv-ReLU-Pool\({}_{\text{a}}\), Conv-\(X^{2}act\)-Pool\({}_{\text{m}}\), and Conv-\(X^{2}act\)-Pool\({}_{\text{a}}\). The second layer has two combinations: Conv-ReLU and Conv-\(X^{2}act\). The Conv block's parameters can be either shared among candidates or separately trained during the search.

### **Operator Modeling and Latency Analysis**

This section will analyze five different operators: 2PC-ReLU, 2PC-\(X^{2}act\), 2PC-MaxPool, 2PC-AvgPool, and 2PC-Conv. Therefore, they require \((1,n)\)-OT (noted as **OT flow** block to implement 2PC comparison flows. Batch normalization can be fused into the convolution layer and it's not listed.

#### Iii-C1 2PC-OT Processing Flow.

While OT-based comparison protocol has been discussed in [15], we hereby provide other communication detail as shown in Fig. 4. Assume both servers have a shared prime number \(m\), one generator (\(g\)) selected from the finite space \(\mathbb{Z}_{m}\), and an **index** list with \(L\) length. As we adopt 2-bit part, the length of **index** list is \(L=4\).

**1 Server 0** (\(S_{0}\)) generates a random integer \(rd_{s_{0}}\), and compute mask number \(S\) with \(S=g^{rd_{S_{0}}}\ mod\ m\), then shares

Fig. 4: Processing Steps of **2PC-OT** flow.

Fig. 3: Overview of PASNet framework for 2PC DNN based private inference setup.
\(S\) with the Server 1 (\(S_{1}\)). We only need to consider communication (\(COMM_{1}\)) latency as \(COMM_{1}=T_{bc}+\frac{32}{Rtb_{bw}}\), since computation (\(CMP_{1}\)) latency is trivial.

**2 Server 1** (\(S_{1}\)) received \(S\), and generates \(\mathbf{R}\) list based on \(S_{1}\)'s 32-bit dataset \(\mathbf{M_{1}}\), and then send them to \(S_{0}\). Each element of \(\mathbf{M_{1}}\) is split into \(U=16\) parts, thus each part is with 2 bits. Assuming the input feature is square with size \(FI\) and \(IC\) denotes the input channel, and we denote the computational parallelism as \(PP\). The \(CMP_{2}\) is modeled as Eq. 5, and \(COMM_{2}\) is modeled as Eq. 6.

\[CMP_{2}=\frac{32\times 17\times FI^{2}\times IC}{PP\times freq} \tag{5}\]

\[COMM_{2}=T_{bc}+\frac{32\times 16\times FI^{2}\times IC}{Rtb_{bw}} \tag{6}\]

**3 Server 0** (\(S_{0}\)) received \(\mathbf{R}\), it will first generate the encryption \(\mathbf{key_{0}}(y,u)=\mathbf{R}(y,u)\oplus(S^{b2d(\mathbf{M_{1}}(y,u))+1}\ mod\ m)^{rd_{S_{0}}}\ mod\ m\). The \(S_{0}\) also generates is comparison matrix for it's \(\mathbf{M_{0}}\) with 32-bit datatype and \(U=16\) parts, thus the matrix size for each value (\(x\)) is \(4\times 16\). The encrypted \(Enc(\mathbf{M_{0}}(x,u))=\mathbf{M_{0}}(x,u)\oplus\mathbf{key_{0}}(y,u)\) will be sent to \(S_{1}\). The \(COMM_{3}\) of this step is shown in Eq. 8, and \(CMP_{3}\) can be estimated as Eq. 7.

\[CMP_{3}=\frac{32\times(17+(4\times 16))\times FI^{2}\times IC}{PP\times freq} \tag{7}\]

\[COMM_{3}=T_{bc}+\frac{32\times 4\times 16\times FI^{2}\times IC}{Rtb_{bw}} \tag{8}\]

**4 Server 1** (\(S_{1}\)) decodes the interested encrypted massage by \(\mathbf{key_{1}}=S^{rd_{S_{0}}}\ mod\ m\) in the final step. The \(CMP_{4}\) and \(COMM_{4}\) are calculated as following:

\[CMP_{4}=\frac{((32\times 4\times 16)+1)\times FI^{2}\times IC}{PP\times freq} \tag{9}\]

\[COMM_{4}=T_{bc}+\frac{FI^{2}\times IC}{Rtb_{bw}} \tag{10}\]

#### Iii-C2 2PC-ReLU Operator

2PC-ReLU requires 2PC-OT flow. 2PC-ReLU latency (\(Lat_{2PC-ReLU}\)) model is given in Eq. 11.

\[Lat_{2PC-ReLU}=\sum_{i=2}^{4}{CMP_{i}}+\sum_{j=1}^{4}{COMM_{j}} \tag{11}\]

#### Iii-C3 2PC-MaxPool Operator

Original MaxPool function is shown in Eq. 12. The 2PC-MaxPool uses OT flow comparison, and the latency model is shown in Eq. 13.

\[out=\max_{\begin{subarray}{c}k_{h}\in[0,K_{h}-1]\\ k_{w}\in[0,K_{w}-1]\end{subarray}}in(n,c,hS_{h}+k_{h},wS_{w}+k_{w}) \tag{12}\]

\[Lat_{2PC-MaxPool}=\sum_{i=2}^{4}{CMP_{i}}+\sum_{j=1}^{4}{COMM_{j}}+3T_{bc} \tag{13}\]

#### Iii-C4 2PC-\(X^{2}\)act Operator

The original \(X^{2}act\) has been shown in Eq. 4. The \(X^{2}act\) needs a ciphertext square operation and 2 ciphertext-plaintext multiplication operations. The basic protocol is demonstrated in Sec. II-B. The latency of computation and communication can be modeled as: \(CMP_{x^{2}}=\frac{2\times FI^{2}\times IC}{PP\times freq}\) and \(COMM_{x^{2}}=T_{bc}+\frac{32\times FI^{2}\times IC}{R_{hw}}\). The latency model of 2PC-\(X^{2}\)act (\(Lat_{2PC-X^{2}act}\)) is shown in Eq. 14.

\[Lat_{2PC-X^{2}act}=CMP_{x^{2}}+2\times COMM_{x^{2}} \tag{14}\]

#### Iii-C5 2PC-AvgPool Operator

The 2PC-AvgPool operator only involves addition and scaling, the latency is

\[Lat_{2PC-AvgPool}=\frac{2\times FI^{2}\times IC}{PP\times freq} \tag{15}\]

#### Iii-C6 2PC-Conv Operator

The 2PC-Conv operator involves multiplication between ciphertext, and the basic computation and communication pattern are given Sec. II-B. The computation part follows tiled architecture implementation [18]. Assuming we can meet the computation roof by adjusting tiling parameters, the latency of the 2PC-Conv computation part can be estimated as \(CMP_{Conv}=\frac{3\times K\times K\times FC^{2}\times IC\times OC}{PP\times freq}\), where \(K\) is the convolution kernel size. The communication latency is modeled as \(COMM_{Conv}=T_{bc}+\frac{32\times FI^{2}\times IC}{Rt_{bw}}\). Thus, the latency of 2PC-Conv is given in Eq. 16.

\[Lat_{2PC-Conv}=CMP_{Conv}+2\times COMM_{Conv} \tag{16}\]

### **Differentiable Harware Aware NAS Algorithm**

```
0:\(M_{b}\): backbone model; \(D\): a specific dataset \(Lat(OP)\): latency loop up table; \(H\): hardware resource
0: Searched polynomial model \(M_{p}\)
1:while not converged do
2: Sample minibatch \(x_{trn}\) and \(x_{val}\) from trn. and val. dataset
3: // Update architecture parameter \(\alpha\):
4: Forward path to compute \(\zeta_{trn}(\omega,\alpha)\) based on \(x_{trn}\)
5: Backward path to compute \(\delta\omega=\frac{\delta\zeta_{trn}(\omega,\alpha)}{\delta\omega}\)
6: Virtual step to compute \(\omega^{\prime}=\omega-\xi\delta\omega\)
7: Forward path to compute \(\zeta_{val}(\omega^{\prime},\alpha)\) based on \(x_{val}\)
8: Backward path to compute \(\delta\alpha^{\prime}=\frac{\partial_{\zeta_{val}}(\omega^{\prime},\alpha)}{ \partial\alpha^{\prime}}\)
9: Backward path to compute \(\delta\omega^{\prime}=\frac{\partial_{\zeta_{val}}(\omega^{\prime},\alpha)}{ \partial\omega^{\prime}}\)
10: Virtual steps to compute \(\omega^{\pm}=\omega\pm\delta\omega^{\prime}\)
11: Two forward path to compute \(\zeta_{trn}(\omega^{\prime},\alpha)\)
12: Two backward path to compute \(\delta\alpha^{\pm}=\frac{\partial_{\zeta_{trn}}(\omega^{\pm},\alpha)}{ \partial\alpha}\)
13: Compute hessian \(\delta\alpha^{\prime\prime}=\frac{\delta\alpha^{\prime}-\delta\alpha}{2\alpha}\)
14: Compute final architecture parameter gradient \(\delta\alpha=\delta\alpha^{\prime}-\xi\delta\alpha^{\prime\prime}\)
15: Update architecture parameter using \(\delta\alpha\) with Adam optimizer
16: // Update weight parameter \(\omega\):
17: Forward path to compute \(\zeta_{trn}(\omega,\alpha)\) based on \(x_{trn}\)
18: Backward path to compute \(\delta\omega=\frac{\partial_{\zeta_{trn}}(\omega,\alpha)}{\partial\omega}\)
19: Update architecture parameter using \(\delta\omega\) with SGD optimizer
20: **end while**

Obtain architecture by \(OP_{l}(x)=OP_{l,k^{*}}(x)\), \(s.t.\ k^{*}=\text{argmax}_{k}\ \theta_{l,k}\)
```

**Algorithm 1** Differentiable Polynomial Architecture Search.
Early work [19] focus on using RL for NAS. The RL based method effectively explores the search space but still requires a significant amount of search overhead such as GPU hours and energy. Hardware-aware NAS have also been investigated [20]. In this work, we incorporate latency constraint into the target loss function of the DARTS framework [21], and develop a differentiable cryptographic hardware-aware micro-architecture search framework. We firstly determine a supernet model for NAS, and introduces gated operators \(OP_{l}(x)\) which parametrizes the candidate operators \(OP_{l,j}(x)\) selection with a trainable weight \(\alpha_{l,k}\) (Eq. 17). For example, a gated pooling operator consists of MaxPool and AvgPool operators and 2 trainable parameters for pooling selection. The latency of the operators could be determined based on Sec. III-C. A parameterized latency constraint is given as \(Lat(\alpha)=\sum_{l=1}^{n}\sum_{j=1}^{m}\theta_{l,j}Lat(OP_{l,j})\), where the latency of gated operators are weighted by \(\theta_{l,j}\). We incorporate the latency constraint into the loss function as \(\zeta(\omega,\alpha)=\zeta_{CE}(\omega,\alpha)+\lambda Lat(\alpha)\), and penalize the latency \(Lat(\alpha)\) by \(\lambda\).

\[\theta_{l,j}=\frac{\exp(\alpha_{l,j})}{\sum_{k=1}^{m}\exp(\alpha_{l,k})},\;OP _{l}(x)=\sum_{k=1}^{m}\theta_{l,k}OP_{l,k}(x) \tag{17}\]

The optimization objective of our design is shown in Eq. 18, we aim to minimize the validation loss \(\zeta_{val}(\omega^{*},\alpha)\) with regard to architecture parameter \(\alpha\). The optimal weight \(\omega^{*}\) is obtained through minimize the training loss. The second order approximation of the optimal weight is given as \(\omega^{*}\approx\omega^{\prime}=\omega-\xi\;\delta\zeta_{trn}(\omega,\alpha)/ \delta\omega\), the approximation is based on current weight parameter and its' gradient. The virtual learning rate \(\xi\) can be set equal to that of weight optimizer.

\[\text{argmin}_{\alpha}\;\zeta_{val}(\omega^{*},\alpha),\;s.t.\;\omega^{*}= \text{argmin}_{\omega}\;\zeta_{trn}(\omega,\alpha) \tag{18}\]

Eq. 19 gives the approximate \(\alpha\) gradient using chain rule, the second term of \(\alpha\) gradient can be further approximated using small turbulence \(\varepsilon\), where weights are \(\omega^{\pm}=\omega\pm\delta\zeta_{val}(\omega^{\prime},\alpha)/\delta\omega^{\prime}\) and Eq. 20 is used for final \(\alpha\) gradient.

\[\delta\zeta_{val}(\omega^{\prime},\alpha)/\delta\alpha-\xi\delta \zeta_{val}(\omega^{\prime},\alpha)/\delta\omega^{\prime}\delta\delta\zeta_{trn} (\omega,\alpha)/\delta\omega\delta\alpha \tag{19}\] \[\frac{\delta\delta\zeta_{trn}(\omega,\alpha)}{\delta\omega\delta \alpha}=\delta(\zeta_{trn}(\omega^{+},\alpha)-\zeta_{trn}(\omega^{-},\alpha))/ (2\varepsilon\delta\alpha) \tag{20}\]

With the help of analytical modeling of optimization objective, we are able to derive the differentiable polynomial architecture search framework in Algo. 1. The input of search framework includes backbone model \(M_{b}\), dataset \(D\), latency loop up table \(Lat(OP)\), and hardware resource \(H\). The algorithm returns a searched polynomial model \(M_{p}\). The algorithm iteratively trains the architecture parameter \(\alpha\) and weight \(\omega\) parameter till the convergence. Each \(\alpha\) update requires 4 forward paths and 5 backward paths according to Eq. 18 to Eq. 20, and each \(\omega\) update needs 1 forward paths and 1 backward paths. After the convergence of training loop, the algorithm returns a deterministic model architecture by applying \(OP_{l}(x)=OP_{l,k^{*}}(x)\), \(s.t.\;k^{*}=\text{argmax}_{k}\;\alpha_{l,k}\). The returned architecture is then used for 2PC based PI evaluation.

## IV **Evaluation**

**Hardware setup.** Our platform uses two ZCU104 MPSoCs connected via a 1 GB/s LAN router. With a 128-bit load/store bus and 32-bit data, we process four data simultaneously at 200MHz. The fixed point ring size is set to 32 bits for PI.

**Datasets and Backbone Models.** PASNet is evaluated on CIFAR-10 and ImageNet for image classification tasks. CIFAR-10 [22] has colored \(32\times 32\) images, with \(10\) classes, \(50,000\) training, and \(10,000\) validation images. ImageNet [22] has RGB \(224\times 224\) images, with \(1000\) categories, \(1.2\) million training, and \(50,000\) validation images.

**Systems Setup.** Polynomial architecture search experiments are conducted using Ubuntu 18.04, Nvidia Quadro RTX 6000 GPU, PyTorch v1.8.1, and Python 3.9.7. Pretrained weights for CIFAR-10 and ImageNet are from [23] and Pytorch Hub [24], respectively. Cryptographic DNN inference is performed on FPGA-based accelerators using two ZCU104 boards, connected via Ethernet LAN. The FPGA accelerators are optimized with coarse-grained and fine-grained pipeline structures, as discussed in Sec. III-C.

### **Hardware-aware NAS Evaluation**

Our hardware-aware PASNet evaluation experiment (algorithm descripted in Sec. III-D) was conducted on CIFAR-10 training dataset. A new training & validation dataset is randomly sampled from the CIFAR-10 training dataset with 50%-50% split ratio. The new training dataset is used to update the weight parameter of PASNet models, and the new validation dataset is used to update the architecture parameter.

Fig. 5: PASNet framework evaluation on CIFAR-10 dataset under 2PC PI setup. Network bandwidth: 1 GB/s. Device: ZCU104.
The hardware latency is modeled through section. III-C, and the \(\lambda\) for latency constraint in loss function is tuned to generate architectures with different latency-accuracy trade-off. Prior search starts, the major model parameters are randomly initialized and the polynomial activation function is initialized through **STPAI** method. We use VGG-16 [25], ResNet-18, ResNet-34, ResNet-50 [26], and MobileNetV2 [27] as backbone model structure to evaluate our PASNet framework.

With the increase of latency penalty, the searched structure's accuracy decreases since the DNN structure has more polynomial operators. After the proper model structure is found during architecture search process, the transfer learning with **STPAI** is conducted to evaluate the finetuned model accuracy.

The finetuned model accuracy under 2PC setting with regard to \(\lambda\) setting can be found in Fig. 5(a). The baseline model with all ReLU setting and all-polynomial operation based model are also included in the figure for comparison. Generally, a higher polynomial replacement ratio leads to a lower accuracy. The VGG-16 model is the most vulnerable model in the study, while the complete polynomial replacement leads to a 3.2% accuracy degradation (baseline 93.5%). On the other side, ResNet family are very robust to full polynomial replacement and there are only \(0.26\%\) to \(0.34\%\) accuracy drop for ResNet-18 (baseline 93.7%), ResNet-34 (baseline 93.8%) and ResNet-50 (baseline 95.6%). MobileNetV2's is in between the performance of VGG and ResNet, in which a full polynomial replacement leads to \(1.27\%\) degradation (baseline 94.09%).

On the other hand, Fig. 5(b) presents the latency profiling result of searched models performance on CIFAR-10 dataset under 2PC setting. All polynomial replacement leads to 20 times speedup on VGG-16 (baseline 382 ms), 15 times speedup on MobileNetV2 (baseline 1543 ms), 26 times speedup, ResNet-18 (baseline 324 ms), 19 times speedup on ResNet-34 (baseline 435 ms), and 25 times on speedup ResNet-50 (baseline 922 ms). With most strict constraint \(\lambda\), the searched model latency is lower.

### **Cross-work ReLU Reduction Performance Comparison**

A futher accuracy-ReLU count analysis is conducted and compared with SOTA works with ReLU reduction: DeepRe-Duce [7], DELPHI [10], CryptoNAS [8], and SNI [28]. As shown in Fig. 6, we generate the pareto frontier with best accuracy-ReLU count trade-off from our architecture search result. We name the selected models as **PASNet**, and compare it with other works. The accuracy-ReLU count comparison is show in Fig. 7. Our work achieves a much better accuracy vs. ReLU comparison than existing works, especially at the situation with extremely few ReLU counts.

### **Cross-work PI System Performance Comparison**

We pick up 4 searched PASNet model variants for CIFAR-10 & ImageNet dataset accuracy & latency evaluation and name them as **PASNet-A**, **PASNet-B**, **PASNet-C**, **PASNet-D**. PASNet-A is a light-weighted model and shares the same backbone model as ResNet-18 but has only polynomial operators. PASNet-B and PASNet-C are heavily-weighted models that share the same backbone model as ResNet-50. PASNet-B has only polynomial operators and PASNet-C has 4 2PC-ReLU operators. PASNet-D is a medium-weighted model derived from MobileNetV2 with all polynomial layers. Note that the baseline top-1 accuracy of ResNet-18 on CIFAR-10 and ImageNet are 93.7% and 69.76%, baseline top-1 accuracy of ResNet-50 on CIFAR-10 and ImageNet are 95.65% and 78.8%, and the baseline top-1 accuracy of MobileNetV2 on CIFAR-10 and ImageNet are 94.09% and 71.88%.

The PASNet variants evaluation results and ImageNet cross-work comparison with SOTA CryptGPU [13] and Crypt-FLOW [1] implementation can be found in Tab. I. We observe a 0.78% top-1 accuracy increase for our light-weighted

\begin{table}
\begin{tabular}{c|c|c|c|c|c|c|c|c|c} \hline  & \multicolumn{4}{c|}{CIFAR-10 dataset} & \multicolumn{4}{c}{ImageNet dataset} \\ \hline Model & Top I (\%) & Lat. (ms) & Comm. (MB) & Eff. (1/(ms*KW)) & Top I (\%) & Top 5 (\%) & Lat. (s) & Comm. (GB) & Eff. (1/(s*KW)) \\ \hline PASNet-A & 93.37 & 12.2 & 2.86 & 5.12 & 70.54 & 89.59 & 0.063 & 0.035 & 999 \\ \hline PASNet-B & 95.31 & 36.74 & 13.18 & 1.70 & 78.79 & 93.99 & 0.228 & 0.162 & 274 \\ \hline PASNet-C & 95.33 & 62.91 & 30.03 & 0.99 & 79.25 & 94.38 & 0.539 & 0.368 & 115 \\ \hline PASNet-D & 92.82 & 104.09 & 25.01 & 0.60 & 71.36 & 90.15 & 0.184 & 0.103 & 339 \\ \hline CryptoGPU & \(\backslash\) & \(\backslash\) & \(\backslash\) & \(\backslash\) & 78 & 92 & 9.31 & 3.08 & 0.15 \\ \hline ResNet0 & \(\backslash\) & \(\backslash\) & \(\backslash\) & \(\backslash\) & 76.45 & 93.23 & 25.9 & 6.9 & 0.096 \\ \hline \end{tabular}
\end{table} TABLE I: PASNet evaluation & cross-work comparison with CryptGPU [13] and CryptFLOW [1]. Batch size = 1
PASNet-A compared to baseline ResNet-18 performance on ImageNet. Heavily-weighted models PASNet-B and PASNet-C achieve comparable (-0.01%) or even higher accuracy (+0.45%) than the ResNet-50 baseline. we achieve only a 0.13% accuracy drop for our medium-weighted PASNet-D compared to baseline MobileNetV2 performance on ImageNet. Even with the ZCU 104 edge devices setting, we can achieve a much faster secure inference latency than the SOTA works implemented on the large-scale server system. Our light-weighted PASNet-A achieves 147 times latency reduction and 88 times communication volume reduction compared to CryptGPU [13]. Our heavily-weighted model PASNet-B achieved 40 times latency reduction and 19 times communication volume reduction than CryptGPU [13] while maintaining an even higher accuracy. Our highest accuracy model PASNet-C achieved 79.25% top-1 accuracy on the ImageNet dataset with 17 times latency reduction and 8.3 times communication volume reduction than CryptGPU [13]. Note that our system is built upon the ZCU104 edge platform, so our energy efficiency is much higher (more than 1000 times) than SOTA CryptGPU [13] and Crypt FLOW [1] systems.

## V **Discussion**

Existing MLaaS accelerations focused on plaintext inference acceleration [29, 30, 31, 32]. Others target on plaintext training acceleration [53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63], federated learning [64, 65, 66] to protect the privacy of training data, and privacy protection of model vendor [67, 68].

In this work, we propose PASNet to reduce high comparison protocol overhead in 2PC-based privacy-preserving DL, enabling low latency, high energy efficiency, and accurate 2PC-DL. We employ hardware-aware NAS with latency modeling. Experiments demonstrate PASNet-A and PASNet-B achieve 147x and 40x speedup over SOTA CryptGPU on ImageNet PI test, with 70.54% and 78.79% accuracy.

## Acknowledgement

This work was in part supported by the NSF CNS-2247891, 2247892, 2247893, CNS-2153690, DGE-2043183, and the Heterogeneous Accelerated Compute Clusters (HACC) program at UIUC. Any opinions, findings and conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the funding agencies.
