Input-Aware Dynamic Timestep Spiking Neural Networks for Efficient
  In-Memory Computing
Spiking Neural Networks (SNNs) have recently attracted widespread research
interest as an efficient alternative to traditional Artificial Neural Networks
(ANNs) because of their capability to process sparse and binary spike
information and avoid expensive multiplication operations. Although the
efficiency of SNNs can be realized on the In-Memory Computing (IMC)
architecture, we show that the energy cost and latency of SNNs scale linearly
with the number of timesteps used on IMC hardware. Therefore, in order to
maximize the efficiency of SNNs, we propose input-aware Dynamic Timestep SNN
(DT-SNN), a novel algorithmic solution to dynamically determine the number of
timesteps during inference on an input-dependent basis. By calculating the
entropy of the accumulated output after each timestep, we can compare it to a
predefined threshold and decide if the information processed at the current
timestep is sufficient for a confident prediction. We deploy DT-SNN on an IMC
architecture and show that it incurs negligible computational overhead. We
demonstrate that our method only uses 1.46 average timesteps to achieve the
accuracy of a 4-timestep static SNN while reducing the energy-delay-product by
80%.
Yuhang Li, Abhishek Moitra, Tamar Geller, Priyadarshini Panda
# Input-Aware Dynamic Timestep Spiking Neural Networks for Efficient In-Memory Computing

###### Abstract

Spiking Neural Networks (SNNs) have recently attracted widespread research interest as an efficient alternative to traditional Artificial Neural Networks (ANNs) because of their capability to process sparse and binary spike information and avoid expensive multiplication operations. Although the efficiency of SNNs can be realized on the In-Memory Computing (IMC) architecture, we show that the energy cost and latency of SNNs scale linearly with the number of timesteps used on IMC hardware. Therefore, in order to maximize the efficiency of SNNs, we propose input-aware Dynamic Timestep SNN (DT-SNN), a novel algorithmic solution to dynamically determine the number of timesteps during inference on an input-dependent basis. By calculating the entropy of the accumulated output after each timestep, we can compare it to a predefined threshold and decide if the information processed at the current timestep is sufficient for a confident prediction. We deploy DT-SNN on an IMC architecture and show that it incurs negligible computational overhead. We demonstrate that our method only uses 1.46 average timesteps to achieve the accuracy of a 4-timestep static SNN while reducing the energy-delay-product by 80%.

 Spiking neural networks, in-memory computing, dynamic inference

## I Introduction

Deep learning has revolutionized many challenging computational tasks such as computer vision and natural language processing [10] using Artificial Neural Networks (ANNs). These successes, however, have come at the cost of tremendous computing resources and high latency [6]. Over the past decade, Spiking Neural Networks (SNNs) have gained popularity as an energy-efficient alternative to ANNs [14, 17]. SNNs are different from ANNs in that they process inputs over a series of timesteps, whereas ANNs infer over what can be considered a single timestep. The biologically-plausible neurons in SNNs maintain a variable called membrane potential, which controls the behavior of the SNN over a series of timesteps. When the membrane potential exceeds a certain threshold, the neuron fires, creating a spike, and otherwise, the neuron remains inactive (neuron outputs a 0 or 1). Such spike-based computing creates sparsity in the computations and replaces multiplications with additions.

Although the binary spike nature of SNNs eliminates the need for multiplications, compared to ANNs, SNNs require significantly more memory access due to multi-timestep computations on traditional von-Neumann architectures (called the "memory wall problem") [21]. To alleviate this problem, In-Memory Computing (IMC) hardware is used to perform analog dot-product operations to achieve high memory bandwidth and compute parallelism [15]. In this work, we mainly focus on achieving lower energy and latency in the case of IMC-implemented SNNs while maintaining iso-accuracy.

Fig. 1(A) shows a component-wise energy distribution for the CIFAR10-trained VGG-16 network on 64\(\times\)64 4-bit RRAM IMC architecture. Among these, the digital peripherals (containing crossbar input switching circuits, buffers, and accumulators) entail the highest energy cost (45%). The IMC-crossbar and analog-to-digital converter (ADC) consumes the second highest energy (25%). Efforts to lower energy consumption have been made by previous works. As an example, prior IMC-aware algorithm-hardware co-design techniques [13, 22], have used pruning, quantization to reduce the ADC and crossbar energy, and area cost. However, in the case of SNNs, the improvement is rather limited because the crossbar and ADC only occupy 25% of the overall energy cost.

Unlike ANNs, the number of timesteps in SNNs plays an important role in hardware performance, which is orthogonal to data precision or sparsity. In Fig. 1(B) we investigate how timesteps affect the energy consumption and latency of an SNN. Note that both metrics are normalized to the performance of a 1-timestep SNN. We find that both energy consumption and latency scale linearly with the number of timesteps, up to \(4.9\times\) more energy and \(8\times\) more latency when changing the number of timesteps from 1 to 8. More importantly, if one can reduce the number of timesteps in SNNs, then all parts in Fig. 1(A) can benefit from the energy and latency savings. These findings highlight the tremendous potential to optimize SNNs' performance on IMC hardware.

In fact, [3, 8, 12] have explored ways to reduce the number of timesteps from an algorithmic perspective. They

Fig. 1: Energy estimation on our IMC architecture using VGG-16 on CIFAR-10 dataset. (A) energy ratio of each unit, (B) energy/latency vs. timesteps.
all train an SNN with a high number of timesteps first and then finetune the model with fewer timesteps later. However, their method decreases the number of timesteps for all input samples, thereby inevitably leading to an accuracy-timestep trade-off. In this paper, we tackle this problem with another solution. _We view the number of timesteps during inference as a variable conditional to each input sample._ We call our method Dynamic Timestep Spiking Neural Network (DT-SNN) as it varies the number of timesteps based on each input sample. In particular, we use entropy thresholding to determine the appropriate number of timesteps for each sample. To further optimize our algorithm in practice, we design a new training loss function and implement our algorithm on an IMC architecture.

The main contributions of our work are summarized below:

1. Based on what we have seen thus far, this is the first work that changes the number of timesteps in SNNs based on the input, reducing computational overhead and increasing inference efficiency without compromising task performance.
2. To achieve that goal, we propose using entropy thresholding to distinguish the number of timesteps required. Meanwhile, we also provide a new training loss function and an IMC implementation of our method.
3. Extensive experiments are carried out to demonstrate the efficacy and efficiency of DT-SNN. For example, the DT-SNN ResNet-19 achieves the same accuracy as the 4-timestep SNN ResNet-19 with only an average of 1.27-timestep on the CIFAR-10 dataset, reducing 84% energy-delay-product.

## II Preliminaries

We start by introducing the basic background of SNNs. We denote the overall spiking neural network as a function \(f_{T}(\mathbf{x})\) (\(\mathbf{x}\) is the input image), its forward propagation can be formulated as

\[\mathbf{y}=f_{T}(\mathbf{x})=\frac{1}{T}\sum_{t=1}^{T}h\circ g^{L}\circ g^{L-1}\circ g ^{L-2}\circ\cdots g^{1}(\mathbf{x}), \tag{1}\]

where \(g^{\ell}(\mathbf{x})=\mathrm{LIF}(\mathbf{W}^{\ell}\mathbf{x})\) denotes the \(\ell\)-th block. A block contains a convolutional layer, a leaky integrate-and-fire (LIF) layer, and an optional normalization layer placed in between the former two layers [23]. \(L\) represents the total number of blocks in the network and \(h(\cdot)\) denotes the final linear classifier. In this work, we use the direct encoding method, i.e., using \(g^{1}(\mathbf{x})\) to encode the input tensor into spike trains, as done in recent SNN works [20]. To get the final prediction, we repeat the inference process \(T\) times and average the output from the classifier.

SNNs emulate the biological neurons using LIF layers. For each timestep, the input current charges the membrane potential \(\mathbf{u}\) in the LIF neurons. When the membrane potential exceeds a certain threshold, a spike \(\mathbf{s}\) will be fired to the next layer, given by

\[\mathbf{u}^{\ell}[t+1]=\tau\mathbf{u}^{\ell}[t]+\mathbf{W}^{\ell}\mathbf{s}^{\ell}[t], \tag{2}\]

\[\mathbf{s}^{\ell+1}[t+1]=\begin{cases}1&\text{if }\mathbf{u}^{\ell}[t+1]>V_{th}\\ 0&\text{otherwise}\end{cases}, \tag{3}\]

where \(\tau\in(0,1]\) is the leaky factor, mimicking the potential decay. If a spike is fired, the membrane potential will be reset to 0, _i.e._\((\mathbf{u}[t+1]=\mathbf{u}[t+1]*(1-\mathbf{s}[t+1]))\).

In the spiking neurons, all functions except the spike firing function (Eq. (3)) can be normally differentiated. The firing function generates a 0 gradient if \(\mathbf{u}^{\ell}[t+1]\neq V_{th}\), otherwise, it generates a gradient with infinity. This impedes the gradient-based optimization in SNNs. To overcome this problem, we leverage the surrogate gradient training method [19]. Specifically, in the forward propagation, we keep the original LIF neuron dynamics, while in the backward propagation, we use another function:

\[\frac{\partial\mathbf{s}^{\ell}[t]}{\partial\mathbf{u}^{\ell}[t]}=\max(0,V_{th}-|\mathbf{u }^{\ell}[t]-V_{th}|) \tag{4}\]

## III Methodology

In this section, we first introduce the algorithm for our work. Then we demonstrate the hardware implementation of DT-SNN.

### _Dynamic Timestep Spiking Neural Network_

Because spikes in an SNN are sparse and binary, the number of timesteps, therefore, controls the density of information inside the SNNs. Generally, more timesteps help SNNs explore more temporal information and thus achieve higher task performance. Fig. 2 demonstrates that when the number of timesteps of an SNN VGG-16 is increased from 1 to 4 during inference, the accuracy increases as well. Together with the hardware performance as shown in Fig. 1(B), the number of timesteps \(T\) controls a trade-off between hardware performance and task performance on an SNN model \(f_{T}(\cdot)\).

Unlike the conventional approach where \(T\) is selected and fixed for all images, we propose a conditional probability of selecting \(T\) for different input \(\mathbf{x}\). We call our method the Dynamic Timestep Spiking Neural Network (DT-SNN). More concretely, denote \(\mathbb{P}(T|\mathbf{x})\) as the conditional probability of \(T\) with respect to \(\mathbf{x}\), DT-SNN is given by

\[f_{\widehat{T}\sim\mathbb{P}(T|\mathbf{x})}=\frac{1}{\widehat{T}}\sum_{t=1}^{ \widehat{T}}h\circ g^{L}\circ g^{L-1}\circ g^{L-2}\circ\cdots g^{1}(\mathbf{x}). \tag{5}\]

DT-SNN allows allocating a different number of timesteps for each input sample. As seen in Fig. 2, we find that the majority

Fig. 2: The impact of the number of timesteps on the accuracy. We test the spiking VGG-16 on three datasets (CIFAR10, CIFAR100, TinyImageNet).
of samples can be correctly classified with fewer timesteps. For example, on the CIFAR-100 dataset, 69.39% of overall test data can be correctly predicted using only 2 timesteps. Yet only 2.9% of test data needs full timesteps (\(T=4\)) to get the right prediction. If we compare the hardware performance, the 4-timestep model brings 86% more energy consumption and 100% more latency than the 2-timestep model. This observation is also applicable to other datasets like CIFAR10 and TinyImageNet.

Choosing the Right \(T\)Our objective in DT-SNN is to reduce the unnecessary timesteps as much as possible while not compromising accuracy. However, finding the appropriate timestep for each input data is non-trivial. In this work, we use entropy to determine \(T\). Formally, given a dataset that has \(K\) classes, the prediction probability \(\pi(\mathbf{y}|\mathbf{x})\) is calculated by the Softmax function \((\sigma(\cdot))\), given by

\[\pi(\mathbf{y}_{i}|\mathbf{x})=\sigma_{\mathrm{i}}(f(\mathbf{x}))=\frac{\exp(f(\mathbf{x})_{i} )}{\sum_{j=1}^{K}\exp(f(\mathbf{x})_{j})}, \tag{6}\]

where \(\pi(\mathbf{y}_{i}|\mathbf{x})\) is the probability of predicting \(i\)-th class. The entropy can be further calculated by

\[E_{f}(\mathbf{x})=-\frac{1}{\log K}\sum_{i=1}^{K}\pi(\mathbf{y}_{i}|\mathbf{x})\log\pi(\bm {y}_{i}|\mathbf{x}). \tag{7}\]

Here, \(\log K\) ensures the final entropy is normalized to \((0,1]\). The entropy measures the state of uncertainty. For instance, if all classes have an equal probability of \(\frac{1}{K}\), the entropy will become 1, meaning the current state is completely random and uncertain. Instead, if one class's probability is approaching 1 while others are approaching 0, the entropy moves towards 0, indicating the state is becoming certain.

Generally, the prediction accuracy is highly correlated with entropy. If the model is certain about some inputs (low entropy), the prediction would be highly probable to be correct, and vice versa [5]. Therefore, we select the \(T\) if the entropy is lower than some pre-defined threshold \(\theta\), given by

\[\hat{T}(\mathbf{x})=\operatorname*{arg\,min}_{\hat{T}}\{E_{f_{T}}(\mathbf{x})<\theta| 1\leq\hat{T}<T\}\cup\{T\}. \tag{8}\]

Here, the \(\hat{T}\) is selected based on the lowest timestep that can have lower-than-\(\theta\) entropy. If none of them can have confident output, the SNN will use maximum timesteps, _i.e._, \(T\).

Training DT-SNNOriginally, the loss function for training an SNN is the cross-entropy function, given by:

\[\mathcal{L}(\mathbf{x},\mathbf{z})=-\frac{1}{B}\sum_{i=1}^{K}\mathbf{z}_{i}\log\pi(f_{T}( \mathbf{x})_{i}|\mathbf{x}), \tag{9}\]

where \(\mathbf{z}\) is the label vector and \(B\) is the batch size. Although the output from lower timesteps implicitly contributes to \(f_{T}(\mathbf{x})\), there lacks some explicit guidance to them. As shown in Fig. 2, the accuracy in the first timestep is always low. Here, we propose to explicitly add a loss function to each timestep output. The new loss function is defined as:

\[\mathcal{L}(\mathbf{x},\mathbf{z})=-\frac{1}{TB}\sum_{t=1}^{T}\sum_{i=1}^{K}\mathbf{z}_{i }\log\pi(f_{t}(\mathbf{x})_{i}|\mathbf{x}), \tag{10}\]

In practice, we find this loss function does not change much training time on GPUs. Also, we will demonstrate that adding this loss function can benefit the accuracy of the outputs from all timesteps, further improving our DT-SNN.

Relation to Early Exit in ANNConceptually our DT-SNN is similar to the Early-Exit technique in ANN [18, 1] which adds multiple exits to different layers. Here, we want to clarify the relation between our DT-SNN and early exit: (1) DT-SNN is operated in the time dimension, it naturally fits SNNs and does not require any additional layers, while early exit has to add classifier layers in each branch; (2) DT-SNN has a higher potential than early exit: in experiments section, we will show that the majority of the examples can only use the first timestep, while the first exit in ANNs outputs marginal examples. Furthermore, DT-SNN is fully complementary to the early exit, that is, we can further add the early exit technique to SNN to fulfill even higher efficiency.

### _Hardware Implementation_

We implement DT-SNN on a tiled-monolithic chip architecture [2] as shown in Fig. 3a. First, the individual layers of an SNN are mapped onto tiles. The number of tiles occupied by an SNN layer depends on factors such as the crossbar size, the number of input and output channels in a layer, kernel size, and the number of crossbars per tile. To implement DT-SNN-specific functionality, we incorporate the following modifications in conventionally used architectures 1) A digital \(\sigma-E\) module to jointly compute the SoftMax (\(\sigma(\cdot)\)) and entropy (\(E\)) followed by threshold (\(\theta\)) comparison to detect whether to exit or not. 2) Timesteps are processed sequentially without pipelining. This eliminates the delay and hardware overhead (energy and area cost) required to empty the pipeline

Fig. 3: Figure showing (a) monolithic-tiled IMC architecture implementation of an SNN (b) architecture of the \(\sigma-E\) module for softmax and entropy value computation.
in case of dynamic timestep inference. The tiles additionally contain global accumulators (GA) and global buffers (GB) for accumulating partial sums and storing the intermediate outputs, respectively from different processing elements (PE). At the tile level, all modules are connected via a Network-on-Chip (NoC) interconnect. Each tile consists of several PEs, accumulators, and buffers. Each PE contains several crossbars, accumulators and buffers. The PEs and crossbars are connected by an H-Tree interconnect. We use a standard 2D-IMC crossbar connected to peripherals such as switch matrix, multiplexers, analog-to-digital converters (ADCs), and Shift-\(\&\)-Add circuits. The switch matrix provides input voltages at the source lines (SL) while simultaneously activating the word lines (WL). The voltages accumulate over the bit lines (BL). The analog MAC value (partial sum output) is converted to a digital value using the ADC. Multiplexers enable resource sharing of ADCs and Shift-\(\&\)-Add circuits among multiple crossbar columns to reduce the area overheads. The digital partial sum outputs from different crossbars, PEs and tiles are accumulated using the PE, tile, and global accumulators, respectively. For all layers except the last, the final MAC outputs from the GA are transferred to the LIF module for the non-linear activation functionality. The spike outputs are relayed to the tiles mapping the subsequent layers.

For the last layer (a fully connected layer) the GA accumulated MAC output is directed to the \(\sigma-E\) module as shown in Fig. 3a (using red arrows). Inside the \(\sigma-E\) module MAC outputs are stored in the \(y\)-FIFO buffer. The depth of \(y\)-FIFO depends on the dataset. For example, in CIFAR10, the FIFO depth is 10. Data from the \(y\)-FIFO is passed to the address lines of the \(\sigma\)-LUT to compute \(\sigma\) which are pushed into the \(\sigma\)-FIFO. The \(\sigma\)-FIFO outputs are sent as inputs to the Entropy Module that contains LUT for \(\log(\sigma)\) computation. The Entropy Module additionally contains a multiplier and accumulator circuit (comprised of an adder and register) to implement the entropy computation using Eq. (7). If the computed entropy is less than the threshold \(\theta\), the inference is terminated and new input data is loaded into the GB. DT-SNN is implemented on the IMC architecture using parameters shown in Table I.

**Energy Consumption of the \(\sigma-E\) module:** Based on 32nm CMOS implementations, we find that the energy consumed by the \(\sigma-E\) module for one timestep is merely \(2e^{-5}\times\) of the 1 timestep inference energy consumed by the IMC architecture, which is negligible.

## IV Experimental Results

In this section, we present the evaluation of both the task performance and the hardware performance of DT-SNN, highlighting its extreme efficacy and efficiency.

### _Comparison with Static SNN_

We select 4 popular visual benchmarks for evaluation, CIFAR-10 [9], CIFAR-100 [9], TinyImageNet [4], and CIFAR10-DVS [11] dataset. For the architecture, we choose to use VGG-16 [16] and ResNet-19 [7]. We compare our DT-SNN with the static SNN, _i.e.,_ an SNN that uses a fixed number of timesteps for all inputs. The training method for the static SNN and the DT-SNN are kept the same, except that the static SNN uses Eq. (9) as training loss while DT-SNN uses Eq. (10). We train them with a batch size of 256, a learning rate of 0.1 followed by a cosine decay. The L2 regularization is set to 0.0005. The number of timesteps is set to 4 as done in existing work [23]. For task metrics, we report the top-1 accuracy on the visual benchmarks. As for hardware metrics, we measure them based on the parameters shown in Table I and further normalize them w.r.t. static SNNs. We report the number of timesteps (\(T\)), energy, and energy-delay-product (EDP). Note that the cost of DT-SNN is varied across input data, thus we average the hardware metrics in the test dataset.

#### Iv-A1 Comparison of Accuracy, Energy Cost, and \(T\)

We summarize the results of 4 datasets in Table II. Here, we test static SNN with the full number of timesteps, _i.e.,_\(T=4\), and compare the hardware performances with DT-SNN under a similar accuracy level. We find that DT-SNN only needs 1.46 average timesteps on the CIFAR-10 dataset, bringing more than 50% energy saving. For the other three datasets, DT-SNN requires roughly half the number of timesteps used in a static SNN model. Nevertheless, DT-SNN reduces at least 40% of energy cost when compared to static SNN.

Fig. 4: Comparison between static SNN and DT-SNN in terms of Energy-Delay-Product (EDP) (normalized to the static SNN).
#### Vi-A2 Comparison of EDP

We next compare the EDP between static SNNs and DT-SNNs. EDP is more suitable for measuring a holistic performance in hardware because it considers both time and energy efficiency. Fig. 4 shows the EDP comparison normalized by the EDP of the static SNN. We can find that DT-SNN is extremely efficient as it reduces 61.2%\(\sim\)80.9% EDP of static SNNs. These results highlight the efficiency brought by our method, leading to both energy cost and latency reduction.

#### Vi-A3 Accuracy vs. EDP curve

The static SNN can adjust the number of timesteps for all inputs to balance its accuracy and efficiency. Our DT-SNN can also adjust threshold \(\theta\) to balance such a trade-off. Here, we draw an accuracy-EDP curve in Fig. 5. _Note that here the EDP is normalized to the EDP of the 1-timestep static SNN._ We evaluate static SNN at 1,2,3, and 4 timesteps, and evaluate DT-SNN using three different thresholds. It can be seen that our DT-SNN is placed in the top-left corner, indicating a better accuracy-EDP trade-off than the static SNN. Remarkably, DT-SNN can bring significant improvement in low-timestep scenarios. For instance, DT-SNN VGG-16 increases the accuracy by 17% when compared to the 1-timestep static counterpart on the CIFAR-10 dataset, while it only has \(\sim\)10% higher EDP.

In order to further visualize the dynamic timesteps in our method, Fig. 5 provides three pie charts in each case, which show the percentage of input examples that are inferred with 1, 2, 3, or 4 timesteps. Notably, \(T=1\) is usually the most selected case for the input due to the fact that most input examples can be correctly predicted using only 1 timestep. As the threshold decreases, more images start to use higher timesteps. Overall, we find \(T=3\) and \(T=4\) are rarely used in DT-SNN, demonstrating the effectiveness of our method to reduce redundant timesteps.

#### Vi-A4 Comparison with Prior Work :

Here, we also compare our method with prior work on SNNs. We compare tdBN [23] and Dspike [12] with our static-SNN and DT-SNN trained with Eq. (10). Fig. 6(A) shows the accuracy under different \(T\). Our DT-SNN reaches a new state of the art.

#### Vi-A5 Non-Ideal Accuracy with Device Variations

So far, all the experiments are performed without considering device conductance variation. In Fig. 6(B), we compare DT-SNN and static SNN under 20% device conductance variation. We simulate this by adding noise to the weights post-training. We see that DT-SNN still maintains higher accuracy while eliminating the redundant timesteps compared to static-SNN.

### _Acceleration in General Processors_

In the previous section, we demonstrated that our DT-SNN can accelerate the inference on an IMC architecture. Here, we show that apart from the IMC architecture we simulated, our method can also be applicable to other types of hardware like digital processors. To this end, we measure the inference throughput (_i.e.,_ the number of images inferred per second) on an RTX 2080Ti GPU simulated by PyTorch using batch size 1. Table III lists the accuracy, (averaged) timesteps, and throughput. As can be seen from the table, the throughput on GPU significantly reduces as the timesteps are increased.

Fig. 5: Accuracy vs. EDP curve for both static SNN (drawn by pink line) and DT-SNN (drawn by blue line). For the static SNN, we report the accuracy and EDP when \(T=\{1,2,3,4\}\). For the DT-SNN, we draw the pie charts illustrating the distribution of \(\hat{T}(\mathbf{x})\).

Fig. 6: Accuracy vs. the number of timesteps. (A) Comparison with prior works, (B) Comparison under non-ideal (NI) device variation in the IMC.
Compared to static SNNs, our DT-SNN substantially improves the throughput while not sacrificing accuracy. For example, DT-SNN ResNet-19 with 1.07 averaged timesteps can infer 169.3 images per second, quite close to the 1-timestep static SNN (185.3 images per second), yet still bringing 3.4% accuracy improvement.

### _Ablation Study_

In this section, we ablate the training loss function choice. To verify this, we train static an SNN VGG-16 on CIFAR-10 either with Eq. (9) or Eq. (10) and test the corresponding accuracies of both static SNN and DT-SNN. Fig. 7 demonstrates the comparison between these two loss functions. We find that our training loss boosts the accuracy of all timesteps in the static SNN. In particular, the first timestep of VGG-16 changes from 76.3% to 91.5%. This result proves that explicit guidance from label annotations should be added to the lower timesteps. Meanwhile, it also increases the full timestep performance, resulting in a 0.6% accuracy increase on VGG-16.

This improvement is extremely beneficial to DT-SNN. According to the pie charts describing the distribution of \(\hat{T}\), we find our training loss function enables a smaller number of timesteps to be required to classify the test data, thus reducing the EDP significantly.

### _Visualization_

In this section, we visualize the input images that are differentiated by our DT-SNN. Ideally, we anticipate DT-SNN can identify whether an image is easy or hard to infer (corresponding to 4 or 1 timestep). To maximize the differentiation, we use a low threshold to filter out the high timesteps, so that only the easiest images can be classified in the first timestep and vice versa. Fig. 8 presents the results on the TinyImageNet dataset. Generally, we find the images inferred with 1 timestep exhibit a simple structure: a clear object placed in the center of a clean background. In contrast, hard images require 4 timesteps and usually mix the background and the object together, making the object imperceptible.

## V Conclusion

In this work, we introduce the Dynamic Timestep Spiking Neural Network, a simple yet significantly effective method that selects different timesteps for different input samples. DT-SNN determines the suitable timestep based on the confidence of the model output, seamlessly fitting the nature of sequential processing over time in SNNs. Moreover, DT-SNN is practical. It can be deployed to IMC architecture and even general digital processors. Extensive experiments prove that DT-SNN establishes a new state-of-the-art trade-off between hardware efficiency and task performance.
