An Efficient and Accurate Memristive Memory for Array-based Spiking
  Neural Networks
Memristors provide a tempting solution for weighted synapse connections in
neuromorphic computing due to their size and non-volatile nature. However,
memristors are unreliable in the commonly used voltage-pulse-based programming
approaches and require precisely shaped pulses to avoid programming failure. In
this paper, we demonstrate a current-limiting-based solution that provides a
more predictable analog memory behavior when reading and writing memristive
synapses. With our proposed design READ current can be optimized by about 19x
compared to the 1T1R design. Moreover, our proposed design saves about 9x
energy compared to the 1T1R design. Our 3T1R design also shows promising write
operation which is less affected by the process variation in MOSFETs and the
inherent stochastic behavior of memristors. Memristors used for testing are
hafnium oxide based and were fabricated in a 65nm hybrid CMOS-memristor
process. The proposed design also shows linear characteristics between the
voltage applied and the resulting resistance for the writing operation. The
simulation and measured data show similar patterns with respect to voltage
pulse-based programming and current compliance-based programming. We further
observed the impact of this behavior on neuromorphic-specific applications such
as a spiking neural network
Hritom Das, Rocco D. Febbo, SNB Tushar, Nishith N. Chakraborty, Maximilian Liehr, Nathaniel Cady, Garrett S. Rose
# An Efficient and Accurate Memristive Memory for Array-based Spiking Neural Networks

###### Abstract

Memristors provide a tempting solution for weighted synapse connections in neuromorphic computing due to their size and non-volatile nature. However, memristors are unreliable in the commonly used voltage-pulse-based programming approaches and require precisely shaped pulses to avoid programming failure. In this paper, we demonstrate a current-limiting-based solution that provides a more predictable analog memory behavior when reading and writing memristive synapses. With our proposed design READ current can be optimized by \(\sim\)19x compared to the 1T1R design. Moreover, our proposed design saves \(\sim\)9x energy compared to the 1T1R design. Our 3T1R design also shows promising write operation which is less affected by the process variation in MOSFETs and the inherent stochastic behavior of memristors. Memristors used for testing are hafnium oxide based and were fabricated in a \(65\,\mathrm{nm}\) hybrid CMOS-memristor process. The proposed design also shows linear characteristics between the voltage applied and the resulting resistance for the writing operation. The simulation and measured data show similar patterns with respect to voltage pulse based programming and current compliance based programming. We further observed the impact of this behavior on neuromorphic-specific applications such as a spiking neural network.

 Memristor, LRS, HRS, neuromorphic computing, DPE, voltage-controlled, current compliance, memory reliability, accuracy, low-power memory.

## I Introduction

Over the last decade, artificial intelligence has added a useful suite of new computational tools. However, utilizing these tools in an effective manner with limited access to internet and power has proven to be a challenge. Meeting such requirements, using state-of-the-art computing systems, is hindered in part by the separation of the memory and computation unit [1], which causes large energy consumption during the constant rapid transfer of data between memory and processor. This problem can be mitigated by designing a circuit which uses in-memory computing [2, 3, 4, 5]. A classical example of in-memory computing is the dot product engine (DPE) [6, 7, 8], which can be the backbone of many machine learning algorithms including neuromorphic computing [9, 10] and reservoir computing [11, 12]. The most basic implementation of a DPE performs a dot product between a vector and a matrix. The energy during this operation can be reduced further if a memory device such as a memristor is used to store the values of the matrix as a function of their stored resistance. Due to lower _READ_ power and multi-level storage capacity, the memristor device shows a higher energy efficiency compared to conventional digital memory such as SRAM or DRAM [13, 14, 1, 15].

A memristor is a two-terminal device that can act as an analog memory [16]. By applying a specific voltage to the top electrode for some time, the memristor can have its resistance value lowered through the formation of a filament through the material. This is known as the low resistance state (LRS). By applying a negative voltage to the top electrode of the memristor, this filament can be broken which RESETs the memristor into a high resistance state (HRS). For example, the memristive devices used in this paper (resistive random access memory, or RRAM in a one transistor one RRAM or 1T1R configuration) utilize hafnium oxide as the switching material and can be _SET_ into a LRS by applying a voltage of positive \(0.7\,\mathrm{V}\). The purpose of the _SET_ operation is analogous to writing data to memory. During this process, a specific final resistance value is targeted which will later be sensed during _READ_ operations. During this _SET_ process, the memristor's resistance will rapidly reduce as long as the voltage is above the threshold. The lowering of the resistance reaches a stopping point once the voltage goes below the threshold. On the other hand, if a constant current is maintained, this stopping point will occur at a point relative to the magnitude of the current applied. This is due to Ohm's law. Therefore, by limiting the maximum current, a minimum memristor resistance value can be targeted.

When designing memristive based memory systems, specific challenges need to be considered. Managing variation across devices and during read/write cycles is one of these challenges for analog memories. The behavior is required to be predictable across all structures in order to have a reliable memory. This variation can cause large discrepancies between operation during simulation and post-fabrication. In
memristive memory, this is especially apparent due to the inherent stochastic behavior in the memristors themselves. This is largely due to the unpredictable process of filament formation which takes place during a SET operation. To minimize these effects, an LRS range of 5 k\(\Omega\) to 20 k\(\Omega\) is utilized due to its more predictable behavior compared to HRS. Another consideration is the voltage pulse shape during programming [17, 18, 19]. If the pulse shaping is not precise, the write resistance values can vary from their targeted value. To overcome these issues, the 3T1R memristive circuit can be utilized. This circuit is programmed utilizing current compliance through the memristor as opposed to a voltage pulse across the memristor. Also, by targeting the current through the memristor, a low-power array-based spiking neural network can be designed. If we consider a DPE design, the READ power is more crucial than the write power. This is due to the memory element only being written during the initial training operation. After training, the system will be READ repeatedly during the testing process and after deployment. Therefore, the overall power consumption of a design such as a DPE can be optimized if the READ current is reduced.

Analog implementations of a DPE using memristors as the analog storage elements shows promising features for several application domains [7, 8, 20]. However, due to the inherent variability in memristor operation as discussed earlier, computation will be inaccurate compared to traditional digital implementations [1]. This variability is due to the stochastic nature in which the memristor forms and breaks its filament. Careful design of the DPE can help mitigate some of this variability. DPE circuits are commonly implemented in a 2D crossbar array configuration where the top of each memristor is connected across the rows. Then the bottom of each memristor is connected to an n-channel MOSFET which is also connected across the columns as seen in Figure 1. This is known as an in-line configuration.

A memristive DPE can be used in neuromorphic applications such as a spiking neural network (SNN). SNNs perform computations using spikes. These spikes can be applied to a DPE in order to perform a multiplication [11, 12, 20, 21]. The result of this multiplication can be tailored to a specific application such as a classification problem or a control problem [22]. In order to get the best performance in the application, the result of the multiplication needs to be predictable within a certain range.

In this work, toward resolving the above challenges, we make the following contributions:

1. Proposed 3T1R memristive array utilizing current compliance for better reliability. 3T1R configuration provides better controllability during the _SET_ and _READ_ operations.
2. Lower _READ_ current for each resistance level is demonstrated. Due to optimized _READ_ operation, 3T1R shows lower power consumption compared to 1T1R configuration.
3. Experimental measurements and simulated results show a similar trend for variation in LRS.
4. The effect of pulse shaping during programming is observed in simulation and measured data.
5. Analog DPE is modeled and simulated to evaluate the reliability and performance of the proposed design.
6. The effect of our proposed accurate and efficient approach for neuromorphic applications are analyzed.

The remainder of the paper is organized as follows. Section II focuses on in-line style memristive DPE design. Here, the READ and write operation of the design are discussed. Section III shows the proposed design with 3T1R structure. Section IV analyses the non-linear regions of the simulation results for SET current and READ current and their impact reliability. In addition, the impact of process variation on both designs is examined using Monte Carlo. Simulated results from cadence using the memristor model from [23] and our mathematical model is evaluated. In Section V, physical data from a fabricated chip is also analyzed to observe the reliability. Applications are evaluated in Section VI. There are four different classification tasks taken under consideration for an SNN application. A brief overview of peripheral circuity is provided in section VII. Next, a comparison with prior work is discussed in section VIII. Finally, the paper concludes with future work in Section IX.

## II In-line Style Memristive DPE

In our proposed design a TiN TE-HfO2-TiN BE material stack is utilized to construct the memristor device. After fabrication with the 65nm CMOS 10LPe process [24], 26 devices are measured with our probe station to consider process variation and cycle-cycle variation. A Verilog-A model is derived based on our measured data such as the I-V curve, threshold voltage for switching, switching time, and process variation at the different memristive regions. In addition, curve fitting parameters are also used to better match model performance with measured results. A brief illustration of our model is presented in prior work [23]. This model is utilized to characterize the memristor devices during a system-level simulation in Cadence Spectre.

DPEs are very popular for machine learning hardware. There are different architectures available for DPE such as 1T1R (1T: one transistor, 1R: one memristor) [7, 8, 25, 3T1R [26], and so on. Due to its simple structure and operation, most of the existing designs use the 1T1R configuration [7, 8]. In this 2D crossbar array configuration, the top of each memristor is connected across the rows. Then the bottom of each memristor is connected to an n-channel MOSFET which is connected across the columns as seen in Figure 1 (a). This describes an in-line configuration.

### _SET /Write Operation_

Fig. 1 (a) illustrates a 4x4 DPE configuration where each cell represents a 1T1R synaptic memory element. There are two input signals, \(V_{in}\) and \(V_{g}\), for each row and column respectively. Each \(V_{in}\) provides a row-wise input pulse across the DPE unit. Moreover, \(V_{g}\) provides a column-wise READ or write access across the DPE unit. Fig. 1 (b) shows the internal circuit connections of a single 1T1R cell in this DPE. The top node of the memristor is connected to \(V_{in}\) with the bottom connected to the drain of the \(NMOS\) device. Additionally,
\(V_{g}\) is used as a selector for both READ and write operations in a column. During a write, a voltage pulse is driven across the selected memristor using the \(V_{in}\) (top of memristor). This voltage pulse must be carefully shaped in order to drive the appropriate analog voltage for a determined amount of time to properly write the resistance of the device [9]. Shaping this voltage pulse to produce a reliable write is a significant challenge for the 1T1R configuration. The amplitude of \(V_{in}\) for a write operation is in the range of \(0.9\,\mathrm{V}\) to \(1.1\,\mathrm{V}\), depending on the value to be written. \(V_{g}\) signals work as a digitally controlled signal to access the various cells. Analog values are considered in the LRS range of 5 k\(\Omega\) to 20 k\(\Omega\) due to more predictable resistance as compared to HRS [27].

### _READ Operation_

During a READ operation, currents flowing through multiple 1T1R cells accumulate into each column of the DPE array to form the output denoted as \(I_{out}\). The applied \(V_{in}\) could be an analog voltage corresponding to an element in a vector input. Similarly, the resistance of the memristor is expected to have been written with a value corresponding to a matrix element. Thus, the current through a particular 1T1R cell corresponds to the product of a vector element (\(V_{in}\)) and the inverse of the memristor's resistance. The source of each 1T1R \(NMOS\) is shorted with the columnar \(I_{out}\) such that its current into the column to be summed with other such currents courtesy Kirchoff's current law. In this case, the \(I_{out}\) values of the columns correspond to the output vector elements. \(V_{g}\) is the gate signal of the \(NMOS\) and it also acts as an access transistor for the READ operation. Due to high voltage forming operation, thick oxide transistors are often required for \(NMOS\) and \(PMOS\). Moreover, a thick oxide transistor is useful to reduce the flicker noise from the system [28]. For the READ operation, the \(V_{in}\) and \(V_{g}\) will be \(0.6\,\mathrm{V}\) and \(1.2\,\mathrm{V}\), respectively, to achieve low-power READ operation. All the \(V_{g}\)s can be considered as common access signals for DPE operation. As a result, all the column current can be read by activating a single \(V_{g}\). On the other hand, to get more controllability, \(V_{g}\)'s can be operated separately and READ as many column currents as needed.

## III Proposed 3T1R Style DPE

Fig. 2 shows the proposed 3T1R design for memristive DPEs. Our proposed DPE utilizes a current-controlled memristive synapse as the base memory cell. Fig. 2 (a) illustrates a 4x4 DPE arrangement with our current-controlled synapse. According to Fig. 2 (b) \(V_{readB}\) and \(V_{in}\) are the input signals for each 3T1R cell. Similar to the in-line configuration, \(I_{out}\) are the column currents representing output vector elements in the DPE circuitry. Fig. 2 (b) shows the internal configuration of the 3T1R cell. In this circuit, two \(NMOS\) transistors, one \(PMOS\) transistor, and a memristor (R) are used. In the first stage, the drain of \(MP3\) is connected to the top of the memristor and the drain of \(MN1\) is connected at the bottom of the memristor. The presence of the \(PMOS\) helps reduce leakage current through the column. For low-power design, the memristor can also be isolated from \(VDD\) when the circuit is not in operation (hold operation). On the other hand, in 1T1R combination, the top node of the memristor is always shorted with \(V_{in}\). Thus, additional control circuitry is required. \(MN2\) plays an important role to obtain a reduced _READ_ current for our proposed synapse. The gate of the \(MN2\) is controlled precisely with the help of a gate voltage that is generated by the product of the resistance of the memristor and the \(1^{st}\) stage current (Iin).

Fig. 1: (a) 4x4 in-line configuration with 1T1R structure. (b) \(V_{in}\) (red) is the common connection for all memristors in a row. \(V_{g}\) (black) are the controlling signals (READ or write) for all the memristors in a column. \(I_{out}\) (green) is the cumulative current output from each column. The width and length of \(MN1\) are \(5\,\mathrm{\SIUnitSymbolMicro m}\) and \(0.5\,\mathrm{\SIUnitSymbolMicro m}\) respectively. Here, large thick oxide transistors are required due to the high voltage during forming.

Fig. 2: (a) 4x4 3T1R style DPE configuration is illustrated. (b) \(V_{readB}\) is the common connection for all the gate of \(PMOS\) in a column. \(MP3\) will be ”OFF” during a hold operation otherwise, it will be “ON” during a write or READ operation. \(V_{in}\) is the controlling signal to access the memristor in a row to do READ and write operations. The \(V_{in}\) is from \(0.8\,\mathrm{V}\) to \(1.1\,\mathrm{V}\), during a write operation. On the other hand, the \(V_{in}\) is \(0.6\,\mathrm{V}\), during a READ operation. \(I_{out}\) is the cumulative current output from a specific column. Here, the drain of each \(MN2\) will be shorted together for a DPE configuration. Each cell contains its own ground connection for the source of MN1 and MN2.
### _SET /Write Operation_

In Fig. 2 (b), the input current \(I_{in}\) is controlled using the \(V_{in}\) at the gate of \(MN1\). This current will only depend on \(V_{in}\) with \(MN1\) acting as a current sink for the circuit. For a SET or write operation, \(V_{readB}\) is used to digitally turned "ON" \(MP3\). The input \(V_{in}\) is driven in the range from \(0.8\,\mathrm{V}\) to \(1.1\,\mathrm{V}\) to SET the resistance level in the range from 5 k\(\Omega\) to 20 k\(\Omega\).

### _READ Operation_

After a SET operation, the analog value of the 3T1R cell is also READ using a current \(I_{in}\) controlled by \(MN1\). For this, \(V_{readB}\) will set \(MP3\) "ON" with \(0\,\mathrm{V}\) and \(V_{in}\) will set \(MN1\) into the linear region of operation with \(0.6\,\mathrm{V}\). To control the current and reduce power consumption, \(MN1\) is operated at a lower voltage. The voltage at the bottom of the memristor will turn on the \(MN2\) with a minimal gate voltage. Finally, the READ current \(I_{2}\) is measured from the drain of the \(MN2\). This cell-level output current \(I_{2}\) is connected to the common column to be summed with currents from other cells, again leveraging KCL. In the next section, an empirical comparison between 1T1R and 3T1R is provided.

## IV Cadence Simulation Results

### _SET and READ Simulation Results_

In our simulation, a \(65\,\mathrm{nm}\) CMOS 10LPe process from IBM is utilized [24]. A Verilog-A model is used to characterize the memristive device [23]. A statistical block in this model shows the process variation and stochastic behavior of the memristor. Monte Carlo analysis is used to observe the effect of process variation and non-linear effects of the 1T1R and 3T1R circuits. Fig. 3 (a) and (b) show the simulation results for SET operation with an initial resistance of 100 k\(\Omega\) at different \(V_{in}\). The range is varied from \(0.8\,\mathrm{V}\) to \(1.2\,\mathrm{V}\). The SET current for 1T1R cell varies from a low current of about \(7\,\mathrm{\SIUnitSymbolMicro A}\) to \(132\,\mathrm{\SIUnitSymbolMicro A}\). On the other hand, the SET current of 3T1R is slightly higher and varies from about \(35\,\mathrm{\SIUnitSymbolMicro A}\) to \(292\,\mathrm{\SIUnitSymbolMicro A}\). Here, the high SET current of 3T1R is a trade-off for better accessibility for write operations. 3T1R has a more desirable writing functionality compared to 1T1R since the SET current is more linear with respect to the voltage. Due to Ohms law, the final resistance achieved is directly proportional to the current applied during a SET operation. So, having a linear set current will offer better predictability and reliability for programming operations. Fig. 3 (c) and (d), show the power consumption of 1T1R and 3T1R cells respectively. Due to the high SET current, 3T1R draws higher power than 1T1R devices. According to Fig. 3 (c), a SET operation of 1T1R shows the power range from about \(5\,\mathrm{\SIUnitSymbolMicro W}\) to \(160\,\mathrm{\SIUnitSymbolMicro W}\). On the other hand, the power consumption of 3T1R is significantly higher, ranging from about \(115\,\mathrm{\SIUnitSymbolMicro W}\) to \(964\,\mathrm{\SIUnitSymbolMicro W}\). SET current or power is only considered when the memory array will be utilized for training the dataset. READ power has a higher impact than write power on the total power consumption of a system such as a DPE. However, writing a precise resistance value to the memristor is critical for repeatable results in machine learning.

In the READ operation, it is important to precisely represent the weight value for any machine learning application. Thus, the usability of the DPE design hinges on if the current values for a specific resistance level are distinguishable or not. At first, we consider the 1T1R combination and READ the output current \(I_{2}\) when the memristor resistance is varied in the range from 5 k\(\Omega\) to 20 k\(\Omega\). According to Fig. 4 (a), the READ current range is non-linear for the 1T1R, and ranges from about \(110\,\mathrm{\SIUnitSymbolMicro A}\) to \(35\,\mathrm{\SIUnitSymbolMicro A}\). Due to the non-linearity, the current values are not easily distinguishable at the specific resistance levels. As a result, weight precision is limited in this design. On the other hand, our proposed design can differentiate resistance levels from 5 k\(\Omega\) to 20 k\(\Omega\) due to improved linearity. As seen

Fig. 4: Simulation of the current during the READ operation for both devices are shown here. (a) shows the READ current for 1T1R devices from 5 k\(\Omega\) to 20 k\(\Omega\). (b) illustrated the READ current simulation for 3T1R devices for the same resistance range. 3T1R shows a more linear and lower current level according to the resistance level. (c) and (d) show the power consumption of the 1T1R and 3T1R circuits, respectively.

Fig. 3: Cadence simulations are run with \(65\,\mathrm{nm}\) CMOS technology at room temperature. (a) shows the simulated result for 1T1R device during SET operation. SET voltages are varied from \(0.8\,\mathrm{V}\) to \(1.2\,\mathrm{V}\). (b) illustrates the SET current simulation for 3T1R configuration. (c) shows the power simulation for 1T1R device. (d) plots the power range for the 3T1R combination.
in Fig. 4 (b), the 3T1R design was also able to achieve a lower current and thus lower power. This linear output stage makes our design suitable for higher resolution weights, as compared to the 1T1R. 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## V Measured Data

1T1R and 3T1R memristive cells were fabricated as test structures using a \(65\,\mathrm{nm}\) CMOS technology. Hafnium oxide is used for the memristive layer. After fabrication, the raw wafer was tested in our probe station. We have set up different test cases for the devices such as forming, RESET, SET, READ, and endurance. In total, 38 devices were selected for the measurement test. Fig. 8 shows our fabricated chip. There are different test structures constructed with 1T1R and 3T1R combinations. All the signal names are labeled accordingly for 1T1R and 3T1R devices.

Fig. 8: Die photo of our fabricated chip (top). There are five different test structures. We have explored one test structure here. The bottom part is the one 12x2 test structure, where we have 1T1R and 3T1R devices. All the pads are labeled accordingly.

Fig. 10: Measured DC test data of 3T1R configuration where MTop is fixed at a DC voltage and the gate of the \(NMOS\) is varied with different SET voltage. From \(0.7\,\mathrm{V}\) to \(0.9\,\mathrm{V}\), the LRS shows high variability and less stability. On the other hand, at higher SET voltage, the std. dev. of the resistance is lower with LRS. By controlling compliance current with the gate of \(M_{N1}\) a resistance range from 5 k\(\Omega\) and 20 k\(\Omega\) can be targeted during programming in a DC environment. Therefore no pulse shaping is required.

Fig. 7: Layout of 1T1R and 3T1R memristive memory array on \(65\,\mathrm{nm}\) CMOS process. (a) shows a 4x4 memory array of 1T1R cells. (b) illustrates a 4x4 memory array of 3T1R cells. Here, the memristive layer is HfO\({}_{2}\).

Fig. 9: Measured DC test data of 1T1R configuration where gate voltage of NMOS is fixed and the \(V_{in}\) is varied from \(0.8\,\mathrm{V}\) to \(1.2\,\mathrm{V}\). From \(0.8\,\mathrm{V}\) to \(0.9\,\mathrm{V}\), the LRS shows high variability and less stability. This is due to the SET threshold not being met. On the other hand, at higher SET voltages, the variation in resistance is lower with LRS. Most importantly the SET operation range is fixed at \(\sim 4.2\,\mathrm{k\Omega}\). It indicates that without a proper pulse shape, 1T1R is not functional for SET operation.
### _Resistance Variation at LRS_

Fig. 9 exhibits the impact of DC operation. For that test, ten 1T1R cells were taken under consideration at different SET voltages. A "KEITHLEY 2636A SYSTEM SourceMeter" is utilized to provide DC voltage for the SET operation at \(V_{in}\) and \(V_{g}\). Here the \(V_{g}\) is fixed at \(1.2\,\mathrm{V}\) and \(V_{in}\) is varied from \(0.8\,\mathrm{V}\) to \(1.2\,\mathrm{V}\). According to Fig. 9 the std. dev. of the resistance is very high from \(0.8\,\mathrm{V}\) to \(0.9\,\mathrm{V}\). In addition, the std. dev. is comparatively lower after \(0.9\,\mathrm{V}\). However, the SET resistance window is limited to a narrow region around \(\sim 4.2\,\mathrm{k\Omega}\), which is not a functional SET window for our targeted programming region (\(5\,\mathrm{k\Omega}\) to \(20\,\mathrm{k\Omega}\)). Due to the absence of proper pulse width, the 1T1R device is not functional for SET operation.

Fig. 10 shows the LRS variation and distribution at a low \(V_{in}\) from 38 experimental samples. According to Fig. 10, the resulting resistance when the SET voltage is varied from \(0.7\,\mathrm{V}\) to \(1.2\,\mathrm{V}\). The SET variation at LRS is drastically increased from \(0.7\,\mathrm{V}\) to \(0.9\,\mathrm{V}\). Fig. 10 also shows the std. dev. value at different \(V_{in}\) voltages during SET operation. The std. dev. value is significantly lowered at around \(0.8\,\mathrm{V}\)\(V_{g}\). In addition, at LRS the resistance shows less variability and more reliable programming opportunity. It can be said from Fig. 10, the LRS has a negligible variation for the SET operation in the range of \(5\,\mathrm{k\Omega}\) to \(20\,\mathrm{k\Omega}\).

### _Pulse Shape Effect Based on Measured Data_

A Keithley B1500A semiconductor parameter analyzer was utilized to provide the specific pulse widths to the devices. Twenty devices were measured for different SET voltages at various pulse widths. Fig. 11 (a) shows the pulse width effect at \(0.8\,\mathrm{V}\). Lower pulse width results in higher resistance after a SET operation. Conversely, a higher pulse width results in a lower final resistance after the SET operation. In addition, the SET resistance is not in our targeted LRS region for programming. Due to that, \(0.8\,\mathrm{V}\) as a SET voltage is not reliable with various pulse widths. Fig. 11 (b) exhibits the pulse shaping effect on the 1T1R devices at \(1.2\,\mathrm{V}\) for \(V_{in}\). Here the pulse width has less effect on the SET resistance. According to Fig. 6, there are minimal effects of pulse width on the 3T1R design. Thus, for the work shown in Fig. 11, the pulse width analysis is not considered for the 3T1R design. However, when compared to Fig. 11 (a) there are some similarities that can be observed between the relationship of resistance and pulse width with different \(V_{set}\) voltages. For instance, as the pulse width increases, the resistance decreases. This effect is less apparent for \(0.8\,\mathrm{V}\) since only a partial filament is formed due to the low \(SET\) voltage. It can also be seen that with a lower \(V_{set}\) the resulting resistance is higher overall.

### _Aging and Failure Effects on the Device_

Device failure was investigated in a previous paper on 1T1R devices with respect to voltage and endurance [30]. The paper showed that devices fail due to either current, voltage, or aging effects (endurance/cycling). If these elements are limited to certain ranges of resistance and a smaller difference between LRS and HRS is maintained, the ReRAM device can survive for a longer time. Thus, the main failure inducer is long-term switching/ endurance aging. It has been shown previously that devices can switch for over 100 million cycles. In addition, 40% of devices can manage 1 billion cycles at room temperature [30]. Another endurance test showed over 10 years of retention is possible at 125\({}^{\circ}\)C temperature [31]. Device failure mitigation can be addressed throughout testing through different schemes such as the co-optimization framework [32]. However, in this work device aging will be handled by adjusting the weight mapping between software to hardware based on the device's current performance.

## VI Software Model & Applications

### _Software Model_

A single-layer machine learning classification model can be explained as \(\sigma(WX+b)\) where \(\sigma\) is the activation function.

Fig. 11: Measured data of 20 1T1R configurations programmed with different pulse widths. (a) shows the pulse width variation for 1T1R device configuration at \(0.8\,\mathrm{V}\). Here the \(V_{g}\) is fixed at \(1.2\,\mathrm{V}\) and the \(V_{in}\) varied from lower to higher voltage pulse width. The pulse width is varied from \(100\,\mathrm{ns}\) to \(1\,\mathrm{ms}\). (b) illustrates the pulse width effect on 1T1R configuration at \(1.2\,\mathrm{V}\). Here, the pulse width variation shows a lower effect compared to the effect at \(0.8\,\mathrm{V}\).
The linear product (\((WX+b)\)) obtains non-linearity by the activation function which is required by the machine learning model. The dot product of weight matrix W and input vector X can be calculated using the memristive crossbar dot product engine. The size of the matrix, W is the number of input features, and a number of output classes. The bias term can be mapped as the fixed column currents independent of the input as it appears from the equation [33]. The output class is the index of the column having the largest current, \(class=argmax_{col}\sigma(column\_currents)\). This argmax function is non-differentiable and Therefore, the softmax function is used here as a pseudo replacement. The loss function used is the mean squared error of the actual class and model predicted class. In this paper, a software model is trained to determine the parameters of an abstract model where the weight values are floating point values. Later those values were mapped to the memristive conductances which were found from a Cadence Spectre simulation. A linear mapping strategy is followed to convert all the weights to memristive conductance values and all the bias terms to the bias current. For mapping, first of all, the weights were shifted to be positive values [33]. Then, the weights of range (\(W_{L},W_{H}\)) are mapped to the conductance range (\(G_{L},G_{H}\)). All transformations were offset by adding additional terms to the original bias current. If all the bias currents across columns are equal, then the bias term can be ignored and the linear product is the output current across the columns.

Four datasets, namely Iris, Wine, and Breast Cancer Wisconsin (Diagnostic) and banknote from the UCI repository [34] are employed for the purpose of classification in this study. To create input spikes, the data is one-hot encoded with 4 bins. For example, the iris dataset has 4 features and 4 bins for each class. Thus, the total number of features is 16. The dataset is split into 70% training data and 30% testing data. One of the advantages of one-hot encoding is that it returns a specific number of spikes (the number of features) for every data instance at all columns and therefore, a specific number of the memristor is READ for any data instance. This unique feature gives advantages to simplifying the model and the mapping to the hardware.

### _Network Architecture_

The network architecture consists of an input layer and an output layer, without any hidden layers. Initially, the trained network includes bias values. However, during the process of mapping to hardware, the bias values were adjusted to be equal. This eliminates the need for them to be represented in hardware, as detailed in [33]. TABLE II presents the models for the four different classifications. As an example, the iris dataset, which comprises 4 features, has each feature encoded with 4 bins, resulting in a total of 16 units in the input layer. Including the bias term, the input layer consists of 17 units. The number of units in the input layer is equivalent to the number of classes in the classification. The trainable parameters represent the parameters of the model that underwent training.

### _Results from the Software Model_

For mapping an abstract software model to the existing hardware design, a lookup table is required that provides the corresponding current value for all memristive conductances. In this work, two look-up tables are created for 1T1R and 3T1R, respectively, using the results from the Cadence Spectre simulation. In addition, the column current of the DPE is calculated using this look-up table. At the output, \(n\) current levels (\(I_{1},I_{2},....,I_{n}\)) need to be distinguishable in order to determine the column which has the maximum current. Otherwise, all current appears to be the same due to the limitations of current sensing. In this work, it is assumed that the ADC has \(50\,\mathrm{nA}\) current resolution. One of the limitations of analog DPE-based classification systems is the possibility of multiple columns sharing the maximum current. This is a limitation imposed by the ADC. In those cases, the classifier will take the class randomly from one of those columns.

The software model also behaves similarly. Table I shows the comparison of the DPE-based classification using 1T1R and 3T1R for four datasets. The validation metrics are training accuracy, testing accuracy, and mean energy required for the classification of a single sample. The mean energy is proportional to the size of the input vector and the memristive DPE size. Breast cancer has the largest DPE and therefore requires the largest energy among all four classification tasks. The testing accuracy degradation column shows the 3T1R-based DPE performs slightly worse in the wine dataset compared to 1T1R based DPE. But, the 3T1R has a low current range

\begin{table}
\begin{tabular}{|p{56.9pt}|p{56.9pt}|p{56.9pt}|p{56.9pt}|p{56.9pt}|} \hline Dataset & Number of Features & Units in Input Layer & Units in Output Layer, Number of class & Trainable parameters \\ \hline Iris & 4 & 17 & 3 & 51 \\ \hline Wine & 13 & 53 & 3 & 159 \\ \hline Breast Cancer Diagnostic & 30 & 121 & 2 & 242 \\ \hline Banknote & 4 & 17 & 2 & 34 \\ \hline \end{tabular}
\end{table} TABLE II: Architecture of the Network

\begin{table}
\begin{tabular}{|p{56.9pt}|p{56.9pt}|p{56.9pt}|p{56.9pt}|p{56.9pt}|p{56.9pt}|p{56.9pt}|p{56.9pt}|} \hline Dataset & \begin{tabular}{c} Training Acc. (1T1R), (\% ) \\ \end{tabular} & \begin{tabular}{c} Testing Acc. (1T1R), (\%) \\ (1T1R), (\%) \\ \end{tabular} & \begin{tabular}{c} Testing / READ \\ (5T1R), (\%) \\ \end{tabular} & \begin{tabular}{c} Training Acc. (3T1R), (\%) \\ \end{tabular} & \begin{tabular}{c} Testing Acc. (3T1R), (\%) \\ \end{tabular} & \begin{tabular}{c} Testing Acc. (3T1R), (\%) \\ (pJ) \\ \end{tabular} & \begin{tabular}{c} Energy (3T1R), (\%) \\ \end{tabular} & \begin{tabular}{c} Energy \\ (3T1R), (\%) \\ \end{tabular} & \begin{tabular}{c} Energy \\ (5) \\ \end{tabular} & 
\begin{tabular}{c} Improvement \\ (\%) \\ \end{tabular} \\ \hline Iris & 91.43 & 88.88 & 449.61 & 85.71 & 88.88 & 63.09 & 0 & \(\sim\)7.13x \\ \hline Wine & 96.77 & 85.18 & 1446.56 & 96.77 & 81.48 & 205.47 & \(\sim\)3.7 & \(\sim\)7.04x \\ \hline Breast Cancer & 98.24 & 93.56 & 2324 & 97.99 & 93.56 & 318.46 & 0 & \(\sim\)7.3x \\ \hline Banknote & 93.43 & 91.99 & 296.78 & 92.81 & 91.26 & 42.39 & \(\sim\)0.73 & \(\sim\)7x \\ \hline \end{tabular}
\end{table} TABLE I: PERFORMANCE EVALUATION BETWEEN 1T1R AND 3T1R
for \(5\,\mathrm{k}\Omega\) to \(20\,\mathrm{k}\Omega\) and therefore, suffers from current sensing limitations. A \(1\,\mathrm{\SIUnitSymbolMicro s}\) pulse is provided at the gate of MN1 with \(0.6\,\mathrm{V}\) amplitude. Hence, a READ current is calculated from the \(2^{nd}\) stage of the proposed 3T1R synapse. The percentage of samples in each dataset in which multiple columns have at or over the maximum current sensible is described next. For the Iris, Wine, and Breast Cancer Wisconsin (Diagnostic), and Banknote dataset, the percentage same current level for 3T1R was 24.44%, 11.11%, 0.58%, and 1.70% respectively. However, for the 1T1R these results are just 4.4%,0%, 0% and 0% for the same test. This limitation of 3T1R can be overcome by using an ADC with better current sensing capability. On the other hand, the energy is improved by around \(7\times\) when using 3T1R compared to 1T1R.

In addition, in TABLE I the testing dataset accuracy for the Wine dataset is 85.18% when the memristor crossbar is made by the 1T1R devices. The accuracy reduces by approximately 3.7% when 1T1R in the crossbar is replaced by 3T1R.

The 3T1R-based trained DPE model is shown in Fig. 12. The DPE model is just the resistance of the memristor which is shown as the color bar. In the color bar, the range 5-20 represents \(5\,\mathrm{k}\Omega\)-\(20\,\mathrm{k}\Omega\). Lastly, Fig. 13 shows the confusion matrix of the testing dataset for all four classifications. It is clear from the confusion matrix that all the models classify all the classes pretty well. Moreover, in this work, our targeted programming region is from \(5\,\mathrm{k}\Omega\) to \(20\,\mathrm{k}\Omega\). In the 3T1R, depending on the programming / SET voltage, sixteen different resistance levels are targeted. In prior work, it has been shown up to 16 levels of resistance can be achieved with our memristive device [30]. In the DPE configuration, if the array is small then the cumulative current in a column shows almost negligible degradation in precision. However, if the column is containing more than 16 synaptic units then the cumulative current shows saturation in the column current.

## VII Peripheral Circuitry

A CMOS digital-to-analog converter (DAC) is utilized for programming. The energy consumption of our DAC to program the synapse with 1V is \(0.311\,\mathrm{f}\mathrm{J}\). Here, \(1\,\mathrm{V}\) is the output of the DAC circuit from \(1.2\,\mathrm{V}\) as the supply voltage. Moreover, a Winner-Take-All (WTA) circuit is utilized to rank the column current from the cross-bar array. With a particular sample from the Wine dataset, the column current from each column is about \(11.2\,\mathrm{\SIUnitSymbolMicro A}\), \(11.5\,\mathrm{\SIUnitSymbolMicro A}\), and \(11.3\,\mathrm{\SIUnitSymbolMicro A}\) for \(Iout1\), \(Iout2\), and \(Iout3\) respectively. Our designed WTA circuit consumes \(0.607\,\mathrm{p}\mathrm{J}\) energy with \(1\,\mathrm{\SIUnitSymbolMicro s}\) read pulse to detect the maximum current from three columns. Three columns need only nine \(NMOS\) transistors to classify the maximum current. Hence, a sense amplifier is used to convert the analog value into a digital value with one bit per column.

## VIII Comparison with prior work

An analog implementation of a DPE can consume less power during each READ cycle compared to traditional memory like SRAM and DRAM [14, 15, 35]. According to TABLE III, in [1], authors utilized SRAM with 4-bit precision at \(45\,\mathrm{n}\mathrm{m}\) CMOS process to implement a DPE and it consumed \(120\,\mathrm{\SIUnitSymbolMicro A}\) for reading at \(0.4\,\mathrm{V}\). Whereas a memristive analog memory implementation is used to implement a DPE and it consumed only \(27.58\,\mathrm{\SIUnitSymbolMicro A}\) at \(2\,\mathrm{V}\)[36]. In our paper, two different approaches are observed for a DPE implementation. The 1T1R approach draws \(83.52\,\mathrm{\SIUnitSymbolMicro A}\) current at \(0.6\,\mathrm{V}\). On the other hand, the 3T1R approach shows, \(4.459\,\mathrm{\SIUnitSymbolMicro A}\) of READ current at \(0.6\,\mathrm{V}\). Our proposed 3T1R device shows about \(\sim\)26.91x and \(\sim\)6.19x READ current improvement compared to [1] and [36] respectively. In addition, the 3T1R approach can reduce \(\sim\)18.73x READ current compared to a 1T1R design. Another research group presents a mixed-signal synapse circuit

Fig. 12: Model of four classification tasks. A model shows the distribution of the memristor’s weight for different classification tasks such as (a) Iris, (b) Wine, (c) Breast Cancer, and (d) Banknote. The model adapts lower weight value more to ignore the sensitivity effects of HRS.

Fig. 13: Confusion matrix of four datasets are shown here. Four confusion matrices (a) Iris, (b) Wine, (c) Breast Cancer, (d) Banknote illustrate the prediction efficiency of the model. If the diagonal boxes contain a maximum number of rows, the model prediction is better. All confusion matrices show excellent prediction capability.
with 5-bit data precision [37]. The READ power consumption of this design is \(27.43\,\mathrm{\SIUnitSymbolMicro W}\), which is \(\sim\)5.15x higher than our 3T1R approach. Another memristive-based design draws \(14\,\mathrm{\SIUnitSymbolMicro W}\) READ power, which is \(\sim\)2.62x higher than our proposed 3T1R design [35]. Moreover, the 3T1R design consumes \(\sim\)9.37x lower READ power compared to the 1T1R design. A memristor based design with \(28\,\mathrm{nm}\) CMOS process shows \(17.8\,\mathrm{pJ}\) energy consumption [38] which has \(\sim\) 3.33x energy overhead compared to our 3T1R design. Moreover, the 3T1R design can save \(\sim\) 9.37x energy compared with the 1T1R design. However, according to Fig. 3 (c) and (d), 3T1R shows about 2x and 6x _SET_ current and power overhead compared to the 1T1R structure. This higher _SET_ current can be reduced by lowering the memristive device's overall _SET_ threshold and using a thin oxide transistor instead of a thick oxide transistor, which is targeted for future work. The overall area of a 3T1R synapse is almost 2.76x larger than a 1T1R synapse. However, the 3T1R design shows significant area improvement compared to prior work [37]. The area overhead of a 3T1R-based DPE can be optimized further by sharing the \(MP3\) for a whole column. In Fig. 7, each synapse utilizes it's own \(MP3\) transistor.

## IX Conclusion and future work

Array-based memristive memory for SNNs are power-hungry during READ cycles. They also show high sensitivity due to process variation in MOSFET fabrication and the inherent stochastic behavior of memristors. In this work, we leveraged a 3T1R design to achieve a reduction in READ current and process variation sensitivity. According to simulation results, \(\sim\)26.91x and \(\sim\)18.76x of the READ-out current reduction can be achieved as compared to the prior work and 1T1R approach respectively. In addition, both READ power and energy are saved by about 9.37x with the 3T1R device when compared with the 1T1R device. At the same time, the write variation is also reduced by targeting a programmable LRS, ranging from 5 k\(\Omega\) to 20 k\(\Omega\). This region was chosen since it contains the least variability in resistance during programming. Finally, hardware-realistic Cadence Spectre results were used to verify a software model for four different dataset classification tasks. Due to the small change in READ current across the resistance range of our 3T1R DPE, its precision is impacted. As a result, classification tasks show a slight decrease in testing accuracy compared to the 1T1R-based DPE. Overall, the proposed design is power efficient and reliable. For future work, the SET currents of the 3T1R will be optimized alongside further testing of our fabricated chip. At the same time, the output precision will be enhanced for the 3T1R cells. Optimized electrical processes such as write-read-verify and ultra-fast pulsing, pulses less than \(10\,\mathrm{ns}\), can be used to achieve more distinct resistance levels. Further analysis of scaling issues due to peripheral circuitry and interconnect distances will be taken under consideration. In addition, a super-resolution crossbar can be a potential candidate to explore and compare with our design [39, 40].
