Optimizing data-flow in Binary Neural Networks
Binary Neural Networks (BNNs) can significantly accelerate the inference time
of a neural network by replacing its expensive floating-point arithmetic with
bitwise operations. Most existing solutions, however, do not fully optimize
data flow through the BNN layers, and intermediate conversions from 1 to 16/32
bits often further hinder efficiency. We propose a novel training scheme that
can increase data flow and parallelism in the BNN pipeline; specifically, we
introduce a clipping block that decreases the data-width from 32 bits to 8.
Furthermore, we reduce the internal accumulator size of a binary layer, usually
kept using 32-bit to prevent data overflow without losing accuracy.
Additionally, we provide an optimization of the Batch Normalization layer that
both reduces latency and simplifies deployment. Finally, we present an
optimized implementation of the Binary Direct Convolution for ARM instruction
sets. Our experiments show a consistent improvement of the inference speed (up
to 1.91 and 2.73x compared to two state-of-the-art BNNs frameworks) with no
drop in accuracy for at least one full-precision model.
L. Vorabbi, D. Maltoni, S. Santi
# Optimizing data-flow in Binary Neural Networks

###### Abstract

Binary Neural Networks (BNNs) can significantly accelerate the inference time of a neural network by replacing its expensive floating-point arithmetic with bit-wise operations. Most existing solutions, however, do not fully optimize data flow through the BNN layers, and intermediate conversions from 1 to 16/32 bits often further hinder efficiency. We propose a novel training scheme that can increase data flow and parallelism in the BNN pipeline; specifically, we introduce a clipping block that decreases the data-width from 32 bits to 8. Furthermore, we reduce the internal accumulator size of a binary layer, usually kept using 32-bit to prevent data overflow without losing accuracy. Additionally, we provide an optimization of the Batch Normalization layer that both reduces latency and simplifies deployment. Finally, we present an optimized implementation of the Binary Direct Convolution for ARM instruction sets. Our experiments show a consistent improvement of the inference speed (up to \(\mathbf{1.91}\) and \(\mathbf{2.73\times}\) compared to two state-of-the-art BNNs frameworks) with no drop in accuracy for at least one full-precision model.

Lorenzo Vorabbi\({}^{*+}\), Davide Maltoni\({}^{+}\), Stefano Santi\({}^{*}\)

\({}^{*}\)Datalogic Labs

\({}^{*}\)University of Bologna, Department of Computer Science and Engineering (DISI)

## 1 Introduction

In the last decade deep neural networks (DNNs) have come to demonstrate high accuracy on many datasets like ImageNet, outperforming legacy methods and sometimes even human experts ([21], [9]). These improvements have been achieved by increasing the depth and complexity of the network, leading to intensive usage of computational resources and memory bandwidth. Large DNN models run smoothly on expensive GPU-based machines but cannot be easily deployed to edge devices (i.e., small mobile or IoT systems), which are typically more resource-constrained. Various techniques have been introduced to mitigate this problem, including network quantization, network pruning and efficient architecture design.

Recent work on quantization (e.g. [5, 11, 14, 17]) has shown that a DNN model can be even quantized to 1-bit (also known as binarization) thus achieving a remarkable speedup compared to the full precision network. The memory requirement of such a binarized DNN (BNN) is drastically reduced compared to a DNN of the same structure,
since a significant proportion of weights and activations can be represented by 1-bit, usually \(\{-1,+1\}\). In addition, high-precision multiply-and-accumulate operations can be replaced by faster XNOR and popcount operations.

However, the aggressive quantization can make BNN's less accurate than their full-precision counterparts. Some researchers showed that the performance loss often arises from the gradient mismatch problem caused by the non-differentiable binary activation function [14]. This non-differentiability of the quantization functions prevents gradient back-propagation through the quantization layer. Therefore, previous works used straight-through-estimator (STE) to approximate the gradient on non-differentiable layers [11].

Furthermore, to prevent that the binarization of weights and activations leads to feature maps of lower quality and capacity, a combination of binary and floating-point layers is usually adopted. Unfortunately, each time a binary layer is connected to a floating-point one, the efficiency of the pipeline is compromised by input/output layer data type conversion. In addition, the internal parallelism of a binary layer depends on the encoding of the accumulator, which is often maintained at 32 bits to prevent overflow. In this paper we present several optimizations that allow training a BNN with an inter-layer data width of 8 bits. Most prior work on BNN's emphasize overall network accuracy; in contrast, our aim is to preserve initial accuracy while improving efficiency. Our contributions (graphically highlighted in Figure 0(i) and 0(ii)) can be summarized as follows:

* a novel training scheme is proposed to improve the data-flow in the BNN pipeline (Section 3.1); specifically, we introduce a clipping block to shrink the data width from 32 to 8 bits while simultaneously reducing the internal accumulator size.
* we provide (Section 3.2) an optimization of the Batch Normalization layer when executed after a binary operation that decreases latency and simplifies deployment.
* we optimize the Binary Direct Convolution method for ARM instruction sets (Section 3.3).

To prove the effectiveness of the proposed optimizations in Section 4 we provide experimental evaluations that show's the speed-up relative to state-of-the-art BNN engines like LCE [1] and DaBNN [24].

## 2 Related Work

BNNs were first introduced in [5], whose authors established an end-to-end gradient back-propagation framework for training the binary weights and activations. They achieved good success on small classification datasets including CIFAR10 and MNIST, but encountered a severe accuracy drop on ImageNet.

Many subsequent studies focused on enhancing BNN accuracy. The authors of [19] proposed XNOR-Net, subsequently improved in [4], where real-valued scaling factors are used to multiply the binary weight kernels, and this methodology then became a
representative binarization approach to bridge the gap between BNN's and their real-valued counterparts. The Bi-Real Net [14] added shortcuts to propagate values along the feature maps, which further boosted the top-1 accuracy on ImageNet; nevertheless, the model still relies on 32-bit floating point to execute batch normalization and addition operator (as shown in Fig. 1ii).

One of the major weaknesses of BNN's is the gradient approximation by the STE binarization function [5]. In fact, STE computes the derivative of sign as if the binary operation was a linear function, as reported in the following formula :

\[\begin{split} A(x)=\max(-1,\min(1,x))\\ STE(x)=A^{\prime}(x)=[-1\leq x\leq 1]\end{split} \tag{1}\]

This implementation of STE cancels the gradients when the inputs get too large [11]. STE provides a coarse approximation of the gradient that inevitably affects the testing accuracy of the BNN. To address this issue, other recent studies tried to improve the performance of BNNs by adopting a proper optimization method for the quantization. Inspired by STE, many works update the parameters approximately introducing auxiliary loss functions; PCNN [8] proposes a projection convolutional network with a discrete back propagation via projection. IR-Net [18] introduces a new parametrized binarization function to minimize both quantization error and information loss of parameters by balanced and standardized weights in forward propagation. RBNN [13] proposes a training-aware approximation of the sign function for gradient backpropagation. Similarly, AdamBNN [15] analyzes the influence of Adam and weight decay when training BNNs, showing that the regularization effect of second-order momentum in Adam is crucial to revitalize dead weights.

To close the accuracy gap with real-valued networks other works propose to add a distribution loss or special regularization to the overall loss function. Real-to-Bin [17] makes use of an additional loss function by matching the spatial attention maps computed at the output of the binary and real-valued convolutions. ReActNet [16] adopts a distributional loss to further enforce the binary network to learn output distributions similar to those of a real-valued network.

Recently, some works proposed new network topology structures to increase BNN performance. High-Capacity Expert Binary Networks [3] addresses the information bottleneck in binary networks by introducing an efficient width expansion mechanism which keeps the binary operations within the same budget. RepBNN [20] proposes a new replaceable convolution module which enhances feature maps by replicating input or output along channel dimension without extra cost with respect to the number of parameters and convolutional computation.

8-bit quantization of weights and activations in a neural network is a well-known topic, as reported in [12]. In BNNs, 8-bit quantization is not widespread and the Batch Normalization (BN) layer is usually executed in floating point arithmetic using off-the-shelf inference engines [24, 1]. In contrast, we show that, the quantization of BN layer and the reduced width size of the accumulator inside the binary operator, can lead to substantial speed up of the binary layer (binary operation + BN).

In contrast with previous works [19, 4, 14, 16], where binary convolution is used with scaling factors, we directly binarize input activations and weights, then we quantize BN layer avoiding to execute floating-point arithmetic. When scaling factor is
applied only to the weights and BN layer is inserted immediately after binary operation, the scaling factor multiplication can be absorbed by BN multiplication while in the previously cited works this operation is executed in floating point. Furthermore, the adoption of learnable biases (_ReAct Sign_), as adopted in ReactNet [16], during inputs binarization further increases the usage of floating-point computation.

Besides many efforts to develop more efficient and accurate architectures, a few works have provided benchmarks on real devices such as ARM processors. Based on the analysis provided in [1], the fastest inference engines for binary neural networks, with proven benchmarks (Section 4 of [1]), are LCE and DaBNN.

## 3 Data-Flow Optimizations

As illustrated in Figs. 0(i) and 0(ii) (a), the most commonly used BNN architectures (e.g., VGG and ResNet) have four essential blocks in each convolution/fully-connected (CONV/FC) layer: sign (binarization), XNOR, popcount and Batch Normalization (BN). Since the weights, inputs and outputs are all binary, the traditional multiply-and-accumulate operation is replaced by XNOR and bit counting (i.e., popcount). XNOR and popcount are usually fused to improve efficiency. The use of Batch Normalization after each binarized layer is very important in BNN's because it makes the optimization landscape significantly smoother; this smoothness induces a more predictive and stable behavior of the gradients, allowing for faster training. Figures 0(i) and 0(i) (b and c) point out our proposed BNN optimizations during training and inference. Before discussing them in detail, we show the data-flow bottlenecks that affect existing solutions and then describe how to reduce them.

In Figs. 1(i) and 1(ii) we report an example of binary convolutional layer outputs for a VGG and a ResNet model. The ranges of activation values after popcount (green

Figure 1: a) Standard BNN blocks used in [19] and [14]. b) BNN block with output convolution clipping used during training. c) Optimized BNN block adopted during inference. Popcount operation is performed using saturation arithmetic in order to keep the data width to 8 bits at inference time. BN is replaced in by a comparison in case i, while in ii BN is 8-bit quantized.
histograms) exceed the interval \([-128;+127]\)1, so adopting an 8-bit encoding would lead to overflow. To prevent such a data loss, most of the existing BNN frameworks (including [1, 24]) encode such data in 32-bit floating point. On the other hand, the ranges of values after BN (red histograms in Fig. 2) are more limited.

Footnote 1: We actually consider the symmetric quantization interval \([-127;+127]\) because this choice enables a substantial optimization opportunity, as reported in Appendix B of [12].

In this paper, we propose to accumulate the popcount output with 8-bit integers (using saturation arithmetic) through a two-stages training procedure, which is designed to preserve model accuracy. In the next subsection we show how to apply this technique to VGG and ResNet models.

### Two-stage Clipping

Our training procedure selectively executes or skips a clipping operation at each binary layer (row \(b\) of Figs. 0(i) and 0(ii), blue blocks). A two-stage training method is introduced to avoid accuracy loss when clipping is enabled: during a first warm-up stage, the model is trained without any range constraints, while in the second stage (details are reported in Algorithm 1) the network is trained with the clipping block enabled. Based on the high accuracy reached at the end of the first training stage, in the second training stage the model better tolerates clipping 8-bit quantization; we experimentally found that this approach preserves the accuracy of a model that does not contain clipping.

### Batch Normalization Optimization

The BN layers after the clipping are also optimized/8-bit quantized to further increase the data-flow of the inference pipeline. The Batch Normalization layer scales and shifts the output of the CONV/FC layer as follows:

\[BN\left(F_{out}^{l}\right)=\gamma\frac{F_{out}^{l}-\mu}{\sigma}+\beta \tag{2}\]

Figure 2: Example of output distributions after binary convolution. i, refers to a VGG style network while ii to a ResNet architecture. Green shows the distribution before the BN layer and red afterward.
where \(\gamma,\ \mu,\ \sigma\ and\ \beta\) are learned parameters and \(F_{out}^{l}\) is the ouput feature of layer \(l\) that is the input of BN function.

The BN optimization depends on the network model: VGG or ResNet. In both cases we show that it is possible to keep the inter-layer data type to 8-bit with appropriate changes to the binary layer structure.

* **VGG style block**. When the BN layer is inserted in a pipeline similar to Fig. 1i, where the following block is still binary, the BN operation can be simplified replacing multiplication and division in Eq. 2 with a simple comparison with a threshold \(\tau\). The simplification of Eq. 2 leads to: \[sign\left(BN\left(F_{out}^{l}\right)\right)=\begin{cases}+1&if\ \ BN\left(F_{out}^{l}\right)\geq 0\\ -1&otherwise\end{cases}\] \[\gamma\frac{F_{out}^{l}-\mu}{\sigma}+\beta\geq 0\Rightarrow\tau\doteq \mu-\beta\frac{\sigma}{\gamma}\] (3) \[sign\left(BN\left(F_{out}^{l}\right)\right)=\begin{cases}+1\ if\ F_{out}^{l} \geq\tau\ else\ -1\ \left(when\ \frac{\gamma}{\sigma}\geq 0\right)\\ -1\ if\ F_{out}^{l}\leq\tau\ else\ +1\ \left(when\ \frac{\gamma}{\sigma}<0\right) \end{cases}\] The threshold \(\tau\) of Eq. 3 can be computed offline and easily quantized to 8
bits in order to exploit the output features of layer \(l\). Therefore, when multiple BNN modules are stacked, Batch Normalization can be replaced by a threshold comparison according to Eq. 3. Even if BN can be replaced with a threshold comparison, 8-bit data flow is still important because it allows to accumulate the binary xnor and popcount operations direclty on 8-bit using saturation arithmetic instead of the standard 32-bit.
* **ResNet style block**. When a BNN block is placed in a ResNet style pipeline, followed by an addition operator, Fig. 1ii, the BN layer can be executed with both scaling and bias factors to 8 bits. As reported in Fig. 3, the internal data representation of a quantized BN layer is expanded to 16-bit to preserve accuracy during quantization but the input/output data type still remains within 8 bits. The iterative quantization procedure we adopted is symmetric and keeps unaltered the zero point representation, as reported in Algorithm 2. The procedure iterates over the BN floating-point layers and, for each one: computes the quantization scale; quantizes; freezes the weights; and retrains the remaining layers.

### Binary Direct Convolution optimization on ARM

The GEMM (GEneral Matrix Multiplication) is a widely adopted method to efficiently implement convolutions. However, as reported in [25], the GEMM approach increases the memory footprint of the model, making a model's port to an embedded device more difficult. Furthermore, GEMM routines are not always optimized for convolutions on ARM devices, in particular ARMv8 (64-bit ARM architecture) and its relevant operations such as _vocount_ and _addv_.

_vocount_ takes an N-byte vector as input and outputs an N-byte vector containing the number of \(1s\) present in each input byte. _addv_ takes an N-byte vector as input and outputs the sum of the N bytes as one single value.

Figure 3: **a)**: 8-bit symmetric quantization procedure that reserves fractional/integer bits based on the range of input 32-bit floating point values. **b)**: implementation of the BN layer with 8-bit quantization using an internal 16-bit representation to preserve accuracy.
Inspired by [25] and [24] we propose a hybrid direct binary convolution (see Fig. 4) that uses both the _addv_ instruction and the common _add_ operations. The binary convolution is usually composed of three different steps: binarization/bit-packing, padding and convolution. [24], executes these steps in a sequential way. In contrast, we devise a more cache-friendly approach that collapses the previous steps in one operation executed with tiling. We also devise a different kernel memory layout that better fits ARMv8 SIMD processing instructions, as illustrated in Fig. 4.

The implementation details of our binary convolution are reported in Fig. 5. The operation _Extract sign bit_ executes the binarization, bit-packing and padding. Then,
the (bit-wise) XNOR output is consumed by the popcount operation (_vcnt 8-bit wise_,

Figure 4: The \(7\times 7\) input image with \(3\) different channels (denoted by color) is convolved with two separate kernels to obtain a \(5\times 5\) output with two output channels. To better exploit the SIMD 128-bit registers a different memory layout for kernel is devised: \([out_{channels},\ H_{filter},\ W_{filter},\ in_{channels}]\).

Figure 5: The \(3\times 3\times 128\) input patch is convolved (XNOR + popcount) with one kernel through the Extract sign bit, XNOR and then popcount operations. Popcount is performed using _vcnt_, summing in pairs the _vcnt_ output and the last step uses the _addv_ operation. TL (top left), TM (top middle), TR (top right) and ML (middle left) indicate the position of elements inside the \(3\times 3\) patch.
_add_ and _addv_). On the ARM architecture, the latter can be implemented with _vcount_ and a sequence of additions (_addv_ instructions). We decided to implement several pairwise additions and only a final _addv_ instruction (which is more expensive). The entire convolution process does not provide intermediate outputs but instead processes the input data as a whole. It is worth noting that the clipping operation can be obtained for free on ARM devices by exploiting its saturation arithmetic; all the addition operations (_add_ and _addv_) can be limited to the fixed range \([-127;+127]\) by simply adding the postfix \(q\) to the operations and executing \(\max\) to avoid \(-128\) value.

## 4 Experimental Results

In this section, we first evaluate the efficiency result of our approach compared to the state-of-art BNN frameworks such as LCE and DaBNN; the comparison is carried out on real hardware devices like Raspberry Pi Model 3B and 4B with 64-bit OS. Then, we present various accuracy benchmarks of the proposed two-stage training procedure focusing on CIFAR-10, SVHN and ImageNet, and to two different architectures: VGG and Resnet-18.

### Efficiency Analysis

To validate the efficiency of our method we focused on the convolution macro-block (to extend the results reported in [1] also to Raspberry Pi 3) of Fig. 1 and compared the efficiency of the proposed approach with LCE and DaBNN, which, to the best of our knowledge, are the fastest inference engines for binary neural networks.

Our assessment was performed on ARMv8 platforms, Raspberry Pi 3B and 4B. We implemented, differently from our predecessors, the convolution operation using ARM NEON _intrinsics_ instead of inline assembly. Intrisics allow to produce code easier to maintain and automatically fit both ARMv7 and ARMv8 platforms without losing appreciable performance compared to pure assembly code. In Fig. 6 we compare implementations on targets Rpi 3B and 4B. Our solution shows a clear performance improvement for single binarized convolutions for all kernels and, including all the optimizations introduced in Section 3, accelerates binary convolution up to \(1.91\) and \(2.73\times\) compared to LCE and DaBNN with an average improvements of \(1.46\) and \(1.61\times\) respectively.

### Accuracy Analysis

We evaluated two VGG-style networks (VGG-11 and VGG-Small) and a ResNet-18 for CIFAR-10 and SVHN. VGG-11 [22] and VGG-Small [23] are both high-capacity networks for classification. Pre-trained binary models (BinaryResNetE18 and BinaryDenseNet28) were adopted to evaluate the accuracy on ImageNet.

**Results on CIFAR10 and SVHN**. For CIFAR10 the RGB images are scaled to the interval \([-1.0;+1.0]\) and the following data augmentation was used: zero padding of 4 pixels for each side, a random \(32\times 32\) crop and a random horizontal flip. No augmentation is used at test time. The models have been trained for 140 epochs.
On SVHN the input images are scaled to the interval \([-1.0;+1.0]\) and the following data augmentation procedure is used: random rotation (\(\pm 8\) degrees), zoom (\([0.95,1.05]\)), random shift (\([0;10]\)) and random shear (\([0;0.15]\)). The models have been trained for 70 epochs.

All the networks have been trained using the same training procedure without adopting additional distillation losses to further improve accuracy of BNN models.

The accuracy achieved by the models is reported in Table 1 showing that the clip operation does not substantially affect the overall accuracy and the two-stage clipping allows to preserve the original accuracy. Figs. 7 and 8 show the training and validation curves on CIFAR10 and SVHN; we can note that a limited number of epochs is necessary during the second training stage to recover accuracy.

Figure 6: Latency evaluation of our method compared to DaBNN and LCE on Raspberry Pi 3B (i) and 4B (ii) devices.
Figure 7: Training loss and testing accuracy curves for VGG11 and VGGSmall on CIFAR10 and SVHN of the first and second training stages.
Figure 8: Training loss and testing accuracy curves for ResNet-18 on CIFAR10 and SVHN of the first and second training stages.
**Results on ImageNet**. Tests were performed by using pre-trained binary versions of ResNet18 and DenseNet28 [2] taken from _zoo literature of Plumerai_2. Each BNN module (refer to Fig. 1) has been modified according to Fig. 1ii. Residual blocks seem to be more robust to clipping compared to VGG style blocks (Results are in Table 2).

Footnote 2: [https://docs.larq.dev/zoo/api/literature/](https://docs.larq.dev/zoo/api/literature/)

## 5 Conclusion

This paper introduced several optimization in the BNN data-flow that together achieve a speed-up of \(\mathbf{1.91}\) and \(\mathbf{2.73\times}\) compared to state-of-the-art BNNs frameworks, without any accuracy loss for at least one full-precision model. In the future, we intend to investigate: (i) the application of similar optimization techniques to ternary networks, which naturally get higher accuracies; (ii) the simplification of the training procedure, possibly collapsing it to a single stage to further reduce training time and complexity.

\begin{table}
\begin{tabular}{c c c c c} \hline Method & Topology & Bit-width & CIFAR10 \% & SVHN \% \\ \hline \hline BNN [5] & VGGSmall [23] & 32 FP & 93.8 & 96.5 \\ Main/Subs. Net. & VGG11 [22] & 32 FP & 83.8 & - \\ ResNet-18 [18] & ResNet-18 & 32 FP & 93.0 & 97.3 \\ \hline BNN & VGGSmall & 1-bit & 89.9 & 96.5 \\ XNOR-Net [19] & VGGSmall & 1-bit & 82.0 & 96.5 \\ Bop [10] & VGGSmall & 1-bit & 91.3 & - \\ BNN-DL [6] & VGGSmall & 1-bit & 89.9 & 97.2 \\ IR-Net [7] & VGGSmall & 1-bit & 90.4 & - \\ Main/Subs. Net. & VGG11 & 1-bit & 82.0 & - \\ Bi-Real Net [14] & ResNet-18 & 1-bit & 89.3 & 94.7 \\ ReActNet [16] & ResNet-18 & 1-bit & 91.5 & 95.7 \\ \hline
**ours** & VGGSmall & 1-bit & 88.8 & 96.1 \\
**ours** & VGG11 & 1-bit & **83.7** & 95.5 \\
**ours** & ResNet-18 & 1-bit & 90.3 & 95.3 \\ \end{tabular}
\end{table}
Table 1: Accuracy comparison (top1) of our method with SOTA on CIFAR10 and SVHN.

\begin{table}
\begin{tabular}{c c c c c} \hline Method & Topology & Bit-width & top1 \% & top5 \% \\ \hline XNOR-Net [19] & ResNet-18 & 1-bit & 51.2 & 73.2 \\ Bi-Real Net [14] & ResNet-18 & 1-bit & 56.4 & 79.5 \\ BinaryResNetE18 [2] & ResNet-18 & 1-bit & 58.1 & 80.6 \\ BinaryDenseNet28 [2] & DenseNet-28 & 1-bit & 60.7 & 82.4 \\ \hline
**ours** & ResNet-18 & 1-bit & 58.1 & 80.6 \\
**ours** & DenseNet-28 & 1-bit & 60.7 & 82.4 \\ \end{tabular}
\end{table}
Table 2: Accuracy comparison of our method with SOTA on ImageNet.