CktGNN: Circuit Graph Neural Network for Electronic Design Automation
The electronic design automation of analog circuits has been a longstanding
challenge in the integrated circuit field due to the huge design space and
complex design trade-offs among circuit specifications. In the past decades,
intensive research efforts have mostly been paid to automate the transistor
sizing with a given circuit topology. By recognizing the graph nature of
circuits, this paper presents a Circuit Graph Neural Network (CktGNN) that
simultaneously automates the circuit topology generation and device sizing
based on the encoder-dependent optimization subroutines. Particularly, CktGNN
encodes circuit graphs using a two-level GNN framework (of nested GNN) where
circuits are represented as combinations of subgraphs in a known subgraph
basis. In this way, it significantly improves design efficiency by reducing the
number of subgraphs to perform message passing. Nonetheless, another critical
roadblock to advancing learning-assisted circuit design automation is a lack of
public benchmarks to perform canonical assessment and reproducible research. To
tackle the challenge, we introduce Open Circuit Benchmark (OCB), an
open-sourced dataset that contains $10$K distinct operational amplifiers with
carefully-extracted circuit specifications. OCB is also equipped with
communicative circuit generation and evaluation capabilities such that it can
help to generalize CktGNN to design various analog circuits by producing
corresponding datasets. Experiments on OCB show the extraordinary advantages of
CktGNN through representation-based optimization frameworks over other recent
powerful GNN baselines and human experts' manual designs. Our work paves the
way toward a learning-based open-sourced design automation for analog circuits.
Our source code is available at \url{https://github.com/zehao-dong/CktGNN}.
Zehao Dong, Weidong Cao, Muhan Zhang, Dacheng Tao, Yixin Chen, Xuan Zhang
# CktGNN: Circuit Graph Neural Network for Electronic Design Automation

###### Abstract

The electronic design automation of analog circuits has been a longstanding challenge in the integrated circuit field due to the huge design space and complex design trade-offs among circuit specifications. In the past decades, intensive research efforts have mostly been paid to automate the transistor sizing with a given circuit topology. By recognizing the graph nature of circuits, this paper presents a Circuit Graph Neural Network (CktGNN) that simultaneously automates the circuit topology generation and device sizing based on the encoder-dependent optimization subroutines. Particularly, CktGNN encodes circuit graphs using a two-level GNN framework (of nested GNN) where circuits are represented as combinations of subgraphs in a known subgraph basis. In this way, it significantly improves design efficiency by reducing the number of subgraphs to perform message passing. Nonetheless, another critical roadblock to advancing learning-assisted circuit design automation is a lack of public benchmarks to perform canonical assessment and reproducible research. To tackle the challenge, we introduce Open Circuit Benchmark (OCB), an open-sourced dataset that contains \(10\)K distinct operational amplifiers with carefully-extracted circuit specifications. OCB is also equipped with communicative circuit generation and evaluation capabilities such that it can help to generalize CktGNN to design various analog circuits by producing corresponding datasets. Experiments on OCB show the extraordinary advantages of CktGNN through representation-based optimization frameworks over other recent powerful GNN baselines and human experts' manual designs. Our work paves the way toward a learning-based open-sourced design automation for analog circuits. Our source code is available at [https://github.com/zehao-dong/CktGNN](https://github.com/zehao-dong/CktGNN).

## 1 Introduction

Graphs are ubiquitous to model relational data across disciplines (Gilmer et al., 2017; Duvenaud et al., 2015; Dong et al., 2021). Graph neural networks (GNNs) (Kipf and Welling, 2016; Xu et al., 2019; Velickovic et al., 2018; You et al., 2018; Scarselli et al., 2008) have been the de facto standard for representation learning over graph-structured data due to the superior expressiveness and flexibility. In contrast to heuristics using hand-crafted node features (Kriege et al., 2020) and non-parameterized graph kernels (Vishwanathan et al., 2010; Shervashidze et al., 2009; Borgwardt and Kriegel, 2005), GNNs incorporate both graph topologies and node features to produce the node/graph-level embeddings by leveraging inductive bias in graphs, which have been extensively used for node/graph classification (Hamilton et al., 2017; Zhang et al., 2018), graph decoding (Dong et al., 2022; Li et al., 2018), link prediction (Zhang and Chen, 2018), and etc. Recent successes in GNNs have boosted the requirement for benchmarks to properly evaluate and compare the performance of different GNN architectures. Numerous efforts have been made to produce benchmarks of various graph-structured data. Open Graph Benchmark (OGB) (Hu et al., 2020) introduces a collection of realistic and diverse graph datasets for real-world applications including molecular networks, citation networks,
source code networks, user-product networks, etc. NAS-Bench-\(101\)(Ying et al., 2019) and NAS-Bench-\(301\)(Zela et al., 2022) create directed acyclic graph datasets for surrogate neural architecture search (Elsken et al., 2019; Wen et al., 2020). These benchmarks efficiently facilitate substantial and reproducible research, thereby advancing the study of graph representation learning.

Analog circuits, an important type of integrated circuit (IC), are another essential graph modality (directed acyclic graphs, i.e., DAGs). However, since the advent of ICs, labor-intensive manual efforts dominate the analog circuit design process, which is quite time-consuming and cost-ineffective. This problem is further exacerbated by continuous technology scaling where the feature size of transistor devices keeps shrinking and invalidates designs built with older technology. Automated analog circuit design frameworks are thus highly in demand. Dominant representation-based approaches (Liu et al., 2021; Wang et al., 2020; Cao et al., 2022; Zhang et al., 2019) have recently been developed for analog circuit design automation. Specifically, they optimize device parameters to fulfill desired circuit specifications with a given circuit topology. Typically, GNNs are applied to encode nodes' embeddings from circuit device features based on the fixed topology, where black-box optimization techniques such as reinforcement learning (Zoph & Le, 2016) and Bayesian Optimization (Kandasamy et al., 2018) are used to optimize parameterized networks for automated searching of device parameters. While these methods promisingly outperform traditional heuristics (Liu et al., 2017) in node feature sizing (i.e., device sizing), they are not targeting the circuit topology optimization/generation, which, however, constitutes the most critical and challenging task in analog circuit design.

In analogy to neural architecture search (NAS), we propose to encode analog circuits into continuous vectorial space to optimize both the topology and node features. Due to the DAG essence of analog circuits, recent DAG encoders for computation graph optimization tasks are applicable to circuit encoding. However, GRU-based DAG encoders (D-VAE (Zhang et al., 2019)) and DAGNN (Thost & Chen, 2021) use shallow layers to encode computation defined by DAGs, which is insufficient to capture contextualized information in circuits. Transformer-based DAG encoder (Dong et al., 2022), however, encodes DAG structures instead of computations. Consequently, we introduce Circuit Graph neural Network (CktGNN) to address the above issues. Particularly, CktGNN follows the nested GNN (NGNN) framework (Zhang & Li, 2021), which represents a graph with rooted subgraphs around nodes and implements message passing between nodes with each node representation encoding the subgraph around it. The core difference is that CktGNN does not extract subgraphs around each node. Instead, a subgraph basis is formulated in advance, and **each circuit is modeled as a DAG \(G\) where each node represents a subgraph in the basis**. Then CktGNN uses two-level GNNs to encode a circuit: the inner GNNs independently learn the representation of each subgraph as node embedding, and the outer GNN further performs directed message passing with learned node embeddings to learn a representation for the entire graph. The inner GNNs enable CktGNN to stack multiple message passing iterations to increase the expressiveness and parallelizability, while the outer directed message passing operation empowers CktGNN to encode computation of circuits (i.e. circuit performance).

Nonetheless, another critical barrier to advancing automated circuit design is the lack of public benchmarks for sound empirical evaluations. Researches in the area are hard to be reproduced due to the non-unique simulation processes on different circuit simulators and different search space design. To ameliorate the issue, we introduce Open Circuit Benchmark (OCB), the first open graph dataset for optimizing both analog circuit topologies and device parameters, which is a good supplement to the growing open-source research in the electronic design automation (EDA) community for IC (Chai et al., 2022; Hakhamaneshi et al., 2022). OCB contains \(10\)K distinct operational amplifiers (circuits) whose topologies are modeled as graphs and performance metrics are carefully extracted from circuit simulators. Therefore, the EDA research can be conducted via querying OCB without notoriously tedious circuit reconstructions and simulation processes on the simulator. In addition, we will open-source codes of the communicative circuit generation and evaluation processes to facilitate further research by producing datasets with arbitrary sizes and various analog circuits. The OCB dataset is also going to be uploaded to OGB to augment the graph machine learning research.

The key contributions in this paper are: 1) we propose a novel two-level GNN, CktGNN, to encode circuits with deep contextualized information, and show that our GNN framework with a pre-designed subgraph basis can effectively increase the expressiveness and reduce the design space of a very challenging problem-circuit topology generation; 2) we introduce the first circuit benchmark dataset OCB with open-source codes, which can serve as an indispensable tool to advance research in EDA; 3) experimental results on OCB show that CktGNN not only outperforms competitive GNN baselines but also produces high-competitive operational amplifiers compared to human experts' designs.
## 2 Related Works

### Graph Neural Networks

**GNNs for DAGs** Directed acyclic graphs (DAGs) are another ubiquitous graph modality in the real world. Instead of implementing message passing across all nodes simultaneously, DAG GNNs (encoders) such as D-VAE (Zhang et al., 2019) and DAGNN (Thost and Chen, 2021) sequentially encode nodes following the topological order. Message passing order thus respects the computation dependency defined by DAGs. Similarly, S-VAE (Bowman et al., 2016) represents DAGs as sequences of node strings of the node type and adjacency vector of each node and then applies a GRU-based RNN to the topologically sorted sequence to learn the DAG representation. To improve the encoding efficiency, PACE (Dong et al., 2022) encodes the node orders in the positional encoding and processes nodes simultaneously under a Transformer (Vaswani et al., 2017) architecture.

### Automated Analog Circuit Design

**Design Automation Methods for Device Sizing** Intensive research efforts have been paid in the past decades to automate the analog circuit design at the pre-layout level, i.e., finding the optimal device parameters to achieve the desired circuit specifications. Early explorations focus on optimization-based methods, including Bayesian Optimization (Lyu et al., 2018), Geometric Programming (Colleran et al., 2003), and Genetic Algorithms (Liu et al., 2009). Recently, learning-based methods such as supervised learning methods (Zhang et al., 2019) and reinforcement learning methods (Wang et al., 2020; Li et al., 2021; Cao et al., 2022;b) have emerged as promising alternatives. Supervised learning methods aim to learn the underlying static mapping relationship between the device parameters and circuit specifications. Reinforcement learning methods, on the other hand, endeavor to find a dynamic programming policy to update device parameters in an action space according to the observations from the state space of the given circuit. Despite their great promise, all these prior arts have been limited to optimizing the device parameters with a given analog circuit topology. There are only a few efforts (e.g., Genetic Algorithms (Das and Vemuri, 2007)) to tackle another very challenging yet more important problem, i.e, circuit topology synthesis. These works leverage genetic operations such as crossover and mutation to randomly generate circuit topologies and do not sufficiently incorporate practical constraints from feasible circuit topologies into the generation process. Therefore, most of the generated topologies are often non-functional and ill-posed. Conventionally, a newly useful analog circuit topology is manually invented by human experts who have rich domain knowledge within several weeks or months. Our work focuses on efficiently and accurately automating circuit topology generation, based on which the device parameters for the circuit topology are further optimized.

**Graph Learning for Analog Circuit Design Automation** With the increasing popularity of GNNs in various domains, researchers have recently applied GNNs to model circuit structures as a circuit topology resembles a graph very much. Given a circuit structure, the devices in the circuit can be treated as graph vertices, and the electrical connections between devices can be abstracted as edges between vertices. Inspired by this homogeneity between the circuit topology and graph, several prior arts have explored GNNs to automate the device sizing for analog circuits. A supervised learning method (Zhang et al., 2019) is applied to learn the geometric parameters of passive devices with a customized circuit-topology-based GNN. And reinforcement learning-based methods (Wang et al., 2020; Cao et al., 2022) propose circuit-topology-based policy networks to search for optimal device parameters to fulfill desired circuit specifications. Distinctive from these prior arts, our work harnesses a two-level GNN encoder to simultaneously optimize circuit topologies and device features.

## 3 Circuit Graph Neural Network

In this section, we introduce the proposed CktGNN model constructed upon a two-level GNN framework with a subgraph basis to reduce the topology search space for the downstream optimization algorithm. We consider the graph-level learning task. Given a graph \(\mathcal{G}=(V,E)\), where \(V=\{1,2,...,n\}\) is the node set with \(|V|=n\) and \(E\in V\times V\) is the edge set. For each node \(i\) in a graph \(\mathcal{G}\), we let \(\mathcal{N}(v)=\{u\in V|(u,v)\in E\}\) denote the set of neighboring nodes of \(v\).
### Two-level GNN Framework with a Subgraph Basis

Most undirected GNNs follow the message passing framework that iteratively updates the nodes' representation by propagating information from the neighborhood into the center node. Let \(h_{v}^{t}\) denote the representation of \(v\) at time stamp \(t\), the message passing framework is given by:

\[a_{v}^{t+1}=\mathcal{A}(\{h_{u}^{t}|(u,v)\in E\})\ \ h_{v}^{t+1}=\mathcal{U}(h_{v}^{t},a_{v}^{t+1}) \tag{1}\]

Here, \(\mathcal{A}\) is an aggregation function on the multiset of representations of nodes in \(\mathcal{N}(v)\), and \(\mathcal{U}\) is an update function. Given an undirected graph \(G\), GNNs perform the message passing over all nodes simultaneously. For a DAG \(G\), the message passing progresses following the dependency of nodes in DAG \(G\). That is, a node \(v\)'s representation is not updated until all of its predecessors are processed.

It has been shown that the message passing scheme mimics the 1-dimensional Weisfeiler-Lehman (1-WL) algorithm (Leman and Weisfeiler, 1968). Then, the learned node representation encodes a rooted subtree around each node. And GNNs exploit the homophily as a strong inductive bias in graph learning tasks, where graphs with common substructures will have similar predictions. However, encoding rooted subtrees limits the representation ability, and the expressive power of GNNs is upper-bounded by the 1-WL test (Xu et al., 2019). For instance, message passing GNNs fail to differentiate d-regular graphs (Chen et al., 2019; Murphy et al., 2019).

To improve the expressive ability, Zhang and Li (2021) introduces a two-level GNN framework, NGNN, that encodes the general local rooted subgraph around each node instead of a subtree. Concretely, given a graph \(G\), \(h\)-hop rooted subgraph \(g_{v}^{h}\) around each node \(v\) is extracted. Then, inner GNNs are independently applied to these subgraphs \(\{g_{v}^{h}|v\in G\}\) and the learned graph representation of \(g_{v}^{h}\) is used as the input embedding of node \(v\) to the outer GNN. After that, the outer GNN applies graph pooling to get a graph representation. The NGNN framework is strictly more powerful than 1-WL and can distinguish almost all \(d\)-regular graphs. However, the two-level GNN framework can not be applied to DAG encoders (GNNs).

Hence, we introduce a two-level GNN framework with an (ordered) subgraph basis, to restrict subgraphs for inner message passing in the given subgraph basis and apply it to the circuit (DAG) encoding problems in order to reduce the topology search space and increase the expressive ability.

**Definition 3.1**: _(Ordered subgraph basis) An ordered subgraph basis \(\mathbb{B}=\{g_{1},g_{2},...,g_{K}\}\) is a set of subgraphs with a total order \(o\). For \(\forall g_{1},\ g_{2}\in\mathbb{B}\), \(g_{1}<g_{2}\) if and only if \(o(g_{1})<o(g_{2})\)._

Figure 1 illustrates the two-level GNN framework. Given a graph \(G\) and an ordered subgraph basis \(\mathbb{B}\), the rules to extract subgraphs for inner GNNs to learn representations are as follows: 1) For node \(v\in G\), suppose it belongs to multiple subgraphs \(g_{1}^{v},...g_{m}^{v}\in\mathbb{B}\), then the selected subgraph to perform (inner) message passing is \(g_{h}^{v}=\textit{argmax}_{i=1,2,...,m}o(g_{i}^{v})\). 2) If connected nodes \(v\) and \(u\) select the same subgraph \(g_{h}\in\mathbb{B}\), we merge \(v\) and \(u\) and use the representation of subgraph \(g_{h}\) as the feature of the merged node when performing the outer message passing. We show that two-level GNNs can be more powerful than 1-WL in Appendix B.

Figure 1: Illustration of the two-level GNN framework with a pre-designed subgraph basis. It first represents input graph \(g\) as a combination of subgraphs in the subgraph basis \(\mathbb{B}\) and then learns representations of subgraphs with inner GNNs. The subgraph representations are used as input features to the outer message passing operation, where the message passing can be directed/undirected.
### The CktGNN Model

Next, we introduce the CktGNN model for the circuit (i.e. DAGs) automation problem which requires optimizing the circuit topology and node features at the same time. Given a circuit \(G=(V,E)\), each node \(v\in V\) has a node type \(x_{t}\) and node features \(x_{s}\), where \(x_{t}\) denotes the device type in a circuit (i.e., resistor, capacitor, and etc.), and \(x_{s}\) are the categorical or continuous features of the corresponding device.

Due to the similarity between the circuit automation problem and neural architecture search (NAS), potential solutions naturally come from advancements in neural architecture search, where two gradient-based frameworks have achieved impressive results in DAG architecture learning: 1) The VAE framework (Dong et al., 2022; Zhang et al., 2019) uses a GRU-based (or Transformer-based) encoder to map DAGs into vectorial space and then trains the model with a VAE loss. 2) NAS-subroutine-based framework develops DAG encoders and implements encoding-dependent subroutines such as perturb-architecture subroutines (Real et al., 2019; White et al., 2020) and train-predictor-model subroutines (Wen et al., 2020; Shi et al., 2019). As the NAS-subroutine-based framework usually requires a relatively large-size training dataset, yet the large-scale performance simulation of circuits can be time-consuming, we resort to the VAE framework.

Due to the complexity of circuit (DAG) structures and the huge size of the circuit design space (see Appendix A), the circuit automation problem is typically a highly non-convex, challenging optimization problem. Thus, the GRU-based encoders that use shallow layers to encode complex DAG architectures are not sufficient to capture complicated contextualized information of node features and topologies.

To address these limitations, we introduce the CktGNN model. Figure 2 illustrates the architecture of CktGNN. The key idea is to decompose the input circuit as combinations of non-overlapping subgraphs in the subgraph basis \(\mathbb{B}\). After the graph transformation process (i.e. graphizer \(f\)), each node in the transformed DAG \(G^{{}^{\prime}}=(V^{{}^{\prime}},E^{{}^{\prime}})\) represents a subgraph in the input graph (circuit). Then, the representation of a circuit is learned in the two-level GNN framework.

Each node \(v^{{}^{\prime}}\in V^{{}^{\prime}}\) in the transformed DAG \(G^{{}^{\prime}}\) corresponds to a subgraph \(g_{v^{{}^{\prime}}}\) in the input graph. CktGNN treats \(g_{v^{{}^{\prime}}}\) as an undirected graph and uses inner GNNs to learn the subgraph representation \(h_{v^{{}^{\prime}}}\), and each inner GNN consists of multiple undirected message passing layers followed by a graph pooling layer to summarize a subgraph representation. Such a technique enables inner GNNs to capture the contextualized information within each subgraph, thereby increasing the representation ability. In addition, undirected message passing also provides better parallelizability than directed message passing, which increases encoding efficiency.

Figure 2: Illustration of the overall framework. The performance evaluation of circuits is implemented on the circuit simulator. In the representation learning process, we formulate a subgraph basis for operational amplifiers to implement the CktGNN model.
In the outer level GNN, CktGNN performs directed message passing where the aggregation function \(\mathcal{A}\) uses a gated summation and the update function \(\mathcal{U}\) uses a gated recurrent unit (GRU):

\[a_{v^{{}^{\prime}}}=\mathcal{A}(\{z_{u^{{}^{\prime}}}|u^{{}^{ \prime}}\in\mathcal{N}(v^{{}^{\prime}})\})=\sum_{u^{{}^{\prime}}\in\mathcal{N} (v^{{}^{\prime}})}g(z_{u^{{}^{\prime}}})\otimes m(z_{u^{{}^{\prime}}}), \tag{2}\] \[z_{v^{{}^{\prime}}}=\mathcal{U}(\textit{concat}(x_{v^{{}^{ \prime}}}^{{}^{\prime}},h_{v^{{}^{\prime}}}),a_{v^{{}^{\prime}}}). \tag{3}\]

Here, \(z_{v^{{}^{\prime}}}\) is the hidden representation of node \(v^{{}^{\prime}}\) in the transformed DAG \(G^{{}^{\prime}}\), \(m\) is a mapping network and \(g\) is a gating network. In the GRU, \(x_{v^{{}^{\prime}}}^{{}^{\prime}}\) is the one-hot encoding of the subgraph type, and \(h_{v^{{}^{\prime}}}\) is the corresponding subgraph representation learned by inner GNNs. The outer level GNN processes nodes in transformed DAG \(G^{{}^{\prime}}\) following the topological order, and uses the hidden representation of the output node as the graph representation.

### Discussions

**The Injectivity of Graph Transformation Process** Since CktGNN is constructed upon a graphlizer \(f:G\to G^{{}^{\prime}}\) that converts input circuits \(G\) to DAGs \(G^{{}^{\prime}}\) whose nodes \(v^{{}^{\prime}}\) represent non-overlapping subgraphs in \(G\), it's worth discussing the injectivity of \(f\). If \(f(G)\) is not unique, CktGNN will map the same input circuit (DAG \(G\)) to different transformed \(G^{{}^{\prime}}\), thereby learning different representations for the same input \(G\).

**Theorem 3.2**: _Let subgraph basis \(\mathbb{B}\) contain every subgraph of size \(1\). There exists an injective graph transformation \(f\), if each subgraph \(g_{v^{{}^{\prime}}}\in\mathbb{B}\) has only one node to be the head (tail) of a directed edge whose tail (head) is outside the subgraph \(g_{v^{{}^{\prime}}}\)._

We prove Theorem 3.2 in Appendix C. The theorem implies that \(f\) exists when subgraph basis \(\mathbb{B}\) contains every subgraph of size \(1\) and characterizes conditions when the injectivity concern is satisfied. The proof shows that an injective \(f\) can be constructed based on the order function \(o\) over the basis \(\mathbb{B}\). The condition in the Theorem holds in various real-world applications including circuit automation and neural architecture search. For instance, Figure 2 presents an ordered subgraph basis that satisfies the condition for the general operational amplifiers (circuits), and we introduce operational amplifiers and the corresponding subgraph basis in Appendix A.

**Comparison to Related Works.** The proposed CktGNN model extends the NGNN technique (i.e., two-level GNN framework) (Zhang & Li, 2021) to the directed message passing framework for DAG encoding problem. In contrast to NGNN which extracts a rooted subgraph structure around each node within which inner GNNs perform message passing to learn the subgraph representation, CktGNN only uses inner GNNs to learn representations of non-overlapping subgraphs in a known ordered subgraph basis \(\mathbb{B}\). Two main advantages come from the framework over GRU-based DAG encoders (i.e. D-VAE and DAGNN). 1) The topology within subgraphs is automatically embedded once the subgraph type is encoded in CktGNN, which significantly reduces the size of the topology search space. 2) The inner GNNs in CktGNN help to capture the contextualized information within each subgraph, while GNNs in GRU-based DAG encoders are usually too shallow to provide sufficient representative ability.

## 4 Open Circuit Benchmark

We take operational amplifiers (Op-Amps) to build our open circuit benchmark as they are not only one of the most difficult analog circuits to design in the world, but also are the common benchmarks used by prior arts (Wang et al., 2020; Li et al., 2021; Cao et al., 2022b) to evaluate the performance of the proposed methods. Our benchmark equips with communicative circuit generation and evaluation capabilities such that it can also be applied to incorporate a broad range of analog circuits for the evaluations of various design automation methods. To enable such great capabilities, two notable features are proposed and introduced below.

**Converting Circuits into Graphs** We leverage an acyclic graph mapping method by abstracting a complex circuit structure to several simple low-level functional sub-structures, which is similar to the standard synthesis of modern digital circuits. Such a conversion method is thus scalable to large-scale analog circuits with thousands of devices while effectively avoiding cycles in graph converting. To
illustrate this general mapping idea, we take the Op-Amps in our benchmark as an example (see the left upper corner in Figure 2). For an \(N\)-stage Op-Amp (\(N=2,3\)), it consists of \(N\) single-stage Op-Amps in the main feedforward path (i.e., from the input direction to the output direction) and several feedback paths (i.e., vice versa) with different sub-circuit modules. We encode all single-stage Op-Amps and sub-circuit modules as functional sub-structures by using their behavioral models (Lu et al., 2021). In this way, each functional sub-structures can be significantly simplified without using its exact yet complex circuit structure. For instance, a single-stage Op-Amp with tens of transistors can be modeled as a voltage-controlled current source (VCCS, \(g_{m}\)) with a pair of parasitic capacitor \(C\) and resistor \(R\). Instead of using these functional sub-structures as graph vertices, we leverage them as our graph edges while the connection point (e.g., node \(1\) and node \(2\)) between these sub-structures is taken as vertices. Meanwhile, we unify both feedforward and feedback directions as feedforward directions but distinguish them by adding a polarity (e.g., '\(+\)' for feedforward and '\(-\)' for feedback) on device parameters (e.g., \(g_{m}\)+ or \(g_{m}\)\(-\)). In this way, an arbitrary Op-Amp can be efficiently converted into an acyclic graph as shown in Figure 2. Inversely, a newly-generated circuit topology from graph sampling can be converted back into the corresponding Op-Amp by using a conversion-back process from the graph and functional sub-structures to real circuits.

**Interacting with Circuit Simulators** Another important feature of our circuit benchmark is that it can directly interact with a circuit simulator to evaluate the performance of a generated Op-Amp in real-time. Once a circuit topology is generated from our graph sampling, a tailored Python script can translate it into a circuit netlist. A circuit netlist is a standard hardware description of a circuit, based on which the circuit simulator can perform a simulation (evaluation) to extract the circuit specifications, e.g., gain, phase margin, and bandwidth for Op-Amps. This process can be inherently integrated into a Python environment as both open-sourced and commercial circuit simulators support command-line operations. We leverage this conversion-generation-simulation loop to generate \(10,000\) different Op-Amps with detailed circuit specifications. Note that in our dataset, the topologies of Op-Amps are not always distinct from each other. Some Op-Amps have the same topology but with different device parameters. However, our benchmark is friendly to augment other analog circuits such as filters if corresponding circuit-graph mapping methods are built.

## 5 Experiments

### Dataset, Baselines, and Tasks

**Dataset** Our circuit dataset contains 10,000 operational amplifiers (circuits) obtained from the circuit generation process of OCB. Nodes in a circuit (graph) are sampled from \(C\) (capacitor), \(R\) (resistor), and single-stage Op-Amps with different polarities (positive or negative) and directions (feedforward or feedback). Node features are then determined based on the node type: resistor \(R\) has a specification from \(10^{5}\) to \(10^{7}\) Ohm, capacitor \(C\) has a specification from \(10^{-14}\) to \(10^{-12}\) F, and the single-stage Op-Amp has a specification (transconductance, \(g_{m}\)) from \(10^{-4}\) to \(10^{-2}\) S. For each circuit, the circuit simulator of OCB performs careful simulations to get the graph properties (circuit specifications): DC gain (Gain), bandwidth (BW), and phase margin (PM), which characterize the circuit performance from different perspectives. Then the Figure of Merit (FoM) which is an indicator of the circuit's overall performance is computed from Gain, BW, and PM. Details are available in B.

**Baselines** We compare CktGNN with GNN baselines including: 1) widely adopted (undirected) GNNs: GCN (Kipf and Welling, 2016), GIN (Xu et al., 2019), NGNN (Zhang and Li, 2021) and

\begin{table}
\begin{tabular}{l c c c c c c c c c c} \hline \hline  & \multicolumn{2}{c}{Gain} & \multicolumn{2}{c}{BW} & \multicolumn{2}{c}{PM} & \multicolumn{2}{c}{Fault} & \multicolumn{2}{c}{Reconc} \\ \cline{2-10} Evaluation Mode & RMSE \(\downarrow\) & Pearson \(\downarrow\) & \(\uparrow\) & RMSE \(\downarrow\) & Pearson \(\downarrow\) & \(\uparrow\) & RMSE \(\downarrow\) & Pearson \(\downarrow\) & \(\uparrow\) & Acc \(\uparrow\) \\ \hline
**GateN** & **0.657\(\pm\)0.003** & **0.751\(\pm\)0.002** & **0.637\(\pm\)0.003** & **0.647\(\pm\)0.001** & 0.793\(\pm\)0.002 & 0.217\(\pm\)0.001 & **0.854\(\pm\)0.003** & **0.649\(\pm\)0.002** & **0.937** \\ \hline
**PACE** & 0.644 \(\pm\)0.003 & 0.732\(\pm\)0.001 & 0.836\(\pm\)0.003 & 0.642\(\pm\)0.001 & 0.979\(\pm\)0.003 & 0.232\(\pm\)0.001 & 0.839\(\pm\)0.003 & **0.632\(\pm\)0.001** & 0.336 \\ DACNN & 0.659 \(\pm\)0.003 & 0.720\(\pm\)0.001 & 0.818\(\pm\)0.002 & 0.455\(\pm\)0.001 & 0.969\(\pm\)0.003 & 0.231\(\pm\)0.002 & 0.607\(\pm\)0.001 & 0.442\(\pm\)0.001 & 0.289 \\ D-VAE & 0.658 \(\pm\)0.003 & 0.729\(\pm\)0.001 & 0.914\(\pm\)0.000 & 0.396\(\pm\)0.001 & **0.556\(\pm\)0.003** & **0.331\(\pm\)0.002** & 0.977\(\pm\)0.003 & 0.442\(\pm\)0.001 & 0.271 \\ \hline GCN & 0.975\(\pm\)0.003 & 0.140\(\pm\)0.002 & 0.970\(\pm\)0.000 & 0.236\(\pm\)0.001 & 0.993\(\pm\)0.002 & 0.171\(\pm\)0.001 & 0.974\(\pm\)0.003 & 0.217\(\pm\)0.001 & 0.055 \\ GCN & 0.950\(\pm\)0.003 & 0.532\(\pm\)0.001 & 0.935\(\pm\)0.002 & 0.251\(\pm\)0.001 & 0.985\(\pm\)0.004 & 0.187\(\pm\)0.002 & 0.705\(\pm\)0.001 & 0.246\(\pm\)0.001 & 0.058 \\
Graphormer (Ying et al., 2021); 2) dominant DAG encoders (directed GNNs): D-VAE (Zhang et al., 2019), DAGNN (Thost and Chen, 2021) and PACE (Dong et al., 2022). Baseline settings are provided in Appendix D.

**Tasks** We compare CktGNN against baselines on the following three tasks to evaluate the expressiveness, efficiency, and real-world impact: (1) Predictive performance and topology reconstruction accuracy: We test how well the learned graph representation encodes information to predict the graph properties (i.e., Gain, BW, PM, FoM) and reconstruct the input circuit topology. (2) Circuit encoding efficiency: This task compares the training/inference time to characterize the efficiency of the circuit (DAG) encoders. (3) Effectiveness in real-world electronic circuit design automation: For the purpose of circuit generation, we test the proportion that the decoder in the VAE architecture can generate valid DAGs, circuits, and new circuits that are never seen in the training set. Furthermore, for the purpose of automated circuit design, we also perform Bayesian Optimization and compare the overall performance (i.e. FoM) of the detected circuit topology and specifications.

### Predictive Performance and Topology Reconstruction Accuracy

In the experiment, we test the expressive ability of circuit encoders by evaluating the predictivity of the learned graph representation. As the encoder with more expressive ability can better distinguish circuits (graphs) with different topologies and specifications, circuits with similar properties (Gain, BW, PM, or FoM) can be mapped to close representations. Following experimental settings of D-VAE (so as DAGNN and PACE), we train sparse Gaussian Process (SGP) regression models (Snelson and Ghahramani, 2005) to predict circuit properties based on learned representations. In addition, we also characterize the complexity of topology space to encode by measuring the reconstruction accuracy of the circuit topology.

We show our results in Table 1. Experimental results illustrate that CktGNN consistently achieves state-of-art performance in predicting circuit properties. In analogy to D-VAE, we find CktGNN encodes computation (i.e., circuit performance) instead of graph structures when the map between subgraph structure and their defined computation is injective for subgraphs in the basis B. Compared to DAG encoders D-VAE and DAGNN that encodes circuit, inner GNNs in CktGNN enables more message passing iterations to better encode the complicated contextualized information in circuits. On the other hand, PACE, undirected GNNs, and graph Transformers inherently encode graph structures, hence, the latent graph representation space of CktGNN is smoother w.r.t the circuit performance. Furthermore, we also find that CktGNN significantly improves the topology reconstruction accuracy. Such an observation is consistent with the purpose of CktGNN (see Section 3.2) to reduce the topology search space.

### Circuit Encoding Efficiency

Besides the representation learning ability, efficiency and scalability play critical roles in the model design due to the potential heavy traffic coming into the circuit design automation problem in the real world. In the experiment, we compare the average training time per epoch to validate the efficiency of the VAE framework that includes a circuit encoding process and a circuit generation process, while the encoding efficiency itself is tested using the average inference time. Figure 3 illustrates the results. Compared to GRU-based computation encoders (i.e., D-VAE and DAGNN), since CktGNN utilizes simultaneous message passing within each subgraph, it significantly reduces the training/inference

Figure 3: Comparison of training/inference efficiency.
time. In addition, we also find that the extra computation time of CktGNN to fully parallelize encoders (i.e., undirected GNNs like GCN) is marginal.

### Effectiveness in Real-World Electronic Circuit Design

Next, we test the real-world performance of different circuit encoders from two aspects. 1) In a real-world automation process, the circuit generator (i.e., decoder in the VAE framework) is required to be effective to generate proper and novel circuits. Hence, we compare the proportion of valid DAGs, valid circuits, and novel circuits of different methods. 2) We also perform batch Bayesian Optimization (BO) with a batch size of \(50\) using the expected improvement heuristic (Jones et al., 1998) and compute the FoM of the detected circuits after \(10\) iterations.

Table 2 illustrates the results. We find that the proportion of valid circuits generated by the CktGNN-related decoder is significantly higher than other decoders. One potential reason is that CktGNN has an easier topology space to encode and the corresponding decoder can thus better learn the circuit generation rules. We also find that CktGNN has the best circuit design (generation) ability in the generation process. These observations are significant for real-world applications as the automation tools can perform fewer simulations to be cost-effective and time-efficient. In the end, we find that CktGNN-based VAE can find the best circuits with the highest FoM, and we visualize detected circuits in Appendix D.

## 6 Conclusion and Discussions

In this paper, we have presented CktGNN, a two-level GNN model with a pre-designed subgraph basis for the circuit (DAG) encoding problem. Inspired by previous VAE-based neural architecture search routines, we applied CktGNN based on a VAE framework for the challenging analog circuit design automation task. Experiments on the proposed open circuit benchmark (OCB) show that our automation tool can address this long-standing challenging problem in a predictivity-effective and time-efficient way. To the best of our knowledge, the proposed CktGNN-based automation framework pioneers the exploration of learning-based methods to simultaneously optimize the circuit topology and device parameters to achieve the best circuit performance. In addition, the proposed OCB is also the first open-source benchmark in the field of analog circuit topology generation and device parameter optimization. Last but not the least, both our method and benchmark can be generalized to other types of analog circuits with excellent scalability and compatibility.

With the increasing popularity of applying deep learning methods to design industrial digital circuits such as Google TPU (Mirhoseini et al., 2021) and Nvidia GPU (Khailany et al., 2020), the attention paid to analog circuit design automation will be unprecedented as analog circuits are a critical type of ICs to connect our physical analog world and modern digital information world. In a nutshell, we believe that deep learning (especially graph learning)-based analog circuit design automation is an important rising field, which is worthy of extensive explorations and interdisciplinary collaborations.

## 7 Acknowledgement

This work is supported in part by NSF CCF #1942900 and NSF CBET 2225809.

\begin{table}
\begin{tabular}{l c c c c} \hline \hline Methods & Valid DAGs (\%) \(\uparrow\) & Valid circuits (\%) \(\uparrow\) & Novel circuits (\%) \(\uparrow\) & BO (FoM) \(\uparrow\) \\ \hline
**CRIGNN** & **98.92** & **98.92** & 92.29 & **33.43647** \\ \hline PACE & 83.12 & 75.82 & 97.14 & 32.271422 \\ DAGNN & 83.10 & 74.21 & 97.19 & 33.271462 \\ D-VAE & 82.12 & 73.93 & **97.15** & 32.77778 \\ \hline GCN & 81.02 & 72.03 & 97.01 & 31.624473 \\ GIN & 80.92 & 73.17 & 96.88 & 31.624473 \\ NQNN & 82.17 & 73.22 & 95.29 & 32.82656 \\ Graphomer & 82.81 & 72.70 & 94.80 & 32.82656 \\ \hline \hline \end{tabular}
\end{table}
Table 2: Effectiveness in real-world electronic circuit design.
## 8 Reproducibility Statement

The main theoretical contribution of our paper comes from Theorem 3.2, and the complete proof of the Theorem is available in Appendix C. Furthermore, our proposed circuit encoder, CktGNN, is constructed upon the two-level GNN framework with a pre-designed subgraph basis, hence we compare it with general two-level GNN in Section 3.2, and discuss the expressive ability in Appendix B. For our open circuit benchmark (OCB), we provide detailed instructions in Appendix A, and provide open-source code in supplementary material, including the circuit generation code and the simulation file for the circuit simulator. Our source code to implement experiments is also provided in the supplementary materials, and we will make it public on Github in the future.
