a shift register memory device having {HEAD ~ data input} and output means for receiving and delivering data, respectively, and a clock input for receiving clock pulses, said shift register operative to store and to shift data stored within in read/write operations upon {TAIL ~ receipt} of clock pulses 
a shift register memory device having { HEAD ~ data input } and output means for receiving and delivering data , respectively , and a clock input for receiving clock pulses , said shift register operative to store and to shift data stored within in read / write operations upon { TAIL ~ receipt } of clock pulses
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH