Extra latency is added between the time a memory controller issues a write instruction and the time {HEAD ~ the data} is transferred on {TAIL ~ the data bus} 
Extra latency is added between the time a memory controller issues a write instruction and the time { HEAD ~ the data } is transferred on { TAIL ~ the data bus }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL