In this manner, a command sent by the address switch experiences a fixed number of cycles of {TAIL ~ delay} before the command is made available to {HEAD ~ the memory controller} 
In this manner , a command sent by the address switch experiences a fixed number of cycles of { TAIL ~ delay } before the command is made available to { HEAD ~ the memory controller }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD