The unique bus structure of the central processing unit system of the invention incorporates three data paths wherein memory bus means operatively connecting central processing units along a first path, and operatively connection address sourcing {HEAD ~ devices} other than the central processing units along a second path to a first part of memory, and operatively connecting said central processing units and said other address sourcing {TAIL ~ devices} along said first path and second path respectively, and along a common third path to the remaining second part of said memory 
The unique bus structure of the central processing unit system of the invention incorporates three data paths wherein memory bus means operatively connecting central processing units along a first path , and operatively connection address sourcing { HEAD ~ devices } other than the central processing units along a second path to a first part of memory , and operatively connecting said central processing units and said other address sourcing { TAIL ~ devices } along said first path and second path respectively , and along a common third path to the remaining second part of said memory
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