When {HEAD ~ a low logic level} is asserted in {TAIL ~ device A}, the portion of the circuit in device B causes a low logic level to be asserted in device B at the converted level 
When { HEAD ~ a low logic level } is asserted in { TAIL ~ device A } , the portion of the circuit in device B causes a low logic level to be asserted in device B at the converted level
OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH