A predetermined time after the clock signal on the clock wire terminates, i.e., remains inactive for a predetermined period, {HEAD ~ the shift/latch control circuit} generates {TAIL ~ a latch signal} that can be used to capture the data transmitted over the data wire 
A predetermined time after the clock signal on the clock wire terminates , i.e. , remains inactive for a predetermined period , { HEAD ~ the shift / latch control circuit } generates { TAIL ~ a latch signal } that can be used to capture the data transmitted over the data wire
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH