FIG 5 is a schematic diagram showing a cross section view of {HEAD ~ a DMOS device} 500 of {TAIL ~ the present invention} 
FIG 5 is a schematic diagram showing a cross section view of { HEAD ~ a DMOS device } 500 of { TAIL ~ the present invention }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL