{HEAD ~ The phase} of a memory clock signal is adjusted by advancing and delaying {TAIL ~ the phase} 
{ HEAD ~ The phase } of a memory clock signal is adjusted by advancing and delaying { TAIL ~ the phase }
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL REL REL OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL