{HEAD ~ The dummy region} comprises a semiconductor substrate, {TAIL ~ first and second laminates}, at least one first region, and at least one second region 
{ HEAD ~ The dummy region } comprises a semiconductor substrate , { TAIL ~ first and second laminates } , at least one first region , and at least one second region
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH