FIGS 19 22 illustrate {HEAD ~ a method} for {TAIL ~ forming CMOS devices} that include self aligned contacts in core region 200 and forming CMOS devices in non core region 300 using a salicide process, in which a dielectric barrier layer 107 is the protective layer that is used to block salicidation, and in which barrier spacers are formed in core region 200 
FIGS 19 22 illustrate { HEAD ~ a method } for { TAIL ~ forming CMOS devices } that include self aligned contacts in core region 200 and forming CMOS devices in non core region 300 using a salicide process , in which a dielectric barrier layer 107 is the protective layer that is used to block salicidation , and in which barrier spacers are formed in core region 200
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