According to the present invention there is provided a memory address control apparatus, for {TAIL ~ a data processor} using a virtual memory technique, is connected to a main memory unit and a processing unit including an instruction fetch unit, an operand fetch unit, and {HEAD ~ an execution unit} 
According to the present invention there is provided a memory address control apparatus , for { TAIL ~ a data processor } using a virtual memory technique , is connected to a main memory unit and a processing unit including an instruction fetch unit , an operand fetch unit , and { HEAD ~ an execution unit }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD