A sum of first and second input signals to be multiplied is applied to {TAIL ~ a base} or {HEAD ~ gate} of the first transistor with regard to a reference point 
A sum of first and second input signals to be multiplied is applied to { TAIL ~ a base } or { HEAD ~ gate } of the first transistor with regard to a reference point
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH