A memory circuit which has both RAM cells and {HEAD ~ ROM cells} along {TAIL ~ a common row} has a ROM cell which is directly connected to the word line for the row but which is not enabled when a logic state opposite to that represented by the ROM cell is attempted to be written into the ROM cell 
A memory circuit which has both RAM cells and { HEAD ~ ROM cells } along { TAIL ~ a common row } has a ROM cell which is directly connected to the word line for the row but which is not enabled when a logic state opposite to that represented by the ROM cell is attempted to be written into the ROM cell
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH