An output signal showing multiplication result of the first and second input signals is differentially derived between {HEAD ~ the collectors} or drains of {TAIL ~ the first and fourth transistors} and the collectors or drains of the second and third transistors 
An output signal showing multiplication result of the first and second input signals is differentially derived between { HEAD ~ the collectors } or drains of { TAIL ~ the first and fourth transistors } and the collectors or drains of the second and third transistors
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH