At row predecoder 52 2 the input terminals 530 and 531 are controlled by address inputs A8 and A9 respectively and the output terminals L0 L3 drive bus 56 to the row decoder block 32, and at row predecoder 52 3 the input terminals 530 and 531 are controlled by {HEAD ~ address} inputs A10 and {TAIL ~ A11} respectively and the output terminals L0 L3 drive bus 57 to the row decoder block 32 
At row predecoder 52 2 the input terminals 530 and 531 are controlled by address inputs A8 and A9 respectively and the output terminals L0 L3 drive bus 56 to the row decoder block 32 , and at row predecoder 52 3 the input terminals 530 and 531 are controlled by { HEAD ~ address } inputs A10 and { TAIL ~ A11 } respectively and the output terminals L0 L3 drive bus 57 to the row decoder block 32
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