A computer aided clock tree synthesis tool that designs a clock tree tries to position the clock trees buffers or inverters 18 to equalize {HEAD ~ path distances} between {TAIL ~ the clock trees} root 19 and all sinks 16 to help ensure that clock signal edges will arrive at all sinks 16 at substantially the same time 
A computer aided clock tree synthesis tool that designs a clock tree tries to position the clock trees buffers or inverters 18 to equalize { HEAD ~ path distances } between { TAIL ~ the clock trees } root 19 and all sinks 16 to help ensure that clock signal edges will arrive at all sinks 16 at substantially the same time
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