A synchronizing circuit for synchronizing {HEAD ~ an input video signal} with {TAIL ~ a sampling clock signal}, comprising: 
A synchronizing circuit for synchronizing { HEAD ~ an input video signal } with { TAIL ~ a sampling clock signal } , comprising :
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH