The read write circuit 1, wherein third and fourth high resistance p transistors are connected between the supply voltage and the gates of {TAIL ~ the third and fourth n transistors}, the outputs of {HEAD ~ the first and second inverters} being connected to the gates of the third and fourth p transistors 
The read write circuit 1 , wherein third and fourth high resistance p transistors are connected between the supply voltage and the gates of { TAIL ~ the third and fourth n transistors } , the outputs of { HEAD ~ the first and second inverters } being connected to the gates of the third and fourth p transistors
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH