A vertical synchronization signal separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14, and based on an obtained V reset signal, {HEAD ~ a vertical synchronization signal} is obtained in {TAIL ~ a VS output circuit} 18 
A vertical synchronization signal separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14 , and based on an obtained V reset signal , { HEAD ~ a vertical synchronization signal } is obtained in { TAIL ~ a VS output circuit } 18
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH