{HEAD ~ The data transmitting portion} 6 has {TAIL ~ a counter}, and outputs the transmitted data TXD bit by bit, amounting eight bits D7 . . . D0, to the external slaves 7a 7n via the bus 83, each time it detects the asserting edge AG of the transmission clock signal SCLKO 
{ HEAD ~ The data transmitting portion } 6 has { TAIL ~ a counter } , and outputs the transmitted data TXD bit by bit , amounting eight bits D7 . . . D0 , to the external slaves 7a 7n via the bus 83 , each time it detects the asserting edge AG of the transmission clock signal SCLKO
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH