Here, the VS output circuit 18 internally has {TAIL ~ a delay circuit}, and {HEAD ~ the timing} of a vertical synchronization signal VS to be output is shifted from that of a horizontal synchronization signal HS 
Here , the VS output circuit 18 internally has { TAIL ~ a delay circuit } , and { HEAD ~ the timing } of a vertical synchronization signal VS to be output is shifted from that of a horizontal synchronization signal HS
OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH