{HEAD ~ The sampling} and {TAIL ~ holding} of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines 
{ HEAD ~ The sampling } and { TAIL ~ holding } of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines
HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH