The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, {HEAD ~ intermediate semiconductor layer} and upper semiconductor layer laminated in this sequence, a gate insulating film of {TAIL ~ silicon oxide} formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate 
The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer , { HEAD ~ intermediate semiconductor layer } and upper semiconductor layer laminated in this sequence , a gate insulating film of { TAIL ~ silicon oxide } formed on the surface of the side wall of the laminate , and a gate electrode formed so as to cover the side wall of the laminate
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