A fourth multiplexer is included in {TAIL ~ the memory controller} to receive the output signal of the third multiplexer and the output signal of {HEAD ~ the eleventh FF} 
A fourth multiplexer is included in { TAIL ~ the memory controller } to receive the output signal of the third multiplexer and the output signal of { HEAD ~ the eleventh FF }
OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD