Also shown in FIG 4 are {HEAD ~ SBREQ1 and SBREQ2 signals} 470, 475, asserted by {TAIL ~ the bus controller} 215 over the bus 222, which indicate that the bus controller for the first CPU module 120 and the bus controller for the second CPU module 125, respectively, are requesting access to the system bus 110 
Also shown in FIG 4 are { HEAD ~ SBREQ1 and SBREQ2 signals } 470 , 475 , asserted by { TAIL ~ the bus controller } 215 over the bus 222 , which indicate that the bus controller for the first CPU module 120 and the bus controller for the second CPU module 125 , respectively , are requesting access to the system bus 110
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH