In this manner the memory can be inhibited from accepting and shifting data by preventing {HEAD ~ the clock signals} from enabling {TAIL ~ the shift register} 
In this manner the memory can be inhibited from accepting and shifting data by preventing { HEAD ~ the clock signals } from enabling { TAIL ~ the shift register }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL