The integrated circuit 46, wherein {TAIL ~ the channel regions} of {HEAD ~ at least a portion} of the array of memory cells are removed prior to a corresponding word line being formed 
The integrated circuit 46 , wherein { TAIL ~ the channel regions } of { HEAD ~ at least a portion } of the array of memory cells are removed prior to a corresponding word line being formed
OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH