In one aspect, the invention includes DRAM circuitry having an array of {TAIL ~ word lines} forming gates of field effect transistors and an array of {HEAD ~ bit lines} 
In one aspect , the invention includes DRAM circuitry having an array of { TAIL ~ word lines } forming gates of field effect transistors and an array of { HEAD ~ bit lines }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD