said gate or base of said first transistor for receiving , said gate or base of said second transistor for receiving , said gate or base of said third transistor for receiving , and said gate or base of said fourth transistor for receiving , where {HEAD ~ Vx} and Vy are {TAIL ~ first and second input signals}, respectively and u, v and w are constants, excluding the combination u=v=1/2 
said gate or base of said first transistor for receiving , said gate or base of said second transistor for receiving , said gate or base of said third transistor for receiving , and said gate or base of said fourth transistor for receiving , where { HEAD ~ Vx } and Vy are { TAIL ~ first and second input signals } , respectively and u , v and w are constants , excluding the combination u = v=1/2
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