{HEAD ~ The memory device} 14, wherein said {TAIL ~ first column selection circuitry} is selectively controlled by a row address bit and a column address bit; and 
{ HEAD ~ The memory device } 14 , wherein said { TAIL ~ first column selection circuitry } is selectively controlled by a row address bit and a column address bit ; and
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH