{HEAD ~ a processor} operatively coupled to {TAIL ~ memory}, the memory having a capability analysis structure further comprising: 
{ HEAD ~ a processor } operatively coupled to { TAIL ~ memory } , the memory having a capability analysis structure further comprising :
HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH