This can be implemented by feeding the modulo 2 sum of {HEAD ~ the bits} at {TAIL ~ each check} node to a logical OR gate and determining the output 
This can be implemented by feeding the modulo 2 sum of { HEAD ~ the bits } at { TAIL ~ each check } node to a logical OR gate and determining the output
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH