FIG 4 shows {HEAD ~ areas} to be masked on {TAIL ~ the original PCB layout} for primary substrate 1 
FIG 4 shows { HEAD ~ areas } to be masked on { TAIL ~ the original PCB layout } for primary substrate 1
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH