A redundancy circuit for {HEAD ~ a multiport memory device} with {TAIL ~ first and second memories} includes a fuse programming circuit, shared between the first and second memories, for programming a first redundant address 
A redundancy circuit for { HEAD ~ a multiport memory device } with { TAIL ~ first and second memories } includes a fuse programming circuit , shared between the first and second memories , for programming a first redundant address
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH