The architecture includes a decoding scheme wherein the EEPROM chip has {HEAD ~ a row address bit} which is used for the row decoding also participating in the column decoding {TAIL ~ process} 
The architecture includes a decoding scheme wherein the EEPROM chip has { HEAD ~ a row address bit } which is used for the row decoding also participating in the column decoding { TAIL ~ process }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL