wherein said means for connecting includes DC biasing circuitry, said {HEAD ~ DC} biasing {TAIL ~ circuitry} including four identically sized n channel transistors, three of said n channel transistors receiving a second bias current input and one of said n channel transistors receiving a first bias current input, and three identically sized n channel sink transistors connected to said n channel transistor receiving said first bias current input and to two of said 
wherein said means for connecting includes DC biasing circuitry , said { HEAD ~ DC } biasing { TAIL ~ circuitry } including four identically sized n channel transistors , three of said n channel transistors receiving a second bias current input and one of said n channel transistors receiving a first bias current input , and three identically sized n channel sink transistors connected to said n channel transistor receiving said first bias current input and to two of said
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