{HEAD ~ a second multiplexer} receiving as inputs an output of said second inverted XOR gate and {TAIL ~ an output} of said third inverted XOR gate, said first and second multiplexers under control of a common clocking signal, 
{ HEAD ~ a second multiplexer } receiving as inputs an output of said second inverted XOR gate and { TAIL ~ an output } of said third inverted XOR gate , said first and second multiplexers under control of a common clocking signal ,
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH