The switch block circuit 8, wherein {HEAD ~ the common control determination signal} is provided from {TAIL ~ a program memory} 
The switch block circuit 8 , wherein { HEAD ~ the common control determination signal } is provided from { TAIL ~ a program memory }
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL