Each of the pixels includes a first switching device connected to a first gate line of the plurality of first gate lines, and one of a first data line of the plurality of data lines and a first dummy data line of the plurality of dummy data lines; and a second switching device connected to a second gate line of the plurality of {TAIL ~ second gate lines}, and the other one of first data line of {HEAD ~ the plurality} of data lines and the first dummy data line of the plurality of dummy data lines 
Each of the pixels includes a first switching device connected to a first gate line of the plurality of first gate lines , and one of a first data line of the plurality of data lines and a first dummy data line of the plurality of dummy data lines ; and a second switching device connected to a second gate line of the plurality of { TAIL ~ second gate lines } , and the other one of first data line of { HEAD ~ the plurality } of data lines and the first dummy data line of the plurality of dummy data lines
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