The control circuit may be configured to generate a control signal in response to a data signal, a half rate clock signal, and {HEAD ~ a quadrature} of {TAIL ~ the half rate clock signal} 
The control circuit may be configured to generate a control signal in response to a data signal , a half rate clock signal , and { HEAD ~ a quadrature } of { TAIL ~ the half rate clock signal }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL