In this manner, a command sent by the address switch experiences {HEAD ~ a fixed number} of {TAIL ~ cycles} of delay before the command is made available to the memory controller 
In this manner , a command sent by the address switch experiences { HEAD ~ a fixed number } of { TAIL ~ cycles } of delay before the command is made available to the memory controller
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH