The structure 8 further including a third set of switches for selectively reading out said signals from said first and second set of storage capacitors onto {HEAD ~ a set} of {TAIL ~ output lines} as line signals 
The structure 8 further including a third set of switches for selectively reading out said signals from said first and second set of storage capacitors onto { HEAD ~ a set } of { TAIL ~ output lines } as line signals
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH