The output of only one NAND gate will go to {TAIL ~ logical 0 state} when both its input lines are at logic 1 state simultaneously, and so {HEAD ~ the outputs} of the remaining NAND gates will be at logical 1 state 
The output of only one NAND gate will go to { TAIL ~ logical 0 state } when both its input lines are at logic 1 state simultaneously , and so { HEAD ~ the outputs } of the remaining NAND gates will be at logical 1 state
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH