In one embodiment, {HEAD ~ the second transistor} impedes {TAIL ~ static current flow} from the first transistor, through the second transistor, to the logic input 
In one embodiment , { HEAD ~ the second transistor } impedes { TAIL ~ static current flow } from the first transistor , through the second transistor , to the logic input
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH