At {TAIL ~ a given circuit board position} {HEAD ~ predetermined logic levels} are applied to the input mode pins to selectively set internal gating so as to interconnect a desired circuit block to the interface pins of the gate array 
At { TAIL ~ a given circuit board position } { HEAD ~ predetermined logic levels } are applied to the input mode pins to selectively set internal gating so as to interconnect a desired circuit block to the interface pins of the gate array
REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH