The multithreaded processor 6, wherein {HEAD ~ the instruction} corresponds to a thread with a first thread ID and {TAIL ~ the plurality} of stages contain instructions corresponding to more than one thread, and wherein the trap logic unit is further configured to initiate a flush of only those instructions which follow the instruction and which correspond to the first thread ID 
The multithreaded processor 6 , wherein { HEAD ~ the instruction } corresponds to a thread with a first thread ID and { TAIL ~ the plurality } of stages contain instructions corresponding to more than one thread , and wherein the trap logic unit is further configured to initiate a flush of only those instructions which follow the instruction and which correspond to the first thread ID
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH