{HEAD ~ a third inverted XOR logic gate} having as inputs said {TAIL ~ first filtered signal} and said chip sequence, 
{ HEAD ~ a third inverted XOR logic gate } having as inputs said { TAIL ~ first filtered signal } and said chip sequence ,
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH