A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at {HEAD ~ the surface} with {TAIL ~ an array} of channel regions between the bitlines 
A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at { HEAD ~ the surface } with { TAIL ~ an array } of channel regions between the bitlines
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH