The memory controller comprises an XOR gate receiving a phase delayed {HEAD ~ double speed clock signal} from {TAIL ~ the first programmable delay} and a second set of one or more bits from the configuration register and a first flip flop receiving a write command load signal and driven by the internal memory controller clock signal 
The memory controller comprises an XOR gate receiving a phase delayed { HEAD ~ double speed clock signal } from { TAIL ~ the first programmable delay } and a second set of one or more bits from the configuration register and a first flip flop receiving a write command load signal and driven by the internal memory controller clock signal
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