The second gate is electrically connected to the first gate, and {HEAD ~ the second source} is electrically connected to {TAIL ~ the first source}, such that when the DMOS device is ON, a surface channel and a buried channel are formed 
The second gate is electrically connected to the first gate , and { HEAD ~ the second source } is electrically connected to { TAIL ~ the first source } , such that when the DMOS device is ON , a surface channel and a buried channel are formed
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH