{TAIL ~ The device} 1, wherein outputs of each converter are evenly divided into two groups, half being connected to said two multiplexers and {HEAD ~ half} being connected to said first storage register 
{ TAIL ~ The device } 1 , wherein outputs of each converter are evenly divided into two groups , half being connected to said two multiplexers and { HEAD ~ half } being connected to said first storage register
TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH