Memory and {TAIL ~ circuit} for accessing {HEAD ~ data bits} in a memory array in multi data rate operation 
Memory and { TAIL ~ circuit } for accessing { HEAD ~ data bits } in a memory array in multi data rate operation
OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH