Similar to the second embodiment, the fourth embodiment may further decrease the conduction resistance of {TAIL ~ the DMOS device} 500 by reducing the resistance in {HEAD ~ the buried channel} 
Similar to the second embodiment , the fourth embodiment may further decrease the conduction resistance of { TAIL ~ the DMOS device } 500 by reducing the resistance in { HEAD ~ the buried channel }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD