The lock includes {HEAD ~ a counter} and a gate for inhibiting clock pulses to the memory element until {TAIL ~ a predetermined number} of control pulses have been received to initiate a read/write operation 
The lock includes { HEAD ~ a counter } and a gate for inhibiting clock pulses to the memory element until { TAIL ~ a predetermined number } of control pulses have been received to initiate a read / write operation
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH