For each of {HEAD ~ the transistors} 51 0 to 51 3, one end of the current paths connects to the selecting gate lines SGDI0 to SGDI3 of {TAIL ~ the corresponding block} BLK0, the other ends are connected to signal lines SGD0 to SGD3, and signals TG are assigned to the gate 
For each of { HEAD ~ the transistors } 51 0 to 51 3 , one end of the current paths connects to the selecting gate lines SGDI0 to SGDI3 of { TAIL ~ the corresponding block } BLK0 , the other ends are connected to signal lines SGD0 to SGD3 , and signals TG are assigned to the gate
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH