{TAIL ~ The information processing terminal} 1, wherein {HEAD ~ the information processing terminal} is configured to be an integrated circuit card 
{ TAIL ~ The information processing terminal } 1 , wherein { HEAD ~ the information processing terminal } is configured to be an integrated circuit card
TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH