A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of {HEAD ~ the first FET} such that the first FET comprises characteristics of {TAIL ~ an integrated precision resistor} 
A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of { HEAD ~ the first FET } such that the first FET comprises characteristics of { TAIL ~ an integrated precision resistor }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL