Each stage begins with four 32 bit values in {TAIL ~ an A register}, a B register; a C register; and {HEAD ~ a D} register 
Each stage begins with four 32 bit values in { TAIL ~ an A register } , a B register ; a C register ; and { HEAD ~ a D } register
OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH