A plurality of integrated circuit features are provided in {TAIL ~ the context} of an array of {HEAD ~ memory cells} including a plurality of word lines and a plurality of bit lines 
A plurality of integrated circuit features are provided in { TAIL ~ the context } of an array of { HEAD ~ memory cells } including a plurality of word lines and a plurality of bit lines
OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH