A clock tree synthesis tool uses the subtree model to determine the maximum and minimum rising and falling edge path delays though the subtree when estimating the maximum and minimum amounts by which the clock tree delays the clock signals rising and falling edges as they pass from the clock tree root to {HEAD ~ any sink} of {TAIL ~ the IC} 
A clock tree synthesis tool uses the subtree model to determine the maximum and minimum rising and falling edge path delays though the subtree when estimating the maximum and minimum amounts by which the clock tree delays the clock signals rising and falling edges as they pass from the clock tree root to { HEAD ~ any sink } of { TAIL ~ the IC }
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