a second number of {TAIL ~ memory banks} containing said words of {HEAD ~ said logical vector register circuit}; and 
a second number of { TAIL ~ memory banks } containing said words of { HEAD ~ said logical vector register circuit } ; and
OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH