The switch contains {HEAD ~ a data processor}, having {TAIL ~ a segmented ring} with a plurality of dedicated modules designed to process the data connected through that ring 
The switch contains { HEAD ~ a data processor } , having { TAIL ~ a segmented ring } with a plurality of dedicated modules designed to process the data connected through that ring
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH