a second memory cell column that is connected to the second bit line, the second memory cell column being formed by {HEAD ~ a plurality} of {TAIL ~ MONOS type transistors} 
a second memory cell column that is connected to the second bit line , the second memory cell column being formed by { HEAD ~ a plurality } of { TAIL ~ MONOS type transistors }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL