In FIGS 6 a to 6 d are shown, in slice planes, different arrangements for a wafer scale package comprising solid state image sensors , according to {HEAD ~ the principle} of {TAIL ~ the present invention} 
In FIGS 6 a to 6 d are shown , in slice planes , different arrangements for a wafer scale package comprising solid state image sensors , according to { HEAD ~ the principle } of { TAIL ~ the present invention }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL