wherein the second transistor has a control terminal coupling to an output of the decoder, and the at least one additional transistor has {HEAD ~ a control terminal coupling} to {TAIL ~ an output} of the decoder 
wherein the second transistor has a control terminal coupling to an output of the decoder , and the at least one additional transistor has { HEAD ~ a control terminal coupling } to { TAIL ~ an output } of the decoder
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH