a second number of {HEAD ~ memory banks} containing said words of {TAIL ~ said logical vector register circuit}; and 
a second number of { HEAD ~ memory banks } containing said words of { TAIL ~ said logical vector register circuit } ; and
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH