a third adder configured to modulo add the B register value and an output of {TAIL ~ the fixed 32 bit shift unit}, wherein the output of the fixed 32 bit shift unit is provided to the third adder via {HEAD ~ direct bit} routing to the third adder; and 
a third adder configured to modulo add the B register value and an output of { TAIL ~ the fixed 32 bit shift unit } , wherein the output of the fixed 32 bit shift unit is provided to the third adder via { HEAD ~ direct bit } routing to the third adder ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH