Additionally, the memory controller comprises a second multiplexer receiving the output signal of {TAIL ~ the seventh FF} and the output signal of the ninth FF and controlled by {HEAD ~ a third set} of one or more bits from the configuration register 
Additionally , the memory controller comprises a second multiplexer receiving the output signal of { TAIL ~ the seventh FF } and the output signal of the ninth FF and controlled by { HEAD ~ a third set } of one or more bits from the configuration register
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH