The memory device 1, wherein K is two, and wherein a first control line is associated with {TAIL ~ a rising edge} of the clock signal and a second control line is associated with a falling edge of {HEAD ~ the clock signal} 
The memory device 1 , wherein K is two , and wherein a first control line is associated with { TAIL ~ a rising edge } of the clock signal and a second control line is associated with a falling edge of { HEAD ~ the clock signal }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD