{HEAD ~ The method} 11 wherein the CMOS device includes a memory core of substantially replicated cells and includes a periphery region that includes control logic, the first region extending entirely within the memory core, and the second region extending partially within the memory core and partially within {TAIL ~ the periphery region} 
{ HEAD ~ The method } 11 wherein the CMOS device includes a memory core of substantially replicated cells and includes a periphery region that includes control logic , the first region extending entirely within the memory core , and the second region extending partially within the memory core and partially within { TAIL ~ the periphery region }
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL