The subsystem monitoring circuit includes {HEAD ~ a transfer count register} which indicates {TAIL ~ how many data transfer cycles} can be run in succession before the local CPU has to relinquish control of the system bus 
The subsystem monitoring circuit includes { HEAD ~ a transfer count register } which indicates { TAIL ~ how many data transfer cycles } can be run in succession before the local CPU has to relinquish control of the system bus
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH