Similar to the second embodiment, the fourth embodiment may further decrease {HEAD ~ the conduction resistance} of {TAIL ~ the DMOS device} 500 by reducing the resistance in the buried channel 
Similar to the second embodiment , the fourth embodiment may further decrease { HEAD ~ the conduction resistance } of { TAIL ~ the DMOS device } 500 by reducing the resistance in the buried channel
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH