wherein, in the step , a gate electrode of a third MISFET is formed by patterning the conductive film such that {HEAD ~ the gate electrode} of {TAIL ~ the second MISFET} is arranged, in the first direction, between the gate electrode of the first MISFET and the gate electrode of the third MISFET, 
wherein , in the step , a gate electrode of a third MISFET is formed by patterning the conductive film such that { HEAD ~ the gate electrode } of { TAIL ~ the second MISFET } is arranged , in the first direction , between the gate electrode of the first MISFET and the gate electrode of the third MISFET ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH