A refresh counter circuit 5 or 6, wherein {HEAD ~ each} of said path switches comprises {TAIL ~ a complementary type transfer gate} including PMOS and NMOS 
A refresh counter circuit 5 or 6 , wherein { HEAD ~ each } of said path switches comprises { TAIL ~ a complementary type transfer gate } including PMOS and NMOS
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH