This disclosure refers to multiprocessor {HEAD ~ systems} having {TAIL ~ individual cache memories} including means to keep the cache memories coherent 
This disclosure refers to multiprocessor { HEAD ~ systems } having { TAIL ~ individual cache memories } including means to keep the cache memories coherent
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH