{TAIL ~ The control circuit} may be configured to generate a control signal in response to a data signal, a half rate clock signal, and {HEAD ~ a quadrature} of the half rate clock signal 
{ TAIL ~ The control circuit } may be configured to generate a control signal in response to a data signal , a half rate clock signal , and { HEAD ~ a quadrature } of the half rate clock signal
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH