In one embodiment, each memory cell constituted of {HEAD ~ the floating gate field effect transistor} has a triple well structure in which {TAIL ~ a P well} that provides a channel region is formed via an N well on a P type semiconductor substrate 
In one embodiment , each memory cell constituted of { HEAD ~ the floating gate field effect transistor } has a triple well structure in which { TAIL ~ a P well } that provides a channel region is formed via an N well on a P type semiconductor substrate
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH