In the circuit of the second aspect, if the first and second input signals are defined as Vx and Vy, the gate of the first FET receives , the gate of {HEAD ~ the second FET} receives Vx +vVy !, the gate of the third FET receives uVx +Vy !, and the gate of the fourth FET receives Vx +Vy !, where u, v and w are {TAIL ~ constants} 
In the circuit of the second aspect , if the first and second input signals are defined as Vx and Vy , the gate of the first FET receives , the gate of { HEAD ~ the second FET } receives Vx + vVy ! , the gate of the third FET receives uVx + Vy ! , and the gate of the fourth FET receives Vx + Vy ! , where u , v and w are { TAIL ~ constants }
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