{HEAD ~ The memory controller} further comprises {TAIL ~ an OR gate} receiving the output signal of the fourth FF and the output signal of the sixth FF; a seventh FF receiving the output signal of the OR gate and driven by the output signal of the first programmable delay; an eighth FF receiving the output signal of the OR gate and driven by the output signal of the first programmable delay; and a ninth FF receiving the output signal of the seventh FF and driven by the output signal of the first programmable delay 
{ HEAD ~ The memory controller } further comprises { TAIL ~ an OR gate } receiving the output signal of the fourth FF and the output signal of the sixth FF ; a seventh FF receiving the output signal of the OR gate and driven by the output signal of the first programmable delay ; an eighth FF receiving the output signal of the OR gate and driven by the output signal of the first programmable delay ; and a ninth FF receiving the output signal of the seventh FF and driven by the output signal of the first programmable delay
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH