The semiconductor memory device 6, further comprising an adjustment transistor coupled in {HEAD ~ parallel} with {TAIL ~ the pull down transistor}, wherein the adjustment transistor is configured to be controllable by at least one bit of the stack position identifier 
The semiconductor memory device 6 , further comprising an adjustment transistor coupled in { HEAD ~ parallel } with { TAIL ~ the pull down transistor } , wherein the adjustment transistor is configured to be controllable by at least one bit of the stack position identifier
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH