At the same time output terminals L1, L2 and {TAIL ~ L3} will be at {HEAD ~ logical 0 state} 
At the same time output terminals L1 , L2 and { TAIL ~ L3 } will be at { HEAD ~ logical 0 state }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD