{HEAD ~ The feedback stage} is operable in {TAIL ~ at least two feedback modes} to hold the output bit state during the second clock state of the clock signal 
{ HEAD ~ The feedback stage } is operable in { TAIL ~ at least two feedback modes } to hold the output bit state during the second clock state of the clock signal
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH