The parallel connected differential CMOS sections of each variable delay element are controlled by a differential control voltage whose magnitude sets {HEAD ~ relative levels} of {TAIL ~ operation} of the two differential sections of each variable delay element 
The parallel connected differential CMOS sections of each variable delay element are controlled by a differential control voltage whose magnitude sets { HEAD ~ relative levels } of { TAIL ~ operation } of the two differential sections of each variable delay element
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH