The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, {TAIL ~ either processors}, I/O agents, or coherent memory adapters, organized into a set of {HEAD ~ nodes} supported by a node controller 
The distributed system structure contains an address switch , multiple memory subsystems , and multiple master devices , { TAIL ~ either processors } , I / O agents , or coherent memory adapters , organized into a set of { HEAD ~ nodes } supported by a node controller
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH