{HEAD ~ The integrated circuit} 46, wherein {TAIL ~ the channel regions} of at least a portion of the array of memory cells are removed prior to a corresponding word line being formed 
{ HEAD ~ The integrated circuit } 46 , wherein { TAIL ~ the channel regions } of at least a portion of the array of memory cells are removed prior to a corresponding word line being formed
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH