{HEAD ~ The LSSD scan paths} of each logic circuit chip on a circuit module are connected to {TAIL ~ additional test circuit chips} on the same module 
{ HEAD ~ The LSSD scan paths } of each logic circuit chip on a circuit module are connected to { TAIL ~ additional test circuit chips } on the same module
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH