In addition, {HEAD ~ a predetermined voltage} generated by {TAIL ~ the second field effect transistor} is applied to the gate of the first field effect transistor to set the bias point of the first field effect transistor such that the first field effect transistor comprises characteristics of an integrated precision resistor 
In addition , { HEAD ~ a predetermined voltage } generated by { TAIL ~ the second field effect transistor } is applied to the gate of the first field effect transistor to set the bias point of the first field effect transistor such that the first field effect transistor comprises characteristics of an integrated precision resistor
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH