a first inverted XOR logic gate having as {TAIL ~ inputs} said first filtered signal and {HEAD ~ a chip sequence}, 
a first inverted XOR logic gate having as { TAIL ~ inputs } said first filtered signal and { HEAD ~ a chip sequence } ,
OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH