The method 11 wherein {HEAD ~ the CMOS device} includes {TAIL ~ a memory core} of substantially replicated cells and includes a periphery region that includes control logic, the first region extending entirely within the memory core, and the second region extending partially within the memory core and partially within the periphery region 
The method 11 wherein { HEAD ~ the CMOS device } includes { TAIL ~ a memory core } of substantially replicated cells and includes a periphery region that includes control logic , the first region extending entirely within the memory core , and the second region extending partially within the memory core and partially within the periphery region
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH