The memory controller comprises an XOR gate receiving a phase delayed double speed clock signal from the first programmable delay and {HEAD ~ a second set} of one or more bits from {TAIL ~ the configuration register} and a first flip flop receiving a write command load signal and driven by the internal memory controller clock signal 
The memory controller comprises an XOR gate receiving a phase delayed double speed clock signal from the first programmable delay and { HEAD ~ a second set } of one or more bits from { TAIL ~ the configuration register } and a first flip flop receiving a write command load signal and driven by the internal memory controller clock signal
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH