The memory device 1, wherein K is two, and wherein a first control line is associated with a rising edge of the clock signal and a second control line is associated with {HEAD ~ a falling edge} of {TAIL ~ the clock signal} 
The memory device 1 , wherein K is two , and wherein a first control line is associated with a rising edge of the clock signal and a second control line is associated with { HEAD ~ a falling edge } of { TAIL ~ the clock signal }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL