{HEAD ~ One aspect} of this invention comprises an architecture and {TAIL ~ circuitry} that enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in a given column to the bit lines such as the architecture of FIG 2 of U.S. Pat 
{ HEAD ~ One aspect } of this invention comprises an architecture and { TAIL ~ circuitry } that enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in a given column to the bit lines such as the architecture of FIG 2 of U.S. Pat
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH REL OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH