The analyzer includes a load bank consisting of a plurality of {HEAD ~ resistors} in {TAIL ~ selective parallel interconnection} 
The analyzer includes a load bank consisting of a plurality of { HEAD ~ resistors } in { TAIL ~ selective parallel interconnection }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL