{HEAD ~ The circuit} 1, wherein {TAIL ~ the delay circuit} delays the internal vertical synchronization signal by about 1.5 μsec 
{ HEAD ~ The circuit } 1 , wherein { TAIL ~ the delay circuit } delays the internal vertical synchronization signal by about 1.5 μsec
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH