At the same time {HEAD ~ output terminals L1}, L2 and L3 will be at {TAIL ~ logical 0 state} 
At the same time { HEAD ~ output terminals L1 } , L2 and L3 will be at { TAIL ~ logical 0 state }
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL