A semiconductor integrated circuit having bias circuits {HEAD ~ each} including {TAIL ~ different reference resistor} is disclosed 
A semiconductor integrated circuit having bias circuits { HEAD ~ each } including { TAIL ~ different reference resistor } is disclosed
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH