Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and {HEAD ~ those signals} described as negative logic signals may be implemented as {TAIL ~ positive logic signals} 
Therefore , in alternate embodiments , those signals described as positive logic signals may be implemented as negative logic signals , and { HEAD ~ those signals } described as negative logic signals may be implemented as { TAIL ~ positive logic signals }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL