As will subsequently appear, provision is made in the digital logic circuitry for taking the pattern elements A, B, {HEAD ~ C}, and D from a present scan, while the elements E, F, and {TAIL ~ G} are taken from a previous scan 
As will subsequently appear , provision is made in the digital logic circuitry for taking the pattern elements A , B , { HEAD ~ C } , and D from a present scan , while the elements E , F , and { TAIL ~ G } are taken from a previous scan
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH