The apparatus includes a buffer utilized for buffering an input signal and then outputting an output signal; a digital to analog converter utilized for converting a digital value representative of phase delay into a corresponding control voltage and outputting a control voltage; and a variable capacitor that has {HEAD ~ a capacitance value} controlled by {TAIL ~ the control voltage} 
The apparatus includes a buffer utilized for buffering an input signal and then outputting an output signal ; a digital to analog converter utilized for converting a digital value representative of phase delay into a corresponding control voltage and outputting a control voltage ; and a variable capacitor that has { HEAD ~ a capacitance value } controlled by { TAIL ~ the control voltage }
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