A pattern discriminating apparatus 1, 2 or 3, wherein said smoothing means comprises shift registers which receive and shift the signal output from said first memory means and which simultaneously parallel output the interval integrated values for the plurality of intervals; D/A converters for converting digital signals output from said shift registers into {HEAD ~ analog signals} for {TAIL ~ each} of the intervals; and an amplifying circuit which takes a mean value of outputs from said D/A converters 
A pattern discriminating apparatus 1 , 2 or 3 , wherein said smoothing means comprises shift registers which receive and shift the signal output from said first memory means and which simultaneously parallel output the interval integrated values for the plurality of intervals ; D / A converters for converting digital signals output from said shift registers into { HEAD ~ analog signals } for { TAIL ~ each } of the intervals ; and an amplifying circuit which takes a mean value of outputs from said D / A converters
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH