{HEAD ~ Source and drain regions} of {TAIL ~ field effect transistors} are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed 
{ HEAD ~ Source and drain regions } of { TAIL ~ field effect transistors } are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed
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