{HEAD ~ The control logic circuit} is coupled to the first tracking bit line and configured to generate {TAIL ~ the SAE signal} in response to the voltage level on the first tracking bit line 
{ HEAD ~ The control logic circuit } is coupled to the first tracking bit line and configured to generate { TAIL ~ the SAE signal } in response to the voltage level on the first tracking bit line
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH