The illustrative embodiments provide a design structure for actively biasing field effect transistors in {TAIL ~ a loop filter} in an integrated phase lock loop circuit to form {HEAD ~ precision integrated resistors} having a reduced area and improved high frequency capability 
The illustrative embodiments provide a design structure for actively biasing field effect transistors in { TAIL ~ a loop filter } in an integrated phase lock loop circuit to form { HEAD ~ precision integrated resistors } having a reduced area and improved high frequency capability
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH