address decoder means responsive to one portion of said logical address in said register for selecting and reading out to said TLB {HEAD ~ a set} having {TAIL ~ mT compartments} in said TLB, 
address decoder means responsive to one portion of said logical address in said register for selecting and reading out to said TLB { HEAD ~ a set } having { TAIL ~ mT compartments } in said TLB ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH