The period T0 to T5 covers approximately 133 milliseconds during which {HEAD ~ approximately 266 pulses} are generated by {TAIL ~ the controller unit} 66 and passed to the transistor switch 64 
The period T0 to T5 covers approximately 133 milliseconds during which { HEAD ~ approximately 266 pulses } are generated by { TAIL ~ the controller unit } 66 and passed to the transistor switch 64
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH