The delay can further be reduced by reducing {TAIL ~ the gate widths} of {HEAD ~ the differential transistors} Q9 and Q10 in the differential section D2 relative to the gate widths of the differential transistors Q7 and Q8 in the first differential section D1 
The delay can further be reduced by reducing { TAIL ~ the gate widths } of { HEAD ~ the differential transistors } Q9 and Q10 in the differential section D2 relative to the gate widths of the differential transistors Q7 and Q8 in the first differential section D1
OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH