a Dual Port RAM connected to the single electrical interface, the Dual Port RAM configured to parallelly transfer {HEAD ~ data} through {TAIL ~ the single electrical interface}; and 
through
a Dual Port RAM connected to the single electrical interface , the Dual Port RAM configured to parallelly transfer { HEAD ~ data } through { TAIL ~ the single electrical interface } ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH