The analyzer includes a load bank consisting of {HEAD ~ a plurality} of {TAIL ~ resistors} in selective parallel interconnection 
of
The analyzer includes a load bank consisting of { HEAD ~ a plurality } of { TAIL ~ resistors } in selective parallel interconnection
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH