{HEAD ~ The issue circuit} issues an instruction to the execution circuit, and generates {TAIL ~ a control signal} responsive to whether or not the instruction is issued to the execution circuit 
generates
{ HEAD ~ The issue circuit } issues an instruction to the execution circuit , and generates { TAIL ~ a control signal } responsive to whether or not the instruction is issued to the execution circuit
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH