Also, optionally, {HEAD ~ the VBUS power signal} may be routed to {TAIL ~ a programmed or discrete logic circuit} or other circuitry 25 to adjust the polarity of the signal and to output an Enable signal 
routed to
Also , optionally , { HEAD ~ the VBUS power signal } may be routed to { TAIL ~ a programmed or discrete logic circuit } or other circuitry 25 to adjust the polarity of the signal and to output an Enable signal
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH