In one aspect, the invention includes DRAM circuitry having {HEAD ~ an array} of {TAIL ~ word lines} forming gates of field effect transistors and an array of bit lines 
of
In one aspect , the invention includes DRAM circuitry having { HEAD ~ an array } of { TAIL ~ word lines } forming gates of field effect transistors and an array of bit lines
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH