The delay can further be reduced by reducing the gate widths of the differential transistors Q9 and Q10 in the differential section D2 relative to the gate widths of the differential transistors {TAIL ~ Q7} and Q8 in {HEAD ~ the first differential section D1} 
The delay can further be reduced by reducing the gate widths of the differential transistors Q9 and Q10 in the differential section D2 relative to the gate widths of the differential transistors { TAIL ~ Q7 } and Q8 in { HEAD ~ the first differential section D1 }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD