FIG 2 depicts {HEAD ~ a simple clock tree} 14 for delivering a clock signal arriving at its root 19 to several sinks 16 through a set of {TAIL ~ buffers} and inverters 18 provided to fan out the clock signal 
FIG 2 depicts { HEAD ~ a simple clock tree } 14 for delivering a clock signal arriving at its root 19 to several sinks 16 through a set of { TAIL ~ buffers } and inverters 18 provided to fan out the clock signal
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH