Disabling the output circuit following such a delay severs {HEAD ~ the potential current path} between {TAIL ~ the supply voltage} of the integrated circuit and an external voltage source coupled to the signal line via a pull up device 
between
Disabling the output circuit following such a delay severs { HEAD ~ the potential current path } between { TAIL ~ the supply voltage } of the integrated circuit and an external voltage source coupled to the signal line via a pull up device
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH