The apparatus 14 wherein the clocking circuit includes a plurality of levels of clock buffer circuitry, and wherein {HEAD ~ a first level} of the plurality of levels includes {TAIL ~ one or more logic gates} which combine the clock input and the control signal input 
includes
The apparatus 14 wherein the clocking circuit includes a plurality of levels of clock buffer circuitry , and wherein { HEAD ~ a first level } of the plurality of levels includes { TAIL ~ one or more logic gates } which combine the clock input and the control signal input
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH