The suppression circuit may be a single varistor or a number of varistors in parallel with {HEAD ~ a number} of {TAIL ~ lines} in the distribution circuit 
of
The suppression circuit may be a single varistor or a number of varistors in parallel with { HEAD ~ a number } of { TAIL ~ lines } in the distribution circuit
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH