{HEAD ~ The control signal} is asserted by {TAIL ~ a control circuit} following the detection of a logic high signal of a predetermined duration at the external signal connection point 
is asserted by
{ HEAD ~ The control signal } is asserted by { TAIL ~ a control circuit } following the detection of a logic high signal of a predetermined duration at the external signal connection point
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH