The apparatus 1 wherein said load bank comprises {HEAD ~ a plurality} of {TAIL ~ resistors} in selective parallel interconnection 
of
The apparatus 1 wherein said load bank comprises { HEAD ~ a plurality } of { TAIL ~ resistors } in selective parallel interconnection
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH