Each stage begins with four 32 bit values in an A register, a B register; {TAIL ~ a C register}; and {HEAD ~ a D} register 
Each stage begins with four 32 bit values in an A register , a B register ; { TAIL ~ a C register } ; and { HEAD ~ a D } register
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH