The processes and {HEAD ~ logic flows} can also be performed by, and apparatus of the invention can be implemented as, special purpose logic circuitry, {TAIL ~ e.g., an FPGA} or an ASIC  
performed by
The processes and { HEAD ~ logic flows } can also be performed by , and apparatus of the invention can be implemented as , special purpose logic circuitry , { TAIL ~ e.g. , an FPGA } or an ASIC
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH REL REL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH