The memory controller further comprises a third multiplexer receiving the output signal of the second FF and {TAIL ~ the output signal} of {HEAD ~ the third FF} and controlled by the output signal of the eighth FF 
The memory controller further comprises a third multiplexer receiving the output signal of the second FF and { TAIL ~ the output signal } of { HEAD ~ the third FF } and controlled by the output signal of the eighth FF
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH