The memory sharing arrangement provides {HEAD ~ a separate high speed data transfer mechanism} between {TAIL ~ the PLCs} and the DSP 
between
The memory sharing arrangement provides { HEAD ~ a separate high speed data transfer mechanism } between { TAIL ~ the PLCs } and the DSP
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH