The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of {HEAD ~ silicon oxide} formed on {TAIL ~ the surface} of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate 
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The vertical MISFETs respectively mainly include a laminate formed of a lower semiconductor layer , intermediate semiconductor layer and upper semiconductor layer laminated in this sequence , a gate insulating film of { HEAD ~ silicon oxide } formed on { TAIL ~ the surface } of the side wall of the laminate , and a gate electrode formed so as to cover the side wall of the laminate
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