{HEAD ~ The memory controller} comprises an XOR gate receiving a phase delayed double speed clock signal from the first programmable delay and a second set of one or more bits from the configuration register and {TAIL ~ a first flip flop} receiving a write command load signal and driven by the internal memory controller clock signal 
comprises
{ HEAD ~ The memory controller } comprises an XOR gate receiving a phase delayed double speed clock signal from the first programmable delay and a second set of one or more bits from the configuration register and { TAIL ~ a first flip flop } receiving a write command load signal and driven by the internal memory controller clock signal
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH