A plurality of integrated circuit features are provided in the context of an array of {HEAD ~ memory cells} including a plurality of word lines and {TAIL ~ a plurality} of bit lines 
including
A plurality of integrated circuit features are provided in the context of an array of { HEAD ~ memory cells } including a plurality of word lines and { TAIL ~ a plurality } of bit lines
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH