{HEAD ~ four 32 bit registers} designated A, B, C and {TAIL ~ D}, wherein each register holds a value; and 
designated
{ HEAD ~ four 32 bit registers } designated A , B , C and { TAIL ~ D } , wherein each register holds a value ; and
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH