The bus enables single or multiple controllers to access {TAIL ~ real time information} generated by {HEAD ~ the attached hardware} 
The bus enables single or multiple controllers to access { TAIL ~ real time information } generated by { HEAD ~ the attached hardware }
OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD