However, during the integration time, the gate 205 is kept at surface potential, in order to obtain {HEAD ~ the noise advantages} of {TAIL ~ a virtual floating gate} 205 
of
However , during the integration time , the gate 205 is kept at surface potential , in order to obtain { HEAD ~ the noise advantages } of { TAIL ~ a virtual floating gate } 205
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH