{TAIL ~ A fourth multiplexer} is included in the memory controller to receive the output signal of {HEAD ~ the third multiplexer} and the output signal of the eleventh FF 
{ TAIL ~ A fourth multiplexer } is included in the memory controller to receive the output signal of { HEAD ~ the third multiplexer } and the output signal of the eleventh FF
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH