Operation of {TAIL ~ the semiconductor device} having {HEAD ~ the above described configuration} according to the exemplary embodiment will be described in detail with reference to FIGS 4 to 8 
Operation of { TAIL ~ the semiconductor device } having { HEAD ~ the above described configuration } according to the exemplary embodiment will be described in detail with reference to FIGS 4 to 8
OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH