In one aspect, the invention includes DRAM circuitry having an array of {HEAD ~ word lines} forming {TAIL ~ gates} of field effect transistors and an array of bit lines 
forming
In one aspect , the invention includes DRAM circuitry having an array of { HEAD ~ word lines } forming { TAIL ~ gates } of field effect transistors and an array of bit lines
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH