{HEAD ~ An output signal} showing multiplication result of {TAIL ~ the first and second input signals} is differentially derived between the collectors or drains of the first and fourth transistors and the collectors or drains of the second and third transistors 
{ HEAD ~ An output signal } showing multiplication result of { TAIL ~ the first and second input signals } is differentially derived between the collectors or drains of the first and fourth transistors and the collectors or drains of the second and third transistors
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH