a second inverted XOR logic gate having as inputs said {TAIL ~ second filtered signal} and said {HEAD ~ chip sequence}, 
a second inverted XOR logic gate having as inputs said { TAIL ~ second filtered signal } and said { HEAD ~ chip sequence } ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH