A high speed, {HEAD ~ low power Static Random Access Memory Array}, which includes {TAIL ~ a 4T cell} with two integrated Schottky Barrier Diodes is disclosed 
includes
A high speed , { HEAD ~ low power Static Random Access Memory Array } , which includes { TAIL ~ a 4 T cell } with two integrated Schottky Barrier Diodes is disclosed
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH