However, during the integration time, the gate 205 is kept at surface potential, in {TAIL ~ order} to obtain {HEAD ~ the noise advantages} of a virtual floating gate 205 
However , during the integration time , the gate 205 is kept at surface potential , in { TAIL ~ order } to obtain { HEAD ~ the noise advantages } of a virtual floating gate 205
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH