According to one aspect of the present invention, a delay circuit delays an internal vertical synchronization signal, and there by {HEAD ~ the timing} of an internal horizontal synchronization signal and an internal vertical synchronization signal can be shifted by {TAIL ~ a predetermined short period} of time 
shifted by
According to one aspect of the present invention , a delay circuit delays an internal vertical synchronization signal , and there by { HEAD ~ the timing } of an internal horizontal synchronization signal and an internal vertical synchronization signal can be shifted by { TAIL ~ a predetermined short period } of time
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH