The width of the non conductive region, designated Ls in FIG 3, is selected to increase {HEAD ~ the base width} of the parasitic NPN bipolar transistor 39 while preserving the surface area of {TAIL ~ the device} 
The width of the non conductive region , designated Ls in FIG 3 , is selected to increase { HEAD ~ the base width } of the parasitic NPN bipolar transistor 39 while preserving the surface area of { TAIL ~ the device }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL