In {HEAD ~ a first feedback mode}, the output bit state of {TAIL ~ the output bit signal} is held as provided from the sampling stage 
In { HEAD ~ a first feedback mode } , the output bit state of { TAIL ~ the output bit signal } is held as provided from the sampling stage
OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH