The semiconductor package 1, wherein {HEAD ~ each} of {TAIL ~ the chips} is configured to have a DRAM+controller structure 
of
The semiconductor package 1 , wherein { HEAD ~ each } of { TAIL ~ the chips } is configured to have a DRAM+controller structure
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH