{HEAD ~ Multiple channels} are accommodated via a channel interface, also controlled by {TAIL ~ the microprocessor}, between external video devices and the random access memory 
are controlled by
{ HEAD ~ Multiple channels } are accommodated via a channel interface , also controlled by { TAIL ~ the microprocessor } , between external video devices and the random access memory
HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH