The SSE may be provided in a pipeline circuit of {HEAD ~ a TRSS machine} to receive and store {TAIL ~ a bit state} of bit signal generated by combinational circuits within the pipeline circuit 
to receive
The SSE may be provided in a pipeline circuit of { HEAD ~ a TRSS machine } to receive and store { TAIL ~ a bit state } of bit signal generated by combinational circuits within the pipeline circuit
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH