comparison means responsive to the logical addresses read out from {HEAD ~ said register} and said TLB for comparing the logical addresses in said set having been read out with a portion of said logical address in {TAIL ~ said register}, 
comparison means responsive to the logical addresses read out from { HEAD ~ said register } and said TLB for comparing the logical addresses in said set having been read out with a portion of said logical address in { TAIL ~ said register } ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH