In FIGS 6 a to 6 d are shown, in slice planes, different arrangements for a wafer scale package comprising {TAIL ~ solid state image sensors} , according to {HEAD ~ the principle} of the present invention 
In FIGS 6 a to 6 d are shown , in slice planes , different arrangements for a wafer scale package comprising { TAIL ~ solid state image sensors } , according to { HEAD ~ the principle } of the present invention
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH