Said first and second path being effective for said central processing units and said address sourcing {TAIL ~ devices} to access the first part of {HEAD ~ the memory} without contention with each other, and for diminishing contention with each other when accessing the second part of the memory 
Said first and second path being effective for said central processing units and said address sourcing { TAIL ~ devices } to access the first part of { HEAD ~ the memory } without contention with each other , and for diminishing contention with each other when accessing the second part of the memory
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH