A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and {HEAD ~ a plurality} of {TAIL ~ bit lines} 
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A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and { HEAD ~ a plurality } of { TAIL ~ bit lines }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL