However, during the integration time, the gate 205 is kept at surface potential, in {HEAD ~ order} to obtain {TAIL ~ the noise advantages} of a virtual floating gate 205 
to obtain
However , during the integration time , the gate 205 is kept at surface potential , in { HEAD ~ order } to obtain { TAIL ~ the noise advantages } of a virtual floating gate 205
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH