In another embodiment, {HEAD ~ a latency} of {TAIL ~ a DRAM} or SRAM is adjusted based on the SPID 
of
In another embodiment , { HEAD ~ a latency } of { TAIL ~ a DRAM } or SRAM is adjusted based on the SPID
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH