In another aspect of the present invention there is provided a semiconductor device comprising {HEAD ~ a chip region}, {TAIL ~ a sealing ring region} which surrounds the chip region in plan, and a dummy region which surrounds an outer periphery of the sealing ring region in plan 
In another aspect of the present invention there is provided a semiconductor device comprising { HEAD ~ a chip region } , { TAIL ~ a sealing ring region } which surrounds the chip region in plan , and a dummy region which surrounds an outer periphery of the sealing ring region in plan
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH