The horizontal synchronization signal {HEAD ~ HSYNC} is supplied to {TAIL ~ a VCO/AFC circuit} 12, in which a 4 MHz internal clock synchronized with the horizontal synchronization signal HSYNC is generated 
is supplied to
The horizontal synchronization signal { HEAD ~ HSYNC } is supplied to { TAIL ~ a VCO / AFC circuit } 12 , in which a 4 MHz internal clock synchronized with the horizontal synchronization signal HSYNC is generated
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH