{HEAD ~ The interface circuit} schedules parallel pipeline operations so that one set of data buses can be shared in {TAIL ~ cycles} by several data flows to save chip area and alleviate data congestion 
{ HEAD ~ The interface circuit } schedules parallel pipeline operations so that one set of data buses can be shared in { TAIL ~ cycles } by several data flows to save chip area and alleviate data congestion
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH