an interlayer dielectric layer provided over {HEAD ~ the semiconductor layer} and the non volatile memory transistor with the interlayer dielectric layer being in direct contact with {TAIL ~ a component} of the non volatile memory transistor, 
an interlayer dielectric layer provided over { HEAD ~ the semiconductor layer } and the non volatile memory transistor with the interlayer dielectric layer being in direct contact with { TAIL ~ a component } of the non volatile memory transistor ,
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH