FIG 2 depicts a simple clock tree 14 for delivering a clock signal arriving at its root 19 to several sinks 16 through {HEAD ~ a set} of {TAIL ~ buffers} and inverters 18 provided to fan out the clock signal 
of
FIG 2 depicts a simple clock tree 14 for delivering a clock signal arriving at its root 19 to several sinks 16 through { HEAD ~ a set } of { TAIL ~ buffers } and inverters 18 provided to fan out the clock signal
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH