The control logic circuit is coupled to the first tracking bit line and configured to generate {HEAD ~ the SAE signal} in response to {TAIL ~ the voltage level} on the first tracking bit line 
The control logic circuit is coupled to the first tracking bit line and configured to generate { HEAD ~ the SAE signal } in response to { TAIL ~ the voltage level } on the first tracking bit line
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH