performing {TAIL ~ an analysis} of the IC design to determine maximum and minimum clock signal edge path delays through the clock tree it describes, wherein the analysis includes using the model of {HEAD ~ the macro cells} subtree to determine the clock signals maximum and minimum rising and falling edge delays through the subtree described by the instance 
performing { TAIL ~ an analysis } of the IC design to determine maximum and minimum clock signal edge path delays through the clock tree it describes , wherein the analysis includes using the model of { HEAD ~ the macro cells } subtree to determine the clock signals maximum and minimum rising and falling edge delays through the subtree described by the instance
OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH