At row predecoder 52 1 the input terminals 530 and 531 are controlled by {HEAD ~ address} inputs {TAIL ~ A5} and A6 respectively and the output terminals L0 L3 drive bus 55 to the row decoder block 32 
inputs
At row predecoder 52 1 the input terminals 530 and 531 are controlled by { HEAD ~ address } inputs { TAIL ~ A5 } and A6 respectively and the output terminals L0 L3 drive bus 55 to the row decoder block 32
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH