In one architecture, {HEAD ~ a memory device} includes a memory array for storing data values, {TAIL ~ multiple sensing circuits}, multiple control lines, and an I/O pad 
includes
In one architecture , { HEAD ~ a memory device } includes a memory array for storing data values , { TAIL ~ multiple sensing circuits } , multiple control lines , and an I / O pad
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH