The apparatus 71 wherein {HEAD ~ said processor circuit} is configured to define, as said second meaningful grouping, {TAIL ~ a theme} comprising said at least two patterns 
is configured to define
The apparatus 71 wherein { HEAD ~ said processor circuit } is configured to define , as said second meaningful grouping , { TAIL ~ a theme } comprising said at least two patterns
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH