Referring to FIG 1C, the exposed semiconductor substrate 10 is isotropically etched using {TAIL ~ the hard mask pattern} 12 and {HEAD ~ the spacer} 13 as etch barriers so that sidewalls of the preliminary lower pillar 11B are recessed to a predetermined width 
Referring to FIG 1C , the exposed semiconductor substrate 10 is isotropically etched using { TAIL ~ the hard mask pattern } 12 and { HEAD ~ the spacer } 13 as etch barriers so that sidewalls of the preliminary lower pillar 11B are recessed to a predetermined width
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH