The horizontal synchronization signal {TAIL ~ HSYNC} is supplied to a VCO/AFC circuit 12, in which a 4 MHz internal clock synchronized with {HEAD ~ the horizontal synchronization signal} HSYNC is generated 
The horizontal synchronization signal { TAIL ~ HSYNC } is supplied to a VCO / AFC circuit 12 , in which a 4 MHz internal clock synchronized with { HEAD ~ the horizontal synchronization signal } HSYNC is generated
OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH