The invention provides {TAIL ~ a simple interface circuit} between a large capacity, high speed DRAM and a single port SRAM cache to achieve {HEAD ~ fast cycle memory performance} 
The invention provides { TAIL ~ a simple interface circuit } between a large capacity , high speed DRAM and a single port SRAM cache to achieve { HEAD ~ fast cycle memory performance }
OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD