{TAIL ~ The semiconductor package} 1, wherein each of {HEAD ~ the chips} is configured to have a DRAM+controller structure 
{ TAIL ~ The semiconductor package } 1 , wherein each of { HEAD ~ the chips } is configured to have a DRAM+controller structure
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH