Then the method includes applying a second voltage across the bitline BL and the sourceline SL and applying {HEAD ~ a second gate voltage} across the gate of the semiconductor transistor 22 to allow {TAIL ~ the second voltage} to form a second write current second time duration from the bitline BL to the sourceline SL and writing a second data state to the resistive sense memory cell 10 
to allow
Then the method includes applying a second voltage across the bitline BL and the sourceline SL and applying { HEAD ~ a second gate voltage } across the gate of the semiconductor transistor 22 to allow { TAIL ~ the second voltage } to form a second write current second time duration from the bitline BL to the sourceline SL and writing a second data state to the resistive sense memory cell 10
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH