The switch contains a data processor, having a segmented ring with {HEAD ~ a plurality} of {TAIL ~ dedicated modules} designed to process the data connected through that ring 
of
The switch contains a data processor , having a segmented ring with { HEAD ~ a plurality } of { TAIL ~ dedicated modules } designed to process the data connected through that ring
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH