wherein the second transistor has a control terminal coupling to an output of the decoder, and {HEAD ~ the at least one additional transistor} has {TAIL ~ a control terminal coupling} to an output of the decoder 
has
wherein the second transistor has a control terminal coupling to an output of the decoder , and { HEAD ~ the at least one additional transistor } has { TAIL ~ a control terminal coupling } to an output of the decoder
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH