{TAIL ~ Clock gating} of sub circuits within a processor execution unit responsive to instruction latency counter within {HEAD ~ processor issue circuit} 
{ TAIL ~ Clock gating } of sub circuits within a processor execution unit responsive to instruction latency counter within { HEAD ~ processor issue circuit }
TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD