During each verify cycle, drivers and decoders 130 apply to the control gate of the target memory cell {HEAD ~ a voltage Vvfy} which depends on voltage VW , grounds the source lines, and applies {TAIL ~ a read voltage Vrc} to the column line of the target memory cell 
applies
During each verify cycle , drivers and decoders 130 apply to the control gate of the target memory cell { HEAD ~ a voltage Vvfy } which depends on voltage VW , grounds the source lines , and applies { TAIL ~ a read voltage Vrc } to the column line of the target memory cell
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH