Finally, the memory controller comprises {HEAD ~ a twelfth FF} receiving the output signal of the fourth multiplexer, outputting a write data mask and write data signal, and driven by {TAIL ~ the output signal} of the XOR gate 
driven by
Finally , the memory controller comprises { HEAD ~ a twelfth FF } receiving the output signal of the fourth multiplexer , outputting a write data mask and write data signal , and driven by { TAIL ~ the output signal } of the XOR gate
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH