{HEAD ~ The latter transistor} is controlled by a N channel transistor 315 whose gate electrode is driven by {TAIL ~ the GG reset output pin} of the host controller 104 
{ HEAD ~ The latter transistor } is controlled by a N channel transistor 315 whose gate electrode is driven by { TAIL ~ the GG reset output pin } of the host controller 104
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH