CMOS device using {HEAD ~ additional implant regions} to enhance {TAIL ~ ESD performance} and device manufactured thereby 
to enhance
CMOS device using { HEAD ~ additional implant regions } to enhance { TAIL ~ ESD performance } and device manufactured thereby
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH