At the same time output terminals L1, {TAIL ~ L2} and {HEAD ~ L3} will be at logical 0 state 
At the same time output terminals L1 , { TAIL ~ L2 } and { HEAD ~ L3 } will be at logical 0 state
OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH