{HEAD ~ a processor} operatively coupled to memory, the memory having {TAIL ~ a capability analysis structure} further comprising: 
{ HEAD ~ a processor } operatively coupled to memory , the memory having { TAIL ~ a capability analysis structure } further comprising :
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH