In this circuit, the smaller number in one register is arranged so that the complement thereof is denormalized and added to the subtrahend and {HEAD ~ the result} of {TAIL ~ the addition} is returned to the original register 
of
In this circuit , the smaller number in one register is arranged so that the complement thereof is denormalized and added to the subtrahend and { HEAD ~ the result } of { TAIL ~ the addition } is returned to the original register
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH