Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and {HEAD ~ those signals} described as {TAIL ~ negative logic signals} may be implemented as positive logic signals 
described as
Therefore , in alternate embodiments , those signals described as positive logic signals may be implemented as negative logic signals , and { HEAD ~ those signals } described as { TAIL ~ negative logic signals } may be implemented as positive logic signals
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH