wherein an output signal showing a result of multiplication of said first and second input signals is differentially derived between said collectors or {HEAD ~ drains} of said first and fourth transistors and said collectors or {TAIL ~ drains} of said second and third transistors 
wherein an output signal showing a result of multiplication of said first and second input signals is differentially derived between said collectors or { HEAD ~ drains } of said first and fourth transistors and said collectors or { TAIL ~ drains } of said second and third transistors
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH