{HEAD ~ The processor} assigns each instruction {TAIL ~ a thread ID} and error information as it follows the pipeline 
assigns
{ HEAD ~ The processor } assigns each instruction { TAIL ~ a thread ID } and error information as it follows the pipeline
HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH