The invention provides {HEAD ~ a simple interface circuit} between {TAIL ~ a large capacity, high speed DRAM} and a single port SRAM cache to achieve fast cycle memory performance 
between
The invention provides { HEAD ~ a simple interface circuit } between { TAIL ~ a large capacity , high speed DRAM } and a single port SRAM cache to achieve fast cycle memory performance
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH