In addition, a bus arbiter in {HEAD ~ the node controller} parks {TAIL ~ a data bus} towards a memory subsystem 
parks
In addition , a bus arbiter in { HEAD ~ the node controller } parks { TAIL ~ a data bus } towards a memory subsystem
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH