{HEAD ~ The semiconductor structure} 3 wherein {TAIL ~ the electrical isolation} of the source and drain regions comprises a dielectric region partly surrounding the regions and a dielectric layer under each of the regions 
wherein
{ HEAD ~ The semiconductor structure } 3 wherein { TAIL ~ the electrical isolation } of the source and drain regions comprises a dielectric region partly surrounding the regions and a dielectric layer under each of the regions
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH