The first unit connectable to the wafer voltage source Vb and {HEAD ~ the second unit} connectable to {TAIL ~ a third, collector voltage source Vc} 
connectable to
The first unit connectable to the wafer voltage source Vb and { HEAD ~ the second unit } connectable to { TAIL ~ a third , collector voltage source Vc }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL