A second address compare circuit compares {HEAD ~ a second received address} for the second memory with {TAIL ~ the first redundant address} 
with
A second address compare circuit compares { HEAD ~ a second received address } for the second memory with { TAIL ~ the first redundant address }
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL