{HEAD ~ The device} 1 wherein {TAIL ~ the input conductors} associated with each of the logic blocks receive signals from the first set of conductors 
wherein
{ HEAD ~ The device } 1 wherein { TAIL ~ the input conductors } associated with each of the logic blocks receive signals from the first set of conductors
HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH