The output of the sync mark detector is enabled according to {HEAD ~ the current state} of {TAIL ~ the state machine}, i.e., at a predetermined sample period interval 
of
The output of the sync mark detector is enabled according to { HEAD ~ the current state } of { TAIL ~ the state machine } , i.e. , at a predetermined sample period interval
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH