{TAIL ~ Memory} and circuit for accessing {HEAD ~ data bits} in a memory array in multi data rate operation 
{ TAIL ~ Memory } and circuit for accessing { HEAD ~ data bits } in a memory array in multi data rate operation
TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH