Accordingly, each count register 702 a 702 d accepts and stores the output of the counter 201 at {HEAD ~ every fourth transition} of the sample clock 103 in {TAIL ~ a deceleration} by four embodiment and every Mth transition of the sample clock 103 in a deceleration by M embodiment 
in
Accordingly , each count register 702 a 702 d accepts and stores the output of the counter 201 at { HEAD ~ every fourth transition } of the sample clock 103 in { TAIL ~ a deceleration } by four embodiment and every Mth transition of the sample clock 103 in a deceleration by M embodiment
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH