One aspect of this invention comprises an architecture and circuitry that enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in {HEAD ~ a given column} to {TAIL ~ the bit lines} such as the architecture of FIG 2 of U.S. Pat 
to
One aspect of this invention comprises an architecture and circuitry that enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in { HEAD ~ a given column } to { TAIL ~ the bit lines } such as the architecture of FIG 2 of U.S. Pat
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