A fourth multiplexer is included in {HEAD ~ the memory controller} to receive {TAIL ~ the output signal} of the third multiplexer and the output signal of the eleventh FF 
to receive
A fourth multiplexer is included in { HEAD ~ the memory controller } to receive { TAIL ~ the output signal } of the third multiplexer and the output signal of the eleventh FF
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH