{TAIL ~ A control signal} is generated to control {HEAD ~ the variable delay circuit} so that a delayed test signal jitters 
{ TAIL ~ A control signal } is generated to control { HEAD ~ the variable delay circuit } so that a delayed test signal jitters
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH