{HEAD ~ The device} 1, wherein {TAIL ~ outputs} of each converter are evenly divided into two groups, half being connected to said two multiplexers and half being connected to said first storage register 
wherein
{ HEAD ~ The device } 1 , wherein { TAIL ~ outputs } of each converter are evenly divided into two groups , half being connected to said two multiplexers and half being connected to said first storage register
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH