a second number of {HEAD ~ memory banks} containing {TAIL ~ said words} of said logical vector register circuit; and 
a second number of { HEAD ~ memory banks } containing { TAIL ~ said words } of said logical vector register circuit ; and
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH