The architecture includes a decoding scheme wherein the EEPROM chip has {HEAD ~ a row address bit} which is used for {TAIL ~ the row} decoding also participating in the column decoding process 
is used for
The architecture includes a decoding scheme wherein the EEPROM chip has { HEAD ~ a row address bit } which is used for { TAIL ~ the row } decoding also participating in the column decoding process
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH