A predetermined time after the clock signal on the clock wire terminates, i.e., remains inactive for a predetermined period, the shift/latch control circuit generates a latch signal that can be used to capture {HEAD ~ the data} transmitted over {TAIL ~ the data wire} 
transmitted over
A predetermined time after the clock signal on the clock wire terminates , i.e. , remains inactive for a predetermined period , the shift / latch control circuit generates a latch signal that can be used to capture { HEAD ~ the data } transmitted over { TAIL ~ the data wire }
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