In other embodiments, both processors may be gated in the illustrated manner, or {HEAD ~ any} of {TAIL ~ the other units} shown in FIG 8 may be gated  
of
In other embodiments , both processors may be gated in the illustrated manner , or { HEAD ~ any } of { TAIL ~ the other units } shown in FIG 8 may be gated
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH