Each {HEAD ~ the plurality} of memory modules includes {TAIL ~ a memory MMW transceiver} and a plurality of memory cells 
includes
Each { HEAD ~ the plurality } of memory modules includes { TAIL ~ a memory MMW transceiver } and a plurality of memory cells
OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH