wherein said means for connecting includes DC biasing {HEAD ~ circuitry}, said DC biasing circuitry including four identically sized n channel transistors, {TAIL ~ three of said n channel transistors} receiving a second bias current input and one of said n channel transistors receiving a first bias current input, and three identically sized n channel sink transistors connected to said n channel transistor receiving said first bias current input and to two of said 
wherein said means for connecting includes DC biasing { HEAD ~ circuitry } , said DC biasing circuitry including four identically sized n channel transistors , { TAIL ~ three of said n channel transistors } receiving a second bias current input and one of said n channel transistors receiving a first bias current input , and three identically sized n channel sink transistors connected to said n channel transistor receiving said first bias current input and to two of said
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH