The present invention provides {TAIL ~ a memory controller} for {HEAD ~ a double data rate} synchronous dynamic random access memory  
The present invention provides { TAIL ~ a memory controller } for { HEAD ~ a double data rate } synchronous dynamic random access memory
OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH