{TAIL ~ An internal clock} is synchronized with {HEAD ~ a horizontal synchronization signal} separated in a synchronization separation circuit 10, an H reset signal is generated based thereon in an H countdown circuit 14, and a horizontal synchronization signal is generated based thereon 
{ TAIL ~ An internal clock } is synchronized with { HEAD ~ a horizontal synchronization signal } separated in a synchronization separation circuit 10 , an H reset signal is generated based thereon in an H countdown circuit 14 , and a horizontal synchronization signal is generated based thereon
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH