Here, the VS output circuit 18 internally has a delay circuit, and {HEAD ~ the timing} of {TAIL ~ a vertical synchronization signal} VS to be output is shifted from that of a horizontal synchronization signal HS 
of
Here , the VS output circuit 18 internally has a delay circuit , and { HEAD ~ the timing } of { TAIL ~ a vertical synchronization signal } VS to be output is shifted from that of a horizontal synchronization signal HS
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH