The apparatus further includes an allocation circuit for executing access time allocation with respect to {HEAD ~ a packet processing time} allowed for processing {TAIL ~ each} of the packets 
allowed for processing
The apparatus further includes an allocation circuit for executing access time allocation with respect to { HEAD ~ a packet processing time } allowed for processing { TAIL ~ each } of the packets
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH