determining a portion, in the input logic circuit, in which {TAIL ~ event judgment logic} is to be inserted, on {HEAD ~ the basis} of the signal processing flow detection result; and 
determining a portion , in the input logic circuit , in which { TAIL ~ event judgment logic } is to be inserted , on { HEAD ~ the basis } of the signal processing flow detection result ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH