At a given circuit board position predetermined logic levels are applied to {HEAD ~ the input mode pins} to selectively set {TAIL ~ internal gating} so as to interconnect a desired circuit block to the interface pins of the gate array 
to selectively set
At a given circuit board position predetermined logic levels are applied to { HEAD ~ the input mode pins } to selectively set { TAIL ~ internal gating } so as to interconnect a desired circuit block to the interface pins of the gate array
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH