According to a preferred embodiment of the invention, {HEAD ~ a shift register} is used for {TAIL ~ the memory means}, with data being serially loaded in the shift register for storage 
is used for
According to a preferred embodiment of the invention , { HEAD ~ a shift register } is used for { TAIL ~ the memory means } , with data being serially loaded in the shift register for storage
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH