{HEAD ~ Multiple channels} are accommodated via a channel interface, also controlled by the microprocessor, between external video devices and {TAIL ~ the random access memory} 
controlled between
{ HEAD ~ Multiple channels } are accommodated via a channel interface , also controlled by the microprocessor , between external video devices and { TAIL ~ the random access memory }
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH REL OTH OTH OTH OTH REL OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL