{HEAD ~ Packet communication apparatus} with {TAIL ~ first and second processing circuits} which access a storage circuit during first and second time periods, respectively 
with
{ HEAD ~ Packet communication apparatus } with { TAIL ~ first and second processing circuits } which access a storage circuit during first and second time periods , respectively
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH