Alternatively, when the differential section D2 receives {TAIL ~ all the current} and the differential section D1 is altogether off, the delay is shortest , there being no resistors connected between {HEAD ~ the inputs} 36 and 38 and the gates of the transistors Q9 and Q10 
Alternatively , when the differential section D2 receives { TAIL ~ all the current } and the differential section D1 is altogether off , the delay is shortest , there being no resistors connected between { HEAD ~ the inputs } 36 and 38 and the gates of the transistors Q9 and Q10
OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH