This disclosure describes an efficient architecture for {HEAD ~ an imaging device} that supports {TAIL ~ image registration} for still images and video coding of a video sequence 
supports
This disclosure describes an efficient architecture for { HEAD ~ an imaging device } that supports { TAIL ~ image registration } for still images and video coding of a video sequence
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH