a first DAC for outputting a first control voltage corresponding to {HEAD ~ a first digital value} representative of {TAIL ~ a phase delay}; and 
representative of
a first DAC for outputting a first control voltage corresponding to { HEAD ~ a first digital value } representative of { TAIL ~ a phase delay } ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH