In this manner the memory can be inhibited from accepting and shifting {HEAD ~ data} by preventing {TAIL ~ the clock signals} from enabling the shift register 
by preventing
In this manner the memory can be inhibited from accepting and shifting { HEAD ~ data } by preventing { TAIL ~ the clock signals } from enabling the shift register
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH