As shown in FIG 5, {HEAD ~ the regulator circuit} 51 is controlled by {TAIL ~ three control buses 30a a}, thereby providing triple redundancy 
is controlled by
As shown in FIG 5 , { HEAD ~ the regulator circuit } 51 is controlled by { TAIL ~ three control buses 30a a } , thereby providing triple redundancy
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH