{HEAD ~ The phase detector circuitry} may be configured to generate {TAIL ~ the control signal} based on a first time difference and a second time difference 
configured to generate
{ HEAD ~ The phase detector circuitry } may be configured to generate { TAIL ~ the control signal } based on a first time difference and a second time difference
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH