The processor also determines whether any other switch controller intends to transmit to the determined destination of {TAIL ~ the packet} at {HEAD ~ a given time} 
The processor also determines whether any other switch controller intends to transmit to the determined destination of { TAIL ~ the packet } at { HEAD ~ a given time }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD