Bus masters 14 and 16 may be implemented as {HEAD ~ any} of {TAIL ~ a variety} of differing types of functional devices, such as a central processing unit , a direct memory access controller, any type of processor or any other device that functions as a bus master 
of
Bus masters 14 and 16 may be implemented as { HEAD ~ any } of { TAIL ~ a variety } of differing types of functional devices , such as a central processing unit , a direct memory access controller , any type of processor or any other device that functions as a bus master
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH