{HEAD ~ The memory controller} further comprises a third multiplexer receiving the output signal of the second FF and the output signal of {TAIL ~ the third FF} and controlled by the output signal of the eighth FF 
{ HEAD ~ The memory controller } further comprises a third multiplexer receiving the output signal of the second FF and the output signal of { TAIL ~ the third FF } and controlled by the output signal of the eighth FF
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH