The processor assigns {HEAD ~ each instruction} {TAIL ~ a thread ID} and error information as it follows the pipeline 
The processor assigns { HEAD ~ each instruction } { TAIL ~ a thread ID } and error information as it follows the pipeline
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH