The semiconductor memory device 6, further comprising {HEAD ~ an adjustment transistor} coupled in {TAIL ~ parallel} with the pull down transistor, wherein the adjustment transistor is configured to be controllable by at least one bit of the stack position identifier 
coupled in
The semiconductor memory device 6 , further comprising { HEAD ~ an adjustment transistor } coupled in { TAIL ~ parallel } with the pull down transistor , wherein the adjustment transistor is configured to be controllable by at least one bit of the stack position identifier
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH