{HEAD ~ The SSE} may be provided in {TAIL ~ a pipeline circuit} of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit 
provided in
{ HEAD ~ The SSE } may be provided in { TAIL ~ a pipeline circuit } of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH