In addition, {HEAD ~ a bus arbiter} in {TAIL ~ the node controller} parks a data bus towards a memory subsystem 
in
In addition , { HEAD ~ a bus arbiter } in { TAIL ~ the node controller } parks a data bus towards a memory subsystem
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH