A second address compare circuit compares {TAIL ~ a second received address} for the second memory with {HEAD ~ the first redundant address} 
A second address compare circuit compares { TAIL ~ a second received address } for the second memory with { HEAD ~ the first redundant address }
OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD