One of a reference clock, which is generated by a reference clock generator, and a delay clock, which is obtained by {HEAD ~ a delay circuit} delaying {TAIL ~ the reference clock}, is selected in accordance with delay selection data 
delaying
One of a reference clock , which is generated by a reference clock generator , and a delay clock , which is obtained by { HEAD ~ a delay circuit } delaying { TAIL ~ the reference clock } , is selected in accordance with delay selection data
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH