{HEAD ~ a Dual Port RAM} connected to the single electrical interface, the Dual Port RAM configured to parallelly transfer data through {TAIL ~ the single electrical interface}; and 
{ HEAD ~ a Dual Port RAM } connected to the single electrical interface , the Dual Port RAM configured to parallelly transfer data through { TAIL ~ the single electrical interface } ; and
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH