The latter transistor is controlled by a N channel transistor 315 whose gate electrode is driven by {HEAD ~ the GG reset output pin} of {TAIL ~ the host controller} 104 
of
The latter transistor is controlled by a N channel transistor 315 whose gate electrode is driven by { HEAD ~ the GG reset output pin } of { TAIL ~ the host controller } 104
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH