The switch contains a data processor, having a segmented ring with a plurality of {HEAD ~ dedicated modules} designed to process {TAIL ~ the data} connected through that ring 
designed to process
The switch contains a data processor , having a segmented ring with a plurality of { HEAD ~ dedicated modules } designed to process { TAIL ~ the data } connected through that ring
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH