a third inverted XOR logic gate having as {TAIL ~ inputs} said {HEAD ~ first filtered signal} and said chip sequence, 
as
a third inverted XOR logic gate having as { TAIL ~ inputs } said { HEAD ~ first filtered signal } and said chip sequence ,
OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH