Otherwise, {HEAD ~ a data address} of an identifier for a previously prepared ultimate LRU in {TAIL ~ the cache memory} is transmitted to the CPU at a step  
in
Otherwise , { HEAD ~ a data address } of an identifier for a previously prepared ultimate LRU in { TAIL ~ the cache memory } is transmitted to the CPU at a step
OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH