{HEAD ~ The first programmable delay} receives {TAIL ~ a first set} of one or more bits from the configuration register and a double speed clock signal 
receives
{ HEAD ~ The first programmable delay } receives { TAIL ~ a first set } of one or more bits from the configuration register and a double speed clock signal
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH