Clock gating of {HEAD ~ sub circuits} within {TAIL ~ a processor execution unit} responsive to instruction latency counter within processor issue circuit 
within
Clock gating of { HEAD ~ sub circuits } within { TAIL ~ a processor execution unit } responsive to instruction latency counter within processor issue circuit
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH