A design structure for {HEAD ~ a loop filter} in {TAIL ~ a phase lock loop circuit} comprising a reference precision resistor, a first and second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage 
in
A design structure for { HEAD ~ a loop filter } in { TAIL ~ a phase lock loop circuit } comprising a reference precision resistor , a first and second FET , wherein the gate of the first FET is tied to the gate of the second FET , and a filter capacitor connected to the first FET for producing a capacitor voltage
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH