An arrangement is also provided to enhance deselection speed by discharging {HEAD ~ the base node} of {TAIL ~ the word line driving transistor} 
of
An arrangement is also provided to enhance deselection speed by discharging { HEAD ~ the base node } of { TAIL ~ the word line driving transistor }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL