In addition, {HEAD ~ a bus arbiter} in the node controller parks {TAIL ~ a data bus} towards a memory subsystem 
parks
In addition , { HEAD ~ a bus arbiter } in the node controller parks { TAIL ~ a data bus } towards a memory subsystem
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH