The fourth multiplexer is controlled by the third set of {HEAD ~ one or more bits} from {TAIL ~ the configuration register} 
The fourth multiplexer is controlled by the third set of { HEAD ~ one or more bits } from { TAIL ~ the configuration register }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL