in a first clock cycle, {HEAD ~ old data} are latched into {TAIL ~ the cache memory sense amplifiers}, while new data are latched in the DRAM memory sense amplifiers, 
are latched into
in a first clock cycle , { HEAD ~ old data } are latched into { TAIL ~ the cache memory sense amplifiers } , while new data are latched in the DRAM memory sense amplifiers ,
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH