In {HEAD ~ addition} to the memory 202, {TAIL ~ the processor} 201 can also be connected to at least one interface or other means for displaying, transmitting and receiving data, content or the like 
In { HEAD ~ addition } to the memory 202 , { TAIL ~ the processor } 201 can also be connected to at least one interface or other means for displaying , transmitting and receiving data , content or the like
OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH