At {TAIL ~ the same time} output terminals L1, L2 and {HEAD ~ L3} will be at logical 0 state 
At { TAIL ~ the same time } output terminals L1 , L2 and { HEAD ~ L3 } will be at logical 0 state
OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH