The fourth multiplexer is controlled by {HEAD ~ the third set} of {TAIL ~ one or more bits} from the configuration register 
of
The fourth multiplexer is controlled by { HEAD ~ the third set } of { TAIL ~ one or more bits } from the configuration register
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH