{HEAD ~ Operation} of the semiconductor device having the above described configuration according to {TAIL ~ the exemplary embodiment} will be described in detail with reference to FIGS 4 to 8 
{ HEAD ~ Operation } of the semiconductor device having the above described configuration according to { TAIL ~ the exemplary embodiment } will be described in detail with reference to FIGS 4 to 8
HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH