In the CPU reset circuit of FIG 1, {HEAD ~ the reset signal} provided from watch dog circuit 20 is usually generated for {TAIL ~ a proper time interval}, and therefore presents little problem 
is generated for
In the CPU reset circuit of FIG 1 , { HEAD ~ the reset signal } provided from watch dog circuit 20 is usually generated for { TAIL ~ a proper time interval } , and therefore presents little problem
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH REL OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH