A memory device for storing data into and receiving data from a logical vector register circuit accessed as a first number of {HEAD ~ register subarrays} each containing {TAIL ~ a plurality} of words, said memory device comprising: 
A memory device for storing data into and receiving data from a logical vector register circuit accessed as a first number of { HEAD ~ register subarrays } each containing { TAIL ~ a plurality } of words , said memory device comprising :
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH