One of a reference clock, which is generated by a reference clock generator, and {HEAD ~ a delay clock}, which is obtained by {TAIL ~ a delay circuit} delaying the reference clock, is selected in accordance with delay selection data 
is obtained by
One of a reference clock , which is generated by a reference clock generator , and { HEAD ~ a delay clock } , which is obtained by { TAIL ~ a delay circuit } delaying the reference clock , is selected in accordance with delay selection data
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH