In {TAIL ~ this manner} {HEAD ~ the memory} can be inhibited from accepting and shifting data by preventing the clock signals from enabling the shift register 
In
In { TAIL ~ this manner } { HEAD ~ the memory } can be inhibited from accepting and shifting data by preventing the clock signals from enabling the shift register
REL TAIL TAIL TAIL TAIL TAIL TAIL HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH