A refresh counter circuit 5 or 6, wherein each of said path switches comprises {HEAD ~ a complementary type transfer gate} including PMOS and {TAIL ~ NMOS} 
including
A refresh counter circuit 5 or 6 , wherein each of said path switches comprises { HEAD ~ a complementary type transfer gate } including PMOS and { TAIL ~ NMOS }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH TAIL TAIL TAIL TAIL TAIL