Additionally, the memory controller comprises a second multiplexer receiving the output signal of the seventh FF and {HEAD ~ the output signal} of {TAIL ~ the ninth FF} and controlled by a third set of one or more bits from the configuration register 
of
Additionally , the memory controller comprises a second multiplexer receiving the output signal of the seventh FF and { HEAD ~ the output signal } of { TAIL ~ the ninth FF } and controlled by a third set of one or more bits from the configuration register
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH