A semiconductor package facilitates package connection due to different locations of input/output pads in {HEAD ~ each interlayer die} depending on {TAIL ~ coding information} in a multi chip package 
depending on
A semiconductor package facilitates package connection due to different locations of input / output pads in { HEAD ~ each interlayer die } depending on { TAIL ~ coding information } in a multi chip package
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH