The feedback stage is operable in {HEAD ~ at least two feedback modes} to hold the output bit state during the second clock state of {TAIL ~ the clock signal} 
The feedback stage is operable in { HEAD ~ at least two feedback modes } to hold the output bit state during the second clock state of { TAIL ~ the clock signal }
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL