As such, {TAIL ~ the DQ signal} may represent {HEAD ~ any signal} internal to the chip that may be mapped to one of eight pads or interconnect positions on a given memory device 
As such , { TAIL ~ the DQ signal } may represent { HEAD ~ any signal } internal to the chip that may be mapped to one of eight pads or interconnect positions on a given memory device
OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH