This disclosure refers to multiprocessor systems having {TAIL ~ individual cache memories} including {HEAD ~ means} to keep the cache memories coherent 
This disclosure refers to multiprocessor systems having { TAIL ~ individual cache memories } including { HEAD ~ means } to keep the cache memories coherent
OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH