In the circuit of the second aspect, if {HEAD ~ the first and second input signals} are defined as {TAIL ~ Vx} and Vy, the gate of the first FET receives , the gate of the second FET receives Vx +vVy !, the gate of the third FET receives uVx +Vy !, and the gate of the fourth FET receives Vx +Vy !, where u, v and w are constants 
are defined as
In the circuit of the second aspect , if { HEAD ~ the first and second input signals } are defined as { TAIL ~ Vx } and Vy , the gate of the first FET receives , the gate of the second FET receives Vx + vVy ! , the gate of the third FET receives uVx + Vy ! , and the gate of the fourth FET receives Vx + Vy ! , where u , v and w are constants
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH