{HEAD ~ The sampling} and holding of {TAIL ~ bits states} are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines 
of
{ HEAD ~ The sampling } and holding of { TAIL ~ bits states } are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH