{HEAD ~ The lock} includes {TAIL ~ a counter} and a gate for inhibiting clock pulses to the memory element until a predetermined number of control pulses have been received to initiate a read/write operation 
includes
{ HEAD ~ The lock } includes { TAIL ~ a counter } and a gate for inhibiting clock pulses to the memory element until a predetermined number of control pulses have been received to initiate a read / write operation
HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH