The memory device 1, wherein K is two, and wherein a first control line is associated with a rising edge of the clock signal and {HEAD ~ a second control line} is associated with {TAIL ~ a falling edge} of the clock signal 
is associated with
The memory device 1 , wherein K is two , and wherein a first control line is associated with a rising edge of the clock signal and { HEAD ~ a second control line } is associated with { TAIL ~ a falling edge } of the clock signal
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH