determining {HEAD ~ a portion}, in {TAIL ~ the input logic circuit}, in which event judgment logic is to be inserted, on the basis of the signal processing flow detection result; and 
in
determining { HEAD ~ a portion } , in { TAIL ~ the input logic circuit } , in which event judgment logic is to be inserted , on the basis of the signal processing flow detection result ; and
OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH