A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of {HEAD ~ channel regions} between {TAIL ~ the bitlines} 
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A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of { HEAD ~ channel regions } between { TAIL ~ the bitlines }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL