A high speed, low power Static Random Access Memory Array, which includes {HEAD ~ a 4T cell} with {TAIL ~ two integrated Schottky Barrier Diodes} is disclosed 
with
A high speed , low power Static Random Access Memory Array , which includes { HEAD ~ a 4 T cell } with { TAIL ~ two integrated Schottky Barrier Diodes } is disclosed
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH