{HEAD ~ The memory core} includes vertical electrically erasable and programmable read only memories cells having, for example, a stacked gate or {TAIL ~ a split channel configuration} 
{ HEAD ~ The memory core } includes vertical electrically erasable and programmable read only memories cells having , for example , a stacked gate or { TAIL ~ a split channel configuration }
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL