A non volatile semiconductor memory device that includes an address buffer block, {TAIL ~ a matrix} of {HEAD ~ memory cells}, and an output buffer block 
A non volatile semiconductor memory device that includes an address buffer block , { TAIL ~ a matrix } of { HEAD ~ memory cells } , and an output buffer block
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH