in a first clock cycle, {TAIL ~ old data} are latched into the cache memory sense amplifiers, while {HEAD ~ new data} are latched in the DRAM memory sense amplifiers, 
in a first clock cycle , { TAIL ~ old data } are latched into the cache memory sense amplifiers , while { HEAD ~ new data } are latched in the DRAM memory sense amplifiers ,
OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH