{HEAD ~ A refresh counter circuit} 5 or 6, wherein each of said path switches comprises a complementary type transfer gate including PMOS and {TAIL ~ NMOS} 
{ HEAD ~ A refresh counter circuit } 5 or 6 , wherein each of said path switches comprises a complementary type transfer gate including PMOS and { TAIL ~ NMOS }
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL