The processor also determines whether any other switch controller intends to transmit to {HEAD ~ the determined destination} of the packet at {TAIL ~ a given time} 
at
The processor also determines whether any other switch controller intends to transmit to { HEAD ~ the determined destination } of the packet at { TAIL ~ a given time }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL