When a low logic level is asserted in device A, the portion of the circuit in device B causes {HEAD ~ a low logic level} to be asserted in {TAIL ~ device B} at the converted level 
to be asserted in
When a low logic level is asserted in device A , the portion of the circuit in device B causes { HEAD ~ a low logic level } to be asserted in { TAIL ~ device B } at the converted level
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH