{HEAD ~ A video operational amplifier} and video buffer 318 is provided between the FPGA or {TAIL ~ ASIC} 302 and a video analog to digital converter 316, for enhancing the video signals and implementing the video gains 
is provided between
{ HEAD ~ A video operational amplifier } and video buffer 318 is provided between the FPGA or { TAIL ~ ASIC } 302 and a video analog to digital converter 316 , for enhancing the video signals and implementing the video gains
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