A predetermined voltage generated by the second FET is applied to {HEAD ~ the gate} of {TAIL ~ the first FET} to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor 
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A predetermined voltage generated by the second FET is applied to { HEAD ~ the gate } of { TAIL ~ the first FET } to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH