The multiple read/write pipelines share a read circuit and {HEAD ~ a write circuit} to reduce {TAIL ~ the circuit area} of each pipeline and the circuit area of the memory as a whole 
to reduce
The multiple read / write pipelines share a read circuit and { HEAD ~ a write circuit } to reduce { TAIL ~ the circuit area } of each pipeline and the circuit area of the memory as a whole
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH