The device 1, further comprising {HEAD ~ a gate pad} and a data pad on {TAIL ~ the first substrate} 
on
The device 1 , further comprising { HEAD ~ a gate pad } and a data pad on { TAIL ~ the first substrate }
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL