The circuit 1 in which the interpreter means comprises a microprocessor for evaluating the binary states of the input signal and {HEAD ~ the beginning} and end of {TAIL ~ the counting interval} and adjusting the pulse count in response 
of
The circuit 1 in which the interpreter means comprises a microprocessor for evaluating the binary states of the input signal and { HEAD ~ the beginning } and end of { TAIL ~ the counting interval } and adjusting the pulse count in response
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH