The apparatus includes {HEAD ~ a buffer} utilized for buffering an input signal and then outputting {TAIL ~ an output signal}; a digital to analog converter utilized for converting a digital value representative of phase delay into a corresponding control voltage and outputting a control voltage; and a variable capacitor that has a capacitance value controlled by the control voltage 
utilized for outputting
The apparatus includes { HEAD ~ a buffer } utilized for buffering an input signal and then outputting { TAIL ~ an output signal } ; a digital to analog converter utilized for converting a digital value representative of phase delay into a corresponding control voltage and outputting a control voltage ; and a variable capacitor that has a capacitance value controlled by the control voltage
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH