{HEAD ~ The LSSD scan paths} of each logic circuit chip on {TAIL ~ a circuit module} are connected to additional test circuit chips on the same module 
on
{ HEAD ~ The LSSD scan paths } of each logic circuit chip on { TAIL ~ a circuit module } are connected to additional test circuit chips on the same module
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH