Otherwise, a data address of an identifier for a previously prepared ultimate LRU in the cache memory is transmitted to {HEAD ~ the CPU} at {TAIL ~ a step}  
Otherwise , a data address of an identifier for a previously prepared ultimate LRU in the cache memory is transmitted to { HEAD ~ the CPU } at { TAIL ~ a step }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH