{HEAD ~ The semiconductor device} 1, wherein {TAIL ~ the additional leads} further include a fourth lead between the second and third leads 
wherein
{ HEAD ~ The semiconductor device } 1 , wherein { TAIL ~ the additional leads } further include a fourth lead between the second and third leads
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH