However, during the integration time, {HEAD ~ the gate} 205 is kept at surface potential, in {TAIL ~ order} to obtain the noise advantages of a virtual floating gate 205 
is kept in
However , during the integration time , { HEAD ~ the gate } 205 is kept at surface potential , in { TAIL ~ order } to obtain the noise advantages of a virtual floating gate 205
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH REL REL OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH