The signal “MODE” is set to a logical “low” level when the clock signal arrives and {TAIL ~ the entire buck boost converter} is configured in {HEAD ~ buck mode} of operation 
The signal “ MODE ” is set to a logical “ low ” level when the clock signal arrives and { TAIL ~ the entire buck boost converter } is configured in { HEAD ~ buck mode } of operation
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH