This disclosure refers to multiprocessor systems having individual cache memories including {HEAD ~ means} to keep {TAIL ~ the cache memories} coherent 
to keep
This disclosure refers to multiprocessor systems having individual cache memories including { HEAD ~ means } to keep { TAIL ~ the cache memories } coherent
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH