In the embodiment illustrated in FIG 2, region 0 includes mask bits 3:0 and is the least significant region; region 1 includes mask bits 7:4 and is more significant than region 0 and less significant than regions 2 and 3; region 2 includes {TAIL ~ mask bits} 11:8 and is more significant than regions 0 and 1 and less significant than region 3; and region 3 includes mask bits 15:12 and is {HEAD ~ the most significant region} 
In the embodiment illustrated in FIG 2 , region 0 includes mask bits 3:0 and is the least significant region ; region 1 includes mask bits 7:4 and is more significant than region 0 and less significant than regions 2 and 3 ; region 2 includes { TAIL ~ mask bits } 11:8 and is more significant than regions 0 and 1 and less significant than region 3 ; and region 3 includes mask bits 15:12 and is { HEAD ~ the most significant region }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD