a second number of memory banks containing {HEAD ~ said words} of {TAIL ~ said logical vector register circuit}; and 
of
a second number of memory banks containing { HEAD ~ said words } of { TAIL ~ said logical vector register circuit } ; and
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH