The architecture includes {HEAD ~ a decoding scheme} wherein {TAIL ~ the EEPROM chip} has a row address bit which is used for the row decoding also participating in the column decoding process 
wherein
The architecture includes { HEAD ~ a decoding scheme } wherein { TAIL ~ the EEPROM chip } has a row address bit which is used for the row decoding also participating in the column decoding process
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH