The interface circuit schedules parallel pipeline operations so that {HEAD ~ one set} of data buses can be shared in cycles by {TAIL ~ several data flows} to save chip area and alleviate data congestion 
shared by
The interface circuit schedules parallel pipeline operations so that { HEAD ~ one set } of data buses can be shared in cycles by { TAIL ~ several data flows } to save chip area and alleviate data congestion
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH