{HEAD ~ A memory circuit} which has both RAM cells and ROM cells along a common row has {TAIL ~ a ROM cell} which is directly connected to the word line for the row but which is not enabled when a logic state opposite to that represented by the ROM cell is attempted to be written into the ROM cell 
has
{ HEAD ~ A memory circuit } which has both RAM cells and ROM cells along a common row has { TAIL ~ a ROM cell } which is directly connected to the word line for the row but which is not enabled when a logic state opposite to that represented by the ROM cell is attempted to be written into the ROM cell
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH