The phase detector circuitry may be configured to generate {HEAD ~ the control signal} based on {TAIL ~ a first time difference} and a second time difference 
based on
The phase detector circuitry may be configured to generate { HEAD ~ the control signal } based on { TAIL ~ a first time difference } and a second time difference
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH