The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by {HEAD ~ several data flows} to save {TAIL ~ chip area} and alleviate data congestion 
to save
The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by { HEAD ~ several data flows } to save { TAIL ~ chip area } and alleviate data congestion
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH