The phase detector circuitry may be configured to generate {HEAD ~ the control signal} based on a first time difference and {TAIL ~ a second time difference} 
based on
The phase detector circuitry may be configured to generate { HEAD ~ the control signal } based on a first time difference and { TAIL ~ a second time difference }
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL