{HEAD ~ a second number} of {TAIL ~ memory banks} containing said words of said logical vector register circuit; and 
of
{ HEAD ~ a second number } of { TAIL ~ memory banks } containing said words of said logical vector register circuit ; and
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH