{TAIL ~ A memory controller} for {HEAD ~ a double data rate} synchronous dynamic random access memory , the memory controller comprising: 
{ TAIL ~ A memory controller } for { HEAD ~ a double data rate } synchronous dynamic random access memory , the memory controller comprising :
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH