The processor also determines whether {HEAD ~ any other switch controller} intends to transmit to {TAIL ~ the determined destination} of the packet at a given time 
intends to transmit to
The processor also determines whether { HEAD ~ any other switch controller } intends to transmit to { TAIL ~ the determined destination } of the packet at a given time
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH