Operation of {HEAD ~ the semiconductor device} having {TAIL ~ the above described configuration} according to the exemplary embodiment will be described in detail with reference to FIGS 4 to 8 
having
Operation of { HEAD ~ the semiconductor device } having { TAIL ~ the above described configuration } according to the exemplary embodiment will be described in detail with reference to FIGS 4 to 8
OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH