One of a reference clock, which is generated by a reference clock generator, and a delay clock, which is obtained by a delay circuit delaying {HEAD ~ the reference clock}, is selected in accordance with {TAIL ~ delay selection data} 
One of a reference clock , which is generated by a reference clock generator , and a delay clock , which is obtained by a delay circuit delaying { HEAD ~ the reference clock } , is selected in accordance with { TAIL ~ delay selection data }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL