{TAIL ~ The first programmable delay} receives a first set of {HEAD ~ one or more bits} from the configuration register and a double speed clock signal 
{ TAIL ~ The first programmable delay } receives a first set of { HEAD ~ one or more bits } from the configuration register and a double speed clock signal
TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH