The device 1, wherein {HEAD ~ outputs} of each converter are evenly divided into {TAIL ~ two groups}, half being connected to said two multiplexers and half being connected to said first storage register 
are evenly divided into
The device 1 , wherein { HEAD ~ outputs } of each converter are evenly divided into { TAIL ~ two groups } , half being connected to said two multiplexers and half being connected to said first storage register
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH