The multiple read/write {HEAD ~ pipelines} share a read circuit and {TAIL ~ a write circuit} to reduce the circuit area of each pipeline and the circuit area of the memory as a whole 
share
The multiple read / write { HEAD ~ pipelines } share a read circuit and { TAIL ~ a write circuit } to reduce the circuit area of each pipeline and the circuit area of the memory as a whole
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH