In the illustrated embodiment the video data acquisition signals includes a horizontal reset, a vertical reset, {TAIL ~ a field}, a write enable and {HEAD ~ a pixel clock signal} 
In the illustrated embodiment the video data acquisition signals includes a horizontal reset , a vertical reset , { TAIL ~ a field } , a write enable and { HEAD ~ a pixel clock signal }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD