instruction address translation means coupled to said instruction fetch unit for translating only logical addresses for reading out instruction words stored in {TAIL ~ the MMU} into corresponding real addresses of {HEAD ~ the MMU}; and 
instruction address translation means coupled to said instruction fetch unit for translating only logical addresses for reading out instruction words stored in { TAIL ~ the MMU } into corresponding real addresses of { HEAD ~ the MMU } ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH