a first counter receiving {HEAD ~ an output} of {TAIL ~ said first multiplexer} and outputting a first count signal, 
of
a first counter receiving { HEAD ~ an output } of { TAIL ~ said first multiplexer } and outputting a first count signal ,
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH