performing an analysis of the IC design to determine maximum and minimum clock signal edge path delays through {HEAD ~ the clock tree} it describes, wherein the analysis includes using the model of the macro cells subtree to determine the clock signals maximum and minimum rising and falling edge delays through the subtree described by {TAIL ~ the instance} 
performing an analysis of the IC design to determine maximum and minimum clock signal edge path delays through { HEAD ~ the clock tree } it describes , wherein the analysis includes using the model of the macro cells subtree to determine the clock signals maximum and minimum rising and falling edge delays through the subtree described by { TAIL ~ the instance }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL