a plurality of bus mastering modules, wherein each of said bus mastering modules includes a subcircuit which, before an address directed to one of said memory modules is placed on said system bus, monitors said address requested by {TAIL ~ said bus mastering modules}, and wherein said subcircuit grants the local bus mastering circuit control of the system bus for a next data transfer cycle if a current memory address is to {HEAD ~ a different memory module} than a previous address request 
a plurality of bus mastering modules , wherein each of said bus mastering modules includes a subcircuit which , before an address directed to one of said memory modules is placed on said system bus , monitors said address requested by { TAIL ~ said bus mastering modules } , and wherein said subcircuit grants the local bus mastering circuit control of the system bus for a next data transfer cycle if a current memory address is to { HEAD ~ a different memory module } than a previous address request
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