Otherwise, a data address of {TAIL ~ an identifier} for a previously prepared ultimate LRU in the cache memory is transmitted to the CPU at {HEAD ~ a step}  
Otherwise , a data address of { TAIL ~ an identifier } for a previously prepared ultimate LRU in the cache memory is transmitted to the CPU at { HEAD ~ a step }
OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH