Otherwise, a data address of an identifier for a previously prepared ultimate LRU in {HEAD ~ the cache memory} is transmitted to the CPU at {TAIL ~ a step}  
Otherwise , a data address of an identifier for a previously prepared ultimate LRU in { HEAD ~ the cache memory } is transmitted to the CPU at { TAIL ~ a step }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH