The method 11 wherein the CMOS device includes a memory core of substantially replicated cells and includes a periphery region that includes control logic, the first region extending entirely within the memory core, and {HEAD ~ the second region} extending partially within the memory core and partially within {TAIL ~ the periphery region} 
extending partially within
The method 11 wherein the CMOS device includes a memory core of substantially replicated cells and includes a periphery region that includes control logic , the first region extending entirely within the memory core , and { HEAD ~ the second region } extending partially within the memory core and partially within { TAIL ~ the periphery region }
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