The memory device 14, wherein said {HEAD ~ first column selection circuitry} is selectively controlled by a row address bit and {TAIL ~ a column address bit}; and 
is selectively controlled by
The memory device 14 , wherein said { HEAD ~ first column selection circuitry } is selectively controlled by a row address bit and { TAIL ~ a column address bit } ; and
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH