When a low logic level is asserted in device A, the portion of the circuit in device B causes {HEAD ~ a low logic level} to be asserted in device B at {TAIL ~ the converted level} 
to be asserted at
When a low logic level is asserted in device A , the portion of the circuit in device B causes { HEAD ~ a low logic level } to be asserted in device B at { TAIL ~ the converted level }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL