a Dual Port RAM connected to the single electrical interface, {HEAD ~ the Dual Port RAM} configured to parallelly transfer {TAIL ~ data} through the single electrical interface; and 
configured to parallelly transfer
a Dual Port RAM connected to the single electrical interface , { HEAD ~ the Dual Port RAM } configured to parallelly transfer { TAIL ~ data } through the single electrical interface ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH