A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of {HEAD ~ the instructions} located in {TAIL ~ the main memory} , the other for storing a portion of the operand data located in main memory 
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A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of { HEAD ~ the instructions } located in { TAIL ~ the main memory } , the other for storing a portion of the operand data located in main memory
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH