four 32 bit registers designated {HEAD ~ A}, B, {TAIL ~ C} and D, wherein each register holds a value; and 
four 32 bit registers designated { HEAD ~ A } , B , { TAIL ~ C } and D , wherein each register holds a value ; and
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH