At a given circuit board position predetermined logic levels are applied to {TAIL ~ the input mode pins} to selectively set internal gating so as to interconnect {HEAD ~ a desired circuit block} to the interface pins of the gate array 
At a given circuit board position predetermined logic levels are applied to { TAIL ~ the input mode pins } to selectively set internal gating so as to interconnect { HEAD ~ a desired circuit block } to the interface pins of the gate array
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH