The delay can further be reduced by reducing the gate widths of the differential transistors Q9 and {HEAD ~ Q10} in {TAIL ~ the differential section D2} relative to the gate widths of the differential transistors Q7 and Q8 in the first differential section D1 
in
The delay can further be reduced by reducing the gate widths of the differential transistors Q9 and { HEAD ~ Q10 } in { TAIL ~ the differential section D2 } relative to the gate widths of the differential transistors Q7 and Q8 in the first differential section D1
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH