The semiconductor package 1, wherein {HEAD ~ each} of the chips is configured to have {TAIL ~ a DRAM+controller structure} 
is configured to have
The semiconductor package 1 , wherein { HEAD ~ each } of the chips is configured to have { TAIL ~ a DRAM+controller structure }
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL