{HEAD ~ address decoder} means responsive to {TAIL ~ one portion} of said logical address in said register for selecting and reading out to said TLB a set having mT compartments in said TLB, 
responsive to
{ HEAD ~ address decoder } means responsive to { TAIL ~ one portion } of said logical address in said register for selecting and reading out to said TLB a set having mT compartments in said TLB ,
HEAD HEAD HEAD HEAD HEAD HEAD OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH