During each verify cycle, drivers and decoders 130 apply to the control gate of the target memory cell a voltage Vvfy which depends on voltage VW , grounds the source lines, and applies a read voltage Vrc to {HEAD ~ the column line} of {TAIL ~ the target memory cell} 
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During each verify cycle , drivers and decoders 130 apply to the control gate of the target memory cell a voltage Vvfy which depends on voltage VW , grounds the source lines , and applies a read voltage Vrc to { HEAD ~ the column line } of { TAIL ~ the target memory cell }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL