The phase generation circuitry may include a plurality of {HEAD ~ controllable delay stages} arranged in {TAIL ~ series} and phase detector circuitry 
arranged in
The phase generation circuitry may include a plurality of { HEAD ~ controllable delay stages } arranged in { TAIL ~ series } and phase detector circuitry
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH