A processor 19 is shown for configuring {HEAD ~ the arbiter} through {TAIL ~ a bus} 17 
through
A processor 19 is shown for configuring { HEAD ~ the arbiter } through { TAIL ~ a bus } 17
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH