In this circuit, {TAIL ~ the smaller number} in one register is arranged so that the complement thereof is denormalized and added to the subtrahend and the result of the addition is returned to {HEAD ~ the original register} 
In this circuit , { TAIL ~ the smaller number } in one register is arranged so that the complement thereof is denormalized and added to the subtrahend and the result of the addition is returned to { HEAD ~ the original register }
OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD