A computer aided clock tree synthesis tool that designs a clock tree tries to position the clock trees buffers or inverters 18 to equalize path distances between {TAIL ~ the clock trees} root 19 and {HEAD ~ all sinks} 16 to help ensure that clock signal edges will arrive at all sinks 16 at substantially the same time 
A computer aided clock tree synthesis tool that designs a clock tree tries to position the clock trees buffers or inverters 18 to equalize path distances between { TAIL ~ the clock trees } root 19 and { HEAD ~ all sinks } 16 to help ensure that clock signal edges will arrive at all sinks 16 at substantially the same time
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH