a logical address register responsive to {HEAD ~ a logical address} from its respective fetch unit for holding said logical address, the latter comprising {TAIL ~ a page or segment name} plus a displacement, 
a logical address register responsive to { HEAD ~ a logical address } from its respective fetch unit for holding said logical address , the latter comprising { TAIL ~ a page or segment name } plus a displacement ,
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH