In {HEAD ~ another embodiment}, {TAIL ~ a latency} of a DRAM or SRAM is adjusted based on the SPID 
In { HEAD ~ another embodiment } , { TAIL ~ a latency } of a DRAM or SRAM is adjusted based on the SPID
OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH