An arithmetic logic unit is arranged to receive the signals from the registers and to add {HEAD ~ the numbers} together to form {TAIL ~ a resultant} 
together to form
An arithmetic logic unit is arranged to receive the signals from the registers and to add { HEAD ~ the numbers } together to form { TAIL ~ a resultant }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL