said {HEAD ~ system bus} for enabling communication between said processor means, said {TAIL ~ cache means}, said interface means and said main memory means 
said { HEAD ~ system bus } for enabling communication between said processor means , said { TAIL ~ cache means } , said interface means and said main memory means
OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH