wherein a predetermined voltage generated by the second field effect transistor is applied to the gate of the first field effect transistor to set a bias point of the first field effect transistor such that the first field effect {HEAD ~ transistor comprises characteristics} of {TAIL ~ an integrated precision resistor} 
of
wherein a predetermined voltage generated by the second field effect transistor is applied to the gate of the first field effect transistor to set a bias point of the first field effect transistor such that the first field effect { HEAD ~ transistor comprises characteristics } of { TAIL ~ an integrated precision resistor }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL