address decoder means responsive to one portion of said logical address in said register for selecting and reading out to said TLB a set having {HEAD ~ mT compartments} in said {TAIL ~ TLB}, 
in
address decoder means responsive to one portion of said logical address in said register for selecting and reading out to said TLB a set having { HEAD ~ mT compartments } in said { TAIL ~ TLB } ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL OTH TAIL TAIL TAIL TAIL TAIL OTH