The apparatus 1 wherein {HEAD ~ said load bank} comprises {TAIL ~ a plurality} of resistors in selective parallel interconnection 
comprises
The apparatus 1 wherein { HEAD ~ said load bank } comprises { TAIL ~ a plurality } of resistors in selective parallel interconnection
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH