{HEAD ~ the first circuit} is coupled to the oscillator through the second input node and configured for detecting {TAIL ~ a phase/frequency difference} between the externally provided clock signal and an internal clock signal to be generated by the oscillator, and 
configured for detecting
{ HEAD ~ the first circuit } is coupled to the oscillator through the second input node and configured for detecting { TAIL ~ a phase / frequency difference } between the externally provided clock signal and an internal clock signal to be generated by the oscillator , and
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH