Extra latency is added between the time {TAIL ~ a memory controller} issues a write instruction and the time the data is transferred on {HEAD ~ the data bus} 
Extra latency is added between the time { TAIL ~ a memory controller } issues a write instruction and the time the data is transferred on { HEAD ~ the data bus }
OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD