A device includes a memory cell array to store data, a register to store test data, and a decision circuit to invert {HEAD ~ the test data} and to determine a failure of at least one memory cell within the memory cell array responsive to the data, the test data, and {TAIL ~ the inverted test data} 
A device includes a memory cell array to store data , a register to store test data , and a decision circuit to invert { HEAD ~ the test data } and to determine a failure of at least one memory cell within the memory cell array responsive to the data , the test data , and { TAIL ~ the inverted test data }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL