The feedback stage is operable in at least two feedback modes to hold the output bit state during {HEAD ~ the second clock state} of {TAIL ~ the clock signal} 
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The feedback stage is operable in at least two feedback modes to hold the output bit state during { HEAD ~ the second clock state } of { TAIL ~ the clock signal }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL