a counter which is reset when {HEAD ~ a signal} indicating writing of data in the memory is detected to output {TAIL ~ a counter signal} when a predetermined value has been counted 
is detected to output
a counter which is reset when { HEAD ~ a signal } indicating writing of data in the memory is detected to output { TAIL ~ a counter signal } when a predetermined value has been counted
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH