{HEAD ~ Memory controller} 801 within {TAIL ~ memory subsystem} 800 receives a command from the address switch via unidirectional bus 802, also labeled as bus AInX, through a number of latches FD 803, which is merely a fixed delay pipe 
within
{ HEAD ~ Memory controller } 801 within { TAIL ~ memory subsystem } 800 receives a command from the address switch via unidirectional bus 802 , also labeled as bus AInX , through a number of latches FD 803 , which is merely a fixed delay pipe
HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH