analyzing a signal processing flow in {TAIL ~ an area} from which {HEAD ~ the asynchronous element} in the logic circuit is excluded 
analyzing a signal processing flow in { TAIL ~ an area } from which { HEAD ~ the asynchronous element } in the logic circuit is excluded
OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH