The latch 62 is reset by the RUN signal and is gated to receive {HEAD ~ data} from {TAIL ~ the data BUS} under control of the signal I63 
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The latch 62 is reset by the RUN signal and is gated to receive { HEAD ~ data } from { TAIL ~ the data BUS } under control of the signal I63
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH