Each {HEAD ~ the plurality} of memory modules includes a memory MMW transceiver and {TAIL ~ a plurality} of memory cells 
includes
Each { HEAD ~ the plurality } of memory modules includes a memory MMW transceiver and { TAIL ~ a plurality } of memory cells
OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH REL OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH