The latched binary states of {HEAD ~ the input signal} and {TAIL ~ the pulse count} of the digital counter are evaluated by an interpreter such as logic circuitry or a microprocessor 
The latched binary states of { HEAD ~ the input signal } and { TAIL ~ the pulse count } of the digital counter are evaluated by an interpreter such as logic circuitry or a microprocessor
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH