The delay can further be reduced by reducing the gate widths of the differential transistors Q9 and Q10 in the differential section D2 relative to {HEAD ~ the gate widths} of the differential transistors Q7 and {TAIL ~ Q8} in the first differential section D1 
of
The delay can further be reduced by reducing the gate widths of the differential transistors Q9 and Q10 in the differential section D2 relative to { HEAD ~ the gate widths } of the differential transistors Q7 and { TAIL ~ Q8 } in the first differential section D1
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH