{HEAD ~ The control circuit} may be configured to generate {TAIL ~ a control signal} in response to a data signal, a half rate clock signal, and a quadrature of the half rate clock signal 
configured to generate
{ HEAD ~ The control circuit } may be configured to generate { TAIL ~ a control signal } in response to a data signal , a half rate clock signal , and a quadrature of the half rate clock signal
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH