said system bus for enabling {TAIL ~ communication} between {HEAD ~ said processor means}, said cache means, said interface means and said main memory means 
said system bus for enabling { TAIL ~ communication } between { HEAD ~ said processor means } , said cache means , said interface means and said main memory means
OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH