In {TAIL ~ this manner}, {HEAD ~ a command} sent by the address switch experiences a fixed number of cycles of delay before the command is made available to the memory controller 
In
In { TAIL ~ this manner } , { HEAD ~ a command } sent by the address switch experiences a fixed number of cycles of delay before the command is made available to the memory controller
REL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH