The latched binary states of the input signal and the pulse count of the digital counter are evaluated by {HEAD ~ an interpreter} such as {TAIL ~ logic circuitry} or a microprocessor 
such as
The latched binary states of the input signal and the pulse count of the digital counter are evaluated by { HEAD ~ an interpreter } such as { TAIL ~ logic circuitry } or a microprocessor
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH