Upon {HEAD ~ the determination} of {TAIL ~ a branch misprediction}, a processor may ease the task of flushing its pipeline of erroneously fetched and speculatively executed instructions by continuing normal execution for only several cycles, and utilizing existing hardware that handles pipeline flushes in the event of exceptions 
of
Upon { HEAD ~ the determination } of { TAIL ~ a branch misprediction } , a processor may ease the task of flushing its pipeline of erroneously fetched and speculatively executed instructions by continuing normal execution for only several cycles , and utilizing existing hardware that handles pipeline flushes in the event of exceptions
OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH