In this circuit, the smaller number in one register is arranged so that {HEAD ~ the complement} thereof is denormalized and added to {TAIL ~ the subtrahend} and the result of the addition is returned to the original register 
added to
In this circuit , the smaller number in one register is arranged so that { HEAD ~ the complement } thereof is denormalized and added to { TAIL ~ the subtrahend } and the result of the addition is returned to the original register
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH