The circuit 1 in which the interpreter means comprises {HEAD ~ a microprocessor} for evaluating {TAIL ~ the binary states} of the input signal and the beginning and end of the counting interval and adjusting the pulse count in response 
for evaluating
The circuit 1 in which the interpreter means comprises { HEAD ~ a microprocessor } for evaluating { TAIL ~ the binary states } of the input signal and the beginning and end of the counting interval and adjusting the pulse count in response
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH