A plurality of integrated circuit features are provided in the context of an array of memory cells including {HEAD ~ a plurality} of {TAIL ~ word lines} and a plurality of bit lines 
of
A plurality of integrated circuit features are provided in the context of an array of memory cells including { HEAD ~ a plurality } of { TAIL ~ word lines } and a plurality of bit lines
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH