{TAIL ~ The circuit} 1 in which {HEAD ~ the interpreter} means comprises a microprocessor for evaluating the binary states of the input signal and the beginning and end of the counting interval and adjusting the pulse count in response 
in
{ TAIL ~ The circuit } 1 in which { HEAD ~ the interpreter } means comprises a microprocessor for evaluating the binary states of the input signal and the beginning and end of the counting interval and adjusting the pulse count in response
TAIL TAIL TAIL TAIL TAIL TAIL OTH REL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH