According to the present invention there is provided a memory address control apparatus, for a data processor using a virtual memory technique, is connected to a main memory unit and {HEAD ~ a processing unit} including an instruction fetch unit, an operand fetch unit, and {TAIL ~ an execution unit} 
including
According to the present invention there is provided a memory address control apparatus , for a data processor using a virtual memory technique , is connected to a main memory unit and { HEAD ~ a processing unit } including an instruction fetch unit , an operand fetch unit , and { TAIL ~ an execution unit }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL