a second inverted XOR logic gate having as {TAIL ~ inputs} said second filtered signal and said {HEAD ~ chip sequence}, 
as
a second inverted XOR logic gate having as { TAIL ~ inputs } said second filtered signal and said { HEAD ~ chip sequence } ,
OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH