Each stage begins with {HEAD ~ four 32 bit values} in an A register, a B register; {TAIL ~ a C register}; and a D register 
in
Each stage begins with { HEAD ~ four 32 bit values } in an A register , a B register ; { TAIL ~ a C register } ; and a D register
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH