said gate or base of said first transistor for receiving , said gate or base of said second transistor for receiving , said gate or base of said third transistor for receiving , and said {HEAD ~ gate} or base of said {TAIL ~ fourth transistor} for receiving , where Vx and Vy are first and second input signals, respectively and u, v and w are constants, excluding the combination u=v=1/2 
of
said gate or base of said first transistor for receiving , said gate or base of said second transistor for receiving , said gate or base of said third transistor for receiving , and said { HEAD ~ gate } or base of said { TAIL ~ fourth transistor } for receiving , where Vx and Vy are first and second input signals , respectively and u , v and w are constants , excluding the combination u = v=1/2
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH REL OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH