Each of the processing modules includes a subcircuit which monitors addresses requested by the processing modules, and wherein {TAIL ~ the subcircuit} grants {HEAD ~ the local processing circuit control} of the system bus for a next data transfer cycle if a current memory address is to a different memory module than a previous address request 
Each of the processing modules includes a subcircuit which monitors addresses requested by the processing modules , and wherein { TAIL ~ the subcircuit } grants { HEAD ~ the local processing circuit control } of the system bus for a next data transfer cycle if a current memory address is to a different memory module than a previous address request
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH