said {HEAD ~ second column selection circuitry} is selectively controlled by {TAIL ~ a row address bit} and a column address bit 
is selectively controlled by
said { HEAD ~ second column selection circuitry } is selectively controlled by { TAIL ~ a row address bit } and a column address bit
OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH