The combination 1 wherein {TAIL ~ said logic means} includes means for connecting said parallel shift register paths into a single shift register scan path including the shift register paths of {HEAD ~ all the individual logic units} 
The combination 1 wherein { TAIL ~ said logic means } includes means for connecting said parallel shift register paths into a single shift register scan path including the shift register paths of { HEAD ~ all the individual logic units }
OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD