{HEAD ~ A vector register} provides {TAIL ~ the capability} for simultaneously writing through at least two write ports and simultaneous reading from at least two read ports 
provides
{ HEAD ~ A vector register } provides { TAIL ~ the capability } for simultaneously writing through at least two write ports and simultaneous reading from at least two read ports
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH