{TAIL ~ four 32 bit registers} designated A, B, C and D, wherein each register holds {HEAD ~ a value}; and 
{ TAIL ~ four 32 bit registers } designated A , B , C and D , wherein each register holds { HEAD ~ a value } ; and
TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH