The invention provides {HEAD ~ a simple interface circuit} between a large capacity, high speed DRAM and a single port SRAM cache to achieve {TAIL ~ fast cycle memory performance} 
to achieve
The invention provides { HEAD ~ a simple interface circuit } between a large capacity , high speed DRAM and a single port SRAM cache to achieve { TAIL ~ fast cycle memory performance }
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL