Also shown in FIG 4 are SBREQ1 and SBREQ2 signals 470, 475, asserted by the bus controller 215 over the bus 222, which indicate that the bus controller for the first CPU module 120 and {HEAD ~ the bus controller} for {TAIL ~ the second CPU module} 125, respectively, are requesting access to the system bus 110 
for
Also shown in FIG 4 are SBREQ1 and SBREQ2 signals 470 , 475 , asserted by the bus controller 215 over the bus 222 , which indicate that the bus controller for the first CPU module 120 and { HEAD ~ the bus controller } for { TAIL ~ the second CPU module } 125 , respectively , are requesting access to the system bus 110
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH