To reduce the number of instructions that the processor may process, a clock generator which provides {HEAD ~ clock signals} to {TAIL ~ the processor} may be slowed down or the processor itself may be slowed down  
to
To reduce the number of instructions that the processor may process , a clock generator which provides { HEAD ~ clock signals } to { TAIL ~ the processor } may be slowed down or the processor itself may be slowed down
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH