{HEAD ~ A plurality} of integrated circuit features are provided in {TAIL ~ the context} of an array of memory cells including a plurality of word lines and a plurality of bit lines 
are provided in
{ HEAD ~ A plurality } of integrated circuit features are provided in { TAIL ~ the context } of an array of memory cells including a plurality of word lines and a plurality of bit lines
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH