In the CPU reset circuit of FIG 1, the reset signal provided from {TAIL ~ watch dog circuit} 20 is usually generated for {HEAD ~ a proper time interval}, and therefore presents little problem 
In the CPU reset circuit of FIG 1 , the reset signal provided from { TAIL ~ watch dog circuit } 20 is usually generated for { HEAD ~ a proper time interval } , and therefore presents little problem
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH