{HEAD ~ A DC regulator} 1 wherein said first switching means further comprises a first three electrode FET transistor operatively connected as {TAIL ~ a switching device} across said fourth terminal and said second terminal 
{ HEAD ~ A DC regulator } 1 wherein said first switching means further comprises a first three electrode FET transistor operatively connected as { TAIL ~ a switching device } across said fourth terminal and said second terminal
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH