The semiconductor memory device 6, further comprising an adjustment transistor coupled in parallel with the pull down transistor, wherein the adjustment transistor is configured to be controllable by {HEAD ~ at least one bit} of {TAIL ~ the stack position identifier} 
of
The semiconductor memory device 6 , further comprising an adjustment transistor coupled in parallel with the pull down transistor , wherein the adjustment transistor is configured to be controllable by { HEAD ~ at least one bit } of { TAIL ~ the stack position identifier }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL