FIG 5 is a schematic diagram showing {TAIL ~ a cross section view} of {HEAD ~ a DMOS device} 500 of the present invention 
FIG 5 is a schematic diagram showing { TAIL ~ a cross section view } of { HEAD ~ a DMOS device } 500 of the present invention
OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH