In another embodiment, {HEAD ~ a latency} of a DRAM or {TAIL ~ SRAM} is adjusted based on the SPID 
of
In another embodiment , { HEAD ~ a latency } of a DRAM or { TAIL ~ SRAM } is adjusted based on the SPID
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH