When a high logic level is asserted in device A, {HEAD ~ the portion} of {TAIL ~ the circuit} in device B causes a high logic level to be asserted in device B also at the converted level 
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When a high logic level is asserted in device A , { HEAD ~ the portion } of { TAIL ~ the circuit } in device B causes a high logic level to be asserted in device B also at the converted level
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH