The integrated circuit 46, wherein {HEAD ~ the channel regions} of at least a portion of the array of memory cells are removed prior to {TAIL ~ a corresponding word line} being formed 
are removed prior to
The integrated circuit 46 , wherein { HEAD ~ the channel regions } of at least a portion of the array of memory cells are removed prior to { TAIL ~ a corresponding word line } being formed
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH