During each verify cycle, drivers and {HEAD ~ decoders} 130 apply to {TAIL ~ the control gate} of the target memory cell a voltage Vvfy which depends on voltage VW , grounds the source lines, and applies a read voltage Vrc to the column line of the target memory cell 
apply to
During each verify cycle , drivers and { HEAD ~ decoders } 130 apply to { TAIL ~ the control gate } of the target memory cell a voltage Vvfy which depends on voltage VW , grounds the source lines , and applies a read voltage Vrc to the column line of the target memory cell
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH