a first inverted XOR logic gate having as {HEAD ~ inputs} said {TAIL ~ first filtered signal} and a chip sequence, 
a first inverted XOR logic gate having as { HEAD ~ inputs } said { TAIL ~ first filtered signal } and a chip sequence ,
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH