{HEAD ~ The first subcircuit} and the third subcircuit are configured to pull {TAIL ~ the first node} and the second node, respectively, to a common precharge voltage in response to a first state of the clock signal in order to pass the clock signal 
are configured to pull
{ HEAD ~ The first subcircuit } and the third subcircuit are configured to pull { TAIL ~ the first node } and the second node , respectively , to a common precharge voltage in response to a first state of the clock signal in order to pass the clock signal
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH