{HEAD ~ The subsystem monitoring circuit} includes {TAIL ~ a transfer count register} which indicates how many data transfer cycles can be run in succession before the local CPU has to relinquish control of the system bus 
includes
{ HEAD ~ The subsystem monitoring circuit } includes { TAIL ~ a transfer count register } which indicates how many data transfer cycles can be run in succession before the local CPU has to relinquish control of the system bus
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH