a second inverted XOR logic gate having as {HEAD ~ inputs} said {TAIL ~ second filtered signal} and said chip sequence, 
a second inverted XOR logic gate having as { HEAD ~ inputs } said { TAIL ~ second filtered signal } and said chip sequence ,
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH