{HEAD ~ The memory address control apparatus} includes {TAIL ~ an instruction address translation} look aside buffer for translating logical addresses to real addresses in the MMU at which instructions are stored and an operand data address translation look aside buffer for translating logical addresses to real addresses in the MMU at which operand data are stored 
includes
{ HEAD ~ The memory address control apparatus } includes { TAIL ~ an instruction address translation } look aside buffer for translating logical addresses to real addresses in the MMU at which instructions are stored and an operand data address translation look aside buffer for translating logical addresses to real addresses in the MMU at which operand data are stored
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH