{HEAD ~ an interlayer dielectric layer} provided over {TAIL ~ the semiconductor layer} and the non volatile memory transistor with the interlayer dielectric layer being in direct contact with a component of the non volatile memory transistor, 
provided over
{ HEAD ~ an interlayer dielectric layer } provided over { TAIL ~ the semiconductor layer } and the non volatile memory transistor with the interlayer dielectric layer being in direct contact with a component of the non volatile memory transistor ,
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH