wherein, in the step , a gate electrode of a third MISFET is formed by patterning the conductive film such that {HEAD ~ the gate electrode} of the second MISFET is arranged, in the first direction, between {TAIL ~ the gate electrode} of the first MISFET and the gate electrode of the third MISFET, 
is arranged between
wherein , in the step , a gate electrode of a third MISFET is formed by patterning the conductive film such that { HEAD ~ the gate electrode } of the second MISFET is arranged , in the first direction , between { TAIL ~ the gate electrode } of the first MISFET and the gate electrode of the third MISFET ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH REL REL OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH