{TAIL ~ The process} 9, wherein {HEAD ~ the gate electrode} comprises in situ doped polysilicon 
{ TAIL ~ The process } 9 , wherein { HEAD ~ the gate electrode } comprises in situ doped polysilicon
TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH