wherein {TAIL ~ the second transistor} has a control terminal coupling to an output of the decoder, and {HEAD ~ the at least one additional transistor} has a control terminal coupling to an output of the decoder 
wherein { TAIL ~ the second transistor } has a control terminal coupling to an output of the decoder , and { HEAD ~ the at least one additional transistor } has a control terminal coupling to an output of the decoder
OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH