A plurality of {TAIL ~ integrated circuit features} are provided in the context of an array of memory cells including a plurality of {HEAD ~ word lines} and a plurality of bit lines 
A plurality of { TAIL ~ integrated circuit features } are provided in the context of an array of memory cells including a plurality of { HEAD ~ word lines } and a plurality of bit lines
OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH