The apparatus includes a storage circuit, a first processing circuit which accesses the storage circuit for processing data obtained from each of the packets, and {HEAD ~ a second processing circuit} which accesses {TAIL ~ the storage circuit} for processing data stored in the storage circuit 
accesses
The apparatus includes a storage circuit , a first processing circuit which accesses the storage circuit for processing data obtained from each of the packets , and { HEAD ~ a second processing circuit } which accesses { TAIL ~ the storage circuit } for processing data stored in the storage circuit
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH