{HEAD ~ A memory device} includes a memory cell array to store data, {TAIL ~ a register} to store test data, and a decision circuit to invert the test data and to determine a failure of at least one memory cell within the memory cell array responsive to the data, the test data, and the inverted test data 
includes
{ HEAD ~ A memory device } includes a memory cell array to store data , { TAIL ~ a register } to store test data , and a decision circuit to invert the test data and to determine a failure of at least one memory cell within the memory cell array responsive to the data , the test data , and the inverted test data
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