Each the plurality of {HEAD ~ memory modules} includes {TAIL ~ a memory MMW transceiver} and a plurality of memory cells 
Each the plurality of { HEAD ~ memory modules } includes { TAIL ~ a memory MMW transceiver } and a plurality of memory cells
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH