The multithreaded processor 6, wherein the instruction corresponds to {HEAD ~ a thread} with {TAIL ~ a first thread ID} and the plurality of stages contain instructions corresponding to more than one thread, and wherein the trap logic unit is further configured to initiate a flush of only those instructions which follow the instruction and which correspond to the first thread ID 
with
The multithreaded processor 6 , wherein the instruction corresponds to { HEAD ~ a thread } with { TAIL ~ a first thread ID } and the plurality of stages contain instructions corresponding to more than one thread , and wherein the trap logic unit is further configured to initiate a flush of only those instructions which follow the instruction and which correspond to the first thread ID
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH