Although {HEAD ~ each bit} of {TAIL ~ the transmitted data} is kept output during the time period from the asserting edge AG to the next asserting edge AG of the transmission clock signal SCLKO, the holding interval T of the final bit is determined by the holding interval decision register 9 
of
Although { HEAD ~ each bit } of { TAIL ~ the transmitted data } is kept output during the time period from the asserting edge AG to the next asserting edge AG of the transmission clock signal SCLKO , the holding interval T of the final bit is determined by the holding interval decision register 9
OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH