The first programmable delay receives {HEAD ~ a first set} of {TAIL ~ one or more bits} from the configuration register and a double speed clock signal 
of
The first programmable delay receives { HEAD ~ a first set } of { TAIL ~ one or more bits } from the configuration register and a double speed clock signal
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH