{TAIL ~ Packet communication apparatus} with {HEAD ~ first and second processing circuits} which access a storage circuit during first and second time periods, respectively 
{ TAIL ~ Packet communication apparatus } with { HEAD ~ first and second processing circuits } which access a storage circuit during first and second time periods , respectively
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH