a third adder configured to modulo add the B register value and an output of the fixed 32 bit shift unit, wherein the output of the fixed 32 bit shift unit is provided to {HEAD ~ the third adder} via {TAIL ~ direct bit} routing to the third adder; and 
via
a third adder configured to modulo add the B register value and an output of the fixed 32 bit shift unit , wherein the output of the fixed 32 bit shift unit is provided to { HEAD ~ the third adder } via { TAIL ~ direct bit } routing to the third adder ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH