At row predecoder 52 2 the input terminals 530 and 531 are controlled by address inputs A8 and A9 respectively and {TAIL ~ the output terminals L0 L3 drive bus} 56 to the row decoder block 32, and at row predecoder 52 3 the input terminals 530 and 531 are controlled by address inputs A10 and {HEAD ~ A11} respectively and the output terminals L0 L3 drive bus 57 to the row decoder block 32 
At row predecoder 52 2 the input terminals 530 and 531 are controlled by address inputs A8 and A9 respectively and { TAIL ~ the output terminals L0 L3 drive bus } 56 to the row decoder block 32 , and at row predecoder 52 3 the input terminals 530 and 531 are controlled by address inputs A10 and { HEAD ~ A11 } respectively and the output terminals L0 L3 drive bus 57 to the row decoder block 32
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH