Said first and second path being effective for said central processing units and said address sourcing devices to access the first part of {HEAD ~ the memory} without {TAIL ~ contention} with each other, and for diminishing contention with each other when accessing the second part of the memory 
without
Said first and second path being effective for said central processing units and said address sourcing devices to access the first part of { HEAD ~ the memory } without { TAIL ~ contention } with each other , and for diminishing contention with each other when accessing the second part of the memory
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH