The output of only one NAND gate will go to logical 0 state when both its input lines are at {TAIL ~ logic 1 state} simultaneously, and so the outputs of the remaining NAND gates will be at {HEAD ~ logical 1 state} 
The output of only one NAND gate will go to logical 0 state when both its input lines are at { TAIL ~ logic 1 state } simultaneously , and so the outputs of the remaining NAND gates will be at { HEAD ~ logical 1 state }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD