a second inverted XOR logic gate having as inputs said {HEAD ~ second filtered signal} and said {TAIL ~ chip sequence}, 
a second inverted XOR logic gate having as inputs said { HEAD ~ second filtered signal } and said { TAIL ~ chip sequence } ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH