The lock includes a counter and a gate for inhibiting {HEAD ~ clock pulses} to {TAIL ~ the memory element} until a predetermined number of control pulses have been received to initiate a read/write operation 
to
The lock includes a counter and a gate for inhibiting { HEAD ~ clock pulses } to { TAIL ~ the memory element } until a predetermined number of control pulses have been received to initiate a read / write operation
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH