The integrated circuit 46, wherein the channel regions of at least a portion of {HEAD ~ the array} of {TAIL ~ memory cells} are removed prior to a corresponding word line being formed 
of
The integrated circuit 46 , wherein the channel regions of at least a portion of { HEAD ~ the array } of { TAIL ~ memory cells } are removed prior to a corresponding word line being formed
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH