{TAIL ~ The differential amplifier} 60, wherein the main differential amplifier includes a second differential pair including {HEAD ~ a fifth transistor} and a sixth transistor, the second differential pair, wherein the second differential pair is adapted to receive the shifted differential voltage signal to generate the output signal 
{ TAIL ~ The differential amplifier } 60 , wherein the main differential amplifier includes a second differential pair including { HEAD ~ a fifth transistor } and a sixth transistor , the second differential pair , wherein the second differential pair is adapted to receive the shifted differential voltage signal to generate the output signal
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH