Finally, the memory controller comprises {HEAD ~ a twelfth FF} receiving {TAIL ~ the output signal} of the fourth multiplexer, outputting a write data mask and write data signal, and driven by the output signal of the XOR gate 
receiving
Finally , the memory controller comprises { HEAD ~ a twelfth FF } receiving { TAIL ~ the output signal } of the fourth multiplexer , outputting a write data mask and write data signal , and driven by the output signal of the XOR gate
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH