a third adder configured to modulo add the B register value and an output of the fixed 32 bit shift unit, wherein {HEAD ~ the output} of {TAIL ~ the fixed 32 bit shift unit} is provided to the third adder via direct bit routing to the third adder; and 
of
a third adder configured to modulo add the B register value and an output of the fixed 32 bit shift unit , wherein { HEAD ~ the output } of { TAIL ~ the fixed 32 bit shift unit } is provided to the third adder via direct bit routing to the third adder ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH