Finally, the memory controller comprises a twelfth FF receiving the output signal of the fourth multiplexer, outputting a write data mask and write data signal, and driven by {HEAD ~ the output signal} of {TAIL ~ the XOR gate} 
of
Finally , the memory controller comprises a twelfth FF receiving the output signal of the fourth multiplexer , outputting a write data mask and write data signal , and driven by { HEAD ~ the output signal } of { TAIL ~ the XOR gate }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL