Otherwise, {HEAD ~ a data address} of {TAIL ~ an identifier} for a previously prepared ultimate LRU in the cache memory is transmitted to the CPU at a step  
of
Otherwise , { HEAD ~ a data address } of { TAIL ~ an identifier } for a previously prepared ultimate LRU in the cache memory is transmitted to the CPU at a step
OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH