{HEAD ~ The device} 1 wherein the input conductors associated with each of the logic blocks receive {TAIL ~ signals} from the first set of conductors 
receive
{ HEAD ~ The device } 1 wherein the input conductors associated with each of the logic blocks receive { TAIL ~ signals } from the first set of conductors
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH