According to one embodiment of the invention, {HEAD ~ a method} for simulating the operation of {TAIL ~ an integrated circuit} is provided 
According to one embodiment of the invention , { HEAD ~ a method } for simulating the operation of { TAIL ~ an integrated circuit } is provided
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH