The combination 1 wherein said logic means includes means for connecting said parallel shift register paths into a single shift register scan path including {HEAD ~ the shift register paths} of {TAIL ~ all the individual logic units} 
of
The combination 1 wherein said logic means includes means for connecting said parallel shift register paths into a single shift register scan path including { HEAD ~ the shift register paths } of { TAIL ~ all the individual logic units }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL