A method 10, wherein {HEAD ~ the sourceline voltage adjustment amount} is predetermined based on {TAIL ~ specifications} of the resistive sense memory cell and the transistor 
is predetermined based on
A method 10 , wherein { HEAD ~ the sourceline voltage adjustment amount } is predetermined based on { TAIL ~ specifications } of the resistive sense memory cell and the transistor
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH