Otherwise, {HEAD ~ a data address} of an identifier for a previously prepared ultimate LRU in the cache memory is transmitted to the CPU at {TAIL ~ a step}  
is transmitted at
Otherwise , { HEAD ~ a data address } of an identifier for a previously prepared ultimate LRU in the cache memory is transmitted to the CPU at { TAIL ~ a step }
OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL REL OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH