generating the IC design, wherein the IC design comprises an instance of the macro cell and a description of a clock tree for delivering the clock signal from a root of {HEAD ~ the clock tree} to the root of the clock tree subtree described by {TAIL ~ the instance} of the macro cell; and 
generating the IC design , wherein the IC design comprises an instance of the macro cell and a description of a clock tree for delivering the clock signal from a root of { HEAD ~ the clock tree } to the root of the clock tree subtree described by { TAIL ~ the instance } of the macro cell ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH