{HEAD ~ A ROM memory array} comprises {TAIL ~ a doped silicon substrate} having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of channel regions between the bitlines 
comprises
{ HEAD ~ A ROM memory array } comprises { TAIL ~ a doped silicon substrate } having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of channel regions between the bitlines
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