A semiconductor integrated circuit having {HEAD ~ bias circuits} {TAIL ~ each} including different reference resistor is disclosed 
A semiconductor integrated circuit having { HEAD ~ bias circuits } { TAIL ~ each } including different reference resistor is disclosed
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH