The invention provides {TAIL ~ a simple interface circuit} between {HEAD ~ a large capacity, high speed DRAM} and a single port SRAM cache to achieve fast cycle memory performance 
The invention provides { TAIL ~ a simple interface circuit } between { HEAD ~ a large capacity , high speed DRAM } and a single port SRAM cache to achieve fast cycle memory performance
OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH