It should be noted that {HEAD ~ a video signal} obtained at the synchronization separation circuit 10 is displayed on {TAIL ~ a display} at the timing of the internally generated horizontal and vertical synchronization signals 
is displayed on
It should be noted that { HEAD ~ a video signal } obtained at the synchronization separation circuit 10 is displayed on { TAIL ~ a display } at the timing of the internally generated horizontal and vertical synchronization signals
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH