Memory address control apparatus with separate translation look aside {HEAD ~ buffers} for {TAIL ~ a data processor} using a virtual memory technique 
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Memory address control apparatus with separate translation look aside { HEAD ~ buffers } for { TAIL ~ a data processor } using a virtual memory technique
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH