This disclosure describes an efficient architecture for an imaging device that supports {HEAD ~ image registration} for still images and video coding of {TAIL ~ a video sequence} 
This disclosure describes an efficient architecture for an imaging device that supports { HEAD ~ image registration } for still images and video coding of { TAIL ~ a video sequence }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL