The processor also determines whether any other switch controller intends to transmit to {HEAD ~ the determined destination} of {TAIL ~ the packet} at a given time 
of
The processor also determines whether any other switch controller intends to transmit to { HEAD ~ the determined destination } of { TAIL ~ the packet } at a given time
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH