said system bus for enabling communication between said processor means, said cache means, said {TAIL ~ interface} means and said {HEAD ~ main memory} means 
said system bus for enabling communication between said processor means , said cache means , said { TAIL ~ interface } means and said { HEAD ~ main memory } means
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH