{HEAD ~ A test circuit} is configured to change the logic code stored in the register circuit and store {TAIL ~ the changed logic code} irrespective of the logic code of the fuse circuit for test operation of the NAND flash memory device 
is configured to store
{ HEAD ~ A test circuit } is configured to change the logic code stored in the register circuit and store { TAIL ~ the changed logic code } irrespective of the logic code of the fuse circuit for test operation of the NAND flash memory device
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH