With reference now to FIG 8, a diagram depicts a memory subsystem connected to the address switch of {HEAD ~ the distributed system} of {TAIL ~ the present invention} 
of
With reference now to FIG 8 , a diagram depicts a memory subsystem connected to the address switch of { HEAD ~ the distributed system } of { TAIL ~ the present invention }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL