An internal clock is synchronized with {HEAD ~ a horizontal synchronization signal} separated in {TAIL ~ a synchronization separation circuit} 10, an H reset signal is generated based thereon in an H countdown circuit 14, and a horizontal synchronization signal is generated based thereon 
separated in
An internal clock is synchronized with { HEAD ~ a horizontal synchronization signal } separated in { TAIL ~ a synchronization separation circuit } 10 , an H reset signal is generated based thereon in an H countdown circuit 14 , and a horizontal synchronization signal is generated based thereon
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH