a counter which is reset when {HEAD ~ a signal} indicating writing of data in {TAIL ~ the memory} is detected to output a counter signal when a predetermined value has been counted 
a counter which is reset when { HEAD ~ a signal } indicating writing of data in { TAIL ~ the memory } is detected to output a counter signal when a predetermined value has been counted
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH