{HEAD ~ A vertical synchronization signal} separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14, and based on {TAIL ~ an obtained V reset signal}, a vertical synchronization signal is obtained in a VS output circuit 18 
{ HEAD ~ A vertical synchronization signal } separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14 , and based on { TAIL ~ an obtained V reset signal } , a vertical synchronization signal is obtained in a VS output circuit 18
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH