Additionally, {HEAD ~ the issue circuit} is configured to generate a control signal responsive to whether or not the instruction is issued to {TAIL ~ the execution circuit} 
Additionally , { HEAD ~ the issue circuit } is configured to generate a control signal responsive to whether or not the instruction is issued to { TAIL ~ the execution circuit }
OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL