A clock tree synthesis tool uses {HEAD ~ the subtree model} to determine {TAIL ~ the maximum and minimum rising and falling edge path delays} though the subtree when estimating the maximum and minimum amounts by which the clock tree delays the clock signals rising and falling edges as they pass from the clock tree root to any sink of the IC 
to determine
A clock tree synthesis tool uses { HEAD ~ the subtree model } to determine { TAIL ~ the maximum and minimum rising and falling edge path delays } though the subtree when estimating the maximum and minimum amounts by which the clock tree delays the clock signals rising and falling edges as they pass from the clock tree root to any sink of the IC
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH