Moreover, {HEAD ~ both an n bit row address} in the normal area and an m bit row address in the parity area can be generated through switching control of {TAIL ~ a connected state} with the first switching circuit 
Moreover , { HEAD ~ both an n bit row address } in the normal area and an m bit row address in the parity area can be generated through switching control of { TAIL ~ a connected state } with the first switching circuit
OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH