{TAIL ~ The second address compare circuit} generates {HEAD ~ a redundant address selection signal} when the received address is the same as the first redundant address 
{ TAIL ~ The second address compare circuit } generates { HEAD ~ a redundant address selection signal } when the received address is the same as the first redundant address
TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH