The fourth multiplexer is controlled by {HEAD ~ the third set} of one or more bits from {TAIL ~ the configuration register} 
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The fourth multiplexer is controlled by { HEAD ~ the third set } of one or more bits from { TAIL ~ the configuration register }
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL