The NS decoder 33a comprises combinational logic that evaluates both the state machine inputs signals from {TAIL ~ STATEIN circuit} 31 and the values {HEAD ~ DSV} 31:0 in bit form from the output decoder 33c 
The NS decoder 33a comprises combinational logic that evaluates both the state machine inputs signals from { TAIL ~ STATEIN circuit } 31 and the values { HEAD ~ DSV } 31:0 in bit form from the output decoder 33c
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH