{HEAD ~ The analyzer} includes {TAIL ~ a load bank} consisting of a plurality of resistors in selective parallel interconnection 
includes
{ HEAD ~ The analyzer } includes { TAIL ~ a load bank } consisting of a plurality of resistors in selective parallel interconnection
HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH