The interpreter 30 may be digital logic circuitry that compares {HEAD ~ the states} of {TAIL ~ the signals} GH and GL or may be a microprocessor that employs software routines to accomplish the same purpose 
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The interpreter 30 may be digital logic circuitry that compares { HEAD ~ the states } of { TAIL ~ the signals } GH and GL or may be a microprocessor that employs software routines to accomplish the same purpose
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH