determining a portion, in the input logic circuit, in which event judgment logic is to be inserted, on {HEAD ~ the basis} of {TAIL ~ the signal processing flow detection result}; and 
of
determining a portion , in the input logic circuit , in which event judgment logic is to be inserted , on { HEAD ~ the basis } of { TAIL ~ the signal processing flow detection result } ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH