At {TAIL ~ the same time} {HEAD ~ output terminals L1}, L2 and L3 will be at logical 0 state 
At
At { TAIL ~ the same time } { HEAD ~ output terminals L1 } , L2 and L3 will be at logical 0 state
REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH