At row predecoder 52 1 the input terminals 530 and 531 are controlled by address inputs {TAIL ~ A5} and {HEAD ~ A6} respectively and the output terminals L0 L3 drive bus 55 to the row decoder block 32 
At row predecoder 52 1 the input terminals 530 and 531 are controlled by address inputs { TAIL ~ A5 } and { HEAD ~ A6 } respectively and the output terminals L0 L3 drive bus 55 to the row decoder block 32
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH