a second inverted XOR logic gate having as {HEAD ~ inputs} said second filtered signal and said {TAIL ~ chip sequence}, 
a second inverted XOR logic gate having as { HEAD ~ inputs } said second filtered signal and said { TAIL ~ chip sequence } ,
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH