Otherwise, a data address of {HEAD ~ an identifier} for {TAIL ~ a previously prepared ultimate LRU} in the cache memory is transmitted to the CPU at a step  
for
Otherwise , a data address of { HEAD ~ an identifier } for { TAIL ~ a previously prepared ultimate LRU } in the cache memory is transmitted to the CPU at a step
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH