A refresh counter circuit 5 or 6, wherein each of said path switches comprises {HEAD ~ a complementary type transfer gate} including {TAIL ~ PMOS} and NMOS 
including
A refresh counter circuit 5 or 6 , wherein each of said path switches comprises { HEAD ~ a complementary type transfer gate } including { TAIL ~ PMOS } and NMOS
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH