{HEAD ~ a second memory cell column} that is connected to {TAIL ~ the second bit line}, the second memory cell column being formed by a plurality of MONOS type transistors 
is connected to
{ HEAD ~ a second memory cell column } that is connected to { TAIL ~ the second bit line } , the second memory cell column being formed by a plurality of MONOS type transistors
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH