In {TAIL ~ one architecture}, {HEAD ~ a memory device} includes a memory array for storing data values, multiple sensing circuits, multiple control lines, and an I/O pad 
In
In { TAIL ~ one architecture } , { HEAD ~ a memory device } includes a memory array for storing data values , multiple sensing circuits , multiple control lines , and an I / O pad
REL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH