In response to receiving the enable signal, {HEAD ~ the voltage supply} outputs {TAIL ~ a new USB VBUS power signal} compliant with USB VBUS power signal requirements 
outputs
In response to receiving the enable signal , { HEAD ~ the voltage supply } outputs { TAIL ~ a new USB VBUS power signal } compliant with USB VBUS power signal requirements
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH