address decoder means responsive to {HEAD ~ one portion} of said {TAIL ~ logical address} in said register for selecting and reading out to said TLB a set having mT compartments in said TLB, 
of
address decoder means responsive to { HEAD ~ one portion } of said { TAIL ~ logical address } in said register for selecting and reading out to said TLB a set having mT compartments in said TLB ,
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH