In accordance with the present invention, {HEAD ~ an integrated circuit} includes {TAIL ~ a digital signal processor}, at least one programmable logic core, shared memory and a memory bus system coupling the digital signal processor and programmable logic core to the memory and to each other 
includes
In accordance with the present invention , { HEAD ~ an integrated circuit } includes { TAIL ~ a digital signal processor } , at least one programmable logic core , shared memory and a memory bus system coupling the digital signal processor and programmable logic core to the memory and to each other
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH