In {TAIL ~ this circuit}, {HEAD ~ the smaller number} in one register is arranged so that the complement thereof is denormalized and added to the subtrahend and the result of the addition is returned to the original register 
In
In { TAIL ~ this circuit } , { HEAD ~ the smaller number } in one register is arranged so that the complement thereof is denormalized and added to the subtrahend and the result of the addition is returned to the original register
REL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH