a second multiplexer receiving as inputs an output of said second inverted XOR gate and an output of said third inverted XOR gate, said {HEAD ~ first and second multiplexers} under {TAIL ~ control} of a common clocking signal, 
under
a second multiplexer receiving as inputs an output of said second inverted XOR gate and an output of said third inverted XOR gate , said { HEAD ~ first and second multiplexers } under { TAIL ~ control } of a common clocking signal ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH