Said first and second path being effective for said central processing units and said address sourcing {HEAD ~ devices} to access {TAIL ~ the first part} of the memory without contention with each other, and for diminishing contention with each other when accessing the second part of the memory 
to access
Said first and second path being effective for said central processing units and said address sourcing { HEAD ~ devices } to access { TAIL ~ the first part } of the memory without contention with each other , and for diminishing contention with each other when accessing the second part of the memory
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH