{HEAD ~ The parallel connected differential CMOS sections} of {TAIL ~ each variable delay element} are controlled by a differential control voltage whose magnitude sets relative levels of operation of the two differential sections of each variable delay element 
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{ HEAD ~ The parallel connected differential CMOS sections } of { TAIL ~ each variable delay element } are controlled by a differential control voltage whose magnitude sets relative levels of operation of the two differential sections of each variable delay element
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH