The multithreaded processor 6, wherein the instruction corresponds to a thread with a first thread ID and the plurality of stages contain instructions corresponding to more than one thread, and wherein the trap logic unit is further configured to initiate a flush of only those instructions which follow the instruction and {HEAD ~ which correspond} to {TAIL ~ the first thread} ID 
to
The multithreaded processor 6 , wherein the instruction corresponds to a thread with a first thread ID and the plurality of stages contain instructions corresponding to more than one thread , and wherein the trap logic unit is further configured to initiate a flush of only those instructions which follow the instruction and { HEAD ~ which correspond } to { TAIL ~ the first thread } ID
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