The presence or absence of {HEAD ~ power voltage VDD supply} from {TAIL ~ the terminal 12 side} is determined from the output of detector 33 
from
The presence or absence of { HEAD ~ power voltage VDD supply } from { TAIL ~ the terminal 12 side } is determined from the output of detector 33
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH