FIG 5 is a schematic diagram showing {TAIL ~ a cross section view} of a DMOS device 500 of {HEAD ~ the present invention} 
FIG 5 is a schematic diagram showing { TAIL ~ a cross section view } of a DMOS device 500 of { HEAD ~ the present invention }
OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD