The device 1, further comprising {TAIL ~ a gate pad} and {HEAD ~ a data pad} on the first substrate 
The device 1 , further comprising { TAIL ~ a gate pad } and { HEAD ~ a data pad } on the first substrate
OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH