{TAIL ~ The LSSD scan paths} of {HEAD ~ each logic circuit chip} on a circuit module are connected to additional test circuit chips on the same module 
{ TAIL ~ The LSSD scan paths } of { HEAD ~ each logic circuit chip } on a circuit module are connected to additional test circuit chips on the same module
TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH