The memory controller further comprises a third multiplexer receiving {HEAD ~ the output signal} of {TAIL ~ the second FF} and the output signal of the third FF and controlled by the output signal of the eighth FF 
of
The memory controller further comprises a third multiplexer receiving { HEAD ~ the output signal } of { TAIL ~ the second FF } and the output signal of the third FF and controlled by the output signal of the eighth FF
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH