{HEAD ~ A vertical synchronization signal} separated in {TAIL ~ the synchronization separation circuit} 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14, and based on an obtained V reset signal, a vertical synchronization signal is obtained in a VS output circuit 18 
separated in
{ HEAD ~ A vertical synchronization signal } separated in { TAIL ~ the synchronization separation circuit } 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14 , and based on an obtained V reset signal , a vertical synchronization signal is obtained in a VS output circuit 18
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH