In particular, the clock signal may oscillate between a first clock state and {TAIL ~ a second clock state} to synchronize the operation of the SSE according to the timing provided by {HEAD ~ the clock states} 
In particular , the clock signal may oscillate between a first clock state and { TAIL ~ a second clock state } to synchronize the operation of the SSE according to the timing provided by { HEAD ~ the clock states }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD