Digital processor has program circuit to periodically read and square the digital representation at a given rate, register for summing a number N of square digital representations to give a summed value, and an algorithm for periodically dividing the summed value by the number N to provide a quotient and then taking the square root of said quotient to thereby digitally construct rms signal representing {HEAD ~ the root mean square} of {TAIL ~ the weld current} 
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Digital processor has program circuit to periodically read and square the digital representation at a given rate , register for summing a number N of square digital representations to give a summed value , and an algorithm for periodically dividing the summed value by the number N to provide a quotient and then taking the square root of said quotient to thereby digitally construct rms signal representing { HEAD ~ the root mean square } of { TAIL ~ the weld current }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL