In a first feedback mode, {HEAD ~ the output bit state} of {TAIL ~ the output bit signal} is held as provided from the sampling stage 
of
In a first feedback mode , { HEAD ~ the output bit state } of { TAIL ~ the output bit signal } is held as provided from the sampling stage
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH