in {TAIL ~ a first clock cycle}, {HEAD ~ old data} are latched into the cache memory sense amplifiers, while new data are latched in the DRAM memory sense amplifiers, 
in
in { TAIL ~ a first clock cycle } , { HEAD ~ old data } are latched into the cache memory sense amplifiers , while new data are latched in the DRAM memory sense amplifiers ,
REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH