In {TAIL ~ another embodiment}, {HEAD ~ a latency} of a DRAM or SRAM is adjusted based on the SPID 
In
In { TAIL ~ another embodiment } , { HEAD ~ a latency } of a DRAM or SRAM is adjusted based on the SPID
REL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH