When a low logic level is asserted in device A, {HEAD ~ the portion} of {TAIL ~ the circuit} in device B causes a low logic level to be asserted in device B at the converted level 
of
When a low logic level is asserted in device A , { HEAD ~ the portion } of { TAIL ~ the circuit } in device B causes a low logic level to be asserted in device B at the converted level
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH