The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit {HEAD ~ signal} generated by {TAIL ~ combinational circuits} within the pipeline circuit 
generated by
The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit { HEAD ~ signal } generated by { TAIL ~ combinational circuits } within the pipeline circuit
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH