said {HEAD ~ system bus} for enabling {TAIL ~ communication} between said processor means, said cache means, said interface means and said main memory means 
for enabling
said { HEAD ~ system bus } for enabling { TAIL ~ communication } between said processor means , said cache means , said interface means and said main memory means
OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH