A memory architecture for a non volatile analog or {HEAD ~ multiple bits} per {TAIL ~ cell memory} includes multiple separate memory arrays and multiple read/write pipelines 
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A memory architecture for a non volatile analog or { HEAD ~ multiple bits } per { TAIL ~ cell memory } includes multiple separate memory arrays and multiple read / write pipelines
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH