{HEAD ~ Multiple channels} are accommodated via a channel interface, also controlled by the microprocessor, between {TAIL ~ external video devices} and the random access memory 
controlled between
{ HEAD ~ Multiple channels } are accommodated via a channel interface , also controlled by the microprocessor , between { TAIL ~ external video devices } and the random access memory
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH REL OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH