passing {HEAD ~ the clock signal} through {TAIL ~ the clock gater} in response to the test enable signal having a first state 
through
passing { HEAD ~ the clock signal } through { TAIL ~ the clock gater } in response to the test enable signal having a first state
OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH