{TAIL ~ The dummy region} comprises a semiconductor substrate, first and second laminates, {HEAD ~ at least one first region}, and at least one second region 
{ TAIL ~ The dummy region } comprises a semiconductor substrate , first and second laminates , { HEAD ~ at least one first region } , and at least one second region
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH