a third inverted XOR logic gate having as {HEAD ~ inputs} said first filtered signal and said {TAIL ~ chip sequence}, 
a third inverted XOR logic gate having as { HEAD ~ inputs } said first filtered signal and said { TAIL ~ chip sequence } ,
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH