Referring to FIG 1C, the exposed semiconductor substrate 10 is isotropically etched using the hard mask pattern 12 and the spacer 13 as etch barriers so that {HEAD ~ sidewalls} of {TAIL ~ the preliminary lower pillar} 11B are recessed to a predetermined width 
of
Referring to FIG 1C , the exposed semiconductor substrate 10 is isotropically etched using the hard mask pattern 12 and the spacer 13 as etch barriers so that { HEAD ~ sidewalls } of { TAIL ~ the preliminary lower pillar } 11B are recessed to a predetermined width
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH