The bus enables {HEAD ~ single or multiple controllers} to access {TAIL ~ real time information} generated by the attached hardware 
to access
The bus enables { HEAD ~ single or multiple controllers } to access { TAIL ~ real time information } generated by the attached hardware
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH