In the illustrated embodiment the video data acquisition signals includes {HEAD ~ a horizontal reset}, a vertical reset, {TAIL ~ a field}, a write enable and a pixel clock signal 
In the illustrated embodiment the video data acquisition signals includes { HEAD ~ a horizontal reset } , a vertical reset , { TAIL ~ a field } , a write enable and a pixel clock signal
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH