{HEAD ~ Extra latency} is added between {TAIL ~ the time} a memory controller issues a write instruction and the time the data is transferred on the data bus 
is added between
{ HEAD ~ Extra latency } is added between { TAIL ~ the time } a memory controller issues a write instruction and the time the data is transferred on the data bus
HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH