{TAIL ~ The memory device} 14, wherein said first column selection circuitry is selectively controlled by a row address bit and {HEAD ~ a column address bit}; and 
{ TAIL ~ The memory device } 14 , wherein said first column selection circuitry is selectively controlled by a row address bit and { HEAD ~ a column address bit } ; and
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH