The memory controller further comprises an OR gate receiving the output signal of the fourth FF and the output signal of the sixth FF; a seventh FF receiving the output signal of {TAIL ~ the OR gate} and driven by the output signal of the first programmable delay; an eighth FF receiving the output signal of {HEAD ~ the OR gate} and driven by the output signal of the first programmable delay; and a ninth FF receiving the output signal of the seventh FF and driven by the output signal of the first programmable delay 
The memory controller further comprises an OR gate receiving the output signal of the fourth FF and the output signal of the sixth FF ; a seventh FF receiving the output signal of { TAIL ~ the OR gate } and driven by the output signal of the first programmable delay ; an eighth FF receiving the output signal of { HEAD ~ the OR gate } and driven by the output signal of the first programmable delay ; and a ninth FF receiving the output signal of the seventh FF and driven by the output signal of the first programmable delay
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