{HEAD ~ The semiconductor package} 1, wherein each of the chips is configured to have {TAIL ~ a DRAM+controller structure} 
{ HEAD ~ The semiconductor package } 1 , wherein each of the chips is configured to have { TAIL ~ a DRAM+controller structure }
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL