said system bus for enabling {HEAD ~ communication} between {TAIL ~ said processor means}, said cache means, said interface means and said main memory means 
between
said system bus for enabling { HEAD ~ communication } between { TAIL ~ said processor means } , said cache means , said interface means and said main memory means
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH