The lock includes a counter and a gate for inhibiting {HEAD ~ clock pulses} to the memory element until a predetermined number of control pulses have been received to initiate {TAIL ~ a read/write operation} 
The lock includes a counter and a gate for inhibiting { HEAD ~ clock pulses } to the memory element until a predetermined number of control pulses have been received to initiate { TAIL ~ a read / write operation }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL