The processor assigns each instruction {HEAD ~ a thread ID} and {TAIL ~ error information} as it follows the pipeline 
The processor assigns each instruction { HEAD ~ a thread ID } and { TAIL ~ error information } as it follows the pipeline
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH