With reference now to FIG 8, a diagram depicts {HEAD ~ a memory subsystem} connected to {TAIL ~ the address switch} of the distributed system of the present invention 
connected to
With reference now to FIG 8 , a diagram depicts { HEAD ~ a memory subsystem } connected to { TAIL ~ the address switch } of the distributed system of the present invention
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH