Accordingly, each count register 702 {HEAD ~ a 702 d} accepts and stores {TAIL ~ the output} of the counter 201 at every fourth transition of the sample clock 103 in a deceleration by four embodiment and every Mth transition of the sample clock 103 in a deceleration by M embodiment 
accepts
Accordingly , each count register 702 { HEAD ~ a 702 d } accepts and stores { TAIL ~ the output } of the counter 201 at every fourth transition of the sample clock 103 in a deceleration by four embodiment and every Mth transition of the sample clock 103 in a deceleration by M embodiment
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH