If it is present, {HEAD ~ a data address} of the target identifier in the cache memory is transmitted to {TAIL ~ the CPU} 
is transmitted to
If it is present , { HEAD ~ a data address } of the target identifier in the cache memory is transmitted to { TAIL ~ the CPU }
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL