According to the present invention there is provided a memory address control apparatus, for a data processor using a virtual memory technique, is connected to a main memory unit and {HEAD ~ a processing unit} including {TAIL ~ an instruction fetch unit}, an operand fetch unit, and an execution unit 
including
According to the present invention there is provided a memory address control apparatus , for a data processor using a virtual memory technique , is connected to a main memory unit and { HEAD ~ a processing unit } including { TAIL ~ an instruction fetch unit } , an operand fetch unit , and an execution unit
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