analyzing {HEAD ~ a signal processing flow} in {TAIL ~ an area} from which the asynchronous element in the logic circuit is excluded 
in
analyzing { HEAD ~ a signal processing flow } in { TAIL ~ an area } from which the asynchronous element in the logic circuit is excluded
OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH