A second address compare circuit compares {HEAD ~ a second received address} for {TAIL ~ the second memory} with the first redundant address 
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A second address compare circuit compares { HEAD ~ a second received address } for { TAIL ~ the second memory } with the first redundant address
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH