Referring to FIG 1C, {HEAD ~ the exposed semiconductor substrate} 10 is isotropically etched using the hard mask pattern 12 and {TAIL ~ the spacer} 13 as etch barriers so that sidewalls of the preliminary lower pillar 11B are recessed to a predetermined width 
is isotropically etched using
Referring to FIG 1C , { HEAD ~ the exposed semiconductor substrate } 10 is isotropically etched using the hard mask pattern 12 and { TAIL ~ the spacer } 13 as etch barriers so that sidewalls of the preliminary lower pillar 11B are recessed to a predetermined width
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