{HEAD ~ A second data switch} is selectively coupled to {TAIL ~ a first terminal} of the second capacitor and one of the data lines 
is selectively coupled to
{ HEAD ~ A second data switch } is selectively coupled to { TAIL ~ a first terminal } of the second capacitor and one of the data lines
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH