Otherwise, {HEAD ~ a data address} of an identifier for a previously prepared ultimate LRU in the cache memory is transmitted to {TAIL ~ the CPU} at a step  
is transmitted to
Otherwise , { HEAD ~ a data address } of an identifier for a previously prepared ultimate LRU in the cache memory is transmitted to { TAIL ~ the CPU } at a step
OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH