The SSE may be provided in a pipeline circuit of {HEAD ~ a TRSS machine} to receive and store a bit state of bit signal generated by {TAIL ~ combinational circuits} within the pipeline circuit 
The SSE may be provided in a pipeline circuit of { HEAD ~ a TRSS machine } to receive and store a bit state of bit signal generated by { TAIL ~ combinational circuits } within the pipeline circuit
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH