{HEAD ~ The latched binary states} of {TAIL ~ the input signal} and the pulse count of the digital counter are evaluated by an interpreter such as logic circuitry or a microprocessor 
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{ HEAD ~ The latched binary states } of { TAIL ~ the input signal } and the pulse count of the digital counter are evaluated by an interpreter such as logic circuitry or a microprocessor
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH