FIG 2 depicts a simple clock tree 14 for delivering {HEAD ~ a clock signal} arriving at {TAIL ~ its root} 19 to several sinks 16 through a set of buffers and inverters 18 provided to fan out the clock signal 
arriving at
FIG 2 depicts a simple clock tree 14 for delivering { HEAD ~ a clock signal } arriving at { TAIL ~ its root } 19 to several sinks 16 through a set of buffers and inverters 18 provided to fan out the clock signal
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH