A data bus or {HEAD ~ related set} of {TAIL ~ wires} and associated circuitry forms a suitable data communication path that can interconnect the input, output, CPU and memory, as well as any peripheral equipment in such a way as to permit the system to operate as an integrated whole 
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A data bus or { HEAD ~ related set } of { TAIL ~ wires } and associated circuitry forms a suitable data communication path that can interconnect the input , output , CPU and memory , as well as any peripheral equipment in such a way as to permit the system to operate as an integrated whole
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH