An output signal showing {HEAD ~ multiplication result} of {TAIL ~ the first and second input signals} is differentially derived between the collectors or drains of the first and fourth transistors and the collectors or drains of the second and third transistors 
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An output signal showing { HEAD ~ multiplication result } of { TAIL ~ the first and second input signals } is differentially derived between the collectors or drains of the first and fourth transistors and the collectors or drains of the second and third transistors
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH