This additional latency is optimized to reduce {HEAD ~ the number} of {TAIL ~ idle time slots} on the data bus when switching between a read instruction and a write instruction 
of
This additional latency is optimized to reduce { HEAD ~ the number } of { TAIL ~ idle time slots } on the data bus when switching between a read instruction and a write instruction
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH