The method reduces the number of {HEAD ~ vias} in the power grid structure and the diagonal wiring blockage caused by {TAIL ~ the vias} while still meeting design specifications 
The method reduces the number of { HEAD ~ vias } in the power grid structure and the diagonal wiring blockage caused by { TAIL ~ the vias } while still meeting design specifications
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH