When a high level or {HEAD ~ a positive signal} is applied to the AND gate 33 from {TAIL ~ the comparator} 21, the clock pulses are supplied to the digital counter 34 and are counted up thereat 
is applied from
When a high level or { HEAD ~ a positive signal } is applied to the AND gate 33 from { TAIL ~ the comparator } 21 , the clock pulses are supplied to the digital counter 34 and are counted up thereat
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH