The apparatus further includes an allocation circuit for executing {HEAD ~ access time allocation} with {TAIL ~ respect} to a packet processing time allowed for processing each of the packets 
with
The apparatus further includes an allocation circuit for executing { HEAD ~ access time allocation } with { TAIL ~ respect } to a packet processing time allowed for processing each of the packets
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH