{HEAD ~ The switch block circuit} 8, wherein {TAIL ~ the common control determination signal} is provided from a program memory 
wherein
{ HEAD ~ The switch block circuit } 8 , wherein { TAIL ~ the common control determination signal } is provided from a program memory
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH