In this circuit, the smaller number in one register is arranged so that the complement thereof is denormalized and added to the subtrahend and {HEAD ~ the result} of the addition is returned to {TAIL ~ the original register} 
is returned to
In this circuit , the smaller number in one register is arranged so that the complement thereof is denormalized and added to the subtrahend and { HEAD ~ the result } of the addition is returned to { TAIL ~ the original register }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL