The delay can further be reduced by reducing the gate widths of the differential transistors {HEAD ~ Q9} and {TAIL ~ Q10} in the differential section D2 relative to the gate widths of the differential transistors Q7 and Q8 in the first differential section D1 
The delay can further be reduced by reducing the gate widths of the differential transistors { HEAD ~ Q9 } and { TAIL ~ Q10 } in the differential section D2 relative to the gate widths of the differential transistors Q7 and Q8 in the first differential section D1
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH