In particular, {HEAD ~ the clock signal} may oscillate between a first clock state and a second clock state to synchronize {TAIL ~ the operation} of the SSE according to the timing provided by the clock states 
In particular , { HEAD ~ the clock signal } may oscillate between a first clock state and a second clock state to synchronize { TAIL ~ the operation } of the SSE according to the timing provided by the clock states
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH