At {TAIL ~ a given circuit board position} predetermined logic levels are applied to the input mode pins to selectively set internal gating so as to interconnect a desired circuit block to the interface pins of {HEAD ~ the gate array} 
At { TAIL ~ a given circuit board position } predetermined logic levels are applied to the input mode pins to selectively set internal gating so as to interconnect a desired circuit block to the interface pins of { HEAD ~ the gate array }
OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD