The first subcircuit and the third subcircuit are configured to pull the first node and the second node, respectively, to a common precharge voltage in {TAIL ~ response} to {HEAD ~ a first state} of the clock signal in order to pass the clock signal 
The first subcircuit and the third subcircuit are configured to pull the first node and the second node , respectively , to a common precharge voltage in { TAIL ~ response } to { HEAD ~ a first state } of the clock signal in order to pass the clock signal
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH