In this manner, {TAIL ~ a command} sent by the address switch experiences a fixed number of {HEAD ~ cycles} of delay before the command is made available to the memory controller 
In this manner , { TAIL ~ a command } sent by the address switch experiences a fixed number of { HEAD ~ cycles } of delay before the command is made available to the memory controller
OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH