Additionally, the memory controller comprises a second multiplexer receiving the output signal of the seventh FF and the output signal of the ninth FF and controlled by {HEAD ~ a third set} of one or more bits from {TAIL ~ the configuration register} 
from
Additionally , the memory controller comprises a second multiplexer receiving the output signal of the seventh FF and the output signal of the ninth FF and controlled by { HEAD ~ a third set } of one or more bits from { TAIL ~ the configuration register }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL