a counter which is reset when a signal indicating {HEAD ~ writing} of {TAIL ~ data} in the memory is detected to output a counter signal when a predetermined value has been counted 
of
a counter which is reset when a signal indicating { HEAD ~ writing } of { TAIL ~ data } in the memory is detected to output a counter signal when a predetermined value has been counted
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH