The circuit 14 further comprising an inverter coupled between {HEAD ~ a control node} of {TAIL ~ the first transistor} and a control node of the second transistor 
of
The circuit 14 further comprising an inverter coupled between { HEAD ~ a control node } of { TAIL ~ the first transistor } and a control node of the second transistor
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH