According to one or more embodiments, the {HEAD ~ IOM} 13 in {TAIL ~ processor} 10 includes additional circuits and logic that facilitate efficiently flushing the lower pipeline upon discovery of a mispredicted branch instruction 
in
According to one or more embodiments , the { HEAD ~ IOM } 13 in { TAIL ~ processor } 10 includes additional circuits and logic that facilitate efficiently flushing the lower pipeline upon discovery of a mispredicted branch instruction
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH