{HEAD ~ a fixed 32 bit shift unit} configured to effect {TAIL ~ a fixed bit shift} on an output of the second adder, wherein the fixed 32 bit shift unit implements only a single hardware implemented MD5 shift value 
configured to effect
{ HEAD ~ a fixed 32 bit shift unit } configured to effect { TAIL ~ a fixed bit shift } on an output of the second adder , wherein the fixed 32 bit shift unit implements only a single hardware implemented MD5 shift value
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH