In {TAIL ~ other embodiments}, {HEAD ~ both processors} may be gated in the illustrated manner, or any of the other units shown in FIG 8 may be gated  
In
In { TAIL ~ other embodiments } , { HEAD ~ both processors } may be gated in the illustrated manner , or any of the other units shown in FIG 8 may be gated
REL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH