Write buffering may also be dynamically disabled for individual peripherals based on the state of a peripheral by using {TAIL ~ a hardware side band signal} driven by {HEAD ~ the peripheral} to override a static buffer write policy programmed in control registers 
Write buffering may also be dynamically disabled for individual peripherals based on the state of a peripheral by using { TAIL ~ a hardware side band signal } driven by { HEAD ~ the peripheral } to override a static buffer write policy programmed in control registers
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH