A circuit is usable to generate {TAIL ~ a sense amplifier} enable {HEAD ~ signal} for a static random access memory circuit 
A circuit is usable to generate { TAIL ~ a sense amplifier } enable { HEAD ~ signal } for a static random access memory circuit
OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH