four 32 bit registers designated A, B, C and D, wherein {HEAD ~ each register} holds {TAIL ~ a value}; and 
holds
four 32 bit registers designated A , B , C and D , wherein { HEAD ~ each register } holds { TAIL ~ a value } ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH