The architecture includes a decoding scheme wherein the EEPROM chip has a row address bit which is used for the row decoding also participating in {HEAD ~ the column} decoding {TAIL ~ process} 
decoding
The architecture includes a decoding scheme wherein the EEPROM chip has a row address bit which is used for the row decoding also participating in { HEAD ~ the column } decoding { TAIL ~ process }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL