passing the clock signal through the clock gater in {HEAD ~ response} to {TAIL ~ the test enable signal} having a first state 
to
passing the clock signal through the clock gater in { HEAD ~ response } to { TAIL ~ the test enable signal } having a first state
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH