{HEAD ~ A memory device} for storing data into and receiving {TAIL ~ data} from a logical vector register circuit accessed as a first number of register subarrays each containing a plurality of words, said memory device comprising: 
for receiving
{ HEAD ~ A memory device } for storing data into and receiving { TAIL ~ data } from a logical vector register circuit accessed as a first number of register subarrays each containing a plurality of words , said memory device comprising :
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH