passing the clock signal through {HEAD ~ the clock gater} in {TAIL ~ response} to the test enable signal having a first state 
in
passing the clock signal through { HEAD ~ the clock gater } in { TAIL ~ response } to the test enable signal having a first state
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH