In {HEAD ~ a data processing system memory address control apparatus} connected to {TAIL ~ a main memory unit} and a processing unit including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: 
connected to
In { HEAD ~ a data processing system memory address control apparatus } connected to { TAIL ~ a main memory unit } and a processing unit including an instruction fetch unit , an operand fetch unit , and an execution unit , said control apparatus comprising :
OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH