Extra latency is added between the time {HEAD ~ a memory controller} issues a write instruction and {TAIL ~ the time} the data is transferred on the data bus 
issues
Extra latency is added between the time { HEAD ~ a memory controller } issues a write instruction and { TAIL ~ the time } the data is transferred on the data bus
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH