{HEAD ~ A control signal} is generated to control {TAIL ~ the variable delay circuit} so that a delayed test signal jitters 
is generated to control
{ HEAD ~ A control signal } is generated to control { TAIL ~ the variable delay circuit } so that a delayed test signal jitters
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH