The circuit 1, wherein {HEAD ~ the delay circuit} delays {TAIL ~ the internal vertical synchronization signal} by about 1.5 μsec 
delays
The circuit 1 , wherein { HEAD ~ the delay circuit } delays { TAIL ~ the internal vertical synchronization signal } by about 1.5 μsec
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH