The first subcircuit and {HEAD ~ the third subcircuit} are configured to pull the first node and {TAIL ~ the second node}, respectively, to a common precharge voltage in response to a first state of the clock signal in order to pass the clock signal 
are configured to pull
The first subcircuit and { HEAD ~ the third subcircuit } are configured to pull the first node and { TAIL ~ the second node } , respectively , to a common precharge voltage in response to a first state of the clock signal in order to pass the clock signal
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH