{TAIL ~ The invention} provides {HEAD ~ a simple interface circuit} between a large capacity, high speed DRAM and a single port SRAM cache to achieve fast cycle memory performance 
{ TAIL ~ The invention } provides { HEAD ~ a simple interface circuit } between a large capacity , high speed DRAM and a single port SRAM cache to achieve fast cycle memory performance
TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH