Memory controller 801 within {TAIL ~ memory subsystem} 800 receives a command from the address switch via unidirectional bus 802, also labeled as bus AInX, through a number of {HEAD ~ latches} FD 803, which is merely a fixed delay pipe 
Memory controller 801 within { TAIL ~ memory subsystem } 800 receives a command from the address switch via unidirectional bus 802 , also labeled as bus AInX , through a number of { HEAD ~ latches } FD 803 , which is merely a fixed delay pipe
OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH