passing the clock signal through {HEAD ~ the clock gater} in response to the test enable signal having {TAIL ~ a first state} 
passing the clock signal through { HEAD ~ the clock gater } in response to the test enable signal having { TAIL ~ a first state }
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL