The apparatus 8 wherein {HEAD ~ the test control signal} is {TAIL ~ a test mode select signal} and the module test control signal is a module test mode select signal 
is
The apparatus 8 wherein { HEAD ~ the test control signal } is { TAIL ~ a test mode select signal } and the module test control signal is a module test mode select signal
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH