According to one aspect of the present invention, a delay circuit delays an internal vertical synchronization signal, and there by {HEAD ~ the timing} of an internal horizontal synchronization signal and {TAIL ~ an internal vertical synchronization signal} can be shifted by a predetermined short period of time 
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According to one aspect of the present invention , a delay circuit delays an internal vertical synchronization signal , and there by { HEAD ~ the timing } of an internal horizontal synchronization signal and { TAIL ~ an internal vertical synchronization signal } can be shifted by a predetermined short period of time
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH