A fourth multiplexer is included in the memory controller to receive the output signal of the third multiplexer and {HEAD ~ the output signal} of {TAIL ~ the eleventh FF} 
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A fourth multiplexer is included in the memory controller to receive the output signal of the third multiplexer and { HEAD ~ the output signal } of { TAIL ~ the eleventh FF }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL