{HEAD ~ a third inverted XOR logic gate} having as {TAIL ~ inputs} said first filtered signal and said chip sequence, 
{ HEAD ~ a third inverted XOR logic gate } having as { TAIL ~ inputs } said first filtered signal and said chip sequence ,
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH