{HEAD ~ The memory management unit} is operable to determine {TAIL ~ configuration} of at least some of the plurality of memory modules to form a memory block, identify an interface MMW transceiver to provide a wireless link to the memory block, and generate a configuration signal based on the determined configuration and the identified interface MMW transceiver 
is operable to determine
{ HEAD ~ The memory management unit } is operable to determine { TAIL ~ configuration } of at least some of the plurality of memory modules to form a memory block , identify an interface MMW transceiver to provide a wireless link to the memory block , and generate a configuration signal based on the determined configuration and the identified interface MMW transceiver
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH