an interlayer dielectric layer provided over the semiconductor layer and {HEAD ~ the non volatile memory transistor} with {TAIL ~ the interlayer dielectric layer} being in direct contact with a component of the non volatile memory transistor, 
an interlayer dielectric layer provided over the semiconductor layer and { HEAD ~ the non volatile memory transistor } with { TAIL ~ the interlayer dielectric layer } being in direct contact with a component of the non volatile memory transistor ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH