{TAIL ~ The analyzer} includes a load bank consisting of a plurality of {HEAD ~ resistors} in selective parallel interconnection 
{ TAIL ~ The analyzer } includes a load bank consisting of a plurality of { HEAD ~ resistors } in selective parallel interconnection
TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH