If it is present, a data address of {TAIL ~ the target identifier} in the cache memory is transmitted to {HEAD ~ the CPU} 
If it is present , a data address of { TAIL ~ the target identifier } in the cache memory is transmitted to { HEAD ~ the CPU }
OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD