{HEAD ~ The output} of only one NAND gate will go to {TAIL ~ logical 0 state} when both its input lines are at logic 1 state simultaneously, and so the outputs of the remaining NAND gates will be at logical 1 state 
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{ HEAD ~ The output } of only one NAND gate will go to { TAIL ~ logical 0 state } when both its input lines are at logic 1 state simultaneously , and so the outputs of the remaining NAND gates will be at logical 1 state
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH