The circuit 1, wherein {HEAD ~ the delay circuit} delays the internal vertical synchronization signal by {TAIL ~ about 1.5 μsec} 
The circuit 1 , wherein { HEAD ~ the delay circuit } delays the internal vertical synchronization signal by { TAIL ~ about 1.5 μsec }
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL