The method reduces {HEAD ~ the number} of {TAIL ~ vias} in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications 
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The method reduces { HEAD ~ the number } of { TAIL ~ vias } in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH