Then, {TAIL ~ second semiconductor substrate} 12 is etched down to {HEAD ~ a predetermined depth} to provide etched area 17 as shown in FIG 3G 
Then , { TAIL ~ second semiconductor substrate } 12 is etched down to { HEAD ~ a predetermined depth } to provide etched area 17 as shown in FIG 3 G
OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH