address decoder means responsive to {HEAD ~ one portion} of said logical address in said register for selecting and reading out to said TLB a set having {TAIL ~ mT compartments} in said TLB, 
address decoder means responsive to { HEAD ~ one portion } of said logical address in said register for selecting and reading out to said TLB a set having { TAIL ~ mT compartments } in said TLB ,
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH