This disclosure refers to multiprocessor systems having {HEAD ~ individual cache memories} including {TAIL ~ means} to keep the cache memories coherent 
including
This disclosure refers to multiprocessor systems having { HEAD ~ individual cache memories } including { TAIL ~ means } to keep the cache memories coherent
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH