{HEAD ~ A memory device} for storing {TAIL ~ data} into and receiving data from a logical vector register circuit accessed as a first number of register subarrays each containing a plurality of words, said memory device comprising: 
for storing
{ HEAD ~ A memory device } for storing { TAIL ~ data } into and receiving data from a logical vector register circuit accessed as a first number of register subarrays each containing a plurality of words , said memory device comprising :
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH