{HEAD ~ The first address compare circuit} generates {TAIL ~ a redundant address selection signal} when the received address is the same as the first redundant address 
generates
{ HEAD ~ The first address compare circuit } generates { TAIL ~ a redundant address selection signal } when the received address is the same as the first redundant address
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH