The width of {HEAD ~ the non conductive region}, designated {TAIL ~ Ls} in FIG 3, is selected to increase the base width of the parasitic NPN bipolar transistor 39 while preserving the surface area of the device 
designated
The width of { HEAD ~ the non conductive region } , designated { TAIL ~ Ls } in FIG 3 , is selected to increase the base width of the parasitic NPN bipolar transistor 39 while preserving the surface area of the device
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH