The first programmable delay receives {HEAD ~ a first set} of one or more bits from the configuration register and {TAIL ~ a double speed clock signal} 
The first programmable delay receives { HEAD ~ a first set } of one or more bits from the configuration register and { TAIL ~ a double speed clock signal }
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL