{HEAD ~ a Dual Port RAM} connected to {TAIL ~ the single electrical interface}, the Dual Port RAM configured to parallelly transfer data through the single electrical interface; and 
connected to
{ HEAD ~ a Dual Port RAM } connected to { TAIL ~ the single electrical interface } , the Dual Port RAM configured to parallelly transfer data through the single electrical interface ; and
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH