One aspect of this invention comprises an architecture and circuitry that enables random read and write operations into cells in {HEAD ~ an array} that contains {TAIL ~ staggered source} or drain connections from the memory cells in a given column to the bit lines such as the architecture of FIG 2 of U.S. Pat 
contains
One aspect of this invention comprises an architecture and circuitry that enables random read and write operations into cells in { HEAD ~ an array } that contains { TAIL ~ staggered source } or drain connections from the memory cells in a given column to the bit lines such as the architecture of FIG 2 of U.S. Pat
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH