A vertical synchronization signal separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in {TAIL ~ the H countdown circuit} 14, and based on {HEAD ~ an obtained V reset signal}, a vertical synchronization signal is obtained in a VS output circuit 18 
A vertical synchronization signal separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in { TAIL ~ the H countdown circuit } 14 , and based on { HEAD ~ an obtained V reset signal } , a vertical synchronization signal is obtained in a VS output circuit 18
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH