When a low logic level is asserted in device A, {HEAD ~ the portion} of the circuit in device B causes {TAIL ~ a low logic level} to be asserted in device B at the converted level 
causes
When a low logic level is asserted in device A , { HEAD ~ the portion } of the circuit in device B causes { TAIL ~ a low logic level } to be asserted in device B at the converted level
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH