The memory device 1, wherein K is two, and wherein {HEAD ~ a first control line} is associated with a rising edge of the clock signal and a second control line is associated with a falling edge of {TAIL ~ the clock signal} 
The memory device 1 , wherein K is two , and wherein { HEAD ~ a first control line } is associated with a rising edge of the clock signal and a second control line is associated with a falling edge of { TAIL ~ the clock signal }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL