{HEAD ~ The latter transistor} is controlled by {TAIL ~ a N channel transistor} 315 whose gate electrode is driven by the GG reset output pin of the host controller 104 
is controlled by
{ HEAD ~ The latter transistor } is controlled by { TAIL ~ a N channel transistor } 315 whose gate electrode is driven by the GG reset output pin of the host controller 104
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH