The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by {HEAD ~ combinational circuits} within {TAIL ~ the pipeline circuit} 
within
The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by { HEAD ~ combinational circuits } within { TAIL ~ the pipeline circuit }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL