At the same time output terminals L1, L2 and {HEAD ~ L3} will be at {TAIL ~ logical 0 state} 
at
At the same time output terminals L1 , L2 and { HEAD ~ L3 } will be at { TAIL ~ logical 0 state }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL