The apparatus 14 wherein the clocking circuit includes a plurality of levels of clock buffer circuitry, and wherein a first level of the plurality of levels includes {HEAD ~ one or more logic gates} which combine the clock input and {TAIL ~ the control signal input} 
combine
The apparatus 14 wherein the clocking circuit includes a plurality of levels of clock buffer circuitry , and wherein a first level of the plurality of levels includes { HEAD ~ one or more logic gates } which combine the clock input and { TAIL ~ the control signal input }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL