{TAIL ~ The first and second sub gates} of {HEAD ~ the first gate} are separated by a first intergate dielectric layer 
{ TAIL ~ The first and second sub gates } of { HEAD ~ the first gate } are separated by a first intergate dielectric layer
TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH