address decoder means responsive to one portion of said {HEAD ~ logical address} in said register for selecting and reading out to said TLB a set having mT compartments in said {TAIL ~ TLB}, 
address decoder means responsive to one portion of said { HEAD ~ logical address } in said register for selecting and reading out to said TLB a set having mT compartments in said { TAIL ~ TLB } ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH