Although each bit of {TAIL ~ the transmitted data} is kept output during the time period from the asserting edge AG to the next asserting edge AG of the transmission clock signal SCLKO, the holding interval T of {HEAD ~ the final bit} is determined by the holding interval decision register 9 
Although each bit of { TAIL ~ the transmitted data } is kept output during the time period from the asserting edge AG to the next asserting edge AG of the transmission clock signal SCLKO , the holding interval T of { HEAD ~ the final bit } is determined by the holding interval decision register 9
OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH