An improved circuit design is disclosed that enables a faster and more reliable read process since {HEAD ~ the reference} is {TAIL ~ a second MTJ} within the same bit cell 
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An improved circuit design is disclosed that enables a faster and more reliable read process since { HEAD ~ the reference } is { TAIL ~ a second MTJ } within the same bit cell
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH