Moreover, both an n bit row address in the normal area and an m bit row address in the parity area can be generated through {TAIL ~ switching control} of a connected state with {HEAD ~ the first switching circuit} 
Moreover , both an n bit row address in the normal area and an m bit row address in the parity area can be generated through { TAIL ~ switching control } of a connected state with { HEAD ~ the first switching circuit }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD