{HEAD ~ The differential amplifier} 60, wherein {TAIL ~ the main differential amplifier} includes a second differential pair including a fifth transistor and a sixth transistor, the second differential pair, wherein the second differential pair is adapted to receive the shifted differential voltage signal to generate the output signal 
wherein
{ HEAD ~ The differential amplifier } 60 , wherein { TAIL ~ the main differential amplifier } includes a second differential pair including a fifth transistor and a sixth transistor , the second differential pair , wherein the second differential pair is adapted to receive the shifted differential voltage signal to generate the output signal
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH