{HEAD ~ four 32 bit registers} designated {TAIL ~ A}, B, C and D, wherein each register holds a value; and 
designated
{ HEAD ~ four 32 bit registers } designated { TAIL ~ A } , B , C and D , wherein each register holds a value ; and
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH