a seventh step which divides the number of counts into cycle count values of the speed detection signal and computes {HEAD ~ a first time ratio} between the input timing of the current reproducing control signal and {TAIL ~ the input timing} of the first speed detection signal after the current reproducing control signal is inputted 
between
a seventh step which divides the number of counts into cycle count values of the speed detection signal and computes { HEAD ~ a first time ratio } between the input timing of the current reproducing control signal and { TAIL ~ the input timing } of the first speed detection signal after the current reproducing control signal is inputted
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH