This additional latency is optimized to reduce {HEAD ~ the number} of idle time slots on {TAIL ~ the data bus} when switching between a read instruction and a write instruction 
This additional latency is optimized to reduce { HEAD ~ the number } of idle time slots on { TAIL ~ the data bus } when switching between a read instruction and a write instruction
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH