Moreover, both an n bit row address in the normal area and an m bit row address in the parity area can be generated through switching control of {HEAD ~ a connected state} with {TAIL ~ the first switching circuit} 
with
Moreover , both an n bit row address in the normal area and an m bit row address in the parity area can be generated through switching control of { HEAD ~ a connected state } with { TAIL ~ the first switching circuit }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL