{HEAD ~ The apparatus} 1 wherein {TAIL ~ said load bank} comprises a plurality of resistors in selective parallel interconnection 
wherein
{ HEAD ~ The apparatus } 1 wherein { TAIL ~ said load bank } comprises a plurality of resistors in selective parallel interconnection
HEAD HEAD HEAD HEAD HEAD HEAD OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH