Said first and second path being effective for said central processing units and said address sourcing devices to access the first part of the memory without contention with each other, and for diminishing contention with each other when accessing {HEAD ~ the second part} of {TAIL ~ the memory} 
of
Said first and second path being effective for said central processing units and said address sourcing devices to access the first part of the memory without contention with each other , and for diminishing contention with each other when accessing { HEAD ~ the second part } of { TAIL ~ the memory }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL