In FIGS 6 a to 6 d are shown, in slice planes, different arrangements for {HEAD ~ a wafer scale package} comprising {TAIL ~ solid state image sensors} , according to the principle of the present invention 
comprising
In FIGS 6 a to 6 d are shown , in slice planes , different arrangements for { HEAD ~ a wafer scale package } comprising { TAIL ~ solid state image sensors } , according to the principle of the present invention
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH