A memory device for storing data into and receiving data from a logical vector register circuit accessed as {HEAD ~ a first number} of {TAIL ~ register subarrays} each containing a plurality of words, said memory device comprising: 
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A memory device for storing data into and receiving data from a logical vector register circuit accessed as { HEAD ~ a first number } of { TAIL ~ register subarrays } each containing a plurality of words , said memory device comprising :
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH