Note that {TAIL ~ any} of {HEAD ~ the signals} described herein can be designed as either negative or positive logic signals 
Note that { TAIL ~ any } of { HEAD ~ the signals } described herein can be designed as either negative or positive logic signals
OTH OTH TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH