{HEAD ~ A display control device} 1, wherein {TAIL ~ said timer} means is a counter which is reset in response to the assertion of the reset signal and asserts the timer signal when said counter has counted up to a value corresponding to the predetermined period of time 
wherein
{ HEAD ~ A display control device } 1 , wherein { TAIL ~ said timer } means is a counter which is reset in response to the assertion of the reset signal and asserts the timer signal when said counter has counted up to a value corresponding to the predetermined period of time
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH