{HEAD ~ An output signal} showing {TAIL ~ multiplication result} of the first and second input signals is differentially derived between the collectors or drains of the first and fourth transistors and the collectors or drains of the second and third transistors 
showing
{ HEAD ~ An output signal } showing { TAIL ~ multiplication result } of the first and second input signals is differentially derived between the collectors or drains of the first and fourth transistors and the collectors or drains of the second and third transistors
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH