{HEAD ~ The apparatus} includes a storage circuit, {TAIL ~ a first processing circuit} which accesses the storage circuit for processing data obtained from each of the packets, and a second processing circuit which accesses the storage circuit for processing data stored in the storage circuit 
includes
{ HEAD ~ The apparatus } includes a storage circuit , { TAIL ~ a first processing circuit } which accesses the storage circuit for processing data obtained from each of the packets , and a second processing circuit which accesses the storage circuit for processing data stored in the storage circuit
HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH