A plurality of integrated circuit features are provided in the context of {HEAD ~ an array} of {TAIL ~ memory cells} including a plurality of word lines and a plurality of bit lines 
of
A plurality of integrated circuit features are provided in the context of { HEAD ~ an array } of { TAIL ~ memory cells } including a plurality of word lines and a plurality of bit lines
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH