{HEAD ~ a second multiplexer} receiving as inputs {TAIL ~ an output} of said second inverted XOR gate and an output of said third inverted XOR gate, said first and second multiplexers under control of a common clocking signal, 
receiving
{ HEAD ~ a second multiplexer } receiving as inputs { TAIL ~ an output } of said second inverted XOR gate and an output of said third inverted XOR gate , said first and second multiplexers under control of a common clocking signal ,
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH