The interface circuit schedules parallel pipeline operations so that {HEAD ~ one set} of data buses can be shared in {TAIL ~ cycles} by several data flows to save chip area and alleviate data congestion 
shared in
The interface circuit schedules parallel pipeline operations so that { HEAD ~ one set } of data buses can be shared in { TAIL ~ cycles } by several data flows to save chip area and alleviate data congestion
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH