{HEAD ~ The output} of the adder 12 is clocked into {TAIL ~ a latch} 14 by a system clock CLK 
is clocked into
{ HEAD ~ The output } of the adder 12 is clocked into { TAIL ~ a latch } 14 by a system clock CLK
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH