{TAIL ~ The processor} assigns {HEAD ~ each instruction} a thread ID and error information as it follows the pipeline 
{ TAIL ~ The processor } assigns { HEAD ~ each instruction } a thread ID and error information as it follows the pipeline
TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH