passing {TAIL ~ the clock signal} through the clock gater in {HEAD ~ response} to the test enable signal having a first state 
passing { TAIL ~ the clock signal } through the clock gater in { HEAD ~ response } to the test enable signal having a first state
OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH