The multiple read/write pipelines share a read circuit and a write circuit to reduce {TAIL ~ the circuit area} of {HEAD ~ each pipeline} and the circuit area of the memory as a whole 
The multiple read / write pipelines share a read circuit and a write circuit to reduce { TAIL ~ the circuit area } of { HEAD ~ each pipeline } and the circuit area of the memory as a whole
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH