Also, {HEAD ~ the negated data input line} is connected in like manner through a second CMOS transfer gate to the input of a second NOT circuit and through an n transistor with {TAIL ~ crossover} to the gate of a low resistance n transistor in the read circuit which is associated with the true data line 
is connected with
Also , { HEAD ~ the negated data input line } is connected in like manner through a second CMOS transfer gate to the input of a second NOT circuit and through an n transistor with { TAIL ~ crossover } to the gate of a low resistance n transistor in the read circuit which is associated with the true data line
OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH