{HEAD ~ The memory address control apparatus} includes an instruction address translation look aside buffer for translating logical addresses to real addresses in the MMU at which instructions are stored and an operand data address translation look aside buffer for translating {TAIL ~ logical addresses} to real addresses in the MMU at which operand data are stored 
{ HEAD ~ The memory address control apparatus } includes an instruction address translation look aside buffer for translating logical addresses to real addresses in the MMU at which instructions are stored and an operand data address translation look aside buffer for translating { TAIL ~ logical addresses } to real addresses in the MMU at which operand data are stored
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