The apparatus 71 wherein said processor circuit is configured to define, as {TAIL ~ said second meaningful grouping}, {HEAD ~ a theme} comprising said at least two patterns 
as
The apparatus 71 wherein said processor circuit is configured to define , as { TAIL ~ said second meaningful grouping } , { HEAD ~ a theme } comprising said at least two patterns
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH