{HEAD ~ An internal clock} is synchronized with {TAIL ~ a horizontal synchronization signal} separated in a synchronization separation circuit 10, an H reset signal is generated based thereon in an H countdown circuit 14, and a horizontal synchronization signal is generated based thereon 
is synchronized with
{ HEAD ~ An internal clock } is synchronized with { TAIL ~ a horizontal synchronization signal } separated in a synchronization separation circuit 10 , an H reset signal is generated based thereon in an H countdown circuit 14 , and a horizontal synchronization signal is generated based thereon
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH