{HEAD ~ A predetermined voltage} generated by the second FET is applied to {TAIL ~ the gate} of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor 
is applied to
{ HEAD ~ A predetermined voltage } generated by the second FET is applied to { TAIL ~ the gate } of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH