Once a steady state condition is reached, {HEAD ~ the voltage} produced across load resistor RL, i.e. the voltage Eo, will have {TAIL ~ the desired DC voltage level} 
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Once a steady state condition is reached , { HEAD ~ the voltage } produced across load resistor RL , i.e. the voltage Eo , will have { TAIL ~ the desired DC voltage level }
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL