The control circuit may be configured to generate {HEAD ~ a control signal} in {TAIL ~ response} to a data signal, a half rate clock signal, and a quadrature of the half rate clock signal 
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The control circuit may be configured to generate { HEAD ~ a control signal } in { TAIL ~ response } to a data signal , a half rate clock signal , and a quadrature of the half rate clock signal
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH