{HEAD ~ a third inverted XOR logic gate} having as inputs said first filtered signal and said {TAIL ~ chip sequence}, 
having
{ HEAD ~ a third inverted XOR logic gate } having as inputs said first filtered signal and said { TAIL ~ chip sequence } ,
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH