{HEAD ~ The second gate} is electrically connected to {TAIL ~ the first gate}, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed 
is electrically connected to
{ HEAD ~ The second gate } is electrically connected to { TAIL ~ the first gate } , and the second source is electrically connected to the first source , such that when the DMOS device is ON , a surface channel and a buried channel are formed
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH