With reference now to FIG 8, {HEAD ~ a diagram} depicts a memory subsystem connected to the address switch of {TAIL ~ the distributed system} of the present invention 
With reference now to FIG 8 , { HEAD ~ a diagram } depicts a memory subsystem connected to the address switch of { TAIL ~ the distributed system } of the present invention
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH