When {HEAD ~ a high logic level} is asserted in {TAIL ~ device A}, the portion of the circuit in device B causes a high logic level to be asserted in device B also at the converted level 
is asserted in
When { HEAD ~ a high logic level } is asserted in { TAIL ~ device A } , the portion of the circuit in device B causes a high logic level to be asserted in device B also at the converted level
OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH