According to one embodiment of the invention, {HEAD ~ a method} for simulating {TAIL ~ the operation} of an integrated circuit is provided 
for simulating
According to one embodiment of the invention , { HEAD ~ a method } for simulating { TAIL ~ the operation } of an integrated circuit is provided
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH