{HEAD ~ This additional latency} is optimized to reduce {TAIL ~ the number} of idle time slots on the data bus when switching between a read instruction and a write instruction 
is optimized to reduce
{ HEAD ~ This additional latency } is optimized to reduce { TAIL ~ the number } of idle time slots on the data bus when switching between a read instruction and a write instruction
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH