It includes a decoding scheme wherein {HEAD ~ the memory chip} has {TAIL ~ a row address bit} which is used for the row decoding also participates in the column and bit line decoding process 
has
It includes a decoding scheme wherein { HEAD ~ the memory chip } has { TAIL ~ a row address bit } which is used for the row decoding also participates in the column and bit line decoding process
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH