wherein an output signal showing a result of multiplication of said first and second input signals is differentially derived between said collectors or drains of said first and fourth transistors and said {HEAD ~ collectors} or drains of {TAIL ~ said second and third transistors} 
of
wherein an output signal showing a result of multiplication of said first and second input signals is differentially derived between said collectors or drains of said first and fourth transistors and said { HEAD ~ collectors } or drains of { TAIL ~ said second and third transistors }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL