{HEAD ~ The process} 9, wherein {TAIL ~ the gate electrode} comprises in situ doped polysilicon 
wherein
{ HEAD ~ The process } 9 , wherein { TAIL ~ the gate electrode } comprises in situ doped polysilicon
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH