The SBACK1 and SBACK2 signals 480, 485 acknowledge whether the CPU module 120 or the CPU module 125, respectively, has been assigned {TAIL ~ control} of {HEAD ~ the system bus} 110 after the CPU module currently on the system bus 110 has finished 
The SBACK1 and SBACK2 signals 480 , 485 acknowledge whether the CPU module 120 or the CPU module 125 , respectively , has been assigned { TAIL ~ control } of { HEAD ~ the system bus } 110 after the CPU module currently on the system bus 110 has finished
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH