{HEAD ~ a fixed 32 bit shift unit} configured to effect a fixed bit shift on an output of the second adder, wherein {TAIL ~ the fixed 32 bit shift unit} implements only a single hardware implemented MD5 shift value 
{ HEAD ~ a fixed 32 bit shift unit } configured to effect a fixed bit shift on an output of the second adder , wherein { TAIL ~ the fixed 32 bit shift unit } implements only a single hardware implemented MD5 shift value
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH