The analyzer includes {HEAD ~ a load bank} consisting of a plurality of {TAIL ~ resistors} in selective parallel interconnection 
The analyzer includes { HEAD ~ a load bank } consisting of a plurality of { TAIL ~ resistors } in selective parallel interconnection
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH