A ROM memory array comprises {HEAD ~ a doped silicon substrate} having a surface with a first array of {TAIL ~ parallel bitlines} formed in the substrate at the surface with an array of channel regions between the bitlines 
A ROM memory array comprises { HEAD ~ a doped silicon substrate } having a surface with a first array of { TAIL ~ parallel bitlines } formed in the substrate at the surface with an array of channel regions between the bitlines
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH