wherein, in the step , a gate electrode of {TAIL ~ a third MISFET} is formed by patterning the conductive film such that the gate electrode of the second MISFET is arranged, in the first direction, between {HEAD ~ the gate electrode} of the first MISFET and the gate electrode of the third MISFET, 
wherein , in the step , a gate electrode of { TAIL ~ a third MISFET } is formed by patterning the conductive film such that the gate electrode of the second MISFET is arranged , in the first direction , between { HEAD ~ the gate electrode } of the first MISFET and the gate electrode of the third MISFET ,
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH