The lock includes a counter and {HEAD ~ a gate} for inhibiting {TAIL ~ clock pulses} to the memory element until a predetermined number of control pulses have been received to initiate a read/write operation 
for inhibiting
The lock includes a counter and { HEAD ~ a gate } for inhibiting { TAIL ~ clock pulses } to the memory element until a predetermined number of control pulses have been received to initiate a read / write operation
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH