The apparatus 1 wherein {TAIL ~ said load bank} comprises a plurality of {HEAD ~ resistors} in selective parallel interconnection 
The apparatus 1 wherein { TAIL ~ said load bank } comprises a plurality of { HEAD ~ resistors } in selective parallel interconnection
OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH