Another specific embodiment of the invention provides {HEAD ~ a memory architecture} that includes a memory array for storing data values, multiple sensing circuits, multiple switches, multiple control lines, {TAIL ~ a column timing switch control circuit}, and an I/O pad 
includes
Another specific embodiment of the invention provides { HEAD ~ a memory architecture } that includes a memory array for storing data values , multiple sensing circuits , multiple switches , multiple control lines , { TAIL ~ a column timing switch control circuit } , and an I / O pad
OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH