A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of the instructions located in the main memory , the other for storing a portion of {TAIL ~ the operand data} located in {HEAD ~ main memory} 
A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of the instructions located in the main memory , the other for storing a portion of { TAIL ~ the operand data } located in { HEAD ~ main memory }
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