The analyzer includes {TAIL ~ a load bank} consisting of a plurality of resistors in {HEAD ~ selective parallel interconnection} 
The analyzer includes { TAIL ~ a load bank } consisting of a plurality of resistors in { HEAD ~ selective parallel interconnection }
OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD