As will subsequently appear, provision is made in the digital logic circuitry for taking the pattern elements A, B, C, and D from a present scan, while {HEAD ~ the elements E}, F, and G are taken from {TAIL ~ a previous scan} 
are taken from
As will subsequently appear , provision is made in the digital logic circuitry for taking the pattern elements A , B , C , and D from a present scan , while { HEAD ~ the elements E } , F , and G are taken from { TAIL ~ a previous scan }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL