The memory sharing arrangement provides {TAIL ~ a separate high speed data transfer mechanism} between the PLCs and {HEAD ~ the DSP} 
The memory sharing arrangement provides { TAIL ~ a separate high speed data transfer mechanism } between the PLCs and { HEAD ~ the DSP }
OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD