The memory core includes {HEAD ~ vertical electrically erasable and programmable read only memories cells} having, for example, a stacked gate or {TAIL ~ a split channel configuration} 
having
The memory core includes { HEAD ~ vertical electrically erasable and programmable read only memories cells } having , for example , a stacked gate or { TAIL ~ a split channel configuration }
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL