In the embodiment illustrated in FIG 2, region 0 includes mask bits 3:0 and is the least significant region; region 1 includes mask bits 7:4 and is more significant than region 0 and less significant than regions 2 and 3; {HEAD ~ region} 2 includes mask bits 11:8 and is more significant than {TAIL ~ regions} 0 and 1 and less significant than region 3; and region 3 includes mask bits 15:12 and is the most significant region 
is more significant than
In the embodiment illustrated in FIG 2 , region 0 includes mask bits 3:0 and is the least significant region ; region 1 includes mask bits 7:4 and is more significant than region 0 and less significant than regions 2 and 3 ; { HEAD ~ region } 2 includes mask bits 11:8 and is more significant than { TAIL ~ regions } 0 and 1 and less significant than region 3 ; and region 3 includes mask bits 15:12 and is the most significant region
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