The suppression circuit may be a single varistor or {TAIL ~ a number} of varistors in parallel with {HEAD ~ a number} of lines in the distribution circuit 
The suppression circuit may be a single varistor or { TAIL ~ a number } of varistors in parallel with { HEAD ~ a number } of lines in the distribution circuit
OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH