{HEAD ~ Memory controller} 801 within memory subsystem 800 receives {TAIL ~ a command} from the address switch via unidirectional bus 802, also labeled as bus AInX, through a number of latches FD 803, which is merely a fixed delay pipe 
receives
{ HEAD ~ Memory controller } 801 within memory subsystem 800 receives { TAIL ~ a command } from the address switch via unidirectional bus 802 , also labeled as bus AInX , through a number of latches FD 803 , which is merely a fixed delay pipe
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH