In {HEAD ~ this manner}, a command sent by the address switch experiences a fixed number of cycles of delay before {TAIL ~ the command} is made available to the memory controller 
In { HEAD ~ this manner } , a command sent by the address switch experiences a fixed number of cycles of delay before { TAIL ~ the command } is made available to the memory controller
OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH