The UART 103 comprises {TAIL ~ one or more registers} for buffering {HEAD ~ data} that is to be transmitted or data that have been received 
The UART 103 comprises { TAIL ~ one or more registers } for buffering { HEAD ~ data } that is to be transmitted or data that have been received
OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH