a second inverted XOR logic gate having as {TAIL ~ inputs} said {HEAD ~ second filtered signal} and said chip sequence, 
as
a second inverted XOR logic gate having as { TAIL ~ inputs } said { HEAD ~ second filtered signal } and said chip sequence ,
OTH OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH