The bus enables single or multiple controllers to access {HEAD ~ real time information} generated by {TAIL ~ the attached hardware} 
generated by
The bus enables single or multiple controllers to access { HEAD ~ real time information } generated by { TAIL ~ the attached hardware }
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL