The combination 1 wherein said logic means includes means for connecting {TAIL ~ said parallel shift register paths} into a single shift register scan path including {HEAD ~ the shift register paths} of all the individual logic units 
The combination 1 wherein said logic means includes means for connecting { TAIL ~ said parallel shift register paths } into a single shift register scan path including { HEAD ~ the shift register paths } of all the individual logic units
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH