{TAIL ~ Clock gating} of sub circuits within {HEAD ~ a processor execution unit} responsive to instruction latency counter within processor issue circuit 
{ TAIL ~ Clock gating } of sub circuits within { HEAD ~ a processor execution unit } responsive to instruction latency counter within processor issue circuit
TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH