The phase detector circuitry may be configured to generate the control signal based on {HEAD ~ a first time difference} and {TAIL ~ a second time difference} 
The phase detector circuitry may be configured to generate the control signal based on { HEAD ~ a first time difference } and { TAIL ~ a second time difference }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL