The sampling and {TAIL ~ holding} of {HEAD ~ bits states} are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines 
The sampling and { TAIL ~ holding } of { HEAD ~ bits states } are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines
OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH