The protocol supports a memory subsystem which queues memory requests such that {TAIL ~ the processor}, or cache memory requesting {HEAD ~ data}, relinquishes the shared bus after making its request 
The protocol supports a memory subsystem which queues memory requests such that { TAIL ~ the processor } , or cache memory requesting { HEAD ~ data } , relinquishes the shared bus after making its request
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH