generating and outputting {HEAD ~ a robust phase error signal} representative of {TAIL ~ said robust phase error}; and 
generating and outputting { HEAD ~ a robust phase error signal } representative of { TAIL ~ said robust phase error } ; and
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH