A fourth multiplexer is included in the memory controller to receive {HEAD ~ the output signal} of {TAIL ~ the third multiplexer} and the output signal of the eleventh FF 
A fourth multiplexer is included in the memory controller to receive { HEAD ~ the output signal } of { TAIL ~ the third multiplexer } and the output signal of the eleventh FF
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH