{HEAD ~ a shift} register {TAIL ~ memory device} having data input and output means for receiving and delivering data, respectively, and a clock input for receiving clock pulses, said shift register operative to store and to shift data stored within in read/write operations upon receipt of clock pulses 
{ HEAD ~ a shift } register { TAIL ~ memory device } having data input and output means for receiving and delivering data , respectively , and a clock input for receiving clock pulses , said shift register operative to store and to shift data stored within in read / write operations upon receipt of clock pulses
HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH