The method 1, wherein obtaining the pipeline semiconductor layout of the single redundant state machine comprises synthesizing a netlist logically describing {HEAD ~ the single redundant state machine} to generate {TAIL ~ the pipeline semiconductor layout} of the single redundant state machine 
The method 1 , wherein obtaining the pipeline semiconductor layout of the single redundant state machine comprises synthesizing a netlist logically describing { HEAD ~ the single redundant state machine } to generate { TAIL ~ the pipeline semiconductor layout } of the single redundant state machine
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH