{TAIL ~ The interface circuit} schedules parallel pipeline operations so that one set of data buses can be shared in cycles by {HEAD ~ several data flows} to save chip area and alleviate data congestion 
{ TAIL ~ The interface circuit } schedules parallel pipeline operations so that one set of data buses can be shared in cycles by { HEAD ~ several data flows } to save chip area and alleviate data congestion
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH