passing {HEAD ~ the clock signal} through the clock gater in {TAIL ~ response} to the test enable signal having a first state 
passing { HEAD ~ the clock signal } through the clock gater in { TAIL ~ response } to the test enable signal having a first state
OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH