The processor also determines whether any other switch controller intends to transmit to {TAIL ~ the determined destination} of {HEAD ~ the packet} at a given time 
The processor also determines whether any other switch controller intends to transmit to { TAIL ~ the determined destination } of { HEAD ~ the packet } at a given time
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH