According to one embodiment of the invention, a method for simulating {HEAD ~ the operation} of {TAIL ~ an integrated circuit} is provided 
According to one embodiment of the invention , a method for simulating { HEAD ~ the operation } of { TAIL ~ an integrated circuit } is provided
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH