a second memory cell column that is connected to {TAIL ~ the second bit line}, {HEAD ~ the second memory cell column} being formed by a plurality of MONOS type transistors 
a second memory cell column that is connected to { TAIL ~ the second bit line } , { HEAD ~ the second memory cell column } being formed by a plurality of MONOS type transistors
OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH