A method of making {HEAD ~ an IGFET} with {TAIL ~ a selectively doped multilevel polysilicon gate} that includes upper and lower polysilicon gate levels is disclosed 
A method of making { HEAD ~ an IGFET } with { TAIL ~ a selectively doped multilevel polysilicon gate } that includes upper and lower polysilicon gate levels is disclosed
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH