The memory device 1, wherein {HEAD ~ K} is two, and wherein a first control line is associated with a rising edge of {TAIL ~ the clock signal} and a second control line is associated with a falling edge of the clock signal 
The memory device 1 , wherein { HEAD ~ K } is two , and wherein a first control line is associated with a rising edge of { TAIL ~ the clock signal } and a second control line is associated with a falling edge of the clock signal
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH