The memory controller further comprises a first multiplexer receiving the output signal of the first FF and {TAIL ~ the write command load signal} and controlled by a first control signal and a second programmable delay receiving the first set of one or more bits from {HEAD ~ the configuration register} and the output signal of the first multiplexer 
The memory controller further comprises a first multiplexer receiving the output signal of the first FF and { TAIL ~ the write command load signal } and controlled by a first control signal and a second programmable delay receiving the first set of one or more bits from { HEAD ~ the configuration register } and the output signal of the first multiplexer
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH