With reference now to FIG 8, a diagram depicts a memory subsystem connected to {TAIL ~ the address switch} of the distributed system of {HEAD ~ the present invention} 
With reference now to FIG 8 , a diagram depicts a memory subsystem connected to { TAIL ~ the address switch } of the distributed system of { HEAD ~ the present invention }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD