The circuit 1, wherein the delay circuit delays {HEAD ~ the internal vertical synchronization signal} by {TAIL ~ about 1.5 μsec} 
The circuit 1 , wherein the delay circuit delays { HEAD ~ the internal vertical synchronization signal } by { TAIL ~ about 1.5 μsec }
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL