wherein {HEAD ~ a predetermined voltage} generated by the second field effect transistor is applied to the gate of {TAIL ~ the first field} effect transistor to set a bias point of the first field effect transistor such that the first field effect transistor comprises characteristics of an integrated precision resistor 
wherein { HEAD ~ a predetermined voltage } generated by the second field effect transistor is applied to the gate of { TAIL ~ the first field } effect transistor to set a bias point of the first field effect transistor such that the first field effect transistor comprises characteristics of an integrated precision resistor
OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH