{HEAD ~ A refresh counter circuit} 5 or 6, wherein each of said path switches comprises a complementary type transfer gate including {TAIL ~ PMOS} and NMOS 
{ HEAD ~ A refresh counter circuit } 5 or 6 , wherein each of said path switches comprises a complementary type transfer gate including { TAIL ~ PMOS } and NMOS
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH