The combination 1 wherein {HEAD ~ said logic means} includes {TAIL ~ means} for connecting said parallel shift register paths into a single shift register scan path including the shift register paths of all the individual logic units 
The combination 1 wherein { HEAD ~ said logic means } includes { TAIL ~ means } for connecting said parallel shift register paths into a single shift register scan path including the shift register paths of all the individual logic units
OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH