{TAIL ~ The phase detector circuitry} may be configured to generate the control signal based on {HEAD ~ a first time difference} and a second time difference 
{ TAIL ~ The phase detector circuitry } may be configured to generate the control signal based on { HEAD ~ a first time difference } and a second time difference
TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH