The semiconductor memory device 6, further comprising {HEAD ~ an adjustment transistor} coupled in parallel with the pull down transistor, wherein the adjustment transistor is configured to be controllable by at least one bit of {TAIL ~ the stack position identifier} 
The semiconductor memory device 6 , further comprising { HEAD ~ an adjustment transistor } coupled in parallel with the pull down transistor , wherein the adjustment transistor is configured to be controllable by at least one bit of { TAIL ~ the stack position identifier }
OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL