{HEAD ~ The lock} includes a counter and {TAIL ~ a gate} for inhibiting clock pulses to the memory element until a predetermined number of control pulses have been received to initiate a read/write operation 
{ HEAD ~ The lock } includes a counter and { TAIL ~ a gate } for inhibiting clock pulses to the memory element until a predetermined number of control pulses have been received to initiate a read / write operation
HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH