In {TAIL ~ another embodiment}, a latency of a DRAM or SRAM is adjusted based on {HEAD ~ the SPID} 
In { TAIL ~ another embodiment } , a latency of a DRAM or SRAM is adjusted based on { HEAD ~ the SPID }
OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD