analyzing a signal processing flow in an area from which {HEAD ~ the asynchronous element} in {TAIL ~ the logic circuit} is excluded 
analyzing a signal processing flow in an area from which { HEAD ~ the asynchronous element } in { TAIL ~ the logic circuit } is excluded
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH