{HEAD ~ The semiconductor package} 1, wherein {TAIL ~ each} of the chips is configured to have a DRAM+controller structure 
{ HEAD ~ The semiconductor package } 1 , wherein { TAIL ~ each } of the chips is configured to have a DRAM+controller structure
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH