{HEAD ~ a third element} processed to generate {TAIL ~ a functional computer executable representation} of a first field effect transistor and a second field effect transistor, wherein a gate of the first field effect transistor is tied to a gate of the second field effect transistor; and 
{ HEAD ~ a third element } processed to generate { TAIL ~ a functional computer executable representation } of a first field effect transistor and a second field effect transistor , wherein a gate of the first field effect transistor is tied to a gate of the second field effect transistor ; and
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH