{TAIL ~ The feedback stage} is operable in at least two feedback modes to hold the output bit state during the second clock state of {HEAD ~ the clock signal} 
{ TAIL ~ The feedback stage } is operable in at least two feedback modes to hold the output bit state during the second clock state of { HEAD ~ the clock signal }
TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD