The apparatus includes a buffer utilized for buffering an input signal and then outputting {TAIL ~ an output signal}; a digital to analog converter utilized for converting a digital value representative of {HEAD ~ phase delay} into a corresponding control voltage and outputting a control voltage; and a variable capacitor that has a capacitance value controlled by the control voltage 
The apparatus includes a buffer utilized for buffering an input signal and then outputting { TAIL ~ an output signal } ; a digital to analog converter utilized for converting a digital value representative of { HEAD ~ phase delay } into a corresponding control voltage and outputting a control voltage ; and a variable capacitor that has a capacitance value controlled by the control voltage
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH