{HEAD ~ a first DAC} for outputting a first control voltage corresponding to a first digital value representative of {TAIL ~ a phase delay}; and 
{ HEAD ~ a first DAC } for outputting a first control voltage corresponding to a first digital value representative of { TAIL ~ a phase delay } ; and
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH