A gate insulating layer, a gate electrode, and {HEAD ~ a spacer} may be formed over {TAIL ~ a second silicon layer} 
A gate insulating layer , a gate electrode , and { HEAD ~ a spacer } may be formed over { TAIL ~ a second silicon layer }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL