The invention provides {HEAD ~ a simple interface circuit} between a large capacity, high speed DRAM and {TAIL ~ a single port SRAM cache} to achieve fast cycle memory performance 
The invention provides { HEAD ~ a simple interface circuit } between a large capacity , high speed DRAM and { TAIL ~ a single port SRAM cache } to achieve fast cycle memory performance
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH