{TAIL ~ The memory management unit} is operable to determine configuration of {HEAD ~ at least some} of the plurality of memory modules to form a memory block, identify an interface MMW transceiver to provide a wireless link to the memory block, and generate a configuration signal based on the determined configuration and the identified interface MMW transceiver 
{ TAIL ~ The memory management unit } is operable to determine configuration of { HEAD ~ at least some } of the plurality of memory modules to form a memory block , identify an interface MMW transceiver to provide a wireless link to the memory block , and generate a configuration signal based on the determined configuration and the identified interface MMW transceiver
TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH