Floating point processor architecture which performs {HEAD ~ subtraction} with reduced number of {TAIL ~ guard} bits 
Floating point processor architecture which performs { HEAD ~ subtraction } with reduced number of { TAIL ~ guard } bits
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH