A predetermined voltage generated by the second FET is applied to the gate of {HEAD ~ the first FET} to set {TAIL ~ the bias point} of the first FET such that the first FET comprises characteristics of an integrated precision resistor 
A predetermined voltage generated by the second FET is applied to the gate of { HEAD ~ the first FET } to set { TAIL ~ the bias point } of the first FET such that the first FET comprises characteristics of an integrated precision resistor
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH