When a high logic level is asserted in device A, {HEAD ~ the portion} of the circuit in device B causes {TAIL ~ a high logic level} to be asserted in device B also at the converted level 
When a high logic level is asserted in device A , { HEAD ~ the portion } of the circuit in device B causes { TAIL ~ a high logic level } to be asserted in device B also at the converted level
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH