{HEAD ~ The second gate} is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is {TAIL ~ ON}, a surface channel and a buried channel are formed 
{ HEAD ~ The second gate } is electrically connected to the first gate , and the second source is electrically connected to the first source , such that when the DMOS device is { TAIL ~ ON } , a surface channel and a buried channel are formed
HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH