In order to reduce a period comparison error, {HEAD ~ synchronization circuitry} operates to synchronize {TAIL ~ the N divider} of the PLL and an M divider of the coarse tuning circuit 
In order to reduce a period comparison error , { HEAD ~ synchronization circuitry } operates to synchronize { TAIL ~ the N divider } of the PLL and an M divider of the coarse tuning circuit
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH