With reference now to FIG 8, a diagram depicts a memory subsystem connected to {HEAD ~ the address switch} of {TAIL ~ the distributed system} of the present invention 
With reference now to FIG 8 , a diagram depicts a memory subsystem connected to { HEAD ~ the address switch } of { TAIL ~ the distributed system } of the present invention
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH