At a given circuit board position predetermined logic levels are applied to the input mode pins to selectively set internal gating so as to interconnect {HEAD ~ a desired circuit block} to {TAIL ~ the interface pins} of the gate array 
At a given circuit board position predetermined logic levels are applied to the input mode pins to selectively set internal gating so as to interconnect { HEAD ~ a desired circuit block } to { TAIL ~ the interface pins } of the gate array
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH