a logical address register responsive to {HEAD ~ a logical address} from {TAIL ~ its respective fetch unit} for holding said logical address, the latter comprising a page or segment name plus a displacement, 
a logical address register responsive to { HEAD ~ a logical address } from { TAIL ~ its respective fetch unit } for holding said logical address , the latter comprising a page or segment name plus a displacement ,
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH