{HEAD ~ The semiconductor memory device} 6, further comprising {TAIL ~ an adjustment transistor} coupled in parallel with the pull down transistor, wherein the adjustment transistor is configured to be controllable by at least one bit of the stack position identifier 
{ HEAD ~ The semiconductor memory device } 6 , further comprising { TAIL ~ an adjustment transistor } coupled in parallel with the pull down transistor , wherein the adjustment transistor is configured to be controllable by at least one bit of the stack position identifier
HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH