The memory controller further comprises a first multiplexer receiving the output signal of the first FF and the write command load signal and controlled by a first control signal and {HEAD ~ a second programmable delay} receiving {TAIL ~ the first set} of one or more bits from the configuration register and the output signal of the first multiplexer 
The memory controller further comprises a first multiplexer receiving the output signal of the first FF and the write command load signal and controlled by a first control signal and { HEAD ~ a second programmable delay } receiving { TAIL ~ the first set } of one or more bits from the configuration register and the output signal of the first multiplexer
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH