Accordingly, each count register 702 a 702 d accepts and stores the output of the counter 201 at every fourth transition of the sample clock 103 in a deceleration by four embodiment and every Mth transition of the sample clock 103 in {HEAD ~ a deceleration} by {TAIL ~ M embodiment} 
Accordingly , each count register 702 a 702 d accepts and stores the output of the counter 201 at every fourth transition of the sample clock 103 in a deceleration by four embodiment and every Mth transition of the sample clock 103 in { HEAD ~ a deceleration } by { TAIL ~ M embodiment }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL