said system bus for enabling {HEAD ~ communication} between said processor means, said cache means, said {TAIL ~ interface} means and said main memory means 
said system bus for enabling { HEAD ~ communication } between said processor means , said cache means , said { TAIL ~ interface } means and said main memory means
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH