In one aspect, the invention includes DRAM circuitry having an array of word lines forming gates of field effect transistors and {HEAD ~ an array} of {TAIL ~ bit lines} 
In one aspect , the invention includes DRAM circuitry having an array of word lines forming gates of field effect transistors and { HEAD ~ an array } of { TAIL ~ bit lines }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL