Then, {HEAD ~ the ECC control circuit} 12 thereafter receives {TAIL ~ the data} having been corrected from the data memory circuit 14 through the SCSI controller circuit 13 and sends the corrected data in question to the upper circuit 10  
Then , { HEAD ~ the ECC control circuit } 12 thereafter receives { TAIL ~ the data } having been corrected from the data memory circuit 14 through the SCSI controller circuit 13 and sends the corrected data in question to the upper circuit 10
OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH