The device 1, wherein outputs of each converter are evenly divided into two groups, {HEAD ~ half} being connected to {TAIL ~ said two multiplexers} and half being connected to said first storage register 
The device 1 , wherein outputs of each converter are evenly divided into two groups , { HEAD ~ half } being connected to { TAIL ~ said two multiplexers } and half being connected to said first storage register
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH