{HEAD ~ A memory controller} for {TAIL ~ a double data rate} synchronous dynamic random access memory , the memory controller comprising: 
{ HEAD ~ A memory controller } for { TAIL ~ a double data rate } synchronous dynamic random access memory , the memory controller comprising :
HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH