Referring to FIG 1C, {HEAD ~ the exposed semiconductor substrate} 10 is isotropically etched using {TAIL ~ the hard mask pattern} 12 and the spacer 13 as etch barriers so that sidewalls of the preliminary lower pillar 11B are recessed to a predetermined width 
Referring to FIG 1C , { HEAD ~ the exposed semiconductor substrate } 10 is isotropically etched using { TAIL ~ the hard mask pattern } 12 and the spacer 13 as etch barriers so that sidewalls of the preliminary lower pillar 11B are recessed to a predetermined width
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH REL REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH