a fixed 32 bit shift unit configured to effect a fixed bit shift on an output of the second adder, wherein the fixed 32 bit shift unit implements {HEAD ~ only a single hardware} implemented {TAIL ~ MD5 shift value} 
a fixed 32 bit shift unit configured to effect a fixed bit shift on an output of the second adder , wherein the fixed 32 bit shift unit implements { HEAD ~ only a single hardware } implemented { TAIL ~ MD5 shift value }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL