{HEAD ~ The device} 1, wherein outputs of each converter are evenly divided into two groups, {TAIL ~ half} being connected to said two multiplexers and half being connected to said first storage register 
{ HEAD ~ The device } 1 , wherein outputs of each converter are evenly divided into two groups , { TAIL ~ half } being connected to said two multiplexers and half being connected to said first storage register
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH