In one embodiment of the invention, the output circuit is responsive to assertion of {HEAD ~ a control signal} to selectively enter {TAIL ~ a high impedance state} 
In one embodiment of the invention , the output circuit is responsive to assertion of { HEAD ~ a control signal } to selectively enter { TAIL ~ a high impedance state }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL