Since {HEAD ~ the output signal} from comparator 56 is at a low logic level, the output signal from NAND gate 128 is at {TAIL ~ a high logic level}, and maintains the output signal from NOR gate 130 at a high logic level 
Since { HEAD ~ the output signal } from comparator 56 is at a low logic level , the output signal from NAND gate 128 is at { TAIL ~ a high logic level } , and maintains the output signal from NOR gate 130 at a high logic level
OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH