The switch block circuit 8, wherein {TAIL ~ the common control determination signal} is provided from {HEAD ~ a program memory} 
The switch block circuit 8 , wherein { TAIL ~ the common control determination signal } is provided from { HEAD ~ a program memory }
OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD