{HEAD ~ The read write circuit} 1, wherein third and fourth high resistance p transistors are connected between the supply voltage and the gates of the third and fourth n transistors, {TAIL ~ the outputs} of the first and second inverters being connected to the gates of the third and fourth p transistors 
{ HEAD ~ The read write circuit } 1 , wherein third and fourth high resistance p transistors are connected between the supply voltage and the gates of the third and fourth n transistors , { TAIL ~ the outputs } of the first and second inverters being connected to the gates of the third and fourth p transistors
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