The first programmable delay receives a first set of {HEAD ~ one or more bits} from {TAIL ~ the configuration register} and a double speed clock signal 
The first programmable delay receives a first set of { HEAD ~ one or more bits } from { TAIL ~ the configuration register } and a double speed clock signal
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH