{HEAD ~ address decoder} means responsive to one portion of said {TAIL ~ logical address} in said register for selecting and reading out to said TLB a set having mT compartments in said TLB, 
{ HEAD ~ address decoder } means responsive to one portion of said { TAIL ~ logical address } in said register for selecting and reading out to said TLB a set having mT compartments in said TLB ,
HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH