In {HEAD ~ one aspect}, the invention includes DRAM circuitry having an array of word lines forming {TAIL ~ gates} of field effect transistors and an array of bit lines 
In { HEAD ~ one aspect } , the invention includes DRAM circuitry having an array of word lines forming { TAIL ~ gates } of field effect transistors and an array of bit lines
OTH HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH