The multiple read/write {HEAD ~ pipelines} share {TAIL ~ a read circuit} and a write circuit to reduce the circuit area of each pipeline and the circuit area of the memory as a whole 
The multiple read / write { HEAD ~ pipelines } share { TAIL ~ a read circuit } and a write circuit to reduce the circuit area of each pipeline and the circuit area of the memory as a whole
OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH