{HEAD ~ The apparatus} 14 wherein {TAIL ~ the clocking circuit} includes a plurality of levels of clock buffer circuitry, and wherein a first level of the plurality of levels includes one or more logic gates which combine the clock input and the control signal input 
{ HEAD ~ The apparatus } 14 wherein { TAIL ~ the clocking circuit } includes a plurality of levels of clock buffer circuitry , and wherein a first level of the plurality of levels includes one or more logic gates which combine the clock input and the control signal input
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