However, when {HEAD ~ the first clock signal} remains inactive, i.e., in {TAIL ~ a predetermined state}, for a predetermined time period, the active signal is clocked by the second clock signal through the first and second storage elements to an output terminal of the second storage element 
However , when { HEAD ~ the first clock signal } remains inactive , i.e. , in { TAIL ~ a predetermined state } , for a predetermined time period , the active signal is clocked by the second clock signal through the first and second storage elements to an output terminal of the second storage element
OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL OTH OTH OTH REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH