Note that {HEAD ~ any} of {TAIL ~ the signals} described herein can be designed as either negative or positive logic signals 
Note that { HEAD ~ any } of { TAIL ~ the signals } described herein can be designed as either negative or positive logic signals
OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH