{HEAD ~ The processor} assigns {TAIL ~ each instruction} a thread ID and error information as it follows the pipeline 
{ HEAD ~ The processor } assigns { TAIL ~ each instruction } a thread ID and error information as it follows the pipeline
HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH