Also, the negated data input line is connected in like manner through a second CMOS transfer gate to {HEAD ~ the input} of {TAIL ~ a second NOT circuit} and through an n transistor with crossover to the gate of a low resistance n transistor in the read circuit which is associated with the true data line 
Also , the negated data input line is connected in like manner through a second CMOS transfer gate to { HEAD ~ the input } of { TAIL ~ a second NOT circuit } and through an n transistor with crossover to the gate of a low resistance n transistor in the read circuit which is associated with the true data line
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH