Therefore, the P channel MOS transistor P1 in {HEAD ~ each} of {TAIL ~ all the driver/decoder units} 12 1, 12 2, . . . 12 n enters the off state, and the N channel MOS transistor N1 enters the on state 
Therefore , the P channel MOS transistor P1 in { HEAD ~ each } of { TAIL ~ all the driver / decoder units } 12 1 , 12 2 , . . . 12 n enters the off state , and the N channel MOS transistor N1 enters the on state
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH