In a data processing system memory address control apparatus connected to {TAIL ~ a main memory unit} and {HEAD ~ a processing unit} including an instruction fetch unit, an operand fetch unit, and an execution unit, said control apparatus comprising: 
In a data processing system memory address control apparatus connected to { TAIL ~ a main memory unit } and { HEAD ~ a processing unit } including an instruction fetch unit , an operand fetch unit , and an execution unit , said control apparatus comprising :
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH