At least one mode select interface pin is provided, in conjunction with gating circuitry that is interposed between the first and second circuit blocks and the interface pins for selectively coupling, in {TAIL ~ accordance} with a logic level applied to {HEAD ~ the at least one mode select interface pin}, only one of the circuit blocks to the interface pins 
At least one mode select interface pin is provided , in conjunction with gating circuitry that is interposed between the first and second circuit blocks and the interface pins for selectively coupling , in { TAIL ~ accordance } with a logic level applied to { HEAD ~ the at least one mode select interface pin } , only one of the circuit blocks to the interface pins
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH