{HEAD ~ The microprocessor} 18 handles the interface to the controller 20, the channel interface 16 and {TAIL ~ the RAM} 12, as well as determining when to read/write the video in the RAM to/from the disk drive 14 
{ HEAD ~ The microprocessor } 18 handles the interface to the controller 20 , the channel interface 16 and { TAIL ~ the RAM } 12 , as well as determining when to read / write the video in the RAM to / from the disk drive 14
HEAD HEAD HEAD HEAD HEAD HEAD OTH REL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH