Operation of the semiconductor device having {HEAD ~ the above described configuration} according to {TAIL ~ the exemplary embodiment} will be described in detail with reference to FIGS 4 to 8 
Operation of the semiconductor device having { HEAD ~ the above described configuration } according to { TAIL ~ the exemplary embodiment } will be described in detail with reference to FIGS 4 to 8
OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH