a fixed 32 bit shift unit configured to effect a fixed bit shift on {HEAD ~ an output} of {TAIL ~ the second adder}, wherein the fixed 32 bit shift unit implements only a single hardware implemented MD5 shift value 
a fixed 32 bit shift unit configured to effect a fixed bit shift on { HEAD ~ an output } of { TAIL ~ the second adder } , wherein the fixed 32 bit shift unit implements only a single hardware implemented MD5 shift value
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH