The method 1, wherein obtaining the pipeline semiconductor layout of the single redundant state machine comprises synthesizing a netlist logically describing the single redundant state machine to generate {HEAD ~ the pipeline semiconductor layout} of {TAIL ~ the single redundant state machine} 
The method 1 , wherein obtaining the pipeline semiconductor layout of the single redundant state machine comprises synthesizing a netlist logically describing the single redundant state machine to generate { HEAD ~ the pipeline semiconductor layout } of { TAIL ~ the single redundant state machine }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD HEAD REL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL TAIL