Additionally, the issue circuit is configured to generate a control signal responsive to whether or not {TAIL ~ the instruction} is issued to {HEAD ~ the execution circuit} 
Additionally , the issue circuit is configured to generate a control signal responsive to whether or not { TAIL ~ the instruction } is issued to { HEAD ~ the execution circuit }
OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH OTH HEAD HEAD HEAD HEAD HEAD HEAD HEAD