four 32 bit registers designated A, B, {HEAD ~ C} and D, wherein each register holds {TAIL ~ a value}; and 
four 32 bit registers designated A , B , { HEAD ~ C } and D , wherein each register holds { TAIL ~ a value } ; and
OTH OTH OTH OTH OTH OTH OTH OTH OTH HEAD HEAD HEAD HEAD HEAD OTH OTH OTH OTH OTH OTH OTH TAIL TAIL TAIL TAIL TAIL TAIL OTH OTH