Moore's law 2015 that the pace of advancement has slowed, starting at the 22 nm feature width around 2012, and continuing at 14 nm. Brian Krzanich, the former CEO of Intel, announced, "Our cadence today is closer to two and a half years than two." Intel is expected to reach the 10 nm node in 2018, a three-year cadence. Intel also stated in 2017 that hyperscaling would be able to continue the trend of Moore's law and offset the increased cadence by aggressively scaling beyond the typical doubling of transistors. Krzanich cited Moore's 1975 revision as a precedent for the current deceleration,
Intel 4040 subroutines and/or interrupts, plus a doubling of program ROM address range. Federico Faggin proposed the project, formulated the architecture and led the design. The detailed design was done by Tom Innes (Tinnes of Bristol). Philippines Intel 4040 The Intel 4040 microprocessor was the successor to the Intel 4004. It was introduced in 1974. The 4040 employed a 10 μm silicon gate enhancement load PMOS technology, was made up of 3,000 transistors and could execute approximately 62,000 instructions per second. General performance, bus layout and instruction set was identical to the 4004, with the main improvements being in the addition of