Bit-serial architecture a single N-bit parallel processor. Bit-serial architecture In digital logic applications, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel word architectures, in which data values are sent all bits or a word at once along a group of wires. All computers before 1951, and most of the early massive parallel processing machines used a bit-serial architecture—they were serial computers. Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation. Often N serial processors will take less FPGA area and have
Embarrassingly parallel are thus well suited to large, Internet-based distributed platforms such as BOINC, and do not suffer from parallel slowdown. The opposite of embarrassingly parallel problems are inherently serial problems, which cannot be parallelized at all. A common example of an embarrassingly parallel problem is 3D video rendering handled by a graphics processing unit, where each frame (forward method) or pixel (ray tracing method) can be handled with no interdependency. Password cracking is another embarrassingly parallel task that is easily distributed on central processing units, CPU cores, or clusters. "Embarrassingly" is used here in the same sense as in the phrase