DDR4 SDRAM computer buses have migrated towards replacing parallel buses with serial buses, for example by the evolution of Serial ATA replacing Parallel ATA, PCI Express replacing PCI, and serial ports replacing parallel ports. In general, serial buses are easier to scale up and have fewer wires/traces, making circuit boards using them easier to design. In the longer term, experts speculate that non-volatile RAM types like PCM (phase-change memory), RRAM (resistive random-access memory), or MRAM (magnetoresistive random-access memory) could replace DDR4 SDRAM and its successors. GDDR5 SGRAM is a graphics type of DDR3 synchronous graphics RAM, which was introduced before DDR4, and
NAS Parallel Benchmarks serial versions of the benchmarks consistent with the parallel versions and defined a problem size "Class W" for small-memory systems. NPB 2.4 of 2002 offered a new MPI implementation and introduced another still larger problem size "Class D". It also augmented one benchmark with I/O-intensive subtypes. NPB 3 retained the MPI implementation from NPB 2 and came in more flavors, namely OpenMP, Java and High Performance Fortran. These new parallel implementations were derived from the serial codes in NPB 2.3 with additional optimizations. NPB 3.1 and NPB 3.2 added three more benchmarks, which, however, were not available across all implementations;