Bit-serial architecture Bit-serial architecture In digital logic applications, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel word architectures, in which data values are sent all bits or a word at once along a group of wires. All computers before 1951, and most of the early massive parallel processing machines used a bit-serial architecture—they were serial computers. Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation. Often N serial processors will take less FPGA area and have a higher total performance than
Parallel algorithm wall, and thus multicore systems have become more widespread, making parallel algorithms of more general use. The cost or complexity of serial algorithms is estimated in terms of the space (memory) and time (processor cycles) that they take. Parallel algorithms need to optimize one more resource, the communication between different processors. There are two ways parallel processors communicate, shared memory or message passing. Shared memory processing needs additional locking for the data, imposes the overhead of additional processor and bus cycles, and also serializes some portion of the algorithm. Message passing processing uses channels and message boxes but this communication