Bit-serial architecture Bit-serial architecture In digital logic applications, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel word architectures, in which data values are sent all bits or a word at once along a group of wires. All computers before 1951, and most of the early massive parallel processing machines used a bit-serial architecture—they were serial computers. Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation. Often N serial processors will take less FPGA area and have a higher total performance than
Parallel and counter parallel major and tL in minor. If chords may be formed by raising (major) or lowering (minor) the fifth a whole step ["parallel" or relative chords], they may also be formed by lowering (major) or raising (minor) the root a half-step to "wechsel", the leading tone or "leitton". For example, Am is the tonic parallel of C, thus, Em is the counter parallel of C. The usual parallel chord in a major key is a minor third below the root and the counter parallel is a major third above. In a minor key the intervals are reversed: the tonic parallel (e.g.