Bit-serial architecture a single N-bit parallel processor. Bit-serial architecture In digital logic applications, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel word architectures, in which data values are sent all bits or a word at once along a group of wires. All computers before 1951, and most of the early massive parallel processing machines used a bit-serial architecture—they were serial computers. Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation. Often N serial processors will take less FPGA area and have
NAS Parallel Benchmarks serial versions of the benchmarks consistent with the parallel versions and defined a problem size "Class W" for small-memory systems. NPB 2.4 of 2002 offered a new MPI implementation and introduced another still larger problem size "Class D". It also augmented one benchmark with I/O-intensive subtypes. NPB 3 retained the MPI implementation from NPB 2 and came in more flavors, namely OpenMP, Java and High Performance Fortran. These new parallel implementations were derived from the serial codes in NPB 2.3 with additional optimizations. NPB 3.1 and NPB 3.2 added three more benchmarks, which, however, were not available across all implementations;