CompactPCI Serial parallel CompactPCI comprises another specification called PICMG 2.30 CompactPCI PlusIO. This is why CompactPCI Serial and CompactPCI PlusIO as a whole were also called CompactPCI Plus. PICMG's first working title of CompactPCI Serial was CPLUS.0. (See also #Compatibility and Migration.) CompactPCI Serial backplanes and chassis are developed by Schroff, Elmа, and Pixus Technologies companies, as for the CompactPCI Serial board level electronics – they are developed by MEN Mikro Elektronik, Fastwel, EKF, Emerson Embedded Computing, ADLINK, and Kontron. Fast serial point-to-point connections have become the state-of-the-art technology and are gradually replacing the classic bus architecture in computers. The CompactPCI standard
Parallel algorithm wall, and thus multicore systems have become more widespread, making parallel algorithms of more general use. The cost or complexity of serial algorithms is estimated in terms of the space (memory) and time (processor cycles) that they take. Parallel algorithms need to optimize one more resource, the communication between different processors. There are two ways parallel processors communicate, shared memory or message passing. Shared memory processing needs additional locking for the data, imposes the overhead of additional processor and bus cycles, and also serializes some portion of the algorithm. Message passing processing uses channels and message boxes but this communication