Computation of cyclic redundancy checks may use whichever form is more convenient. Parallel update for a byte or a word at a time can also be done explicitly, without a table. This is normally used in high-speed hardware implementations. For each bit an equation is solved after 8 bits have been shifted in. The following tables list the equations for some commonly used polynomials, using following symbols: As the CRC-32 polynomial has a large number of terms, when computing the remainder a byte at a time each bit depends on several bits of the previous iteration. In byte-parallel hardware implementations this calls for either multiple-input
64-bit computing in 64 bits depends on the integer representation used. With the two most common representations, the range is 0 through 18,446,744,073,709,551,615 (2 − 1) for representation as an (unsigned) binary number, and −9,223,372,036,854,775,808 (−2) through 9,223,372,036,854,775,807 (2 − 1) for representation as two's complement. Hence, a processor with 64-bit memory addresses can directly access 2 bytes (=16 exabytes) of byte-addressable memory. With no further qualification, a "64-bit computer architecture" generally has integer and addressing processor registers that are 64 bits wide, allowing direct support for 64-bit data types and addresses. However, a CPU might have external data buses or address