Hexagon around each vertex. A regular hexagon can also be created as a truncated equilateral triangle, with Schläfli symbol t{3}. Seen with two types (colors) of edges, this form only has D symmetry. A truncated hexagon, t{6}, is a dodecagon, {12}, alternating 2 types (colors) of edges. An alternated hexagon, h{6}, is a equilateral triangle, {3}. A regular hexagon can be stellated with equilateral triangles on its edges, creating a hexagram. A regular hexagon can be dissected into 6 equilateral triangles by adding a center point. This pattern repeats within the regular triangular tiling. A regular hexagon can be extended into
Qualcomm Hexagon 20 DMIPS per milliwatt, operating at 500 MHz. Clock speed of Hexagon varies in 400–2000 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5. Both Hexagon (QDSP6) and pre-Hexagon (QDSP5) cores are used in modern Qualcomm SoCs, QDSP5 mostly in low-end products. Modem QDSPs (often pre-Hexagon) are not shown in the table. QDSP5 usage: QDSP6 (Hexagon) usage: This is a single instruction packet from the inner loop of a FFT: This packet is claimed by Qualcomm to be equal to 29 classic RISC operations; it includes vector add (4x 16-bit), complex multiply operation and