Hexagon them. Coxeter states that every zonogon (a 2"m"-gon whose opposite sides are parallel and of equal length) can be dissected into "m"("m"-1)/2 parallelograms. In particular this is true for regular polygons with evenly many sides, in which case the parallelograms are all rhombi. This decomposition of a regular hexagon is based on a Petrie polygon projection of a cube, with 3 of 6 square faces. Other parallelogons and projective directions of the cube are dissected within rectangular cuboids. A regular hexagon has Schläfli symbol {6}. A regular hexagon is a part of the regular hexagonal tiling, {6,3}, with 3 hexagonal
Qualcomm Hexagon 20 DMIPS per milliwatt, operating at 500 MHz. Clock speed of Hexagon varies in 400–2000 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5. Both Hexagon (QDSP6) and pre-Hexagon (QDSP5) cores are used in modern Qualcomm SoCs, QDSP5 mostly in low-end products. Modem QDSPs (often pre-Hexagon) are not shown in the table. QDSP5 usage: QDSP6 (Hexagon) usage: This is a single instruction packet from the inner loop of a FFT: This packet is claimed by Qualcomm to be equal to 29 classic RISC operations; it includes vector add (4x 16-bit), complex multiply operation and