Parameters and variables From the [O] model, we recall that a tile represents the minimal area unit considered within the FPGA grid and we denote by tileW and tileH its width and height respectively.
following one of the few approaches existing in literature, we use a Node-Arc model (better described in Section II) similar to the one used in [17] where each node is a Reconfigurable Region (RR), thus allowing high level analysis.