The terms RISC and CISC have become less meaningful with the continued improvements of both CISC and RISC designs and implementations. The first highly pipelined "CISC" implementations, such as Intel 80486 series, supports every instruction that their predecessors did, but achieved "high efficiency" only on a few simple x86 subset (similar to a RISC instruction set, but without the "load-store" limitations of RISC). Modern x86 processors also decode and split more complex instructions into a series of smaller internal "Micro-operations" which can thereby be executed in a pipelined (parallel) fashion, thus achieving high performance on a much larger subset of instructions.