title: Assign a single bit from STD_LOGIC_VECTOR to STD_LOGIC
body: <p>It seems like I have done this plenty of times, but for some reason today it just doesn't want to work.</p>
  
  <p>I would like to assign the MSB of a 16-bit vector to a single-bit variable.</p>
  
  <pre><code>Din : in  STD_LOGIC_VECTOR (15 downto 0);
  
  ...
  
  signal signBit : std_logic;
  
  begin
      signBit &lt;= Din(15 downto 15);
  </code></pre>
  
  <p>The error given is:</p>
  
  <pre><code>Type of signBit is incompatible with type of Din.
  </code></pre>
  
  <p>Yes I get it, vectors don't play nice with std_logic, but this is 1-bit, clearly denoted by (15 downto 15)</p>