title: In synthesizable verilog, can we use assign statement in generate block?
body: <p>For example, I have the below piece of code. Can we assign wire inside the generate block in synthesizable verilog? Can we use assign statement inside the generate block in synthesizable verilog? </p>
  
  <pre><code>genvar i;
  generate
          for (i = 0; i &lt; W; i=i+1) begin:m
                  wire [2:0] L;
                  assign L[1:0] = { a[i], b[i] };
          end
  endgenerate
  </code></pre>