title: Write a Verilog code that only has an output when enabled
body: <p>I am creating a register file that has 4 empty 4 bit registers, and with each clock cycle, a register gets a value pushed onto it, and then this value is displayed using a 7 segment decoder. If the register is empty, there should not be a display, but once a value is loaded to the register, then there should be a display. I tried writing the verilog code for the 7 segment decoder where there should only be an output if En = 1. My problem is that instead of not displaying anything, the 7 segment decoder will display zero until a value is added to the register, in which case then the decoder will display the loaded value. Here is the verilog code.</p>
  
  <pre><code>module seven_seg_decoder(S, Z, Y, X, W,En);
  input Z,Y,X,W,En; 
  output [6:0] S;
  reg [6:0] S;
  
  always @(En)
      begin
          case({Z,Y,X,W,En})
              5'b00001: S = 'b0000001;
              5'b00011: S = 'b1001111;
              5'b00101: S = 'b0010010;
              5'b00111: S = 'b0000110;
              5'b01001: S = 'b1001100;
              5'b01011: S = 'b0100100;
              5'b01101: S = 'b0100000;
              5'b01111: S = 'b0001111;
              5'b10001: S = 'b0000000;
              5'b10011: S = 'b0000100;
              5'b10101: S = 'b0001000;
              5'b10111: S = 'b1100000;
              5'b11001: S = 'b0110001;
              5'b11011: S = 'b1000010;
              5'b11101: S = 'b0110000;
              5'b11111: S = 'b0111000;
  
          endcase
      end
  endmodule
  </code></pre>
  
  <p>When the register is loaded with a value, I have an output come from the register saying that it is loaded, and that is used as the input for the enable on this decoder</p>