title: Can't infer register for ... at ... because it does not hold its value outside the clock edge
body: <p>This must be the most common problem among people new to VHDL, but I don't see what I'm doing wrong here! This seems to conform to all of the idioms that I've seen on proper state machine design. I'm compiling in Altera Quartus 9.2, for what it's worth. The actual error is:</p>
  
  <p>"Can't infer register for "spiclk_out" at [file] [line] because it does not hold its value outside the clock edge"</p>
  
  <pre><code>ENTITY spi_state_machine IS
      PORT(
              spiclk_internal : IN STD_LOGIC;
              reset : IN STD_LOGIC;
              spiclk_out : BUFFER STD_LOGIC
      );
  END spi_state_machine;
  
  PROCESS(spiclk_internal, reset)
  BEGIN
      IF reset = '1' THEN
          spiclk_out &lt;= '0';
      END IF;
  
      IF spiclk_internal = '1' AND spiclk_internal'EVENT THEN --error here
          spiclk_out &lt;= NOT spiclk_out;
      END IF;
  END PROCESS;
  </code></pre>
  
  <p>Thanks for your time.</p>