title: Structural design for testing a gate system
body: <p>I'm working on experiment 3 in the book Fundamentals of Digital and Computer Design with VHDL. This is what it wants. <a href="https://i.stack.imgur.com/Cp1Cm.png" rel="nofollow"><img src="https://i.stack.imgur.com/Cp1Cm.png" alt="experiment3"></a></p>
  
  <p>I have Modules 1,2,and 3 all working individually. It's when I try to get them together in the top module that I start having issues. When I tried to simulate the program it failed, and I'm not sure how to fix.</p>
  
  <pre><code>--Module 1
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity Displetter is
      Port ( mux_in : in  STD_LOGIC;
             Cath : out  STD_LOGIC_VECTOR (7 downto 0);
             An : out  STD_LOGIC_VECTOR (3 downto 0));
  end Displetter;
  
  architecture Behavioral of Displetter is
  
  begin
    process(mux_in)
    begin
        if(mux_in = '0') then
                  Cath &lt;= "11000111"; --L pgfedcba 0s are what's lit up
        elsif (mux_in = '1') then
                  Cath &lt;= "10001001"; -- H pgfedcba
        end if;
    end process;
  
    An &lt;= "0111";
  end Behavioral;
  
  --Module 2
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  
  entity MUX8 is
      Port ( D : in  STD_LOGIC_VECTOR (7 downto 0);
             S : in  STD_LOGIC_VECTOR (2 downto 0);
             MUXOUT : out  STD_LOGIC);
  end MUX8;
  
  architecture Behavioral of MUX8 is
  
  begin
      MUXOUT &lt;= D(0) when (S="000") else
              D(1) when (S="001") else
              D(2) when (S="010") else
              D(3) when (S="011") else
              D(4) when (S="100") else
              D(5) when (S="101") else
              D(6) when (S="110") else
              D(7);
  
  end Behavioral;
  
  --Module 3
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity Displetter is
      Port ( mux_in : in  STD_LOGIC;
             Cath : out  STD_LOGIC_VECTOR (7 downto 0);
             An : out  STD_LOGIC_VECTOR (3 downto 0));
  end Displetter;
  
  architecture Behavioral of Displetter is
  
  begin
    process(mux_in)
    begin
        if(mux_in = '0') then
                  Cath &lt;= "11000111"; --L pgfedcba 0s are what's lit up
        elsif (mux_in = '1') then
                  Cath &lt;= "10001001"; -- H pgfedcba
        end if;
    end process;
  
    An &lt;= "0111";
  end Behavioral;
  
  
  --Top Module
  
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity TopMod is
      Port ( s6 : in  STD_LOGIC;
             s7 : in  STD_LOGIC;
             Cath : out  STD_LOGIC_VECTOR (7 downto 0);
             An : out  STD_LOGIC_VECTOR (3 downto 0);
             s0 : in  STD_LOGIC;
             s1 : in  STD_LOGIC;
             s2 : in  STD_LOGIC);
  end TopMod;
  
  architecture Behavioral of TopMod is
  
  COMPONENT Gates
    PORT(
        s6 : in  STD_LOGIC;
           s7 : in  STD_LOGIC;
           a0 : out  STD_LOGIC;
           a1 : out  STD_LOGIC;
           a2 : out  STD_LOGIC;
           a3 : out  STD_LOGIC;
           a4 : out  STD_LOGIC;
           a5 : out  STD_LOGIC;
           a6 : out  STD_LOGIC;
           a7 : out  STD_LOGIC
        );
    END COMPONENT;
  
  COMPONENT MUX8
    PORT(
      D : in  STD_LOGIC_VECTOR (7 downto 0);
        S : in  STD_LOGIC_VECTOR (2 downto 0);      
      MUXOUT : OUT std_logic
      );
    END COMPONENT;
  
  COMPONENT Displetter
    PORT(
      mux_in : in  STD_LOGIC;
        Cath : out  STD_LOGIC_VECTOR (7 downto 0);
        An : out  STD_LOGIC_VECTOR (3 downto 0))
    );
    END COMPONENT;
  
    signal mout;
  begin
    GATE : PORT MAP(
      s6 =&gt; s6;
      s7 =&gt; s7;
    );
    MUX : PORT MAP(
      D&lt;7&gt; =&gt; a7,
      D&lt;6&gt; =&gt; a6,
      D&lt;5&gt; =&gt; a5,
      D&lt;4&gt; =&gt; a4,
      D&lt;3&gt; =&gt; a3,
      D&lt;2&gt; =&gt; a2,
      D&lt;1&gt; =&gt; a1,
      D&lt;0&gt; =&gt; a0,
  
      s&lt;0&gt; =&gt; s0,
      s&lt;1&gt; =&gt; s1,
      s&lt;2&gt; =&gt; s2
      MUXOUT =&gt; mout
    );
  
    Disp : PORT MAP(
      Cath =&gt; Cath,
      An =&gt; An,
      mux_in =&gt; mout
    );
  
  end Behavioral;
  </code></pre>