title: VHDL what is more efficient to use : an integer with range or a std_logic_vector
body: <p>If i declare a signal integer range 0 to 6 , will it be better or worse opposing to declaring a std_logic_vector (2 downto 0) to do the exact same job.I am referring to design cost so that i can decide whether to use an integer with a small range or a one-hot representation with a vector.</p>
  
  <p><strong>To put it plainly how much space will be reserved for an integer range 0 to n ?</strong></p>