title: $size, $bits, verilog
body: <p>What is the difference between <code>$size</code> and <code>$bits</code> operator in verilog.?
  if I've variables, <code>[9:0]a</code>,<code>[6:0]b</code>,<code>[31:0]c</code>.</p>
  
  <pre><code>c &lt;= [($size(a)+$size(b)-1]-:$bits(b)];
  </code></pre>
  
  <p>What will be the output at 'c' from the above expression?</p>