title: Adding header files in Verilog
body: <p>I wanted to add a header file to my Verilog project. This should be a very easy thing to do. However, it turns out is is not trivial. This my header file. Let's say the file name is parameters.vh</p>
  
  <pre><code>`ifndef _parameters_vh_
  `define _parameters_vh_
  parameter Tm = 2;
  parameter Tn = 2;
  `endif
  </code></pre>
  
  <p>Then I include it to the top module</p>
  
  <pre><code>`include "parameters.vh"
  </code></pre>
  
  <p>But it cannot get synthesized. This is the error message:</p>
  
  <p>Verilog HDL error at parameters.vh(3): declaring global objects is a SystemVerilog feature.
  I am wondering if anyone can help me here.</p>