title: Verilog bit shift
body: <p>I'm just starting out on how to learn verilog and I stumbled upon this problem. So  I'm trying to make a bit shifter that shifts the input bit once to the left for each rising clock pulse. However, when I tried running the simulations, the output came out as XXXX. Any help will be apreciated</p>
  
  <pre><code>module shift_left #(parameter i=3)(
  input clk,
  input rst,
  input [i:0]data_in,
  output reg [i:0]data_out
  );
  wire [i:0]in;
  assign in=data_in;
  reg [i:0]temp;
  
  always @(posedge clk)begin
  
      if(rst==1)begin
          temp&lt;=in;
      end
      else
          data_out&lt;=temp;
          temp&lt;=temp&lt;&lt;1;
          temp[0]=1'b0;
      end
  
  endmodule
  </code></pre>