title: Can anyone explain the usage of "$sreadmemh" in SystemVerilog? I don't get clear explanation anywhere
body: <p>Pls Explain how this code work... </p>
  
  <pre><code>module top;
      //string mem [5];        
      real mem [5];            
      initial begin
          $sreadmemh(mem,2,3,"A","B");
          $display("mem = %p",mem);
      end 
  endmodule
  </code></pre>