title: How to sign-extend a number in Verilog
body: <p>I'm working on a simple sign-extender in Verilog for a processor I'm creating for Computer Architecture.</p>
  
  <p>Here's what I've got so far: [EDIT: Changed the selection statement slightly]</p>
  
  <pre><code>`timescale 1ns / 1ps
  
  module SignExtender( CLK, extend, extended );
  input[7:0] extend;
  input CLK;
  output[15:0] extended;
  
  reg[15:0] extended;
  wire[7:0] extend;
  
  always
  begin
      while (CLK == 1)
      extended[7:0] = extend[7:0];
      extended[15:8] = {8{extend[7]}};
  end
  endmodule
  </code></pre>
  
  <p>I added the while (CLK == 1) thinking that would solve my problem, which I believe is an infinite loop. When I try to test this in iSim, the circuit never initializes.</p>
  
  <p>I also tried removing the copying syntax and just doing extended[8] = extend[7] etc. for [8]-[15], but the same result occurs, so I'm pretty sure that the innermost syntax is correct.</p>
  
  <p>Here's the test file:</p>
  
  <pre><code>`timescale 1ns / 1ps
  module SignExtender_testbench0;
  
      // Inputs
      reg [7:0] extend;
      reg CLK;
  
      // Outputs
      wire [15:0] extended;
  
      // Instantiate the Unit Under Test (UUT)
      SignExtender uut (
          .extend(extend), 
          .extended(extended)
      );
  
      initial begin
          // Initialize Inputs
          extend = 0;
  
          #100; // Wait 100 ns for global reset to finish
  
          extend = -30;
          CLK = 1;
          #10;
          CLK = 0;
          if (extended == -30)
              $display("okay 1");
          else
              $display("fail 1");
  
          extend = 40;
          #10;
          if (extended == 40)
              $display("okay 2");
          else
              $display("fail 2");
  
      end
  
  endmodule
  </code></pre>
  
  <p>Any ideas how I can do this successfully?</p>