title: [VHDL]Using signal to drive output ports,why are the output ports not visible?
body: <p>in reference to this post <a href="https://stackoverflow.com/questions/12144019/how-to-write-to-two-output-ports-from-inside-architecture-in-vhdl">How to write to two output ports from inside architecture in VHDL?</a> I made a VHDL module using the same concept as decribed in one of its answers.
  His code:</p>
  <pre><code>entity HIER is
  port (
      IN1 : in bit;
      OUT1, OUT2 : out bit);
  end hier;
  
  architecture HIER_IMPL of HIER is 
     signal temp : bit;
     component BUF1 is 
        port (a : in bit; o : out bit);
     end component;
  begin
     BUF2 : BUF1 port map (a =&gt; IN1, o =&gt; temp);
     OUT1 &lt;= temp;
     OUT2 &lt;= temp;
  
  end HIER_IMPL;
  </code></pre>
  <p>His generated RTL(using xilinx 9.1i)
  <a href="https://i.stack.imgur.com/GpGVl.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/GpGVl.png" alt="enter image description here" /></a></p>
  <p>I made a D flip flop using the same concept of signal to drive output ports
  my code:</p>
  <pre><code>entity dfff is
      Port ( D : in  STD_LOGIC;
             clk : in  STD_LOGIC;
             Q : out  STD_LOGIC;
             Qbar : out  STD_LOGIC);
  end dfff;
  
  architecture Behavioral of dfff is
  component nand_2 is
  port(A:in std_logic;
          B:in std_logic;
          C:out std_logic);
  end component;
  component not_1 is
  port(A:in std_logic;
                  B:out std_logic);
                  end component;
  signal Z : std_logic_vector(4 downto 0);
  begin
  n1 : not_1 port map (D,z(0));
  n2 : nand_2 port map(D,clk,z(1));
  n3 : nand_2 port map(z(0),clk,z(2));
  n4 : nand_2 port map(z(1),z(3),z(4));
  n5 : nand_2 port map(z(2),z(4),z(3));
  Q&lt;=z(4);
  Qbar&lt;=z(3);
  end Behavioral;
  </code></pre>
  <p>my generated RTL(using xilinx 9.1i):
  <a href="https://i.stack.imgur.com/dFnlV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/dFnlV.png" alt="enter image description here" /></a></p>
  <p>Now MY question is that why My output ports Q and Qbar not visible in the RTL while his OUT1 and OUT2 are?
  I am a beginner in this field.</p>