title: Non resolved signal has multiple sources VHDL
body: <p>i am  implementing a simple FSM using VHDL .
  I came out with this code in VHDL and i got this error:'non resolved signal NS has multiple sources'.I looked deeply in the code but coudln't figure out the mistake
  Can anyone help me to solve this problem?</p>
  
  <pre><code>                     library ieee ;
                       use ieee.std_logic_1164.all ;
                       entity MeallyMachine is
                       port( 
                       x,res,clk:in std_logic;
                       z1,z2:out std_logic       
                       );
  
                      end MooreMachine;
  
  
                      architecture M1 of MooreMachine is
                      type state_type is(s0,s1,s2,s3);
                      signal PS,NS:state_type;
  
                       begin
                       ETAT:process(PS,x)
                       begin
                       case PS is
                        when  s0=&gt;  if (x='0') then
                        NS&lt;=s0;
                                   elsif (x='1') then
                                   NS&lt;=s1;
                                   end if;
                       when s1=&gt;  if (x='0') then
                        NS&lt;=s1;
                                  elsif (x='1') then
                        NS&lt;=s2;
                                  end if;  
                       when s2=&gt;  if (x='0') then
                       NS&lt;=s2;
                                  elsif (x='1') then
                       NS&lt;=s3;
                                   end if;
                       when s3=&gt;  if (x='0') then
                       NS&lt;=s3;
                                   elsif (x='1') then
                       NS&lt;=s0;
                                   end if;
                       end case;
                     end process ETAT;
                  Sortie:process(PS,x)
                    begin
                     case PS is
                        when s0=&gt;  
                              z1&lt;='1';
                          if (x='0') then
                              z2&lt;='0';
                           elsif (x='1') then
                              z2&lt;='1';
                            end if;
                        when s1=&gt;   
                              z1&lt;='1';
                         if (x='0') then
                              z2&lt;='0';
                         elsif (x='1') then
                          z2&lt;='1';
                         end if;  
                       when s2=&gt;  z1&lt;='0';
                        if (x='0') then
                          z2&lt;='0';
                        elsif (x='1') then
                          z2&lt;='1';
                        end if;
                     when s3=&gt;   z1&lt;='1';
                          if (x='0') then
                           z2&lt;='0';
                          elsif (x='1') then
                           z2&lt;='1';
                          end if;
                     end case;
                  end process Sortie;
             Horloge:process(clk,res,NS)
                  begin
                   if (res='0') then
                        NS&lt;=s0;
                   elsif (rising_edge(clk)) then 
                        PS&lt;=NS;
                   end if;
                   end process Horloge;
  
  
  
  
           end M1;
  </code></pre>