title: Why this Modelsim error? "Ambiguous types in signal assignment statement."
body: <p>I am trying to compile the following example with ModelSim Microsemi 10.2c:</p>
  
  <pre><code>architecture example of assignment_to_an_aggregate is
      type vowel_type is (a, e, i, o, u);
      type consonant_type is (b, c, d, f, g);
  
      signal my_vowel: vowel_type;
      signal my_consonant: consonant_type;
  begin
  
      (my_vowel, my_consonant) &lt;= (a, b);
  
  end;
  </code></pre>
  
  <p>And it gives the following error:</p>
  
  <pre><code>** Error: assignment_to_aggregates.vhdl(40): (vcom-1349) Ambiguous types in signal assignment statement.
  
     Possible target types are:
          std.STANDARD.TIME_VECTOR
          std.STANDARD.REAL_VECTOR
          std.STANDARD.INTEGER_VECTOR
          std.STANDARD.BIT_VECTOR
          std.STANDARD.BOOLEAN_VECTOR
          std.STANDARD.STRING
  
  ** Error: assignment_to_aggregates.vhdl(57): VHDL Compiler exiting
  </code></pre>
  
  <p>Anyone could explain whit this doesn't work? And why would the compiler think that TIME_VECTOR, STRING, etc. are reasonable types for the target of this assignment? Note: I get the same error even when the target aggregate has only signals of a same type.</p>
  
  <p>Thanks!</p>