title: VHDL assigning bit inputs to bit vector
body: <p>In my homework, I have to put in a truth table and get a schematic from it. My code is below:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity C0 is
      Port (  a1 : in STD_LOGIC;
              a0 : in STD_LOGIC;
              b1 : in STD_LOGIC;
              b0 : in STD_LOGIC;
              input : in STD_LOGIC_VECTOR(0 to 1);
              OutC0 : out STD_LOGIC);
  end C0;
  
  architecture Behavioral of C0 is
  begin
  
  process (input)
  begin
      case input is
  
         when "0000" =&gt; OutC0 &lt;= '0';
         when "0001" =&gt; OutC0 &lt;= '1';
         when "0010" =&gt; OutC0 &lt;= '0';
         when "0011" =&gt; OutC0 &lt;= '1';
         when "0100" =&gt; OutC0 &lt;= '1';
         when "0101" =&gt; OutC0 &lt;= '0';
         when "0110" =&gt; OutC0 &lt;= '1';
         when "0111" =&gt; OutC0 &lt;= '0';
         when "1000" =&gt; OutC0 &lt;= '0';
         when "1001" =&gt; OutC0 &lt;= '1';
         when "1010" =&gt; OutC0 &lt;= '0';
         when "1011" =&gt; OutC0 &lt;= '1';
         when "1100" =&gt; OutC0 &lt;= '1';
         when "1101" =&gt; OutC0 &lt;= '0';
         when "1110" =&gt; OutC0 &lt;= '1';
         when "1111" =&gt; OutC0 &lt;= '0';
  
      end case ; 
  end process;
  
  end Behavioral;
  </code></pre>
  
  <p>The problem is that when I get the schematic, there is only one input. Four inputs, <code>a1</code>, <code>a0</code>, <code>b1</code>, and <code>b0</code>, should be visible. Somehow, I have to put <code>a1</code>, <code>a0</code>, <code>b1</code>, and <code>b0</code> into the vector input. If you recommend another way it would be great too, but not too complicated please. Thanks in advance.</p>