title: I wrote a verilog code but got errors like not a constant or unknown type
body: <p>How can I remove the errors mentioned in the title? </p>
  
  <pre><code>  reg [3:0]count;
    reg [6:0]seg;
  
    always @ (posedge clock) begin
      if (reset)
        count = 0;
      else
        count = count+1'b0;   //starting A counter
    end
  
    begin // this seems to need an "always @*" just before "begin"
      case(count)
        4'b0000: seg = 7'b0000001;
      endcase
    end
  
    assign {a,b,c,d,e,f,g} = seg;
  
  endmodule  // where is "module"?
  </code></pre>
  
  <p>It shows error 44 i.e. count is not a constant
   Error 1059 i.e. seg is of unknown type. Please help. 
  can't figure out what to do next</p>