title: JK flipflop code in verilog using structural
body: <p>i am writing an verilog program for jk flipflop in structural level
  my program is as follows:</p>
  
  <pre><code>module jkstruct(j,k,clk,q,qbar);
  
  input j,k,clk;
  
  output reg q,qbar;
  
  initial begin q=1'b1;qbar=1'b0; end
  
  wire x,y,w,z;
  
  assign w=q;
  
  assign z=qbar;
  
  nand n1(x,z,j,clk);
  
  nand n2(y,k,w,clk);
  
  nand n3(q,x,z);
  
  nand n4(qbar,y,w);
  
  endmodule
  </code></pre>
  
  <blockquote>
    <p>ERROOR:Simulator:754 - Signal EXCEPTION_ACCESS_VIOLATION
    receivedPrinting stacktrace...</p>
  </blockquote>
  
  <p>was appearing on simulator error panel.
  I am using xilinx 13.4 licensed version.</p>