title: What does #1 mean in verilog?
body: <p>I understand that <code>always @(posedge clk)</code> in verilog is a flip flop. </p>
  
  <pre><code>input ld;
  reg ld_r;
  always @(posedge clk) ld_r &lt;= #1 ld;
  </code></pre>
  
  <p>What does <code>#1</code> do in above code? I found it in verilog code for AES. I include a snippet of it below:</p>
  
  <pre><code>always @(posedge clk)
  if(!rst)    dcnt &lt;= #1 4'h0;
  else
  if(ld)      dcnt &lt;= #1 4'hb;
  else
  if(|dcnt)   dcnt &lt;= #1 dcnt - 4'h1;
  
  always @(posedge clk) done &lt;= #1 !(|dcnt[3:1]) &amp; dcnt[0] &amp; !ld;
  always @(posedge clk) if(ld) text_in_r &lt;= #1 text_in;
  always @(posedge clk) ld_r &lt;= #1 ld;
  </code></pre>