title: Variable treated unexpectedly in Makefile
body: <p>I have <code>Makefile</code> below that treats <code>$(CC)</code> varaible as <code>cc</code>. Variable <code>$(BB)</code> is treated <code>gcc</code> as expected. Why <code>$(CC)</code> is treated as <code>cc</code> and not <code>gcc</code>?</p>
  <pre><code>#
  # Makefile
  
  BB ?= gcc
  CC ?= gcc
  LVGL_DIR ?= ${shell pwd}
  CFLAGS ?= -Wall -Wshadow -Wundef -Wmaybe-uninitialized -O3 -g0 -I$(LVGL_DIR)/
  # LDFLAGS ?= -lSDL2 -lm
  LDFLAGS ?= -lm
  BUILDDIR := build
  BINDIR := bin
  BIN = $(BINDIR)/output
  
  
  #Collect the files to compile
  MAINSRC = ./main.c
  
  include $(LVGL_DIR)/lvgl/lvgl.mk
  include $(LVGL_DIR)/lv_drivers/lv_drivers.mk
  
  #include 
  INC := -I . -I lvgl -I lv_drivers
  
  #CSRCS +=$(LVGL_DIR)/mouse_cursor_icon.c
  
  OBJEXT ?= .o
  
  AOBJS = $(ASRCS:.S=$(OBJEXT))
  COBJS = $(CSRCS:.c=$(OBJEXT))
  # AOBJS = $(patsubst %,%,$(ASRCS:.S=$(OBJEXT)))
  
  #reference
  # SOURCES := $(shell find . -type f -iname &quot;*.$(SRCEXT)&quot; )
  # OBJECTS := $(patsubst %,%,$(SOURCES:.$(SRCEXT)=.o))
  
  MAINOBJ = $(MAINSRC:.c=$(OBJEXT))
  
  SRCS = $(ASRCS) $(CSRCS) $(MAINSRC)
  OBJS = $(AOBJS) $(COBJS)
  
  ## MAINOBJ -&gt; OBJFILES
  
  all: default
  %.o: %.c
      @echo &quot;TEST $(CC) $(BB) $&lt;&quot;
      $(CC) $(CFLAGS) $(INC) -c $&lt; -o $@
      
      
  default: $(AOBJS) $(COBJS) $(MAINOBJ)
      @mkdir -p $(BINDIR)
      $(CC) -o $(BIN) $(MAINOBJ) $(AOBJS) $(COBJS) $(LDFLAGS)
  
  clean: 
      rm -f $(BIN) $(AOBJS) $(COBJS) $(MAINOBJ)
  </code></pre>
  <p>UPD</p>
  <p>If I comment <code>#CC ?= gcc</code> then it is still treated as <code>cc</code>.  In case I run command <code>echo $CC </code> nothing is printed. So who sets <code>CC</code> to <code>cc</code> ?</p>