title: Verilog D Flip Flop
body: <p>I'm attempting to write a specific version of the D Flip Flop that uses NOR gates only:</p>
  
  <p>Following is gate level diagram:</p>
  
  <p><a href="https://i.stack.imgur.com/3mx5a.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/3mx5a.png" alt="NOR Gate D Flip Flop"></a></p>
  
  <p>The code I'm using in Verilog:</p>
  
  <pre><code>module DFlipFlop(D,CLK,Q,QN);
      input D, CLK;
      output Q, QN;
      reg Q, QN, R, S;
  
  always @(negedge CLK) begin
      R = ~(~(~(D|S)|R)|CLK);
      S = ~(~(D|S)|R|CLK); 
      Q = ~(R|QN);
      QN = ~(S|Q);
  end
  
  endmodule
  </code></pre>
  
  <p>I then uploaded the compiled program to a PLD and it's not flip flopping and I cannot figure out why. I've tried many different things already.</p>
  
  <p>Note that I have to use the 4 equations in my program for R, S, Q, and QN.</p>