title: Referencing entity generic inside package in VHDL?
body: <p>I am trying to define a type inside a package whose size is dependent on the component generics. Here is what I am trying to do, but synthesis is complaining:</p>
  
  <pre><code>package DcoPack is
      component SinCosDco
      generic
      (
           g_LUT_DEPTH   : integer := 2**10;
           g_LUT_BIT_RES : integer := 15
  
      );
      port
      (
          reset       : in  std_logic;
          lClk        : in  std_logic;
  
          InFreqCtrl  : in  std_logic_vector(31 downto 0) := X"028F5C28";   
          InStartPhse : in  std_logic_vector(31 downto 0) := X"00000000";   
  
          OutDco      : out signed((g_LUT_BIT_RES - 1) downto 0)
      );
  
  
      type LutSinT is array(0 to g_LUT_DEPTH - 1) of 
              std_logic_vector(g_LUT_BIT_RES-1 downto 0);
  
      function f_QuantizationSgn(nbit : integer; max_abs : real; dval : real) 
      return std_logic_vector;
  
      function f_InitLutSin 
      return LutSinT;   
  end package DcoPack;
  
  package body DcoPack is
      function f_QuantizationSgn(nbit : integer; max_abs : real; dval : real) 
      return std_logic_vector is
          &lt;function body&gt;
      end function;
  
      function f_InitLutSin return LutSinT is
          &lt;function body&gt;
      end function;
  end package body DcoPack;
  </code></pre>
  
  <p>and my component</p>
  
  <pre><code>library DCO_lib;
  use DCO_lib.DcoPack.all;
  
  entity Dco is
      generic
      (
           g_LUT_DEPTH   : integer := 2**10;
           g_LUT_BIT_RES : integer := 15
      );
      port
      (
          reset       : in  std_logic;
          lClk        : in  std_logic;
  
          InDcoEn     : in  std_logic;
          InFreqCtrl  : in  std_logic_vector(31 downto 0) := X"028F5C28";   
          InStartPhse : in  std_logic_vector(31 downto 0) := X"00000000";
  
          OutDco      : out signed((g_LUT_BIT_RES - 1) downto 0)
      );
  end entity Dco;
  
  architecture zDco of Dco is
      -- want to reference LutSinT in numerous components, it varies depending 
      -- on generics
      constant c_SinCosLut : LutSinT := f_InitLutSin;
  ... &lt;rest of code is irrelevant
  </code></pre>
  
  <p>As the code above shows, I am trying to reference this type inside each component. However, I need to be able to easily vary the generic parameters depending on the project, so is there a way for VHDL to infer the correct array size? Or am I locked into defining the g_LUT_DEPTH/g_LUT_BIT_RES in the package or hard-coding the type inside each component?</p>
  
  <p>EDIT: Added clarifying code snippets and explanation.</p>