title: left-justified text for pli call
body: <p>I'm trying to make my test-bench more scalable and with a set of PLI functions that require a path name to an instance. I'm trying to avoid having to hardcore that paths. I can construct the path with the <code>$sformat</code>/<code>$sformatf</code> system tasks/functions. I tried defining the path as a SystemVerilog <code>string</code> type, but the PLI rejects it and I cannot change the PLI. The PLI does accept a reg array.</p>
  
  <p>The challenge is the PLI requires left-justify text, but <code>$sformat</code>, <code>$sformatf</code> and <code>%s</code> are all right-justified.</p>
  
  <pre> left-justified : "tb.vdut[10].inst9.sample_func       " // Desired
  right-justified : "       tb.vdut[10].inst9.sample_func" // Actual
  </pre>
  
  <p>Example Function:</p>
  
  <pre><code>function void call(
      integer dut_id, inst_id,
      reg [CHAR_NUM-1:0] func_name,
      integer arg0, arg1, argN );
  
    reg [CHAR_NUM-1:0] path;
    $sformat(path,"tb.vdut[%0d].inst%0d.%0s", dut_id, inst_id, func_name );
  
    // Make path left-justified
    /* missing convert code here */
  
    $display("path:'%s', arg0:%0d, arg1:%0d, argN:%0d", path, arg0, arg1, argN );
    //$my_pli( path, arg0, arg1, argN );
  endfunction : call
  </code></pre>
  
  <p>I have a self answer, but I'm looking for a cleaner solution. The while-loop can suck up a lot of CPU time if <code>CHANR_NUM</code> is big and the function <code>call</code> is executed often times.</p>