title: Are there compiler directives for specifying the type of adder synthesized?
body: <p>I haven't had any luck finding this on Google, so here goes:</p>
  
  <p>Has anyone heard of a design compiler directive to specify which type of adder is synthesized? I'm looking for something that would work somewhat like this:</p>
  
  <pre><code>logic [7:0] a, b, c, d, e, f;
  
  /* ... */
  
  // synopsys use_carry_look_ahead
  assign c = a + b;
  
  // synopsys use_carry_select
  assign f = d + e;
  </code></pre>
  
  <p>FWIW, I'm writing with SystemVerilog and using the Synopsys DC compiler, but if anyone has heard of directives to accomplish this for other compilers, I am all ears.</p>
  
  <p>Thank you!</p>