title: How to handle a BUS in Verilog with multiple drivers
body: <p>I'm trying to connect multiple modules in verilog sharing a common "BUS" of size 16bits. I'm having trouble connecting multiple inputs(drivers) to the BUS. When I attach more then one driver, I get an error within Xilinx.</p>
  
  <blockquote>
    <p>Signal BUS in unit {Top_Module_Name} is connected to following multiple drivers:</p>
  </blockquote>
  
  <p>The code I have for the modules are</p>
  
  <pre><code>input         en;
  output [15:0] BUS;
  reg    [15:0] data;
  
  if (en) begin BUS = data;
  else BUS = 16'dZ;
  </code></pre>
  
  <p>In the top module I have something similar to</p>
  
  <pre><code>module1(en1,wBUS);
  module2(en2,wBUS);
  module3(en3,wBUS);
  </code></pre>
  
  <p>I have a controller controlling enables with 1 hot encoding.</p>