title: How to share constants between many files in Verilog?
body: <p>I'm using a simple UART in Verilog that has as part of some definitions of ASCII values.  For example:</p>
  
  <pre><code>parameter ASCII_a  = 8'h61;
  parameter ASCII_b  = 8'h62;
  parameter ASCII_c  = 8'h63;
  parameter ASCII_d  = 8'h64;
  parameter ASCII_e  = 8'h65;
  parameter ASCII_f  = 8'h66;
  </code></pre>
  
  <p>etc.  I'm trying to find the best way to create these parameters just once and then get access to them in multiple files.  I'm used to VHDL when you can create a package and include that package where you like.  I know that Verilog can use the <code>include</code> directive, but then I believe I need to surround it with <code>ifdefs</code>.  </p>
  
  <p>I would like to just create a SystemVerilog package, but I don't want to deal with Synthesis compatibility issues between vendor tools.  (I know that Microsemi has this weird thing where you can include SV files, but they need to end in .v for example).  </p>
  
  <p>For you long-time Verilog coders, what's the preferred approach for this?</p>