title: Saving Returned Value from Verilog Module
body: <p>I don't understand how to save the result from a verilog module.</p>
  
  <p>I declare something like this:  <code>andgate myand(x,y,andout);</code></p>
  
  <pre><code>module andgate(a,b, out);
      input a,b;
      output out;
      wire out;
      assign out = a &amp; b;
  endmodule 
  </code></pre>
  
  <p>But this returns a pointer that seems to evaluate whenever you use the pointer.</p>
  
  <p>So:  <code>assign n = andgate</code> just makes n into a copy of the andgate pointer.  I want to save the result from the module so I can reuse that value.</p>
  
  <p>Thanks</p>