title: Error: Iteration limit 5000 reached at time xxx ns
body: <p>I was reading the book "Verilog Hdl" by Samir Palnitkar. At the end of chapter 6 there is this exercise: design a synchronous counter using master-slave JK flip-flops. However I am struggling with the JK flip-flop part.
  Here's the JK flip-flop circuit provided in the book:
  <a href="https://i.stack.imgur.com/dbg66.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/dbg66.png" alt="Here&#39;s the JK flip-flop circuit provided in the book"></a></p>
  
  <p>And here's my Verilog code for the above circuit (I have checked it multiple times, hopefully there's no stupid mistake):</p>
  
  <pre><code>module test(in1, in2, clk, out, clr);
      input in1, in2, clk, clr;
      output out;
  
      mJKff wtf(
          .Q(out),
          .J(in1),
          .K(in2),
          .clk(clk),
          .clr(clr));
  
  endmodule
  
  module mJKff(Q, J, K, clk, clr);
      output Q;
      input J, K, clk, clr;
  
      wire
          a, b, c, d, y, ybar, cbar, qbar;
  
      assign
          a    = ~(qbar &amp; J &amp; clk &amp; clr),
          b     = ~(clk &amp; K &amp; Q),
          y     = ~(a &amp; ybar),
          ybar = ~(y &amp; clr &amp; b),
          c    = ~(y &amp; cbar),
          d    = ~(ybar &amp; cbar),
          cbar = ~clk;
  
      assign
          qbar = ~(Q &amp; clr &amp; d),
          Q    = ~(c &amp; qbar);
  
  endmodule
  </code></pre>
  
  <p>The code compiled successfully, I use Quartus Prime v18.0 for simulation and get this error:</p>
  
  <blockquote>
    <blockquote>
      <p>Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time xxx ns.</p>
    </blockquote>
  </blockquote>
  
  <p>"xxx" is exactly at the moment when 'clk' is rising and J = 1; K = 0; clr = 1
  What's wrong?</p>