title: How to represent assign logic array in Verilog generate block?
body: <p>I have difficulties in representing a simple assignment with generate block.
  My intention is 
        assign bus = disp[0] | disp[1] | disp[2] ...;
  The following code does not work. How can I fix it? Such accumulation related assignments does not appear in the Verilog mannual.  Thanks in advance for any advice.</p>
  
  <pre><code>genvar varx;
  for (varx = 0; varx &lt; `N; varx = varx + 1) begin
      if (varx == 0) assign bus = disp[0];
      else assign bus = bus | disp[varx];
      end
  </code></pre>