title: Beginner issue about make file syntax understanding
body: <p>I am trying to understand and modify a <code>makefile</code> which contains the following code</p>
  
  <pre><code>SOURCES= cvode.cpp RcppExports.cpp
  OBJECTS= $(SOURCES:.cpp=.o)
  </code></pre>
  
  <p>I understand the first line, i.e., assigning to a variable. I am assuming that second line is same as</p>
  
  <pre><code>OBJECTS = cvode.o RcppExports.o
  </code></pre>
  
  <p>i.e., same file names as in <code>$(SOURCES)</code> but with a <code>.o</code> extension. Is that correct?</p>
  
  <p>I read the <code>GNU make</code> documentation online but was not able to find the help for this sort of code formulation. Is this a macro?</p>
  
  <p>The reason I am asking is that I need to compile a <code>C</code> library on a <code>Solaris</code> machine where <code>GNU make</code> might not be available. I am trying to make the code more portable by as I got the following error:</p>
  
  <pre><code>mksh: Fatal error in reader: = missing from replacement macro reference
  </code></pre>
  
  <p>which might be <code>GNU make</code> specific. So my approach is to replace all the code written in the form of second line above (in the first code fragment) with more explicit inputs (as in second code fragment).</p>
  
  <p>Any guidance here would be very helpful.</p>
  
  <p>Thanks</p>