title: BCD to Excess 3 verilog code (case)
body: <p>I got my code to work. I did not set my output to 3'b000 before running the case statements.  it compiles and gives me desired outputs i think still verifying . I still have trouble with rtl compiler to take a shapshot of the circuit. Im sure every compiler is slightly diffrent so im not sure if anyone can help with this. I'm not sure why it hates everything. will re-post when done or if someones interested in helping thanks</p>