title: Distinguish between simulation and HDL code generation in simulink
body: <p>I am building a model using Simulink / Matlab Embedded Coder which is then converted to VHDL through HDL Coder. It should behave slightly different in simulation versus HDL, in particular concerning debug-output. </p>
  
  <p>Is there a programmatic way to distinguish which target is selected? This should preferably not need a manual switch such as "DEBUG = 1;" and ensure that disabled code or sub-models will not be synthesized at all. If the different "accelerator" modes could also be distinguished, that would be a plus.</p>
  
  <p><strong>Update:</strong>
  Such a switch should come into effect <em>before</em> the HDL code is auto-generated, since I want to avoid to manually touch generated code.</p>
  
  <p><strong>Solution:</strong>
  I found a solution that partially answers my question: <a href="http://www.mathworks.ch/ch/help/simulink/slref/environmentcontroller.html" rel="nofollow">EnvironmentController</a> offers such a switch in Simulink. Maybe there's also an Embedded-Matlab-only way?</p>