title: Peak FLOPs per cycle for ARM11 and Cortex-A7 cores in Raspberry Pi 1 and 2
body: <p>I would like to know the peak FLOPs per cycle for the ARM1176JZF-S core in the the Raspberry Pi 1 and Cortex-A7 cores in the Raspberry Pi 2.</p>
  
  <hr>
  
  <p>From the <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301h/Cegdejjh.html" rel="nofollow">ARM1176JZF-S Technical Reference Manual</a> it seems that VFPv2 can do one SP MAC every clock cycle and one DP MAC every other clock cycle. In addition there are three pipelines which can operate in parallel: a MAC pipeline (FMAC), a division and sqrt pipeline (DS), and a load/store pipeline (LS).  Based on this then it appears the ARM1176JZF-S of the Raspberry PI 1 can do at least (from the FMAC pipeline)</p>
  
  <ul>
  <li>1 DP FLOP/cycle: one MAC/2 cycles</li>
  <li>2 SP FLOPs/cycle: one MAC/cycle</li>
  </ul>
  
  <p><a href="https://en.wikipedia.org/wiki/Raspberry_Pi#Hardware" rel="nofollow">Wikipedia</a> claims the FLOPS of the raspberry PI 1 is <a href="http://elinux.org/RPi_Performance" rel="nofollow">0.041 DP GFLOPS</a>. Dividing by 0.700 GHz gives less than 0.06 DP FLOPs/cycle. That's about 17 times less than my estimate of 1 DP FLOP/cycle I get.</p>
  
  <p>So what's the correct answer?</p>
  
  <hr>
  
  <p>For the Cortex-A7 processor in the Raspberry Pi 2 I believe it's the same as the Cortex-A9. <a href="https://stackoverflow.com/questions/15655835/flops-per-cycle-for-sandy-bridge-and-haswell-sse2-avx-avx2/15657772#15657772">The FLOPs/cycle/core for the Cortex-A9</a> is:</p>
  
  <ul>
  <li>1.5 DP FLOPs/cycle: scalar addition + scalar multiplication every other cycle</li>
  <li>4 SP FLOPs/cycle: 4-wide NEON addition every other cycle + 4-wide NEON multiplication every other cycle.</li>
  </ul>
  
  <p>Is the FLOPs/cycle/core for the Raspberry Pi 2 the same as for Corrtex-A9? If not, what is the correct answer?</p>
  
  <p>Edit:</p>
  
  <p><a href="http://minipute.com/2013/06/29/which-mini-pc-cpu-architecture-cortex-a7-or-cortex-a9/1568" rel="nofollow">The main differences between the Cortex-A9 and Cortex-A7</a> (when it comes to peaks flops/cycle) are:</p>
  
  <ul>
  <li>the Cortex-A9 is dual-issue (two instructions per clock) and the Cortex-A7 is <a href="http://www.anandtech.com/show/4991/arms-cortex-a7-bringing-cheaper-dualcore-more-power-efficient-highend-devices" rel="nofollow">only partially dual-issue</a> "the A7 cannot dual-issue floating point or NEON instructions."</li>
  <li>the Cortex-A9 is an out-of-order (OoO) processor and the Cortex-A7 is not.</li>
  </ul>
  
  <p>I'm not sure why the OoO would affect the peak FLOPS. The dual issue certainly should. That would cut the peak FLOPS in half I think.</p>
  
  <p>Edit: based on the table <a href="http://hardwarebug.org/2014/05/15/cortex-a7-instruction-cycle-timings/" rel="nofollow">http://hardwarebug.org/2014/05/15/cortex-a7-instruction-cycle-timings/</a> Stephen Canon gave in a comment here are my new peak flops for the Cortex-A7</p>
  
  <ul>
  <li>0.5 DP FLOPs/cycle: one VMLA.F64 (VFP) every four cycles.</li>
  <li>1.0 DP FLOPs/cycle: one VADD.F64 (VFP) every cycle.</li>
  <li>2.0 SP FLOPs/cycle: one VMLA.F32 (VFP) every cycle. </li>
  <li>2.0 SP FLOPs/cycle: one VMLA.F32 (NEON) on two 32-bit floats every other cycle.</li>
  </ul>