title: What is the difference between "make" and "make all"?
body: <p>I have a Makefile with the following structure (working example).</p>
  
  <pre><code>.PHONY: image flashcard put-files
  
  put-files:
      @echo "=== put-files"
  
  image:
      @echo "=== image"
  
  flashcard:
      @echo "=== flashcard"
  
  all: put-files image flashcard
      @echo "Done"
  </code></pre>
  
  <p>I expect that a simple <code>make</code> would build all three targets, but this is not so:</p>
  
  <pre><code>% make
  === put-files
  </code></pre>
  
  <p>But if I explicitly specify the target, the dependencies are built as well:</p>
  
  <pre><code>% make all
  === put-files
  === image
  === flashcard
  Done
  </code></pre>
  
  <p>What am I doing wrong?</p>