title: Verilog code will simulate but won't synthesize.
body: <p>This is the code for my finite state machine</p>
  
  <pre><code>//
  `timescale 1ns / 1ps
  //Moore Finite State Machine Lab 3
  // 
  // WORKING, needs Screen output
  
  module moore(
      input BTNC,    //manual clk
      input SW0,     //clr
      input SW1,    
      input SW2,     
      input SW3,    
      input SW4,
      output reg [3:0] LED,    //z
      reg [2:0] y,Y
      );
      localparam S_00=3'b000, S_01=3'b001, S_02=3'b010,
                 S_03=3'b011, S_04=3'b100;
  
  //Define next state
      always @(y,SW0,SW1,SW2,SW3,SW4)
      begin
              case (y)
                  S_00: if (SW1)      Y &lt;= S_01;
                        else          Y &lt;= S_00;
                  S_01: if (SW1)      Y &lt;= S_02;
                        else if (SW3) Y &lt;= S_03;
                        else          Y &lt;= S_01;
                  S_02: if (SW1)      Y &lt;= S_04;
                        else          Y &lt;= S_02;
                  S_03: if (SW2)      Y &lt;= S_04;
                        else if (SW3) Y &lt;= S_02;
                        else          Y &lt;= S_03;
                  S_04: if (SW2)      Y &lt;= S_02;
                        else if (SW4) Y &lt;= S_00;
                        else          Y &lt;= S_04;
                        default:      Y &lt;= 3'bxxx;
              endcase
          end 
  
      //Define state update
      always @(SW0, BTNC)
         begin
          if (!SW0) y &lt;= S_00;
          else y &lt;= Y;
         end  
  
      //Define output
      always @(y)
          if (y==S_00)
              begin 
              assign LED = 3'b000;
              end
          else if (y==S_01)
              begin
              assign LED = 3'b001;
              end
          else if (y==S_02) 
              begin
              assign LED = 3'b010;
              end
          else if (y==S_03)
              begin 
              assign LED = 3'b011;
              end
          else if (y==S_04)
              begin 
              assign LED = 3'b100;
              end
          else
              begin 
              assign LED = 3'b000;  //not used
              end
  endmodule // lab3ht codename moore
  </code></pre>
  
  <p>and when trying to synthesize in vivado 2015.3 this is what it tells me</p>
  
  <pre><code>[Common 17-69] Command failed: Vivado Synthesis failed
  [Synth 8-285] failed synthesizing module 'moore' ["C:/Users/C/Desktop/moore3h/moore3/moore3.srcs/sources_1/new/moore.v":6]
  [Synth 8-27] procedural assign not supported ["C:/Users/C/Desktop/moore3h/moore3/moore3.srcs/sources_1/new/moore.v":51]
  [Synth 8-567] referenced signal 'Y' should be on the sensitivity list ["C:/Users/C/Desktop/moore3h/moore3/moore3.srcs/sources_1/new/moore.v":41]
  </code></pre>
  
  <p>I know that delays cannot be synthesized, and I tried fixing this by getting rid
  of always @(negedge BTNC) and using just the button press, but thats as far a my knowledge of verilog goes. I dont know why this cant be synthesized so i can later generate a bitstream and upload it to the basys3 board and use it there
  Any insight is greatly appreciated, The code runs beautifully during the simulation</p>