title: Xilinx error: Port connections cannot be mixed ordered and named
body: <pre><code>FA FA9(.in0(CSA10[0]), .in1(CSA11[0]), .carry_in(CSA12[0]), .sum(CSA20[0]), carry_out(CSA20[1]));
  </code></pre>
  
  <p>For the above line of code, I got error "Port connections cannot be mixed ordered and named". All the CSAs are declared as wire [1:0] CSA11, CSA12, etc. The tool I am using is Xilinx 14.7.</p>
  
  <p>I think the port connection I am using in the above statement is only named connection.</p>
  
  <p>Thanks in advance!</p>