title: wait statement must contain condition clause with UNTIL keyword
body: <p>The following VHDL is to be used to test bench. I keep getting an error on the first wait statement during analysis : "wait statement must contain condition clause with UNTIL keyword" I have several working test benches written this way. I can't seem to find what the error might be.  </p>
  
  <pre><code>`library IEEE;
  USE IEEE.std_logic_1164.all;
  entity case_ex_TB is end;
  architecture simple_test of case_ex_TB is
  --- DUT Component Declaration ---
  component case_ex
      port(
      clk, rstN: IN std_logic;
      color: OUT std_logic_vector(2 downto 0));
  end component;
  --- Signals Declaration ---
  signal rst, clock: std_logic:='0';
  signal color: std_logic_vector(2 downto 0);
  
  begin
  DUT: case_ex  --- DUT instantiation ---
  port map (clk =&gt; clock,
           rstN =&gt; rst,
           color =&gt; color);
  --- Signal's Waves Creation ---
  rst &lt;= '1','0' after 50 ns, '1' after 2 us;
  clock_crtate: process
  begin
      while rst = '0' loop
          clock &lt;= '1','0' after 50 ns;
          wait for 100 ns;
      end loop;
          clock &lt;= '1';
          wait;
  end process;
  end simple_test;`
  </code></pre>