title: Or Reduce An Array of Vectors
body: <p>Needs to be placed on a real board, so will have to synthesize.</p>
  
  <p>Using an old VHDL, libraries included:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.numeric_std.all;
  use ieee.std_logic_misc.all;
  </code></pre>
  
  <p>Some signals:</p>
  
  <pre><code>type my_array is array (N-1 downto 0) of std_logic_vector(31 downto 0);
  signal enable : my_array;
  signal ored_enable: std_logic_vector(31 downto 0);
  </code></pre>
  
  <p>Signals get joined up in a generator:</p>
  
  <pre><code>my_gen: for i in 0 to (N-1) generate
  
      woah: entity work.my_entity
  
              port map(
                      clk =&gt; clk,
                      enable =&gt; enable(i)
                      );
  
  
   end generate;
  
  ored_enable &lt;= or_reduce(enable); -- this fails
  </code></pre>
  
  <p>I'm just trying to create a <code>std_logic_vector</code> which holds the ored signals from the array. Any ideas how I can simply achieve this?</p>