title: Signals and Variables in VHDL
body: <p>I want to ask about the signals and variables in VHDL, I know the difference between them, but I want to see the difference at simulation.</p>
  
  <p>I used this simple program in Quartus Tool to see the difference between them:</p>
  
  <pre><code>ENTITY test IS PORT (
    a : IN bit;
    y : OUT bit);
  END test;
  
  ARCHITECTURE beh OF test IS
  SIGNAL x : BIT;
  BEGIN
    PROCESS (a)
    BEGIN
      x &lt;= '1';
      IF x = '1' THEN y &lt;= '0' AFTER 8 ns;
      ELSE y &lt;= '1' AFTER 5 ns;
      END IF;
    END PROCESS;
  END BEH;
  </code></pre>
  
  <p>for signals and this for variables:</p>
  
  <pre><code>entity test1 is port (
    a : IN bit;
    y : OUT bit);
  end test1;
  
  architecture beh of test1 is
  begin
    process (a)
    variable x : bit;
    begin
      x := '1';
      if x = '1' then y &lt;= '0' after 8 ns;
      else y &lt;= '1' after 5 ns;
      end if;
    end process;
  end beh;
  </code></pre>
  
  <p>the i created waveform to see the difference in the first program <code>(y)value</code> should be set to <code>1</code> at <code>5ns</code>,but it doesn't change..Why?</p>
  
  <p>Thank you in advance.</p>