title: BCD adder in Verilog code , I don't know my error
body: <h2>it is giving these errors:
  1bitFulladder.v:2: syntax error</h2>
  <p>I'm going to make a bcd adder into a structural design with two 4 bit adders.
  The error is not specific. No matter how much I look for errors, I can't find them.
  I don't understand what is wrong in this code:</p>
  <pre><code>module 1bitFulladder(ai, bi, cin, sum, cout);
  input   ai, bi, cin;
  output  sum, cout;
  
  wire    s0, c0, c1;
  
  assign  s0=ai^bi;
  assign  c0=ai&amp;bi;
  assign  c1=s0&amp;cin;
  assign  sum=s0^cin;
  assign  cout=c0|c1; endmodule
  
  module 4bitFulladder(a, b, Cin, Sum, Cout);
  
  input   [3:0]a;
  input   [3:0]b;
  input   Cin;
  output  [3:0]Sum;
  output  Cout;
  
  wire    c1, c2, c3;
  
  1bitFulladder f0(.ai(a[0]), .bi(b[0]), .cin(Cin), .sum(Sum[0]), .cout(c1));
  1bitFulladder f1(.ai(a[1]), .bi(b[1]), .cin(c1), .sum(Sum[1]), .cout(c2));
  1bitFulladder f2(.ai(a[2]), .bi(b[2]), .cin(c2), .sum(Sum[2]), .cout(c3));
  1bitFulladder f3(.ai(a[3]), .bi(b[3]), .cin(c3), .sum(Sum[3]), .cout(Cout));endmodule
  
  module bcdadder(A, B, Carry_in, C, result);
  
  input   [3:0]A;
  input   [3;0]B;
  input   Carry_in;
  output  [3:0]result;
  output  C;
  
  integer mid_sum=0;
  reg [4:0] mid_sum;
  reg [3:0] result;
  reg C;
  
  wire    [3:0]z;
  wire    [3:0]s;
  wire    k, w1, w2, w3;
  
  always@(A, B, Carry_in)
  begin
      mid_sum=A+B+Carry_in;
      if(mid_sum&gt;9) begin
          mid_sum=mid_sum+6;
          C=1;
          result=mid_sum[3:0]; 
      end
      else begin
          C=0;
          result=mid_sum[3:0];
      end
  end
  
  4bitFulladder F0(.a(A), .b(B), .Cin(Carry_in), .Sum(z), .Cout(k));
  assign  w1= z[3]&amp;z[2];
  assign  w2 = z[3]&amp;z[1];
  assign  result = k|w1|w2;
  assign  begin s[0]=0; s[1]=C; s[2]=C; s[3]=0; end
  4bitFulladder F1(.a(z), .b(s), .Cin(0), .Sum(result), .Cout(0)); endmodule
  </code></pre>
  <p>Thank you for any help!</p>