title: Casting to System Verilog struct and referencing member
body: <p>I would like to cast a vector to a struct and extract a member in the same statement.   Is this possible?  Otherwise, I would have to assign to a temporary variable, which is ugly.</p>
  
  <p>For example:</p>
  
  <pre><code>typedef struct packed { logic a; logic b } struct_t;
  struct_t my_struct;
  
  logic [1:0] foo;
  assign bar = struct_t'(foo).a;
  </code></pre>
  
  <p>^^^^^ This is apparently not allowed !   Why ?</p>