title: VHDL My timer does not work
body: <p>I have a 25MHz clock in my FPGA and I would like to make a timer which returns '1' when it counts for 60 seconds. But I have two problems:</p>
  
  <ul>
  <li>I don't understand why my outpout signal "count_sortie" is undefined in Vivado when I simulate it.</li>
  <li>To force to define my signal count_sortie, I add ":= 0" in the testbench file to simulate but "count_sortie" stays equal to '0' after the 60 seconds delay.</li>
  </ul>
  
  <p>Here are my VHDL files:</p>
  
  <pre><code>    library IEEE;
      use IEEE.STD_LOGIC_1164.ALL;
      use IEEE.STD_LOGIC_ARITH.all;
      use IEEE.STD_LOGIC_UNSIGNED.all;
  
  
      entity count is
          Port ( clk : in  STD_LOGIC;
                 count_entree : in STD_LOGIC;
                 count_sortie : out STD_LOGIC
                );
      end count;
  
      architecture Behavioral of count is
  
      signal q : integer range 0 to 30000000 :=0;
  
      begin
  
          process(clk)
          begin
          if (clk'event and clk='1')
          then 
  
                while ((count_entree = '1') and (q &lt; 25000000)) loop
  
                   if (q &lt; 25000000) then
  
                        q := q + 1;
                        count_sortie &lt;= '0';  
                   else 
  
                      count_sortie &lt;= '1';
  
                   end if;
                end loop;
          end if;
          end process;
  
      end Behavioral;
  </code></pre>
  
  <p>And the testbench file:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  ENTITY tbcount IS
  END tbcount;
  
  ARCHITECTURE behavior OF tbcount IS 
  
      -- Component Declaration for the Unit Under Test (UUT)
  
      COMPONENT count
      PORT(
             clk : in  STD_LOGIC;
             count_entree : in STD_LOGIC;
             count_sortie : out STD_LOGIC
          );
      END COMPONENT;
  
  
      --Inputs
  
     signal clk : std_logic := '0';
     signal count_entree : std_logic;
  
      --Outputs
  
     signal count_sortie : std_logic;
  
      --Clock
  
     constant clk_period : time := 40 ns;
  
  BEGIN
  
      -- Instantiate the Unit Under Test (UUT)
     uut: count PORT MAP (
            clk =&gt; clk,
            count_entree =&gt; count_entree,
            count_sortie =&gt; count_sortie
          );
  
     -- Clock process definitions
     clk_process :process
     begin
          clk &lt;= '0';
          wait for clk_period/2;
          clk &lt;= '1';
          wait for clk_period/2;
     end process;
  
  
         -- Stimulus process
     stim_proc: process
     begin        
  
      count_entree &lt;= '1';
  
        wait;
     end process;
  
  END;
  </code></pre>
  
  <p>Thank you for your support.</p>