title: How to run this code in series using verilog
body: <p>The following code is compiled and is working in parallel, Please help me to make these code work sequentially, i.e after stage1 counter should reset itself and starts from 0 for the stage2. The following codes has Module1- stage1 and module2-stage2. This is the process flow in which one stage occur after completion of another. For example when stage 1 is done then counter reset itself and then stage 2 starts with count zero.Here stage 1 module has counter that counts till 18 and stage 2 counter counts 8.  </p>
  
  <pre><code>    module stage1(
                  input Clk, //50 Hz clock
                  input x0,
                  input reset,
                  output reg y0,y1,y2,y3,y5,y7,y10,y15,
                  output reg stage1_done
                  );                
          reg [15:0] counter = 0;
          parameter F = 50;                  
          always@ (posedge Clk or posedge reset)
              if(reset) begin
                  counter &lt;= 0;
                  {y0,y1,y2,y3,y5,y7,y10,y15} &lt;= 8'b00000000;
                  stage1_done &lt;= 0;
              end else begin  
                  if(x0 == 1) begin
                      if(counter == 18*F)
                          stage1_done &lt;= 1;
                      else begin
                          counter &lt;= counter + 1;
                          stage1_done &lt;= 0;
                      end 
                      if(counter &gt;= 1*F &amp;&amp; counter &lt; 10*F)
                          y0 &lt;= 1;
                      else
                          y0 &lt;= 0;
                      if(counter &gt;= 1*F &amp;&amp; counter &lt; 17*F)
                          y1 &lt;= 1;
                      else
                          y1 &lt;= 0;
                      if(counter &gt;= 1*F &amp;&amp; counter &lt; 9*F)
                          y2 &lt;= 1;
                      else
                          y2 &lt;= 0;
                      if(counter &gt;= 11*F &amp;&amp; counter &lt; 16*F)
                          y3 &lt;= 1;
                      else
                          y3 &lt;= 0;
                      if(counter &gt;= 1*F &amp;&amp; counter &lt; 18*F)
                          y5 &lt;= 1;
                      else
                          y5 &lt;= 0;
                      if(counter &gt;= 1*F &amp;&amp; counter &lt; 5*F)
                          y7 &lt;= 1;
                      else
                          y7 &lt;= 0;
                      if(counter &gt;= 1*F &amp;&amp; counter &lt; 5*F)
                          y10 &lt;= 1;
                      else
                          y10 &lt;= 0;
                      if((counter &gt;= 2*F &amp;&amp; counter &lt; 9*F) || (counter &gt;= 13*F &amp;&amp; counter &lt; 17*F))
                          y15 &lt;= 1;
                      else
                          y15 &lt;= 0;   
                  end         
              end 
  
          endmodule
  </code></pre>
  
  <p>//Module for stage 2;</p>
  
  <pre><code>    module stage2(
              input x0,
              input Clk, //50 Hz clock
              input reset,
              output reg y1,y3,y5,
              output reg stage2_done 
              );            
      reg [15:0] counter = 0;
      parameter F = 50;         
      always@ (posedge Clk or posedge reset)
          if(reset) begin
              counter &lt;= 0;
              {y1,y3,y5} &lt;= 3'b000;
              stage2_done &lt;= 0;
          end 
      else begin   if(x0 == 1) begin
              if(counter == 8*F)
                  stage2_done &lt;= 1;
              else begin
                  counter &lt;= counter + 1;
                  stage2_done &lt;= 0;
              end 
              if(counter &gt;= 1*F &amp;&amp; counter &lt; 8*F)
                  y1 &lt;= 1;
              else
                  y1 &lt;= 0;
              if(counter &gt;= 1*F &amp;&amp; counter &lt; 8*F)
                  y3 &lt;= 1;
              else
                  y3 &lt;= 0;
              if(counter &gt;= 1*F &amp;&amp; counter &lt; 8*F)
                  y5 &lt;= 1;
              else
                  y5 &lt;= 0;
              end                     
          end 
  
      endmodule
  </code></pre>