title: Is it necessary to sign extend 0 bits in Verilog?
body: <p>Simple 32-bit register:</p>
  
  <pre><code>    reg32 Reg_32 (
      .in(valueA), // input 32 bits               
      .clock(clk),
      .reset(rst),
      .out(valueB) // output 32 bits  
  </code></pre>
  
  <p>However, <code>valueA</code> is defined as a 10-bit wire [9:0].</p>
  
  <p>Does <code>valueA</code> need 22 extended 0 bits?</p>
  
  <p>i.e.:  </p>
  
  <pre><code>    .in({22b'0,valueA}), // 22 bits of 0 + value of wire [9:0]
  </code></pre>
  
  <p>or does the compiler do this in ModelSim?</p>