title: Direct Mapped Cache of Blocks Example
body: <p>So i have this question in my homework assignment that i have struggling a bit with. I looked over my lecture content/notes and have been able to utilize those  to answer the questions, however, i am not 100% sure that i did everything correctly. There are two parts (part C and D) in the question that i was not able to figure out even after consulting my notes and online sources. I am not looking for a solution for those two parts by any means, but it would be greatly appreciated if i could get, at least, a nudge in the right direction in how i can go about solving it. </p>
  
  <p>I know this is a rather large question, however, i hope someone could possibly check my answers and tell me if all my work and methods of looking at this problem is correct. As always, thank you for any help :) </p>
  
  <p>Alright, so now that we have the formalities out of the way,</p>
  
  <p><strong>--------------------------Here is the Question:--------------------------</strong></p>
  
  <p>Suppose a small direct-mapped cache of blocks with 32 blocks is constructed. Each cache block stores
  eight 32-bit words. The main memory—which is byte addressable1—is 16,384 bytes in size. 32-bit words are stored
  word aligned in memory, i.e., at an address that is divisible by 4.</p>
  
  <p>(a) How many 32-bit words can the memory store (in decimal)?</p>
  
  <p>(b) How many address bits would be required to address each byte of memory?</p>
  
  <p>(c) What is the range of memory addresses, in hex? That is, what are the addresses of the first and last bytes of
  memory? I'll give you a hint: memory addresses are numbered starting at 0.</p>
  
  <p>(d) What would be the address of the last word in memory?</p>
  
  <p>(e) Using the cache mapping scheme discussed in the Chapter 5 lecture notes, how many and which address bits
  would be used to form the block offset?</p>
  
  <p>(f) How many and which memory address bits would be used to form the cache index?</p>
  
  <p>(g) How many and which address bits would be used to form the tag field for each cache block?</p>
  
  <p>(h) To which cache block (in decimal) would memory address 0x2A5C map to?</p>
  
  <p>(i) What would be the block offset (in decimal) for 0x2A5C?</p>
  
  <p>(j) How many other main memory words would map to the same block as 0x2A5C?</p>
  
  <p>(k) When the word at 0x2A5C is moved into a cache block, what are the memory addresses (in hex) of the other
  words which will also be moved into this block? Express your answer as a range, e.g., [0x0000, 0x0200].</p>
  
  <p>(l) The first word of a main memory block that is mapped to a cache block will always be at an address that is
  divisible by __ (in decimal)?</p>
  
  <p>(m) Including the V and tag bits of each cache block, what would be the total size of the cache (in bytes)</p>
  
  <p>(n) what would be the size allocated for the data bits (in bytes)?</p>
  
  <p><strong>----------------------My answers and work-----------------------------------</strong></p>
  
  <p>a) memory = 16384 bytes. 16384 bytes into bits = 131072 bits. 131072/32 = <strong>4096 32-bit words</strong></p>
  
  <p>b) 2^14 (main memory) * 2^2 (4 bits/word) = 2^16. take log(base2)(2^16) = <strong>16 bits</strong></p>
  
  <p>c) couldnt figure this part out (would appreciate some input (<strong>NOT A SOLUTION</strong>) on how i can go about looking at this problem </p>
  
  <p>d)could not figure this part out either :(</p>
  
  <p>e)8 words in each cache line. 8 * 4(2^2 bits/word) = 32 bits in each cache line. log(base2)(2^5) = <strong>5 bits used for block offset</strong>.</p>
  
  <p>f) # of blocks = 2^5 = 32 blocks. log(base2)(2^5) = <strong>5 bits for cache index</strong></p>
  
  <p>g) tag = 16 - 5 - 5 - 2(word alignment) = <strong>4 bits</strong></p>
  
  <p>h) 0x2A5C</p>
  
  <pre><code>   0010    10100      10111          00 
  
     tag     index      offset  word aligned bits
  </code></pre>
  
  <p>maps to cache block index = 10100 = <strong>0x14</strong></p>
  
  <p>i) maps to block offset = 10111 = <strong>0x17</strong></p>
  
  <p>j) 4 tag bits, 5 block offset = <strong>2^9 other main memory words</strong></p>
  
  <p>k) it is a permutation of the block offsets. so it maps the memory addresses with the same tag and cache index bits and block offsets of <strong>0x00 0x01 0x02 0x04 0x08 0x10 0x11 0x12 0x14 0x18 0x1C 0x1E 0x1F</strong></p>
  
  <p>l)divisible by <strong>4</strong></p>
  
  <p>m) 2(V+tag+data) = 2(1+4+2^3*2^5) = 522 bits = <strong>65.25 bytes</strong></p>
  
  <p>n)data bits = 2^5 blocks * 2^3 words per block = 256 bits =  <strong>32 bytes</strong></p>