title: Is there a way to embed a constant in a struct in SystemVerilog?
body: <p>In a perfect world, I would be able to scope a localparam to the inside of a struct:</p>
  
  <pre><code>typedef struct {
    logic [10:0] mantissa;
    localparam exponent = -10;
  } my_fixed_point_type;
  </code></pre>
  
  <p>But alas, this is not legal SystemVerilog.  I've investigated using const ints (illegal), enums (not scoped to the struct, and requires "storage").  </p>
  
  <p>I might consider just embedding an int into the struct, and trust the synthesis tool to notice the values are only ever initialized, and strip them away, but some synthesis tools are just as likely to ignore initialization.</p>
  
  <p>The only approach I've found so far that actually words is this abomination:</p>
  
  <pre><code>typedef struct {
    logic [10:0] mantissa;
    logic [25:0] _hidden;
  } my_fixed_point_type;
  
  `define FP_EXPONENT(var) $bits(var._hidden)
  </code></pre>
  
  <p>Since <code>_hidden</code> is never read from, I have high confidence that it will get stripped out at elaboration time, while the bit width of <code>_hidden</code> can be used to hide an (unsigned) integer constant.  Ugly!</p>
  
  <p>Surely there must be a better way to scope a constant to a struct in a way that is preserved in synthesis, but doesn't take up any actual bits.  Or, do I have to take this up with the SystemVerilog 2016 committee?</p>