title: Assign integer to reg in Verilog
body: <p>I have problems with this Verilog code. Basically, it won't let me do the <code>Y = 3'di</code> statement. Basically, I want <code>Y</code> to equal <code>i</code>. I am pretty sure the problem is the <code>i</code>. So, is there a way to do this in Verilog? Also, <code>W</code> is an input with 8 bits (in other words, <code>W[7:0]</code>). </p>
  
  <pre><code>for (i = 7; i &gt;= 0; i = i - 1)
  begin
      if(W[i]) Y=3'di;
  end
  </code></pre>
  
  <p>Thanks. </p>