title: Verilog: differences between if statement and case statement
body: <p>I am new to Verilog language and want to do some practices to get familiar with it. And I encountered this problem on HDLbits: <a href="https://hdlbits.01xz.net/wiki/Dff8ar" rel="nofollow noreferrer">DFF8ar</a></p>
  <p>This problem asks me to create 8 D flip-flops with active-high asynchronous reset. I use a <code>case</code> statement to handle the <code>areset</code> signal:</p>
  <pre><code>module top_module (
  input clk,
  input areset,   // active high asynchronous reset
  input [7:0] d,
  output reg[7:0] q
  );
  
  always @(posedge clk or posedge areset) begin
      case (areset)
          1'b1: q &lt;= 8'b0; 
          default: q &lt;= d;
      endcase
  end
  endmodule
  </code></pre>
  <p>And to my surprise, the circuit it generated ignores the <code>clk</code> signal:
  <a href="https://i.stack.imgur.com/0iG7J.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0iG7J.png" alt="enter image description here" /></a></p>
  <p>But, if I switch the <code>case</code> statement to an <code>if-else</code> statement, the result will be correct:</p>
  <pre><code>always @(posedge clk or posedge areset) begin
      if (areset)
          q &lt;= 8'b0; 
      else q &lt;= d;
  end
  </code></pre>
  <p><a href="https://i.stack.imgur.com/ZMk6I.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZMk6I.png" alt="enter image description here" /></a></p>
  <p>I don't know the reason behind it even after doing some research. Does <code>if-else</code> statements and <code>case</code> statements have some fundamental difference? Any help is appreciated!</p>