title: Systemverilog coverpoint for each element in enum
body: <p>I am using UVM environment for verification my design. In monitor, I created coverpoints for my design. However, I can not use  enums for coverpoint bins. </p>
  
  <p>For each coverpoint, I want to create a bin for each element in enum. </p>
  
  <p>For example,
  in monitor.sv file</p>
  
  <pre><code>enum bit [7:0]
  {
     data_type_0 =8'd1,
     data_type_1 =8'd16,
     data_type_2 =8'd32,
     data_type_3 =8'd64
  } data_types;
  
  data_type: coverpoint seq_item.data_type
  {
    bins data_type_bins[] = {[data_types.first:data_types.last]};
  }
  </code></pre>
  
  <p>I tried first and last method, but it creates bin for each number between 1 and 64. I don't want that. I want bins for only 1,16,32,64</p>