title: Use of conv_integer in VHDL
body: <p>I am in the process of trying to write some code that will simply just shift a 32 bit vector left or right, with a 5 bit input that will be used for the shift amount (<code>shamt</code>).  The issue I am having is trying to convert an <code>std_logic_vector</code> to an <code>integer</code>. My code is this:</p>
  
  <pre><code>library ieee;
  use ieee.STD_LOGIC_1164.all;
  use ieee.STD_LOGIC_ARITH.all;
  
  entity shiftlogical is
    port(x     : in  std_logic_vector(31 downto 0);
         shamt : in  std_logic_vector( 4 downto 0);
         y     : out std_logic_vector(31 downto 0));
  end shiftlogical;
  
  architecture beh of shiftlogical is
    signal shift : integer;
    signal temp  : std_logic_vector(31 downto 0);
  begin
    shift &lt;= conv_integer(unsigned(shamt));
    temp  &lt;= x(shift downto 0);
    y     &lt;= temp;
  end beh;
  </code></pre>
  
  <p>The code is not complete I know, but to test some ideas I am trying to pass <code>"00010"</code> (2) into <code>shamt</code>, but shift comes out to be -2147483648.  But I cannot figure out why it is doing this, nor can I find any resources online that shows anything different than what I am doing.  I greatly appreciate any help.</p>