title: near text "=" expecting "(" or " ' " or "."
body: <p>I'm trying to create an entity to fill an array from signals, but I'm getting the following error: near text "=" expecting "(" or " ' " or "."</p>
  
  <p>This is my vhdl code</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  library work;
  use work.all;
  
  entity decryptionarray is 
      port(
          clk: in std_logic;
          key_in: in std_logic_vector(7 downto 0);
          encrypted_data : in std_logic_vector(127 downto 0);
          encrypted_data_in : in std_logic_vector(127 downto 0);
          decryption_key: out std_logic_vector(7 downto 0)
      );
  end entity decryptionarray;
  
  architecture bhv of decryptionarray is
  type deckeyarray is array (0 to 10) of std_logic_vector(127 downto 0);
  signal dkey, keyin : std_logic_vector(7 downto 0);
  signal edatain, edata : std_logic_vector(127 downto 0);
  
  begin
      P0:process(clk) is 
          begin
              if(deckeyarray(10)/=null) then
                  for j in 0 to 10 loop
                      deckeyarray(j)=null;
                  end loop;
  
              else
                  keyin &lt;= key_in;
                  edata &lt;= encrypted_data;
                  edatain &lt;= encrypted_data_in ;
                  dkey &lt;= decryption_key ;
              end if;
      end process P0;
  end architecture bhv;   
  </code></pre>