title: How to concatenate a byte with a string in SystemVerilog
body: <p>In ModelSim, the following code works just fine:</p>
  
  <pre><code>string r;
  string s;
  // ...assign some string to s...
  integer i;
  r = "";
  for (i=s.len()-1; i&gt;=0; i=i-1) begin
      if (s[i] != "\n") begin
          r = {s[i], r};
      end
  end
  </code></pre>
  
  <p>In Aldec Riviera, this causes a compilation error <code>Incompatible types at assignment: .r&lt;string&gt; &lt;- s[i]&lt;byte&gt;</code>. </p>
  
  <p>Reading the SystemVerilog LRM, I can see that the curly braces seem to be only supported to concatenate strings, not bytes. So either ModelSim is not as strict with the LRM or it implicitly converts the <code>s[i]</code> byte to a one-character string (which seems sensible in this context). In Riviera, it looks like I have to convert the byte <code>s[i]</code> to a one-character string manually. What is the most efficient and concise solution (if possible without having to introduce a temporary variable)?</p>