title: Systemverilog problem with always_comb construct
body: <p>I have a problem with this SystemVerilog code.  Here is the code:</p>
  
  <pre><code>module mult ( multiplicand, multiplier, Product, clk, clear, Startm, endm );
  
  input [31:0] multiplicand;
  input [31:0] multiplier  ;
  input clk;
  input clear; 
  input Startm;
  
  output logic [63:0] Product;
  output logic endm;
  
  
  enum logic [1:0] { inicio, multiplicar, nao_multiplicar, fim } estados;
  logic [1:0] state;
  
  logic [31:0] mplier;
  logic [31:0] mplier_aux;
  logic [31:0] mcand ;
  logic [31:0] mcand_aux;
  logic [63:0] Prod  ;
  logic [63:0] Prod_aux;
  logic [5:0] cont;
  logic [5:0] cont_aux;
  
  initial begin
      mplier     = multiplier;
      mplier_aux = multiplier;
      mcand     = multiplicand;
      mcand_aux = multiplicand;
      Prod      = 0;
      Prod_aux  = 0;
      state     = inicio;
      cont      = 0;
      cont_aux  = 0; 
  end
  
  always_ff @( posedge clk )
  begin
      if( clear ) 
      begin
          state &lt;= inicio;
      end
      else if ( Startm )
      begin
          case( state )
          inicio :
          begin
                      if( mplier[0] == 0 )
                      begin
                          state &lt;= nao_multiplicar;
                      end
                      else if( mplier[0] == 1 )
                      begin
                          state &lt;= multiplicar;
                      end
          end
          multiplicar :
          begin
                      if( cont == 32 )
                          state &lt;= fim;
                      else if( mplier[0] == 0 )
                      begin
                          state &lt;= nao_multiplicar;
                      end
                      else if( mplier[0] == 1 )
                      begin
                          state &lt;= multiplicar;
                      end
          end
          nao_multiplicar:
          begin
                      if( cont == 32 )
                          state &lt;= fim;
                      else if( mplier[0] == 0 )
                      begin
                          state &lt;= nao_multiplicar;
                      end
                      else if( mplier[0] == 1 )
                      begin
                          state &lt;= multiplicar;
                      end
          end
          fim:
          begin
                      state &lt;= inicio;
          end
          endcase
      end
  end
      always_comb
      begin
          case(state)
          inicio:
          begin
                      mplier = multiplier;
                      mcand  = multiplicand;
                      Prod   = 0;
                      cont_aux = cont + 1;
                      cont = cont_aux;
          end
          multiplicar:
          begin   
                      mcand_aux  = mcand  &lt;&lt; 1;
                      mcand      = mcand_aux  ;
                      mplier_aux = mplier &gt;&gt; 1;
                      mplier     = mplier_aux ;
                      Prod_aux   = Prod + mcand;
                      Prod       = Prod_aux;
                      cont_aux   = cont + 1;
                      cont       = cont_aux;
          end
          nao_multiplicar:
          begin
                      cont_aux = cont + 1;
                      cont     = cont_aux;
          end
          fim:
          begin
                      Product = Prod;
                      endm    = 1;
          end
          endcase
      end     
  endmodule
  </code></pre>
  
  <p>I'm trying write a multiplicator with inputs of 32 bits and a product of 64 bits using 
  the Booth's algorithm. This error occur:</p>
  
  <blockquote>
    <p>always_comb construct does not infer purely combinational logic</p>
  </blockquote>
  
  <p>Why does this happens? </p>