title: Access top level resources outside of hierarchy
body: <p>is there a way to synthesize an architecture in verilog such that a deeply nested endpoint can access some top level pins (from a .ucf) without expressly routing the pins through every module of the  hierarchy.</p>
  
  <p>In my case i have a PCIe block with a deeply nested endpoint.
  AT the endpoint there have an address decoder that needs to provide some signal information from pins at the top level.</p>
  
  <p>I'd rather not modify every intervening module to carry the necessary wires.</p>
  
  <p>my web searches are frustrated because the terms 'net' and 'bus'  already have alternative meanings in verilog.</p>
  
  <p>I have tried specific hierarchical naming like (for example)
  top.button and top.LED but have only succeeded in getting access to readable pins, but not writeable pins, leading me to assume i'm missing something fundamental here.</p>
  
  <p><strong>UPDATE</strong>
  I can simulate this
  <a href="http://www.edaplayground.com/x/AAq" rel="nofollow">http://www.edaplayground.com/x/AAq</a></p>
  
  <p>and synthesize (a similar construct)  without error (Xilinx XST)
  but there is no output on the LED when it is run in real hardware
  so i'm wondering if upwards name reference is not supported for synthesis?</p>