title: VHDL Frequency Meter that reads NCO
body: <p>&lt;hi guys im trying to make an auto-ranging 4-digit frequency meter for measuring signals with frequencies from
  10 Hz to 10 MHz. An external 1 MHz generator is used to provide a clock signal to the meter. To do this I have made an NCO to generate frequency but I dont know how to make the frequency meter. Any clues or examples you can show me? From what I understand is you can use &quot;1 sec gate&quot; to compare your rising_edge from NCO pulses to another clock, maybe Im wrong Help Please.</p>
  <p>NCO code</p>
  <pre><code>    
  ENTITY PA IS
      -- N:width of address 2^N; M:width of accumultor;
      GENERIC(N:natural:=12;
                  M:natural:=26);
      PORT(
          clk: IN STD_LOGIC; -- 50 MHz
          nrst: IN STD_LOGIC;
          -- 100Hz resolution, Fres=Fclk/(2^M)
          phase_inc: IN STD_LOGIC_VECTOR(M-1 DOWNTO 0);
          address: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0);
      );
  END PA;
  
  ARCHITECTURE PA_IMPL OF PA IS
      SIGNAL accum: STD_LOGIC_VECTOR(M-1 DOWNTO 0):=(OTHERS=&gt;'0');
  BEGIN
      PROCESS(clk,nrst)
      BEGIN
          IF(nrst='0') THEN
              accum &lt;= (OTHERS=&gt;'0');
          ELSIF(rising_edge(clk)) THEN
                  if (accum &gt;= &quot;10111110101111000010000000&quot;) then --capping it at 50MHZ
              accum &lt;=phase_inc;
                  else
                  accum &lt;= phase_inc + accum ; --accum into phase freq in?
                  end if;
          END IF;    
      END PROCESS;    
      address &lt;= accum(M-1 DOWNTO M-N);
       --msb_o &lt;= count(count'left);
  END ARCHITECTURE;   
  </code></pre>