title: verilog counter implementation unexpected behaviour
body: <p>I made a counter in verilog and realized it in hardware. But I am unable to explain the behaviour The code is:</p>
  
  <pre><code>module clock_test(clk_in,led,rst);
  input wire clk_in;
  input wire rst;
  output wire [7:0] led;
  
  reg [23:0] counter = 24'b0;
  
  assign led = counter[23:16];
  
  always @(posedge clk_int)  begin
      if(rst) begin
       counter &lt;= 0;
    end
  else begin
       counter &lt;= counter +1;
     end
   end
   endmodule // clock_test
  </code></pre>
  
  <p>In the hardware, when I hit <code>rst</code>, the LEDs freeze at the point it was counting. Its not becoming exactly zero. Assert <code>rst</code>, and you can see some random pattern other than zero, which dont change unless I release <code>rst</code>.</p>
  
  <p>My question is : when <code>if(rst) begin</code> block executes, <code>counter</code> is set to 0. Since leds are assigned as combo logic from <code>counter</code>, should'nt it reflect immediately ?</p>