title: How to prevent ModelSIM from stopping during simulation?
body: <p>I'm trying to simulate a down counter which I described using D-Latches in SystemVerilog but when I start simulating, ModelSIM stops working and I can not do anything.</p>
  
  <p>This is the down counter description</p>
  
  <pre><code>`timescale 1ns/1ns
  module Down_Counter_Part5 (input RST,CLK,EnableIN, output[7:0] Qout, output EnableOUT);
  
      genvar i;
      wire[8:0] En;
      wire[7:0] D,Qbar;
  
      assign En[0] = EnableIN;
      assign EnableOUT = En[8];
  
      generate
          for (i=0; i&lt;8; i=i+1) begin
              assign D[i] = (Qout[i] ^ En[i]) &amp; (~RST);
              assign En[i+1] = Qbar[i] &amp; En[i];
              Clocked_D_Latch Ii (D[i],CLK,Qout[i],Qbar[i]);
          end
      endgenerate
  
  endmodule
  </code></pre>
  
  <p>And It's my testbench</p>
  
  <pre><code>`timescale 1ns/1ns
  module Testbench_Part6 ();
  
      logic rst = 1,clk = 1,enablein = 1;
      wire[7:0] qout;
      wire enableout;
  
      Down_Counter_Part5 UUT (rst,clk,enablein,qout,enableout);
  
      initial repeat (5) #5000 rst = ~rst;
  
  endmodule
  </code></pre>
  
  <p>How can I solve the problem?</p>