title: Calling a Component Inside Another Component "Port Mapping" (Illegal Statement) VHDL
body: <p>I am facing a confusing problem in my program. I need in my program to port map (calling) a component. Also, inside the component, I need to do another port mapping (calling) which is illegal in VHDL. Do you have an alternative solution to this problem. Here is an example of what I meant. </p>
  
  <p>Here I start my program:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  entity binary1 is
  port( N: in std_logic;
    d: out integer);
  end binary1 ;  
  
  
  Architecture Behavior1 of binary1 is
  </code></pre>
  
  <p>Here is a component for example:</p>
  
  <pre><code>component binary_integer_1 is
  port ( b1: in std_logic;
     int1: out integer);
  end component;
  </code></pre>
  
  <p>The command for calling the component:
      begin
      s0: binary_integer_1 port map(n,d);
      end Behavior1 ;</p>
  
  <p>Also, here is the main program:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  entity binary_integer_1 is
  port ( b1: in std_logic;
  int1: out integer);
  end binary_integer_1;
  architecture Behavior4 of binary_integer_1 is 
  begin
  process(b1)
  begin
  if b1 = '1' then
     int1 &lt;= 1; 
     else
     int1 &lt;= 0;
   end if;
   end process;
   end Behavior4;
  </code></pre>
  
  <p>For example, if I want to do a port map inside the upper entity. I have got an illegal statement.
  Please, provide me with another way to do it.</p>