title: What should '{default:'1} do in system verilog?
body: <p>I have an array that I would like to initialize to all 1.  To do this, I used the following code snippet:</p>
  
  <pre><code>logic [15:0] memory [8];
  always_ff @(posedge clk or posedge reset) begin
     if(reset) begin
        memory &lt;= '{default:'1};
     end
     else begin
        ...
     end  
  end
  </code></pre>
  
  <p>My simulator does what I think is the correct thing and sets the registers to <code>16'hFFFF</code> on reset.  However, my lint tool gives me a warning that bit 0 has an async set while bits 1 through 15 have async resets.  This implies that the linter thinks that this code assigns <code>16'h0001</code> to the registers.</p>
  
  <p>Since both tools come from the same vendor I file a bug report since they can't both be right.</p>
  
  <p>The question is: Which behavior is correct according to the spec?  There is no example that shows this exact situation.  Section 5.7.1 mentions that:</p>
  
  <blockquote>
    <p>An unsized single-bit value can be specified by preceding the single-bit value with an apostrophe ( ' ), but
    without the base specifier. All bits of the unsized value shall be set to the value of the specified bit. In a
    self-determined context, an unsized single-bit value shall have a width of 1 bit, and the value shall be treated
    as unsigned.</p>
    
    <p>'0, '1, 'X, 'x, 'Z, 'z // sets all bits to specified value</p>
  </blockquote>
  
  <p>I f this is a "self-determined context" then the answer is 1 bit sign extended to 16'h0001, but if it is not, then I guess the example which says it "sets all bits to the specified value" applies.  I am not sure if this is a self -determined context.</p>