title: Verilog testbench for fifo
body: <p>Can anyone help me in writing verilog test bench code for the following code !.
   I have tried but it's doesn't work !.
  it's a code for fifo(first in first out) with a single clock.
  i use icarus simulator</p>
  
  <p>fifo4:</p>
  
  <pre><code>`timescale 1ns/10ps
  
  module fifo4(clk, rst, clr,  din, we, dout, re, full, empty);
  
  parameter dw = 8;
  
  input       clk, rst;
  input       clr;
  input   [dw:1]  din;
  input       we;
  output  [dw:1]  dout;
  input       re;
  output      full, empty;
  
  
  
  
  reg     [dw:1]  mem[0:3];
  reg     [1:0]   wp;
  reg     [1:0]   rp;
  wire    [1:0]   wp_p1;
  wire    [1:0]   wp_p2;
  wire    [1:0]   rp_p1;
  wire        full, empty;
  reg     gb;
  
  
  always @(posedge clk or negedge rst)
      if(!rst)    wp &lt;= #1 2'h0;
      else
      if(clr)     wp &lt;= #1 2'h0;
      else
      if(we)      wp &lt;= #1 wp_p1;
  
  assign wp_p1 = wp + 2'h1;
  assign wp_p2 = wp + 2'h2;
  
  always @(posedge clk or negedge rst)
      if(!rst)    rp &lt;= #1 2'h0;
      else
      if(clr)     rp &lt;= #1 2'h0;
      else
      if(re)      rp &lt;= #1 rp_p1;
  
  assign rp_p1 = rp + 2'h1;
  
  
  assign  dout = mem[ rp ];
  
  
  always @(posedge clk)
      if(we)  mem[ wp ] &lt;= #1 din;
  
  
  assign empty = (wp == rp) &amp; !gb;
  assign full  = (wp == rp) &amp;  gb;
  
  
  always @(posedge clk)
  if(!rst)            gb &lt;= #1 1'b0;
  else
  if(clr)             gb &lt;= #1 1'b0;
  else
  if((wp_p1 == rp) &amp; we)      gb &lt;= #1 1'b1;
  else
  if(re)              gb &lt;= #1 1'b0;
  
  endmodule
  </code></pre>