title: Physical or virtual addressing is used in processors x86/x86_64 for caching in the L1, L2 and L3?
body: <p>Which addressing is used in processors x86/x86_64 for caching in the L1, L2 and L3(LLC) - physical or virtual(using PT/PTE and <a href="http://en.wikipedia.org/wiki/Translation_Lookaside_Buffer" rel="noreferrer">TLB</a>) and somehow does <a href="http://en.wikipedia.org/wiki/Page_Attribute_Table" rel="noreferrer">PAT(page attribute table)</a> affect to it?</p>
  
  <p>And is there difference between the drivers(kernel-space) and applications(user-space) in this case?</p>
  
  <hr>
  
  <p>Short answer - Intel uses <strong>virtually indexed, physically tagged</strong> (VIPT) L1 caches: <a href="https://stackoverflow.com/questions/32979067/what-will-be-used-for-data-exchange-between-threads-are-executing-on-one-core-wi">What will be used for data exchange between threads are executing on one Core with HT?</a></p>
  
  <ul>
  <li>L1 - <strong>Virtual</strong> addressing (in <code>8-way</code> cache for define <code>Set</code> is required low <code>12 bits</code> which are the same in virt &amp; phys)</li>
  <li>L2 - <strong>Physical</strong> addressing (requires access to TLB for Virt-2-Phys)</li>
  <li>L3 - <strong>Physical</strong> addressing (requires access to TLB for Virt-2-Phys)</li>
  </ul>