title: Verilog signed vs unsigned samples and first
body: <p>Assuming I have a register <code>reg [15:0] my_reg</code>, which contains a 16-bit <strong>signed</strong> sample:</p>
  
  <p>How do I convert the sample from signed to unsigned? 
  I have read <a href="http://en.wikipedia.org/wiki/Signed_number_representations" rel="nofollow noreferrer">this Wikipedia article</a>, and am aware of the 2-bit complement for signed numbers, but how do I perform this conversion in Verilog efficiently?
  (I don't know if <code>my_reg</code> is positive or negatve, and it changes in every clock cycle = I receive a new sample on every positive clock edge).</p>
  
  <p>The ultimate goal (to add a little bit of context) is to implement a digital FPGA built-in automatic gain control (AGC).</p>
  
  <p><strong>EDIT:</strong> as suggested I have split the two questions in two different posts. See the other one <a href="https://stackoverflow.com/questions/24166295/verilog-bit-change-location"><strong>here</strong></a></p>