title: Direction mismatch and does not have driver warning in Vivado
body: <p>Hi I am getting these warnings and because of these warnings my code does not work as intented. To be specific here are the complete warnings below. By the way, since these 2 warnings are closely related to each other, I asked this question including both these warnings instead of asking 2 seperate questions.</p>
  
  <pre><code>[Synth 8-547] port direction mismatch for port 'douta' 
  [Synth 8-3848] Net data_out_ram in module/entity top_mod does not have 
  driver.
  </code></pre>
  
  <p>However, there are no need for these warnings. As far as I know driver means connection and this signal below has connections. I mean I do not understand the reason behind these warnings.</p>
  
  <pre><code>signal data_out_ram : std_logic_vector(11 downto 0); --declared in top_module
  
  U4: Block_Ram port map(addra =&gt; address_ram,
                         clka =&gt; clk,
                         dina =&gt; data_in_ram,
                         douta =&gt; data_out_ram, -- here
                         wea =&gt; write_enable);
  
  U5: Brightness_Contrast port map(clk_in =&gt; clk,
                                   operation =&gt; operation,
                                   pos_x =&gt; pos_x,
                                   pos_y =&gt; pos_y,
                                   data_in =&gt; data_out_ram, --here
                                   cursor_pos_x =&gt; cursor_pos_x,
                                   cursor_pos_y =&gt; cursor_pos_y,
                                   length =&gt; length,
                                   output_of_operation =&gt; output_of_operation,
                                   mode =&gt; mode);
  
  U6: Display port map(clk_in =&gt; clk,
                       rst =&gt; rst,
                       visible =&gt; visible,
                       data_r =&gt; data_r,
                       data_g =&gt; data_g,
                       data_b =&gt; data_b,
                       pos_x =&gt; pos_x,
                       pos_y =&gt; pos_y,
                       data_out_ram =&gt; data_out_ram, --here
                       length =&gt; length,
                       cursor_pos_x =&gt; cursor_pos_x,
                       cursor_pos_y =&gt; cursor_pos_y);
  
  component Display
  port(clk_in : in  std_logic ;
  rst     : in  std_logic;
  visible: in std_logic;
  data_r  : out std_logic_vector(COLOR_BIT-1 downto 0);
  data_g  : out std_logic_vector(COLOR_BIT-1 downto 0);
  data_b  : out std_logic_vector(COLOR_BIT-1 downto 0);
  pos_x  : in integer range 0 to 2047;
  pos_y  : in integer range 0 to 2047;
  display_data: in std_logic_vector(11 downto 0);
  length: in integer range 0 to PICTURE_WIDTH_HEIGHT;
  cursor_pos_x: in integer range 0 to PICTURE_WIDTH_HEIGHT;
  cursor_pos_y: in integer range 0 to PICTURE_WIDTH_HEIGHT
  );
  end component;
  
  component Block_Ram
  port(addra :in std_logic_vector(15 downto 0);
   clka : in std_logic;
   dina : in std_logic_vector(11 downto 0);
   douta: in std_logic_vector(11 downto 0);
   wea: in std_logic);
   end component;
  
  component Brightness_Contrast
  port (
  clk_in : in  std_logic;
  operation : in std_logic_vector(1 downto 0);
  pos_x: in integer range 0 to 2047 ;  
  pos_y: in integer range 0 to 2047 ; 
  data_in: in std_logic_vector(11 downto 0);
  cursor_pos_x: in integer range 0 to PICTURE_WIDTH_HEIGHT;
  cursor_pos_y: in integer range 0 to PICTURE_WIDTH_HEIGHT;
  length: in integer range 0 to PICTURE_WIDTH_HEIGHT;
  output_of_operation: out std_logic_vector(11 downto 0);
  mode: in std_logic
  );
  </code></pre>
  
  <p>Ram is constructed with block memory generator</p>
  
  <p>I really need help on this. How can I solve the issue here??</p>