title: Dividing and Modulus in verilog
body: <p>I'm creating an ALU in verilog just for the purpose of simulation. But I can't figure out how to divide two 16 bit inputs. A regular <code>A=B/C</code> doesn't work (where B,C is a <code>input[15:0]</code> and A is <code>output reg[15:0]</code>). Similarly with <code>A=B%C</code>.</p>
  
  <p>Would I have to separately implement a division circuit module? I understand division is a very complex operation and that would be the actual way to do it but I'm only doing it for simulation. Is there no shorter way to divide two 16bit inputs?</p>