title: how to predict the behaviour of a direct-mapped cache with alternating loads from two 512 byte arrays
body: <p>given this piece of code:</p>
  <blockquote>
  <pre><code>int x[2][128];
  int i;
  int sum=0;
  
  for(i=0; i&lt;128; i++){
     sum += x[0][i] * x[1][i];
  }
  </code></pre>
  <p>Assuming we execute this under the following conditions:</p>
  <ol>
  <li>sizeof(int) = 4.</li>
  <li>Array x begins at memory address 0x0 and is stored in row-major order.</li>
  <li>In each case below, the cache is initially empty.</li>
  <li>The only memory accesses are to the entries of the array x. All other variables are stored in registers.</li>
  </ol>
  <p>Given these assumptions,
  estimate the miss rates for the following cases: Assume the cache is
  512 bytes, direct-mapped, with 16-byte cache blocks.</p>
  </blockquote>
  <p>Given this info, I know that there are 32 sets (obtained from 512/16) in this cache. So the first set gets loaded with x[0][i] with 4 ints.</p>
  <ol>
  <li><p>But for the second part x[1][i], how do I know whether this load of the values here will override
  the first load of x[0][i], x[0][i+1], x[0][i+2], x[0][i+3] ? Or will the x[1][i], x[1][i+1],x[1][i+2],x[1][i+3] be stored in a different set to the first load of x[0][i]? I am confused about how the loading into the cache will be done for this piece of code.</p>
  </li>
  <li><p>What would be the miss rate of this?</p>
  </li>
  </ol>
  <p>Any help is appreciated please :)</p>