title: Signed and Unsigned Multiplication Problem in Verilog
body: <p>I have been working on approximate multiplication recently and I want to write a Verilog code for dynamic segment multiplication (DSM) . It suggest that you find the first index in you number which has a value of 1 and then take other 3 indexes next to it to form a 4 bit number that represent an 8 bit number then you should multiply these 4 bit numbers instead of 8 bits then some shifts to have the final result it helps a lot on hardware actually.. but my problem is about multiplication of these segments because sometimes they should be considered signed and some time unsigned I have the last 3 lines of my code: (a and b are input 8 bit numbers) and m1 and m2 are segments I wrote m,m2 as reg signed [3:0] and a and b as input signed [7:0]
  Here is my code:</p>
  <pre><code>    assign out = ({a[7],b[7]}==2'b11)||({a[7],b[7]}==2'b00) ? ($unsigned(m1)*$unsigned(m2)) &lt;&lt; (shift_m1+shift_m2) : 16'dz;
  assign out = ({a[7],b[7]}==2'b01) ? ($signed({1'b0,m1})*$signed(m2)) &lt;&lt; (shift_m1+shift_m2) : 16'dz;
  assign out = ({a[7],b[7]}==2'b10) ? ($signed(m1)*$signed({1'b0,m2})) &lt;&lt; (shift_m1+shift_m2) : 16'dz;
  </code></pre>
  <p>But in simulation Verilog always considers segments as unsigned and does unsigned multiplication even though I noted signed or unsigned mark...
  Can anyone help? I read all of the questions about this problem in stackoverflow and other places but still cannot solve this issue...</p>