title: How do the store buffer and Line Fill Buffer interact with each other?
body: <p>I was reading the MDS attack paper <a href="https://mdsattacks.com/files/ridl.pdf" rel="noreferrer">RIDL: Rogue In-Flight Data Load</a>. They discuss how the Line Fill Buffer can cause leakage of data. There is the <a href="https://stackoverflow.com/questions/56187269/about-the-ridl-vulnerabilities-and-the-replaying-of-loads">About the RIDL vulnerabilities and the &quot;replaying&quot; of loads</a> question that discusses the micro-architectural details of the exploit.</p>
  
  <p>One thing that isn't clear to me after reading that question is why we need a Line Fill Buffer if we already have a store buffer.</p>
  
  <p>John McCalpin discusses how the store buffer and Line Fill Buffer are connected in <a href="https://software.intel.com/en-us/forums/intel-moderncode-for-parallel-architectures/topic/843581" rel="noreferrer"> How does WC-buffer relate to LFB?</a> on the Intel forums, but that doesn't really make things clearer to me.</p>
  
  <blockquote>
    <p>For stores to WB space, the store data stays in the store buffer until after the retirement of the stores.  Once retired, data can written to the L1 Data Cache (if the line is present and has write permission), otherwise an LFB is allocated for the store miss.  The LFB will eventually receive the "current" copy of the cache line so that it can be installed in the L1 Data Cache and the store data can be written to the cache.   Details of merging, buffering, ordering, and "short cuts" are unclear....  One interpretation that is reasonably consistent with the above would be that the LFBs serve as the cacheline-sized buffers in which store data is merged before being sent to the L1 Data Cache.  At least I think that makes sense, but I am probably forgetting something....</p>
  </blockquote>
  
  <p>I've just recently started reading up on out-of-order execution so please excuse my ignorance. Here is my idea of how a store would pass through the store buffer and Line Fill Buffer.</p>
  
  <ol>
  <li>A store instruction get scheduled in the front-end. </li>
  <li>It executes in the store unit.</li>
  <li>The store request is put in the store buffer (an address and the data)</li>
  <li>An invalidate read request is sent from the store buffer to the cache system</li>
  <li>If it misses the L1d cache, then the request is put in the Line Fill Buffer</li>
  <li>The Line Fill Buffer forwards the invalidate read request to L2</li>
  <li>Some cache receives the invalidate read and sends its cache line</li>
  <li>The store buffer applies its value to the incoming cache line</li>
  <li>Uh? The Line Fill Buffer marks the entry as invalid</li>
  </ol>
  
  <hr>
  
  <p><a href="https://i.stack.imgur.com/PmR2H.png" rel="noreferrer"><img src="https://i.stack.imgur.com/PmR2H.png" alt="enter image description here"></a></p>
  
  <h3>Questions</h3>
  
  <ol>
  <li>Why do we need the Line Fill Buffer if the store buffer already exists to track outsanding store requests?</li>
  <li>Is the ordering of events correct in my description?</li>
  </ol>