title: Can't compare = in VHDL with std_logic_vector types
body: <p>I've tried to work around this and have failed.  Strangely enough, the exact same code in another file of my project seems fine, and I'm using the same libraries.. What's wrong?</p>
  
  <p>Line of code (and the generate that it's inside)</p>
  
  <pre><code>generate_decounter_ppl: for i in 0 to ppl - 1 generate
  block_decounter_load(i) &lt;= (ppl_stage_count = conv_std_logic_vector((i),log2(ppl)));
  </code></pre>
  
  <p>Error:</p>
  
  <pre><code>Line 175: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "="
  </code></pre>
  
  <p>Context:</p>
  
  <pre><code>ppl : integer := 18;    
  
  ppl_stage_count : in std_logic_vector(log2(ppl)-1 downto 0);
  
  signal block_decounter_load : std_logic_vector(ppl -1 downto 0); 
  
  
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  </code></pre>