title: VHDL: Is it possible to define a generic type with records?
body: <p>I am trying to define a complex type (i.e, a type that consists of both a real and imaginary part) and am trying to find out a way to make it generic.</p>
  
  <pre><code>This my current static code:
  
    type complex_vector is record
      Re : signed(15 downto 0);
      Im : signed(15 downto 0);
    end record;
  </code></pre>
  
  <p>Now I wonder whether there is a way to make this generic, in in other word something like:</p>
  
  <pre><code>  type complex_vector (Generic: Integer := WIDTH) is record
      Re : signed(WIDTH downto 0);
      Im : signed(WIDTH downto 0);
    end record;
  </code></pre>
  
  <p>I tried to google for a solution as well as going through my books, but I cannot find any solution. Is there really none? Without records it is possible to wright something like this:</p>
  
  <pre><code>type blaaa is array (NATURAL range &lt;&gt;) of STD_LOGIC;
  </code></pre>
  
  <p>Thanks for any input</p>
  
  <p>EDIT:</p>
  
  <p>Or could I do something like the following?</p>
  
  <pre><code>type complex_primitives is (re, im);
  type complex_vector is array (re to im) of signed(natural range &lt;&gt;);
  </code></pre>
  
  <p>The compiler complains though..</p>