title: Accessing Verilog genvar generated instances in simulation code
body: <p>This is a Verilog releated question. I am working with XILINX ISE as a dev environment.</p>
  
  <p>I am trying to access variables in the simulation that are automatically generated using genvar but I am receiving the following error -> HDLCompiler:71</p>
  
  <p>Problem Example:</p>
  
  <pre><code>genvar i;
  
  generate
  
  for(i=0; i &lt; N; i=i+1)
  
  begin:Sys_Modules
  
    TypeXModule #(.width(10)) xmod(.dataY(dataY)));
  
  end
  
  endgenerate 
  </code></pre>
  
  <p>When I ran synthesis or simulation I can see that Sys_Modules[0..N-1].xmod instances are created.</p>
  
  <p>When I try to add a line to the simulation accessing the Sys_Modules array:</p>
  
  <p>Sys_Modules[i].xmod.dataY</p>
  
  <p>I get the following error:</p>
  
  <p>HDLCompiler:71 dataY is not declared under prefix xmod</p>
  
  <p>Is there any way to access automatically generated values in the simulation?</p>
  
  <p>Thanks!</p>