title: How to connect top module's input port to a components output port?
body: <p>I'm using Xilinx ISE 13.2.</p>
  
  <p>I'm very new to VHDL and I'm having troubles connecting components. I have a top module and a component (defined in another file) defined as below:</p>
  
  <pre><code>entity kcpsm3_int_test is
      Port (      number_in  : in std_logic_vector(3 downto 0);
                      number_out  : out std_logic_vector(3 downto 0);
                      button      : in std_logic;
             interrupt_event : in std_logic;
                         clk : in std_logic);
      end kcpsm3_int_test;
  
  component debounce_logic
  Port ( clk   : in  STD_LOGIC;
         btn_in  : in  STD_LOGIC;
         btn_out : out  STD_LOGIC);
  end component;
  
  --port
  db: debounce_logic
   port map(
              clk     =&gt; clk,
          btn_in  =&gt; button,
          btn_out  =&gt; btn_out);
  </code></pre>
  
  <p>I also defined a signal btn_out to connect those two. I can see how two other components (a processor and a ROM) are connected, but I could not manage to connect these two. I think  I need to port the top module somehow but I don't know how to and I'm pretty much stuck here, how can I proceed? How can I connect the btn_out, output of debounce logic, to the input of the top-module??</p>