title: using assign statement for `define statement
body: <p>I am using assign statement of verilog for assigning `define as below in my driver module.</p>
  
  <pre><code>`define  SPI_MASTER_P_IF spi_vif.spi_master_p.spi_master_p_cb
  
  `define SPI_MASTER_N_IF spi_vif.spi_master_n.spi_master_n_cb
  
  `define SPI_MASTER_IF
  
  class my_driver extends uvm_driver;
  
    assign `SPI_MASTER_IF = (if_posedge)?`SPI_MASTER_P_IF: `SPI_MASTER_N_IF;
  
  endclass
  </code></pre>
  
  <p>When I compile I am facing the error as "near "assign": syntax error, unexpected assign, expecting function or task" </p>
  
  <p>What is the proper way to do this assignment?</p>