title: Verilog module for a smoke detector and a buzzer
body: <p>I have Altera DE2-115 FPGA and I try to self-learn Verilog. I decided to make a smoke detector and whenever it smells smoke the buzzer rings (<em>the smoke detector outputs a digital signal</em>).</p>
  
  <p>Here is my trial :</p>
  
  <pre><code>module fire(flag,clock,reset,fire,fire_state,firealarm);
    input        clock, reset, flag, fire;
    output [2:0] fire_state;
    output       firealarm; 
  
    wire         fire;
    reg    [2:0] fire_state;
  
    assign firealarm = (fire_state == 1) ? (flag ? 0 : 1) : 0;
  
    always @ (posedge clock)
      fire_state&lt;= fire ? 1: 0;
  
  end module
  </code></pre>
  
  <p>But it doesn't run and I think there are a lot of logic errors in this code, any help please? :)</p>