title: Verilog generate statement with always@(*) block
body: <p>I have this generate block below which I think should work, but I am seeing issues with the <code>always @(*)</code> part under the <code>else</code> block. When using VCS, <code>temp_in[i+1][j]</code> is assigned 'x' always. I expect it to be set to '0'. If I instantiate a module/gate instead of always block, like I did for the <code>if</code> part, then it works correctly. Googling for the right syntax for using foreach, generate, always and if within a single block does not yield any useful results. I know the fix is a minor change but I am not that familiar with all the language constructs, so I will appreciate any help.</p>
  
  <p><code>ceil()</code> is a function which returns an integer. It uses only parameters which are fixed at compile time, so I expect the loop unrolling to happen correctly.</p>
  
  <pre><code>  genvar i, j, k;
    generate
      for (i = 0; i &lt; NUM_STAGES; i = i + 1) begin:gen_stage
        for (j = 0; j &lt; (TOTAL_LENGTH/(2**(i+1))); j = j + 1) begin:gen_or
          if(j &lt; ceil(i)) begin
            for (k = 0; k &lt; CPU_DATA_WIDTH; k = k + 1) begin:gen_bit
              msw_mem_out_mux_bit_or U_msw_mem_out_mux_bit_or (
                .in_1 (temp_in[i][2*j][k]),
                .in_2 (temp_in[i][(2*j)+1][k]),
                .out  (temp_in[i+1][j][k])
              );
            end
          end else begin
            always @(*) begin
              temp_in[i+1][j] = {CPU_DATA_WIDTH{1'b0}};
            end
          end
        end
      end
    endgenerate
  </code></pre>