title: How to convert Signed Binary to Integer in Verilog?
body: <p>I am trying to convert signed binary numbers to integer in verilog for synthesis to display, I have a couple of questions. Below is my code, </p>
  
  <pre><code>.....
  if(acc[i][j]&gt;10)               //acc is a 2d register
  
  begin
    m_reg &lt;= j-const_10;        // const_10 is 16'b0000000000001010
    m_int &lt;= m_reg;              
    $display("Current value of M(bits)=%b",m_reg);
    $display("Current value of M(int)=%d",m_int);
  end
  else
  ....
  </code></pre>
  
  <ol>
  <li><p>j can be less than 10, meaning m_reg can be negative. In that case, I am assuming m_reg will give me a signed binary negative number.</p></li>
  <li><p>If it does, how do I convert it to an integer to display because I guess m_int = m_reg will give me only unsigned. </p></li>
  </ol>