title: Using entities from another file in VHDL
body: <p>How does one "include" another file from a workspace in VHDL and then use an architecure of an entity that is implemented in another file? Here is what I have but it is not right:</p>
  
  <p><strong>updated code:</strong></p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  library Part2;
  use Part2.all;
  
  
  entity problem4Gates is
      port(X,Clk: in std_logic; Q: out std_logic_vector(2 downto 0)) ;
  end entity problem4Gates;  
  
  architecture behavioral OF problem4Gates IS  
  
  for all: yourGateName use entity  Part2.JKflipFlop(jkFF); --port (J, K, Clk, Preset, Clear : in std_logic; Q, Qn : Buffer std_logic) --JKflipFlop --jkFF    
  signal s0, ns0, s1, ns1, s2, na2, ps0, ps1, ps2, restart : std_logic :='0';
  begin
      process(clk)
      begin                  
           yourgatename( ns0, clk, '0', restart, Q(0), ns0 );
      end process;
  end architecture behavioral;
  </code></pre>
  
  <p>I now get 2 errors:</p>
  
  <pre><code># Error: COMP96_0078: Part3.vhd : (13, 10): Unknown identifier "yourGateName".
  # Error: COMP96_0134: Part3.vhd : (13, 10): Cannot find component declaration.
  </code></pre>