title: How to pass a variable to the define macro used for accessing the path in system verilog
body: <p>I am using a define macro to set the path for a module,
  ie, 
  `define DUT_PATH(CH) dut_top.u_channel_```CH``_mode</p>
  
  <p>and using this define macro in a module where we are passing the channel number ,</p>
  
  <p>module channel_oper # (int channel_num = 0)
  (
  input logic addr_base;
  ) ;</p>
  
  <p>assign addr_base = `DUT_PATH(channel_num).addr_base ;</p>
  
  <p>endmodule</p>
  
  <p>In the top file , we are calling the module as</p>
  
  <p>channel_oper(3);  //channel_oper(channel_num)</p>
  
  <p>where I expect the output of the addr_base to be  <strong>dut_top.u_channel_3_mode.addr_base</strong> , but I am getting the value assigned as dut_top.u_channel_<strong>channel_num</strong>_mode.addr_base and cross dereferenece error .</p>
  
  <p>Can you please provide me a solution or any suggestions for this to use a parameterised vaiable to the define macro. </p>
  
  <p>In this case, genvar or generate block could not be used as this is not used for any manipulation . This is used to access the different path for the different channel number and we are passing the channel number from the top module . The module channel operation takes the channel number from the parameter and goes to that particular channel path and takes the vaiable. </p>