title: Looking for verilog 2001 module declaration grammar
body: <p>I can find several v2k full grammars with google -- but either I am losing my mind or they are all broken in the same way with regard to port declarations.
  Example input:</p>
  
  <pre><code>module foo ( 
      input x, 
       output [2:0] y);
  endmodule;
  </code></pre>
  
  <p>I can't find a grammar which will parse that syntax, but they will accept things like this
  as a 'port' in the list_of_port:</p>
  
  <pre><code>         { name[3:0], name2[2:0]} 
  .. or ..   .name( othername )
  </code></pre>
  
  <p>I.e. things I expect to see in the grammar for a module instantiation port binding are supplied for a module port declaration.</p>
  
  <p>Examples</p>
  
  <p><a href="http://www.externsoft.ch/download/verilog.html#module_declaration" rel="nofollow">http://www.externsoft.ch/download/verilog.html#module_declaration</a></p>
  
  <p><a href="http://www.syncad.com/VeriLogger_bnf_Syntax_Verilog_2001.htm#list_of_ports" rel="nofollow">http://www.syncad.com/VeriLogger_bnf_Syntax_Verilog_2001.htm#list_of_ports</a></p>
  
  <p>I guess I can look into the icarus source, or Perl::Verilog. I'm hoping to get a confirmation that the grammars above are broken, though -- or can someone point out what I'm missing if not. A source for a correct grammar would be great...</p>