title: How to automatically simulate the top-level VHDL entity with ModelSim?
body: <p>When calling the <code>vsim</code> command, how can I make ModelSim automatically use the top-level VHDL entity (or entities)? I'm writing a generic script for running VHDL simulations.</p>
  
  <p>Currently I'm doing the following to compile and simulate:</p>
  
  <pre><code>vcom design.vhd testbench.vhd
  vsim -c -do "onElabError resume; run -all; exit" MY_TB
  </code></pre>
  
  <p>How can I make it so that ModelSim automatically simulates <code>MY_TB</code> without explicitly specifying it.</p>
  
  <p>Automatically using the top-level module(s) is possible with Verilog:</p>
  
  <pre><code>vlog -writetoplevels my.tops design.v testbench.v
  vsim -c -do "onElabError resume; run -all; exit" -f my.tops
  </code></pre>