title: How to create port map that maps a single signal to 1 bit of a std_logic_vector?
body: <p>I am designing some hardware using VHDL. My design requires the use of a 12-bit ripple counter that will utimately get connected as shown in the schematic screenshot below.</p>
  
  <p><a href="https://i.stack.imgur.com/vDtA1.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vDtA1.png" alt="ripple counter schematic"></a></p>
  
  <p>I found an existing entity &amp; architecture for a ripple counter from online that I have decided should be suitable for my design. Here it is, in case it is useful in helping answer my question. </p>
  
  <pre><code>entity ripple_counter is
      generic (
          n : integer := 12
      );
      port (
          clk   : in std_logic;
          clear : in std_logic;
          dout  : out std_logic_vector(n-1 downto 0)
      );
  end ripple_counter;
  
  architecture behavioral of ripple_counter is
  
      signal clk_i, q_i : std_logic_vector(n-1 downto 0);
  
  begin
      clk_i(0) &lt;= clk;
      clk_i(n-1 downto 1) &lt;= q_i(n-2 downto 0);
  
      gen_cnt: for i in 0 to n-1 generate
          dff: process(clear, clk_i)
          begin
              if (clear = '1') then
                  q_i(i) &lt;= '1';
              elsif (clk_i(i)'event and clk_i(i) = '1') then
                  q_i(i) &lt;= not q_i(i);
              end if;
              end process dff;
      end generate;
      dout &lt;= not q_i;
  end behavioral;
  </code></pre>
  
  <p>One will see that the ripple counter entity uses a n-bit (12-bit in this case) std_logic_vector for it's output. But, only two of the Q* outputs get connected. The ripple counter's component and port map declarations have been created as follows. Note that u22d_out, u21b_out and, u26_q12_out are all signals that have been defined in the same structural architecture as the ripple counter's component and port map. Also, q10 is an output of the system.</p>
  
  <pre><code>component ripple_counter is
      generic (
          n : integer := 12
      );
      port (
          clk   : in std_logic;
          clear : in std_logic;
          dout  : out std_logic_vector(n-1 downto 0)
      );
  end component;
  
  u26: ripple_counter port map (
      clk =&gt; u22d_out,
      clear =&gt; u21b_out,
      dout(11) =&gt; u26_q12_out,
      dout(9) =&gt; q10
  );
  </code></pre>
  
  <p>When I attempt to run my design I get the following errors...</p>
  
  <blockquote>
    <h1>Error: [42972]: "c:/somefilepath/somefilename.vhd", line 493: Incomplete sub-element association for formal dout</h1>
    
    <h1>Error: [42604]: "c:/somefilepath/somefilename.vhd", line 489: Port and Port Map does not match</h1>
    
    <h1>Error: [40008]: HDL analysis failed.</h1>
  </blockquote>
  
  <ul>
  <li>Line 493 is the line that reads <strong>dout(9) => q10</strong>. </li>
  <li>Line 489 is the line that reads <strong>u26: ripple_counter port map</strong>.</li>
  </ul>
  
  <p>I am unsure if this is a syntax error or if it is a functional issue. How can I map specific bits of a vector to a single signal?</p>