title: Verilog promote one-bit wire to 64-bit bus
body: <p>I have a 64-bit bus, and I would like to &amp; every bit of the bus with a one-bit wire. What's the best way to do this? I would like to do something like below, but it doesn't seem to work as expected.</p>
  
  <pre><code>logic [63:0] bus, other_bus;
  logic signal;
  ...
  bus = other_bus &amp; signal;
  </code></pre>