title: Is there a reason to initialize (not reset) signals in VHDL and Verilog?
body: <p>I have never initialized signals. That way any signal missing a reset or assignment would be unknown or initialized. In some reference code they have initialization. This defeats what I wish. Also since intialization isn't synthesizable, there could be a simulation/synthesis mismatch.</p>
  
  <p>Is there any reason to initialize signals in this case?</p>
  
  <p>EDIT 6/17/11: As @Adam12 asked, this is for both storage (Verilog reg) and combinatorial (wire) elements.</p>