title: Array of systemverilog interfaces with different inputs
body: <p>I would like to instantiate an array of systemverilog interfaces where each array element uses a different input.</p>
  
  <p>If all the elements use the same input, then the instantiation is simple:</p>
  
  <pre><code>x_if x_IF[`NUM_INTERFACES](clk);
  </code></pre>
  
  <p>Here, if <code>`NUM_INTERFACES</code> is <code>2</code>, then the <code>clk</code> input goes to both <code>x_IF[0]</code> and <code>x_IF[1]</code>.</p>
  
  <p>But if I also have </p>
  
  <pre><code>reg clk[`NUM_INTERFACES];
  </code></pre>
  
  <p>how do I instantiate <code>x_IF</code> so that <code>clk[0]</code> is input to <code>x_IF[0]</code> and <code>clk[1]</code> is input to <code>x_IF[1]</code>?</p>
  
  <p>This is a simple example; I am looking forward to implement this in some sort of loop (probably using <code>generate</code>) for an array of 12 interfaces.</p>