title: How to test the current instance name?
body: <p>I need to use the current instance name (full hierarchical name) in a generate if condition:</p>
  
  <pre><code>generate
     if (current_instance_name() == "a.b.c.foo")
     ...
  </code></pre>
  
  <p>Is there any way to do that in Verilog or SystemVerilog?
  I know %m, but it only allows to print the instance name.</p>
  
  <p>Thanks.</p>