title: First-In-First-Out (FIFO) using verilog
body: <p>Hello i really need help with this cuz its driving me crazy im using Spartan 3E and below is the .v file for FIFO and after that .ucf file ... im just wondering why i cant write/read to the memory even though i get no errors when i generate the binary file and program the fpga!!</p>
  
  <hr>
  
  <pre><code>module fifo (
    input [3:0] data_in, 
    input clk, rst, rd, wr, 
    output empty, full, 
    output reg [3:0] fifo_cnt,
    output reg [3:0] data_out
  ); 
  
  reg [3:0] fifo_ram[0:7];
  reg [2:0] rd_ptr, wr_ptr;
  
  assign empty = (fifo_cnt==0);
  assign full = (fifo_cnt==8);
  
  always @( posedge clk ) 
  begin: write
  if(wr &amp;&amp; !full) fifo_ram[wr_ptr] &lt;= data_in;
  else if(wr &amp;&amp; rd) fifo_ram[wr_ptr] &lt;= data_in;
  end
  
  always @( posedge clk ) 
  begin: read
  if(rd &amp;&amp; !empty)
    data_out &lt;= fifo_ram[rd_ptr];
  else if(rd &amp;&amp; wr &amp;&amp; empty) 
    data_out &lt;= fifo_ram[rd_ptr];
  end
  
  always @( posedge clk ) 
  begin: pointer
    if( rst ) 
    begin 
      wr_ptr &lt;= 0; 
      rd_ptr &lt;= 0;
    end 
    else 
    begin
      wr_ptr &lt;= ((wr &amp;&amp; !full)||(wr &amp;&amp; rd)) ? wr_ptr+1 : wr_ptr;
      rd_ptr &lt;= ((rd &amp;&amp; !empty)||(wr &amp;&amp; rd)) ? rd_ptr+1 : rd_ptr;
    end 
  end
  
  always @( posedge clk ) 
  begin: count 
    if( rst ) 
      fifo_cnt &lt;= 0;
    else 
    begin
      case ({wr,rd})
        2'b00 : fifo_cnt &lt;= fifo_cnt;
        2'b01 : fifo_cnt &lt;= (fifo_cnt==0) ? 0 : fifo_cnt-1; 
        2'b10 : fifo_cnt &lt;= (fifo_cnt==8) ? 8 : fifo_cnt+1; 
        2'b11 : fifo_cnt &lt;= fifo_cnt;
        default: fifo_cnt &lt;= fifo_cnt;
      endcase 
    end
  end
  
  
  endmodule  
  </code></pre>
  
  <hr>
  
  <pre><code># ==== Clock Source ==== 
  NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33; 
  NET "clk" PERIOD = 5ns HIGH 40%; 
  
  
  NET "rst"     LOC "D18" | IOSTANDARD = LVTTL | PULLDOWN ;  
  NET "wr"      LOC "H13" | IOSTANDARD = LVTTL | PULLDOWN ;  
  NET "rd"      LOC "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
  
  
  # ==== Slide Switches (SW) ==== 
  NET "data_in&lt;0&gt;" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; #// SW1 
  NET "data_in&lt;1&gt;" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ; #// SW2
  NET "data_in&lt;2&gt;" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; #// SW3
  NET "data_in&lt;3&gt;" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ; #// SW4
  
  
  # ==== Discrete LEDs (LED) ==== 
  NET "data_out&lt;3&gt;" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
  NET "data_out&lt;2&gt;" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
  NET "data_out&lt;1&gt;" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
  NET "data_out&lt;0&gt;" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; 
  
  NET "empty"   LOC "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
  NET "full"    LOC "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
  </code></pre>