title: Can signal in std_logic have other value than 0 and 1?
body: <p>I've been learning VHDL (mostly on my own) during my studies. I've heard that I should always cover all possible situations in <em>case</em> or <em>if</em> statements. My question is: is it technically possible for <em>std_logic</em> internal signal to have any other value than 0 or 1?</p>
  <p>For example, is this possible:</p>
  <pre><code>signal or_gate : std_logic;
  
  ...
  or_gate &lt;= input1 or input2;
  ...
  if(or_gate = '1') then
  --led blinks fast
  elsif(or_gate = '0') then
  --led blinks slow
  else
  --led off
  end if;
  </code></pre>
  <p>or there can only be led blinks or led off?</p>