title: Error (10395): VHDL Conditional Signal Assignment error at (146): conditional waveforms must have same number of elements
body: <p>Error (10395): VHDL Conditional Signal Assignment error at vga.vhd(146): conditional waveforms must have same number of elements.
  in this line show me error  </p>
  
  <pre><code>R&lt;=intensity WHEN red_switch='0' AND dena='1' ELSE (OTHERS=&gt;'1');
  </code></pre>
  
  <p>I really don't know what's wrong vhdl Altera code error but it didn't solve my problem. thanks in advance.</p>
  
  <pre><code> LIBRARY ieee;
   USE ieee.std_logic_1164.all;
   USE ieee.std_logic_arith.all;
   LIBRARY lpm;
   USE lpm.lpm_components.all;
   ----------------------------------------------------------
   ENTITY vga IS
   GENERIC (
   Ha: INTEGER := 96; --Hpulse
   Hb: INTEGER := 144; --Hpulse+HBP
   Hc: INTEGER := 784; --Hpulse+HBP+Hactive
   Hd: INTEGER := 800; --Hpulse+HBP+Hactive+HFP
   Va: INTEGER := 2; --Vpulse
   Vb: INTEGER := 35; --Vpulse+VBP
   Vc: INTEGER := 515; --Vpulse+VBP+Vactive
   Vd: INTEGER := 525); --Vpulse+VBP+Vactive+VFP
   PORT (
   clk: IN STD_LOGIC; --50MHz in our board
   red_switch, green_switch, blue_switch: IN STD_LOGIC;
   pixel_clk: BUFFER STD_LOGIC;
   Hsync, Vsync: BUFFER STD_LOGIC;
   R, G, B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
   nblanck, nsync : OUT STD_LOGIC);
   END vga;
   ----------------------------------------------------------
   ARCHITECTURE vga OF vga IS
   SIGNAL Hactive, Vactive, dena: STD_LOGIC;
   SIGNAL address: STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL intensity: STD_LOGIC_VECTOR(9 DOWNTO 0);
   BEGIN
   -------------------------------------------------------
   --Part 1: CONTROL GENERATOR
   -------------------------------------------------------
   --Static signals for DACs:
   nblanck &lt;= '1'; --no direct blanking
   nsync &lt;= '0'; --no sync on green
   --Create pixel clock (50MHz-&gt;25MHz):
   PROCESS (clk)
   BEGIN
   IF (clk'EVENT AND clk='1') THEN
   pixel_clk &lt;= NOT pixel_clk;
   END IF;
   END PROCESS;
   --Horizontal signals generation:
   PROCESS (pixel_clk)
   VARIABLE Hcount: INTEGER RANGE 0 TO Hd;
   BEGIN
   IF (pixel_clk'EVENT AND pixel_clk='1') THEN
   Hcount := Hcount + 1;
   IF (Hcount=Ha) THEN
   Hsync &lt;= '1';
   ELSIF (Hcount=Hb) THEN
   Hactive &lt;= '1';
   ELSIF (Hcount=Hc) THEN
   Hactive &lt;= '0';
   ELSIF (Hcount=Hd) THEN
   Hsync &lt;= '0';
   Hcount := 0;
   END IF;
   END IF;
    END PROCESS;
   --Vertical signals generation:
   PROCESS (Hsync)
   VARIABLE Vcount: INTEGER RANGE 0 TO Vd;
   BEGIN
   IF (Hsync'EVENT AND Hsync='0') THEN
   Vcount := Vcount + 1;
   IF (Vcount=Va) THEN
   Vsync &lt;= '1';
   ELSIF (Vcount=Vb) THEN
   Vactive &lt;= '1';
   ELSIF (Vcount=Vc) THEN
   Vactive &lt;= '0';
   ELSIF (Vcount=Vd) THEN
   Vsync &lt;= '0';
   Vcount := 0;
   END IF;
   END IF;
   END PROCESS;
   ---Display enable generation:
   dena &lt;= Hactive AND Vactive;
   -------------------------------------------------------
   --Part 2: IMAGE GENERATOR
   -------------------------------------------------------
       PROCESS (Hsync, Vsync, Vactive, dena, red_switch,
       green_switch, blue_switch)
       VARIABLE line_counter: INTEGER RANGE 0 TO Vc;
       BEGIN
       IF (Vsync='0') THEN
       line_counter := 0;
       ELSIF (Hsync'EVENT AND Hsync='1') THEN
       IF (Vactive='1') THEN
       line_counter := line_counter + 1;
       END IF;
       END IF;
       IF (dena='1') THEN
       IF (line_counter=1) THEN
       R &lt;= (OTHERS =&gt; '1');
       G &lt;= (OTHERS =&gt; '0');
       B &lt;= (OTHERS =&gt; '0');
       ELSIF (line_counter&gt;1 AND line_counter&lt;=3) THEN
       R &lt;= (OTHERS =&gt; '0');
       G &lt;= (OTHERS =&gt; '1');
        B &lt;= (OTHERS =&gt; '0');
       ELSIF (line_counter&gt;3 AND line_counter&lt;=6) THEN
       R &lt;= (OTHERS =&gt; '0');
       G &lt;= (OTHERS =&gt; '0');
       B &lt;= (OTHERS =&gt; '1');
       ELSE
       R &lt;= (OTHERS =&gt; red_switch);
       G &lt;= (OTHERS =&gt; green_switch);
       B &lt;= (OTHERS =&gt; blue_switch);
       END IF;
      ELSE
       R &lt;= (OTHERS =&gt; '0');
       G &lt;= (OTHERS =&gt; '0');
       B &lt;= (OTHERS =&gt; '0');
       END IF;
       END PROCESS;
  --END vga;
   -------------------------------------------
   --ROM instantiation:
   myrom: lpm_rom
   GENERIC MAP (
   lpm_widthad =&gt; 9, --address width
   lpm_outdata =&gt; "UNREGISTERED",
   lpm_address_control =&gt; "REGISTERED",
   lpm_file =&gt; "pic_6.mif", --data file
   lpm_width =&gt; 10) --data width
   PORT MAP (
   inclock=&gt;NOT pixel_clk, address=&gt;address, q=&gt;intensity);
   --Create address (row number):
   PROCESS (Vsync, Hsync)
   VARIABLE line_counter: INTEGER RANGE 0 TO Vd;
   BEGIN
   IF (Vsync='0') THEN
   line_counter := 0;
   ELSIF (Hsync'EVENT AND Hsync='1') THEN
   IF (Vactive='1') THEN
   line_counter := line_counter + 1;
   END IF;
   END IF;
   address &lt;= conv_std_logic_vector(line_counter, 9);
   END PROCESS;
  -- --Assign color values to R/G/B:
   R&lt;=intensity WHEN red_switch='0' AND dena='1' ELSE (OTHERS=&gt;'1');
   G&lt;=intensity WHEN green_switch='0' AND dena='1' ELSE (OTHERS=&gt;'1');
   B&lt;=intensity WHEN blue_switch='0' AND dena='1' ELSE (OTHERS=&gt;'1');
   END vga;
  </code></pre>