title: VHDL 3-bit sequence counter with T-Flip Flops
body: <p>I am new to VHDL and I can't see a solution to my problem. I want to find a VHDL code for my 3-bit sequence counter with T Flip Flop's which goes: ..,0,4,5,7,6,2,3,1,0,... I made a truth table and minimized equations for T_FF like so: </p>
  
  <p><a href="https://i.stack.imgur.com/9Lqq4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/9Lqq4.png" alt="enter image description here"></a></p>
  
  <p>T0=Q2 xor Q1 xor Q0;</p>
  
  <p>T1=(Q2 xor Q1) and Q0;</p>
  
  <p>T2= not(Q2 xor Q1) and Q0;</p>
  
  <p>Then I draw the circuit:</p>
  
  <p><a href="https://i.stack.imgur.com/0SXAN.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/0SXAN.png" alt="enter image description here"></a></p>
  
  <p>Last VHDL:</p>
  
  <p>T-FLIP FLOP</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  entity tff is
    port(
          clk: in std_logic;
          reset: in std_logic;
          t: in std_logic;
          q: out std_logic
        );
  end tff;
  
  architecture behave of tff is
   -- signal q_reg: std_logic; --v registru
  --  signal q_next: std_logic; --naslednje stanje
  begin
   process
  variable x: std_logic:='0';
   begin
  wait on clk;
         if (clk' event and clk = '1') then
      if reset='1' then
      x:='0';
      else x:=t;
  end if;
  end if;
  if (t = '1') then
  q&lt;=not x;
  else 
  q&lt;=x;
  end if;
  end process;
  
  end behave;
   -----------------------------------------------------------
  </code></pre>
  
  <p>Gray counter</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  entity tff_gray is
    port(
          clk: in std_logic;
          reset: in std_logic;
          q: inout std_logic_vector (2 downto 0)
          --q: out std_logic
        );
  end tff_gray;
  
  architecture behave of tff_gray is
  component tff is
    port(
          clk: in std_logic;
          reset: in std_logic;
          t: in std_logic;
          q: out std_logic
        );
  end component;
  
    signal i0,i1,i2: std_logic; --v registru
    --signal q_next: std_logic; --naslednje stanje
  begin
  i0&lt;=q(0) xor q(1) xor q(2);
  i1&lt;=q(0) and (q(1) xor q(2));
  i2&lt;=q(0) and not(q(1) xor q(2));
      Tff0: tff port map(clk, reset, i0, Q(0));
      Tff1: tff port map(clk, reset, i1, Q(1));
      Tff2: tff port map(clk, reset, i2, Q(2));
  end behave;
  </code></pre>
  
  <p>I wrote this bunch of code of what I found over the internet. When I compiled my code it all went through without a problem but the simulation is wrong. I went through this code a lot of times and I don't know what is wrong. If anyone has any idea please share. 
  I have mostly watched this <a href="https://www.altera.com/support/support-resources/design-examples/design-software/vhdl/vhd-gray-counter.html" rel="nofollow noreferrer">altera</a> site and LBEbooks on YouTube.</p>