title: 4-to-1 Multiplexer that implements addition, inversion, AND, OR gates on Verilog
body: <p>I just started learning Verilog this semester and I just got stuck on a task to create a Verilog module that has uses multiplexed to do different operations on 2 8-bit inputs. The below is the Verilog code that I wrote, I am getting several errors that I do not understand. Please help!</p>
  
  <pre><code>module eightbit_palu( input[7:0] a, input[7:0] b, input[1:0] sel, output[7:0] f, output ovf ); 
  
  reg f, ovf; 
      always @ (a , b, sel)
  
      case (sel)
          0 : f = a + b;
              ovf = f[8]^f[7]; 
  
          1 : f[0] = ~b[0]; 
              f[1] = ~b[1]; 
              f[2] = ~b[2]; 
              f[3] = ~b[3]; 
              f[4] = ~b[4]; 
              f[5] = ~b[5]; 
              f[6] = ~b[6]; 
              f[7] = ~b[7];
  
          2 : f[0] = a[0]&amp;b[0]; f[1] = a[1]&amp;b[1]; f[2] = a[2]&amp;b[2]; f[3] = a[3]&amp;b[3]; f[4] = a[4]&amp;b[4]; 
               f[5] = a[5]&amp;b[5]; f[6] = a[6]&amp;b[6]; f[7] = a[7]&amp;b[7]; 
  
          3 : f[0] = a[0]|b[0]; f[1] = a[1]|b[1]; f[2] = a[2]|b[2]; f[3] = a[3]|b[3]; f[4] = a[4]|b[4]; 
               f[5] = a[5]|b[5]; f[6] = a[6]|b[6]; f[7] = a[7]|b[7];
      endcase
  
  endmodule
  </code></pre>
  
  <p>The errors being displayed by the simulators are:</p>
  
  <blockquote>
    <p>8: syntax error<br>
    10: error: Incomprehensible case expression.<br>
    11: syntax error<br>
    19: error: Incomprehensible case expression.<br>
    19: syntax error<br>
    22: error: Incomprehensible case expression.<br>
    22: syntax error  </p>
  </blockquote>