title: Verilog always block with pushbutton activation, FSM
body: <p>I'm writing some <code>Verilog</code> code to be programmed on an <em>Altera Cyclone II FPGA</em> board, and I have an <code>always</code> block which should be activated on the press of a key switch:</p>
  
  <pre><code>reg START;
  
  ...
  ...
  
  always @ (negedge key[3]) begin
      if (START != 1) START = 1;
  end
  </code></pre>
  
  <p>I'm writing a program for a finite state machine and this key press is supposed to indicate that the user would like to begin using the program and it should move from its initial state to the next state.  Since the initialization of registers is not synthesizable, I can't assume that <code>START</code> begins at 0.  </p>
  
  <p>The problem is that once I program the board and turn it on, this <code>always</code> block has already run once before I press the key assigned to <code>key[3]</code>. I've done checks for the value of <code>START</code> at program execution and it is already at <code>1</code>. I can't figure out why this would be happening, as the key is at its negative edge only upon key press.  I've used always blocks with the same condition in previous situations and it worked fine, so I assume this has something to do with the initialization of <code>START</code>?</p>