title: How to implement a (pseudo) hardware random number generator
body: <p>How do you implement a hardware random number generator in an HDL (verilog)?</p>
  
  <p>What options need to be considered?</p>
  
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  <p>This question is following the <a href="https://stackoverflow.com/help/self-answer">self-answer</a> format. Addition answers and updates are encouraged.</p>