title: Invoking the Makefile of parent directory
body: <p>I have a project with the following directory structure:</p>
  
  <pre><code>foo/
  foo/Makefile
  foo/bar/
  </code></pre>
  
  <p>My goal is to add a file <code>foo/bar/Makefile</code>, so that if I invoke <code>make</code> in <code>foo/bar</code>, the Makefile of the parent directory will be used. It's kind of an inverted recursive Makefile structure (I want every Makefile to invoke the parent directory until it reaches the project root).</p>
  
  <p>Symlinking fails since invoking it from the wrong directory breaks all relative paths:</p>
  
  <pre><code>$ ln -s ../Makefile foo/bar/Makefile
  $ make -C foo/bar
  [error]
  </code></pre>
  
  <p>The only solution I have found is to write a Makefile which captures all of the targets that I am interested in and invokes the parent directory with that target:</p>
  
  <pre><code>$ cat foo/bar/Makefile
  all clean:
      $(MAKE) -C .. $@
  </code></pre>
  
  <p>This is laborious and prone to break. Is there a more elegant solution?</p>
  
  <p><strong>Justification</strong></p>
  
  <p>The project is a large LaTeX document which contains multiple subdirectories for <code>.tex</code> files for Chapters, Figures, etc. I want to be able to invoke <code>make</code> from any one of these directories to build the document.</p>