title: Makefile: Wildcard for two programs with different source files
body: <p>I'm working on a C project with two programs, a server and a client.<br>
  My projects structure:</p>
  
  <pre><code>.
  +--/bin
  |  +--/client
  |  +--/server
  |
  +--/lib
  |  +--header1.h
  |  +--header2.h
  |  +--header3.h
  |
  +--/obj
  |  +--/client
  |  +--/server
  |
  +--/src
  |  +--/client
  |  |  +--files.c
  |  +--/server
  |     +--otherfiles.c
  |
  +--Makefile
  </code></pre>
  
  <p>Now I'm stuck on the Makefile, both my programs need different and some overlapping headers. I tried looking into other projects/repositories, but that didn't help me.<br>
  This is what i currently got:</p>
  
  <pre><code>SOURCES_CLIENT = ${wildcard src/client/files.c}
  SOURCES_SERVER = ${wildcard src/client/otherfiles.c}
  
  HEADERS_CLIENT = ${wildcard lib/header1.h lib/header2.h}
  HEADERS_SERVER = ${wildcard lib/header2.h lib/header3.h}
  
  OBJ_CLIENT = ${SOURCES_CLIENT:.c=.o}
  OBJ_SERVER = ${SOURCES_SERVER:.c=.o}
  
  CC = gcc
  CFLAGS = #not relevant
  
  all: client server
  
  client: ${OBJ_CLIENT}
      ${CC} -o $@ $^
  
  server: ${OBJ_SERVER}
      ${CC} -o $@ $^
  </code></pre>
  
  <p>How would I create wildcard rules to convert my source files to object files (in the correct bin/ directory) using the corresponding header files? Also my Makefile seems to be optimizable, if so how?</p>