title: Systemverilog interfaces over hierarchical boundaries
body: <p>I have experienced some back-end issues using systemverilog interfaces when and interface is traversing over hierarchical boundaries. I've tried to sketch the situation in the attached drawing.</p>
  
  <p>The top picture shows the "regular" method of using interfaces. the interface and connected module are all instantiated at the same level of hierarchy. This works for simulation and back-end.</p>
  
  <p>The middle picture shows my situation. At the toplevel I have a module and interface instantiation. The interface is connected to the purple module and then connected to 2 sub-modules. In simulation this works.</p>
  
  <p>Then the synthesis tool complains that the interface at the purple level should be an modport. So I added that. However the synthesis tool is interpreting the wires in the as bidirectional and adds logic to facilitate this. In my design all wires are unidirectional.</p>
  
  <p>The only workaround I could find to fix this issue is depicted in the lower picture. I connect via a modport the original interface (labeled A). Then I instantiate a new interface (labeled B) which has the same parent as interface A. Both interfaces A and B are connected to a connect module which contains a lot of statements like:</p>
  
  <p>assign interfaceB.rx1 = interfaceA.rx1;</p>
  
  <p>assign interfaceB.rx2 = interfaceA.rx2;</p>
  
  <p>assign interfaceA.statusX = interfaceB.statusX;</p>
  
  <p>etc</p>
  
  <p>so it is just a "dumb" connection of interface A and B.</p>
  
  <p>This way of work feels very wrong as this connect module is creating a lot of overhead. Is there a good / easier way of using the interface over hierarchical boundaries that is not only working in simulations but also works for synthesis?</p>
  
  <p>Thanks
  <a href="https://i.stack.imgur.com/CrNHW.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CrNHW.png" alt="enter image description here"></a></p>