title: VHDL: Equality of std_logic_vector in combinational logic
body: <p>I am trying to write what I thought would be some simple combinational logic equations. It is for a CPLD that performs address decoding.
  So I have an address bus: <code>a: std_logic_vector(15 downto 0)</code> and want to test for a specific but partial (IO) address. (mytemp is signal of std_logic)</p>
  
  <pre><code>mytemp &lt;= a(11 downto 2) == "1111111111";
  </code></pre>
  
  <p>Does not fly and I have no idea why. I have been searching for examples but everything I try does not work and gives syntax errors.</p>
  
  <p>What am I doing wrong here?</p>
  
  <p>EDIT: the '==' I saw somewhere on the interweb but that should be '='.</p>