title: Can I use generate-endgenerate block inside initial in SystemVerilog?
body: <p>For e.g.</p>
  
  <pre><code>initial
  begin
  
  generate
  for(genvar i; i &lt; 4; i++)
  //Code
  endgenerate
  
  end //initial
  </code></pre>
  
  <p>I'm getting error using QuestaSim with the concept. "Near generate: syntax error, unexpected generate "</p>