title: vhdl code understanding, if there is modelsim error about possible infinite loop
body: <pre><code>--
  -- VHDL Architecture di_lib.ShiftRegister1.ShiftRegister1
  --
  -- Created:
  --          by - 294162.UNKNOWN (VD1210)
  --          at - 14:19:36 10-04-2015
  --
  -- using Mentor Graphics HDL Designer(TM) 2010.2a (Build 7)
  --
  LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  
  LIBRARY WORK;
  USE WORK.CALC_PKG.ALL;
  LIBRARY di_lib;
  USE di_lib.calc_pkg.all;
  USE ieee.NUMERIC_STD.all;
  
  ENTITY ShiftRegister1 IS
     PORT( 
        d_out       : OUT    Std_Logic_Vector (7 DOWNTO 0);
        multiplexer : IN     Std_Logic_Vector (7 DOWNTO 0);
        carry       : IN     std_logic;
        load_out    : IN     std_logic;
        f_code      : IN     std_logic_vector (2 DOWNTO 0);
        out_loaded  : OUT    std_logic
     );
  
  -- Declarations
  
  END ShiftRegister1 ;
  
  --
  ARCHITECTURE ShiftRegister1 OF ShiftRegister1 IS
  BEGIN
  
    ShiftRegister1 : process
  
    variable remember, multiplexer_var       : std_logic_vector(7 DOWNTO 0);
    variable state          : std_logic_vector(2 DOWNTO 0);
    variable counter        : integer := 0; 
          begin
  
            state := f_code;
  
          case state is
  
          when "000" =&gt; 
              d_out &lt;= multiplexer;
  
          when "001" =&gt;
              d_out &lt;= multiplexer;
  
          when "010" =&gt;
                  multiplexer_var := multiplexer;
              if load_out = '1' then 
                if carry = '1' then
                  --shifting is done without function SRL
                  remember(0) := multiplexer_var(1);
                  remember(1) := multiplexer_var(2);
                  remember(2) := multiplexer_var(3);
                  remember(3) := multiplexer_var(4);
                  remember(4) := multiplexer_var(5);
                  remember(5) := multiplexer_var(6);
                  remember(6) := multiplexer_var(7);
                  remember(7) := '1';
                  d_out &lt;= remember;
                  out_loaded &lt;= '1';
  
                elsif  carry = '0' then
                  remember(0) := multiplexer_var(1);
                  remember(1) := multiplexer_var(2);
                  remember(2) := multiplexer_var(3);
                  remember(3) := multiplexer_var(4);
                  remember(4) := multiplexer_var(5);
                  remember(5) := multiplexer_var(6);
                  remember(6) := multiplexer_var(7);
                  remember(7) := '0';
                  d_out &lt;= remember;
                  out_loaded &lt;= '1';
                end if;
              end if;
  
          when "011" =&gt;
              if load_out = '1' then
                d_out &lt;= multiplexer;
                out_loaded &lt;= '1';
              end if;
  
          when others =&gt; null;
  
          end case;
     end process;
  
  END ARCHITECTURE ShiftRegister1;
  </code></pre>
  
  <p>--ERROR GIVEN --</p>
  
  <blockquote>
    <p>-- Compiling architecture shiftregister1 of shiftregister1<br>
    **Warning: [2] &lt;...>vhd(109): (vcom-1090) Possible infinite loop:   Process contains no WAIT statement.<br>
    Warning: Cannot create unmappedlibrary work  </p>
  </blockquote>
  
  <p>QUESTION:
  where possibly in this code an infinite loop can occur?</p>