title: Verilog comparator
body: <p>I'm newbie to a verilog.</p>
  
  <p>I did a lot of research, and finally wrote this code, but it seems to not work.</p>
  
  <p>Can anyone fix it for me?</p>
  
  <pre><code>module comparator();
      reg[3:0] a, b;
      wire[1:0] equal, lower, greater;    
  
      if (a&lt;b) begin
  
          equal = 0;
          lower = 1;
          greater = 0;
      end
  
      else if (a==b) begin
          equal = 1;
          lower = 0;
          greater = 0;
      end
  
      else begin
          equal = 0;
          lower = 0;
          greater = 1;
      end;
  
      initial begin
                  $monitor($time, 
                           "a=%b, b=%b, greater=%b, equals=%b, lower=%b",
                            a, b, greater, equal, lower);
  
                  a=9; b=10;
                  #100 $display ("\n", $time, "\n");
          end
  endmodule 
  </code></pre>