title: Instantiating multiple modules in Verilog
body: <p>I am writing an 8-bit register comprised of D ffs, and I was wondering if I there is an easier way I could instantiate it in a more simple and easier way, other than what I have below.</p>
  
  <pre><code>module multiplicand(
      input [7:0] A,
      output [7:0] RA,
      input reset,
      input LOAD_cmd,
       input clk
      );
  
  d_flipflop ff0(.D(A[0]), .Q(RA[0]) , .reset(reset), .clk(clk) );
  d_flipflop ff1(.D(A[1]), .Q(RA[1]) , .reset(reset), .clk(clk) );
  d_flipflop ff2(.D(A[2]), .Q(RA[2]) , .reset(reset), .clk(clk) );
  d_flipflop ff3(.D(A[3]), .Q(RA[3]) , .reset(reset), .clk(clk) );
  d_flipflop ff4(.D(A[4]), .Q(RA[4]) , .reset(reset), .clk(clk) );
  d_flipflop ff5(.D(A[5]), .Q(RA[5]) , .reset(reset), .clk(clk) );
  d_flipflop ff6(.D(A[6]), .Q(RA[6]) , .reset(reset), .clk(clk) );
  d_flipflop ff7(.D(A[7]), .Q(RA[7]) , .reset(reset), .clk(clk) );
  
  endmodule
  </code></pre>
  
  <p>Ideally I want to create a vector ff[7:0] that contains all the instantiations above.</p>