title: What's wrong with this simple VHDL for loop?
body: <p>For some reason the OutputTmp variable will always be uninitialized in the simulation. I can make it work without a for loop but I really want to automate it so I can later move on to bigger vectors. The intermediate variable works fine.</p>
  
  <p>Note: I'm a DBA and C# programmer, really new to VHDL, sorry if this is a stupid question.</p>
  
  <pre><code>architecture Arch of VectorMultiplier4 is
  
  signal Intermediate : std_logic_vector(0 to 4);
  signal OutputTmp : std_logic;
  
  begin
  
  process (Intermediate)
  begin
  
    for i in 0 to 4 loop
      Intermediate(i) &lt;= (VectorA(i) AND VectorB_Reduced(i));    
    end loop;
  
    --THIS IS WHAT DOES NOT WORK APPARENTLY
    OutputTmp &lt;= '0';
    for i in 0 to 4 loop
      OutputTmp &lt;= OutputTmp XOR Intermediate(i);
    end loop;
  Output &lt;= OutputTmp;
  end process;
  
  end architecture;
  </code></pre>
  
  <p>Thanks!</p>