title: `include with function definition in system Verilog
body: <p>I have a simple system Verilog code with a `include file which has few function definitions. However when I have multiple files which include this file then I get compile error due to function redefinition. Any suggestions how to work around it?</p>
  
  <p>Code test.sv:</p>
  
  <pre><code>`include "constants.sv"
  
  module test();
  
  real myReal1;
  real myReal2;
  
  initial myReal1 = 10.1;
  
  assign myReal2 = abs(myReal1);
  
  endmodule
  </code></pre>
  
  <p>Code:test2.sv:</p>
  
  <pre><code>`include "constants.sv"
  
  module test2();
  
  real myReal1;
  real myReal2;
  
  initial myReal1 = 10.1;
  
  assign myReal2 = 10.2;
  
  endmodule
  </code></pre>
  
  <p>Error:</p>
  
  <pre><code>function real abs(input real a);
                  |
  ncvlog: *E,DUPIDN (./constants.sv,19|16): identifier 'abs' previously declared [12.5(IEEE)].
  </code></pre>