title: Recursive make: correct way to insert `$(MAKEFLAGS)`
body: <p>How can I use <code>$(MAKEFLAGS)</code> (or another way of passing variables defined on the command line to sub-make) in a way that supports invocation from shell with both <code>make VAR=val</code> and <code>make -args</code>?</p>
  
  <p>I need my subprojects configurable, but I hate autotools, so I'm using make variables for this, e.g. invoking from shell:</p>
  
  <pre><code>$ make USE_SSE3=1
  </code></pre>
  
  <p>and <code>USE_SSE3</code> needs to apply to all builds in all sub-makefiles.</p>
  
  <p><a href="http://www.gnu.org/software/make/manual/html_node/Options_002fRecursion.html" rel="noreferrer">The manual</a> states that:</p>
  
  <blockquote>
    <p>if you do ‘make -ks’ then MAKEFLAGS gets the value ‘ks’.</p>
  </blockquote>
  
  <p>Therefore I'm using <code>-$(MAKEFLAGS)</code> (with a dash prefix) in my Makefile. </p>
  
  <p>However, that <strong>expands into invalid arguments when variables with no flags are used</strong>. If I run:</p>
  
  <pre><code>$ make FOO=bar
  </code></pre>
  
  <p>then sub-make gets invalid <code>-FOO=bar</code>. OTOH without the dash prefix variable definitions work, then but <code>make -s</code>, etc. don't.</p>
  
  <p>Is there a syntax/variable/hack that makes passing of arguments <em>and</em> lone variable definitions work with sub-makefiles?</p>
  
  <p>The legacy <code>$(MKFLAGS)</code> doesn't have the weird dash prefix problem, but it doesn't include variable definitions either. I've tried fixing the variable with <code>$(patsubst)</code>, but that only made things worse by trimming whitespace.</p>
  
  <p>I need the solution to be compatible with the outdated GNU Make 3.81 shipped with Mac OS X Mavericks.</p>
  
  <hr>
  
  <pre><code>foo:
      $(MAKE) -C subproject -$(MAKEFLAGS)
  </code></pre>
  
  <hr>
  
  <pre><code>$ make foo -s       # MAKEFLAGS = 's'
  $ make foo BAR=baz  # MAKEFLAGS = 'BAR=baz'
  $ make foo -j8      # MAKEFLAGS = ' --job-server=…'
  </code></pre>