title: sample input signals and check their values VHDL
body: <p>I have 2 <code>input</code> signals - <code>ID_1,ID_2</code> which sampled into <code>id_vec</code>.<br>
  <code>LEDx_GRNn</code> are <code>output</code>.
  In this point, only one of <code>a,b,c,d</code> should be '1' and the others '0', which after should make only one led on and the others off.  </p>
  
  <p>For some reason all the leds are on so I'm guessing I do something wrong.<br>
  Waht am I missing?<br>
  ID_1,ID_2 have the constants values.  </p>
  
  <pre><code>signal id_vec :std_logic_vector (1 downto 0);
  signal flag :std_logic;
  signal a:std_logic;
  signal b:std_logic;
  signal c:std_logic;
  signal d :std_logic;
  
  id_vec(0)&lt;=ID_1;
  id_vec(1)&lt;=ID_2;
  
  a &lt;='1' when id_vec&lt;="10" else '0';
  b &lt;='1' when id_vec&lt;="00" else '0';
  c &lt;='1' when id_vec&lt;="01" else '0';
  d &lt;='1' when id_vec&lt;="11" else '0';
  
  
  LED1_GRNn &lt;=  not (a);
  LED2_GRNn &lt;=  not (b);
  LED3_GRNn &lt;=  not (c);
  LED4_GRNn &lt;=  not (d); 
  </code></pre>