title: Force signal from testbench
body: <p><strong>The Problem</strong></p>
  
  <p>In my design there is a counter used for delays. For simulation purposes I would like to cap it's maximum value witout editing any of the production code. This is done in order to speed up the simulation.</p>
  
  <p><strong>What I've tried</strong></p>
  
  <p>I wanted to check if it exceeds a maximum value from my testbench, and if it does I wanted to set it to that value. My first try looked like this:</p>
  
  <pre><code>alias ext_delay is &lt;&lt; signal .architecture.in.my.production.code.delay : std_logic_vector(31 downto 0) &gt;&gt;;
  cap_delay : process (ext_delay) is
      constant max_value : std_logic_vector(31 downto 0) := x"00001000"
  begin
      if ext_delay &gt; max_value then
          ext_delay &lt;= max_value;
      end if:
  end process cap_delay;
  </code></pre>
  
  <p>However, this causes the delay signal in the architecture to always be <code>'U'</code>, probably since it was driven by multiple processes. I then tried it by using the <code>force</code> keyword, which succeeded in changing the value and did not cause it to become <code>'U'</code>, but then I need a way to release it again the next time it gets decremented.</p>