title: Ring Oscillator
body: <p>I'm having some trouble implementing a ring oscillator. I don't care about it working on an FPGA. I only want to simulate using Xilinx ISE. Is the code below acceptable? I also addded the test bench. Thanks!</p>
  
  <p><strong>Code</strong></p>
  
  <hr>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  -- 5 Ring Oscillator
  
  entity ring_osc is
      port (ro_en : in std_logic;
              delay : in time;
              ro_out : out std_logic);
  end ring_osc;
  
  architecture behavioral of ring_osc is
      signal gate_out : std_logic_vector(5 downto 0) := (others =&gt; '0');
  
  begin
      process
      begin
          gate_out(0) &lt;= ro_en and gate_out(5);
          wait for delay;
          gate_out(1) &lt;= not(gate_out(0));
          wait for delay;
          gate_out(2) &lt;= not(gate_out(1));
          wait for delay;
          gate_out(3) &lt;= not(gate_out(2));
          wait for delay;
          gate_out(4) &lt;= not(gate_out(3));
          wait for delay;
          gate_out(5) &lt;= not(gate_out(4));
          wait for delay;
          ro_out &lt;= gate_out(5);
      end process;
  
  end behavioral;
  </code></pre>
  
  <p><strong>Test Bench</strong></p>
  
  <hr>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity ring_osc_tb is
  end ring_osc_tb;
  
  architecture behavior of ring_osc_tb is 
  
      -- component declaration for the unit under test (uut)
  
      component ring_osc
          port (ro_en : in  std_logic;
                delay : in time;
                ro_out : out  std_logic);
      end component;
  
  
      -- Inputs
      signal ro_en : std_logic := '0';
      signal delay : time := 0.5 ns;
  
      -- Outputs
      signal ro_out : std_logic;
  
      signal clk : std_logic := '0';
      constant clk_period : time := 10 ns;
  
  begin
  
      -- instantiate the unit under test (uut)
      uut: ring_osc port map (
          ro_en =&gt; ro_en,
          delay =&gt; delay,
          ro_out =&gt; ro_out
      );
  
      -- clock process definitions
      clk_process :process
      begin
          clk &lt;= '0';
          wait for clk_period/2;
          clk &lt;= '1';
          wait for clk_period/2;
      end process;
  
      -- stimulus process
      stim_proc: process
      begin
          ro_en &lt;= '1';
          delay &lt;= 0.5 ns;
          wait for 10*clk_period;
  
          delay &lt;= 1 ns;
          wait for 5*clk_period;
  
          assert false report "End of Simulation" severity failure;
      end process;
  
  end;
  </code></pre>