title: Adding variable to a string in systemverilog
body: <p>I need to generate filenames with variables in the name. Eg. filename needs to be <code>wave_mon[0]_ch0_dat.out</code> The <code>0</code> in this string will vary based on a for loop. My code is as below:</p>
  
  <pre><code>for (i=0; i&lt;16; i=i+1) begin
      fname = {"wave_mon[",i,"]_ch",i,"_dat.out"};
      $display("Filename created is %s \n", fname);
      #1us;
  end 
  </code></pre>
  
  <p>The output from this code is always as below. What am I missing that it is not able to print value of <code>i</code> in the string name?</p>
  
  <pre><code>Filename created is wave_mon[]_channel__data.out                                     
  
  Filename created is wave_mon[]_channel__data.out 
  
  Filename created is wave_mon[]_channel__data.out 
  </code></pre>