title: How to monitor signal in SystemVerilog program block
body: <p>I'm trying to learn few things about testbenches with SystemVerilog.
  However I couldn't seem to find a way to monitor DUT signal inside program block</p>
  
  <p>Consider following example.
  Signal 'dummy' is output of DUT and input to program block.
  Now I need to monitor 'dummy' in program block to raise a flag 'test' when 'dummy' has particular value.</p>
  
  <p>In general module-driven testbench, I would simply write always @(dummy), but always blocks are not allowed under program. How would I achieve this?</p>