title: In "latency value table": latency values of each level cache are including the previous level cache access?
body: <p>For the question, I will use this table as example:</p>
  <p><a href="https://i.stack.imgur.com/qXsC1.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/qXsC1.png" alt="enter image description here" /></a></p>
  <p>But the memory hierarchy of this processor is not relevant for this question!</p>
  <p>My question is if the latency values of each level cache are including the previous level cache access or not. I mean, if we assume that we only access to L2 after a L1 miss (and only access L3 after a L2 miss), looking in my example (for a L1 miss, L2 miss and L3 hit) the number of cicles spent will be ~21 cycles or will be ~(4+12+21) cycles?</p>
  <p>And, if the answer is that the latency value includes the previous level cache acesses, the RAM access latency value does it too?</p>
  <p>As I said, ignore the exact numbers of the processor, just take this question in a general way please.</p>
  <p>I have seen a lot of &quot;latency value tables&quot; and I've never known how to interpret them correctly due to this doubt.</p>