title: How to use a constant calculated from generic parameter in a port declaration in VHDL?
body: <p>An example would be a generic register file which I'm trying to implement like this:</p>
  
  <pre><code>entity register_file is
  generic(reg_width: integer := 32; reg_num: integer := 16);
  constant sel_num: integer := integer(CEIL(LOG(Real(reg_num))));
  port (
      data_in: in std_logic_vector(reg_width - 1 downto 0);
      data_out: out std_logic_vector(reg_width - 1 downto 0);
      rd_sel: in std_logic_vector(sel_num - 1 downto 0);
      wr_sel: in std_logic_vector(sel_num - 1 downto 0);
      rd_enable: in std_logic;
      wr_enable: in std_logic;
      clock: in std_logic;
  );
  end register_file;
  </code></pre>
  
  <p>This doesn't work because it seems generic and port have to be the first two declarations, followed by the others. If I move type and constant after the port declaration, they are not visible when the port declaration is being processed.</p>
  
  <p>I'm new to VHDL and I think this should be a common problem, but I can't find the solution. Obviously, I would like to avoid the copy-paste solution.</p>