title: How to store input into reg from wire in verilog?
body: <p>I' trying to store value from wire named 'in' into reg 'a'. 
  But, the problem is value of reg 'a' is showing 'xxxx' in simulator. However, value of wire 'in' is showing correctly.
  My target is just to read value from input wire and store it into a register. </p>
  
  <pre><code>module test(
  input [3:0] in,
  output [3:0] out
  );
  reg [3:0] a;
  
  initial
  begin
  a = in;
  end
  endmodule
  </code></pre>