title: Shifting a Concatenate Register
body: <p>Ive been doing verilog HDL in quartus II for 2 month now and have not synthesized any of my codes yet. I am struggling to code a fractional division circuit. Of course theres a lot of problems...</p>
  
  <p>I would like to know how do I concatenate two registers to form a larger register that I can shift to the right where the shifting of the data would occur at every positive edge of the clock pulse... The data in the newly created register has 3 zeros (MSB) followed by 4 data bits from another register called divider.<br/>
  For example <code>B=[0 0 0]:[1 0 1 0]</code></p>
  
  <p>I have tried the following</p>
  
  <pre><code>module FRACDIV (divider,clk,B,START,CLR);
  
  input       [3:0]  divider;
  input           START, CLR, clk;
  output      [6:0] B;
  
      reg [6:0]       B;
  
  
  always @ (posedge clk)
      begin
          B = {3'd0, divider};
              if (START == 1'b1)
          begin
          B=B+B&lt;&lt;1;
          end
      end
  
  endmodule
  </code></pre>
  
  <p>Any help would be deeply appreciated as I've been trying to figure this out for 5 hours now...</p>
  
  <hr>
  
  <p>Mr. Morgan,</p>
  
  <p>Thank you for the tips. The non-blocking statement did help. However the code would not shift perhaps because B is always reinitialized at every clock pulse as it is outside the if statement.</p>
  
  <p>With a fresh new day and a fresh mind and owing to your suggestion using the non-blocking statement I tried this...</p>
  
  <pre><code>module FRACDIV(divider,clk,B,START,CLR);
  input       [3:0] divider;
  input           START, CLR, clk;
  output      [6:0] B;
  
      reg [6:0] B;
  
      always @ (posedge clk) 
      begin
        if (START) begin
          B &lt;= {3'b0, divider};
        end
        else begin
           B &lt;= B &lt;&lt;1;
        end
      end
  endmodule
  </code></pre>
  
  <p>The if statement loads data into B whenever START is HIGH. When START is LOW, the data shifts at every positive edge of the clock. Is there anyway to make the data in B to start shifting right after loading it with the concatenated data without the if statement? </p>
  
  <p>Just curious and I still do not feel this code is the most efficient.</p>