title: VHDL Clock divider
body: <p>I am using the following VHDL to take a 100 Mhz clock and put out a 25 Mhz clock. :</p>
  
  <pre><code>process(clk, reset)
    variable count : integer range 0 to 2;
  begin
    if (reset = '1') then
      clock_25MHz &lt;= '0';
      count       := 0;
    elsif rising_edge(clk) then
      count := count+1;
      if(count &gt;= 2) then
        clock_25MHz &lt;= not clock_25MHz;
        count       := 0;
      end if;
    end if;
  end process;
  </code></pre>
  
  <p>It is giving me this warning:</p>
  
  <p>"WARNING:Xst:1293 - FF/Latch count_1 has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process."</p>
  
  <p>I don't understand why its happening. Can anyone shed some light on this for me? Thanks!</p>