title: Verilog forcing struct to be packed
body: <p>I have a struct declared inside a module like this:</p>
  
  <pre><code>module myModule;
  
    struct {
      logic a;
      logic b;
      logic [A - 1:0] c[0:B - 1];
      logic [C - 1:0] d;
    } [D - 1:0] e [0:E - 1][0:F - 1];
  
  endmodule
  </code></pre>
  
  <p>I want to use <code>c</code> like an unpacked array, but Verilog does not allow this.  It throws an error on the line where <code>c</code> is defined:</p>
  
  <pre><code>Unsupported: Unpacked array in packed struct/union
  </code></pre>
  
  <p>Is there a way around this?</p>