title: Is this "glitch safe" clock mux really glitch safe?
body: <p>I found this design for a clock mux at <a href="http://www.vlsi-world.com/content/view/64/47/1/1/" rel="nofollow">http://www.vlsi-world.com/content/view/64/47/1/1/</a></p>
  
  <p>The author claims that it is glitch safe, but I think that it could still have a glitch if the routing delays for the clock signal to the respective or gate (or_three, or_four) was greater than the routing delay + clock to out delay of q3/q4 to the or gate when the output of q3/q4 went low. In order to avoid these glitches, the outputs of q3/q4 would have to have go high on the clock's rising edge and go low on a clock falling edge. Am I correct in this assessment?</p>
  
  <p>Also note that the schematic on the page I linked doesn't quite match the verilog (q3's qbar output isn't used in the verilog) and that the testbench used to generate the simulation transposes clk_a and clk_b.</p>
  
  <pre><code>`timescale 1ns/100ps
  
  module clk_switch (
     // Outputs
     out_clk,
     // Inputs
     clk_a, clk_b, select
     );
  
     input clk_a;
     input clk_b;
     input select;
  
     output out_clk;
  wire   out_clk;
  
  reg q1,q2,q3,q4;
  wire or_one, or_two,or_three,or_four;
  
  always @ (posedge clk_a)
  begin
      if (clk_a == 1'b1)
      begin
         q1 &lt;= q4;
         q3 &lt;= or_one;
      end
  end
  
  always @ (posedge clk_b)
  begin
      if (clk_b == 1'b1)
      begin
          q2 &lt;= q3;
          q4 &lt;= or_two;
      end
  end
  
  assign or_one   = (!q1) | (!select);
  assign or_two   = (!q2) | (select);
  assign or_three = (q3)  | (clk_a);
  assign or_four  = (q4)  | (clk_b);
  
  assign out_clk  = or_three &amp; or_four;
  
  endmodule 
  </code></pre>
  
  <p>I wrote up a quick translation in VHDL so clever folks who are more familiar with that language will be able to check it and nobody will take issue with a VHDL tag on here.</p>
  
  <pre><code>entity clk_switch is
     port(
        out_clk : out std_logic;
        clk_a   : in  std_logic;
        clk_b   : in  std_logic;
        sel     : in  std_logic;
     );
  end clk_switch;
  
  architecture rtl of clk_switch is
     signal q1 : std_logic;
     signal q2 : std_logic;
     signal q3 : std_logic;
     signal q4 : std_logic;
  
     signal or_one   : std_logic;
     signal or_two   : std_logic;
     signal or_three : std_logic;
     signal or_four  : std_logic;
  begin
     process(clk_a)
     begin
        if (clk_a'event and clk_a='1') then
           q1 &lt;= q4;
           q3 &lt;= or_one;
        end if;
     end process;
  
     process(clk_b)
     begin
        if (clk_b'event and clk_b='1') then
           q2 &lt;= q3;
           q4 &lt;= or_two;
        end if;
     end process;
  
  or_one &lt;= not q1 or not sel;
  or_two &lt;= not q2 or sel;
  or_three &lt;= q3 or clk_a;
  or_four  &lt;= q4 or clk_b;
  
  out_clk &lt;= or_three and or_four;
  
  end rtl;
  </code></pre>