title: Error synthesizing hierarchical names in vivado
body: <p>Using Vivado 2015.1, I'm attempting to use a hierarchical name to access an object on the top level module of my design. The simulation runs fine but I receive the following synthesis error:</p>
  
  <p><code>[Synth 8-660] unable to resolve 'top' ["child.sv":3]</code></p>
  
  <pre><code>module top()
      logic foo;
  endmodule
  
  module child()
      always(bar) begin
          logic top.foo &lt;= bar;
      end
  endmodule
  </code></pre>
  
  <p>Any Ideas?</p>