title: Design of a VHDL LUT Module
body: <p>Description:
  I am trying to write vhdl module a LUT (Look Up Table) with 4 inputs and 3 outputs. I want my 3 bit output to be a binary number equal to the number of 1's in the input.</p>
  
  <p>My Truth Table:</p>
  
  <blockquote>
    <p>ABCD|XYZ<br>
    0000|000<br>
    0001|001<br>
    0010|001<br>
    0011|010<br>
    0100|011<br>
    0101|010<br>
    0110|010<br>
    0111|011<br>
    1000|001<br>
    1001|010<br>
    1010|010<br>
    1011|011<br>
    1100|010<br>
    1101|011<br>
    1110|011<br>
    1111|100</p>
  </blockquote>
  
  <p>My VHDL code:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  
  entity lut is
  Port (
  a : in STD_LOGIC; 
  b : in STD_LOGIC; 
  c : in STD_LOGIC; 
  d : in STD_LOGIC; 
  x : out STD_LOGIC; 
  y : out STD_LOGIC; 
  z : out STD_LOGIC);  
  
  end lut;   
  
  architecture Behavioral of lut is  
  signal s0: STD_LOGIC;
  signal s1: STD_LOGIC;
  signal s2: STD_LOGIC;  
  signal s3: STD_LOGIC;
  signal s4: STD_LOGIC;
  signal s5: STD_LOGIC;
  signal s6: STD_LOGIC;
  signal s7: STD_LOGIC; 
  signal s8: STD_LOGIC;
  signal s9: STD_LOGIC;
  signal s10: STD_LOGIC;
  signal s11: STD_LOGIC;
  signal s12: STD_LOGIC;
  signal s13: STD_LOGIC;
  
  begin 
  ----------MUX1----------- 
  process(a,b) 
  begin
  if a='0' 
  then s0&lt;=a;
  else
  s0&lt;=b;
  end if; 
  end process; 
  
  --------MUX2---------- 
  process(a,b) 
  begin
  if a='0' 
  then s1&lt;=a;
  else
  s1&lt;=b; 
  end if;
  end process;
  
  ---------MUX3-----------
  process(a,b) 
  begin
  if a='0' 
  then s2&lt;=a;
  else
  s2&lt;=b;
  end if; 
  end process;
  ---------MUX4-----------
  process(a,b) 
  begin
  if a='0' 
  then s3&lt;=a;
  else
  s3&lt;=b;
  end if; 
  end process;
  ---------MUX5-----------
  process(c,d,a) 
  begin
  if a='0' 
  then s4&lt;=c;
  else
  s4&lt;=d;
  end if; 
  end process;
  ---------MUX6-----------
  process(c,d,a) 
  begin
  if a='0' 
  then s5&lt;=c;
  else
  s5&lt;=d;
  end if; 
  end process;
  ---------MUX7-----------
  process(c,d,a) 
  begin
  if a='0' 
  then s6&lt;=c;
  else
  s6&lt;=d;
  end if; 
  end process;
  ---------MUX8-----------
  process(c,d,a) 
  begin
  if a='0' 
  then s7&lt;=c;
  else
  s7&lt;=d;
  end if; 
  end process;
  ---------MUX9-----------
  process(s0,s1,b) 
  begin
  if b='0' 
  then s8&lt;=s0;
  else
  s8&lt;=s1;
  end if; 
  end process;
  ---------MUX10-----------
  process(s2,s3,b) 
  begin
  if b='0' 
  then s9&lt;=s2;
  else
  s9&lt;=s3;
  end if; 
  end process;
  ---------MUX11-----------
  process(s4,s5,b) 
  begin
  if b='0' 
  then s10&lt;=s4;
  else
  s10&lt;=s5;
  end if; 
  end process;
  ---------MUX12-----------
  process(s6,s7,b) 
  begin
  if b='0' 
  then s11&lt;=s6;
  else
  s11&lt;=s7;
  end if; 
  end process;
  ---------MUX13-----------
  process(s8,s9,c) 
  begin
  if c='0' 
  then s12&lt;=s8;
  x&lt;= s8;
  else
  s12&lt;=s9;
  x&lt;= s9;
  end if; 
  end process;
  ---------MUX14-----------
  process(s10,s11,c) 
  begin
  if c='0' 
  then s13&lt;=s10;
  z&lt;=s10;
  else
  s13&lt;=s11; 
  z&lt;=s11
  end if; 
  end process; 
  ---------MUX15-----------
  process(s12,s13,d) 
  begin
  if d='0' 
  then y&lt;=s12;
  else
  y&lt;=s13;
  end if; 
  end process;
  end Behavioral;
  </code></pre>
  
  <p>Assumptions:
  I need a total of 15 multiplexers to model what I need. They will be cascaded to one output.
  I would have a total of 15 processes shown above.</p>
  
  <p>Questions:<br>
  1.) What are my selects for the mux, ABCD?<br>
  2.) Am I modeling this the correct way? Will I achieve what I want from the info given?<br>
  3.) If there is a better way or you have a different Idea could you please provide an example?<br>
  4.) I am not getting my xyz output, its close but what am i doing wrong?</p>
  
  <p>I have tried to provide as much research as possible. If you have any questions I will respond immediately</p>