title: Verilog/VHDL - How to avoid resetting data registers within a single always block?
body: <p>I like to avoid resetting data registers that don't need to be reset. For example, when streaming data through pipeline stages, if each stage has a valid bit, there is no need to reset the data registers. (I believe this eases routing and timing on the data registers.)</p>
  
  <p>This can easily be accomplished by using separate always blocks (or processes in vhdl), but I find this verbose, and doing the following is problematic because the data register is essentially being enabled by the reset.</p>
  
  <pre><code>always @(posedge clk)
  if (rst)
    out_valid &lt;= 0;
    // NOTE: out_data is not reset
  else begin
    out_valid &lt;= in_valid;
    if (in_valid)
      out_data &lt;= in_data + 1;
  end
  </code></pre>
  
  <p>Instead, I've been putting the reset clause at the end of the always block and taking advantage of the "last assignment wins" rule.</p>
  
  <pre><code>always @(posedge clk)
  begin
    out_valid &lt;= in_valid;
    if (in_valid)
      out_data &lt;= in_data + 1;
  
    if (rst)
      out_valid &lt;= 0
  end
  </code></pre>
  
  <p>I haven't seen a lot of people using this style. Are there any drawbacks or issues that I'm missing? Is there a better way of doing this?</p>
  
  <p><strong>Bonus Question</strong>: What if the reset is asynchronous? As in:</p>
  
  <pre><code>always @(posedge clk, posedge rst)
  begin
    out_valid &lt;= in_valid;
    if (in_valid)
      out_data &lt;= in_data + 1;
  
    if (rst)
      out_valid &lt;= 0
  end
  </code></pre>
  
  <p>In this case I think the synthesizer will connect the reset signal to the data register, which defeats the purpose. Is there an elegant way of decoupling the data register from the reset signal without resorting to separate always block?</p>