title: Evaluate Assert First when Simulating
body: <p>I have an assert in my VHDL code that validates generics passed through the entity of my component. The severity of the assert is set to FAILURE, because I want to quit the simulation if the generics are misused. When simulating with Active-HDL (really any version, but I've specifically used versions 12-14a), the assert is hit when the generics are misused and the simulation exits before doing anything else. When simulating with ModelSim DE (I've only tried 10.6c, 32-bit), however, the assert is not the first thing to be evaluated, and a different error appears for a signal assignment of different array lengths, related to the values of the generics (which is why the assert exists). Here is my MCVE:</p>
  
  <p><code>example.vhd</code>:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity example is
    generic
    (
      INPUT_LEN : integer := 4;
      OUTPUT_LEN : integer := 5
    );
    port
    (
      my_input : in std_logic_vector(INPUT_LEN-1 downto 0);
      my_output : out std_logic_vector(OUTPUT_LEN-1 downto 0)
    );
  end entity example;
  
  architecture rtl of example is
  begin
    -- We want this evaluated first.
    assert (INPUT_LEN = OUTPUT_LEN)
      report "INPUT_LEN and OUTPUT_LEN must be equal!"
      severity FAILURE;
  
    -- This is actually what is evaluated first.
    my_output &lt;= my_input;
  end architecture rtl;
  </code></pre>
  
  <p>As you can see, <code>my_output</code> and <code>my_input</code> are affected by the values of the generics, and I want the assert to happen first so that a helpful error message will be printed to the console, instead of the current <code>Fatal: (vsim-3420) Array lengths do not match. Left is 32 (31 downto 0). Right is 8 (7 downto 0).</code>.</p>
  
  <p>I compile and simulate using the following two ModelSim commands:</p>
  
  <p><code>vcom -work work example.vhd</code></p>
  
  <p><code>vsim -c -lib work example</code></p>
  
  <p>My question is, <strong>is there a directive for <code>vsim</code> that forces ModelSim to evaluate asserts first?</strong> Or more broadly, <strong>a command that will look for and evaluate asserts before doing anything else?</strong> It seems Active-HDL does it by default, but ModelSim doesn't... I've looked through the documentation for <code>vsim</code> and I've tried the <code>-immedassert</code> flag but that didn't change anything.</p>
  
  <p>I'm also working with very old code that gets used in a lot of different places (and is obviously way more complex than my MCVE), so the best solution would <em>not</em> be to modify the source code.</p>
  
  <p>Thanks for any help.</p>