title: How to flush cache line in aarch64
body: <p>How can I flush the cache line on aarch64 inside the userspace code? Just like on x86 we can use the following lib call:</p>
  
  <pre><code>_mm_clflush(&amp;array);
  </code></pre>
  
  <p>I tried the following code:</p>
  
  <pre><code>void flush(void)
  {
      asm volatile ( "MCR p15, 0, =0x0,c7, c6, 0\n");
      return;
  }
  </code></pre>
  
  <p>But GCC has compiling error:</p>
  
  <pre><code>Error: unknown mnemonic `mcr' -- `mcr p15,0,=0x0,c7,c6,0'
  </code></pre>
  
  <p>Thanks.</p>
  
  <hr>
  
  <p>Update from @Peter's comment:
  I tried the <code>__builtin___clear_cache</code> with the following code:</p>
  
  <pre><code>int tt = 0;
  unsigned long *ptr;
  
  tt++;
  TIMESTAMP(ts2);
  printf("cycle: %lu. %d\n", ts2-ts1, tt);
  
  ptr = &amp;tt;
  __builtin___clear_cache(ptr, ptr+128);
  TIMESTAMP(ts1);
  tt++;
  TIMESTAMP(ts2);
  printf("cycle: %lu. %d\n", ts2-ts1, tt);
  </code></pre>
  
  <p>The result seems doesn't show we have successfully evicted the data out of the data cache:</p>
  
  <pre><code>cycle: 5. 1
  cycle: 0. 2
  </code></pre>
  
  <p>I looked at the disassembly, and referenced <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html" rel="nofollow noreferrer">the AARCH64 instruction manual</a>. It seems that the builtin function has clean the cache, right?</p>
  
  <pre><code>0000000000400788 &lt;__clear_cache&gt;:
    400788:       14000002        b       400790 &lt;__aarch64_sync_cache_range&gt;
    40078c:       00000000        .inst   0x00000000 ; undefined
  
  0000000000400790 &lt;__aarch64_sync_cache_range&gt;:
    400790:       b0000083        adrp    x3, 411000 &lt;_GLOBAL_OFFSET_TABLE_+0x28&gt;
    400794:       b9404462        ldr     w2, [x3,#68]
    400798:       35000082        cbnz    w2, 4007a8 &lt;__aarch64_sync_cache_range+0x18&gt;
    40079c:       d53b0024        mrs     x4, ctr_el0
    4007a0:       2a0403e2        mov     w2, w4
    4007a4:       b9004464        str     w4, [x3,#68]
    4007a8:       d3504c44        ubfx    x4, x2, #16, #4
    4007ac:       52800083        mov     w3, #0x4                        // #4
    4007b0:       12000c45        and     w5, w2, #0xf
    4007b4:       1ac42064        lsl     w4, w3, w4
    4007b8:       51000482        sub     w2, w4, #0x1
    4007bc:       1ac52063        lsl     w3, w3, w5
    4007c0:       8a220002        bic     x2, x0, x2
    4007c4:       93407c84        sxtw    x4, w4
    4007c8:       eb01005f        cmp     x2, x1
    4007cc:       540000a2        b.cs    4007e0 &lt;__aarch64_sync_cache_range+0x50&gt;
    4007d0:       d50b7b22        dc      cvau, x2
    4007d4:       8b040042        add     x2, x2, x4
    4007d8:       eb02003f        cmp     x1, x2
    4007dc:       54ffffa8        b.hi    4007d0 &lt;__aarch64_sync_cache_range+0x40&gt;
    4007e0:       d5033b9f        dsb     ish
    4007e4:       51000462        sub     w2, w3, #0x1
    4007e8:       93407c63        sxtw    x3, w3
    4007ec:       8a220000        bic     x0, x0, x2
    4007f0:       eb00003f        cmp     x1, x0
    4007f4:       540000a9        b.ls    400808 &lt;__aarch64_sync_cache_range+0x78&gt;
    4007f8:       d50b7520        ic      ivau, x0
    4007fc:       8b030000        add     x0, x0, x3
    400800:       eb00003f        cmp     x1, x0
    400804:       54ffffa8        b.hi    4007f8 &lt;__aarch64_sync_cache_range+0x68&gt;
    400808:       d5033b9f        dsb     ish
    40080c:       d5033fdf        isb
    400810:       d65f03c0        ret
    400814:       00000000        .inst   0x00000000 ; undefined
  </code></pre>