title: VHDL: for...loop instead of for...generate
body: <p>Hello I have a problem in using for...loop instead of for...generate. I'd like to use for...loop because our Professor only taught us about it.</p>
  <pre class="lang-vhdl prettyprint-override"><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity supersomm_4bit is
    port (
      c_in: in std_logic;
      a,b: in std_logic_vector(3 downto 0);
      s: out std_logic_vector(3 downto 0);
      sP,sG: out std_logic
    );
  end supersomm_4bit;
  
  architecture arch of supersomm_4bit is
    signal p,g,c: std_logic_vector(3 downto 0);
  
    begin
      g1: for i in 0 to 3 generate
        g(i) &lt;= a(i) and b(i);
        p(i) &lt;= a(i) or b(i);
      end generate;
  
      c(0) &lt;= c_in;
      c(1) &lt;= g(0) or (p(0) and c(0));
      c(2) &lt;= g(1) or (p(1) and g(0)) or (p(1) and p(0) and c(0));
      c(3) &lt;= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0))
              or (p(2) and p(1) and p(0) and c(0));
  
      g2: for i in 0 to 3 generate
        s(i) &lt;= a(i) xor b(i) xor c(i);
      end generate;
  
      sP &lt;= p(0) and p(1) and p(2) and p(3);
      sG &lt;= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1))
            or (p(3) and p(2) and p(1) and g(0));
  end arch;
  </code></pre>
  <p>I've tried doing something like this</p>
  <pre class="lang-vhdl prettyprint-override"><code>architecture for_loop of supersomm_4bit is
    signal p,g,c: std_logic_vector(3 downto 0);
    begin
      process begin
          for i in 0 to 3 loop
          g(i) &lt;= a(i) and b(i);
          p(i) &lt;= a(i) or b(i);
          end loop;
          wait;
      end process;
  
      c(0) &lt;= c_in;
      c(1) &lt;= g(0) or (p(0) and c(0));
      c(2) &lt;= g(1) or (p(1) and g(0)) or (p(1) and p(0) and c(0));
      c(3) &lt;= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0))
              or (p(2) and p(1) and p(0) and c(0));
          
      process begin
          for i in 0 to 3 loop
          s(i) &lt;= a(i) xor b(i) xor c(i);
          end loop;
          wait;
      end process;
  
      sP &lt;= p(0) and p(1) and p(2) and p(3);
      sG &lt;= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1))
              or (p(3) and p(2) and p(1) and g(0));
  end architecture for_loop;
  </code></pre>
  <p>but it doesn't work (s and sP/sG are uninitialized). I've also tried putting all the code under a single process but it still doesn't work.
  Am I doing something wrong or should I simply avoid using for...loop?
  Thanks!</p>
  <p>EDIT (adding the whole project):</p>
  <pre class="lang-vhdl prettyprint-override"><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity unita_cla is
    port (
      a,b: in std_logic_vector(15 downto 0);
      c_in: in std_logic;
      S: out std_logic_vector(15 downto 0);
      C_OUT: out std_logic
    );
  end unita_cla;
  
  architecture arch of unita_cla is
    signal C: std_logic_vector(4 downto 1);
    signal P,G: std_logic_vector(3 downto 0);
  
    component supersomm_4bit
      port (
        c_in: in std_logic;
        a,b: in std_logic_vector(3 downto 0);
        s: out std_logic_vector(3 downto 0);
        sP,sG: out std_logic
      );
    end component;
  
    begin
      C(1) &lt;= G(0) or (P(0) and c_in);
      C(2) &lt;= G(1) or (P(1) and G(0)) or (P(1) and P(0) and c_in);
      C(3) &lt;= G(2) or (P(2) and G(1)) or (P(2) and P(1) and G(0))
              or (P(2) and P(1) and P(0) and c_in);
      C(4) &lt;= G(3) or (P(3) and G(2)) or (P(3) and P(2) and G(1))
              or (P(3) and P(2) and P(1) and G(0))
              or (P(3) and P(2) and P(1) and P(0) and c_in);
  
      bit0_3: supersomm_4bit port map (c_in, a(3 downto 0), b(3 downto 0),
                                       S(3 downto 0), P(0), G(0));
      bit4_7: supersomm_4bit port map (C(1), a(7 downto 4), b(7 downto 4),
                                       S(7 downto 4), P(1), G(1));
      bit8_11: supersomm_4bit port map (C(2), a(11 downto 8), b(11 downto 8),
                                       S(11 downto 8), P(2), G(2));
      bit12_15: supersomm_4bit port map (C(3), a(15 downto 12), b(15 downto 12),
                                       S(15 downto 12), P(3), G(3));
  
      C_OUT &lt;= C(4);
  end arch;
  </code></pre>
  <p>TESTBENCH:</p>
  <pre class="lang-vhdl prettyprint-override"><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity unita_cla_tb is
  end unita_cla_tb;
  
  architecture testbench of unita_cla_tb is
    signal a,b,S: std_logic_vector(15 downto 0);
    signal c_in,C_OUT: std_logic;
  
    component unita_cla
      port (
        a,b: in std_logic_vector(15 downto 0);
        c_in: in std_logic;
        S: out std_logic_vector(15 downto 0);
        C_OUT: out std_logic
      );
    end component;
  
    begin
      u1: unita_cla port map (a,b,c_in,S,C_OUT);
      tb: process
      begin
        a &lt;= &quot;0000000000000000&quot;;
        b &lt;= &quot;0000000000000000&quot;;
        c_in &lt;= '1';
        wait for 10 ns;
        a &lt;= &quot;1111111111111111&quot;;
        b &lt;= &quot;0000000000000000&quot;;
        c_in &lt;= '0';
        wait for 10 ns;
        a &lt;= &quot;1010101010101010&quot;;
        b &lt;= &quot;0101010101010101&quot;;
        c_in &lt;= '1';
        wait for 10 ns;
        a &lt;= &quot;1111111111111111&quot;;
        b &lt;= &quot;1111111111111111&quot;;
        c_in &lt;= '0';
        wait for 10 ns;
        a &lt;= &quot;1010101010101010&quot;;
        b &lt;= &quot;1010101010101010&quot;;
        c_in &lt;= '1';
        wait for 10 ns;
        wait;
      end process;
    end testbench;
  </code></pre>