title: Why is CPSR not a banked register?
body: <p>In ARM, the SPSR is a banked register i.e. after every change in mode, CPSR is copied into the SPSR, and after the mode returns, the SPSR is copied back to CPSR. Why is the CPSR not banked directly? It seems like there are two additional instructions with every mode change (copy into spsr, copy into cpsr)</p>