title: What are yosys formal capabilities with verific?
body: <p>I'm trying to use Yosys formal verification capabilities along with Verific parser.</p>
  
  <p>What are the supported capabilities of yosys with verific for formal verification, compared to the "read_verilog -formal" command?
  For example, a quick compilation of formal code that works with read_verilog gave me an error for "assume property" syntax:
  "The sva directive is not sensitive to a clock. Unclocked directives are not supported"</p>
  
  <p>I'm not sure if I should modify the Verific library flags in any way to make it support more capabilities, or it's something that is not supported.</p>