title: Compile Date and Time in FPGA
body: <p>Can I uses in VHDL something similar to the C-Sourcecode-Macros <code>__DATE__</code> and <code>__TIME__</code>
   to make the compile time available in the FPGA as a kind of version time stamp?</p>
  
  <p>As a >>>new-comer&lt;&lt;&lt; to VHDL I want to modify the following existing code, which puts a hard coded date into a FPGA register. I always have to remember adjusting the values before compiling. It would be easier if this is done automatically. Can I also include hours/minutes/seconds?</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.std_logic_arith.all;
  
  ENTITY Datum2 IS
     PORT
     (
          Day         :OUT std_logic_vector(4 downto 0);
          Month       :OUT std_logic_vector(3 downto 0);
          Year        :OUT std_logic_vector(4 downto 0)
     );
  END Datum2 ;
  
  ARCHITECTURE rtl OF Datum2 IS
  
  BEGIN
  --  "08.08.0013"
      Day   &lt;= conv_std_logic_vector(8, 5);
      Month &lt;= conv_std_logic_vector(8, 4);
      Year  &lt;= conv_std_logic_vector(13, 5);
  END ARCHITECTURE rtl;
  </code></pre>