title: VHDL: Is there a convenient way to assign ascii values to std_logic_vector?
body: <ul>
  <li><p>In verilog, I can assign a string to a vector like: </p>
  
  <pre><code>wire [39:0] hello;
  assign hello = "hello"; 
  </code></pre></li>
  <li><p>In VHDL, I'm having difficulty finding a method like this:</p>
  
  <pre><code>SIGNAL hello : OUT std_logic_vector (39 DOWNTO 0);
  ...
  hello &lt;= "hello";
  </code></pre></li>
  </ul>
  
  <p>I've been using:</p>
  
  <pre><code>hello &lt;= X"65_68_6c_6c_6f";
  </code></pre>
  
  <p>which is unclear and time consuming for large strings.</p>
  
  <p>I've looked at the <a href="http://paws.kettering.edu/~mcdonald/class/ce422/qhdl/8_TxtIO.pdf" rel="noreferrer"><code>textio</code> package</a> and the<a href="http://www.stefanvhdl.com/vhdl/vhdl/txt_util.vhd" rel="noreferrer"><code>txt_util</code> package</a>, but neither seem to be very clear on how to interpret a string and convert it to std_logic.</p>
  
  <p>Is there a simple method of assigning ascii codes to std_logic in VHDL?</p>
  
  <p>Here's a minimal example:</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  
  ENTITY test IS
  PORT(
     ctrl : IN std_logic;
     stdout : OUT std_logic_vector (39 DOWNTO 0)
  );
  END ENTITY;
  
  ARCHITECTURE rtl OF test IS
     SIGNAL temp : std_logic_vector (39 DOWNTO 0);
  BEGIN
     stdout &lt;= temp;
     PROCESS(ctrl)
     BEGIN
        IF (ctrl = '0') THEN
           temp &lt;= "hello"; -- X"68_65_6C_6C_6F";
        ELSE
           temp &lt;= "world";
        END IF;
     END PROCESS;
  
  END rtl;
  </code></pre>