title: VHDL Clock Divider With Decimals
body: <p>I'm trying to slow a 50MHz clock down to 25.175MHz for use in a VGA controller. I have a clock divider already, but am having trouble slowing the clock down whenever the resulting division of the current clock speed and the desired clock speed is not a whole number. I.E. 50000000/25175000 ~ 1.98. The clock divider compiles and runs, but outputs nothing if the division is a decimal number. Here's my code:</p>
  
  <pre><code>    LIBRARY IEEE;
      USE  IEEE.STD_LOGIC_1164.ALL;
  
      ENTITY Clockdiv IS PORT (
          Clkin: IN STD_LOGIC;
          Clk: OUT STD_LOGIC);
      END Clockdiv;
  
      ARCHITECTURE Behavior OF Clockdiv IS
          CONSTANT max: INTEGER := 50000000/25175000;
          CONSTANT half: INTEGER := max/2;
          SIGNAL count: INTEGER RANGE 0 TO max;
      BEGIN
          PROCESS
          BEGIN
              WAIT UNTIL Clkin'EVENT and Clkin = '1';
  
              IF count &lt; max THEN
                  count &lt;= count + 1;
              ELSE
                  count &lt;= 0;
              END IF;
  
              IF count &lt; half THEN
                  Clk &lt;= '0';
              ELSE
                  Clk &lt;= '1';
              END IF;
          END PROCESS;
      END Behavior;
  </code></pre>
  
  <p>I searched on google, and found using the REAL data type will allow you to use decimals, but when I changed the variables I'm using to REALs, Quartus gives me the error: <code>Error (10414): VHDL Unsupported Feature error at Clockdiv.vhd(12): cannot synthesize non-constant real objects or values</code>.</p>
  
  <p>Then, if I change "count" to a <code>CONSTANT</code> type, I get the error: <code>Error (10477): VHDL error at Clockdiv.vhd(18): name "count" must represent signal</code>.</p>
  
  <p>Does anybody know how I can slow a clock down to 25.175MHz? Also, does anybody know how to slow a clock down so that the compiler is happy with the resulting division being a decimal value?</p>
  
  <p>Thanks</p>