title: VHDL : Signal s Cannot be Synthesised
body: <blockquote>
    <p>line 62: Signal s cannot be synthesized, bad synchronous description.
    The description style you are using to describe a synchronous element
    (register, memory, etc.) is not supported in the current software
    release.</p>
  </blockquote>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity clock is
      Port ( start : in  STD_LOGIC;                       
             reset : in  STD_LOGIC;                       
             CLOCK : in  STD_LOGIC;                       
             setH, setM, setS : in  STD_LOGIC;            
             alarmH, alarmM, alarmS : in  STD_LOGIC; 
             Alarm_On : in  STD_LOGIC;                    
             Buzzer_Stop : in  STD_LOGIC;                 
             BUZZER : out STD_LOGIC;                      
             hh, mm, ss : out INTEGER);                   
  end clock;
  
  architecture Behavioral of clock is
  
  signal h, m, s : INTEGER range 0 to 60 := 0;
  signal hA, mA, sA : INTEGER range 0 to 60 := 0;
  signal clk : std_logic :='0';
  signal count : integer :=1;
  
  begin
  
  Frequency_Reducer : process(CLOCK)  --Reducing Frequency From 40MHz to 1Hz
  begin
      if rising_edge(CLOCK) then
              count &lt;= count + 1;
          if(count = 20000000) then
              clk &lt;= not clk;
              count &lt;=1;
          end if;
      end if;
  end process;
  
  Clock_Logic : process(start, reset, clk)
  begin
      if reset = '1' then  
          h &lt;= 00;
          m &lt;= 00;
          s &lt;= 0;
      end if;
  
      if start = '1' then   
          if rising_edge(clk) then        --Clock Logic Start
              s &lt;= s + 1; 
          end if;
      end if;
  
          if s = 60 then
              s &lt;= 0;
              m &lt;= m + 1;
          end if; 
          if m = 60 then 
              m &lt;= 0;
              h &lt;= h + 1;
          end if; 
          if h = 24 then
              h &lt;= 0;
          end if;                             --Clock Logic End
  
      if setH = '1' then                  --Set Time Logic Start
          h &lt;= h + 1;
      end if;
      if setM = '1' then
          m &lt;= m + 1;
      end if;
      if setS = '1' then
          s &lt;= s + 1;
      end if;                                 -- Set Time Logic End
  end process;
  
  hh &lt;= h;
  mm &lt;= m;
  ss &lt;= s;
  
  end Behavioral;
  </code></pre>