title: Micro fusion and addressing modes
body: <p>I have found something unexpected (to me) using the <a href="https://software.intel.com/en-us/articles/intel-architecture-code-analyzer" rel="noreferrer">Intel® Architecture Code Analyzer</a> (IACA).</p>
  
  <p>The following instruction using <code>[base+index]</code> addressing </p>
  
  <pre><code>addps xmm1, xmmword ptr [rsi+rax*1]
  </code></pre>
  
  <p>does not micro-fuse according to IACA. However, if I use <code>[base+offset]</code> like this</p>
  
  <pre><code>addps xmm1, xmmword ptr [rsi]
  </code></pre>
  
  <p>IACA reports that it does fuse.</p>
  
  <p>Section 2-11 of the <a href="http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html" rel="noreferrer">Intel optimization reference manual</a> gives the following as an example "of micro-fused micro-ops that can be handled by all decoders"</p>
  
  <pre><code>FADD DOUBLE PTR [RDI + RSI*8]
  </code></pre>
  
  <p>and <a href="http://www.agner.org/optimize/" rel="noreferrer">Agner Fog's optimization assembly manual</a> also gives examples of micro-op fusion using <code>[base+index]</code> addressing. See, for example, Section 12.2 "Same example on Core2". So what's the correct answer?</p>