title: SystemVerilog case statement does not work
body: <p>Anyone know why this case statement doesn't work:</p>
  
  <pre><code>int width;
  width = 8;
  case (width === 16)
    1'b0: begin
      // correct code
    end
    1'b1: begin
      // we end up here
    end
  endcase
  </code></pre>
  
  <p>I am using VCS. I tried running this with DVE debugger, and the code worked correctly when running with the debugger. Also, this code is nested within another case statement, not shown here.</p>