title: verification testbench ports need directions or not necessary?
body: <p>I am having a question regarding declaring signals in verification testbench/interface. As i am told in the textbook, i suppose to declare each signal with directions in my testbench or interface, but strangely i can still get correct results without doing that. I can just declare all signals as "logic", and feed them to the correct input/output ports of my DUT. </p>
  
  <p>So I am confused if input/output declaration is necessary for a verification testbench? verification testbenches are not necessarily to be synthesizable, aren't them?  even some examples in my book didn't write the testbench with input/output ports. Sometimes i see plainly "module test();" all signals in the module are declared as "logic".</p>
  
  <p>can someone give some detailed explanations on this? Do I must declare directions for my signals in my testbench? </p>