title: VHDL: how to set a value on an inout port?
body: <p>I am trying to test a <a href="http://en.wikipedia.org/wiki/VHDL" rel="noreferrer">VHDL</a> component, but I can't seem to get this one inout port to give me any behaviour. I've tried setting the port to everything from '1' to '-', but it still comes up as 'U' in simulation. Any sugestions what might be wrong? </p>