title: assign real value to wire in Verilog
body: <p>Hi I have a simple verilog statements where I want to transfer value at real net to a wire using assign statement. However I see a wire at "x" all the time regardless of the value of a real variable. Here is a snapshot of a sample code with values annotated at time zero:</p>
  
  <p>QN is a wire and real_QN is of type real.</p>
  
  <p><a href="https://i.stack.imgur.com/wBxmU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/wBxmU.png" alt="enter image description here"></a></p>
  
  <p><a href="https://i.stack.imgur.com/4C1xM.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/4C1xM.png" alt="enter image description here"></a></p>
  
  <p>Any ideas why QN is at "x" even though real_QN is at "0" ?</p>