title: Square Waveform Generation in VHDL
body: <p>I'm working on a stopwatch project in VHDL but I don't know how to make the CLK square waveform of the counter? Please help.</p>
  
  <p>Here is my code:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_unsigned.ALL;
  
   entity Circuit is
      Port ( CLK : in  STD_LOGIC := '0';
             CLR : in  STD_LOGIC;
             Q : out  STD_LOGIC_VECTOR (5 downto 0));
  end Circuit;
  
  architecture Behavioral of Circuit is
  
  signal s: STD_LOGIC_VECTOR := "000000";
  
  begin
  
  process (CLK, CLR)
  begin
  if rising_edge(CLK) then
  if CLR = '1' OR s = "111011" then
  s &lt;= "000000";
  else
  s &lt;= s+1;
  end if;
  end if;
  end process;
  Q &lt;= s;
  end Behavioral;
  </code></pre>