title: VHDL create a vector of alternating zeros and ones
body: <p><br/>
  I want to create an std_logic_vector of variable size, say size = y, of alternating 0's and 1's. <br/>
  A simple solution would be to use a loop or work with the clock cycle, but the program that I'm working on won't work with that. <br />
  I'm looking basically of a solution that looks like the 'others' statement, i.e. (others => '0'). <br />
  Any help is appreciated</p>