title: creating an ALU in verilog
body: <p>I was wondering if it were possible to have if statements, so for the ALU I am trying to build. I am passing values from a datapath test bench to a datapath, from the datapath into the ALU, and from the ALU back to the datapath. I am trying to create a control unit which will only pass values through a certain component if the corresponding control_ALU is activated.</p>
  
  <p>Here is my verilog code :</p>
  
  <pre><code>module ALU (
    input en_ALU, clk_ALU,
    input [31:0]  inputA, inputB, control_ALU,
    output [31:0] resultc
  );
  wire [31:0] res_out;
  
  always @(control_ALU)
  begin       
    if(control_ALU[1])    begin       
      andLogic  andLogic_component(
        .dataA (inputA),
        .dataB (inputB) ,
        .resultA (res_out)
      );
    end
    if(control_ALU[2])    begin
      negate m0(
        .inputnegate  (inputA), 
        .resultnegate (res_out)
      );
    end   
  end 
  
  reg64bit z(
    .clk(clk_ALU) ,
    .clr(clr),
    .enable(en_ALU),
    .inputd(res_out),
    .outputq(resultc)
  );      
  
  endmodule
  </code></pre>