title: No rule to make target `/Makefile', needed by `Makefile'
body: <p>I'm trying to 'make' using a pretty simple makefile. My makefile is named 'Makefile' so I'm simply using the command 'make'.</p>
  
  <p>I get this strange error:<br>
  <code>
  make: *** No rule to make target `/Makefile', needed by `Makefile'.  Stop.
  </code></p>
  
  <p>If, however, I use
  <code>make -f "full-path-to-makefile"</code> it actually does run (with odd consequences...). I should say that I'm running all this from the directory where the Makefile lies, of course.</p>
  
  <p>I'm working on Mac OSX, using tcsh.</p>
  
  <p>Edit:</p>
  
  <p>I'm working in the LLVM framework, trying to compile a pass function and this is  the associated makefile:</p>
  
  <pre>
  LEVEL = ../../../
  LIBRARYNAME = FunctionName
  LOADABLE_MODULE = 1
  include $(LEVEL)/Makefile.common
  </pre>
  
  <p>Any ideas will be appreciated :)</p>