title: VHDL error - unresolved signal "dec" is multiply driven, what is this error?
body: <p>So my group have run into an error with our project that gives the error message:</p>
  <p>[XSIM 43-3249] File C:/Users/hp/Desktop/correct_file_WTB/correct_file_WTB/project/project.srcs/sources_1/new/Sports_venue.vhd, line 53. Unresolved signal &quot;dec&quot; is multiply driven.</p>
  <p>We have tried to do some research and I think it's to do with the fact that we are adding together vectors to just a single signal but I could be completely wrong as I am not that well learned on VHDL. I used this web page to research the issue and try to understand it but I'm still confused: <a href="https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-2015-4-Simulator-XSIM-43-3249-Unresolved-signal-quot-from/td-p/777979" rel="nofollow noreferrer">https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-2015-4-Simulator-XSIM-43-3249-Unresolved-signal-quot-from/td-p/777979</a></p>
  <p>I also looked at similar questions asked on this website as well, but I feel the situations were too different to properly implement the solutions into my own code.</p>
  <p>to explain our project to let anyone helping us understand what we are trying to achieve: We are designing 12 counters that will count attendees to a sports game in a generic stadium, the 12 counters count entries to the 12 seating sections for attendees, we then made an adder that will take all the outputs of the counters and add them together to get the total attendance, this ends up being about a 12-bit number or so and we have then converted it to binary coded decimal, and into 4 4-bit numbers in order to send the data to 4 7-segment displays to display each digit of the total attendance.</p>
  <p>Here is the code we have written:</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL;
  
  entity Sports_venue is
    Port(enable_in, reset_in, updown_in : in std_logic_vector(0 to 11);
             seg_1, seg_2, seg_3, seg_4 : out std_logic_vector(3 downto 0));
  end Sports_venue;
  
  architecture Behavioral of Sports_venue is
  
  type counter_output is array (positive range &lt;&gt;) of unsigned (7 downto 0);
  
  component counter
      port(CLK, enable, reset, updown : in std_logic;
                            Q : out unsigned(7 downto 0));
  end component;
  
  
  signal enable, reset, updown : std_logic_vector(1 to 12);
  signal CLK_TB : std_logic;
  signal adder_input : counter_output(1 to 12);
  signal add_output : unsigned(11 downto 0);
  signal dec, z : integer;
  
  begin
  
  CLK_loop : process
      begin
          while now &lt;= 3000ns loop
              CLK_TB &lt;= '1';
              wait for 5 ns;
              CLK_TB &lt;= '0';
              wait for 5 ns;  
          end loop;
          wait;
      end process;
  
  add_output &lt;= unsigned(adder_input(12) + adder_input(1) + adder_input(2) + adder_input(3)
   + adder_input(4) + adder_input(5)+ adder_input(6) + adder_input(7) + adder_input(8) 
   + adder_input(9) + adder_input(10) + adder_input(11));
  
  dec &lt;= to_integer(add_output);
  
     seg_1_loop : process(dec)
     begin
      case dec is
          when 0 to 999 =&gt; z &lt;= 0;
          when 1000 to 1999 =&gt; z &lt;= 1;
          when 2000 to 2999 =&gt; z &lt;= 2;
          when 3000 =&gt; z &lt;= 3;
          when others =&gt; z &lt;= 0;
     end case;
       if( z = 0) then
          seg_1 &lt;= &quot;0000&quot;;
       elsif( z = 1) then
          dec &lt;= dec  - 1000;
          seg_1 &lt;= &quot;0001&quot;;
       elsif(z = 2) then
          dec &lt;= dec - 2000;
          seg_1 &lt;= &quot;0010&quot;;
       elsif(z = 3) then
          dec &lt;= dec - 3000;
          seg_1 &lt;= &quot;0011&quot;;
     end if;
     end process;
  
  counter_gen:
      for i in 1 to 12 generate
          counterX: counter
           port map (CLK =&gt; CLK_TB, enable =&gt; enable(i), reset =&gt; reset(i), updown =&gt; updown(i), Q =&gt; adder_input(i));
      end generate;
  end Behavioral;
  </code></pre>
  <p>I have removed parts of our full code to just show the sections I think we are having problems with, if you feel you need the rest of it I can add the sections again.</p>
  <p>Thank you.</p>