title: ambiguous clock in event control
body: <p>I wrote such verilog code in xilinx vivado:</p>
  
  <pre><code>module a(input clk, input clk1, output reg [4:0] acc)
  initial
  begin
  acc = 5'd0;
  end
  always @ (posedge clk or posedge clk1)
  begin
  acc &lt;= acc+1;
  end
  endmodule  
  </code></pre>
  
  <p>And the error (ambiguous clock in event control) came out when runnning synthesis, and vivado points out that error is in the line "always @ (posedge clk or posedge clk1)". Only one error occurred.
  I wonder why this error come out and how to solve it without changing function of my code. As you can see, I'd like to do something when clk or clk1 turns from 0 to 1.</p>