title: Makefile: Same Rule for multiple Targets
body: <p>I've some targets (lets say 3). So after the makefile has run, I want to have 3 executable files.</p>
  
  <p>Here's what I've done by now:</p>
  
  <pre><code>CC      = gcc
  CFLAGS  = -Wall -pedantic -ansi
  
  ECHO  = server_echo
  ECHO_O = echo.o
  
  FOO = server_foo
  FOO_O = foo.o
  
  ALL = $(ECHO) $(FOO)
  ALL_O = ECHO_O FOO_O
  
  all: $(ALL) 
  
  $(ECHO): $(ECHO_O)
          $(CC) $(CFLAGS) -o $(ECHO) $(ECHO_O)
  
  $(FOO): $(FOO_O)
          $(CC) $(CFLAGS) -o $(FOO) $(FOO_O)
  
  .PHONY: clean
  clean:         
          - rm -f $(ALL)
          - rm -f *.o
          - rm -f core
  
  %.o: %.c
          $(CC) $(CFLAGS) -c $&lt;
  
  .PHONY: mci
  mci: clean $(ALL) 
  </code></pre>
  
  <p>There I've a duplicate of rules for the targets $(ECHO) and $(FOO). Is there any way, that I can eliminate the duplication? Something like:</p>
  
  <pre><code>for target, target_o in $(ALL), $(ALL_O)
  target: target_o
      $(CC) $(CFLAGS) -o target target_o
  end for
  </code></pre>
  
  <p>Or is there another way to solve my Problem?</p>
  
  <p>Thanks for your help</p>