title: defining makefile variables multiple times
body: <p>I read the <a href="https://www.gnu.org/software/make/manual/html_node/Using-Variables.html" rel="nofollow noreferrer">Using Variables</a> section of the GNU make documentation but couldn't understand how make variables are expanded in make rules when they are defined several times.</p>
  
  <p>See, for example, the following short makefile:</p>
  
  <pre><code>.PHONY: run
  run: a b
  
  TARGET := a
  
  $(TARGET):
      echo $(TARGET)
      touch $@
  
  TARGET := b
  
  $(TARGET):
      echo $(TARGET)
      touch $@
  </code></pre>
  
  <p>which yields the following output when running <code>make</code>:</p>
  
  <pre><code>echo b
  b
  touch a
  echo b
  b
  touch b
  </code></pre>
  
  <p>It seems that there is a target for <code>a</code>, and the automatic variable <code>$@</code> is indeed <code>a</code>. But echoing the <code>TARGET</code> variable, which is the target name as well, prints <code>b</code>... What's going on here?
  I'd appreciate any help, preferably with linking to the docs, that clarifies this behavior.</p>
  
  <p>Other questions that are probably related:</p>
  
  <ol>
  <li>Is the makefile read only once when <code>make</code> is invoked?</li>
  <li>Are the target <em>names</em> expanded when the makefile is read or later? </li>
  <li>Are the target <em>rules</em> expanded when the makefile is read or later?</li>
  </ol>
  
  <p>Note: using recursively expanded variable (that is, changing <code>:=</code> to <code>=</code>) doesn't change the output in the above example.</p>