title: variable must be constrained error
body: <p>I am getting an error and I don't understand why.</p>
  
  <p>my code :</p>
  
  <pre><code> library ieee;
  use ieee.std_logic_1164.all;
  use work.Func_Pack.all;
  use ieee.std_logic_arith.all;
  use IEEE.std_logic_unsigned.ALL;
  --use ieee.numeric_std.all;
  entity letters_arranger   is
  port (
  clock, reset,start,rdy_to_get_new_letter  :in   std_logic; -- asuuming clock is 27 M Hz
   select_input : in integer;      
  
   reg : out std_logic_vector(7 downto 0); 
   drive_letter : out std_logic
   );
  
  end letters_arranger ;
  architecture behave of letters_arranger is
      type state is (idle, set_str, send_str,endstring); 
      signal cur_state: state;
      --signal str :string :="                                              "&amp;CR;
      signal str :string :="                                              "&amp;CR;   
      signal counter :integer;
  
      constant letters_max : integer := 47;
  
  begin
  
  
  pro:process(clock,reset)
  variable data_count : integer range 0 to 10 :=0;
  begin
  if (reset='1') then             
      cur_state &lt;= idle; 
  
  
  elsif  rising_edge(clock) then 
  case cur_state is
  
      when idle=&gt; 
  
          drive_letter&lt;='0';
  
          if start = '1' then
           cur_state &lt;= set_str;
           counter&lt;=0;
  
          elsif counter = letters_max then
              cur_state &lt;= endstring;
  
  
          elsif rdy_to_get_new_letter ='1' then
           cur_state &lt;= send_str;
          end if;
  
      when set_str =&gt;     
          str &lt;= select_str(select_input);
          counter&lt;=1;-- check char pos indx start fr 0 or 1
  
      when send_str =&gt;
          cur_state &lt;= idle;
          if counter&lt;=str'length then
              counter&lt;=counter+1;
          end if;     
          reg&lt;=conv_std_logic_vector(character'pos(str(counter)),8);      
          drive_letter&lt;='1';
  
      when    endstring =&gt;
  
          --need to do something
  
          cur_state &lt;= idle;
  
  
      when others =&gt; null;
  end case; 
  end if;  
  end process;
  
  end behave;
  </code></pre>
  
  <p>and my funcpack (only the function select_str is relevant I believe ):</p>
  
  <pre><code>------------------------ Func_Pack.vhd program ------------------------------------
  LIBRARY IEEE;
  USE ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_unsigned.all;
  PACKAGE Func_Pack IS
  
  ------------Type Decalration ---------------
  SUBTYPE byte IS std_logic_vector(7 downto 0);
  TYPE special_message IS array(0 to 4,0 to 100) OF byte; 
  --------------------------------------------
  
  FUNCTION Parity_calc ( data : std_logic_vector(7 downto 0) )RETURN std_logic ;
  FUNCTION To_7Seg ( data:integer range 0 to 9)RETURN std_logic_vector;   
     FUNCTION select_str ( indx:integer range 0 to 9) RETURN string;
  END Func_Pack;
  ----------------------------------------------------------------------------------------------------------------------------
  PACKAGE BODY Func_Pack IS
  
  --parity_calc--
      FUNCTION Parity_calc ( data : std_logic_vector(7 downto 0) )RETURN std_logic IS
  VARIABLE temp : std_logic ;
  BEGIN
      temp := data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7);
      return (temp);
  end parity_calc;
  
  -----------------------------------------------------------------------------    ------------     
   ------------------ To 7eg  Convert function ---------------------------------------------
   FUNCTION To_7Seg ( data:integer range 0 to 9)RETURN std_logic_vector IS
  VARIABLE temp:std_logic_vector (6 downto 0):=(others=&gt;'1');
  BEGIN
  CASE     data  IS
      WHEN  0 =&gt; temp :="1000000";    -- 40h
      WHEN  1 =&gt; temp :="1111001";    -- 79h
      WHEN  2 =&gt; temp :="0100100";    -- 24h
      WHEN  3 =&gt; temp :="0110000";    -- 30h
      WHEN  4 =&gt; temp :="0011001";    -- 19h
      WHEN  5 =&gt; temp :="0010010";    -- 12h
      WHEN  6 =&gt; temp :="0000010";    -- 02h
      WHEN  7 =&gt; temp :="1111000";    -- 78h
      WHEN  8 =&gt; temp :="0000000";    -- 00h
      WHEN  9 =&gt; temp :="0010000";    -- 10h
      WHEN OTHERS =&gt; NULL;
  END CASE;
  RETURN (temp);
  END To_7Seg;
  
  FUNCTION select_str ( indx:integer range 0 to 9) RETURN string IS
  VARIABLE temp:string; 
  BEGIN
  CASE     indx  IS
      WHEN  0 =&gt; temp :="                                              "&amp;CR;  
      WHEN  1 =&gt; temp :="V18                                           "&amp;CR;  
      WHEN  2 =&gt; temp :="w300                                          "&amp;CR;  
      WHEN  3 =&gt; temp :="SPlease Choose 1 Branch line Out Of 3 Possible"&amp;CR;  
      WHEN  4 =&gt; temp :="SYou chose  Branch Number 1                   "&amp;CR;  
      WHEN  5 =&gt; temp :="SYou chose  Branch Number 2                   "&amp;CR;  
      WHEN  6 =&gt; temp :="SYou chose  Branch Number 3                   "&amp;CR;  
  
      WHEN OTHERS =&gt; temp:="                                              "&amp;CR;   
  END CASE;
  RETURN (temp);
  END select_str;
  
  
  -----------------------------------------------------------------------------------
  
  
  --"V18"
  --"W300"
  --
  --"SPlease Choose 1 Branch line Out Of 3 Possible" -- 46 .
  --"SYou Choosed  Branch Number 1"
  --"SYou Choosed  Branch Number 2"
  --"SYou Choosed  Branch Number 3" --29
  --"SConnecttinngg" -- 14
  --"SI Am Sorry I Couldn't Find the Branch , you tried to Reach"    --59
  --13 -- =D in hex == &lt;cr&gt; . must be sent in the end of each line
  --
  --type message_preset is record
  --  speed: is array(0 to 2) of byte ;
  --  volume: is array(0 to 3) of byte;
  --  cr : is integer range 0 to 255;
  --end record;
  --signal message_set : message_preset := (,,);
  -------------------------------------------------------------------------    --------- 
  END Func_Pack;
  </code></pre>
  
  <p>when running the first code as top-level entity i get this error :</p>
  
  <p>VHDL error at letters_arranger.vhd(21) variable must be constrained .
  line 21 is this line </p>
  
  <blockquote>
  <pre><code>  signal str :string :="                                              "&amp;CR;   
  </code></pre>
  </blockquote>