title: How do I define a module with a parameter in Verilog?
body: <p>I want to define an <code>add</code> module which has a parameter, but my declaration of the new instance doesn't go well.</p>
  
  <p>I want to define an instance of this module:</p>
  
  <pre><code>module add #(parameter wd=1) (input wire [wd-1:0] a,b, output wire [wd-1:0] o);
  
     assign o = a + b;
  
  endmodule
  </code></pre>
  
  <p>I tried this line, but I get an error:</p>
  
  <pre><code> add len_plus_1 #(8)(.a(len),.b(8'h1),.o(lenPlus1));
  </code></pre>