title: How to emulate $display using Verilog Macros?
body: <p>I want to create a macro with multiple parameters just like $display.</p>
  
  <p>My code looks like this but it doesn't work.</p>
  
  <pre><code>               `define format_macro(A) \
                        $write("%s", $sformatf(A)); \
  </code></pre>
  
  <p>This is how I called format_macro.</p>
  
  <pre><code>               `format_macro("variable = %d", variable)
  </code></pre>
  
  <p>How can I do this?</p>