title: How do I use assert in VHDL correctly?
body: <p>I have in VHDL a code segment which makes me unsure if it's right:
  a and b are std_logic_vectors. c1 and c0 are std_logic. Is this correct written? Especially the part "c1 = '1' and c0 = '0'" struggels with me.</p>
  
  <pre><code>if unsigned(a) &gt; unsigned(b) then
      assert(c1 = '1' and c0 = '0')
  </code></pre>
  
  <p>Edit: Here is a bigger code segment:</p>
  
  <pre><code>    signal a: std_logic_vector(3 downto 0);
      signal b: std_logic_vector(3 downto 0);
      signal c1: std_logic;
      signal c0: std_logic;
  
      begin
      TEST: forBitComperator port map(a, b, c1, c0);
        process
        begin
          for i in 0 to 2**4-1 loop
              for k in 0 to 2**4-1 loop
  
                  wait for 0 ns;
  
                  a &lt;= conv_std_logic_vector(i, 4);
                  b &lt;= conv_std_logic_vector(k, 4);
  
                  if i &gt; k then
                    assert c1 = '1' and c0 = '0'
                    report "error ";
                 end if;
          end loop;
      end loop;
      wait;
    end process;
  end;
  </code></pre>