title: How to drive the DDS Compiler IP core from Xilinx
body: <p>I completed <a href="http://antonpotocnik.com/?p=514765" rel="nofollow noreferrer">Anton Potočniks' introductory guide</a> to the red pitaya board and I am now able to send commands from the linux machine running on the SoC to its FPGA logic.</p>
  
  <p>I would like to further modify the project so that I can control the phase of the signal that is being transmitted via the red pitayas' DAC. Some pins (from 7 down to 1) of the first GPIO port were still unused so I started setting them from within the OS and used the red pitaya's LEDs to confirm that they were being set without interfering with the functionality of Anton Potočnik's "high bandwidth averager".</p>
  
  <p>I then set the <a href="https://www.xilinx.com/support/documentation/ip_documentation/dds_compiler/v6_0/pg141-dds-compiler.pdf" rel="nofollow noreferrer">DDS_compilers'</a> to Phase Offset Programmability to "streaming" mode so that it can be configured on the fly using the bits that are currently controling the red pitaya's LEDs. I used some slices to connect my signals to the <a href="https://github.com/apotocnik/redpitaya_guide/blob/master/cores/axis_constant_v1_0/axis_constant.v" rel="nofollow noreferrer">AXI4-Stream Constant</a> IP core, which in turn drives the DDS compiler.</p>
  
  <p><a href="https://i.stack.imgur.com/Mz89E.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/Mz89E.png" alt="my current setup"></a></p>
  
  <p>Unfortunately the DAC is just giving me a constant output of 500 mV.</p>
  
  <p>I created a new project with a  testbench for the DDS compiler, because synthesis takes a long time and doesn't give me much insight into what is happening.</p>
  
  <p><a href="https://i.stack.imgur.com/1KyiP.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/1KyiP.png" alt="simulation results from a testbench containing the DDS compiler"></a></p>
  
  <p>Unfortunately all the output signals of the DDS compiler are undefined.</p>
  
  <p>My question:</p>
  
  <p>What am I doing wrong and how can I proceed to control DACs' phase?</p>
  
  <hr>
  
  <p>EDIT1; <a href="https://www.dropbox.com/s/bpbrxzlnb02ns7j/edit1.txt?dl=0" rel="nofollow noreferrer">here</a> is my test bench</p>
  
  <p>The IP core is configured as follows, so many of the control signals that I provided should not be required:</p>
  
  <p><a href="https://i.stack.imgur.com/KAkxa.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/KAkxa.png" alt="IP core configurations"></a></p>
  
  <hr>
  
  <p>EDIT2; I changed declarations of the form <code>m_axis_data_tready =&gt; '0'</code> to <code>m_axis_phase_tready =&gt; m_axis_phase_tready_signal</code>. I also took a look at the wrapper file called <code>dds_compiler_0.vhd</code> and saw that it treats both <code>m_axis_phase_tready</code> and <code>m_axis_data_tready</code> as inputs.</p>
  
  <p>My simulation results remained unchanged...</p>
  
  <p>My new test bench can be found <a href="https://www.dropbox.com/s/tv8rnlmp22fp694/edit2.txt?dl=0" rel="nofollow noreferrer">here</a>.</p>
  
  <hr>
  
  <p>EDIT3: Vivado was just giving me the old simulation results - creating a new testbench, deleting the file under <code>&lt;project_name&gt;.sim/sim_1/behav/xsim/simulate.log</code> and restarting vivado solved this problem.</p>
  
  <p>I noticed that the wrapper file (<code>dds_compiler_0.vhd</code>) only has five ports:</p>
  
  <ol>
  <li><code>aclk</code> (in)</li>
  <li><code>s_axis_phase_tvalid</code> (in)</li>
  <li><code>s_axis_phase_tdata</code> (in)</li>
  <li><code>m_axis_data_tvalid</code> (out)</li>
  <li>and <code>m_axis_data_tdata</code> (out)</li>
  </ol>
  
  <p>So I removed all the unnecessary control signals and got a new simulation result, but I am still not recieving any useful output from the dds_compiler:
  <a href="https://i.stack.imgur.com/vc8t2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vc8t2.png" alt="without control signals"></a></p>
  
  <p>The corresponding testbench can be found <a href="https://www.dropbox.com/s/ushbs553h165lnx/edit3_no_control_signals.txt?dl=0" rel="nofollow noreferrer">here</a>.</p>
  
  <p>I also don't get any valid output when I include the control signals.
  <a href="https://i.stack.imgur.com/tUnVV.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/tUnVV.png" alt="with control signals"></a></p>
  
  <p>The corresponding testbench can be found <a href="https://www.dropbox.com/s/fbhsbi9fpo2fef4/edit3_control_signal_part.txt?dl=0" rel="nofollow noreferrer">here</a>.</p>