title: VHDL Clock Divider: Counter - Duty Cycle
body: <p>I am new to VHDL. I was given this code on how to generate a clock signal of 1Hz (50 % duty cycle) from input clock signal of 24 MHz. I have some questions for more clarification.</p>
  
  <ol>
  <li>How is the counter limit chosen? in the below case, 12000000. What
  would this limit be if I want generate an 8Hz clock signal.    </li>
  <li><p>How should the code be adjusted if I wanted to change the duty cycle
  to 80% ?</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  entity clock is
     port ( CLKin: in std_logic;
            reset: in std_logic;
            CLKout: out std_logic);
  end clock;
  architecture arch of clock is
  
    signal counter: integer:=0;
    signal temp : std_logic := '1';
  begin
  process(CLKin,counter,reset)
  begin
     if(reset='0') then counter&lt;=0; temp&lt;='1';
      elsif(CLKin'event and CLKin='1') then counter &lt;=counter+1;
       if (counter = 12000000) then temp &lt;= NOT temp; counter&lt;=0;
       end if;
      end if;
     CLKout &lt;= temp;
  end process;
  end arch;
  </code></pre></li>
  </ol>