title: Why can't functions have delays?
body: <p>Verilog and VHDL both prohibit delays in functions. Also, tasks/procedures cannot have a return value. This means code like this:</p>
  
  <pre><code>if (my_function(arg) &gt; 0) begin (...) end
  </code></pre>
  
  <p>must be replaced by</p>
  
  <pre><code>int r;
  my_task(arg, r);
  if (r &gt; 0) begin (...) end
  </code></pre>
  
  <p>if delays are needed. Why this limitation? It appears that even SystemVerilog class member functions have it, which makes little sense to me.</p>
  
  <p>For synthesis delays can obviously not be supported, but having the synthesis tool produce an error when encountering a delay would be perfectly acceptable, like it does for delays in <code>always</code>/<code>process</code> blocks.</p>