title: No actual for constant interface in vhdl
body: <p>I have the following entity, core, containing one of my components, generator. I pass generator a signal that is made from the sum of the generic m_r of core and the signal start of core.</p>
  <p>However upon trying to compile this, I get the error <code> error: no actual for constant interface &quot;m_r&quot;</code> pointing me to the line <code>generator_imp : generator</code>. I assume it has something to do with start_generator being composed of m_r, however even after googling for a few hours, I have been able to find very little related to this specific problem. Has anyone encountered something like this before?</p>
  <p>File the error stems from:</p>
  <pre><code>
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  use work.my_components.all;
  
  entity core is
    generic (
      m_r : unsigned(31 downto 0)  := x&quot;00000001&quot;;
      step  : unsigned(31 downto 0)
    );
    port (
      clk              : in std_logic;
      reset            : in std_logic;
      start            : in unsigned(31 downto 0);
      f                : out std_logic
    );
  end core;
  
  architecture arch of core is
  
    signal start_generator       : unsigned(31 downto 0) := x&quot;00000000&quot;;
    signal n                     : std_logic;
  
  begin
  
    start_generator &lt;= m_r + start;
  
  generator_imp : generator
    generic map(
      step  =&gt; step
    )
    port map(
      clk               =&gt; clk,
      start             =&gt; start_generator,
      reset_in          =&gt; reset,
      padded_message    =&gt; padded_chunk,
      n                 =&gt; n
    );
  
  end arch;
  
  
  </code></pre>
  <p>my_components package:</p>
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  package my_components is
  
  
      component generator is
          generic (
            step  : unsigned(31 downto 0)
          );
          port (
            clk                 : in    std_logic;
            start               : in    unsigned(31 downto 0);
            reset_in            : in    std_logic;
            padded_message      : out   std_logic_vector(511 downto 0);
            n                   : out   unsigned(31 downto 0)
          );
      end component;
  end package my_components;
  
  </code></pre>
  <p>Additionally, the entity core is generated within another component &quot;all&quot; using a for generate loop, as described below. It is also part of the my_components package, but for the sake of keeping this code overseeable I have removed it after thouroughly checking that all port names in the component match the entity. The for-generate loop works like below:</p>
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  use work.my_components.all;
  
  entity all is
    port (
      clk : in std_logic
    );
  end all;
  
  architecture Behavioral of all is
  
    constant count : integer := 5;
    type f_array is array (0 to count -1) of std_logic;
    signal f_signals : found_array;
  
    signal reset         : std_logic := '0';
  
    signal start         : unsigned(31 downto 0) := x&quot;11111111&quot;;
  begin
  
    generate_cores : for I in 1 to mining_core_count - 1 generate
      core_imp: core
        generic map(
          m_r =&gt; to_unsigned(I,32),
          step  =&gt; to_unsigned(count, 32)
        )
        port map(
          clk           =&gt; clk,
          reset         =&gt; reset,
          start         =&gt; start,
          f             =&gt; f_signals(I)
        );
    end generate;
  
    core_zero : core
    generic map(
      m_r =&gt; x&quot;00000000&quot;,
      step  =&gt; to_unsigned(count, 32)
    )
    port map(
      clk           =&gt; clk,
      reset         =&gt; reset,
      start         =&gt; start,
      f             =&gt; f_signals(0)
    );
  
  end Behavioral;
  
  
  </code></pre>