title: How to assign value of signal to out port?
body: <p>I have been trying to assign a value of a signal to an out port. I'm getting the proper output of seconds for the signal when I simulate the design but as soon as I assign the value of signal to out port it gives me a WARNING. This warning is pasted below. I have tried using the signal and outport both keeping <code>std_logic</code> but still get the same error. </p>
  
  <p>I believe one from you will have my answer.</p>
  
  <p>Thanks in advance.</p>
  
  <blockquote>
    <p>FF/Latch has a constant value of 0 in block . <br/>
            This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . <br/>
            This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . <br/>
            This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . <br/>
            This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . <br/>
            This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . <br/>
            This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . <br/>
            This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . <br/>
            This FF/Latch will be trimmed during the optimization process.</p>
  </blockquote>
  
  <p>Here's my code!</p>
  
  <pre><code>    library IEEE;
      use IEEE.STD_LOGIC_1164.ALL;
      use IEEE.STD_LOGIC_ARITH.ALL;
      use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
      entity clock is
         port ( CLKin: in std_logic;
                CLKout: out std_logic);
      end clock;
  
      architecture arch of clock is
  
        signal counter: integer:=0;
        signal temp : std_logic := '1';
  
      begin
  
        process(CLKin,counter,temp)
        begin
          if(CLKin'event and CLKin='1') then
            counter &lt;=counter+1;
            if (counter = 50000000) then
              temp &lt;= NOT temp; 
              counter&lt;=0;
              CLKout &lt;= temp;
            end if;
          end if;
        end process;
      end arch;
  </code></pre>