title: When does verilog use values from the current and when from the previous timeslot?
body: <p>Here is a short example code, which confused me. What is the rule to use values from the current or when from the previous simulation time-slot in verilog processes?</p>
  
  <pre><code>module test();
  
      reg clk, rst, r1, r2, r3;
  
      initial begin
          clk = 0;
          rst = 0;
          r1 = 0;
          r2 = 0;
          r3 = 0;
  
          @(posedge clk)
          rst = 1;
      end // initial
  
      always #5 begin : clkgen
          clk = ~clk;
      end
  
  
      /** TESTS **/
  
      // PREVIOUS
      always @(posedge clk) begin : proc_non_block
          r1 = rst;
      end
  
      // CURRENT
      always @(posedge clk or posedge rst) begin : proc_async
          r2 &lt;= rst;
      end
  
      // PREVIOUS
      always @(posedge clk or negedge rst) begin : proc_async_neg
          r3 &lt;= rst;
      end
  
  endmodule // test
  </code></pre>
  
  <p>Here is the result of the simulation. (Questasim 10.4C)
  <a href="https://i.stack.imgur.com/mVNHJ.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/mVNHJ.png" alt="Sumulation result (Questasim 10.4C)"></a></p>
  
  <p>Experiments above shows me that the current value of a given signal is used only if the given signal has an active event at the current simulation time-slot. Am I right? Any details?</p>