title: VHDL: counter checking
body: <p>I want to detect a external signal connection to a CPLD (only connected or not connected). My system clock is 1MHz and external signal is 4KHz. I have developed a logic that will detect rising edge of external signal and start a counter. If the counter is counting then external signal is connected and if the counter is not counting then external signal is not connected. I write the code but its not working, what is the problem? I am beginner in VHDL. Please help, How to check a counter running in vhdl?</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.numeric_std.all;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity SYNC_detection1 is
  Port (  SYNC        : in  STD_LOGIC;
              CLK     : in  STD_LOGIC;
              EDGE        : out  STD_LOGIC;
              OUTPUT  : out  STD_LOGIC;
              BITSOUT : out  STD_LOGIC_VECTOR (3 downto 0)
                  );
  end SYNC_detection1;
  
  architecture workingarchi of SYNC_detection1 is
  
  signal SYNC_reg : std_LOGIC := '0';
  signal SYNC_edge : std_LOGIC := '0';
  signal TEMP : std_LOGIC := '0';
  signal counter : STD_LOGIC_VECTOR (3 downto 0);
  
  begin
  
  SYNC_edge_p : process(CLK) 
  begin
      if (rising_edge(CLK)) then
          SYNC_reg &lt;= SYNC;
      end if;
  end process;
  
  SYNC_edge &lt;= not SYNC_reg and SYNC;
  
  counter_p: process(CLK) 
  begin
      if (rising_edge(CLK)) then
          if SYNC_edge = '1' then
              counter &lt;= counter + 1; 
                  if (counter = "0000") then
                  TEMP &lt;= '1';
                  end if;
          end if;
      end if;
  end process;
  
  OUTPUT &lt;= TEMP;
  BITSOUT &lt;= counter;
  EDGE &lt;= SYNC_edge;
  end workingarchi;
  </code></pre>