title: Verilog: Concatenation with unsized literal, but why?
body: <p>My project finally compiles without errors, but the warnings are "hungry and numerous". For example, I have this line:</p>
  
  <pre><code>  i_temp_reg &lt;= {{SPI_WIDTH{'b0}}, i_temp_reg[BANK_DATA_WIDTH-1:SPI_WIDTH]};
  </code></pre>
  
  <p>Where I have the parameters defined as:</p>
  
  <pre><code>  parameter SPI_WIDTH                   = 8;
    parameter BANK_DATA_WIDTH             = 32;
  </code></pre>
  
  <p>i_temp_reg is a register, as the name might suggest. I have several more statements like this (same format, different registers) and all of them get the error:</p>
  
  <pre><code>  Concatenation with unsized literal; will interpret as 32 bits
  </code></pre>
  
  <p>But I thought I pretty clearly specified the size of this literal (the 'b0). So what's going on, Verilog? I must say here that I use VHDL normally, and I'm fairly comfortable with it and this crazy language is driving me a bit insane. Did I mess up the sizing of this literal? </p>
  
  <p>Secondly, and kind of related, I get another problem. Here are relevant statements and the warning:</p>
  
  <pre><code> output     [BANK_SIZE-1:0]             wAddr;
   reg        [BANK_SIZE-1:0]             i_wAddr;
  
   assign w_Addr          = i_wAddr;
  
   Warning: Result of 4-bit expression is truncated to fit in 1-bit target.
  </code></pre>
  
  <p>If someone could help me with identifying what I'm doing wrong exactly, I would really appreciate it.</p>