title: How to identify synchronous resets (in verilog)
body: <p>I'm new to EDA and I have the following verilog code and i need to identify the synchronous reset clearly.</p>
  
  <pre><code>module test(clk,d,rst,a);
    input clk,d,rst;
    output reg a;
  
    always @(posedge clk)
    begin
      if(rst)
        a &lt;= 1'b0;
      else
        a &lt;= 1'b1; // assigned to a constant
    end
  endmodule
  </code></pre>
  
  <p>is 'rst' a reset (synchonous) ?</p>