title: VHDL : mux output not following inputs when it comes to clock signals
body: <p>I'm creating an architecture to drive a stepper motor using an FPGA board with a L297 controller. So in order to change the speed i created a clock divider to change the clock frequency taken by the L297. The clock divider works just fine. My problem is that I created mutiple clock outputs, one of which will be selected using Push-buttons on the board, so when i connect those signals to the MUX the output is not tottaly correct when it comes to clock input signals but it works fine with STD_LOGIC. 
  This is the code i used for the MUX</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_unsigned.all;
  use IEEE.NUMERIC_STD.ALL;
  
  entity TEST_MUX is
  Port ( A : in  STD_LOGIC;
         B : in  STD_LOGIC;
         C : in  STD_LOGIC;
         D : in  STD_LOGIC;
         E : in  STD_LOGIC;
         choice_select : in  STD_LOGIC;
         choice_valid : in  STD_LOGIC;
         choice_reset : in  STD_LOGIC;
         Choice : out  STD_LOGIC);
    end TEST_MUX;
  
   architecture Behavioral of TEST_MUX is
  
  signal count : integer  := 0;
  signal S_out : STD_LOGIC ;
  
   begin
  
   process ( choice_select , choice_valid, choice_reset,A,B,C,D,E)
     begin
  if (choice_reset = '0') THEN
              count &lt;=0;
              S_out &lt;= 'Z';
              else
              if (choice_select'event) and (choice_select ='1')  THEN
                      count &lt;= count + 1;
                          if (choice_valid = '1')  THEN
                              case count is
                              when  1=&gt;  S_out&lt;=A ; 
                              when  2=&gt;  S_out&lt;=B ;  
                              when  3=&gt;  S_out&lt;=C ; 
                              when  4=&gt;  S_out&lt;=D; 
                              when  5=&gt;  S_out&lt;=E ;   
                              when others =&gt;   S_out &lt;= 'Z';
                              end case;
                          end if;
             end if;
  end if;                                         
  end process;
  
  Choice&lt;=S_out;
  
  end Behavioral;
  </code></pre>
  
  <p>Here is the correct simulation result when the input are STD_LOGIC :
  <a href="https://i.stack.imgur.com/FkhoJ.png" rel="nofollow noreferrer">enter image description here</a></p>
  
  <p>Here with inputs forced as clock:
  <a href="https://i.stack.imgur.com/XkqDw.png" rel="nofollow noreferrer">enter image description here</a>
  Thank you for you help</p>