title: What are the control instructions and move instructions latency for Intel's newer architectures?
body: <p>I am looking at the <a href="https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf" rel="nofollow noreferrer">Intel Architectures Optimization Reference Manual 2017</a> (Page 759). I am looking for Haswell and Skylake architectures. <code>MOV, PUSH, JMP, CALL</code> instructions are intentionally omitted in that table. No latency information is given. Why is that? Although, those instruction latency is given for the Atom processors on page 776.</p>
  
  <p>Interestingly the <a href="https://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf" rel="nofollow noreferrer">2012 optimization manual</a> from Intel has <code>MOV</code>, <code>PUSH</code> and <code>CALL</code> instructions latency.</p>
  
  <p>Agner's <a href="http://www.agner.org/optimize/" rel="nofollow noreferrer">instruction tables</a> provides latency for <code>MOV</code> and <code>PUSH</code>, but skips for control instructions like <code>JMP</code> and <code>CALL</code>. Any idea why is that?</p>