title: describing clocked SR Latch with verilog
body: <p>I'm trying to describe a clocked SR-Latch with NAND gates in Verilog.  However, when I simulate it, all the outputs become Z, and I don't know why.</p>
  
  <p>Verilog code and the testbench:</p>
  
  <pre><code>module CLOCKED_SR(input clk, s, r, output q, qbar);
    wire i, j;
    nand #20 (s, clk, i);
    nand #20 (r, clk, j);
    nand #20 (qbar, j, q);
    nand #20 (q, i, qbar);
  endmodule
  
  module Q1_test();
    reg clk, s, r;
    wire qbar, q;
    CLOCKED_SR T_SR(clk, s, r, qbar, q);
    initial begin
      #20 clk = 1;
      #50 s = 0; r = 0;
      #50 s = 0; r = 1;
      #50 s = 1; r = 0;
      #50 $stop;
    end
  endmodule
  </code></pre>