title: Cycles/cost for L1 Cache hit vs. Register on x86?
body: <p>I remember assuming that an L1 cache hit is 1 cycle (i.e. identical to register access time) in my architecture class, but is that actually true on modern x86 processors?</p>
  
  <p>How many cycles does an L1 cache hit take? How does it compare to register access?</p>