title: Difference between block and process statement in VHDL
body: <p>I recently ran into a question regarding VHDL block and process structures and didn't find any explanation in text books or internet forums.<br>
  Is there any difference between the block and the process statements in the codes bellow?</p>
  
  <pre><code>library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity example is
      port ( a, b, clock : in  std_logic;
             c           : out std_logic);
  end entity;
  
  architecture rtl of example is
  
  begin
      test_block : block (clock'event and clock = '1')
      begin
          c &lt;= guarded a and b;
      end block test;
  end rtl;
  </code></pre>
  
  <p>and</p>
  
  <pre><code>library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity example is
      port ( a, b, clock : in  std_logic;
             c           : out std_logic);
  end entity;
  
  architecture rtl of example is
  
  begin
  
      test_proc : process (clock)
      begin
          if (clock'event and clock = '1') then
              c &lt;= a and b;
          end if;
      end process test_proc;
  
  end rtl;
  </code></pre>