title: Makefile: Passing command line arguments to file inside Makefile
body: <p>Inside my Makfile I have the following, </p>
  
  <pre><code>smktestrun: smktest
      @../projects/test.sh
  </code></pre>
  
  <p>And I call this using: </p>
  
  <pre><code>Make smktestrun
  </code></pre>
  
  <p>But sometimes I need to pass an parameter/argument along with this file (test.sh)</p>
  
  <p>So basically I would like: </p>
  
  <pre><code>test.sh -abc
  </code></pre>
  
  <p>But if i just pass the argument in the Makefile itself, the argument is not taken as simply the sheel script is executed. </p>
  
  <p>So is  there a way I could specify in the Makefile that an argument needs to be passed with that file?</p>
  
  <p>Thanks.</p>