title: Systemverilog interface - nested interface vs modport
body: <p>Can I use a nested interface in place of a modport?</p>
  
  <p>The purpose of this is large-scale interconnect of many different modules while taking advantage of interfaces to simplify connectivity. I prefer not to use generic interfaces ever - they are hard to follow in source code.</p>
  
  <p>If I have a generic module that is used by many modules (eg, reset_synchronizer), then I could define a modport in each interface to define the signals for that module, eg:</p>
  
  <pre><code>interface xyz(input clk, input arst);
      logic srst;
      modport reset_synchronizer_mp (input clk, input arst, output srst);
  endinterface
  </code></pre>
  
  <p>I can define this in each interface where I have the need to synchronize the reset. But when I need to change the reset_synchronizer module, perhaps to pass in an enable, I'd need to update the interface ports (add enable signal), and update each modport in all interfaces that create a modport for the reset_synchronizer.</p>
  
  <pre><code>interface xyz(input clk, input enable, input arst);
      logic srst;
      modport reset_synchronizer_mp (input clk, input enable, input arst, output srst);
  endinterface
  </code></pre>
  
  <p>If instead of modport, I used a nested interface (reset_synchronizer_intf), couldn't I just do this inside the main interfaces:</p>
  
  <pre><code>interface xyz(input clk, input arst);
      logic srst;
      reset_synchronizer_intf reset_synchronizer_mp (clk, arst, srst);
  endinterface
  </code></pre>
  
  <p>And to simplify this (assuming the signal names match):</p>
  
  <pre><code>interface xyz(input clk, input arst);
      logic srst
      reset_synchronizer_intf reset_synchronizer_mp (.*);
  endinterface
  </code></pre>
  
  <p>And to add enable, I'd just be updating the main reset_synchronizer.sv (where the module and interface are defined) and update all interfaces but only at the port list or in the signal declaration:</p>
  
  <pre><code>interface xyz(input clk, input enable, input arst);
      reset_synchronizer_intf reset_synchronizer_mp (.*);
  endinterface
  </code></pre>
  
  <p>This becomes even more attractive when the signals I'm looking for exist in the main interface, but I now want to bring them into some generic module. Eg, a power-gating module that normally only got srst, but now I want to pass in rst as well. I could change this at the interface level of the power-gating module instead of inside each interface.</p>