title: Concurrent If Statements in VHDL
body: <p>I am writing code for comparing a signal to a number of signals at the same time.</p>
  
  <p>Here is the example:</p>
  
  <pre><code>process (CLK, reset)
  if reset = '0' then
      data &lt;= (others =&gt; '0');
  elsif rising_edge (CLK) then 
      if A = B then
           data &lt;= data OR "0001";
      else data &lt;= data AND "1110";
      end if;
  
      if A = C then
          data &lt;= data OR "0010";
      else data &lt;= data AND "1101";
      end if;
  
      if A = D then
          data &lt;= data OR "0100";
      else data &lt;= data AND "1011";
      end if;
  
      if A = E then
          data &lt;= data OR "1000";
      else data &lt;= data AND "0111";
      end if;
  end if;
  end process;
  </code></pre>
  
  <p>I just want to comparing the A to B, C, D and E signals and then turn the associated bits in data on and off. The code I wrote above is not working since the synthesis tool will optimize the B, C and D if statements and only leaving the E if statement. I have also thought about using case - when statement but it doesn't have a mechanism to turn off the associated single bit off. When others can only turn all 4 bits off. What is the effective way to do this? Thanks!</p>
  
  <p>BTW, are all these 4 if statements run at the same time? Or they are run at different cycles? I guess they would run one by one, otherwise it would cause fan-in. </p>