title: How to force makefile to include a library
body: <p>I use the Intel_safe_string_lib, that is compiled as static (it is a &quot;problem&quot; of this library, it can't be compiled as shared as i would).</p>
  <p>I made a library that uses this intel_safe_string_lib, and this library is compiled as shared.</p>
  <p>Now i'm creating an application that usess my library, and  in the makefile i included my library and the intel one.</p>
  <p>But at linking, the make tells me that, in my library, can't find the reference to the function of the intel lib that i use in my library (/usr/bin/ld: /usr/lib/gcc/x86_64-linux-gnu/8/../../../x86_64-linux-gnu/libutils.so: undefined reference to `strcat_s'     libutils.so is my library).</p>
  <p>Now i tried in my application to use a function of the intel lib (the strcat_s), the make goes smooth, so i think that Make &quot;thinks&quot; that is better not to link the intel library if not necessary (it is necessary in the library, but not, if not for that test, in my application).</p>
  <p>There is a way to &quot;force&quot; Make to use a library, even it is not directly needed?</p>
  <p>I'm temporarly using a useless call to strcat_s in my application to make it compile, but i would have a more elegant way.</p>
  <p>EDIT: this is my makefile</p>
  <pre><code>TARGET = data_scraper
  LIBS = -lpq -llogger -lsafestring -ldaemonizer -lutils
  CC = gcc
  CFLAGS = -Wall -g -o3
  
  .PHONY: clean all default
  
  default: $(TARGET)
  all: default
  
  OBJECTS = $(patsubst %.c, %.o, $(wildcard *.c))
  HEADERS = $(wildcard *.h)
  
  %.o: %.c $(HEADERS)
          $(CC) $(CFLAGS)  -c $&lt; -o $@
  
  .PRECIOUS: $(TARGET) $(OBJECTS)
  
  $(TARGET): $(OBJECTS)
         $(CC) $(OBJECTS) $(LIBS) -o $@
  
  clean:
      -rm -f *.o
      -rm -f $(TARGET)
  </code></pre>