title: Is it possible to shift more than 1 bit per cycle in verilog?
body: <p>I am not sure whether more than 1 cycle is needed, and if I will need to account for a shift taking more than 1 cycle to complete. And if it is possible to shift more than 1 bit at a time, does shifting 1 bit take he same amount of delay/gate time as shifting multiple bits?</p>