title: What is this variable in the Makefile?
body: <p>So here is a Makefile I have been given, with comment I have added.</p>
  
  <pre><code>MF= Makefile_c  #name of the makefile
  CC= cc          #compiler to use
  CFLAGS= -g      #flags to use
  LFLAGS= -lm     #flags to use after the thingy
  EXE=    hello   #name to give the executable
  INC= \          # ??? What's this for ???
  #   No user-defined include files at present - list here if required.
  # name of the source file
  SRC= \
      hello.c
  
  #delete default suffix
  .SUFFIXES:
  #define the suffixes we are interested in
  .SUFFIXES: .c .o
  OBJ=    $(SRC:.c=.o)    # names to give the object files
  #The .o files depend on the .c files. Compile the object files.
  .c.o:
      $(CC) $(CFLAGS) -c $&lt;
  
  all:    $(EXE)    #The output is the executable
  
  $(OBJ): $(INC)    #The objects depend on whatever INC is
  
  # The executable depends on the object files. build it from the object files.
  $(EXE): $(OBJ)
      $(CC) $(CFLAGS) -o $@ $(OBJ) $(LFLAGS)
  
  # ??? the object files depend on the makefile???
  $(OBJ): $(MF)
  
  # remove any old executables or object files.
  clean:
      rm -f $(OBJ) $(EXE) core
  </code></pre>
  
  <p>I am still learning about makefiles so please correct me if I have misidentified anything. The makefile works fine But I want to adapt it to work with my program that has multiple files and header files. I suspect that the variable <code>$INC</code> will somehow make this possible, but so far my attempts to use it have not worked. </p>
  
  <p>For now I would like to understand what this makefile is trying to do, cn you tell me what <code>$INC</code> is for?</p>