title: Substraction in Verilog
body: <p>I am working on a Verilog fixed point adder, using which I will also do the subtraction. When I do the subtraction not always I get the correct result.</p>
  
  <p>For example, 1-1=0, but I get -0.</p>
  
  <p>Kindly have a look on the below mentioned code:</p>
  
  <pre><code>`timescale 1ns/1ps
  
  module adder #(
  //Parameterized values
  parameter Q = 27,
  parameter N = 32
  )
  (
  input [N-1:0] a,
  input [N-1:0] b,
  output [N-1:0] c
  );
  
  reg [N-1:0] res;
  
  assign c = res;
  
  always @(a,b) begin
  // both negative or both positive
  if(a[N-1] == b[N-1]) begin              //Since they have the same sign, absolute magnitude increases
      res[N-2:0] = a[N-2:0] + b[N-2:0];   //So just the two numbers are added
      res[N-1] = a[N-1];                  //and the sign is set appropriately...       
      end     
  //  one of them is negative...
  else if(a[N-1] == 0 &amp;&amp; b[N-1] == 1) begin           //  subtracts a-b
      if( a[N-2:0] &gt; b[N-2:0] ) begin                 //  if a is greater than b,
          res[N-2:0] = a[N-2:0] - b[N-2:0];   
          res[N-1] = 0;                               //  manually the sign is set to positive
          end
      else begin                                      //  if a is less than b,
          res[N-2:0] = b[N-2:0] - a[N-2:0];           // subtracting a from b to avoid a 2's complement answer
          if (res[N-2:0] == 0)
              res[N-1] = 0;                          //   To remove negative zero....
          else
              res[N-1] = 1;                         //        and manually the sign is set to negative
          end
      end
  else begin                                       // subtract b-a (a negative, b positive)
      if( a[N-2:0] &gt; b[N-2:0] ) begin             //  if a is greater than b,
          res[N-2:0] = a[N-2:0] - b[N-2:0];       //      subtracting b from a to avoid a 2's complement answer
          if (res[N-2:0] == 0)
              res[N-1] = 0;                                       
          else
              res[N-1] = 1;                       //      and manually the sign is set to negative
          end
      else begin                                 //   if a is less than b,
          res[N-2:0] = b[N-2:0] - a[N-2:0];       
          res[N-1] = 0;                                   
          end
      end
  end
  endmodule
  </code></pre>
  
  <p>Testbench for the adder is below:</p>
  
  <pre><code>`timescale 1ns/1ps
  
  module tb_adder (
  );
  
  reg clk;
  reg [ 31 : 0 ] a;
  reg [ 31 : 0 ] b;
  
  wire [ 31: 0 ] c;
  
  adder adder_i (
      .a(a),
      .b(b),
      .c(c)
      );
  
  parameter CLKPERIODE = 100;
  
  initial clk = 1'b1;
  always #(CLKPERIODE/2) clk = !clk;
  
  initial begin
  
  $monitor ("adder=%h", c);
  
  #1
      a = 32'h08000000;
      b = 32'hF8000000;
  
    #(CLKPERIODE)
    $finish();
  
  end
  
  endmodule
  </code></pre>
  
  <p>I am having a hard time to find where did I go wrong as I am a newbie in Verilog. I am using this module to calculate Taylor Series in Fixed Point arithmetic. Any suggestions?</p>