title: Recursive self-instantiation component [VHDL]
body: <p>I'm starting a big project in VHDL and I would like to have every basic components (adders, multiplexers, registers, ...) written such that they are as most ordered as possible. </p>
  
  <p>I'm thinking to use different architectures for each entity (to go through different layer of abstraction or different kind of implementation) and then select one using configurations.</p>
  
  <p>My question is: is it possible to recursively self-instantiate a component but with a different configuration?</p>
  
  <p>For example, let's take the adder: </p>
  
  <pre><code>entity ADDER is 
    generic( ... );
    port( ... );
  end entity ADDER;
  </code></pre>
  
  <p>Then I would like to have different kind of architecture, for example:</p>
  
  <pre><code>-- Behavioral Add
  architecture BHV of ADDER is
    out &lt;= A + B;
  end architecture BHV;
  
  
  -- Ripple Carry Adder
  architecture RCA of ADDER is 
    ...
  end architecture RCA;
  
  
  -- Carry Select Adder
  architecture CSA of ADDER is
    component ADDER --   &lt;== this should be configured as RCA
    ...
  end architecture CSA;
  </code></pre>
  
  <p>Is it possible to configure the adder used inside the Carry Select with a Ripple Carry without ending in an infinite instantiation loop?</p>