title: <= Assignment Operator in Verilog
body: <p>What does the <code>&lt;=</code> do in Verilog?</p>
  
  <p>For example:</p>
  
  <pre><code>always @(posedge Clock) begin
     if (Clear) begin
        BCD1 &lt;= 0;
        BCD0 &lt;= 0;
     end
  end
  </code></pre>