title: Atomicity on x86
body: <blockquote>
    <h2>8.1.2 Bus Locking</h2>
    
    <p>Intel 64 and IA-32 processors provide a LOCK# signal that is asserted
    automatically during certain critical memory operations to lock the
    system bus or equivalent link. While this output signal is asserted,
    requests from other processors or bus agents for control of the bus
    are blocked. Software can specify other occasions when the LOCK
    semantics are to be followed by prepending the LOCK prefix to an
    instruction.</p>
  </blockquote>
  
  <p>It comes from Intel Manual, Volume 3</p>
  
  <p>It sounds like the atomic operations on memory will be executed directly on memory (RAM). I am confused because I see "nothing special" when I analyze assembly output. Basically, the assembly output generated for <code>std::atomic&lt;int&gt; X; X.load()</code> puts only "extra" mfence. But, it is responsible for proper memory ordering, not for an atomicity. If I understand  properly the <code>X.store(2)</code> is just <code>mov [somewhere], $2</code>. And that's all. It seems that it doesn't "skip" the cache. I know that moving aligned ( for example ints) to memory is atomic. However, I am confused. </p>
  
  <hr>
  
  <p>So, I have presented my doubts but the main question is:</p>
  
  <h1><strong>How does the CPU implement atomic operations internally?</strong></h1>