title: systemverilog assertion - how to ignore first event after reset
body: <p>I have written following assertion:</p>
  
  <pre><code>    assert property(@(posedge ClkRs_ix.clk) 
          disable iff (ClkRs_ix.reset) $stable(Signal_ia)[*20] |-&gt; 
          (Signal_oq==Signal_ia));
  </code></pre>
  
  <p>I wanted to express that <em>20 clock cycles for which the input signal is stable, at the 21st cycle the output has to have the same value as input.</em></p>
  
  <p>This one works, but only if I assure no changes in the state of Signal_ia during the reset. If I assert reset, change the state of Signal_ia, then release the reset, this condition always fails. This usually happens when I start the simulation with Signal_ia = 'X' and during reset it becomes '0'.</p>
  
  <p>Is there any way how to write this better? Resp. is there a way how to ignore first event after reset, as it might be tripping due to conditions happening at reset? If I understood well, iff assures, that this assertion is ignored during reset. Effects I'm trying to describe have some latency, ideally I would need to ignore this condition not only in reset, but as well 20 cycles following the deassertion of the reset state.</p>
  
  <p>thanks
  .d.</p>