title: std_logic_vector to integer conversion vhdl
body: <p>I faced with conversion problem/I read a lot of similar topics but my code       still not working.Could you pls give me some hints. Quartus give me error:</p>
  
  <blockquote>
    <p>Error (10476): VHDL error at true_dual_port_ram_single_clock.vhd(44): type of identifier "random_num_i" does not agree with its usage as "std_logic_vector" type</p>
  </blockquote>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  use IEEE.std_logic_signed.all;
  use IEEE.std_logic_unsigned.all;
  use IEEE.NUMERIC_STD.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  
  entity write_ram is
    generic(width : integer := 32);
    port(clock_i  : IN  STD_LOGIC;
         we_w     : IN  STD_LOGIC;
         wr_addr  : IN  INTEGER RANGE 0 to 31;
         read_add : IN  INTEGER RANGE 0 to 31;
         q_out    : out STD_LOGIC_VECTOR(2 DOWNTO 0)
    );
  end write_ram;
  
  architecture rtl of write_ram is
    --- Component decalarartion
    component random is
      port(clk        : in  std_logic;
           random_num : out std_logic_vector(width - 1 downto 0) --output vector 
      );
    end component;
  
    component single_clock_ram is
      port(clock         : IN  STD_LOGIC;
           data          : IN  INTEGER RANGE 0 to 31;
           write_address : IN  INTEGER RANGE 0 to 31;
           read_address  : IN  INTEGER RANGE 0 to 31;
           we            : IN  STD_LOGIC;
           q             : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
      );
    end component;
    for all : random use entity work.random(rtl);
    for all : single_clock_ram use entity work.single_clock_ram(rtl);
    Signal random_num_i : INTEGER RANGE 0 to 31; --interanal signals
  begin
    -- Component Instantiation
  
    C1 : random Port map(
        clk        =&gt; clock_i,
        --random_num &lt;=to_integer(to_signed(random_num_i))
        random_num =&gt; random_num_i
      );
    random_num &lt;= to_integer(to_signed(random_num_i)); -- error
  
    C2 : single_clock_ram
      Port map(
        clock         =&gt; clock_i,
        we            =&gt; we_w,
        read_address  =&gt; read_add,
        write_address =&gt; wr_addr,
        data          =&gt; random_num_i,
        q             =&gt; q_out
      );
  
  end rtl;
  </code></pre>