title: How to use "std_logic" after package/package body declaration?
body: <p>I am trying to get better with VHDL, therefore i wanted to try to implement the functions "package ... is" and "package body ... is". 
  When i do this it seems like "std_logic" can't see the contents of the IEEEE library in the step of the GHDL Analysis. </p>
  
  <p>So far i tried the commands with and without code in them -> Same result. 
  Without the "package"-lines it works like a charme...but i won't be able to extend it like planned. </p>
  
  <pre><code>library IEEE;
  use IEEE.std_logic_1164.all;
  
  package run is
      -- some package definitions
  end run;
  
  package body run is
      -- the body
  end run;
  
  entity andfunc is
      Port( A : in std_logic;
          B : in std_logic;
          C : out std_logic
  );
  end andfunc;
  
  architecture Behavioral of andfunc is
  begin
      C &lt;= A and B ;
  end Behavioral;
  </code></pre>
  
  <p>The specific Error Message is: 
  "[...] error: no declaration for "std_logic"</p>
  
  <p>Looking forward to your answers. </p>