title: Verilog bitwise or ("|") monadic
body: <p>I've seen Verilog code where the bitwise or operator ("|") is used monadic. What's the purpose?</p>
  
  <p>For example</p>
  
  <pre><code>| address[15:14]==0
  </code></pre>
  
  <p>or</p>
  
  <pre><code>|address[15:14]? io_din : ramrd
  </code></pre>
  
  <p>Cann't we omit the "|" in these cases? </p>