title: vhdl subtract std_logic_vector
body: <p>I am trying to substract 2 std logic vector and get error</p>
  
  <pre><code>p2 &lt;= p1(11 downto 0)- idata(11 downto 0);
  </code></pre>
  
  <blockquote>
    <p>Error (10327): VHDL error at sub.vhd(32): can't determine definition of operator ""-"" -- found 0 possible definitions</p>
  </blockquote>
  
  <p>I already tried to add <code>use IEEE.std_logic_signed.all</code> or  <code>use IEEE.std_logic_unsigned.all</code> or both and already tried 
  <code>p2 &lt;= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));</code></p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  --use IEEE.std_logic_signed.all;
  --use IEEE.std_logic_unsigned.all;
  
  entity sub is 
  
  port (  
      clk         : in    std_logic;
      rst         : in    std_logic;
      --en            : in    std_logic;  
      idata    : in    std_logic_vector (11 downto 0);
      odata    : out  std_logic_vector (11 downto 0)  
  );
  end sub;
  
  architecture beh of sub is
  signal p1,p2 :std_logic_vector (11 downto 0);
  begin
      process (clk, rst) 
          begin
              if (rst = '1') then
                  odata  &lt;= "000000000000";
              elsif (rising_edge (clk)) then  
                      p1 &lt;= idata;
                      p2 &lt;= p1(11 downto 0)- idata(11 downto 0);
                      --p2 &lt;= std_logic_vector(unsigned(p1(11 downto 0)) - unsigned(idata(11 downto 0)));
  
              end if;             
      end process;
      odata&lt;=p2;
  end beh;
  </code></pre>