title: What is "??" in Verilog casez?
body: <p>I have a module below:</p>
  <pre><code>module bai1c(a, b0, b1, b2, b3, c);
      input [2:0] a;
      input [3:0] b0, b1, b2, b3;
      output reg[3:0] c;
  
      always @(a or b0 or b1 or b2 or b3) begin
          casez(a)
              3'b000: c = b0;
              3'b001: c = b1;
              3'b010: c = b2;
              3'b011: c = b3;
              3'b1??: c = 4'b0000;
          endcase
      end
  endmodule
  </code></pre>
  <p>What kind of circuit will be synthesized?
  When the condition <code>3'b1??</code> happen? (what <code>??</code> is?)</p>