title: How to write new line to file in VHDL?
body: <p>I would like to separate my data with <code>new line</code> character in an output file, but the following codes result in error &quot;can't resolve overload for procedure call&quot;:</p>
  <pre><code>write(out_line, &quot;\n&quot;); 
  write(out_line, &quot;&quot;); 
  write(out_line, '');
  </code></pre>
  <p>An example code how I want to use it:</p>
  <pre><code>ENTITY writer IS 
  PORT ( clk : IN STD_LOGIC := '0'; start : IN STD_LOGIC := '0');
  END ENTITY;
  
  ARCHITECTURE arch OF writer IS
      SIGNAL vect : STD_LOGIC_VECTOR (2 downto 0) := &quot;000&quot;;
      TYPE state_type IS (init, write_file);
      SIGNAL state : state_type := init;
  BEGIN
      PROCESS (clk, start)
          FILE out_file : text;
          VARIABLE out_line : line;
      BEGIN
         IF rising_edge(clk) THEN
             CASE state IS 
                 WHEN init =&gt; 
                     IF start = '1' THEN
                         state &lt;= write_file;
                     ELSE 
                         state &lt;= init;
                     END IF;
                 WHEN write_file =&gt;
                     state =&gt; init;
  
                     FOR i IN 0 TO 10 LOOP
                         write(out_line, vect);
                         writeline(out_file, out_line);
                         -- write(out_line, &quot;\n&quot;); &lt;-- 
                         -- write(out_line, &quot;&quot;); &lt;-- 
                         -- write(out_line, ''); &lt;-- None of these work
                         writeline(out_file, out_line); 
                     END LOOP;
             END CASE;
         END IF;
     END PROCESS;
  END ARCHITECTURE;
                 
  </code></pre>
  <p>So I would like to know, is it possible in VHDL? If yes, how?</p>