title: Append to GNU make variables via command line
body: <p>I am using a GNU-make Makefile to build a C project with several targets (<code>all</code>, <code>clean</code>, and a few project specific targets). In the process of debugging, I would like to append some flags to a single build without permanently editing the Makefile (e.g. add debugging symbols or set a preprocessor flag).</p>
  
  <p>In the past, I have done that as follows (using the debugging symbols example):</p>
  
  <pre><code>make target CFLAGS+=-g
  </code></pre>
  
  <p>Unfortunately, this is not appending to the <code>CFLAGS</code> variable, but instead, clearing it and stopping it from compiling. Is there a clean way of doing this without defining some sort of dummy variable appended to the end of <code>CFLAGS</code> and <code>LDFLAGS</code>?</p>