title: Connecting components in VHDL structural
body: <p>I am working in VHDL, trying to connect three components M88, A8, A16, but once I synthesize the circuit and look at the RTL Schematic none of the components are connected. For example, I want to connect the output of M88 'out_high' to the input A16 of component A16. I do this by defining a signal OUT_H. Below is the structural of the main circuit and the entities of M88 and A16. The library 'Mult8x8.Components' is where I've defined the components. None of the connections between the components I've defined work, but I believe that I'm doing the same mistake that I can't figure out.</p>
  
  <p>Thanks</p>
  
  <pre><code>entity Structure is
  Port ( 
         Clock, RST, Start : in  BIT;
            IN1, IN2 : in  BIT_VECTOR (7 downto 0);
         RESULT8x8 : out  BIT_VECTOR (15 downto 0);
            Done : out BIT_VECTOR(3 downto 0)
        );
  end Structure;
  
  architecture Structural of Structure is use work.Mult8x8_Components.all;
  signal OUT_M1, OUT_M2: BIT_VECTOR(7 downto 0);
  signal OUT_H, OUT_L, ADD_MIXout, result16: BIT_VECTOR(15 downto 0);
  signal Zero, Init, Shift, Add, Low: BIT := '0'; 
  signal High: BIT := '1';
  signal F, OFL, REGclr: BIT;
  signal DD : BIT_VECTOR(3 downto 0);
  
  begin
  --  REGclr &lt;= Init or RST;
      RESULT8x8 &lt;= result16;
      Done &lt;= DD;
      M88 : Mult8x8 port map 
          (CLK =&gt; Clock, RESET =&gt; RST, Start =&gt; Start, input1 =&gt; IN1, input2 =&gt; IN2, out_high =&gt; OUT_H, out_low =&gt; OUT_L, out_mix1 =&gt; OUT_M1, out_mix2 =&gt; OUT_M2, DONE =&gt; DD );
      A8 : Adder8 port map (A=&gt;OUT_M1, B=&gt;OUT_M2, Cin=&gt;Low, Cout=&gt;OFL, Sum=&gt;ADD_MIXout(11 downto 4));
      A16 : Adder16 port map (A16=&gt; OUT_H, B16 =&gt; OUT_L, E16 =&gt; ADD_MIXout, Cin16 =&gt; low, Cout16 =&gt; OFL, Sum16 =&gt; result16 );
  end Structural;
  
  
  
  
  
  
  
  entity Mult8x8 is
      Port( 
               CLK, RESET, Start : in BIT;
               input1 : in  BIT_VECTOR (7 downto 0);
            input2 : in  BIT_VECTOR (7 downto 0);
            out_high : out BIT_VECTOR (15 downto 0) := (others =&gt;'0');
               out_low : out BIT_VECTOR (15 downto 0) := (others =&gt;'0');
               out_mix1 : out BIT_VECTOR (7 downto 0) := (others =&gt;'0');
               out_mix2 : out BIT_VECTOR (7 downto 0) := (others =&gt;'0');
               DONE : out BIT_VECTOR (3 downto 0)
               );
  end Mult8x8;
  
  
  
  
  entity Adder16 is
      Port ( A16, B16, E16 : in BIT_VECTOR (15 downto 0);
             Cin16 : in BIT;
                Cout16 : out BIT;
             Sum16 : out BIT_VECTOR (15 downto 0));
  end Adder16;
  </code></pre>