title: How to define and initialize a vector containing only ones in Verilog?
body: <p>If I want to declare a 128 bit vector of all ones, which one of these methods is always correct?</p>
  
  <pre><code>wire [127:0] mywire;
  
  assign mywire = 128'b1;
  assign mywire = {128{1'b1}};
  assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
  </code></pre>