title: iverilog testbench error: input is declared as wire, but it isn't
body: <p>I am very new to iverilog and am creating a counter to reduce a 100Mhz clock frequency to something easier to work with, as part of a larger project.
  I found some code that does that and so I tried to write a testbench for it.
  Here is the code I found:</p>
  
  <pre><code>    module slowClock(clk, reset, clk_1Hz);
  input clk, reset;
  output clk_1Hz;
  
  reg clk_1Hz;
  reg [27:0] counter;
  
  always@(posedge reset or posedge clk)
  begin
       if (reset == 1'b1)
           begin
               clk_1Hz &lt;= 0;
               counter &lt;= 0;
           end
       else
           begin
               counter &lt;= counter + 1;
               if ( counter == 25_000_000)
                   begin
                       counter &lt;= 0;
                       clk_1Hz &lt;= ~clk_1Hz;
                   end
           end
  end
  endmodule   
  </code></pre>
  
  <p>and here is the testbench I wrote:</p>
  
  <pre><code>module slowClock_tb(clk, reset, clk_1Hz);
      input  clk;
      input  reset;
      output  clk_1Hz;
  
  initial 
  begin
      clk = 1'b0; 
      reset = 1'b0;
  #2 reset = ~reset;
  
  end
  
      always #3 clk = ~clk;
  
  slowClock clock_generator(clk, reset, clk_1Hz);
  
  
  endmodule
  </code></pre>
  
  <p>Here are the error messages:</p>
  
  <pre><code>$ iverilog  slowClock.v slowClock_tb.v 
  slowClock_tb.v:8: error: clk is not a valid l-value in slowClock_tb.
  slowClock_tb.v:2:      : clk is declared here as wire.
  slowClock_tb.v:9: error: reset is not a valid l-value in slowClock_tb.
  slowClock_tb.v:3:      : reset is declared here as wire.
  slowClock_tb.v:10: error: reset is not a valid l-value in slowClock_tb.
  slowClock_tb.v:3:      : reset is declared here as wire.
  slowClock_tb.v:14: error: clk is not a valid l-value in slowClock_tb.
  slowClock_tb.v:2:      : clk is declared here as wire.
  4 error(s) during elaboration.
  </code></pre>
  
  <p>The first error message: clk is declared here as wire.
  But it hasn't been declared as a wire in either the original code or the testbench. Same goes for reset.
  I have tried getting help from the on-campus tutors, but they didn't know why this is happening or were able to advise on how to fix it.</p>
  
  <p>Can anyone suggest how to fix this?</p>