title: VHDL FSM with a counter inside
body: <p>I am new here and here is my question:</p>
  
  <p>I have a state machine with 3 states(s0,s1.s2) and input:(reset, clk, start) and output (done). My state machine works like this: on reset it comes to s0, and then if start = '1' goes to s2 and in this state I want it to stay there for 12 clock cycles (12 clock cycle delay) and then goes to s2 and done ='1' here and then back to s0.
  My codes goes like this :</p>
  
  <p>My code seems fine but my simulation result is not ok.</p>
  
  <pre><code>    LIBRARY ieee;
      USE ieee.std_logic_1164.all;
      USE ieee.std_logic_unsigned.all;
  
      ENTITY fsm_count IS
      port(clk : in std_logic;
          reset : in std_logic;
          start : in std_logic ;
          don : out std_logic );
  
      END ENTITY fsm_count;
  
  --
      ARCHITECTURE arc OF fsm_count IS
       type statetype is (s0,s1,s2);
      signal pr_state,nx_state : statetype;
      signal s_counter : std_logic_vector (3 downto 0):=(others=&gt;'0');  -- zero
  
      begin
      fsmcount: process(clk,reset,pr_state,start)
      begin
        if reset = '1'then pr_state &lt;= s0;
        elsif (clk'event and clk='1') then
  
        case pr_state is 
  
          when s0 =&gt; 
          if start ='1' then nx_state &lt;=s1;
          else nx_state &lt;= s0;
          end if;
  
         when s1 =&gt;
           s_counter &lt;= s_counter + '1';
           if (s_counter = "1100") then 
             nx_state &lt;= s2;
             s_counter &lt;=(others =&gt;'0'); -- initializing the counter back to zero
           else nx_state &lt;=s1;
  
           end if;
  
         when s2 =&gt; 
           nx_state&lt;= s0;
  
  
        end case;
      end if;
       end process fsmcount;
  
        don &lt;= '1' when  (pr_state = s2) else '0';             
      END ARCHITECTURE arc;
  
  </code></pre>