title: Direct-Mapped Cache Hit & Miss
body: <p>4-bit address</p>
  
  <p>tag 1-bit</p>
  
  <p>index 2-bit</p>
  
  <p>offset 1-bit</p>
  
  <p>2 bytes per block</p>
  
  <p>4 sets (1 block per set)</p>
  
  <p>I am trying to determine if the following addresses are hits or misses. I am presenting the information I have acquired thus far.
  (all credit will be given to stack overflow)</p>
  
  <p>Addresses</p>
  
  <p>14</p>
  
  <p>set 3</p>
  
  <p>v = 0</p>
  
  <p>tag = 1</p>
  
  <p>offset = 0</p>
  
  <p>9</p>
  
  <p>set 0</p>
  
  <p>v = 0</p>
  
  <p>tag = 1</p>
  
  <p>offset = 1</p>
  
  <p>2</p>
  
  <p>set 1</p>
  
  <p>v = 0</p>
  
  <p>tag = 0</p>
  
  <p>offset = 0</p>
  
  <p>6</p>
  
  <p>set 3</p>
  
  <p>v = 1</p>
  
  <p>tag = 0</p>
  
  <p>offset = 0</p>
  
  <p>3</p>
  
  <p>set 1</p>
  
  <p>v = 1</p>
  
  <p>tag = 0</p>
  
  <p>offset = 1</p>