title: synthesizable way to load initial values in verilog
body: <p>I would like to write a module that uses some coefficients that are loaded from a file. </p>
  
  <p>For example:</p>
  
  <pre><code>reg [3:0]  coeffs[0:1];
  reg  [6:0]   ans;
  always @(posedge clk) begin
      if (!reset) begin
          coeffs[0] &lt;=  3;
          coeffs[1]  &lt;=  2;
          ans   &lt;=   0;
      end
      else begin
          ans    &lt;=   coeffs[0] *  coeffs[1];
      end
  end
  </code></pre>
  
  <p>I would like to replace the values 3 and 2 by values that I can modify in a file, and provide the file during synthesis. 
  Obviously, this file will only assign initial values to the registers. 
  I don't want it to be a block ram, I want it to be like independent registers. </p>
  
  <p>Just to clarify, I need the solution to be very generic, because I intent to use it in many modules that are doing the same thing, but with a different number of coefficients.</p>
  
  <p>Meaning, in the end I wish to have a generic module that receives as a parameter a file name that stores the coefficients, and the number of coefficients and their width, and generates a code using those parameters.</p>
  
  <p>I have tried <code>readmemh</code> but I understood it is only synthesizable to initiate a memory.</p>
  
  <p>Any suggestions? 
  Thanks. </p>