title: System Verilog: The loop variable is not initialized to a constant ELAB-800
body: <p>When trying to compile my RTL design that is written in System Verilog, I am using Synopsys Design Compiler, but I am getting the following error message:</p>
  
  <blockquote>
    <p>Error: /home/rtl/mydesign.sv:66: The loop variable is not initialized
    to a constant. (ELAB-800)</p>
  </blockquote>
  
  <p>Here is the code in question:</p>
  
  <pre><code>// Zero out bits from savedbit_loc all the way down to the least significant bit
  // We don't know the value of savedbit_loc until the module is instantiated.
  
  assign savedbit_loc = src1- MYPARAM1 - 1;
  
  // Zero out the 
  always @(*) begin
      for (int i = savedbit_loc; i &gt;= 0; i--) begin  
          zeroedout[i] = 1'b0;
    end
  end
  </code></pre>
  
  <p>MYPARAM1 is a parameters that are set when the module is instantiated.</p>
  
  <p>The line it is complaining about is:</p>
  
  <pre><code>for (int i = savedbit_loc; i &gt;= 0; i--) begin
  </code></pre>
  
  <p>My code runs in ncverilog just fine and obtains the correct output.  </p>
  
  <p>Is there another way to write this module so that i don't get this error?</p>