title: FF/Latch and other warnings
body: <p>What is wrong with my VHDL code? Here is the code:</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity main is
      port(
          -- 50 MHz clock
          cp : in std_logic;
          -- Reset signal
          reset : in std_logic;
          -- PS/2 data and clock lines
          ps2d, ps2c : in std_logic;
          -- 7-segment display segments
          segments : out std_logic_vector (7 downto 0);
          -- Anode control
          an : out std_logic_vector (3 downto 0);
          -- Data out to LEDs
          dout : out std_logic_vector (7 downto 0)
      );
  end main;
  
  architecture Behavioral of main is
      -- Data from keyboard entity (scancode)
      signal data : std_logic_vector (7 downto 0);
      -- 7 segments of display
      signal segReg, segNext : std_logic_vector (6 downto 0);
      signal tickDone : std_logic;
  begin
      -- Just an entity that reads PS/2 keyboard data
      -- rx_done is tick (20 ns)
      S1: entity keyboard port map ( cp =&gt; cp, ps2d =&gt; ps2d, ps2c =&gt; ps2c,
                            rx_done =&gt; tickDone, dout =&gt; data);
      dout &lt;= data;
      an &lt;= &quot;1110&quot;;
      segments(6 downto 0) &lt;= segReg;
      -- Turn off dot
      segments(7) &lt;= '1';
      process (cp, reset)
      begin
          if reset = '1' then
              segReg &lt;= (others =&gt; '0');
          elsif rising_edge (cp) then
              segReg &lt;= segNext;
          end if;
      end process;
  
      process (tickDone, segReg)
      begin
          segNext &lt;= segReg;
          if tickDone = '1' then
              if data = x&quot;16&quot; then
                  -- Number 1
                  segNext &lt;= &quot;1001111&quot;;
              elsif data = x&quot;1E&quot; then
                  -- Number 2
                  segNext &lt;= &quot;0010010&quot;;
              elsif data = x&quot;26&quot; then
                  -- Number 3
                  segNext &lt;= &quot;0000110&quot;;
              elsif data = x&quot;25&quot; then
                  -- Number 4
                  segNext &lt;= &quot;1001100&quot;;
              else
                  segNext &lt;= &quot;1111111&quot;;
              end if;
          end if;
      end process;
  
  end Behavioral;
  </code></pre>
  <p>When I try to synthesize it/generate programming file, I get these warnings:</p>
  <pre class="lang-none prettyprint-override"><code>WARNING:Xst:819 - &quot;C:/VHDL_projekti/PS2K/main.vhd&quot; line 48: The following signals are missing in the process sensitivity list:
  WARNING:Xst:2734 - Property &quot;use_dsp48&quot; is not applicable for this technology.
  WARNING:Xst:1710 - FF/Latch  &lt;segReg_0&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  &lt;segReg_1&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  &lt;segReg_2&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  &lt;segReg_3&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  &lt;segReg_4&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  &lt;segReg_5&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1710 - FF/Latch  &lt;segReg_0&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  &lt;segReg_1&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  &lt;segReg_2&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  &lt;segReg_3&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  &lt;segReg_4&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  &lt;segReg_5&gt; (without init value) has a constant value of 0 in block &lt;main&gt;.
  WARNING:Par:288 - The signal reset_IBUF has no load.  PAR will not attempt to route this signal.
  WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
  WARNING:PhysDesignRules:367 - The signal &lt;reset_IBUF&gt; is incomplete. The signal
  </code></pre>
  <p>I've been looking at the code and I don't see anything wrong, but obviously I'm doing something wrong.</p>
  <ol>
  <li><p>&quot;The following signals are missing in the process sensitivity list&quot; Is this maybe <a href="https://en.wikipedia.org/wiki/Xilinx" rel="nofollow noreferrer">Xilinx</a> ISE bug? I don't see why I would need any other signals in process sensitivity list on line 48...</p>
  </li>
  <li><p>&quot;Due to other FF/Latch trimming, has a constant value of 0 in block&quot; OK, what am I doing wrong? I don't want to use latches at all ...</p>
  </li>
  <li><p>&quot;The signal reset_IBUF has no load.  PAR will not attempt to route this signal. &quot; What does this mean? What is wrong with my reset signal? Why is it incomplete?</p>
  </li>
  </ol>
  <p>This code is my attempt at using a <a href="https://en.wikipedia.org/wiki/PS/2_port" rel="nofollow noreferrer">PS/2</a> keyboard with <a href="https://en.wikipedia.org/wiki/List_of_Xilinx_FPGAs#Spartan-3" rel="nofollow noreferrer">Spartan-3</a> starter board. The entity &quot;keyboard&quot; does the reading, and it is working properly (when I test it alone, I get correct scan codes on the <em>dout</em> signal (I see it on LEDs)). <em>rx_done</em> is tick (20 ns) that signals that scancode has been successfully read.</p>
  <p>So I just wanted to see if I can somehow recognize the scan codes (in my second process I'm comparing data signal and putting right values to segNext signal) and display something on the <a href="https://en.wikipedia.org/wiki/Seven-segment_display" rel="nofollow noreferrer">seven-segment display</a>. When I get this to work, I'll then implement correct behaviour (detecting all scan codes, for extra keys and for key down and key up events).</p>
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity main is
      port(
          -- 50 MHz clock
          cp : in std_logic;
          -- Reset signal
          reset : in std_logic;
          -- PS/2 data and clock lines
          ps2d, ps2c : in std_logic;
          -- 7-segment display segments
          segments : out std_logic_vector (7 downto 0);
          -- Anode control
          an : out std_logic_vector (3 downto 0);
          -- Data out to LEDs
          dout : out std_logic_vector (7 downto 0)
      );
  end main;
  
  architecture Behavioral of main is
      -- Data from keyboard entity (scancode)
      signal data : std_logic_vector (7 downto 0);
      -- 7 segments of display
      signal segReg, segNext : std_logic_vector (6 downto 0);
      signal tickDone : std_logic;
  begin
      -- Just entity that reads PS/2 keyboard data
      -- rx_done is tick (20 ns)
      S1: entity keyboard port map ( cp =&gt; cp, ps2d =&gt; ps2d, ps2c =&gt; ps2c,
                            rx_done =&gt; tickDone, dout =&gt; data);
      dout &lt;= data;
      an &lt;= &quot;1110&quot;;
      segments(6 downto 0) &lt;= segReg;
      -- Turn off dot
      segments(7) &lt;= '1';
      process (cp, reset)
      begin
          if reset = '1' then
              segReg &lt;= (others =&gt; '0');
          elsif rising_edge (cp) then
              segReg &lt;= segNext;
          end if;
      end process;
  
      process (tickDone, segReg, data)
      begin
          if tickDone = '1' then
              if data = x&quot;16&quot; then
                  -- Number 1
                  segNext &lt;= &quot;1001111&quot;;
              elsif data = x&quot;1E&quot; then
                  -- Number 2
                  segNext &lt;= &quot;0010010&quot;;
              elsif data = x&quot;26&quot; then
                  -- Number 3
                  segNext &lt;= &quot;0000110&quot;;
              elsif data = x&quot;25&quot; then
                  -- Number 4
                  segNext &lt;= &quot;1001100&quot;;
              else
                  segNext &lt;= &quot;1111111&quot;;
              end if;
          else
              segNext &lt;= segReg;
          end if;
      end process;
  
  end Behavioral;
  </code></pre>
  <p>Unfortunately, after these edits, I still have this warnings:</p>
  <pre class="lang-none prettyprint-override"><code>WARNING:Xst:1710 - FF/Latch &lt;segReg_0&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_1&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_2&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_3&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_4&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_5&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_6&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1710 - FF/Latch &lt;segReg_0&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_1&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_2&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_3&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_4&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch &lt;segReg_5&gt; (without init value) has a constant value of 0 in block &lt;main&gt;. This FF/Latch will be trimmed during the optimization process.
  WARNING:Par:288 - The signal reset_IBUF has no load.  PAR will not attempt to route this signal.
  WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
  </code></pre>