title: Detecting the rising edge of an std_logic signal in VHDL
body: <p>I have a flip flop which uses as clk input a signal which comes from the processing of to other signals. That means, that I'm not using the clock of the system neither an input. Thus, when I do:</p>
  
  <pre><code>architecture sampler_a of sampler_e is
    signal S0_s   : std_logic := '0';  
  begin
    -- In my block this is not only a not. I put this to simplify things.
    S0_s &lt;= not(S0_i);                   
    S0_o &lt;= S0_s;
  
    process(S0_i)
    begin
      --Also with rising edge does not work
      if (S0_s'event and S0_s= '1') then
          BitReady_o &lt;= '1';
      end if;   
    end process;
  end sampler_a;
  </code></pre>
  
  <p>BitReady does not change in the simulation (in modelsim). Is the use of std_logic incorrect here?
  Note that I don't want to generate a pulse that is a clock period's wide, because my circuit works in an asynchronous way.</p>