title: VHDL std_logic_vector indexing with "downto"
body: <p>I would like to set bits of a std_logic_vector separately in order to easily set comments for individual bits or group of bits. Here is what I have:</p>
  
  <pre><code>signal DataOut : std_logic_vector(7 downto 0);
  ...
  DataOut &lt;= (                        5=&gt;'1',     -- Instruction defined
                                      4=&gt;'1',     -- Data length control bit, high=8bit bus mode selected
                                      3=&gt;'1',     -- Display Line Number ctrl bit, high &amp; N3 option pin to VDD=3 lines display
                                      2=&gt;'0',     -- Double height font type control byte, not selected
                                      1 downto 0=&gt;"01",   -- Select Instruction table1
                                      others=&gt;'0' -- for bits 6,7
                                      );
  </code></pre>
  
  <p>However, I've a problem with the "downto" statement, I get the following error using Xilinx ISE:</p>
  
  <pre><code>Type std_ulogic does not match with a string litteral
  </code></pre>
  
  <p>Any solution to avoid  using the equivalent </p>
  
  <pre><code>1=&gt;'0',
  0=&gt;'1',
  </code></pre>
  
  <p>and to allow me to set bits by block?</p>