title: Digital frequency doubler with a dual edge triggered flip flop in VHDL
body: <p>I am trying to implement a digital input frequency doubler. The circuit consists of an XOR2 gate, dual edge triggered flip flop and a couple of buffers.</p>
  
  <p>The frequency-in goes to one of the Xor inputs. The output of the Xor gate goes through a buffer and into the clock signal of the DFF. The output(ussually Q) used in parallel to feed the remaining Xor input and to feedback to the D input of the flip flop through a buffer. finally the output of the doubler is taken from the Xor gate.</p>
  
  <p>I have tested the circuit and it works.I am a novice in VHDL and have very basic knowledge in verilog. I figured i'd analyse it for practice so that i get a feel of VHDL before third year.</p>
  
  <p>Regards 
  Stranger</p>