title: Problems with wires declared inside verilog generate blocks
body: <p>Within a <code>generate</code> block, I have multiple <code>if</code> statements. When I declare a wire in the first if statement - I can't use it in other <code>if</code> statements</p>
  
  <p>See the following stripped down example of my module:</p>
  
  <pre><code>module my_module 
  #(parameter integer NUM_X_PORTS = 1,
    parameter integer NUM_Y_PORTS = 1)
   (
    // port declarations
   );
  
  generate 
  
    if (NUM_X_PORTS &gt; 0) begin
      wire [NUM_X_PORTS-1:0] x1;
      // logic filled in here
    end
  
    if (NUM_Y_PORTS &gt; 0) begin
      wire [NUM_Y_PORTS-1:0] y1;
      // logic filled in here
    end
  
    if ((NUM_X_PORTS &gt; 0) &amp;&amp; (NUM_Y_PORTS &gt; 0)) begin
      for (i=0; i&lt;NUM_Y_PORTS; i=i+1) begin
        assign z[i] = y1[i] &amp; |x1; // I can't use x1 and y1 here
      end
  
  endgenerate
  </code></pre>
  
  <p>The error message from both VCS and nLint is that indentifiers x1 and y1 have not been declared.</p>
  
  <p>But they have been declared within previous generated if statements - what is the problem here?</p>