title: Simplest way to generate Verilog code from Chisel code
body: <p>What is the simplest way to <strong>generate Verilog</strong> code from existing Chisel code? </p>
  
  <p>Would i have to <strong>create my own build file</strong>?</p>
  
  <p>For example from a <strong>standalone scala file</strong> (AND.scala) like the following one..</p>
  
  <pre><code>import Chisel._
  
  class AND extends Module {
    val io = IO(new Bundle {
      val a = Bool(INPUT)
      val b = Bool(INPUT)
      val out = Bool(OUTPUT)
    })
    io.out := io.a &amp; io.b
  }
  </code></pre>
  
  <p>I have the complete <strong>Chisel3 Toolchain installed</strong> under ubuntu 16.4.</p>