title: makefile target-specific files
body: <p>I'm trying to make a single makefile file that compiles two different set of files. Is this posible?</p>
  
  <p>What I tried so far is:</p>
  
  <pre><code>target1: OBJ = foo1.o foo2.o  
  target1: application
  
  target2: OBJ = foo3.o foo4.o
  target2: application
  
  application: $(OBJ)
      $(LD) $(OBJ)
  </code></pre>
  
  <p>What happens is that <code>LD</code> is called with the correct parameters but make never actually checks the dependencies therefore the implicit rules that compile .c files to .o are never executed so linker fails with:</p>
  
  <pre><code>ld: cannot find foo1.o: No such file or directory
  ld: cannot find foo2.o: No such file or directory
  </code></pre>
  
  <p>What is the right way to do this?</p>