title: Creating subdirectories in Makefile without mkdir -p
body: <p>The <a href="https://www.gnu.org/prep/standards/standards.pdf" rel="nofollow noreferrer">GNU standard</a> says it is a good idea to not use the <code>-p</code> command for <code>mkdir</code>:</p>
  
  <blockquote>
    <p>For example, don’t use ‘mkdir -p’, convenient as it may be, because a
    few systems don’t support it at all and with others, it is not safe for parallel execution</p>
  </blockquote>
  
  <p>I would like to adhere to this standard and thus I am running into a problem in my Makefile.</p>
  
  <p>I am recursively compiling all C sources from all directories within the <code>src</code> directory and would like to place them inside the <code>obj</code> directory. The same directory structure is mirrored inside the <code>obj</code> directory, however these directories do not initially exist.</p>
  
  <p>I could very easily do <code>mkdir -p $(@D)</code> to create my directories, but following GNU's standard, I cannot do this, which brings me to my question: How can I work around this in a Makefile?</p>
  
  <p>My Makefile below:</p>
  
  <pre><code>SRCDIR=src
  OBJDIR=obj
  
  CC=cc
  
  CFLAGS=
  CFLAGS=-g -O2 -pedantic -Wall
  ALL_CFLAGS=-std=c89 $(CFLAGS)
  
  # Copied from https://stackoverflow.com/questions/2483182/recursive-wildcards-in-gnu-make/18258352#18258352
  rwildcard=$(foreach d, $(wildcard $1/*), $(call rwildcard, $d, $2) $(filter $(subst *, %, $2), $d))
  
  SOURCES=$(call rwildcard, $(SRCDIR), *.c)
  OBJECTS=$(subst $(SRCDIR),$(OBJDIR),$(SOURCES:.c=.o))
  
  all: $(OBJECTS)
  
  $(OBJDIR)/%.o: $(SRCDIR)/%.c
      $(CC) $(ALL_CFLAGS) -c -o $@ $&lt;
  </code></pre>