title: In VHDL-2008, how to format "real" similar to "%f" in c-language, example: sprintf(str, "%9.6f", myreal)
body: <p>I'm using VHDL-2008 and I want to nicely format real numbers are strings similar to this c-language function:</p>
  
  <pre><code>    sprintf(str, "%9.6f", myreal);
  </code></pre>
  
  <p>Currently, I'm formatting my real numbers this way:</p>
  
  <pre><code>architecture sim of testbench is
      constant myreal :real := 3343.2342;
  begin
  
  process
  begin
     report real'image(real_number);
     wait;
  end process
  
  end architecture;
  </code></pre>
  
  <p>Which doesn't allow enough control over the formatting of the real numbers in VHDL.  What I want, is control over the vhdl formating more like the c-language "%n.mf" formatter.  </p>
  
  <p>Basically, the VHDL defaul in GHDL simulator is always to print real numbers in scientific notation with one digit left of the decimal place, a fraction, and an exponent, which is annoying as heck.</p>