title: Verilog: Sum over n register
body: <p>Im trying to build an moving average module. It should use the number of values to use as parameter.</p>
  
  <p>How do I get the sum of all n <code>tmp</code>-registers using a <code>for</code>- or <code>gernerate</code>-block within one clock-cylce?</p>
  
  <pre><code>reg [WORDLEN - 1:0] tmp [SIZE - 1:0];
  reg [WORDLEN + SIZE / 2 - 1:0] sum;
  always @(posedge clk)
      sum &lt;= sum(tmp) // Like &lt;= tmp[0] + tmp[1] + ... + tmp[SIZE-1]
  </code></pre>