title: Binding a checker in SystemVerilog
body: <p>I would like to bind a checker construct to a VHDL module (in QuestaSim) to ensure some verification properties, without having to declare and bind a more (complex) module/interface/agent structure.
  Without further ado I present you the example code I was using:</p>
  
  <pre><code>module verification_top();
    ...
    bind dut_wrapper.dut test_checker tc();
    ...
  endmodule
  
  checker test_checker();
    ...
  endchecker
  </code></pre>
  
  <p>The vopt error is:<br>
  <code>** Error: src/tb_vtop.sv(210): Failed to instantiate checker 'test_checker' inside bind's target 'dut_wrapper'.
  Optimization failed</code></p>
  
  <p>Binding modules and interfaces work well with the same testbench, syntax and tool.</p>
  
  <p>As far as I understand the 1800-2012 LRM 23.11 specifies that checkers can be bound inside modules. I would like to inquire the collective knowledge: is this a tool related limitation (not supported construct) or is there a special requirement for checkers to be able to get bound. I have consulted MG's QuestaSim user manual and command reference manual, but checkers and bind constructs are usually unmentioned.</p>
  
  <p>I know I have several workaround options, the question relates the checker construct itself, as I have never used it before.</p>