title: iterative read data from more than one files in verilog
body: <p>I am new to Verilog and I have to create a testbench file for a core I designed.
  In the testbench I need to read data from txt files and feed them in my design as inputs. Then, the design's output will be written in an output txt files.
  Already I managed to do that concerning one input file and one output file (reading from a file with fscanf, process the data and write the output to another file with fwrite).</p>
  
  <p>Now I would like to further test my design by reading data from more than one files and write the output results in more than one output files.</p>
  
  <p>For example, I would like to have 1000 input files, iteratively read data from them and feed it to my design, and write the output to 1000 output files (read the first file, process its data, write the first output file, read the second file, process its data, write the second output file, etc etc). Each one of the output files will concern the corresponding input file. Is it even possible in Verilog ? And, if so, in which way I have to implement it ? I searched in the net for that but I didn't found anything related to iterative read/write many files...</p>
  
  <p>Thanks in advance!</p>
  
  <p>The code I used to lead the file and read the data is:</p>
  
  <pre><code>fd_test = $fopen("C:/TEST_FILE.dat","r");
  fd_out_test = $fopen("C:/TEST_OUT_FILE.dat","w");
  
  while(cnt_test&gt;0) begin
     if (fifo_read_request) begin
         cnt_test = $fscanf(fd_test,"%H",read_block);
         mpdu_block = read_block;
     end else begin
         cnt_test = cnt_test;
         mpdu_block = mpdu_block;
     end
     if (valid_enc_mpdu_block) begin
         $fwrite(fd_out_test, "%H\n", enc_mpdu_block);
     end
     #2;  @(posedge clk);
  end
  </code></pre>