title: VHDL - How should I create a clock in a testbench?
body: <p>How should I create a clock in a testbench? I already have found one answer, however others on stack overflow have suggested that there are alternative or better ways of achieving this:</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  
  ENTITY test_tb IS 
  END test_tb;
  
  ARCHITECTURE behavior OF test_tb IS
  
      COMPONENT test
          PORT(clk : IN std_logic;)
      END COMPONENT;
  
     signal clk : std_logic := '0';
     constant clk_period : time := 1 ns;
  
  BEGIN
  
     uut: test PORT MAP (clk =&gt; clk);       
  
     -- Clock process definitions( clock with 50% duty cycle is generated here.
     clk_process :process
     begin
          clk &lt;= '0';
          wait for clk_period/2;  --for 0.5 ns signal is '0'.
          clk &lt;= '1';
          wait for clk_period/2;  --for next 0.5 ns signal is '1'.
     end process;
  
  END;
  </code></pre>
  
  <p>(source <a href="http://vhdlguru.blogspot.sg/2010/03/how-to-write-testbench.html">here</a>)</p>