title: "Invalid Module Instantiation" Error in Mealy sequence detector - Verilog
body: <p>I have defined a module for a Mealy State Machine that detects a particular sequence. I haven't encoded states as is usually a better choice as I wanted to do it the other way(I saw a similar example in a book, but the code was in VHDL).</p>
  
  <pre><code>module seq_detector(y_out,Clk,x_in);
    output y_out;
    reg y_out;
    input x_in, Clk;
    reg Q1,Q2,Q3,Q4;
    always @(posedge Clk)
      Q1 &lt;= (Q1&amp;&amp;(!Q3))||((!Q1)&amp;&amp;Q2;&amp;&amp;(!Q3)&amp;&amp;(!Q4)&amp;&amp;(x_in));
      Q2 &lt;= ((!Q3)&amp;&amp;Q4;&amp;&amp;(!x_in))||(Q1&amp;&amp;Q2;&amp;&amp;(!Q3)&amp;&amp;(!Q4)&amp;&amp;x_in);
      Q3 &lt;= Q1&amp;&amp;Q2;&amp;&amp;(!Q3)&amp;&amp;(x_in);
      Q4 &lt;= (Q1&amp;&amp;Q2;&amp;&amp;(x_in))||(Q1&amp;&amp;(!Q4)&amp;&amp;(!x_in))||((!Q1)&amp;&amp;(!Q2)&amp;&amp;(Q4)&amp;&amp;(!x_in))||((!Q1)&amp;&amp;(!Q2)&amp;&amp;(x_in))||((!Q1)&amp;&amp;(!Q3)&amp;&amp;Q4;&amp;&amp;x_in)||(Q1&amp;&amp;Q2;&amp;&amp;(!Q4)&amp;&amp;x_in);
  
    always @(x_in or Q1 or Q2 or Q3 or Q4)
    y_out &lt;= Q3||(Q2&amp;&amp;(!Q4)&amp;&amp;x_in);
  endmodule
  </code></pre>
  
  <p>On compiling the code, I get the following errors. </p>
  
  <pre><code>mini_project.v:8: syntax error
  mini_project.v:8: error: Invalid module instantiation
  mini_project.v:9: error: Invalid module instantiation
  mini_project.v:10: error: Invalid module instantiation
  </code></pre>
  
  <p>I can't make out anything of the error message. Can someone please explain the error message and suggest how to correct it ?</p>