title: Using array of std_logic_vector as a port type, with both ranges using a generic
body: <p>Is it possible to create an entity with a port that is an array of std_logic_vectors, with both the size of the array and the std_logic_vector coming from generics? Ie. is it possible to create eg. a bus multiplexer with both the bus width and bus count configurable?</p>
  
  <pre><code>entity bus_multiplexer is
          generic (bus_width : positive := 8;
                  sel_width : positive := 2);
          port (  i : in array(integer range 2**sel_width - 1 downto 0) of std_logic_vector(bus_width - 1 downto 0);
                  sel : in std_logic_vector(sel_width - 1 downto 0);
                  o : out std_logic_vector(bus_width - 1 downto 0));
  end bus_multiplexer;
  
  architecture dataflow of bus_multiplexer is
  begin
          o &lt;= i(to_integer(unsigned(sel)));
  end dataflow;
  </code></pre>
  
  <p>The above doesn't seem to work because the array type needs to be defined separately.
  Defining the type before the port also does not work, as then it expects the entity definition to end after it. Defining it after the port definition doesn't work since it'd be used before that. Defining it in a package doesn't work because the type definition doesn't seem to like having an unconstrained range in the "base type".</p>
  
  <p>Is it possible to somehow do this in VHDL-93? (What about VHDL-2008?)</p>
  
  <p>Defining the type as <code>array(natural range &lt;&gt;, natural range &lt;&gt;) of std_logic</code> in the package works - as in the port definition doesn't give an error - but actually using it if it's defined that way seems to be quite unwieldy.</p>
  
  <p>Is there some sane way to use it like this? Is there some simple way to map N separate std_logic_vectors to a port defined like that, and likewise for the actual output logic?</p>
  
  <p>I tried the original and <code>o &lt;= i(to_integer(unsigned(sel)), bus_width - 1 downto 0)</code>, but neither worked. I know I could do it one bit at a time, but I'd prefer something simpler. And while the bit-by-bit -approach might be okay for the internal implementation, I certainly wouldn't want to have to do that for the port mapping every time I use the component...</p>
  
  <p>Is there some sane(-ish) way to do this?</p>
  
  <p><em>(Addendum: I know there are some similar questions, but most of them don't deal with the case of both ranges coming from generics, and were solved using a type definition in a package. The one that did talk about two generic dimensions apparently didn't need the input to come from distinct std_logic_vectors and ended up using the "2d-array of std_logic" method, which doesn't work for me (at least without further clarification about how to use it without losing one's sanity))</em></p>