title: Verilog: Can you put "assign" statements within always@ or begin/end statements?
body: <p>Is this allowed?     </p>
  
  <pre><code>input w;
       input [8:0]y;
       output reg [8:0]x;
       always@(w)
       begin
  
  
       //x[0] or A is never on in any next state
       assign x[0] = 0;
       assign x[1]= (y[0]&amp;~w) | (y[5]&amp;~w) | (y[6]&amp;~w) | (y[7]&amp;~w) | (y[8]&amp;~w); //B
       assign x[2]= (y[1]&amp;~w); //C
       assign x[3]= (y[2]&amp;~w); //D
       assign x[4]= (y[3]&amp;~w) | (y[4]&amp;~w); //E
       assign x[5]= (y[0]&amp;w) | (y[1]&amp;w) | (y[2]&amp;w) | (y[3]&amp;w) | (y[4]&amp;w); //F
       assign x[6]= (y[5]&amp;w);
       assign x[7]= (y[6]&amp;w);
       assign x[8]= (y[7]&amp;w) | (y[8]&amp;w);
  
       end
  </code></pre>