title: Two ways to write pipeline in verilog, which one is better?
body: <p>I learned two ways of writing pipeline(unblocking and blocking), I wonder which is better?</p>
  
  <p>My personal opinion is that the second one is tedious and I don't understand why so many <code>wire</code> are needed.</p>
  
  <p>Also, is there any standard style(template) of writing pipeline like FSM in verilog?
  Thanks in advance.</p>
  
  <pre><code>module simplePipeline
  #(
      parameter WIDTH = 100
  )
  (
      input clk,
      input [WIDTH - 1 : 0] datain,
      output [WIDTH - 1: 0] dataout
  );
  
      reg [WIDTH - 1 : 0] piprData1;
      reg [WIDTH - 1 : 0] piprData2;
      reg [WIDTH - 1 : 0] piprData3;
  
      always @(posedge clk) begin
          piprData1 &lt;= datain;
      end
  
      always @(posedge clk) begin
          piprData2 &lt;= piprData1;
      end
  
      always @(posedge clk) begin
          piprData3 &lt;= piprData2;
      end
  
      assign dataout = piprData3;
  
  endmodule
  
  </code></pre>
  
  <pre><code>module blockingPipeline#2
  (
      parameter WIDTH = 100
  )
  (
      input                   clk,
      input                   rst,
      input                   validIn,
      input [WIDTH - 1 : 0]   dataIn,
      input                   outAllow,
      output wire                 validOut,
      output wire [WIDTH - 1 : 0]   dataOut
  );
  
      reg                 pipe1Valid;
      reg [WIDTH - 1 : 0] pipe1Data;
      reg                 pipe2Valid;
      reg [WIDTH - 1 : 0] pipe2Data;
      reg                 pipe3Valid;
      reg [WIDTH - 1 : 0] pipe3Data;
  
  
      /*------------------------PIPE1 LOGIC------------------------*/
      wire                pipe1AllowIn;
      wire                pipe1ReadyGo;
      wire                pipe1ToPipe2Valid;
  
      assign pipe1ReadyGo = 1'b1
  
      assign pipe1AllowIn = ! pipe1Valid || pipe1ReadyGo &amp;&amp; pipe2AllowIn;
  
      assign pipe1ToPipe2Valid = pipe1Valid &amp;&amp; pipe1ReadyGo
  
      always @(posedge clk)begin
  
          if( rst ) begin
              pipe1Vali &lt;= 1'b0;
          end
  
          else if(pipe1AllowIn)begin
              pipe1Valid &lt;= validIn;
          end
  
          ifvalidIn &amp;&amp; pipe1AllowIn)begin
             pipe1Data &lt;= dataIn;
          end
  
      end
  
      /*------------------------PIPE2 LOGIC------------------------*/
      wire                pipe2AllowIn;
      wire                pipe2ReadyGo;
      wire                pipe2ToPipe3Valid;
  
      assign pipe2ReadyGo = 1'b1;
      assign pipe2AllowIn = ! pipe2Valid || pipe2ReadyGo &amp;&amp; pipe3AllowIn;
      assign pipe2ToPipe3Valid = pipe2Valid &amp;&amp; pipe3ReadyGo;
  
      always @(posedge clk)begin
          if( rst ) begin
              pipe2Valid &lt;= 1'b0;
          end
          else if(pipe2AllowIn)begin
              pipe2Valid &lt;= pipe1ToPipe2Valid;
          end
          if(pipe1ToPipe2Valid &amp;&amp; pipe2AllowIn)begin
              pipe2Data &lt;= pipe1Data;
          end
      end
  
  
      /*------------------------PIPE3 LOGIC------------------------*/
      wire                pipe3AllowIn;
      wire                pipe3ReadyGo;
  
      assign pipe3ReadyGo = 1'b1;
      assign pipe3AllowIn = ! pipe3Valid || pipe3ReadyGo &amp;&amp; outAllow;
  
      always @(posedge clk)begin
          if( rst ) begin
              pipe3Valid &lt;= 1'b0;
          end
          else if(pipe3AllowIn)begin
              pipe3Valid &lt;= pipe2ToPipe3Valid;
          end
          if(pipe2ToPipe3Valid &amp;&amp; pipe3AllowIn)begin
              pipe3Data &lt;= pipe2Data;
          end
      end
  
      assign validOut = pipe3Valid &amp;&amp; pipe3ReadyGo;
      assign dataOut = pipe3Data;
  
  endmodule
  </code></pre>