title: Verilog error: not a valid l-value
body: <p>I'm trying to test if a wire(s) is on or not to signify if there is an error/overflow in my alu code. Given  this code:</p>
  
  <pre><code>output reg[3:0]x;                       // line 149
  output wire error;
  output wire overflow;
  
  always @* begin
      if(error || overflow) begin         
          assign x = 4'b1111;             // line 155
          assign error = ~error;
          assign overflow = ~overflow;
      end else begin
          assign x = opcode;
      end
  end
  </code></pre>
  
  <p>I get following error messages: </p>
  
  <p><a href="https://i.stack.imgur.com/xG2FA.jpg" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/xG2FA.jpg" alt="Errors"></a></p>
  
  <p><code>uut</code> is my instantiation unit in my testbench called <code>main</code></p>