title: Trouble with 8-bit Carry Lookahead Adder in Verilog
body: <p><a href="https://i.stack.imgur.com/DHaSU.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/DHaSU.png" alt="enter image description here"></a>
  I'm new to Verilog programming. I'm trying to put together an 8-bit Carry Lookahead Adder as a step toward building a 64-bit CLA. Basically, the way I implemented it is I use 2 4-bit CLA "blocks" to create the 8-bit CLA. I'll provide my code, then an explanation of the problem I'm having. </p>
  
  <p>Code below:</p>
  
  <pre><code>// 4-BIT CLA CODE
  module CLA4Bit(A, B, carryIn, carryOut, PG, GG, Sum);
      input[3:0] A, B;
      input carryIn;
      output carryOut;
  
      output PG;
      output GG;
  
      output[3:0] Sum;
  
      wire[3:0] G, P, C;
  
      assign G = A &amp; B;
      assign P = A ^ B;
      assign Sum = P ^ C;
  
      assign C[0] = carryIn;
  
      assign C[1] = G[0] | (P[0] &amp; C[0]);
      assign C[2] = G[1] | (P[1] &amp; G[0]) | (P[1] &amp; P[0] &amp; C[0]);
      assign C[3] = G[2] | (P[2] &amp; G[1]) | (P[2] &amp; P[1] &amp; G[0]) | (P[2] &amp; P[1] &amp; P[0] &amp; C[0]);
  
      assign PG = P[3] &amp; P[2] &amp; P[1] &amp; P[0];
      assign GG = G[3] | (P[3] &amp; G[2]) | (P[3] &amp; P[2] &amp; G[1]) | (P[3] &amp; P[2] &amp; P[1] &amp; G[0]);
  endmodule
  
  // 8-BIT CLA CODE BELOW
  module CLA8Bit(A, B, carryIn, carryOut, Sum);
  
      // 8-bit wire for the inputs A and B
      input[7:0] A, B;
  
      // Wire for the ORIGINAL carry-in
      input carryIn;
  
      // Wire for the carryOut
      output carryOut;
  
      // Wire that carries the Sum of this CLA
      output[7:0] Sum;
  
      // Wires for the propagate of the first 4-bit block (p3)
      // and the second (p7)
      wire p3, p7;
  
      // Wires for the generate of the first 4-bit block (g3)
      // and the second (g7)
      wire g3, g7;
  
      // Wires for the carry of the first block (c3) and the
      // second (c7)
      wire c3, c7;
  
      // The two 4-bit CLA blocks that make up the 8-bit CLA
  
      CLA4Bit block1(A[3:0], B[3:0], carryIn, c3, p3, g3, Sum[3:0]);
  
      CLA4Bit block2(A[7:4], B[7:4], c3, c7, p7, g7, Sum[7:4]);
  endmodule
  </code></pre>
  
  <p>I wrote a basic testbench to test my code:</p>
  
  <pre><code>module CLA_TB();
  
  // TEST THE 8-BIT CLA
  
      // Inputs
      reg[7:0] A;
      reg[7:0] B;
      reg carryIn;
  
      // Outputs
      wire carryOut;
      wire[7:0] Sum;
      wire PG;
      wire GG;
  
      // Instantiate the 8-bit CLA
      CLA8Bit CLA8BitDUT (
      .A(A),
      .B(B),
      .carryIn(carryIn),
      .carryOut(carryOut),
      .Sum(Sum)
      );
  
      // Initialize the testbench signals
      initial
          begin
  
          // Start with the carryIn set to 0
          assign carryIn = 0;
  
          // The standard first test. Set
          // A = b0000 0001 and B = b0000 0001
          // Answer should be Sum = b0000 0010
          assign A = 8'b00000001;
          assign B = 8'b00000001;
  
          #20
  
          // Next, set A = b0001 1011 and
          // B = b1101 0111. Answer should
          // be Sum = b1111 0010 = hF2.
          assign A = 8'b00011011;
          assign B = 8'b11010111;
  
          #20
  
          // Finally, try setting the carryIn
          // to 1 and then test A = b0111 1011
          // and B = b1101 0011. Answer should be
          // Sum = 0100 1111 w/ overflow carry
          assign carryIn = 1'b1;
          assign A = 8'b01111011;
          assign B = 8'b11010011;
  
          #20
  
          $finish;
  
          end
  
  endmodule
  </code></pre>
  
  <p>So the problem is, in my simulations of the testbench (I use ModelSim), the first 4 bits of the Sum (which correspond to the first 4-bit CLA instance in the 8-bit CLA module) are given as X in the Wave page. The second 4 bits add just fine, though.</p>
  
  <p>After doing some research, I found out that X's are displayed in Verilog when a wire has more than one driver (source of the signal?). However, I don't see any place where I send more than one signal to my first 4-Bit CLA instance in the 8-Bit CLA module. Also, if something like that were the cause, then I don't know why it wouldn't happen to the second set of 4 bits as well, since both the 4-bit CLAs are set up very similarly.</p>
  
  <p>Why is this happening?</p>