title: How to arrange a Makefile to compile a kernel module with multiple .c files?
body: <p>How to arrange a Makefile to compile a kernel module with multiple .c files?</p>
  
  <p>Here is my current Makefile. It was auto generated by <a href="http://www.kdevelop.org/" rel="noreferrer">KDevelop</a></p>
  
  <pre><code>TARGET = nlb-driver
  OBJS = nlb-driver.o
  MDIR = drivers/misc
  
  EXTRA_CFLAGS = -DEXPORT_SYMTAB
  CURRENT = $(shell uname -r)
  KDIR = /lib/modules/$(CURRENT)/build
  PWD = $(shell pwd)
  DEST = /lib/modules/$(CURRENT)/kernel/$(MDIR)
  
  obj-m += $(TARGET).o
  
  default:
      make -C $(KDIR) M=$(PWD) modules
  
  $(TARGET).o: $(OBJS)
      $(LD) $(LD_RFLAG) -r -o $@ $(OBJS)
  
  ifneq (,$(findstring 2.4.,$(CURRENT)))
  install:
      su -c "cp -v $(TARGET).o $(DEST) &amp;&amp; /sbin/depmod -a"
  else
  install:
      su -c "cp -v $(TARGET).ko $(DEST) &amp;&amp; /sbin/depmod -a"
  endif
  
  clean:
      -rm -f *.o *.ko .*.cmd .*.flags *.mod.c
      make -C $(KDIR) M=$(PWD) clean
  
  -include $(KDIR)/Rules.make
  </code></pre>