title: Recommended order of input and output ports in Verilog module declaration
body: <p>Being new to Verilog I noticed that lots of code is ordering their ports
  in module declarations with inputs first:</p>
  
  <pre><code>module do_something(
      input wire clk_in,
      input wire a_in,
      input wire b_in,
      output reg val_out);
  ....
  endmodule
  </code></pre>
  
  <p>(Almost the same way I'm used to it when programming in C/C++: inputs first, then outputs).</p>
  
  <p>However I've also seen examples with an opposite order of parameters (output first, inputs last).</p>
  
  <p>I hope this isn't a too dumb question:</p>
  
  <p>Is there any recommendation/best practice to prefer one over the other?
  So far I'd simply stick to "inputs first" but I wanted to ask before forming a bad habit.</p>