title: Facing errors while running VHDL code using EDA playground
body: <p>I'm trying to run the following VHDL code using EDA playground as no VHDL simulator is installed on my Laptop. The upper part is the source code and lower part is the testbench. However, getting some errors which need to be resolved. The errors are given below. Is there anyone can help to sort out the problem? Thanks in advance.</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.all;
  
  entity led_controller is
      Port (  clk, reset: in std_logic;                    
              in_word: in std_logic_vector(7 downto 0);   
              LEDs: out std_logic_vector(3 downto 0));
  end led_controller;
  
  architecture behavior of led_controller is
      --------------------- signals ---------------------
      type freq is array (0 to 3) of integer range 0 to 50000;
      signal frq: freq := (25000, 10000, 5000, 2500);      
      signal led_freq_count: integer range 0 to 50000 := frq(0);
  
      type d is array (0 to 3) of integer range 0 to 100;
      signal duty: d := (10, 30, 60, 85);      
      signal duty_cycle: integer range 0 to 100 := duty(0);        
      signal LED_switch, new_command: std_logic := '0';
  begin
  
      --------- clock process / sync reset configuration ---------------
      process (clk)
          variable duty_counter: integer range 0 to 100 := 100;
          variable freq_counter: integer range 0 to 50000 := led_freq_count;
      begin
          if rising_edge(clk) then
              ------- if reset was high or new in_word were arrived --------
  
              if reset = '1' or new_command = '1' then
                  LEDs &lt;= "0000";
                  duty_counter := 100;
                  freq_counter := led_freq_count;
                  new_command &lt;= '0';
              else  
              ------- blinking process --------
  
                  if freq_counter = 0 then 
                     freq_counter := led_freq_count;
                     LED_switch &lt;= not LED_switch;
                  else
                  freq_counter := freq_counter - 1;
                  end if;
  
                  if duty_counter = 0 then 
                     duty_counter := 100;
                  else
                  duty_counter := duty_counter - 1;
                  end if;
                  ------ output assignment -------
                  if LED_switch = '1' and duty_counter &lt; duty_cycle then
                      LEDs &lt;= "1111";
                  else 
                      LEDs &lt;= "0000";
                  end if;
              end if;
          end if; 
      end process;
  
      --------- input process---------------
      process (in_word)
      begin
          case in_word(3 downto 0) is
              when "0001" =&gt;   led_freq_count &lt;= frq(0);
              when "0010" =&gt;   led_freq_count &lt;= frq(1);
              when "0100" =&gt;   led_freq_count &lt;= frq(2);
              when "1000" =&gt;   led_freq_count &lt;= frq(3);
              when others =&gt;   led_freq_count &lt;= frq(0);
          end case;
          case in_word(7 downto 4) is
              when "0001" =&gt;   duty_cycle &lt;= duty(0);
              when "0010" =&gt;   duty_cycle &lt;= duty(1);
              when "0100" =&gt;   duty_cycle &lt;= duty(2);
              when "1000" =&gt;   duty_cycle &lt;= duty(3);
              when others =&gt;   duty_cycle &lt;= duty(0);
          end case; 
          new_command    &lt;= '1';
      end process;
  
  
  end behavior;
  </code></pre>
  
  <p>testbench.vhd:</p>
  
  <pre><code>initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
    #10000 $finish;
  end
  
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.all;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity main_testbench is
  end main_testbench;
  
  architecture behavior of main_testbench is
      component led_controller is 
          Port (  clk, reset: in std_logic;                   -- system clock is assumed 10KHz 
                  in_word: in std_logic_vector(7 downto 0);   -- LS 4 bits - frequency &amp; MS 4 bits - duty-cycle   
                  LEDs: out std_logic_vector(3 downto 0));    
      end component;
  
      signal clk, reset:  std_logic := '0';
      signal in_word:     std_logic_vector(7 downto 0) := "00010001"; -- 0.2 Hz, 10% duty cycle
      signal LEDs:        std_logic_vector(3 downto 0) := "0000";
  
      type in_word_commands is array (0 to 15) of std_logic_vector(7 downto 0);
      signal in_words: in_word_commands := ("00010001", "00010010", "00010100", "00011000", -- 10% duty cycle with 0.2Hz, 0.5Hz, 1Hz, 2Hz
                                            "00100001", "00100010", "00100100", "00101000", -- 30% duty cycle with 0.2Hz, 0.5Hz, 1Hz, 2Hz
                                            "01000001", "01000010", "01000100", "01001000", -- 60% duty cycle with 0.2Hz, 0.5Hz, 1Hz, 2Hz 
                                            "10000001", "10000010", "10000100", "10001000"); -- 85% duty cycle with 0.2Hz, 0.5Hz, 1Hz, 2Hz
      signal command_num : integer := 0;
  
  begin
      dut: led_controller port map (clk, reset, in_word, LEDs);
  
      clk &lt;= not clk after 50 us; -- 0.1ms/2 = 50us  
      command_num &lt;= 0 after 5000 ms when command_num = in_words'HIGH else command_num + 1 after 5000 ms;
      in_word &lt;= in_words(command_num); 
  end behavior;
  </code></pre>
  
  <blockquote>
    <p>[2018-05-13 10:40:56 EDT] vlib work &amp;&amp; vcom '-2008' design.vhd testbench.vhd  &amp;&amp; vsim -c -do "vsim testbench; vcd file dump.vcd; vcd
    add -r sim:/testbench/*; run 80000 ms; exit"<br>
    VSIMSA: Configuration file changed: <code>/home/runner/library.cfg</code><br>
    ALIB: Library <code>work</code>attached.   work = /home/runner/work/work.lib<br>
    Aldec, Inc. VHDL Compiler, build 2014.06.88<br>
    VLM Initialized with path: "/home/runner/library.cfg".<br>
    DAGGEN WARNING DAGGEN_0523: "The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available."<br>
    COMP96 File: design.vhd 
    COMP96 Compile Entity "led_controller"<br>
    COMP96 Compile Architecture "behavior" of Entity "led_controller"<br>
    COMP96 File: testbench.vhd<br>
    COMP96 ERROR COMP96_0016: "Design unit declaration expected." "testbench.vhd" 1 1<br>
    COMP96 Compile Entity "main_testbench"<br>
    COMP96 Compile Architecture "behavior" of Entity "main_testbench"<br>
    COMP96 Compile failure 1 Errors 0 Warnings  Analysis time :  40.0 [ms]<br>
    Exit code expected: 0, received: 1</p>
  </blockquote>