title: Output of "for" is unknown instead of 1 in Verilog
body: <p>I'm using Icarus iVerilog to synthesize and test my code but I'm getting unknown values when logically 1's should be appearing. Here's an example of what I'm trying to do.</p>
  
  <pre><code>reg [8:0] a = 000110100;
  wire [8:0] b = 0;
  
  generate
      genvar i;
      for (i = 8; i &gt; -1; i = i - 1)
      begin:loop
          assign b[i] = |a[8:i];
      end
  endgenerate
  </code></pre>
  
  <p>This should produce some gates in the form of</p>
  
  <pre><code>b[8] = a[8];
  b[7] = a[8] | a[7];
  b[6] = a[8] | a[7] | a[6];
  b[5] = a[8] | a[7] | a[6] | a[5];
  ...
  </code></pre>
  
  <p>My expected output is</p>
  
  <pre><code>000111111
  </code></pre>
  
  <p>I'm actually getting </p>
  
  <pre><code>000xxxxxx
  </code></pre>
  
  <p>I can't find any reason for the x's, and am starting to suspect it's an issue with iVerilog.</p>