title: L1 cache ports in ARM Cortex processors
body: <p>I did some reseach, but could not find much information. </p>
  
  <p>I'd like to know how many <strong>L1</strong> read and L1 write ports ARM embedded processors have and how wide the ports are. Specifically, I am interested in Cortex-A8, Cortex-A9, and Cortext-A15.</p>
  
  <p>My blind guess is that a Cortex-A9 processor has one L1 read port and one L1 write port which are 64 bits wide. My other guess is that it has a single shared read/write port. Any thoughts on that?</p>