title: vhdl "parse error, unexpected FOR"
body: <p>I try to write programm on vhdl in ise 14.4 for crc16 calculation but dont understand why get "parse error, unexpected FOR" in it. Tried to put it into process but it dont works too. </p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  
  entity crc16 is port(
  clk : in STD_LOGIC:='0');
  end crc16;
  
  architecture Behavioral of crc16 is
  signal data:std_logic_vector(15 downto 0):="1010101010101010";
  signal ext_data:std_logic_vector(31 downto 0);
  signal crc16_original:std_logic_vector(15 downto 0):="1100000000000010";
  signal crc16:std_logic_vector(15 downto 0);
  signal position:std_logic_vector(5 downto 0);
  signal crc_out:std_logic_vector(14 downto 0);
  signal i:std_logic_vector(5 downto 0);
  
  begin
  
  
  for i in 1 to 15 loop
      ext_data(i+16)&lt;=data(i);
  end loop;
  
  for i in 1 to 15 loop
      ext_data(i)&lt;='0';
  end loop;
  
  while ext_data &gt; "111111111111111" loop
          for i in 0 to 31 loop
              if ext_data(i)="1" position=i;
          end loop;
  
      crc16&lt;= crc16_original srl 31-position;
      ext_data&lt;=ext_data xor crc16;
  end loop;
  
  for i in 0 to 14 loop
      crc_out(i)&lt;=ext_data(i);
  end loop;
  
  
  end Behavioral;
  </code></pre>