title: Verilog: Check, if a signal is 100 ticks active?
body: <p>I have one input and one output. And I want to turn the output to 1, if the input was 100 ticks active (100 cycles). </p>
  
  <pre><code>module check_100(
     input wire clock,
     input wire reset,
     input wire in_a,
     output reg out_a);  
  
  reg[10:0] counter;  
  
  always @(posedge clock) begin
      counter &lt;= counter + 1;
      if(in_a &amp;&amp; (counter == 100)) begin
          out_a &lt;= 1;
      end
  end
  </code></pre>
  
  <p>But it doesn't seem to work properly.
  Is this a good way to check, whether a signal is 100 ticks/cycles active or not?  </p>
  
  <p>Thank you! :)</p>