title: variable clock generation in verilog using task
body: <p>I have used following code to generate clock (whichever value I pass through task it will create that frequency), but the code only works if I use <code>CLKSEL_global = clksel_local</code> (i.e. blocking assignment) but that creates delta delay.</p>
  
  <p>How do I generate variable clock without introducing delta delay? Is their another way of using a task. I am using task so that I can pass real values</p>
  
  <pre><code>`timescale 1ns/1ps
  module tb();
    real CLKSEL_global;
  
    reg CLK7;
  
  
    new dut(clk,clk_out);
  
    task task_CLOCK;
      input real clksel_local;
      begin
        CLKSEL_global = clksel_local;
      end
    endtask
  
    initial begin
      CLK7 = 0;
      forever begin
        #(500.0/CLKSEL_global) CLK7 = 1;
        #(500.0/CLKSEL_global) CLK7 = 0;
      end
    end
  
  
    initial begin
      task_CLOCK(340.0);
    end
  
    initial begin
      #100 $finish ;
    end
  endmodule
  </code></pre>