title: How to modify this Makefile to build c and cxx files separately?
body: <p>The following Makefile was working very well for C projects, but when we encountered a directory with <code>.cpp</code> files, we found the first pattern rule is getting used for <code>.cpp</code> files.  I've tried 3 or 4 changes to get the desired effect, and I can't seem to find a way.  I'd like to know if it's possible to make any minor alteration to the rules below so that the <code>.cpp</code> files are built with <code>COMPILE_CXX_COMMAND</code>.</p>
  
  <pre><code>C_EXT             ?= c
  CXX_EXT           ?= cpp
  OBJ_EXT           ?= o
  
  C_SRCS := \
  src/RT_Socket.c \
  src/products.c
  
  CXX_SRCS := \
  src/BurnedInAddress.cpp \
  src/DiskID.cpp \
  
  
  C_OBJ_FILES       += $(C_SRCS:.$(C_EXT)=.$(OBJ_EXT))
  CXX_OBJ_FILES     += $(CXX_SRCS:.$(CXX_EXT)=.$(OBJ_EXT))
  
  
  $(ARCHIVE_FILENAME) :   $(C_OBJ_FILES) $(CXX_OBJ_FILES)
      $(CREATE_ARCHIVE_COMMAND)
  
  $(LIBRARY_FILENAME) :   $(ARCHIVE_FILENAME)
      $(CREATE_LIBRARY_COMMAND)
  
  %.$(OBJ_EXT)        :   $(C_SRCS)
      $(COMPILE_C_COMMAND)
  
  %.$(OBJ_EXT)        :   $(CXX_SRCS)
      $(COMPILE_CXX_COMMAND)
  </code></pre>
  
  <p>EDIT:
  I want to add that I tried replacing the pattern targets with the list of <code>OBJ</code> files, and it works.  </p>
  
  <pre><code>$(C_OBJ_FILES)      :   $(C_SRCS)
      $(COMPILE_C_COMMAND)
  
  $(CXX_OBJ_FILES)    :   $(CXX_SRCS)
      $(COMPILE_CXX_COMMAND)
  </code></pre>
  
  <p>However, this creates a new problem.  We have to use some different versions of Make, and one of them fails with the following error whenever there are no <code>.cpp</code> files:</p>
  
  <blockquote>
    <p>No targets on dependency line. Stop.</p>
  </blockquote>
  
  <p>It references this line:  <code>$(CXX_OBJ_FILES) :   $(CXX_SRCS)</code></p>
  
  <p>Gnu make seems to have no problem with this situation, our other one does (OPUS Make).  Can anyone think of a workaround?</p>