title: Unitialized unsigned signals
body: <p>Came across the following sample code:</p>
  
  <pre><code>architecture arch of disp_mux is
    constant N:integer :=18;
    signal q_reg, q_next: unsigned(N-1 downto 0);
    signal sel: std_logic_vector(1 downto 0);
  begin
    process(clk, reset)
    begin
      if reset='1' then
        q_reg &lt;= (others=&gt;'0');
      elsif (clk'event and clk='1') then
        q_reg &lt;= q_next;
      end if;
    end process;
    q_next &lt;= q_reg + 1;
    sel &lt;= std_logic_vector(q_reg(N-1 downto N-2));
    process(sel, ...)
    begin
      case sel is...
      end case;
    end process;
  end arch;
  </code></pre>
  
  <p>If you never write <code>1</code> to <code>reset</code>, what is the value of <code>q_reg</code>? And what happens at <code>q_next &lt;= q_reg + 1;</code> when/if <code>q_reg</code> is <code>UUUUUUUUUUUUUUUUUU</code> which is what I suspect it is.</p>