title: Low Pass Filter in Verilog (De0 Nano)
body: <p>I'm learning verilog and was wondering how to implement a low pass filter in an fpga,</p>
  
  <p>I am looking for a cut off frequency of around 50Hz,
  I don't know how/where to start,</p>
  
  <p>Can anyone point me in the right direction to help me get started?</p>
  
  <p>Thanks in advance</p>