title: Is it possible to implement pipelining in a accumulator based machine/ISA?
body: <p>I am not sure if this is the correct place to ask this but here it goes:</p>
  <p>I was wondering if it is possible to implement pipelining stages into a Von-Neuman Architecture that uses an accumulator to hold a value along with a PC, memory buffer register, instruction register, and memory address register? There would also be a output register to hold the output and a input register to hold input.</p>
  <p>I was wondering this and was thinking that a 3-stage pipeline(Fetch,Decode,Execute) would be more feasible than a 5-stage pipeline as that would introduce the need of extra registers.</p>
  <p>Are there any examples of this and is it possible to implement theoretically?</p>