title: Intel: serializing instructions and branch prediction
body: <p><a href="http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html" rel="nofollow">The Intel Architecture's Developer's Manual</a> (Vol3A, Section 8-26), says:</p>
  
  <blockquote>
    <p>The Pentium processor and more recent processor families use
    branch-prediction techniques to improve performance by prefetching the
    destination of a branch instruction before the branch instruction is
    executed. <em>Consequently, instruction execution is not deterministically
    serialized when a branch instruction is executed.</em></p>
  </blockquote>
  
  <p>What does this mean? </p>
  
  <p>It sounds really, really bad. It sounds like a serializing instruction like CPUID breaks branch prediction (or vice-versa), but that seems unlikely. Can any ASM folks help me understand what "non-deterministic" means in this context.</p>
  
  <p>*Edited for clarity</p>