title: Passing a hexadecimal value into a module in Verilog
body: <p>I created a module that accepts a wire <code>[  4 : 0 ]</code> as input, and I'm using several instances of this module.  But, I'm getting:</p>
  
  <blockquote>
    <p>Syntax error in instance port expression(s)</p>
  </blockquote>
  
  <p>whenever I pass a value that contains A-F.</p>
  
  <p>For example:</p>
  
  <pre><code>key_schedule i1(09); // works
  key_schedule i1(0A); // doesn't work
  key_schedule i1(15); // works
  key_schedule i1(1D); // doesn't work
  </code></pre>
  
  <p>If anyone knows what's wrong, I'd appreciate their help.</p>
  
  <p>Also, what happens if I'm passing a value "C", but I also have a wire called <code>C</code>?</p>