title: VHDL assign integer indexed vector to enum indexed vector
body: <p>does anyone know if this is legal in VHDL?</p>
  
  <pre><code>type foo is (ONE, TWO, THREE);
  signal fooArray is array (foo'left to foo'right) of int;
  signal intArray is array (0 to 2) of int;
  
  fooArray &lt;= intArray;   -- is this statement legal?
  </code></pre>
  
  <p>as far as i can tell reading the VHDL LRM, array assignment is done by position, not by index. so i know that assigning arrays who's bounds are not equal but whose index lengths are equal is legal. but there is nothing that talks about assigning an array indexed by integers to an array indexed by an enumerated type. just wondering if anyone knows if this is legal or if the dominant VHDL simulators allow this?</p>
  
  <p>okay, i guess i should have indicated that the code was "pseudo-code" (and my vhdl coding sucks!). my main intent is to find out if VHDL allows the assignment of an array indexed by enum's to an array of the same size indexed by integers. so let's try this example:</p>
  
  <pre><code>entity eiv is
  end entity;
  
  architecture fooArch of eiv is
  
      type foo is (ONE, TWO, THREE);
      type fooArrayType is array(foo) of integer;
      type intArrayType is array(0 to 2) of integer;
  
      signal fooArray : fooArrayType;
      signal intArray : intArrayType;
  
  begin
  
  Statement:
      fooArray &lt;= intArray;   -- is this statement legal?
  
  end architecture;
  </code></pre>