title: Data hazard in MIPS-like pipeline architecture
body: <p>Let the following pipeline architecture:</p>
  
  <blockquote>
    <ol>
    <li>FETCH</li>
    <li>DECODE - READ REGISTERS</li>
    <li>READ MEMORY</li>
    <li>ALU</li>
    <li>STORE/READ MEMORY</li>
    <li>WRITE BACK - STORE TO REGISTERS</li>
    </ol>
  </blockquote>
  
  <p>We basically added a phase which enables us to read data from memory before ALU phase.</p>
  
  <p>Consider the following new commands:    </p>
  
  <pre><code>lwPointer $2, imm($3) # $2:= Memory[Memory[$3] + imm]`   
  swPointer $2, imm($3) # Memory[Memory[$3] + imm] := $2
  </code></pre>
  
  <p>Let the following program:  </p>
  
  <pre><code>1. add $3 $2 $1   
  2. lwPointer $1, 0($3)
  3. sw $7 0($3)
  </code></pre>
  
  <p>Why there's no data-hazard between for command <code>#3</code>? As I see it, <code>$3</code> decoded by command <code>#3</code> isn't updated.</p>