title: importing VHDL packages to SV from libraries other than WORK
body: <p>I have a VHDL module that is compiled to a library, say, <code>LIB_A</code>. The module has ports that are records, the corresponding type is defined in a package that is also compiled into <code>LIB_A</code>. I would like to write some assertions for the module and check them using OneSpin.</p>
  
  <p>At the moment I have the problem that I can access the simple ports of the module in SV, but I cannot access the ports that are record elements. I tried to import the VHDL package with <code>import</code> and different combinations of library/package names, but it didn't work. </p>
  
  <p>What is exactly the syntax of importing a VHDL package from the library <code>LIB_A</code>? Do I have to consider anything else?</p>
  
  <p>The code example:</p>
  
  <pre><code>import my_package::*; // LIB_A?
  
  module checker_m;
  
  
  // 
  // A plain SVA assertion
  // 
  always dummy_a: assert ( my_module.record_output.Reg1.some_sig == 0 );
  
  
  endmodule
  
  bind my_module checker_m checker_inst ();
  </code></pre>