title: 8 bit Ripple carry adder Port mappinng in VHDL
body: <p>I wrote the code for 8 bit adder by usign 4 bit carry look ahead adder. i instantiated the 4 bit caryy look ahed adder using port map. but i think i am wrong for port mapping . plese any one can hel me , how can i correct the port mapping ..</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity adder_4_bit is
  Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
  
         s : out  STD_LOGIC_VECTOR (3 downto 0);
         cout: out  STD_LOGIC);
  end adder_4_bit;
  
  architecture Behavioral of adder_4_bit is
  signal g, p, c, b1: STD_LOGIC_VECTOR(3 downto 0);
  
  begin
  g &lt;= a and b;
  p &lt;= a xor b;
  
  s(0) &lt;= p(0) ;
  c(0) &lt;= g(0) or p(0) ;
  
  s(1) &lt;= p(1) xor c(0);
  c(1) &lt;= g(1) or (p(1) and g(0)) or (p(1) and p(0));
  
  s(2) &lt;= p(2) xor c(1);
  c(2) &lt;= g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0)) or (p(2) and p(1) and p(0));
  
  s(3) &lt;= p(3) xor c(2);
  c(3) &lt;= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1)) or (p(3) and p(2) and p(1) and g(0)) or (p(3) and p(2) and p(1) and p(0));
  
  cout &lt;= c(3);
  
   end Behavioral;
  
  
  
  
  
  
  
  
   library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
   --********************************************************--
  entity Adder_8_bit is 
          Port ( 
                   a,b : in   STD_LOGIC_VECTOR (7 downto 0);          
                      s : out  STD_LOGIC_VECTOR (7 downto 0);
                   cout: out  STD_LOGIC
                );
  end Adder_8_bit;k
  ---******************---
  architecture Behavioral of Adder_8_bit is
  
  component  adder_4_bit is
       Port (
               A,B :  in   STD_LOGIC_VECTOR (3 downto 0);
                   S:   out   STD_LOGIC_VECTOR (3 downto 0);
               cout: out  STD_LOGIC
               );
  end component;
  ----
  signal a1 ,b1 :  STD_LOGIC_VECTOR (7 downto 0); 
  signal SUM    :  STD_LOGIC_VECTOR (7 downto 0); 
  
  begin 
  
  four_bit_adder1:  adder_4_bit port map ( a1(3 downto 0) ,b1(3 downto 0) , SUM (3 downto 0) , cout) ; 
  four_bit_adder2:  adder_4_bit port map ( a1(7 downto 4) ,b1(7 downto 4) , SUM (7 downto 4) , cout ) ; 
  
  end Behavioral;
  </code></pre>