title: Assign values to an array partially in VHDL?
body: <p>I have an array in VHDL of the form,</p>
  
  <pre><code>type CacheArray is array(0 to 15) of std_logic_vector(33 downto 0);
  signal cache_array: CacheArray := (others =&gt; (others =&gt; '0'));
  </code></pre>
  
  <p>I wish to assign values to this array such that only one bit of each index is initialized. I suspected something like this will work,</p>
  
  <pre><code>cache_array(15 downto 0)(33) &lt;= (others =&gt; '0');
  </code></pre>
  
  <p>But it gives the following error :- </p>
  
  <pre><code>Cache.vhd:72:16: direction of the range mismatch
  Cache.vhd:72:30: static constant violates bounds
  Cache.vhd:72:37: can't match character literal '0' with type array type "std_logic_vector"
  </code></pre>
  
  <p>In some sense, this is like a 2D matrix and I wish to initialize just one column completely.
  What can be done besides assigning the bits one by one?</p>