title: wildcard target in makefile doesn't work
body: <p>I have this simple rule in my <code>Makefile</code>:</p>
  
  <pre><code>PP=g++ -std=c++0x
  %.o: $.cpp
          $(PP) $&lt; -c -o $@
  </code></pre>
  
  <p>When I run <code>make parse_utils.o</code>, the command be executed should be:</p>
  
  <pre><code>g++ -std=c++0x parse_utils.cpp -c -o parse_utils.o
  </code></pre>
  
  <p>But in fact it's:</p>
  
  <pre><code>&gt;make parse_utils.o
  g++    -c -o parse_utils.o parse_utils.cpp
  </code></pre>
  
  <p>And I got a compile error because I used <code>C++11</code> syntax.</p>
  
  <p>Is this wildcard rule wrong?</p>