title: My counter "4-digit BCD Counter" does not work well!
body: <p>I have designed 4-digit BCD Counter and BCD-to-7segment Converter as a project of one of my courses in the university.</p>
  
  <p>Here is the circuit: <a href="http://img849.imageshack.us/img849/930/111vr.png" rel="nofollow noreferrer">http://img849.imageshack.us/img849/930/111vr.png</a></p>
  
  <p><img src="https://i.stack.imgur.com/58vlv.png" alt="enter image description here"></p>
  
  <p>and here is the source code:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity IC_74163 is
  port(LdN, ClrN, P, T, ClK: in std_logic;  
  D: in std_logic_vector(3 downto 0);
  Cout: out std_logic; Qout: out std_logic_vector(3 downto 0) );
  end entity;
  
  architecture IC_74163_1 of IC_74163 is
  signal Q: std_logic_vector(3 downto 0);    -- Q is the counter register
  begin
  Qout &lt;= Q;
  Cout &lt;= Q(3) and Q(2) and Q(1) and Q(0) and T;
  process (CLK)
  begin
  if CLK'event and CLK = '1' then     -- change state on rising edge
  if ClrN = '0' then  Q &lt;= "0000";
  elsif LdN = '0' then Q &lt;= D;
  elsif (P and T) = '1' then Q &lt;= Q+1;
     end if;
     end if;
  end process;
  end architecture;
  </code></pre>
  
  <p>==============================</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity Four_Digit_BCD_Counter is
  port(Clk: in std_logic;
       Q1, Q2, Q3, Q4: inout std_logic_vector(3 downto 0):= "0000");
  end entity;
  
  architecture Four_Digit_BCD_Counter_1 of Four_Digit_BCD_Counter is
  component IC_74163 is
  port(LdN, ClrN, P, T, ClK: in std_logic;  
  D: in std_logic_vector(3 downto 0);
  Cout: out std_logic; Qout: out std_logic_vector(3 downto 0) );
  end component;
  signal ClrN1, ClrN2, ClrN3, ClrN4: std_logic;
  signal T2, T3, T4: std_logic;
  begin
  ClrN1 &lt;= Q1(3) NOR Q1(0);
  ClrN2 &lt;= Q2(3) NOR Q2(0);
  ClrN3 &lt;= Q3(3) NOR Q3(0);
  ClrN4 &lt;= Q4(3) NOR Q4(0);
  T2 &lt;= not (Q1(3) NOR Q1(0));
  T3 &lt;= not (Q2(3) NOR Q2(0));
  T4 &lt;= not (Q3(3) NOR Q3(0));
  IC_1: IC_74163 port map ('1',ClrN1,'1','1',Clk,"ZZZZ",open,Q1);
  IC_2: IC_74163 port map ('1',ClrN2,'1',T2,Clk,"ZZZZ",open,Q2);
  IC_3: IC_74163 port map ('1',ClrN3,'1',T3,Clk,"ZZZZ",open,Q3);
  IC_4: IC_74163 port map ('1',ClrN4,'1',T4,Clk,"ZZZZ",open,Q4);
  end architecture;
  </code></pre>
  
  <p>==============================</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity BCD_to_Seven_Segment_Converter is
    port(B3, B2, B1, B0 :in std_logic; output:out integer range 0 to 9);
  end entity;
  
  architecture BCD_to_Seven_Segment_Converter_1 of BCD_to_Seven_Segment_Converter is
  signal ss:std_logic_vector(6 downto 0);
  signal a, b, c, d, e, f, g:std_logic;
  begin
  a &lt;= B3 or ((not B0) and (not B2)) or B1 or (B0 and B2);
  b &lt;= (not B2) or ((not B0) and (not B1)) or (B0 and B1);
  c &lt;= (not B1) or B0 or B2;
  d &lt;= B3 or ((not B0) and (not B2)) or ((not B0) and B1) or (B0 and (not B1) and B2) or (B1 and (not B2));
  e &lt;= ((not B0) and B1) or ((not B0) and (not B2));
  f &lt;= B3 or ((not B0) and B2) or ((not B0) and (not B1)) or ((not B1) and B2);
  g &lt;= B3 or ((not B1) and B2) or (B1 and (not B2)) or ((not B0) and B1);
  process(ss)
  begin
  case ss is
  when "1111110" =&gt; output &lt;= 0;
  when "0110000" =&gt; output &lt;= 1;
  when "1101101" =&gt; output &lt;= 2;
  when "1111001" =&gt; output &lt;= 3;
  when "0110011" =&gt; output &lt;= 4;
  when "1011011" =&gt; output &lt;= 5;
  when "1011111" =&gt; output &lt;= 6;
  when "1110000" =&gt; output &lt;= 7;
  when "1111111" =&gt; output &lt;= 8;
  when "1111011" =&gt; output &lt;= 9;
  when others =&gt; null;
  end case;
  end process;
  
  
  
  --process(input)
  --begin
  --case input is
  --when "0000" =&gt; output &lt;= "1111110";
  --when "0001" =&gt; output &lt;= "0110000";
  --when "0010" =&gt; output &lt;= "1101101";
  --when "0011" =&gt; output &lt;= "1111001";
  --when "0100" =&gt; output &lt;= "0110011";
  --when "0101" =&gt; output &lt;= "1011011";
  --when "0110" =&gt; output &lt;= "1011111";
  --when "0111" =&gt; output &lt;= "1110000";
  --when "1000" =&gt; output &lt;= "1111111";
  --when "1001" =&gt; output &lt;= "1111011";
  --when others =&gt; null;
  --end case;
  --end process;
  
  
  end architecture;
  </code></pre>
  
  <p>==============================</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity Project is
  port(Clk: in std_logic; Count: out integer range 0000 to 9999 := 0000);
  end entity;
  
  architecture The_Circiut of Project is
  component Four_Digit_BCD_Counter is
  port(Clk: in std_logic;
       Q1, Q2, Q3, Q4: inout std_logic_vector(3 downto 0):= "0000");
  end component;
  
  component BCD_to_Seven_Segment_Converter is
    port(B3, B2, B1, B0 :in std_logic; output:out integer range 0 to 9);
  end component;
  
  signal Qout1, Qout2, Qout3, Qout4: std_logic_vector(3 downto 0):= "0000";
  signal D0, D1, D2, D3:integer range 0 to 9;
  begin
  
  BCD_Counter_4Digit: Four_Digit_BCD_Counter port map (Clk, Qout1, Qout2, Qout3, Qout4);
  BCD_7Segment_Converter1: BCD_to_Seven_Segment_Converter port map (Qout1(0), Qout1(1), Qout1(2), Qout1(3), D0);
  BCD_7Segment_Converter2: BCD_to_Seven_Segment_Converter port map (Qout2(0), Qout2(1), Qout2(2), Qout2(3), D1);
  BCD_7Segment_Converter3: BCD_to_Seven_Segment_Converter port map (Qout3(0), Qout3(1), Qout3(2), Qout3(3), D2);
  BCD_7Segment_Converter4: BCD_to_Seven_Segment_Converter port map (Qout4(0), Qout4(1), Qout4(2), Qout4(3), D3);
  Count &lt;= D3 * 1000 + D2 * 100 + D1 * 10 + D0;
  end architecture;
  </code></pre>
  
  <p>The problem is that, <code>Count</code> stays <code>0</code> forever and does not change and count up. Could you help me to figure out the problem?</p>
  
  <p>====================================</p>
  
  <p><strong>EDIT:</strong></p>
  
  <p>Well, after I edited the problems that @MRAB and @Tomi Junnila mentioned the problem does not fixed!
  Also, I have tried to test <code>IC_74163</code> alone, and I think it is the source of the problem, it gives me <code>Qout</code> as <code>X</code> !! Can you guys test it for me please? I am using Active-HDL btw.</p>
  
  <p>====================================</p>
  
  <p><strong>EDIT2:</strong></p>
  
  <p>Here is the waveform for <code>IC_74163</code>: <a href="http://img851.imageshack.us/img851/8117/52226324.png" rel="nofollow noreferrer">http://img851.imageshack.us/img851/8117/52226324.png</a></p>
  
  <p><img src="https://i.stack.imgur.com/LV8y5.png" alt="enter image description here"></p>
  
  <p>====================================</p>
  
  <p><strong>EDIT3:</strong></p>
  
  <p>OK, the counter is working very well but I still have very small issue. I have four <code>std_logic_vector(3 downto 0)</code> which are <code>Qout1</code>, <code>Qout2</code>, <code>Qout3</code> and <code>Qout4</code> .. How can I convert them to an integer of 4 digits ? <code>std_logic_vector(3 downto 0):= "0000"</code> does not work well.</p>
  
  <p>====================================</p>
  
  <p><strong>EDIT4:</strong></p>
  
  <p>OK guys, the counter is working as required and there is no issue. Thank you for your help, I really appreciate it.</p>
  
  <p>Here is the final source code for anyone interested:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity IC_74163 is
  port(LdN, ClrN, P, T, ClK: in std_logic:='0';  
  D: in std_logic_vector(3 downto 0):="0000";
  Cout: out std_logic; Qout: inout std_logic_vector(3 downto 0):="0000");
  end entity;
  
  architecture IC_74163_1 of IC_74163 is
  begin
  Cout &lt;= Qout(3) and Qout(2) and Qout(1) and Qout(0) and T;
  process (CLK)
  begin
  if CLK'event and CLK = '1' then     -- change state on rising edge
  if ClrN = '0' then  Qout &lt;= "0000";
  elsif LdN = '0' then Qout &lt;= D;
  elsif (P and T) = '1' then Qout &lt;= Qout+1;
     end if;
     end if;
  end process;
  end architecture;
  </code></pre>
  
  <p>==============================    </p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity Four_Digit_BCD_Counter is
  port(Clk: in std_logic;
       Q1, Q2, Q3, Q4: inout std_logic_vector(3 downto 0):= "0000");
  end entity;
  
  architecture Four_Digit_BCD_Counter_1 of Four_Digit_BCD_Counter is
  component IC_74163 is
  port(LdN, ClrN, P, T, ClK: in std_logic;  
  D: in std_logic_vector(3 downto 0);
  Cout: out std_logic; Qout: inout std_logic_vector(3 downto 0) );
  end component;
  signal ClrN1, ClrN2, ClrN3, ClrN4: std_logic;
  signal T2, T3, T4: std_logic;
  begin
  ClrN1 &lt;= Q1(3) NAND Q1(0);
  ClrN2 &lt;= Q2(3) NAND Q2(0);
  ClrN3 &lt;= Q3(3) NAND Q3(0);
  ClrN4 &lt;= Q4(3) NAND Q4(0);
  T2 &lt;= not (Q1(3) NAND Q1(0));
  T3 &lt;= not (Q2(3) NAND Q2(0));
  T4 &lt;= not (Q3(3) NAND Q3(0));
  IC_1: IC_74163 port map ('1',ClrN1,'1','1',Clk,"ZZZZ",open,Q1);
  IC_2: IC_74163 port map ('1',ClrN2,'1',T2,Clk,"ZZZZ",open,Q2);
  IC_3: IC_74163 port map ('1',ClrN3,'1',T3,Clk,"ZZZZ",open,Q3);
  IC_4: IC_74163 port map ('1',ClrN4,'1',T4,Clk,"ZZZZ",open,Q4);
  end architecture;
  </code></pre>
  
  <p>==============================</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity BCD_to_Seven_Segment_Converter is
    port(B3, B2, B1, B0 :in std_logic; output:out integer range 0 to 9);
  end entity;
  
  architecture BCD_to_Seven_Segment_Converter_1 of BCD_to_Seven_Segment_Converter is
  signal ss:std_logic_vector(6 downto 0);
  signal a, b, c, d, e, f, g:std_logic;
  begin
  a &lt;= B3 or ((not B0) and (not B2)) or B1 or (B0 and B2);
  b &lt;= (not B2) or ((not B0) and (not B1)) or (B0 and B1);
  c &lt;= (not B1) or B0 or B2;
  d &lt;= B3 or ((not B0) and (not B2)) or ((not B0) and B1) or (B0 and (not B1) and B2) or (B1 and (not B2));
  e &lt;= ((not B0) and B1) or ((not B0) and (not B2));
  f &lt;= B3 or ((not B0) and B2) or ((not B0) and (not B1)) or ((not B1) and B2);
  g &lt;= B3 or ((not B1) and B2) or (B1 and (not B2)) or ((not B0) and B1);
  ss &lt;= a&amp;b&amp;c&amp;d&amp;e&amp;f&amp;g;
  process(ss)
  begin
  case ss is
  when "1111110" =&gt; output &lt;= 0;
  when "0110000" =&gt; output &lt;= 1;
  when "1101101" =&gt; output &lt;= 2;
  when "1111001" =&gt; output &lt;= 3;
  when "0110011" =&gt; output &lt;= 4;
  when "1011011" =&gt; output &lt;= 5;
  when "1011111" =&gt; output &lt;= 6;
  when "1110000" =&gt; output &lt;= 7;
  when "1111111" =&gt; output &lt;= 8;
  when "1111011" =&gt; output &lt;= 9;
  when others =&gt; null;
  end case;
  end process;
  
  --process(input)
  --begin
  --case input is
  --when "0000" =&gt; output &lt;= "1111110";
  --when "0001" =&gt; output &lt;= "0110000";
  --when "0010" =&gt; output &lt;= "1101101";
  --when "0011" =&gt; output &lt;= "1111001";
  --when "0100" =&gt; output &lt;= "0110011";
  --when "0101" =&gt; output &lt;= "1011011";
  --when "0110" =&gt; output &lt;= "1011111";
  --when "0111" =&gt; output &lt;= "1110000";
  --when "1000" =&gt; output &lt;= "1111111";
  --when "1001" =&gt; output &lt;= "1111011";
  --when others =&gt; null;
  --end case;
  --end process;
  
  
  end architecture;
  </code></pre>
  
  <p>==============================    </p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity Project is
  port(Clk: in std_logic; Count: out integer range 0000 to 9999 := 0000);
  end entity;
  
  architecture The_Circiut of Project is
  component Four_Digit_BCD_Counter is
  port(Clk: in std_logic;
       Q1, Q2, Q3, Q4: inout std_logic_vector(3 downto 0):= "0000");
  end component;
  
  component BCD_to_Seven_Segment_Converter is
    port(B3, B2, B1, B0 :in std_logic; output:out integer range 0 to 9);
  end component;
  
  signal Qout1, Qout2, Qout3, Qout4: std_logic_vector(3 downto 0):= "0000";
  signal D0, D1, D2, D3:integer range 0 to 9;
  begin
  BCD_Counter_4Digit: Four_Digit_BCD_Counter port map (Clk, Qout1, Qout2, Qout3, Qout4);
  BCD_7Segment_Converter1: BCD_to_Seven_Segment_Converter port map (Qout1(3), Qout1(2), Qout1(1), Qout1(0), D0);
  BCD_7Segment_Converter2: BCD_to_Seven_Segment_Converter port map (Qout2(3), Qout2(2), Qout2(1), Qout2(0), D1);
  BCD_7Segment_Converter3: BCD_to_Seven_Segment_Converter port map (Qout3(3), Qout3(2), Qout3(1), Qout3(0), D2);
  BCD_7Segment_Converter4: BCD_to_Seven_Segment_Converter port map (Qout4(3), Qout4(2), Qout4(1), Qout4(0), D3);
  Count &lt;= D3 * 1000 + D2 * 100 + D1 * 10 + D0;
  end architecture;
  </code></pre>