title: VHDL signed data in std_logic_vector to unsigned data
body: <p>I have an ADC (LTC1407A-1) on an FPGA board that is populating a 14-bit register with 2's compliment signed data. I want to convert this data to be unsigned:</p>
  
  <ul>
  <li>Source data range: <code>-8192 to 8191</code></li>
  <li>Target data range: <code>0 to 16383</code></li>
  </ul>
  
  <p>However, whatever I try, I can't seem to get the desired result. My current section of working code for the VHDL register module is as follows:</p>
  
  <pre><code>library IEEE;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_1164.all;
  
  entity reg10 is
      Port ( clk : in  STD_LOGIC;                         --50MHz clock
             reset : in  STD_LOGIC;                       --asynchronous reset
             i_load : in  STD_LOGIC;                      --load signal
             i_data : in  STD_LOGIC_VECTOR (13 downto 0); --data signal
             o_data : out  STD_LOGIC_VECTOR (15 downto 0) --output data
      );
  end reg10;
  
  architecture Behavioral of reg10 is
      signal s_data : STD_LOGIC_VECTOR(9 downto 0);
      signal f_data : STD_LOGIC_VECTOR(13 downto 0);
      signal t_sign : signed (13 downto 0);
  begin
      process(clk, reset)
      begin
          if reset = '1' then
              s_data &lt;= "0000000000";
          elsif clk'event and clk = '1' then
              t_sign &lt;= SIGNED(i_data);
              f_data &lt;= STD_LOGIC_VECTOR(t_sign);
              s_data &lt;= "00" &amp; f_data(13 downto 6);
          end if;
      end process;
      o_data &lt;= "000010" &amp; s_data(9 downto 0);
  end Behavioral;
  </code></pre>
  
  <p>I have done plenty of searching around and find lots of examples where the conversion can be done, but, I don't understand the correct approach to take. I have tried assigning <code>i_data</code> as <code>signed</code>, casting between variables internally, and many other recommended solutions, but all to no avail.</p>
  
  <pre><code>signal t_sign : signed (13 downto 0);
  f_data &lt;= conv_std_logic_vector(i_data, 14);
  </code></pre>
  
  <p>The code buffers a changing input vector, and formats the data into an output vector for a VGA controller to display.</p>
  
  <p>Help appreciated. Thanks.</p>