title: how to map reg values to the ports of other module
body: <p>i am an amateur in verilog. i am trying to call module divider. but i get errors like "Reference to vector reg 'qtnt' is not a legal net lvalue" in synthesis. i have tried using wires as inputs but when i tried to assign values to them an error message was recieved. please help</p>
  
  <pre><code>module euclid_mul(
    input[9:0] p0,p1,q0,
    input[19:0] tot,
    input clk,
    output reg [20:0] p2,
    output reg out_en,o1,o2
  );
  reg[20:0] dvr,dvd,qtnt,rem;
  reg[9:0] ph;
  reg[20:0] mul,res;
  reg enable,f1;
  
  initial f1=0;
  initial enable=0;
  
  divider div2(dvd,dvr,enable,qtnt,rem,f1);   
  
  always @ (negedge clk)
    begin 
      if(f1==0) begin
        mul=q0*p1;
        ph=p0;
        res={11'b00000000000,ph[9:0]}-mul;
        if(res[20])
          begin
            o1=1;
            dvd=-res;
          end
        else
          dvd=res;
          o2=1;
          dvr=tot;
          enable=1;
        end
      end
  
      always @(posedge f1)
        begin
          if(res[20]) 
            begin 
              p2=tot-rem;
              out_en=1;
            end
          else
            begin
              p2=rem;
              out_en=1;
            end
          end
        endmodule
  </code></pre>