title: Writing a Register File in VHDL
body: <p>I am trying to write a register file in VHDL. The file contains 16 64-bit registers. Each cycle, two registers are read and one register is written (given that writing is enabled). There should be a data bypass (forwarding) so that the value just written is forwarded directly to the output if we are reading and writing to/from the same register in a single cycle. </p>
  
  <p>My idea was to write on the rising edge and read on the falling edge of the clock in order to complete this in one cycle. However, my design isn't working (not that I expected it to since I don't believe that checking for a falling edge within an <strong>if</strong> block which checks for a rising edge would work as expected). </p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL;
  
  entity register_file is   
      port
      (
      outA          : out std_logic_vector(63 downto 0);
      outB          : out std_logic_vector(63 downto 0);
      input         : in  std_logic_vector(63 downto 0);
      writeEnable   : in std_logic;
      regASel       : in std_logic_vector(5 downto 0);
      regBSel       : in std_logic_vector(5 downto 0);
      writeRegSel   : in std_logic_vector(5 downto 0);
      clk           : in std_logic
      );
  end register_file;
  
  architecture behavioral of register_file is
  type registerFile is array(0 to 15) of std_logic_vector(63 downto 0);
  signal registers : registerFile;
  begin
  
      regFile: process(clk)
      begin
          if rising_edge(clk) then 
              if(writeEnable = '1') then
                  registers(to_integer(unsigned(writeRegSel))) &lt;= input;
              end if;
              if falling_edge(clk) then
                  outA &lt;= registers(to_integer(unsigned(regASel)));
                  outB &lt;= registers(to_integer(unsigned(regBSel)));
              end if;
          end if;
          if falling_edge(clk) then
                  outA &lt;= registers(to_integer(unsigned(regASel)));
                  outB &lt;= registers(to_integer(unsigned(regBSel)));
          end if;
      end process;
  end behavioral;
  </code></pre>
  
  <p>Any help would be appreciated.</p>