title: ModelSim - Simulating Button Presses
body: <p>I want to use four push buttons as inputs and three seven-segment LED displays as outputs. Two push buttons should step up and down through the sixteen RAM locations; the other two should increment and decrement the contents of the currently-displayed memory location. I am now trying to simulate my design using ModelSim test benches, with button presses. Here is what I believe to be the relevant portions of my code:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  entity DE2_TOP is
  
    port (
      KEY : in std_logic_vector(3 downto 0);         -- Push button
      );
  
  end DE2_TOP;
  
  architecture datapath of DE2_TOP is
  
  begin  
    U1: entity work.lab1 port map (
      key =&gt; key,         
    );
  
  end datapath;
  
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  entity raminfr is                     -STANDARD RAM INFERENCE
      port (
          clk : in std_logic;
          we : in std_logic;
          a : in unsigned(3 downto 0);
          di : in unsigned(7 downto 0);
          do : out unsigned(7 downto 0)
      );
  end raminfr;
  
  architecture rtl of raminfr is
  
  type ram_type is array (0 to 15) of unsigned(7 downto 0);
  signal RAM : ram_type;
  signal read_a : unsigned(3 downto 0);
  begin
  process (clk)
  begin
      if rising_edge(clk) then
          if we = '1' then
              RAM(to_integer(a)) &lt;= di;
          end if;
          read_a &lt;= a;
      end if;
  end process;
  do &lt;= RAM(to_integer(read_a));
  end rtl;
  
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  entity lab1 is
      port(
          clock : in std_logic;
          key : in std_logic_vector(3 downto 0); 
          );
  end lab1;
  
  architecture up_and_down of lab1 is
      signal value_in_ram : unsigned(7 downto 0);
      signal clk : std_logic;
      signal we : std_logic;
      signal value_counter    : unsigned(7 downto 0) ;
      signal register_counter : unsigned(3 downto 0);
          begin
      U1: entity work.raminfr port map (
          a   =&gt; register_counter,
          di  =&gt; value_counter,
          do  =&gt; value_in_ram,
          clk =&gt; clk,
          we  =&gt; we
      );
  
      process(clock)
          begin
              if rising_edge(clock) then
                  if (key(3)='0' and key(2)='0' and key(1)='1' and key(0)='0') then
                      value_counter &lt;= value_counter + "1";   
                  elsif (key(3)='0' and key(2)='0' and key(1)='0' and key(0)='1') then  
                      value_counter &lt;= value_counter - "1";   
                  elsif (key(3)='1' and key(2)='0' and key(1)='0' and key(0)='0') then
                      register_counter&lt;= register_counter + "1";
                      value_counter &lt;= value_in_ram;
                  elsif (key(3)='0' and key(2)='1' and key(1)='0' and key(0)='0') then
                      register_counter&lt;= register_counter - "1";
                      value_counter &lt;= value_in_ram;
                  end if;
              end if;
      end process;
  end architecture up_and_down;
  </code></pre>
  
  <p>The problem is that despite initializing "key" (the buttons) in my test bench, ModelSim still lists the object as "UUUU". Here is the code for my test bench, which is located in a separate file:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity DE2_TOP_TEST is
  end;
  
  architecture BENCH of DE2_TOP_TEST is
  signal KEY : std_logic_vector(3 downto 0);
  
  begin
      KEY&lt;="0010";
      U1: entity work.DE2_TOP port map (
          key=&gt;key,
      );
  end BENCH;
  </code></pre>
  
  <p>Anyone know what's wrong?</p>