title: VHDL - Successive Approximation Register
body: <p>I have a question about VHDL code I am attempting to write for a Successive approximation register for an ADC. </p>
  
  <p>In the Code shown below, will DigitalOutTemp be continuously updating throughout the for loop? or will it only recieve the value of OutTemp at the end of the Process? </p>
  
  <p>I think I may have the logic wrong but what I am trying to do is to have DigitalOutTemp going through a Digital to analog Converter and then into a comparator with the Analog signal I am measuring. The Comparator will then feed back into the register. &nbsp;</p>
  
  <pre><code>LIBRARY ieee;
  USE     ieee.std_logic_1164.all;
  
  ENTITY SARegister IS
  PORT (
      Comparator, Clock                     : IN std_logic;
      DigitalOutFinal, DigitalOutTemp   : OUT std_logic_vector (13 downto 0)
  );
  END;
  
  ARCHITECTURE Behavioural OF SARegister IS
  BEGIN
  
  PROCESS (CompIn, Clock)
      VARIABLE OutTemp : std_logic_vector (13 downto 0);
  BEGIN
      IF (rising_edge(Clock)) THEN
          OutTemp := "10000000000000";
  
          FOR i IN 13 downto 0 LOOP
  
              IF (Comparator = '0') THEN
                  OutTemp(i) := '0';
              END IF;
  
              IF (i &gt; 0) THEN
                  OutTemp(i - 1) := '1';
              END IF;
  
              DigitalOutTemp &lt;= OutTemp;
  
          END LOOP;
  
          DigitalOutFinal &lt;= OutTemp;
  
      END IF;
  
  END PROCESS;
  END;
  </code></pre>