title: test bench of a 32x8 register file VHDL
body: <p>I wrote the assembly code for this circuit in vhdl already. I want to simulate it with a test bench.</p>
  
  <p><img src="https://i.stack.imgur.com/BifOR.png" alt="enter image description here"></p>
  
  <ul>
  <li>RegWrite: 1 bit input (clock)</li>
  <li>Write Register Number: 3-bit input(write addresses)  </li>
  <li>Write Data: 32-bit input (data in)  Read</li>
  <li>Register Number A: 3-bit input (read addresses)</li>
  <li>Read Register Number B: 3-bit input (read adddresses)  </li>
  <li>Port A:  32-bit output (data out)  </li>
  <li>Port B: 32-bit output (data out)</li>
  </ul>
  
  <p>I think my problem is that I don't understand what this circuit does. I chose random values to assign to the inputs, but it didn't output anything. What are good inputs to choose for this circuit?</p>
  
  <p>here is my test bench file for reference:</p>
  
  <pre><code>library ieee; 
  use ieee.std_logic_1164.all; 
  
  entity Reg_TB is     -- entity declaration 
  end Reg_TB; 
  
  architecture TB of Reg_TB is 
  component RegisterFile_32x8
  port (  RegWrite: in std_logic; 
      WriteRegNum: in std_logic_vector(2 downto 0);
      WriteData: in std_logic_vector(31 downto 0);
      ReadRegNumA: in std_logic_vector(2 downto 0);
      ReadRegNumB: in std_logic_vector(2 downto 0);
      PortA: out std_logic_vector(31 downto 0);
      PortB: out std_logic_vector(31 downto 0)
   ); 
  end component; 
  
  signal T_RegWrite : std_logic;
  signal T_WriteRegNum: std_logic_vector(2 downto 0);
  signal T_WriteData: std_logic_vector(31 downto 0);
  signal T_ReadRegNumA: std_logic_vector(2 downto 0);
  signal T_ReadRegNumB: std_logic_vector(2 downto 0);
  signal T_PortA : std_logic_vector(31 downto 0);
  signal T_PortB : std_logic_vector(31 downto 0);
  
  begin 
  T_WriteRegNum &lt;= "011";
  T_WriteData &lt;= "00000000000000000000000000000001";
  T_ReadRegNumA &lt;= "001";
  T_ReadRegNumB &lt;= "100";
  U_RegFile: RegisterFile_32x8 port map 
  (T_RegWrite, T_WriteRegNum,    T_WriteData,T_ReadRegNumA, T_ReadRegNumB, T_PortA, T_PortB); 
  
  -- concurrent process to offer clock signal 
  process 
  begin 
  
  
  T_RegWrite &lt;= '0'; 
  wait for 5 ns; 
  T_RegWrite &lt;= '1'; 
  wait for 5 ns; 
  end process; 
  process 
   begin 
  wait for 12 ns; 
  -- case 2 
  wait for 28 ns; 
  -- case 3 
  wait for 2 ns; 
  -- case 4 
  wait for 10 ns; 
  -- case 5 
  wait for 20 ns; 
  wait; 
   end process; 
  end TB; 
  </code></pre>
  
  <p>as you can see I chose</p>
  
  <ul>
  <li>WriteRegNum = "011"</li>
  <li>WriteData = "00000000000000000000000000000001"</li>
  <li>ReadRegNumA = "001"</li>
  <li>ReadRegNumB = "100" </li>
  </ul>
  
  <p>I think that I chose bad inputs. The simulation does this:</p>
  
  <p><img src="https://i.stack.imgur.com/1yeDg.png" alt="enter image description here"></p>