title: When are x86 LFENCE, SFENCE and MFENCE instructions required?
body: <p>Ok, I have been reading the following Qs from SO regarding x86 CPU fences (<code>LFENCE</code>, <code>SFENCE</code> and <code>MFENCE</code>):</p>
  
  <ul>
  <li><p><a href="https://stackoverflow.com/questions/20316124/does-it-make-any-sense-instruction-lfence-in-processors-x86-x86-64">Does it make any sense instruction LFENCE in processors x86/x86_64?</a></p></li>
  <li><p><a href="https://stackoverflow.com/questions/20326280/what-is-the-impact-sfence-and-lfence-to-caches-of-neighboring-cores/20329574#20329574">What is the impact SFENCE and LFENCE to caches of neighboring cores?</a></p></li>
  <li><p><a href="https://stackoverflow.com/questions/27522190/is-the-mesi-protocol-enough-or-are-memory-barriers-still-required-intel-cpus">Is the MESI protocol enough, or are memory barriers still required? (Intel CPUs)</a></p></li>
  </ul>
  
  <p>and:</p>
  
  <ul>
  <li><p><a href="http://www.puppetmastertrading.com/images/hwViewForSwHackers.pdf" rel="noreferrer">http://www.puppetmastertrading.com/images/hwViewForSwHackers.pdf</a></p></li>
  <li><p><a href="https://onedrive.live.com/view.aspx?resid=4E86B0CF20EF15AD!24884&amp;app=WordPdf&amp;authkey=!AMtj_EflYn2507c" rel="noreferrer">https://onedrive.live.com/view.aspx?resid=4E86B0CF20EF15AD!24884&amp;app=WordPdf&amp;authkey=!AMtj_EflYn2507c</a></p></li>
  </ul>
  
  <p>and I must be honest I am still not totally sure when a fence is required. I am trying to understand from the perspective of removing fully-blown locks and trying to use more fine-granular locking via fences, to minimise latency delays.</p>
  
  <p>Firstly here are two specific questions I do not understand:</p>
  
  <p>Sometimes when doing a store a CPU will write to its store buffer instead of the L1 cache. I do not however understand the terms on which a CPU will do this?</p>
  
  <p>CPU2 may wish to load a value which has been written in to CPU1's store buffer. As I understand it, the problem is CPU2 cannot see the new value in CPU1's store buffer. Why can't the MESI protocol just include flushing store buffers as part of its protocol??</p>
  
  <p>More generally, could somebody please attempt to describe the overall scenario and help explain when <code>LFENCE</code>/<code>MFENCE</code> and <code>SFENCE</code> instructions are required?</p>
  
  <p>NB One of the problems reading around this subject is the number of articles written "generally" for multiple CPU architectures, when I am only interested in the Intel x86-64 architecture specifically.</p>