title: what is #define equivalent in VHDL
body: <p>what is the equivalent of #define, #ifdef and #ifndef in VHDL?</p>
  
  <p>I want to use generics as #define, and change the design according to them. as a simple example: define a string generic and use it to determine if the clock is single or differential.</p>
  
  <pre><code>generic (
    something : boolean := FALSE;
    CLK_MODE : string := "SINGLE_ENDED"
  );
  </code></pre>
  
  <p>Now, How to change the logic according to the generics? one can of course write 2 possible logic descriptions with a simple if statement but then both will be synthesized (although only one is really used).</p>
  
  <p>Also, Is it possible to change the ports according to the generic? for the CLK example, 2 in ports are needed for differential clock but only one is needed for single ended clock. how to enable or disable the second port according to the generic?</p>