title: Verilog. Multidimensional array initialization
body: <p>I create localparam in my simulation-only SystemVerilog module:</p>
  
  <pre><code>   localparam [31:0] SYNTH_PRD_REGS[1][5][13] = '{
                   '{
    '{32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000},
    '{32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000},
    '{32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000},
    '{32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000},
    '{32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000,32'h00000000}                             
                  }
   }; // Error for this line.
  </code></pre>
  
  <p>I compile this module, but when I start simulation, error expected:</p>
  
  <blockquote>
    <p>RUNTIME: Fatal Error: RUNTIME_0123 tb_bus.sv (35): Range width
    expression must be positive.</p>
  </blockquote>
  
  <p>Why this error occurs? I use Active -HDL 9.3.</p>