title: Assigning value to a register in a module instance in verilog
body: <p>I am a beginner to verilog. I was trying to execute this code to store a value in a register which is in an instance of another module. Here are the two modules.</p>
  
  <pre><code>module main;
  reg [15:0] A;
  wire [15:0] B;
  initial
  begin
      A = 16'h1212;
  end
  copy a(B,A);
  endmodule  
  
  module copy(B,A);
  input [15:0] A;
  output reg [15:0] B;
  initial
     B=A;
  endmodule
  </code></pre>
  
  <p>The code compiles fine but on execution the value of B is 'unknown'. 
  If such an assignment is not possible, is there any other way to assign a value to a register in a module instance(from an input to that instance)?</p>
  
  <p>I am using ModelSim Altera Web Edition 6.3</p>