title: Using a file name string as a SystemVerilog interface parameter?
body: <p>Is it possible to use a string as a SystemVerilog interface paramter.  I have 4 instances of the same interface, and I was wondering if I can `include different assertion files for each instance.</p>
  
  <p>My interface looks like this:</p>
  
  <pre><code>interface dai_if #(P_WD_DATA = 24,
                     string P_FILE_NAME = "assertion_file_name")();
  
  
      //Internal Signal Defined Here
  
  
      `include "assertion_file_name"
  
  endinterface : dai_if
  </code></pre>
  
  <p>In the top level, where I instantiate the four instances I have the following code:</p>
  
  <pre><code>module tb_top;
  
      parameter P_WD_DATA = 24;
      parameter string DAI_SER_IN_FILE  = "dai_ser_in_checkers.v";
      parameter string DAI_SER_OUT_FILE = "dai_ser_out_checkers.v";
      parameter string DAI_PAR_IN_FILE  = "dai_par_in_checkers.v";
      parameter string DAI_PAR_OUT_FILE = "dai_par_out_checkers.v";
  </code></pre>
  
  <p>Then I instanced each of the interfaces like this:</p>
  
  <pre><code>dai_if #(.P_WD_DATA(P_WD_DATA),
           .P_FILE_NAME(DAI_SER_IN_FILE))
           dai_ser_ivif();
  </code></pre>
  
  <p>Is this the correct method, or am I missing something?</p>
  
  <p>Thanks</p>