title: VHDL: How to declare a variable width generic
body: <p>I want to create a VHDL entity with a one generic that changes the width of another generic.</p>
  
  <pre><code>entity lfsr_n is 
  generic (
      WIDTH           : integer := 32; -- counter width
      POLYNOMIAL      : std_logic_vector (WIDTH-1 downto 0) := "1000_0000_0000_0000_0000_0000_0110_0010"
  );
  </code></pre>
  
  <p>Unfortunately, it seems I can't reference an earlier defined generic later in the generic list. Active-HDL gives the following errors:</p>
  
  <p>Error: COMP96_0300: modules/m3_test_load/lfsr_n.vhd : (26, 45): Cannot reference "WIDTH" until the interface list is complete.</p>
  
  <p>Error: COMP96_0077: modules/m3_test_load/lfsr_n.vhd : (26, 66): Undefined type of expression. Expected type 'STD_LOGIC_VECTOR'.</p>
  
  <p>One workaround would be to make POLYNOMIAL a port. But it properly should be a generic since since the value is constant at elaboration time. I know that if I apply a constant to the port, it will synthesize the way I want and optimize the constants values into the module, but I'd like to find someway to make it a generic. Any suggestions how to do this?</p>