title: how to connect output of one entity with the input of other entity
body: <p>my vhdl code is as follows:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_unsigned.all;
  
  
  ENTITY pc IS PORT(
  d   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
  clk : IN STD_LOGIC; -- clock.
  q   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- output
  );
  END pc;
  
  ARCHITECTURE description OF pc IS
  BEGIN
  process(clk)
  begin
      if rising_edge(clk) then
              q &lt;= d;
      else
               q &lt;= x"00000000";
      end if;
  end process;
  END description;
  
  
  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_unsigned.all;
  
  entity ins_memory is
  port( inp1 : in std_logic_vector(31 downto 0);
    oup1 : out std_logic_vector (4 downto 0);
    clk : in std_logic);
  end ins_memory;
  
  architecture behv1 of ins_memory is
  type ROM_Array is array (0 to 14)
  of std_logic_vector(4 downto 0);
  constant Content: ROM_Array := (
  0 =&gt; "00001",
  -- Suppose ROM has
  1 =&gt; "00010",
  -- prestored value
  2 =&gt; "00011",
  -- like this table
  3 =&gt; "00100",
  --
  4 =&gt; "00101",
  --
  5 =&gt; "00110",
  --
  6 =&gt; "00111",
  --
  7 =&gt; "01000",
  --
  8 =&gt; "01001",
  --
  9 =&gt; "01010",
  --
  10 =&gt; "01011",
  --
  11 =&gt; "01100",
  --
  12 =&gt; "01101",
  --
  13 =&gt; "01110",
  --
  14 =&gt; "01111",
  --
  OTHERS =&gt; "11111"
  --
  );
  
  component pc IS PORT(
  d   : IN STD_LOGIC_VECTOR(31 DOWNTO 0) :=x"00000000";
  clk : IN STD_LOGIC; -- clock.
  q   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
  END component;
  
  begin
  D1: pc port map(q=&gt; inp1,clk=&gt;clk,d=&gt;open);
  process(inp1,clk)
  begin
  oup1&lt;= Content (conv_integer(inp1));
  end process;
  
  end behv1;
  </code></pre>
  
  <p>basically, I trying to connect 'signal q' which is output of entity pc with 'signal inp1' which is input of entity ins_memory, but I am getting following error when I tried it in simple way </p>
  
  <p><strong>D1: pc port map(q=> inp1,clk=>clk,d=>open);
    Updating port BEHV1:INP1 of mode IN is not allowed.
    Please verify the port mapping for correctness.</strong></p>