title: Why do x86-64 instructions on 32-bit registers zero the upper part of the full 64-bit register?
body: <p>In the <a href="http://x86asm.net/articles/x86-64-tour-of-intel-manuals/" rel="noreferrer">x86-64 Tour of Intel Manuals</a>, I read</p>
  
  <blockquote>
    <p>Perhaps the most surprising fact is that an instruction such as <code>MOV EAX, EBX</code> automatically zeroes upper 32 bits of <code>RAX</code> register.</p>
  </blockquote>
  
  <p>The Intel documentation (3.4.1.1 General-Purpose Registers in 64-Bit Mode in manual Basic Architecture) quoted at the same source tells us:</p>
  
  <blockquote>
    <ul>
    <li>64-bit operands generate a 64-bit result in the destination general-purpose register.</li>
    <li>32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in the destination general-purpose register.</li>
    <li>8-bit and 16-bit operands generate an 8-bit or 16-bit result. The upper 56 bits or 48 bits (respectively) of the destination general-purpose register are not be modified by the operation. If the result of an 8-bit or 16-bit operation is intended for 64-bit address calculation, explicitly sign-extend the register to the full 64-bits.</li>
    </ul>
  </blockquote>
  
  <p>In x86-32 and x86-64 assembly, 16 bit instructions such as</p>
  
  <pre><code>mov ax, bx
  </code></pre>
  
  <p>don't show this kind of "strange" behaviour that the upper word of eax is zeroed.</p>
  
  <p>Thus: what is the reason why this behaviour was introduced? At a first glance it seems illogical (but the reason might be that I am used to the quirks of x86-32 assembly).</p>