title: Does SystemVerilog support downcasting?
body: <p>Does SystemVerilog support downcasting (casting a base object to a derived object)? If so, how?</p>
  
  <p>The following downcast example does not work:</p>
  
  <pre><code>class base;
    int a = 5;
  endclass
  
  class extend extends base;
    int b = 1;
  endclass
  
  module test;
  
    initial begin
      base m_base;
      extend m_extend;
  
      m_base = new();
      m_extend = new();
      $cast(m_extend, m_base);
      $display(m_extend.a);
    end
  endmodule
  </code></pre>
  
  <p>Modify and rerun the example on EDA Playground: <a href="http://www.edaplayground.com/s/4/581" rel="noreferrer">http://www.edaplayground.com/s/4/581</a></p>