title: Selection of specific physical interface in default UVM register layer sequences
body: <p>In our DUT, we have two separate independent physical interfaces (APB &amp; I2C) (active 1 at a time) through which all registers can can be accessed,</p>
  
  <p>Also in our register model, we created two reg_maps, one for each APB &amp; I2C.</p>
  
  <p>Now through testcase, we want only one physical interface at a time, to be subjected to default uvm sequences (i.e. uvm_reg_access_seq, uvm_reg_bit_bash_seq,etc) but it is not possible as uvm_sequence will get all the maps using get_maps();</p>
  
  <p>So <strong>without over-riding</strong> the default uvm_reg_access_seq, is it possible to achieve such type of configuration in testcase itself via using uvm_reg_map or some other methods.</p>
  
  <p>Kindly refer following pseudo code</p>
  
  <pre><code>//Pseudo Code for Scenario
   class  dut_reg_test extends base_test;
    `uvm_component_uti ls(dut_reg_test)
  
    //Handle of default uvm register access sequence
    uvm_reg_access_seq my_reg_seq;
    // Select Physical Interface
    rand bit APB_I2C;
  
    uvm_reg_map test_map;
    dut_reg_model regmodel;
  
    task buid_phase (uvm_phase phase);
      super.build_phase(phase);
      // Select PHY Interface via commandline
        if ($value$plusargs("APB_I2C=%b", APB_I2C))
       else
          APB_I2C = $random;
  
      if (APB_I2C)
         test_map = regmodel.apb
      else
         test_map = regmodel.i2c
    endtask : build_phase
  
     task main_phase (uvm_phase phase); 
      //Create method for sequence
      my_reg_seq=uvm_single_access_seq::type_id::create("my_reg_seq");
      //Randomize with selected map
      my_reg_seq.randomize with { maps == test_map;});
      // Start default sequence
       my_reg_seq.start(NULL);
     endtask : main_phase
  
  endclass : dut_reg_test
  </code></pre>
  
  <p>The above strategy cannot be implemented because uvm_reg_access sequence doesn't contain uvm_reg_map it's only present in uvm_reg_single_access_seq,</p>
  
  <p>Similar kind of limitations persists will all uvm_reg_bit_bash_seq &amp; reset sequences.</p>
  
  <p>Can we have some strategy to resolve this issue ?</p>
  
  <ul>
  <li>Nikunj Hinsu</li>
  </ul>