title: Better way of coding a RAM in Verilog
body: <p>Which code is better in writing a RAM?</p>
  
  <ol>
  <li><p>assigning <code>data_out</code> inside <code>always</code> block:</p>
  
  <pre><code>module memory(
      output reg [7:0] data_out,
      input [7:0] address,
      input [7:0] data_in, 
      input write_enable,
      input clk
  );
      reg [7:0] memory [0:255];
  
      always @(posedge clk) begin
          if (write_enable) begin
              memory[address] &lt;= data_in;
          end
          data_out &lt;= memory[address];
      end
  
  endmodule
  </code></pre></li>
  <li><p>assigning <code>data_out</code> using <code>assign</code> statement:</p>
  
  <pre><code>module memory(
      output [7:0] data_out,
      input [7:0] address,
      input [7:0] data_in, 
      input write_enable,
      input clk
  );
      reg [7:0] memory [0:255];
  
      always @(posedge clk) begin
          if (write_enable) begin
              memory[address] &lt;= data_in;
          end
      end
  
      assign data_out = memory[address];
  
  endmodule
  </code></pre></li>
  </ol>
  
  <p>Any recommendations?</p>