title: Why doesn't my code produce output?
body: <p>I'm new to VHDL and I've just been messing around with Quartus II 9.0 and decided to make a register type component. I think my logic is right but I'm not getting any output when I run the simulation. I created a waveform to test possible situations (used node finder to list all inputs and output, generated the functional simulation netlist) but I do not get any output for Q. Not even the simple case when clr = 1 and all of Q should be set to 0. </p>
  
  <pre><code>library ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.std_logic_arith.ALL;
  USE ieee.std_logic_unsigned.ALL;
  
  ENTITY Register32 IS PORT ( 
      d     : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- input.
      ld    : IN STD_LOGIC; -- load/enable.
      clr   : IN STD_LOGIC; -- async. clear.
      clk   : IN STD_LOGIC; -- clock.
      Q     : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)); -- output.
  END Register32;
  
  ARCHITECTURE description OF Register32 IS
  BEGIN
  
      process (clk) begin
          if (clr = '1') then
              Q &lt;= (others =&gt; '0');
          else
              if (rising_edge(clk)) then
                  if (ld = '1') then
                      Q &lt;= d;
                  end if;
              end if;
          end if; 
      end process;
  
  END description;
  </code></pre>