title: Passing string values to SystemVerilog parameter
body: <p>I have a problem in passing a string value to a generic parameter in SystemVerilog. 
  The modules are instantiated as shown below. The memory writes some values to FILE_OUT, which is a generic parameter.
  I need to produce two different files - "file1.txt" and "file2.txt", for different instances of the memory.</p>
  
  <p>Initially I tried to use <code>`define</code> directive:</p>
  
  <pre><code>if(ch_ID==1)
    `define FILE_OUT file1.txt
  else
    `define FILE_OUT file2.txt 
  </code></pre>
  
  <p>But, since `define creates global macros, simulation was always giving the output "file2.txt"</p>
  
  <p>Then I tried passing file name as a parameter</p>
  
  <pre><code>if(ch_ID==1)
    parameter FILE_OUT= "file1.txt"
  else
    parameter FILE_OUT= "file2.txt"
  
  memory #(.FILE_OUT (FILE_OUT)) mem
  </code></pre>
  
  <p>This gives me the error- "FILE_OUT" should be a constant value".</p>
  
  <p>Doesn't SV support string values as parameter? If not, why is it accepting a string value when I use <code>`define</code> ?</p>
  
  <p>Could someone help me in solving this problem?  </p>
  
  <p><img src="https://i.stack.imgur.com/7qwCk.png" alt="enter image description here"></p>