title: Connecting hierarchical modules: struct vs interface in SystemVerilog
body: <p>In SystemVerilog hierarchical modules can be connected by simple data types, complex data types (structs, unions, etc), or interfaces. The feature that I am interested in is aggregating all signals between two modules in one place which simplifies maintenance of the code. </p>
  
  <p>For example in the following one change s_point's definition without changing the declarations of m1, m2, and top:</p>
  
  <pre><code> typedef struct {
    logic [7:0] x;
    logic [7:0] y;
  } s_point; // named structure
  
  
  module m1 (output s_point outPoint);
  //
  endmodule
  
  module m2 (input s_point inPoint);
  //
  endmodule
  
  module top ();
      s_point point;
      m1 m1_inst (point);
      m2 m2_inst (point);
  endmodule
  </code></pre>
  
  <p>Alternatively, this could have been done using interfaces. 
  However, I believe using structures are easier and they are supported by more CAD tools, and they don't need to be instantiated as is the case for interfaces (although one still has to declare them in the top module).</p>
  
  <p>My question is if only aggregating signals is required (i.e. no interest in interface's task, functions, modports, generic interface, internal always blocks etc) for a synthesizable design, which one is preferred?</p>