title: Accessing wire/reg dimensions in Verilog
body: <p>In VHDL there are many predefined attributes that can help in making code more generic, e.g.: </p>
  
  <pre><code>signal sig : std_logic_vector(7 downto 0);  
  -- ...  
  for i in sig'range loop ...
  </code></pre>
  
  <p>Is there a similar way to access the dimensions of a Verilog <code>wire</code> or <code>reg</code>?</p>
  
  <p>Of course it's possible to define the boundaries of each <code>wire</code> or <code>reg</code> as a parameter as in:</p>
  
  <pre><code>parameter w_upper = 7;  
  parameter w_lower = 0;  
  wire [w_upper:w_lower] w; 
  </code></pre>
  
  <p>but that seems like a lot of overhead and far less elegant than VHDL.</p>
  
  <p>I have seen that SystemVerilog has things like <code>$bits</code>, <code>$size</code>, <code>$high</code> and <code>$low</code>, but what about Verilog-2005 or earlier?</p>