title: Why are output nets also required to be redeclared as either 'wire' or 'reg'?
body: <p>Why do we have to take the same variable name of an output and also wire for getting the value? eg:</p>
  
  <pre><code> module TEST(INP1,INP2,CIN,COUT,SUM);
   input [31:0] INP1;
   input [31:0] INP2;
   output [31:0] SUM;
   input CIN;
   output COUT;
  
   wire [31:0] SUM;// Again redefined 
   wire COUT; // Again Redefined
   assign {COUT,SUM} = INP1 + INP2 + CIN ;
  </code></pre>
  
  <p>Example for getting the Carry-out and the Sum of two numbers and Carry-In taken as the input.  </p>