title: CUDA - Coalescing memory accesses and bus width
body: <p>So the idea that I have about coalescing memory accesses in CUDA is, that threads in a warp should access contiguous memory addresses, as that will only cause a single memory transaction (the values on each address are then broadcast to the threads) instead of multiple ones that would be performed in a serial manner.</p>
  
  <p>Now, my bus width is 48 bytes. This means I can transfer 48 bytes on each memory transaction, right? So, in order to take full advantage of the bus, I would need to be able to read 48 bytes at a time (by reading more than one byte per thread - memory transactions are executed by a warp). However, hypothetically, wouldn't having a single thread reading 48 bytes at a time provide the same advantage (I'm assuming that I can read 48 bytes at a time by reading a structure whose size is 48 bytes)?</p>
  
  <p>My problem with coalescing is the transposing that I have to do on the data. I have lots of data, so transposing it takes time that I would rather use for something else if I could.</p>
  
  <p>I'm on Compute Capability 2.0.</p>