title: An elegant way to handle multiple extensions in Makefile
body: <p>I have a small C++ language project consisting of several source an header files, and I use Makefile to build my project.</p>
  
  <p>Recently I added a .c file in my project that originally had only .cpp files. To build the whole project including the .c file, I revised my Makefile like:</p>
  
  <pre><code>SRC_DIR     := src
  INC_DIR     := include
  BUILD_DIR   := build
  
  C_EXT       := c
  CPP_EXT     := cpp
  SOURCES     := $(shell find $(SRC_DIR) -type f -name *.$(CPP_EXT))
                 $(shell find $(SRC_DIR) -type f -name *.$(C_EXT))       # Added!
  
  ...
  
  $(BUILD_DIR)/%.o: $(SRC_DIR)/%.$(CPP_EXT) $(INC_DIR)/%.h
      @mkdir -p $(BUILD_DIR)
                      $(CXX) $(CFLAGS) -I $(INC_DIR) -c -o $@ $&lt;
  
  $(BUILD_DIR)/%.o: $(SRC_DIR)/%.$(C_EXT) $(INC_DIR)/%.h                 # Added!
      @mkdir -p $(BUILD_DIR)                                             # Added!
                      $(CXX) $(CFLAGS) -I $(INC_DIR) -c -o $@ $&lt;         # Added!
  </code></pre>
  
  <p>But I think it's little ugly because there is duplication of commands. Is there any way to remove the duplication and improve this Makefile commands?</p>