title: getting the target name in a function in prerequisites list [makefile]
body: <p>I'm trying to create a makefile where the target is used to search for dependencies in .d</p>
  
  <p>Thanks to the answers <a href="https://stackoverflow.com/questions/9488256/use-directory-path-of-target-in-list-of-prerequisites-in-makefile">here</a> and <a href="https://stackoverflow.com/questions/9705974/referring-to-the-target-name-from-the-list-of-the-prerequisites">here</a> I have discovered that <code>.SECONDEXPANSION:</code> does the job. However I'm running into an issue nesting functions which is seemingly bizarre. The offending rule looks like this:</p>
  
  <pre><code>.SECONDEXPANSION:
  $(APPS): %: $$(patsubst %.c,%.o,$$(wildcard $$@.d/*.c)) $$(INC_OBJS)
          $(CC) $(CFLAGS) $^ -o $@
  </code></pre>
  
  <p>instead of:</p>
  
  <p><code>gcc -Wall -std=c99 unittest.d/unittest.o common/cards.o -o unittest</code></p>
  
  <p>which is what I want, I get:</p>
  
  <p><code>gcc -Wall -std=c99 unittest.d/unittest.c common/cards.o -o unittest</code></p>
  
  <p>which for some reason doesn't have the <code>.o</code> substituted for the <code>.c</code>. So it appears I'm almost there, I just need to get the substitution working. All help appreciated and if you think this is a poor way to organize a makefile, critizism on that front welcome.</p>