title: Floating Point Division in System Verilog
body: <p>I wanted to use floating point numbers in System Verilog using the <code>real</code> data type. I tried the following code, but it doesn't seem to work. I'm getting <code>2.000000</code> where I expect <code>2.500000</code>.</p>
  
  <p>Module:</p>
  
  <pre><code>module real_check(input [31:0]a, [31:0]b,
                    output real c);
      assign c = a/b;
  endmodule
  </code></pre>
  
  <p>Test bench:</p>
  
  <pre><code>module tb_real_check();
  
  real c;
  reg[31:0] a, b;
  real_check dut(a, b, c);
  
  initial 
  begin
  
    a &lt;= 5;
    b &lt;= 2;
    #50;
    $display("Answer : %f ", c);
  
  end
  endmodule
  </code></pre>