title: implementing a processor ( mips single cycle )
body: <p>i have a mini project , in this project i need to implement a MIPS single cycle processor by Verilog.
  here I write the ALU and ALUControl and FileRegister but i have a problem to implement the Pc ( program counter ) for this ... i want this Pc support branch and jump.
  I need instructions for supporting branch but i don't know how can access to instruction.
  please help me to implement InstructionMemory and Pc.
  here is my code :</p>
  
  <pre><code>module ALU(ALUctl, A, B, ALUOut, Zero);
  input [3:0] ALUctl;
  input [31:0] A,B;
  output reg [31:0] ALUOut;
  output Zero;
  assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0
  always @(ALUctl, A, B) begin //reevaluate if these change
      case (ALUctl)
          0: ALUOut &lt;= A &amp; B;
          1: ALUOut &lt;= A | B;
          2: ALUOut &lt;= A + B;
          6: ALUOut &lt;= A - B;
          7: ALUOut &lt;= A &lt; B ? 1 : 0;
          12: ALUOut &lt;= ~(A | B); // result is nor
          default: ALUOut &lt;= 0;
      endcase
  end
  </code></pre>
  
  <p>endmodule</p>
  
  <pre><code>module ALUControl(ALUOp, FuncCode, ALUCtl);
  input [1:0] ALUOp;
  input [5:0] FuncCode;
  output reg [3:0] ALUCtl;
  always @(ALUOp, FuncCode) begin
      if ( ALUOp == 2 )
          case (FuncCode)
              32: ALUCtl&lt;=2; // add
              34: ALUCtl&lt;=6; //subtract
              36: ALUCtl&lt;=0; // and
              37: ALUCtl&lt;=1; // or
              39: ALUCtl&lt;=12; // nor
              42: ALUCtl&lt;=7; // slt
              default: ALUCtl&lt;=15; // should not happen
          endcase
      else
          case (ALUOp)
              0:  ALUCtl&lt;=2;
              1: ALUCtl&lt;=6;
              default: ALUCtl&lt;=15; // should not happen
          endcase
  end
  </code></pre>
  
  <p>endmodule</p>
  
  <pre><code>module RegFile(ra1, rd1 , ra2 , rd2 , clk , RegWrite , wa ,wd );
  input[4:0] ra1;
  output[31:0] rd1;
  input[4:0] ra2;
  output[31:0] rd2;
  input clk;
  input werf ;
  input[4:0] wa;
  input[31:0] wd;
  reg [31:0] registers[31:0];
  
  assign rd1 = registers[ra1];
  assign rd2 = registers[ra2];
  
  always@ ( posedge clk )
      if (RegWrite)
          registers[wa] &lt;= wd;
  </code></pre>
  
  <p>endmodule</p>