title: task in verilog
body: <p>I am trying to write a task that gives a variable paddr diffrent values:</p>
  
  <pre><code>module paddr1 ;
  task paddr1;
  input [10:0]paddr;
  input clock;
  
   @(posedge clock)
  begin
  paddr=10
  #100; 
  paddr=20; 
  #100; 
  paddr=30; 
  #100;  
  paddr=40;
  #100;   
  paddr=50;
  #100;   
  paddr=60;
  #100;  
  paddr=70;
  #100; 
  paddr=80;
  #100;
  
  end
  endtask
  endmodule
  </code></pre>
  
  <p>I tried to call this task from test bench and wrote:
  paddr1 (paddr,clock);</p>
  
  <p>It passes compilation
  But when I'm trying to run simulation I get an eror massage:
  Unresolved reference to 'paddr1'.
  Thank you for your answer
  the task is in a diffrent file then the test bench</p>
  
  <p>Thank you
  Yaniv</p>