title: Is it possible to configure the same tdata width on the masters and slaves interfaces on the axi4-stream switch IP of xilinx?
body: <p>I have to connect an AXI-stream switch IP into my FPGA VIVADO design, the switch have two slaves and one master. The data width inbound is 32 bits and I need data width outbound to be as well, but no matter how I configure the IP, it seems that the data width outbound will be always equal to the half of the data width inbound (in case I would have 3 masters and 1 slave the bit ratio would be 1/3...).
  Anyone have any idea if it's possible to configure the IP as I need?</p>
  <p><a href="https://i.stack.imgur.com/sY4GK.png" rel="nofollow noreferrer">axi4-stream switch actual configuration</a></p>