title: Logisim gives strange error with J-K flip-flop
body: <p>I have a simple circuit based on 3 J-K flip-flops, all connected to a common clock and configured identically. One of them has both J and K inputs connected to the output of the same OR gate. Logisim doesn't like this: it turns the inputs and the clock wires red, and I can't understand why.</p>
  
  <p>If I disconnect just the J input, everything goes green. If I disconnect just the K input, everything stays red. 
  What's going on here? I can't find anything suggesting that J and K inputs can't be tied together. </p>