title: How to add std_logic to an integer value
body: <p>I am trying to run two 7 segments here, I have searched everywhere but could not find a satisfactory reply, how can I add 1 to a std_logic ? I tried the logic_arith library as well but nothing works. I read somewhere that i gotta use a (0 to 0) vector but umm i didn't really get that part. Here is my code</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL;
  use ieee.std_logic_arith.all;
  
  entity blah is
  Port ( clk : in  STD_LOGIC;
          anode: out STD_LOGIC_VECTOR (3 downto 0);
          segment: out STD_LOGIC_VECTOR (6 downto 0));
  end blah;
  
  architecture Behavioral of blah is
  signal sel: STD_LOGIC;
  signal r_anode: STD_LOGIC_VECTOR (3 downto 0);
  begin
  anode &lt;= r_anode;
      process (clk) begin
          if (clk'event and clk = '1') then 
              sel &lt;= sel+1;
          end if;
          end process;
  
      process (sel) begin
          case sel is 
                  when '0' =&gt; r_anode &lt;= "1110";
                  when '1' =&gt; r_anode &lt;= "1101";
                  when others =&gt; r_anode &lt;= "1111";
                  end case;
              case r_anode is
                  when "1110" =&gt;  segment &lt;= "0100100";
                  when "1101" =&gt;  segment &lt;= "0010010";
                  when others =&gt; segment &lt;= "1111111";
              end case;
      end process;
      end;
  </code></pre>
  
  <p>And the error</p>
  
  <pre><code> ERROR:HDLParsers:808 - "E:/Xilinx Projects/blah/blah.vhd" Line 19. + can not have such operands in this context.
  </code></pre>