title: Not seeing a clock cycle delay in Vivado simulation during a register/flipflop assignment
body: <p>I am trying to generate a pulse from a signal <code>ext_sample_clk</code>. My design currently has 2 clock signals, <code>clk</code> and <code>ext_sample_clk</code>, which I am generating through a testbench. The following is my simplified code. Besides this, I also have the <code>clk</code> and reset generation logic, which I have not shown for simplicity. I can share those if needed.</p>
  <pre><code>module tb;
  reg clk;
  reg rst;
  reg ext_sample_clk;
  reg ext_sample_clk_r1;
  wire ext_sample_pulse_orig;
  
  //clock gen logic
  always 
  begin
      clk = 1'b1; 
      #5; // 10 ns
  
      clk = 1'b0;
      #5;
  end
  
  // reset gen logic
  initial 
  begin 
      rst = 1;
      #(100);
      rst = 0;
  end
  
  // ext_sample_clk logic
  always 
  begin
      ext_sample_clk = 1'b1; 
      #50; 
      ext_sample_clk = 1'b0;
      #50; 
  end
  
  // register the ext_sample_clk logic, should infer a flip flop
  always @(posedge clk) begin
      if (rst)
          ext_sample_clk_r1       &lt;= 0;
      else
          ext_sample_clk_r1       &lt;= ext_sample_clk; // lhs doesn't appear to be delayed by 1 clock cycle wrt to rhs
  end     
  assign ext_sample_pulse_orig   = ext_sample_clk        &amp;&amp; !ext_sample_clk_r1; 
  
  endmodule
  </code></pre>
  <p>I am expecting to see ext_sample_clk_r1 delayed by one clock pulse compared to ext_sample_clk. But the following is what I observe when I run a simulation on Vivado.
  <a href="https://i.stack.imgur.com/ZKEYm.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/ZKEYm.png" alt="enter image description here" /></a></p>
  <p>Can anyone explain why I am not seeing a clock cycle delay in ext_sample_clk_r1 with reference to ext_sample_clk. Am I missing something ?</p>