title: what does "virtual" mean when applied to a SystemVerilog interface?
body: <p>What is the meaning of "virtual tinyalu_bfm" in the SystemVerilog code below?  example:</p>
  
  <pre><code>        uvm_config_db #(virtual tinyalu_bfm)::set(null, "*", "bfm", bfm);
  </code></pre>
  
  <p>would it make any difference if i omitted the virtual keyword?  Just curious, because the usually oop meaning of virtual is applied only to classes or class members and here's an example where its applied to an interface being passed into a static function that's part of UVM package... just wanted to know why I need to call it virutal in this case and what its purpose is to make it virtual.</p>
  
  <pre><code>    module top;
  
          // UVM Framework
          import uvm_pkg::*;
          `include "uvm_macros.svh"
  
          import   tinyalu_pkg::*;       //import all tb classes and types
  
          tinyalu_bfm       bfm();
  
          // invoke APIs from uvm_pkg to start test...
          initial begin
              uvm_config_db #(virtual tinyalu_bfm)::set(null, "*", "bfm", bfm);
  
              run_test();  
          end
  
      endmodule : top
  </code></pre>
  
  <pre><code>    interface tinyalu_bfm;
  
         byte         unsigned        A;
         byte         unsigned        B;
         bit          clk;
         bit          reset_n;
  
         initial begin
            clk = 0;
            forever begin
               #10;
               clk = ~clk;
            end
         end
  
         task reset_alu();
            reset_n = 1'b0;
            @(negedge clk);
            @(negedge clk);
            reset_n = 1'b1;
            start = 1'b0;
         endtask : reset_alu
  
        task send_op(input byte iA, input byte iB, input operation_t iop, output shortint alu_result);
             // ...       
         endtask : send_op
  
      endinterface : tinyalu_bfm
  </code></pre>
  
  <p>see here again... the interface object is declared virtual as well...why?</p>
  
  <pre><code> // FILE: random_test.svh
      class random_test extends uvm_test;
          // ... 
          virtual tinyalu_bfm bfm;
  
          function new (string name, uvm_component parent);
              super.new(name,parent);
              if(!uvm_config_db #(virtual tinyalu_bfm)::get(null, "*","bfm", bfm))
                  $fatal("Failed to get BFM");
          endfunction : new
  
          task run_phase(uvm_phase phase);
              //...
          endtask : run_phase
  
      endclass
  
  </code></pre>