title: VHDL type conversion - found 4 possible definitions
body: <p>I am trying convert two std_logic bits to an integer as follows</p>
  
  <pre><code>LIBRARY IEEE;
  USE IEEE.std_logic_1164.ALL;
  USE IEEE.numeric_std.ALL;
  
  ENTITY TEST IS
      PORT (sw1, sw0  :   IN      std_logic;
            x         :   OUT     integer RANGE 3 DOWNTO 0);
  END ENTITY TEST;
  
  ARCHITECTURE dflow OF TEST IS
      SIGNAL mes_sel : integer RANGE 3 DOWNTO 0;
  BEGIN
      mes_sel &lt;= to_integer(unsigned(std_logic_vector(SW1 &amp; SW0)));
      x &lt;= mes_sel;
  END ARCHITECTURE dflow;
  </code></pre>
  
  <p>but the compiler does not like the mes_sel assignment. I get the following compiler error message:</p>
  
  <blockquote>
    <p>Error (10327): VHDL error at Q4.vhd(92): can't determine definition of operator ""&amp;"" -- found 4 possible definitions</p>
  </blockquote>
  
  <p>Can I not concatenate 2 bit of std_logic to a vector and then convert? Or is it something else?
  regards
  D</p>