title: Query for VHDL synthesis for IC Design (Not FPGA), specifically in case of variable assignment
body: <p>If for a given process, I declare a variable (let's say a 1 bit variable, <code>variable temp : std_logic;</code>) then can I assign a value to the variable if a given condition returns true, i.e. </p>
  
  <pre><code>if (xyz=1) then --Assuming that this condition returns TRUE
  temp:= '1';
  </code></pre>
  
  <p>?? Will this logic be synthesizable for ASICs?</p>