title: Verilog: Loop count limit exceeded. Condition is never false
body: <p><a href="https://i.stack.imgur.com/vgMD4.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/vgMD4.png" alt="enter image description here"></a></p>
  
  <p>Can anyone here help me to remove this error of loop limit exceed? The Databits is defined in another module in "constant.v". The length of Databits is 64. I have uploaded a picture for reference <a href="https://i.stack.imgur.com/vgMD4.png" rel="nofollow noreferrer">1</a>. It has the pLayer "permutation layer" used in cipher under Shannon confusion and diffusion theory. </p>
  
  <p>Basically, I need to change the Position of each bit of input state of cipher, that consists of 64 bits. So if the bit '0' or '1' is in 1st position the output position should be 16, 2nd bit should be reposition to 32nd position, and likewise. The code is also in the same link.</p>