title: generate statement : verilog
body: <p>I need to declare a register inside a generate statement to store some temporary values, </p>
  
  <p>to be used in instantiations.</p>
  
  <p>i have </p>
  
  <pre><code>generate
  
  for(i=0; i&lt; N; i=i+1)
  begin: i_loop
      Inst_file u(S1(i),P1(i),S(i),P(i)); 
      /* S1 and P1 have N bits and 
         S = S1 ^ P1; 
         P = S1 &amp; P1 
       */
  end //i_loop
  </code></pre>
  
  <p>S1 and P1 are simple combinationl logic and i have used them as wires for the first </p>
  
  <p>iteration. But after each iteration of i, I need to assign the outputs S and P as inputs </p>
  
  <p>(i.e replace S1 and P1 with S and P).</p>
  
  <p>I understand I should do it with a register and not a wire (Am i right?)</p>
  
  <p>In such a case i need S1 and P1 as reg. I tried using always statement inside the </p>
  
  <p>generate. It gives error. </p>
  
  <p>Can u please suggest a way out..</p>