title: srand() analog for SystemVerilog
body: <p>C <code>rand()</code> and <code>srand()</code> functions is very useful when you doing something like that:</p>
  
  <pre><code>srand(SEED);
  for()
  {
      //doing something with one thing using rand()
  }
  srand(SEED);
  for()
  {
      //doing something with other thing using rand()
  }
  </code></pre>
  
  <p>Can I have something like this in SystemVerilog? Yeah, I know about <code>$urandom(SEED)</code>, but the thing is it should SRAND once and rand() then many times</p>