title: VHDL or verilog SR latch
body: <p>I'm trying to program my <strong>NEXYS2</strong> board with a <strong>SR latch</strong> with NAND gates with an enable signal C. My <strong>inputs</strong> are <strong>(S, R, C)</strong> and <strong>outputs</strong> are <strong>(Q, Qbar)</strong>. below is some code in VHDL that I tried but keep getting errors. also the schematics are below if that helps anyone to understand my question. if you know it in verilog that's okay too. 
  Thank you in advance</p>
  
  <pre><code>process(S,R,C,Q,Qbar)
  begin
      if (C = '1') then
          Q &lt;= (R nand Qbar);
          Qbar &lt;= (S nand Q);
      end if;
  end process;
  </code></pre>
  
  <p><img src="https://i.stack.imgur.com/1y4jO.gif" alt="Schematic"></p>