title: Function with don't-care inputs
body: <p>How can I implement a VHDL function which has "don't care" inputs and have the "don't cares" be directly represented?</p>
  
  <p>Exercise 4.8-2a of <a href="http://www.freerangefactory.org/site/pmwiki.php/Main/DownloadBooks" rel="nofollow">Free Range VHDL</a> asks me to:</p>
  
  <blockquote>
    <p>...write VHDL models that implement these functions using...selected signal assignment.</p>
    
    <p>a) F (A, B, C, D) = A'CD' + B'C + BCD'</p>
  </blockquote>
  
  <p>This code works:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity funca_selected is
    port (
      a: in std_ulogic;
      b: in std_ulogic;
      c: in std_ulogic;
      d: in std_ulogic;
      x: out std_ulogic);
  end entity;
  
  architecture rtl of funca_selected is
    signal s: std_ulogic_vector(3 downto 0);
  begin
    s &lt;= a &amp; b &amp; c &amp; d;
    with s select x &lt;=
      '1' when "0010" | "0110" | "0011" | "1010" | "1011" | "1110",
      '0' when others;
  end architecture;
  </code></pre>
  
  <p>It is, however, a poor representation of the function definition.  I want to code it using "don't care" inputs so that the code more closely matches the definition.  This would be less work, and easier to get right.  I tried this:</p>
  
  <pre><code>  with s select x &lt;=
      '1' when "0-10" | "-01-" | "-110",
      '0' when others;
  </code></pre>
  
  <p>This does not work: When my test bed exercises this function, the result is always '0'.</p>
  
  <p>I am using GHDL version 0.29+gcc4.3.i386.</p>
  
  <p>How can a VHDL function represent "don't care" inputs?</p>