title: Is the For loop a software for loop instead of the hardware for loop in verilog in the intial block
body: <p>The for loop outside the intial block generates hardware (with genvar), but the for loop in intial block in verilog works like the software for loop right?</p>
  <p>The intial block is ofcourse only for simulation purposes so the software for loop makes sense.</p>
  <p>One example is <a href="http://electrosofts.com/verilog/fsm.html" rel="nofollow noreferrer">here</a>. The test bench from that example that displays the use of the for loops in discussion is shown below:</p>
  <pre><code>module fsm_test;
  
  reg  clk, rst, inp;
  wire outp;
  reg[15:0] sequence;
  integer i;
  
  fsm dut( clk, rst, inp, outp);
  
  initial
  begin
  
     clk = 0;
          rst = 1;
          sequence = 16'b0101_0111_0111_0010;
     #5 rst = 0;
  
     for( i = 0; i &lt;= 15; i = i + 1)
     begin
        inp = sequence[i];
        #2 clk = 1;
        #2 clk = 0;
        $display(&quot;State = &quot;, dut.state, &quot; Input = &quot;, inp, &quot;, Output = &quot;, outp);
  
     end
          test2;
  end
  task test2;
     for( i = 0; i &lt;= 15; i = i + 1)
     begin
        inp = $random % 2;
        #2 clk = 1;
        #2 clk = 0;
        $display(&quot;State = &quot;, dut.state, &quot; Input = &quot;, inp, &quot;, Output = &quot;, outp);
  
     end
  endtask
  
  
  endmodule
  </code></pre>