title: Implementing simple dual port block ram in VHDL not performing as expected
body: <p>I have been trying to implement a simple dual port block RAM in VHDL but it does not yield the expected results in simulation. Here is the code:</p>
  
  <pre><code>library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;
  
  entity rams is
  generic ( g_adress_width: integer:= 18;
            g_ram_size: integer:= 1000
          );
   port(
      clka : in std_logic;
      clkb : in std_logic;
      wea : in std_logic;
      web : in std_logic;
      addra : in std_logic_vector(g_adress_width-1 downto 0);
      addrb : in std_logic_vector(g_adress_width-1 downto 0);
      dia : in std_logic_vector(15 downto 0);
      dib : in std_logic_vector(15 downto 0);
      doa : out std_logic_vector(15 downto 0);
      dob : out std_logic_vector(15 downto 0));
  end rams;
  architecture syn of rams is
      type ram_type is array (g_ram_size-1 downto 0) of std_logic_vector(15 downto 0);
       signal RAM : ram_type; 
  begin
   process (CLKA)
   begin
      if CLKA'event and CLKA = '1' then
              DOA &lt;= RAM(conv_integer(ADDRA));
              if WEA = '1' then --always 0
                  RAM(conv_integer(ADDRA)) &lt;= DIA; --does not execute
          end if;
      end if;
   end process;
  
   process (CLKB)
   begin
   if CLKB'event and CLKB = '1' then
          DOB &lt;= RAM(conv_integer(ADDRB));
          if WEB = '1' then
              RAM(conv_integer(ADDRB)) &lt;= DIB;
      end if;
   end if;
  
  end process;
  end syn; 
  </code></pre>
  
  <p>And here is the simulation:</p>
  
  <p><a href="https://i.stack.imgur.com/5ckhR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/5ckhR.png" alt="Simulation"></a></p>
  
  <p>Both <strong>clka</strong> and <strong>clkb</strong> are connected to the same clock. I give some arbitrary values (unsigned 300 and 355) to <strong>dib</strong>. </p>
  
  <p>Basically, <strong>doa</strong> is always reading so I expect it to be undefined until something has been written to those block ram addresses with <strong>dib</strong>, but it is showing undefined values always.</p>
  
  <p>What I expect to happen is for <strong>doa</strong> to read 300 when <strong>addra</strong> is at 0 again and to read 355 when <strong>addra</strong> is at 15. Something like this (pardon my paint skills):</p>
  
  <p><a href="https://i.stack.imgur.com/5LnRk.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/5LnRk.png" alt="enter image description here"></a> </p>
  
  <p>Would appreciate it if someone could point me in the right direction of what I am doing wrong. Thanks.</p>
  
  <p><strong>EDIT: Code is modified to this and it works now (thanks to Paebbels solution):</strong> </p>
  
  <pre><code>     signal RAM : ram_type; 
  begin
   process (CLKA)
   begin
      if CLKA'event and CLKA = '1' then
              DOA &lt;= RAM(to_integer(unsigned(ADDRA)));
              if WEA = '1' then --always 0
                      RAM(to_integer(unsigned(ADDRA))) &lt;= DIA; --does not happen
          end if;
  
      end if;
  
      if CLKA'event and CLKA = '1' then
          DOB &lt;= RAM(to_integer(unsigned(ADDRB)));
          if WEB = '1' then
              RAM(to_integer(unsigned(ADDRB))) &lt;= DIB;
      end if;
   end if;
  
   end process;
  end syn; 
  </code></pre>