title: VHDL Adder Test Bench
body: <p>I'm new to VHDL and I'm making a 4bit adder using 4 Full Adders. I created a test bench to see if the adder is working and in the ans I'm getting values of UUUU. From what I read is that the process is not being executed. I have no idea how to fix this, any help would be appreciated. </p>
  
  <p>Here is the TestBench</p>
  
  <pre><code>ENTITY Adder4_Test IS
  END Adder4_Test;
  
  ARCHITECTURE behavior OF Adder4_Test IS 
  
  -- Component Declaration for the Unit Under Test (UUT)
  
  COMPONENT Adder4
  PORT(
       X : IN  STD_LOGIC_vector(3 downto 0);
       Y : IN  STD_LOGIC_vector(3 downto 0);
       Ans : OUT STD_LOGIC_VECTOR(3 downto 0);
       Cout : OUT STD_LOGIC
      );
  END COMPONENT;
  
  
  --Inputs
  signal X : STD_LOGIC_vector(3 downto 0) := (others =&gt; '0');
  signal Y : STD_LOGIC_vector(3 downto 0) := (others =&gt; '0');
  
  
  --Outputs
  signal Ans : STD_LOGIC_vector(3 downto 0);
  signal Cout : STD_LOGIC;
  -- No clocks detected in port list. Replace &lt;clock&gt; below with 
  -- appropriate port name 
  
  --constant &lt;clock&gt;_period : time := 10 ns;
  
  BEGIN
  
  -- Instantiate the Unit Under Test (UUT)
  uut: Adder4 PORT MAP (
        X,
        Y, 
        Ans,
        Cout
      );
  
  -- Clock process definitions
  --&lt;clock&gt;_process :process
  --begin
      --&lt;clock&gt; &lt;= '0';
      --wait for &lt;clock&gt;_period/2;
      --&lt;clock&gt; &lt;= '1';
      --wait for &lt;clock&gt;_period/2;
  --end process;
  
  
  -- Stimulus process
  stim_proc: process
  begin       
    -- hold reset state for 100 ns.
    --wait for 100 ns;    
  
    --wait for &lt;clock&gt;_period*10;
  
    -- insert stimulus here 
  
      -- Case 1 that we are testing.
          X &lt;= "0000";
          Y &lt;= "0000";
          wait for 10 ns;
          assert ( Ans = "0000" )report "Failed Case 1 - Ans" severity error;
          assert ( Cout = '0' )   report "Failed Case 1 - Cout" severity error;
          wait for 40 ns;
  
      -- Case 2 that we are testing.
  
          X &lt;= "1111";
          Y &lt;= "1111";
          wait for 10 ns;
          assert ( Ans = "1110" )report "Failed Case 2 - Ans" severity error;
          assert ( Cout = '1' )   report "Failed Case 2 - Cout" severity error;
          wait for 40 ns;
  
  
  
    wait;
   end process;
  
   END;
  </code></pre>
  
  <p>Here is the Adder4</p>
  
  <pre><code>entity Adder4 is
  Port ( X : in  STD_LOGIC_vector (3 DOWNTO 0);
         Y : in  STD_LOGIC_vector (3 DOWNTO 0);
         Ans: out  STD_LOGIC_vector (3 DOWNTO 0);
            Cout: out STD_LOGIC);
  end Adder4;
  
  architecture Structure of Adder4 is
  
  component FullAdder is
  Port ( X : in STD_LOGIC;
         Y : in STD_LOGIC;
         Cin : in STD_LOGIC;
            Sum : out STD_LOGIC;
            Cout : out STD_LOGIC);
  end  component;
  
  signal c0, c1, c2, c3: STD_LOGIC;
  
    begin
  c0 &lt;='0';
  b_adder0: FullAdder port map (X(0), Y(0), c0, Ans(0), c1);
  b_adder1: FullAdder port map (X(1), Y(1), c1, Ans(1), c2);
  b_adder2: FullAdder port map (X(2), Y(2), c2, Ans(2), c3);
  b_adder3: FullAdder port map (X(3), Y(3), c3, Ans(3), Cout);
  
  
   end Structure;
  </code></pre>
  
  <p>Here is the FullAdder</p>
  
  <pre><code>entity FullAdder is
  Port ( X : in  STD_LOGIC;
         Y : in  STD_LOGIC;
         Cin : in  STD_LOGIC;
         Sum : out  STD_LOGIC;
         Cout : out  STD_LOGIC);
  end FullAdder;
  
   architecture Behavioral of FullAdder is
  
  component Xor_Model is
  Port ( A : in  STD_LOGIC;
         B : in  STD_LOGIC;
         C : in  STD_LOGIC;
         Z : out  STD_LOGIC);
  end  component;
  
  
  
    begin
  
  Cout &lt;= ((X and Y) or (Y and Cin) or (X and Cin));
  Sum &lt;= (X AND (NOT Y) AND (NOT Cin)) OR ((NOT X) AND Y AND (NOT Cin)) OR
  ((NOT X) AND (NOT Y) AND Cin) OR (X AND Y AND Cin) after 5ns;
  xorLabel: Xor_Model
      Port Map ( A =&gt; X, B =&gt; Y, C =&gt; Cin, Z =&gt; Sum);
  
  
   end Behavioral;
  </code></pre>