title: Testing multiple configurations of parameterizable modules in a Verilog testbench
body: <p>Say I have a Verilog module that's parameterizable like the below example:</p>
  <pre><code>// Crunches numbers using lots of parallel cores
  module number_cruncher
      #(parameter NUMBER_OF_PARALLEL_CORES = 4)
      (input clock, ..., input [31:0] data, ... etc);
      // Math happens here
  endmodule
  </code></pre>
  <p>Using Verilog 1364-2005, I want to write a testbench that runs tests on this module with many different values <code>NUMBER_OF_PARALLEL_CORES</code>.</p>
  <p>One option that I know will work is to use a <code>generate</code> block to create a bunch of different <code>number_cruncher</code>s with different values for <code>NUMBER_OF_PARALLEL_CORES</code>. This isn't very flexible, though - the values need to be chosen at compile time.</p>
  <p>Of course, I could also explicitly instantiate a lot of different modules, but that is time consuming and won't work for the sort of &quot;fuzz&quot; testing I want to do.</p>
  <p>My questions:</p>
  <ul>
  <li>Is there a way to do this by using a plusarg passed in from the command line using <code>$value$plusargs</code>? (I strongly suspect the answer is 'no' for Verilog 1364-2005).</li>
  <li>Is there another way to &quot;fuzz&quot; module parameterizations in a testbench, or is using a generate block the only way?</li>
  </ul>