title: Memory write in NIOS II - value put in wrong address
body: <p>First of all, I should admit I have submitted this question on the altera forum (<a href="http://www.alteraforum.com/forum/showthread.php?t=40494" rel="nofollow">http://www.alteraforum.com/forum/showthread.php?t=40494</a>). I am asking here too because I think it is likely to be quite a different audience. If this duplicate post is against any stack overflow rules or etiquette please let me know and I'll remove it. If not i'll update the forum submission with any answers I receive here and vice versa. </p>
  
  <p>I'm trying to integrate an I2C core from opencores to my Cyclone IV device. Apparently the version I'm using should just drop into the SOPC and work after being wired to some outputs (<a href="http://alterawiki.com/wiki/I2C_%28OpenCores%29" rel="nofollow">alterawiki.com/wiki/I2C_(OpenCores)</a>). The core compiles with no errors or warnings. </p>
  
  <p>The I2C docs with the core show 6 relevant registers addressed one after another (PRERlo, PRERhi, CTR, TXR, RXR, CR, SR). However, when I attempt to write to these registers the write is put into the wrong address whether from my code or manually in debug memory window. </p>
  
  <p>To investigate this I set the registers to initial values in VHDL to see the result in the debug window. This showed that the register addresses for TXR and CR are not what is suggested in the docs. </p>
  
  <pre><code>Address   0  1  2  3 
  09866160 AA 00 00 00 -- PRERlo
  09866164 00 00 00 00 -- PRERhi
  09866168 BB 00 00 00 -- CTR
  0986616C DD 00 00 00 -- RXR
  09866170 FA 00 00 00 -- SR
  09866174 CC 00 00 00 -- TX
  09866174 EE 00 00 00 -- CR
  </code></pre>
  
  <p>This would be fine, however, when I attempt to write to address 09866174 (TXR) the value is inserted at 09866164 (PRERhi). Similarly when I write to 09866178 (CR) the value is inserted into 09866168(CTR). This happens whether the write comes from the code or manually from the debug window. This is particularly confusing as writing to these registers works fine in VHDL.</p>
  
  <pre><code>#define IOWR(base,offset,value) __builtin_stwio ((unsigned int*)BASE + OFFSET, (DATA));
  IOWR(I2C_MASTER_BASE, 5, 0x1D); 
  </code></pre>
  
  <p>I have attempted to debug this from signal tap also. However, triggers on any of the registers are never implemented.</p>
  
  <p>I'd really appreciate if anyone can point me in the right direction here. </p>
  
  <p>Thanks! </p>
  
  <p>-update: I have been using the VHDL version of the core. However, I decided to throw in the towel for now and use the Verilog version which worked almost straight away when I wired it up. I intend to get back to the VHDL core when my application is done and will update this again then.</p>