title: Illegal sequential statement. error using std_logic_vector
body: <p>i have a project in VHDL and its my first time using it. i need to create an adder/substractor constructed from full adders and it need to have the ability to add between 8 to 32 bits number. i defined a generic but when trying to run the code i get  Illegal sequential statement. the code is this:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all; 
  entity Add_Sub is
    generic (N : integer := 8); 
    port(addsub_line: in std_logic;
          A: in std_logic_vector(N-1 downto 0);
          B: in std_logic_vector(N-1 downto 0);
          SumOut: out std_logic_vector(N-1 downto 0);
          Cout: out std_logic);
  end Add_Sub;
  
  architecture struct of Add_Sub is
    component FA_Ent is
        port(a: in std_logic;
         b: in std_logic;
         carry_in: in std_logic;
         sum: out std_logic;
         carry_out: out std_logic);
    end component;
    component XOR_GATE is
      port(A: in std_logic;
           B: in std_logic;
           F: out std_logic);
    end component;
  
    signal BxorAddSub: std_logic_vector(N-1 downto 0);
    begin 
      process 
        begin
        for i in 0 to N-1 loop
          BxorAddSubLine: XOR_GATE port map(B(0), addsub_line, BxorAddSub(0));
        end loop;
      end process;
    end struct;
  </code></pre>
  
  <p>i guess somewhere im using the loop wrong. im trying to do the xor for all the bits i have and i dont know how many how i got so i must use the loop anyone know why i get the error or how i should do what im trying to achive?
  thank you</p>