title: SystemVerilog foreach syntax for looping through lower dimension of multidimensional array
body: <p>What is the <strong>standard</strong> way of looping through the lower dimension of a multidimensional array? With the higher dimension fixed.</p>
  
  <p>In the following example:</p>
  
  <pre><code>  automatic int i = 2;
    foreach (my_req[i][j]) begin // &lt;-- WARNING
      $display("i:%0d,j:%0d", i, j);
    end
  </code></pre>
  
  <p>I see the warning:</p>
  
  <pre><code>** Warning: testbench.sv(16): (vlog-LRM-2897) Using non-standard foreach loop variable list syntax.
  </code></pre>
  
  <p>Full code example on EDA Playground: <a href="http://www.edaplayground.com/x/nh" rel="noreferrer">http://www.edaplayground.com/x/nh</a></p>