title: System Verilog typedef of typedef
body: <p><code>typedef enum</code>s allow a convenient way to describe a set of name-value pairs. Is there a way to chain them to create deeper structures using enum at all levels?</p>
  
  <p>For instance, I have the following:</p>
  
  <pre><code>typedef enum logic {ALPHA=0, BETA=1} a_t;
  typedef enum logic {GAMMA=0, DELTA=1} b_t;
  typedef enum logic {ZETA=0, ETA=1} c_t;
  ...
  </code></pre>
  
  <p>I want to create a variable <code>c</code> which is formed of <code>a_t</code> and <code>b_t</code>. Is this possible?</p>
  
  <p>Something like:</p>
  
  <pre><code>a_t b_t c;
  </code></pre>
  
  <p>so at every dimension of <code>c</code>, I can have <code>enum</code>s.</p>
  
  <p>EDIT: Some clarification - assume <code>a_t</code>, <code>b_t</code> and <code>c_t</code> are immutable as they are generated automatically. And there are hundreds of such different enums. I want to create bigger structures as I need because automatically generating all combinations of them would make the code too big and messy.</p>
  
  <p>For instance, say my <code>a_t</code> describes number of masters and <code>b_t</code> describes number of slaves. I want to create a structure where I have this hierarchy in my signal, and at the same time allow <code>enum</code>s for them to allow easy of readability and use.</p>
  
  <p>So, something like this:</p>
  
  <pre><code>c[MASTER_0][SLAVE_0]
  c[MASTER_0][SLAVE_1]
  c[MASTER_1][SLAVE_0]
  c[MASTER_1][SLAVE_1]
  </code></pre>