title: Verilog $finish does not stop simulation
body: <p>I've stumbled across a not so serious problem in Verilog + TCL. I wrote a TCL script that does <code>run -all</code>. In my module testbench, there is a call to a <code>$finish</code> at the end, but somehow when simulating, it does not stop and continues.</p>
  
  <p>The <code>$finish</code> is inside an <code>initial</code> block. Other than that, there is also an <code>always</code> block which is not sensitive to anything that is used to generate the clock.</p>
  
  <p>I'm not sure why it won't stop, but I suspect that the <code>always</code> block may have something to do with it.</p>
  
  <p>Any ideas?</p>