title: generating random numbers in verilog
body: <p>I ran into this issue while writing a test bench for a project. I found how to use <code>$random</code> in verilog but for some reason it produces strange results for me. I have 2 16 bit regs called <code>A</code> and <code>B</code>, I tested it with random number between 0-10 every second output is a value which is the max value that you can have in 16 bits. I wonder if anyone else had had similar issue and can offer help. 
  Thanks</p>
  
  <pre><code>reg[15:0]a;
  reg[15:0]b;
  
   integer seed,i,j;
   initial begin 
  
  
     for (i=0; i&lt;6; i=i+1)
      begin
        a=$random%10; 
        #100;
        b=$random%20;
      $display("A %d, B: %d",a,b);    
     end 
  $finish;
  </code></pre>