title: Verilog test bench code
body: <p>Can anyone help me in writing verilog test bench code for the following code !
  I have try but it's doesn't work !</p>
  
  <pre><code>module top(clock_in, Reset, Hold, up_down, Led_Out, f);     
    input clock_in, Reset, Hold, up_down;
    output      [6:0] Led_Out;        
    output wire [3:0] f;
  
    wire pulse;
  
    clock_design temp0(clock_in, pulse);
    up_down_counter temp1(pulse, Reset, Hold, up_down, f);
    led7 temp2(Led_Out, f);
  endmodule
  </code></pre>
  
  <p>led7 :</p>
  
  <pre><code>module led7(iOut, iQ);
    output reg [6:0] iOut;
    input      [3:0] iQ;
  
    always @(iQ)
      case (iQ)
        4'b0000: iOut = 7'b0000001; //0
        4'b0001: iOut = 7'b1001111; //1
        4'b0010: iOut = 7'b0010010; //2
        4'b0011: iOut = 7'b0000110; //3
        4'b0100: iOut = 7'b1001100; //4
        4'b0101: iOut = 7'b0100100; //5
        4'b0110: iOut = 7'b0100000; //6
        4'b0111: iOut = 7'b0001111; //7
        4'b1000: iOut = 7'b0000000; //8
        4'b1001: iOut = 7'b0000100; //9
        default: iOut = 7'b0000000; //default
      endcase  
    endmodule
  </code></pre>
  
  <p>up_down_counter :        </p>
  
  <pre><code> module up_down_counter (Clock,Reset,Hold,up_down,Q);
     input Clock,Reset,Hold,up_down;
     output reg [3:0] Q;
     integer direction;
  
  
      always @(posedge Clock)
      begin
        if(up_down)
          direction = 1;
        else
          direction = -1;
  
       if (!Reset &amp;&amp; direction == 1)
          Q &lt;= 0;
        else if(!Reset &amp;&amp; direction == -1)
          Q &lt;= 1001;
        else if (!Hold)           
          Q &lt;= Q + direction; 
  
        if (direction==1  &amp;&amp; Q[0]==1 &amp;&amp; Q[1]==0 &amp;&amp;Q[1]==0 &amp;&amp; Q[3]==1)
          Q &lt;= 0; 
        else if (direction==-1 &amp;&amp; Q[0]==0 &amp;&amp; Q[1]==0 &amp;&amp;Q[2]==0 &amp;&amp; Q[3]==0)
          Q &lt;= 1001;
        end
      endmodule
  </code></pre>
  
  <p>clock_design :</p>
  
  <pre><code>module clock_design (clock_in,clock_out);
    input clock_in;
    output clock_out;
    parameter which_clock=1;
    reg [31:0] divided_clocks=0;
  
    always @(posedge clock_in)
      divided_clocks = divided_clocks +1;
  
    assign clock_out = divided_clocks[which_clock];
  endmodule
  </code></pre>
  
  <p>My Test-bench code</p>
  
  <pre><code>module counter_tb;
    reg  [6:0] Led_Out_tb;
    wire [3:0] f_tb;
    reg  clock_in_tb, Reset_tb, Hold_tb, up_down_tb;
  
    top dut(clock_in_tb, Reset_tb,Hold_tb, up_down_tb, Led_Out_tb, f_tb);
  
    initial begin
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
      #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0;
    end
  endmodule
  </code></pre>