title: VHDL for loop in test bench to run truth table
body: <p>How would I do this in a VHDL test bench to run through a truth table for a multiplexer. Am I on the right track?</p>
  
  <pre><code>sel &lt;= "00" after 100 ns, "01" after 200 ns, "10" after 300 ns, "11" after 400;
  
  process (sel)
      variable p :STD_LOGIC_VECTOR(3 downto 0); 
  begin
      p := "0000"
      for j in "0001" to "1111" loop
          if j /= "1111" then p:= p + 1;
          wait for 5 ns; 
      end loop ;
  end process;
  
  x &lt;= p;
  </code></pre>