title: Counter based memory array in Verilog
body: <p>I got a problem. 
  I am a Verilog newbie, and I have to write a counter based memory array. Basically, my array is 16 x 8 bits (16 x 1 byte). I have 8 bit data coming into my memory, 16 times. So I made a memory block, and a counter which supplies addresses to this memory block by incrementing with the positive edge of the clock (actually, on each positive edge, 8 bit data is fed into the memory, so I increment my counter). Now I have done this process 16 times, and now 128 bits of data are stored and provided by my memory block. But now I want to reset my counter, and repeat the whole process again after a small delay. I am confused as to how I do this. Please have a look at my code and advise.</p>
  
  <p>Thanking all of you in advance.</p>
  
  <pre><code>// creation of counter &amp; a dummy variable
  wire cnt;
  wire cnt_next;
  reg [3:0] counter;
    always @(posedge clock)
      assign cnt_next=cnt+1'b1;   
          counter &lt;= cnt_next
          wire [3:0] write_address  = counter;
  
  
  //creation of ram function
  module single_port_ram
  (   
      input [7:0] data,
      input [3:0] addr,
      input wr, clk, rd
      output [127:0] q
  );
  
  reg [15:0] ram[0:7];
  
  always @ (posedge clk or posedge reset)
      begin
      // Code for writing the data
          if (wr)
          {
            addr &lt;= write_address 
            case {addr}
                  4'b0000: ram[0] &lt;= data
              4'b0001: ram[1] &lt;= data
              4'b0010: ram[2] &lt;= data
              4'b0011: ram[3] &lt;= data
              4'b0100: ram[4] &lt;= data
              4'b0101: ram[5] &lt;= data
              4'b0110: ram[6] &lt;= data
              4'b0111: ram[7] &lt;= data
              4'b1000: ram[8] &lt;= data
              4'b1001: ram[8] &lt;= data
              4'b1010: ram[10] &lt;= data
              4'b1011: ram[11] &lt;= data
              4'b1100: ram[12] &lt;= data
              4'b1101: ram[13] &lt;= data
              4'b1110: ram[14] &lt;= data
              4'b1111: ram[15] &lt;= data
           end
  
  always @ (posedge clk or posedge reset)
      begin
      //Code for reading the data
          if (rd)
          {
          q &lt;= {ram[15],ram[14],ram[13],ram[12],ram[11],ram[10],ram[9],ram[8],ram[7],ram[6],ram[5],ram[4],ram [3],ram[2],ram[1],ram[0]}   
          }
  </code></pre>