title: Is there a ifx-elsex statement in Verilog/SV like casex?
body: <p>Say I have a scenario in which I need to compare only a few bits of a register and I don't care about other bits. eq, I need to check the first and last bits of a 3 bit register (A[2:0]) and I don't care about the middle bit, say compare vector is 3'b1X0 (Parameter). </p>
  
  <ol>
  <li><p>Simplest way to do this is choose all the bits I care about, AND them and I have generated a control signal:
  <code>if ((A[2]==1) &amp; ((A[0]==0))</code> Here the condition inside <code>if</code> statement is my control signal.</p></li>
  <li><p>Another way is to use a casex statement: <code>casex(A) begin 3'b1?0: ... , ... endcase</code>.</p></li>
  <li><p>Is there anything like ifx-elsex statement or something that can be used to do this kind of operation without using the 1st and 2nd method?</p></li>
  </ol>
  
  <p>Thanks!</p>