title: Verilog: Order of reg
body: <p>Simple question</p>
  
  <p>If I need to use 4 8-bit numbers, I would declare the following reg.</p>
  
  <pre><code>reg [7:0] numbers [3:0]
  </code></pre>
  
  <p>I'm quite confused about the difference between the first and second declaration ([7:0] and [3:0]). In what order should they come? Does first one stay for the size of a number while the second is for the number of numbers or vice versa? And is [7:0] or [0:7] give the right order?</p>
  
  <p>Thanks in advance.</p>
  
  <p>EDIT:</p>
  
  <p>Ordinary arrays of numbers look like this, for example</p>
  
  <pre><code>0000
  0110
  0001
  </code></pre>
  
  <p>There are three 4-bit numbers (0000, 0110, 0001). We can access them by using array indices. So, accessing the first digit of the second number is done by something like this</p>
  
  <pre><code>a[0][1]
  </code></pre>
  
  <p>assuming that this array is stored in a variable a.</p>
  
  <p>Returning to Verilog, how would accessing elements change if I would swap values in reg or declare them in reverse order ([0:7]), for example?</p>