title: Xilinx FFT IP core simulation test bench in VHDL
body: <p>I'm trying to use an FFT IP core on a spartan-3A FPGA board and for simulation. I'm not getting the expected results!</p>
  
  <p>Here is my test bench which doesn't give me the output I want, it just returns 0s for output while the "dv" signal returns '1'!<br>
  P.S. first I'm trying to test a 16 ifft core to see if it works or not.</p>
  
  <pre><code>-- TestBench Template 
  
    LIBRARY ieee;    
    USE ieee.std_logic_1164.ALL;      
    USE ieee.numeric_std.ALL;      
    use std.textio.all;      
    -- use IEEE.std_logic_textio.all;     
    -- use IEEE.STD_LOGIC_ARITH.all;
  
  
    library STD;
    use STD.textio;
  
  
      ENTITY testfft16 IS
      END testfft16;
  
      ARCHITECTURE behavior OF testfft16 IS 
  
      -- Component Declaration    
        COMPONENT tt16       
        port(        
        clk    : in STD_LOGIC;      
        start  : in STD_LOGIC;         
        unload : in STD_LOGIC;       
        fwd_inv    : in STD_LOGIC;      
        fwd_inv_we : in STD_LOGIC;      
        rfd   : out STD_LOGIC;      
        busy  : out STD_LOGIC;      
        edone : out STD_LOGIC;      
        done  : out STD_LOGIC;       
        dv    : out STD_LOGIC;      
        xn_re : in STD_LOGIC_VECTOR ( 31 downto 0 );     
        xn_im : in STD_LOGIC_VECTOR ( 31 downto 0 );        
        xn_index : out STD_LOGIC_VECTOR ( 3 downto 0 );      
        xk_index : out STD_LOGIC_VECTOR ( 3 downto 0 );      
        xk_re : out STD_LOGIC_VECTOR ( 31 downto 0 );      
        xk_im : out STD_LOGIC_VECTOR ( 31 downto 0 )     
           );    
        END COMPONENT;     
  
  
  --inputs
  signal clk :  STD_LOGIC  :='0'; 
  Signal start :  STD_LOGIC  :='1'; 
  Signal unload :  STD_LOGIC  :='0'; 
  Signal fwd_inv : STD_LOGIC  :='0'; 
  Signal fwd_inv_we : STD_LOGIC  :='0';
   Signal xn_re :  STD_LOGIC_VECTOR ( 31 downto 0 ) := "00000000000000000000000000000011"; 
  Signal xn_im :  STD_LOGIC_VECTOR ( 31 downto 0 ) := (others =&gt; '0'); 
  
   --outputs
  Signal rfd   :   STD_LOGIC; 
  Signal busy  :  STD_LOGIC; 
  Signal edone :  STD_LOGIC; 
  Signal done :       STD_LOGIC; 
  Signal dv   :       STD_LOGIC; 
  Signal xn_index :  STD_LOGIC_VECTOR ( 3 downto 0 ); 
  Signal xk_index :  STD_LOGIC_VECTOR ( 3 downto 0 ); 
  Signal xk_re :  STD_LOGIC_VECTOR ( 31 downto 0 ); 
  Signal xk_im :  STD_LOGIC_VECTOR ( 31 downto 0 );
  
  
  
  
  
  
  --constant  declaration 
  constant clk_period : time := 10 ns;
  
  
  
      BEGIN
  
      -- Component Instantiation
        uut: tt16 
         PORT MAP(
        clk , start , unload , fwd_inv , fwd_inv_we ,rfd , busy , edone , done                           ,dv , xn_re , xn_im ,
         xn_index , xk_index , xk_re , xk_im );
  
  
   --Clock process definitions
   clk_process :process
   begin
   clk &lt;= '0';
   wait for clk_period/2;
   clk &lt;= '1';
   wait for clk_period/2;
   end process;
  
  
  
      --  Test Bench Statements
   tb : PROCESS
  
         BEGIN
           start &lt;='1';
         unload &lt;='0';
          fwd_inv &lt;='0'; 
         fwd_inv_we &lt;='1';
  
    wait for clk_period;
    xn_re &lt;= "00000000000000000000000000000001";
    xn_im &lt;= "00000000000000000000000000000000";
     wait for clk_period;
    xn_re &lt;= "00000000000000000000000000000011";
    xn_im &lt;= "00000000000000000000000000000000";
     wait for clk_period;
    xn_re &lt;= "00000000000000000000000000000001";
    xn_im &lt;= "00000000000000000000000000000000";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000000000000001111";
    xn_im &lt;= "00000000000000000000000000000000";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000000000000000001";
    xn_im &lt;= "00000000000000000000000000000000";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000000000000000001";
    xn_im &lt;= "00000000000000000000000011100001";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000000000000000011";
    xn_im &lt;= "00000000000000000000000000000011";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000001110000000011";
    xn_im &lt;= "00000000000000000000000000000010";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000000000000000011";
    xn_im &lt;= "00000000000000000000000000000010";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000000000000000011";
    xn_im &lt;= "00000000000000011110000000000110";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000000000000000011";
    xn_im &lt;= "00000000000000000000000000000000";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000000000000000011";
    xn_im &lt;= "00000000000000011110000000000010";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000000000000000011";
    xn_im &lt;= "00000000000000000000000000000000";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000001111100000011";
    xn_im &lt;= "00000000000000000000000000000000";
     wait for clk_period; 
    xn_re &lt;= "00000000000000000000000000000011";
    xn_im &lt;= "00000000000000000000000000000111";
  
    unload &lt;= '1';
    start &lt;= '0';
  
          wait; -- will wait forever
         END PROCESS tb;
      --  End Test Bench 
  
      END;
  </code></pre>