title: SAMD21 clock configuration
body: <p>I'm trying to configure my SAMD21 clock to go as fast as it can. So I'm using the internal 8 MHz oscillator to feed generic clock generator 1 (with a prescaler of 8) to generate a generic clock to feed the digital phase locked loop, which in turn feeds generic clock generator 0 (my main clock)  that should clock the CPU, but the micro is running very slowly, where did I make a mistake?
  ​I followed this guide <a href="http://borkedlabs.com/2014/08/21/asf-samd21-dpll-for-internal-clock-from-internal-8mhz/" rel="nofollow noreferrer">http://borkedlabs.com/2014/08/21/asf-samd21-dpll-for-internal-clock-from-internal-8mhz/</a>​ , but it doesn't work. Here's my code:</p>
  
  <pre><code>void system_clock_init(void)
  {
      SYSCTRL-&gt;INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | SYSCTRL_INTFLAG_DFLLRDY;
  
      /* switch off all peripheral clocks to save power */
      //_switch_peripheral_gclk();
  
      /* configure and enable generic clock generator 1 (GENCTRL and GENDIV registers of GCLK module) */
      struct system_gclk_gen_config gclk_gen_config1;
      system_gclk_gen_get_config_defaults(&amp;gclk_gen_config1);
      gclk_gen_config1.source_clock = SYSTEM_CLOCK_SOURCE_OSC8M;
      gclk_gen_config1.division_factor = 8;
      gclk_gen_config1.output_enable = false;
      system_gclk_gen_set_config(GCLK_GENERATOR_1,&amp;gclk_gen_config1);
      system_gclk_gen_enable(GCLK_GENERATOR_1);
  
      /* configure and enable generic clock for DPLL (CLKCTRL of GCLK module) */
      struct system_gclk_chan_config gclk_chan_config;
      system_gclk_chan_get_config_defaults(&amp;gclk_chan_config);
      gclk_chan_config.source_generator = GCLK_GENERATOR_1;
      system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL,&amp;gclk_chan_config);
      system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL);
  
      /* configure and enable clock source: DPLL (SYSCTRL registers) */
      struct system_clock_source_dpll_config dpll_config;
      system_clock_source_dpll_get_config_defaults(&amp;dpll_config);
      dpll_config.reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK;
      dpll_config.reference_divider = 1;
      dpll_config.reference_frequency = 1000000;
      dpll_config.output_frequency = 30000000;
      system_clock_source_dpll_set_config(&amp;dpll_config);
      system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL);
  
      /* set NVM wait states */
      system_flash_set_waitstates(2);
  
      /* configure and enable generic clock 0 (GCLK_MAIN) */
      struct system_gclk_gen_config gclk_gen_config0;
      system_gclk_gen_get_config_defaults(&amp;gclk_gen_config0);
      gclk_gen_config0.source_clock = SYSTEM_CLOCK_SOURCE_DPLL;
      gclk_gen_config0.division_factor = 1;
      system_gclk_gen_set_config(GCLK_GENERATOR_0,&amp;gclk_gen_config0);
      system_gclk_gen_enable(GCLK_GENERATOR_0);
  }
  </code></pre>
  
  <p>I updated the conf_clocks.h header to reflect the changes (I don't know if those macros are referenced somewhere else, so just in case) and I changed the system_clock_init() function that's called from system_init().</p>