title: Adding cell to write_verilog causes error
body: <p>first of all, I'd like to say I'm not well versed in c++ or verilog at all, so I have a few problems implementing things in Yosys.</p>
  <p>I'm currently looking for a way to implement a naive information flow tracking approach to <em>write_verilog</em>. The way I intent to implement it, is by creating a new var for each input/output etc. All operations types will be exchanged with simple '<em>or</em>'s. The doubled variables serve as taint bits. Doubling all the wires was an easy task. However when I try to add a new cell, I run into a '<em>std::out_of_range</em>' error (edit: just as I was trying it again, it appears to be an '<em>Found error in internal cell</em>' error now) while dumping the module. As the error happens while calling the dump_module function, I assume the module model broke.</p>
  <p>What I've done is that for every wire in the module, I've added the same wire just with <em>'_taint</em>' appended to its name, its properties stays the same as the original wire, I've basically used a slightly modified version of add_wire from /passes/add.cc.</p>
  <pre><code>// adding taint wires
  
  void attach_ift(RTLIL::Module *module, bool precise)
  {
  
      auto wires = module-&gt;wires_;
      for (auto &amp;wire : wires){
          std::string ift_wire_name = RTLIL::id2cstr(wire.second-&gt;name) + std::string(&quot;_taint&quot;);
          add_wire(module, ift_wire_name, 1, wire.second-&gt;port_input, wire.second-&gt;port_output);
      }
  
      //add cells and connections
  
  }
  
  static void add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output)
  {
      RTLIL::Wire *wire = nullptr;
      name = RTLIL::escape_id(name);
  
      if (module-&gt;count_id(name) != 0)
      {
          wire = module-&gt;wire(name);
  
          if (wire != nullptr &amp;&amp; wire-&gt;width != width)
              wire = nullptr;
  
          if (wire != nullptr &amp;&amp; wire-&gt;port_input != flag_input)
              wire = nullptr;
  
          if (wire != nullptr &amp;&amp; wire-&gt;port_output != flag_output)
              wire = nullptr;
  
          if (wire == nullptr)
              log_cmd_error(&quot;Found incompatible object with same name in module %s!\n&quot;, module-&gt;name.c_str());
  
          log(&quot;Module %s already has such an object.\n&quot;, module-&gt;name.c_str());
      }
      else
      {
          wire = module-&gt;addWire(name, width);
          wire-&gt;port_input = flag_input;
          wire-&gt;port_output = flag_output;
  
          if (flag_input || flag_output) {
              module-&gt;fixup_ports();
          }
  
          log(&quot;Added wire %s to module %s.\n&quot;, name.c_str(), module-&gt;name.c_str());
      }
  }
  </code></pre>
  <p>This works fine.</p>
  <p>Now for the problem with cells. How do I add cells properly?<br />
  at first I tried to use</p>
  <pre><code>//add cells
  
  void attach_ift(RTLIL::Module *module, bool precise)
  {
      // add wires
  
      auto cells = module-&gt;cells_;
      for (auto &amp;cell : cells){
          std::string ift_cell_name = cell.first.c_str() +std::string(&quot;_taint&quot;);
          auto cell_ = cell.second;
          add_cell(module, ift_cell_name, cell_);
      }
  
      // add connections
  }
  
  static void add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output)
  {
      RTLIL::Wire *wire = nullptr;
      name = RTLIL::escape_id(name);
  
      if (module-&gt;count_id(name) != 0)
      {
          wire = module-&gt;wire(name);
  
          if (wire != nullptr &amp;&amp; wire-&gt;width != width)
              wire = nullptr;
  
          if (wire != nullptr &amp;&amp; wire-&gt;port_input != flag_input)
              wire = nullptr;
  
          if (wire != nullptr &amp;&amp; wire-&gt;port_output != flag_output)
              wire = nullptr;
  
          if (wire == nullptr)
              log_cmd_error(&quot;Found incompatible object with same name in module %s!\n&quot;, module-&gt;name.c_str());
  
          log(&quot;Module %s already has such an object.\n&quot;, module-&gt;name.c_str());
      }
      else
      {
          auto ift_cell = module-&gt;addCell(name, &quot;$or&quot;);
          auto cons = cell-&gt;connections();
          for (auto con : cons){
  
              auto wire_ = cell-&gt;getPort(con.first).as_wire();
              auto taint_wire_name = string(wire_-&gt;name.c_str()) + &quot;_taint&quot;;
              auto wire = module-&gt;wire(taint_wire_name);
              ift_cell-&gt;setPort(taint_wire_name, wire);
          }
  
          log(&quot;Added cell %s to module %s.\n&quot;, name.c_str(), module-&gt;name.c_str());
      }
  }
  </code></pre>
  <p>I attach the ift function right before I dump the module, so at this point</p>
  <pre><code>    void execute(std::ostream *&amp;f, std::string filename, std::vector&lt;std::string&gt; args, RTLIL::Design *design) override
      {
  
          // some code
  
          for (auto module : design-&gt;modules()) {
  
              //more code
  
              log(&quot;Attaching ift annotations to `%s'.\n&quot;, module-&gt;name.c_str());
              attach_ift(module, precise);
  
              log(&quot;Dumping module `%s'.\n&quot;, module-&gt;name.c_str());
              dump_module(*f, &quot;&quot;, module);
          }
  
          auto_name_map.clear();
          reg_wires.clear();
      }
  
  </code></pre>
  <p>I then thought maybe I failed at setting proper connections.
  However even just adding a simple <code>module-&gt;addCell(&quot;$dummyName&quot;, &quot;$or&quot;);</code> crashed my program.</p>
  <p>Can someone please help me?</p>