title: VHDL error in For loop
body: <p>In the following code I receive the following errors, but  I don't understand why is it an error.</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity RGSTR_SHFT_N_PARAL_B2 is
  
  Generic (
       n: integer := 4  
       );
  
    port(
      DATA : in std_logic_vector((n-1) downto 0); 
      Shift_In : in std_logic; 
      Load : in std_logic;  
      Enable : in std_logic;  
  CLK : in    std_logic;  
  S : out   std_logic_vector((n-1) downto 0)   
          );
  end entity RGSTR_SHFT_N_PARAL_B2;
  
  architecture simple of RGSTR_SHFT_N_PARAL_B2 is
  
    signal temp_S: std_logic_vector((n-1) downto 0);
  
    signal LOW0, HIGH1: std_logic; -- Constant Signals   
  
    -- Use the D flip flop of B1 excersise
        component D_FF_B1 is
          port( 
          Enable      : in    std_logic;  
         Load        : in std_logic;  
      Load_Val    : in    std_logic;  
       Data_in     : in   std_logic;  
       CLK        : in    std_logic;  
       Q           : out   std_logic  
      );
    end component;
  
  begin
  
    p0:process(Enable, CLK) is
    begin
  
  -- Initialisations 
  
    LOW0  &lt;= '0';
    HIGH1 &lt;= '1';
  
      if (Enable = LOW0) then
             L0: for i in 0 to (n-1) loop
                temp_S(i) &lt;= temp_S(i);
             end loop;
         elsif (CLK 'event and CLK = HIGH1) then 
             if (Load = LOW0)  then             -- Shifter is enabled
                L1: for i in 0 to (n-2) loop
                    temp_S(i) &lt;= temp_S(i+1);
                end loop;
                temp_S(n-1) &lt;= Shift_In;
             else                               -- Loader is enabled
                L2: for i in 0 to (n-1) loop
                  X1: D_FF_B1 port map(HIGH1, LOW0, LOW0, DATA(i), CLK, temp_S(i));
                end loop;
             end if;
         end if;
  
    L3: for i in 0 to (n-1) loop
       S(i) &lt;= temp_S(i);
    end loop;
  
    end process p0;
  
  end architecture simple;
  </code></pre>
  
  <p>Error message:</p>
  
  <pre><code>Error (10500): VHDL syntax error at RGSTR_SHFT_N_PARAL_B2.vhd(79) near text "port";  expecting "(", or "'", or "."
  Error (10500): VHDL syntax error at RGSTR_SHFT_N_PARAL_B2.vhd(79) near text ";";  expecting ":=", or "&lt;="
  </code></pre>
  
  <p>I compile the VHDL program with Quartus II.</p>