title: If a pipeline stage is stalled due to a dependency, do all the stages which follow get stalled for that cycle?
body: <p>If a pipeline stage in a MIPS architecture is stalled due to a dependency, do all the stages which follow get stalled for that cycle? If yes, why?
  e.g.</p>
  
  <pre><code>                                                 1  2    3    4    5    6     7
      add r1, r2, (r3)                            IF  ID  MEM  EX    WB       
      sub r4, r5, (r1)                                IF  ID  stall  MEM  EX    WB  
      st  r4, 0(r10)                                      IF  stall  ID  stall  MEM   
  </code></pre>
  
  <p>In this example, can we do ID of the third instruction in cycle 4? To be more precise, is this allowed -</p>
  
  <pre><code>                                                 1  2    3   4     5    6     7
      add r1, r2, (r3)                            IF  ID  MEM  EX    WB       
      sub r4, r5, (r1)                                IF  ID  stall  MEM  EX   WB     
      st  r4, 0(r10)                                      IF   ID  stall stall MEM     
  </code></pre>