title: Please help identify the mistake in this clock divider code
body: <p>Clock divider from 50mhz (verilog code). I am trying to burn this on fpga but its not working properly. I am using model sim from mentor graphics. Please help identify my mistake.</p>
  
  <pre><code>module clk_div(
  clk,
  rst,
  count);
  
  parameter count_width=27;
  parameter count_max=25000000;
  
  output [count_width-1:0] count;
  reg [count_width-1:0] count;
  input clk,rst;
  
  initial
  count=0;
  
  always@(posedge clk)
    if (rst)
    begin
        count&lt;=0;
    end
    else if (count&lt;count_max-1)
    begin
        count&lt;=count+1;
    end
    else if (count==count_max)
    begin
        count &lt;=~count;
    end
    else if (count&gt;count_max)
    begin
        count&lt;=0;
    end
  endmodule
  </code></pre>