title: systemVerilog - round real type
body: <p>What is the best way to round a real type in systemVerilog according:</p>
  
  <p>Case positive:
  if <code>fraction &gt;= 0.5</code>   ---> round return the "integer part" + 1 (for example 4.5 --->5) 
  if <code>fraction &lt; 0.5</code>   ---> round return the "integer part" (for example 4.2 --->4) </p>
  
  <p>Case negative:
  if <code>fraction &gt;= 0.5</code>   ---> round return the "integer part" -1 (for example -4.5 --->-5) 
  if <code>fraction &lt; 0.5</code>   ---> round return the "integer part" (for example -4.2 ---> -4) </p>