title: Using assignment pattern for union inside a struct in SystemVerilog
body: <p>This is an example for illustration. In SystemVerilog, it has array assignment pattern and struct assignment pattern syntax. No matter the union construct here is packed or unpacked, whether it is synthesizable or not, is it a valid usage for assignment pattern? If yes, what value should be for union <code>x</code>?</p>
  
  <pre><code>typedef struct {
    int a;
    byte b;
    union packed {
        int c;
        bit [31:0] d;
    } x;
  } S;
  
  module top (s);
    output S s;
    assign s = '{int:2, default:1};
  endmodule
  </code></pre>
  
  <p>If no, is it means I have to specify the initial value each field by field for the unpacked structure?</p>
  
  <pre><code>initial begin
    s.a = 2;
    s.b = 1;
    s.x.c = 2;
  end
  </code></pre>