title: Can enum be made an output in systemverilog?
body: <p>In verilog, I can do something like this:</p>
  
  <pre><code>module controller (
      input rstb, clk, start,
      output reg [1:0] state, next_state
  );
      parameter S_idle = 2'b00, S_1 = 2'b01, S_2 = 2'b11;
  
      always @ (posedge clk, negedge rstb)
      begin
          if (!rstb) state &lt;= S_idle;
          else state &lt;= next_state;
      end
  ...
  endmodule
  </code></pre>
  
  <p>But in systemverilog, this will generate an error since I declared <code>state, next_state</code> twice:</p>
  
  <pre><code>module controller (
      input rstb, clk, start,
      output logic [1:0] state, next_state
  );
      enum logic [1:0] {S_idle, S_1, S_2} state, next_state;
  
      always_ff @ (posedge clk, negedge rstb)
      begin
          if (!rstb) state &lt;= S_idle;
          else state &lt;= next_state;
      end
  ...
  endmodule
  </code></pre>
  
  <p>I suppose I could rename my output ports to <code>state_out, next_state_out</code> and assign them to <code>state, next_state</code>. Is there an easier way to use the enum as an output?</p>