title: How to set VHDL vector size based on the log of a constant
body: <p>I would like to know what is corresponding VHDL code for <code>$clog2(DATA_WIDTH)</code> , for example in this line:</p>
  
  <pre><code>parameter DATA_OUT_WIDTH = $clog2(DATA_WIDTH)
  </code></pre>
  
  <p>and also for this sign " -: " in this example</p>
  
  <pre><code>if ( Pattern == In[i_count-:PATTERN_WIDTH] )
  </code></pre>
  
  <p>I will appreciate if anyone can help me.</p>