title: Comparing input signal with array values
body: <p>As I wrote in my previous post <a href="https://stackoverflow.com/questions/30030140/synthesizable-values-array">Synthesizable array of XY values</a>
  I wanted to create an array in Verilog to store <code>x</code>, <code>y</code> values of a given function.</p>
  
  <p>Now I want to compare an input with <code>x</code> values of this array. If the value is within a specific region I want to save the index of this region and perform an addition with <code>y</code> with the same index. The result goes to the output. The code compiles just fine but its not synthesizes any circuit. The idea later is to use this array to perform linear interpolation and determinate the value of <code>y</code> for a given value of <code>x</code> that its not inside the array. The code is the following. I save the save value for <code>x</code> and <code>y</code> for each index. </p>
  
  <pre><code> module memc (inp,outp,clk,reset);
      input[2:0] inp;
      input clk, reset; 
      output[2:0] outp;
      reg[2:0] outp;
      wire [2:0] test;
      reg [5:0] mem[2:0];
  
  always @(posedge clk)
  if (reset == 1'b1) begin
      mem[0] &lt;= {3'b000, 3'b000};//y0,x0
      mem[1] &lt;= {3'b001, 3'b001};//y1,x1
      mem[2] &lt;= {3'b010, 3'b010};//y2,x2
  end
  
  
  assign test ={inp&lt;mem[0][2:0],inp&lt;mem[1][2:0],inp&lt;mem[2][2:0]}; //create a test vector by comparing inp with xo,x1,x2
  always @(test)
  case (test)
  3'b1xx: outp=mem[0][2:0]+mem[0][5:3];//if 0&lt;inp&lt;x1
  3'b0xx: outp=mem[1][2:0]+mem[1][5:3];//if x1&lt;inp&lt;x2
  3'b00x: outp=mem[2][2:0]+mem[2][5:3];//if x2&lt;inp&lt;x3
  default: outp=3'b00;
  endcase
  endmodule
  </code></pre>