title: clock switching in systemverilog test-bench
body: <p>In order to verify my block's DVFS feature, the clock to DUT should switch based on one event.
  for example, if the control register updated to fast mode, my TB need increase the clock frequency, if the control register updated to slow mode, my TB need decrease the clock frequency.</p>
  <p>How can I do this with systemverilog in TB?
  In my simple TB, the clock is always at a fixed frequency.</p>