title: discrete cosine transform using VHDL
body: <p>Am working on discrete cosine transform using VHDL. Am trying to convert the VHDL code from integer to standard logic vector. I applied some of the techniques i read online and from textbooks but it didn't work. Below is the code i tried converting.I would like the input length to be  8 bit and the output length to be 12bit.Thank you. </p>
  
  <pre><code>entity dct is
      port (
              Clk :           in BIT;
              Start :         in BIT;
              Din :           in INTEGER;
              Done :          out BIT;
              Dout :          out INTEGER
              );
  end dct;    
  
  architecture behavioral of dct is
  begin
      process
              type RF is array ( 0 to 7, 0 to 7 ) of INTEGER;
  
              variable i, j, k        : INTEGER;
              variable InBlock        : RF;
              variable COSBlock       : RF;
              variable TempBlock      : RF;
              variable OutBlock       : RF;
              variable A, B, P, Sum   : INTEGER;
  
      begin
  </code></pre>
  
  <p>Here is the one i tried after reading some books and i keep getting errors.</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
  
  
  entity dct is
      port (
              Clk :           in std_logic;
              Start :         in std_logic;
              Din_temp:       in INTEGER;
              temp := conv_std_logic_vector(Din_temp, 8);
              Done :          out std_logic;
              Dout_temp:     out INTEGER;
              temp := conv_std_logic_vector(Dout_temp, 9));
  
  end dct;
  
  architecture behavioral of dct is
  begin
      process
              type  RF is matrix( 0 to 7, 0 to 7 ) of  ;
  
              variable i, j, k        : std_logic_vector(7 downto 0);
              variable InBlock        : RF;
              variable COSBlock       : RF;
              variable TempBlock      : RF;
              variable OutBlock       : RF;
              variable A, B, P, Sum   : std_logic_vector(7 downto 0);
  
      begin
  </code></pre>