title: Type enumeration in VHDL
body: <p>What is the type enumeration in the VHDL?
  where can I use it, to make the code shorter and more understandable? 
  for example, consider a bellow statement: </p>
  
  <pre><code>TYPE st_State IS (st_Idle, st_CheckHeader1, st_CheckHeader2, st_ReceiveData)
  </code></pre>
  
  <p>when must to use it. </p>