title: VHDL compiler error
body: <p>ERROR:HDLParsers:164 - "C:/.Xilinx/Counter/Main.vhd" Line 35. parse error, unexpected ENTITY, expecting COMMA or SEMICOLON</p>
  
  <p>I don't know what error it pointing out... I am not able to see what it means, could someone clarify it for me.. </p>
  
  <pre><code>----------------------------------------------------------------------------------
  -- Company: 
  -- Engineer: 
  -- 
  -- Create Date:    23:52:28 03/05/2014 
  -- Design Name: 
  -- Module Name:    Main - Behavioral 
  -- Project Name: 
  -- Target Devices: 
  -- Tool versions: 
  -- Description: 
  --
  -- Dependencies: 
  --
  -- Revision: 
  -- Revision 0.01 - File Created
  -- Additional Comments: 
  --
  ----------------------------------------------------------------------------------
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL
  -- Uncomment the following library declaration if using
  -- arithmetic functions with Signed or Unsigned values
  --use IEEE.NUMERIC_STD.ALL;
  
  -- Uncomment the following library declaration if instantiating
  -- any Xilinx primitives in this code.
  --library UNISIM;
  --use UNISIM.VComponents.all;
  
  
  
  
  entity Main is
  PORT(
          CLK: in std_logic;
          LED: out std_logic_vector (7 downto 0)
          );
  
  end Main;
  
  
  architecture Behavioral of Main is
  signal counter: std_logic_vector (7 downto 0);
  signal prescaler:  std_logic_vector( 22 downto 0);
  begin
  
  CounterProcess: process(CLK)
  begin
  if rising_edge(CLK) then
      if prescaler &lt; "1111111111111111111111" then 
          prescaler &lt;= prescaler + 1;
          else
              prescaler &lt;= (others =&gt; '0'); 
              counter &lt;= counter + 1;
      end if;
  end if; 
  end process;
  
  LED &lt;= counter; 
  
  end Behavioral;
  </code></pre>