title: Error using non-constant real valued expression for synthesizable VHDL
body: <pre><code> when f9 =&gt;
         if melcol &lt; 128 and framcounter &lt; 2560 then
             temp &lt;= std_logic_vector(signed(framout)*to_signed(melf(melrow,melcol),8));
             firstmelout &lt;= firstmelout + (to_integer(unsigned(temp)))/1000;
             melcol &lt;= melcol+1;
             framcounter &lt;= framcounter+1;
             fstate &lt;= f9;
         elsif melcol = 128 and melrow &lt; 13 and framcounter &lt; 2560 then
             -----MEMORY NEEDED
             framcounter &lt;= framcounter -128;
             melrow &lt;= melrow+1;      --melrow filter number
             melcol &lt;= 0;
             secondmelout &lt;= firstmelout;
             fstate &lt;= f10;
         elsif melcol = 128 and melrow = 13 and framcounter &lt; 2560 then
             ---------MEMORY NEEDED
             framcounter &lt;= framcounter +128;
             melrow &lt;= 0;
             melcol &lt;= 0;
             secondmelout &lt;= firstmelout;
             fstate &lt;= f10;
         elsif framcounter = 2560 then
             flagmel &lt;= '1';
             fstate &lt;= f12;
         else fstate &lt;= f12;
         end if;
  
     when f10 =&gt;
         varmel &lt;= real(secondmelout);
         --varmel := LOG10(firstmelout);
         --varlogresult := 100*varlogresult;
         wea3(0) &lt;= '1';
         --logresult &lt;= intlogresult;
         fstate &lt;= f11;
  </code></pre>
  
  <p>I have a problem to convert non-constant integer to real. I want to take log10 of the firstmelout, but real type is needed. So I tried to cast it to real by using "real()" but Vivado returns this error message;
  non-constant real valued expression is not supported</p>
  
  <p>I tried lots of things but i couldn't solve it, I'm waiting your helps guys
  Thanks a lot.</p>