title: Why is the timer output unknown?
body: <p>I just started building up-count timer in Verilog, and I keep getting unknown as output.</p>
  
  <p>I'm using 50MHz osciliator and these variables for the code:</p>
  
  <p>min : sec : 1/100 sec </p>
  
  <p>a b : c d : e f</p>
  
  <p>For example, I want the timer to be:</p>
  
  <pre><code>00:00:99 &gt; 00:01:00
  ...
  00:59:99 &gt; 1:00:00
  </code></pre>
  
  <pre><code>module timer    (clk,
          a,
          b,
          c,
          d,
          e,
          f,
          count);
  
  
  input clk;
  input [18:0]count;
  
  
  output reg[3:0]a;
  output reg[3:0]b;
  output reg[3:0]c;
  output reg[3:0]d;
  output reg[3:0]e;
  output reg[3:0]f;
  
  
  always@(posedge clk) 
  begin
      if (f == 4'b1010)       f = 4'b0000;
      else if (count == 19'd500000)   f = f+4'b0001;
  end 
  
  always@(posedge clk) 
  begin
      if (e == 4'b1010)       e = 4'b0000;
      else if (f == 4'b1010)      e = e +4'b0001;
  end 
  
  always@(posedge clk) 
  begin
      if (d == 4'b1010)       d = 4'b0000;
      else if (e == 4'b1010)       d = d +4'b0001;
  end 
  
  always@(posedge clk) 
  begin
      if (c == 4'b1010)       c = 4'b0000;
      else if (d == 4'b1010)       c = c +4'b0001;
  end 
  
  always@(posedge clk) 
  begin
      if (b == 4'b1010)       b = 4'b0000;
      else if (c == 4'b0101)      b = b +4'b0001;
  end 
  
  always@(posedge clk) 
  begin
      if (a == 4'b1010)       a = 4'b0000;
      else if (c == 4'b1010)      a = a +4'b0001;
  end 
  
  endmodule
  
  </code></pre>
  
  <p>&lt; test bench ></p>
  
  <pre><code>`timescale 1ns / 1ps
  
  module tb_timer();
  
  parameter clk_period = 10;
  parameter N = 19;
  
  reg clk; 
  reg [N-1:0]count;
  
  wire [3:0]a;
  wire [3:0]b;
  wire [3:0]c;
  wire [3:0]d;
  wire [3:0]e;
  wire [3:0]f;
  
  //instatiate the module 
  timer U0(
      .count(count),
      .clk(clk),
      .a(a),
      .b(b),
      .c(c),
      .d(d),
      .e(e),
      .f(f));
  
  
  
  // clk signal
  always begin
   clk =0;
   forever #(clk_period/2)clk = ~clk;
  end
  
  // count signal 
  always begin
  f = 1'b0
  count = 1'b0;
  forever #clk_period count = ~count;
  end
  
  //reset signal
  initial begin
  reset = 1;
  #12 reset = 0;
  #(clk_period) reset = 0;
  end
  
  endmodule
  </code></pre>