title: packed vs unpacked vectors in system verilog
body: <p>Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this:</p>
  
  <pre><code>node [range_hi:range_lo]x;
  </code></pre>
  
  <p>and others that are defined like this:</p>
  
  <pre><code>node y[range_hi:range_lo];
  </code></pre>
  
  <p>I understand that <code>x</code> is defined as packed, while <code>y</code> is defined as unpacked.  However, I have no idea what that means.</p>
  
  <p>What is the difference between packed and unpacked vectors in System Verilog?</p>
  
  <p><strong>Edit:</strong> Responding to @Empi's answer, why should a hardware designer who's writing in SV care about the internal representation of the array?  Are there any times when I <em>shouldn't</em> or <em>can't</em> use packed signals?</p>