title: What is the difference between elseif and elsif in VHDL
body: <p>Currently, I've been involved in FPGA design techniques using Xilinix. While solving design problems, I repeatedly found the use of <code>elseif</code> and <code>elsif</code> in if-chain almost for similar statements.</p>
  
  <pre><code>elsif(clk'event and clk='1') then
                   pr_state&lt;=nx_state;
  </code></pre>
  
  <p>and</p>
  
  <pre><code>elseif S1=’0’ and  S0=’1’ then
       Z &lt;= B;
  </code></pre>
  
  <p>My problem is- what's the difference between these two constructs? Are they similar? I've gone through D.L. Perry's VHDL book and other online VHDL tutorials' sites but can't find solution.Thanks in advance!</p>