title: Implementing sum of integers up to N in Verilog
body: <p>I am trying to Design hardware that will produce the following sequence, F = sum of the first N whole number, that is, 1+2...+N.
  (e.g. If N=3, F=1+2+3=6). I am implementing a module that whenever its input N changes, it produces F, at latest N clock cycles later. N will be any 4-bit number (meaning that F has to be 7 bits long). N will not change while new a new F is being calculated. Here is my attempt:</p>
  
  <pre><code>module Fib (clock, reset, N, Fib);
  
  input clock, reset;  input [3:0] N;  
  output [6:0] Fib;
  
  reg [6:0] Fib;  
  // local vars  
  reg [2:0] Nprev; 
  reg [2:0] count;  
  reg  state, next_state;
  
  // control lines
  reg [1:0] Fmux, Cmux;
  
  //status line
  wire zero, equal;
  
  parameter wait4newN=1'b0,  
    wait4Zero=1'b1; 
  
  // Datapath
  always@(posedge clock)
    case(Fmux)
      2'h0 : Fib &lt;= N;
      2'h1 : Fib &lt;= Fib + count;
    endcase
  
  always@(posedge clock)
   case (Cmux)
      2'h0 : count &lt;= N-1;
      2'h1 : count &lt;= count - 1;
    endcase
  
  assign zero = (count == 0);
  assign equal = (Nprev==N);
  
  // Controller
  always@(posedge clock)
    Nprev &lt;= N;
  
  always@(posedge clock)
    if (reset) state &lt;= wait4newN;
      else 
        state &lt;= next_state;
  
  always@(*)
    begin
      Fmux = 0; Cmux = 0;
      case (state) // synopsys full_case parallel_case
        wait4newN : 
             if (!equal) 
               begin 
                 Fmux = 0; Cmux = 0;
                 next_state=wait4newN;
               end
             else 
                begin 
                  Fmux = 1; Cmux = 1;
                  next_state=wait4Zero;
                end
        wait4Zero : 
            if(!zero)
                begin
                    Fmux = 1; Cmux = 1;
                    next_state = wait4Zero;
                end
            else
              begin
                  Fmux = 0; Cmux =0;
                  next_state =wait4newN;
              end
        default:
           $display("why am I here?");
        endcase
    end
   endmodule
  </code></pre>
  
  <p>My test fixture is</p>
  
  <pre><code>// Testbench
  module test;
  
  reg  clk, reset;
  reg [3:0] N;
  reg [6:0] Fib; 
  
    // Instantiate device under test
  Fib fibInstance(.clock(clk),.reset(reset), .N(N), .Fib(Fib));
  
    initial begin
      // Dump waves
      $dumpfile("dump.vcd");
      $dumpvars(1, test);
  
      clk = 0;
      reset = 1;
      N = 5;
      $display("wait4newN N: %0h, Fib: %0h",
        N, Fib);
  
      toggle_clk;
      $display("wait4Zero N: %0h, Fib: %0h",
        N, Fib);
  
      toggle_clk;
      $display("wait4Zero N: %0h, Fib: %0h",
        N, Fib);
  
      toggle_clk;
      $display("wait4Zero N: %0h, Fib: %0h",
        N, Fib);
  
      toggle_clk;
      $display("wait4Zero N: %0h, Fib: %0h",
        N, Fib);
  
      toggle_clk;
      $display("wait4Zero N: %0h, Fib: %0h",
        N, Fib);
  
      toggle_clk;
      $display("wait4newN N: %0h, Fib: %0h",
        N, Fib);
    end
  
    task toggle_clk;
      begin
        #5 clk = ~clk;
        #5 clk = ~clk;
      end
    endtask
  
  endmodule
  </code></pre>
  
  <p>The result of simulation is XX for F.</p>
  
  <pre><code>[2017-10-21 20:17:23 EDT] iverilog '-Wall' '-g2012' design.sv testbench.sv  &amp;&amp; unbuffer vvp a.out  
  VCD info: dumpfile dump.vcd opened for output.
  wait4newN N: 5, Fib: xx
  wait4Zero N: 5, Fib: xx
  wait4Zero N: 5, Fib: xx
  wait4Zero N: 5, Fib: xx
  wait4Zero N: 5, Fib: xx
  wait4Zero N: 5, Fib: xx
  wait4newN N: 5, Fib: xx
  Done
  </code></pre>
  
  <p>What am I doing wrong please?</p>
  
  <p>Thank you very much for you time in advance.</p>