title: Can I give part selects meaningful names in verilog?
body: <p>Say I have an 8-bit flags register:</p>
  
  <pre><code>reg [7:0] flags;
  </code></pre>
  
  <p>While in my code I could refer to parts of it as <code>flags[0]</code>, <code>flags[3]</code>, <code>flags[7:4]</code> etc, I'd prefer to be able to do something along the lines of <code>flags.Z</code>, <code>flags.C</code>, <code>flags.STATE</code>.</p>
  
  <p>Currently, I've found that this comes close:</p>
  
  
  
  <pre><code>`define Z [0]
  `define N [1]
  `define C [2]
  `define V [3]
  `define STATE [7:4]
  reg [7:0] flags;
  </code></pre>
  
  <p>Which means I can both assign and evaluate <code>flags`Z</code>, <code>flags`C</code>, and <code>flags`STATE</code>. </p>
  
  <p>However, polluting the global namespace with single-letter defines seems like a bad idea, particularly since <code>notflags`N</code> would be accepted by the compiler. Is this acceptable none-the-less?</p>
  
  <p>Is there some easier way of doing this? I know SystemVerilog has structs, but I'm restricted to verilog 2001.</p>