title: Comparing Packed and Unpacked arrays in Verilog
body: <p>The objective in the following snippet of code is : </p>
  
  <p>Compare 2 Bytes of data which are stored in the form of a packed array (2 locations, 1byte in each) to 2 Bytes of data stored in an unpacked way.  </p>
  
  <pre><code>module byte_design (
  input wire clk,
  input   wire [7:0] my_data [1:0],
  input   wire [15:0] other_data,
  output reg temp
  );
  
  integer j;
  
  assign my_data[0] = 8'haa;
  assign my_data[1] = 8'hbb;
  assign other_data = 16'haabb;
  
  always @ (posedge clk) begin 
  
  for ( j = 0; j &lt; 2 ; j = j+1 ) begin 
    if ( other_data == my_data [j+:1]) begin 
      temp &lt;= 1'b1;
    end
    else begin 
      temp &lt;= 1'b0;
    end 
  end 
  end 
  
  endmodule 
  </code></pre>
  
  <p>So in the above code, according to my thought process, when j=0 other_data (16'haabb) will be equal to my_data[0:1] and result in temp=1'b1. </p>
  
  <p>Testing this design gives out the error of Illegal comparison between packed and an unpacked type.</p>
  
  <p>To summarize, the objective is here to compare 2Bytes of data with 2 1Bytes of data. Any suggestions/ procedure to do this is appreciated.  </p>