title: Johnson Counter Syntax error. Unexpected token: generate
body: <p>My college teacher asked for me to implement a Johnson Counter and it's test bench, with an width&lt;=32 (he calls it an N parameter), and the implementation has to use <code>generate/for</code> structures. Although I had learned a little about Johnson Counter, I don't know how to use <code>generate</code> in this case, and I had some errors when I tried to run the test bench. Here is my implementation so far:</p>
  <pre><code>module johnsonCounter #(parameter N = 32)  
    ( 
      input clk,                
      input rstn,
      output reg [N-1:0] out
    );    
  
    always @ (posedge clk) begin
      if (!rstn)
        out &lt;= 1;
      else begin
        out[N-1] &lt;= ~out[0];
        generate
          for (int i = 0; i &lt; N-1; i=i+1) begin
            out[i] &lt;= out[i+1];
          end
        endgenerate
  
      end
    end
  endmodule
  </code></pre>
  <p>Here is the test bench:</p>
  <pre><code>module tb;
    parameter N = 32;
    
    reg clk;
    reg rstn;
    wire [N-1:0] out;
    
    johnsonCounter    u0 (.clk (clk),
                  .rstn (rstn),
                  .out (out));
    
    always #10 clk = ~clk;
    
    initial begin
      {clk, rstn} &lt;= 0;
  
      $monitor (&quot;T=%0t out=%b&quot;, $time, out);
      repeat (2) @(posedge clk);
      rstn &lt;= 1;
      repeat (15) @(posedge clk);
      $finish;
    end
    
    initial begin
      $dumpvars;
      $dumpfile(&quot;dump.vcd&quot;);
    end
  endmodule
  </code></pre>
  <p>These are the errors:</p>
  <pre><code>ERROR VCP2000 &quot;Syntax error. Unexpected token: generate[_GENERATE]. This is a Verilog keyword since IEEE Std 1364-2001 and cannot be used as an identifier. Use -v95 argument for compilation.&quot; &quot;design.sv&quot; 13  7
  ERROR VCP2020 &quot;begin...end pair(s) mismatch detected. 2 &lt;end&gt; tokens are missing.&quot; &quot;design.sv&quot; 17  7
  ERROR VCP2020 &quot;module/macromodule...endmodule pair(s) mismatch detected. 1 &lt;endmodule&gt; tokens are missing.&quot; &quot;design.sv&quot; 17  7
  ERROR VCP2000 &quot;Syntax error. Unexpected token: endgenerate[_ENDGENERATE]. This is a Verilog keyword since IEEE Std 1364-2001 and cannot be used as an identifier. Use -v95 argument for compilation.&quot; &quot;design.sv&quot; 17  7
  </code></pre>
  <p>Any help is welcome =)</p>