title: 16-bit multiplier simulation results are incorrect
body: <p>I designed a 16-by-16 multiplier in Verilog. It compiles with no errors but results are not correct. Can anybody help me by the code reformation?</p>
  <p>The code is:</p>
  <pre><code>module q_1_2 (input [15:0]x,y, output [31:0]z);
    
    parameter size=256, width=16;
    wire [size-1:0]pi,ci,po,co;
    
    genvar  i,j;
    generate
      
      for (j=0;j&lt;16;j=j+1) assign pi[width*0+j]=0;
      for (i=0;i&lt;16;i=i+1) assign ci[width*i+0]=0;
      q_1_1 eb0_0 (x[0],y[0],pi[o],ci[0],po[0],co[0]);
      
      for (j=1;j&lt;16;j=j+1) begin
       assign ci[width*0+j] = co[width*0+(j-1)];
       q_1_1 eb0_j (x[0],y[j],pi[width*0+j],ci[width*0+j],po[width*0+j],co[width*0+j]);
      end
      
      for (i=1;i&lt;16;i=i+1) begin
       assign pi[width*i+0] = po[width*(i-1)+0];
       q_1_1 ebi_0 (x[i],y[0],pi[width*i+0],ci[width*i+0],po[width*i+0],co[width*i+0]);
      end
     
      for (i=1;i&lt;16;i=i+1) begin
        for (j=1;j&lt;15;j=j+1) begin
          assign ci[width*i+j] = co[width*i+(j-1)];
          assign pi[width*i+j] = po[width*(i-1)+j];
          q_1_1 ebi_j (x[i],y[j],pi[width*i+j],ci[width*i+j],po[width*i+j],co[width*i+j]);
        end
        
        assign ci[width*i+15] = co[width*i+14];
        assign pi[width*i+15] = co[width*(i-1)+15];
        q_1_1 ebi_15 (x[i],y[15],pi[width*i+15],ci[width*i+15],po[width*i+15],co[width*i+15]);
      end
      
      for (i=0;i&lt;16;i=i+1) assign z[i] = po[width*i+0];
      for (j=1;j&lt;16;j=j+1) assign z[j+15] = po[width*15+j];
      assign z[31] = co[width*15+15];
      
    endgenerate
  endmodule
  </code></pre>
  <p>where the q_1_1 module is:</p>
  <pre><code>module q_1_1 (input xi,yi,pi,ci, output po,co);
    wire i,j,k,l,m,n;
    and #5 (i,xi,yi);
    and #5 (j,pi,i);
    and #5 (k,ci,i);
    and #5 (l,pi,ci);
    or #5 (m,j,k);
    or #5 (co,l,m);
    xor #5 (n,pi,i);
    xor #5 (po,ci,i);
  endmodule
  </code></pre>
  <p>and the tb is:</p>
  <pre><code>module testq_1_2();
    
  reg [15:0] xx,yy;
  wire[31:0] zz;
  
  q_1_2 eb(xx,yy,zz);
      
  initial begin
      #0       xx=0;     yy=0;
      #1000    xx=9;     yy=11;
      #1000    xx=16;    yy=8;
      #1000    xx=14;    yy=14;
      #1000    xx=7;     yy=12;
      #1000    xx=24;    yy=3;
      #1000    xx=83;    yy=201;
      #1000    xx=24831; yy=19047;
      #1000    xx=0;     yy=0;
      #1000;
     end
  endmodule
  </code></pre>
  <p>What's wrong?</p>