title: Generate block inside case statement in verilog or system verilog
body: <p>Is there a way in Verilog or SystemVerilog to insert generate statement inside case statement to generate all the possible input combinations. For example a typical use case would be for a N:1 mux.</p>
  
  <pre><code>case(sel)
    generate
      for(i = 0; i &lt; N; i += 1)
        i: out = q[i];
    endgenerate
  endcase
  </code></pre>
  
  <p>I tried this, but the tool gives error. An alternate syntax is available which is</p>
  
  <pre><code>out &lt;= q[sel];
  </code></pre>
  
  <p>But, my tool is not understanding this(the mux is fully decoded) and generating combinational loops. I can use <code>if</code> statement to get the expected mux. But, I was wondering if there was a better way to do it.</p>