title: Verilog: code for MUX
body: <p>I am working on a verilog code with following requirements:
  It is Fully synchronous.
  Implement Muxes between 11 buses where each bus is 8-bits wide.
  It has 2 cycles of latency.
  It has Optimized for maximum clock frequency.</p>
  
  <p>I have written this code so far:</p>
  
  <pre><code>    module muxcase (a,b,c,d,e,f,g,h,i,j,k, select, op, clk, reset);
  input [7:0] a,b,c,d,e,f,g,h,i,j,k;
  input [3:0] select;
  output [7:0] op;
  reg op;
  input reset, clk;
  integer count= 2’b00;
  integer temp= 2’b00;
  always @ (posedge clk)
  begin 
  
  if (reset==1’b1)
  begin
  count=2’b00;
  op=8’b00000000;
  select=4’b0000;
  end
  if (reset==1’b0)
  begin 
  if (count &lt;3)
  begin
  count=count+1;
  temp=count;
  end
  end
  
  case (select)
  4’b0000: op=a;
  4’b0001: op=b;
  4’b0010: op=c;
  4’b0011: op=d;
  4’b0100: op=e;
  4’b0101: op=f;
  4’b0110: op=g;
  4’b0111: op=h;
  4’b1000: op=i;
  4’b1001: op=j;
  4’b1010: op=k;
  endcase
  
  end
  endmodule
  </code></pre>
  
  <p>Now i am not sure how to incorporate the maximum clk frequency part and whether my counter for 2 clock cycles has correct logic. Any help regarding that would be appreciated.</p>
  
  <p>Test Bench:</p>
  
  <pre><code>    module mux_tb;
      reg [7:0] a,b,c,d,e,f,g,h,i,j,k;
      reg [3:0] select;
  
      wire [7:0] op;
  
      initial
      begin
      a =1,b =1,c = 0,d=0,e=0,f=1,g=1,h=0,i=1,j=0,k=1;
      s=4’b0000;
      #5 s=4’b0011;
      #5 s=4’b0111;
      #5 s=4’b1010;
      end
      muxcase f1 (a,b,c,d,e,f,g,h,I,j,k, select, op, clk, reset);
  
      endmodule
  </code></pre>