title: Output get initialized with U logic in simulation in vhdl
body: <p>I am using Xilinx. Currently I am working on a project to develop a pipelined MIPS processor. I have made a component file called Program_Counter.vhd. When I simulate it using a testbench the output get initialised with U and then it's fine afterwards. I can't understand this behavior. Any help will be highly appreciated.</p>
  
  <p>My Program_Counter.vhd </p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.NUMERIC_STD.ALL;
  
  entity Program_Counter is
    port (clk,reset,Last : in std_logic;
          addressALU : in std_logic_vector(31 downto 0);
          addressIR : out std_logic_vector(31 downto 0)
       ) ;
  end entity ; -- Program_Counter
  
  architecture Behavioral of Program_Counter is
  
  signal PC : std_logic_vector(31 downto 0);
  
  begin
  process(clk)
  begin
  if rising_edge(clk) then
      if reset = '1' then
          PC &lt;= (others =&gt; '0');
      elsif Last ='1' then
          null;
      else
          PC &lt;= addressALU;       
      end if ;
  end if ;
  end process;
  addressIR &lt;= PC;
  end Behavioral;
  </code></pre>
  
  <p>Here is the testbench</p>
  
  <pre><code>LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  use ieee.std_logic_unsigned.all;
  USE ieee.numeric_std.ALL;
  
  ENTITY PC_tb IS
  END PC_tb;
  
  ARCHITECTURE behavior OF PC_tb IS 
  
      COMPONENT Program_Counter
      PORT(
           clk : IN  std_logic;
           reset : IN  std_logic;
           Last : IN  std_logic;
           addressALU : IN  std_logic_vector(31 downto 0);
           addressIR : OUT  std_logic_vector(31 downto 0)
          );
      END COMPONENT;
  
  
     --Inputs
     signal clk : std_logic := '0';
     signal reset : std_logic := '0';
     signal Last : std_logic := '0';
     signal addressALU : std_logic_vector(31 downto 0) := (others =&gt; '0');
  
      --Outputs
     signal addressIR : std_logic_vector(31 downto 0);
  
     -- Clock period definitions
     constant clk_period : time := 10 ns;
  
  BEGIN
  
      -- Instantiate the Unit Under Test (UUT)
     uut: Program_Counter PORT MAP (
            clk =&gt; clk,
            reset =&gt; reset,
            Last =&gt; Last,
            addressALU =&gt; addressALU,
            addressIR =&gt; addressIR
          );
  
     -- Clock process definitions
     clk_process :process
     begin
          clk &lt;= '0';
          wait for clk_period/2;
          clk &lt;= '1';
          wait for clk_period/2;
     end process;
  
     -- Stimulus process
     stim_proc: process
     begin        
  
        wait for 35 ns;
          --reset &lt;= '0';
              for i in 1 to 10 loop
                  addressALU &lt;= addressALU + "1";
                  wait for clk_period ;
              end loop;
  
        wait for clk_period*10;
  
        wait;
     end process;
  END;
  </code></pre>
  
  <p>please refer the waveform after simulation.
  Thanks in advance.</p>
  
  <p><a href="https://i.stack.imgur.com/zHY8R.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/zHY8R.png" alt="enter image description here"></a></p>