title: Makefile error: No rule to make target
body: <pre><code>SOURCES = server.c
  
  TARGET = Server
  
  CC = gcc
  
  all: $(SOURCES) $(TARGET) 
  
  
  $(CC) $(SOURCES) -o $(TARGET) 
  
  clean:
  
  
  rm -rf $(TARGET) 
  </code></pre>
  
  <p>Above is the Makefile of my web server. Though server.c file is in the directory this gives the fallowing error</p>
  
  <pre><code>make: *** No rule to make target `Server', needed by `all'.  Stop.
  </code></pre>
  
  <p>What is the mistake I've made and how to solve it.</p>