title: System Verilog Function return value as parameterized bit vector
body: <p>I need to create a function in SystemVerilog with return value as a parameterized bit vector.
  My code is as follows:</p>
  
  <pre><code>class my_class #(parameter ADDR_WIDTH = 32);
      bit [ADDR_WIDTH-1:0] address;
  
      function bit [ADDR_WIDTH-1:0] get_address();
          return address;
      endfunction : get_address
  
  endclass : my_class
  </code></pre>
  
  <p>I get a compile time error in the function declaration saying that the parameter <code>ADDR_WIDTH</code> is not defined. Can anyone please explain why this is happening? The same is working without the parameter (i.e if I have a known value like <code>bit [31:0]</code>).</p>