title: How to toggle a std_logic between 1 and 0
body: <p>I want to toggle a std_logic vector '1' and '0' everytime the input sel='1'.
  I tried this with the following method but both lines give an error.</p>
  
  <pre><code>selected &lt;= not selected when sel='1';
  </code></pre>
  
  <blockquote>
    <p>ERROR: This construct is only supported in VHDL 1076-2008</p>
  </blockquote>
  
  <pre><code>selected &lt;= ~selected when sel='1';
  </code></pre>
  
  <blockquote>
    <p>ERROR: Syntax error near "~"</p>
  </blockquote>
  
  <p>Is there a better way to toggle, or what is the right syntax for a 'not' function.</p>
  
  <p>Here is the code for the entire architecture:</p>
  
  <pre><code>architecture Behavioral of selWeerg is
  
  signal selected : std_logic;
  
  begin   
  process(sel,digl,sysclk)
  begin
      if rising_edge(sysclk) then
  
          selected &lt;= ~selected when sel='1';
  
          if selected = '0' then
              digO1&lt;=digl(3 downto 0);
          else
              digO2&lt;=digl(3 downto 0);
          end if;
      end if;
  end process;
  end Behavioral;
  </code></pre>