title: How to show some different kinds of pictures on fpga board by using verilog with VGA
body: <p>I'm trying to do my school's project, and one of functions that I want to do is showing different kinds of picture when press different buttons. And as I know, I've to load different pictures in the memory. I'm now trying to load two different pictures and showing one of them. However, as it worked fine when I was trying with only one picture but show noting when I was trying with two pictures. Really hope someone can help me!!! The following are my codes.</p>
  
  <pre><code>module top(
  input clk,
  input rst,
  output [3:0] vgaRed,
  output [3:0] vgaGreen,
  output [3:0] vgaBlue,
  output hsync,
  output vsync
   );
  
  wire [11:0] data;
  wire clk_25MHz;
  wire clk_22;
  wire [16:0] pixel_addr;
  wire [11:0] pixel;
  wire valid;
  wire [9:0] h_cnt; //640
  wire [9:0] v_cnt;  //480
  wire [11:0] data_1;
  wire [16:0] pixel_addr_1;
  wire [11:0] pixel_1;
  wire valid_1;
  wire [9:0] h_cnt_1; //640
  wire [9:0] v_cnt_1;  //480
  
  assign {vgaRed, vgaGreen, vgaBlue} = (valid==1'b1) ? pixel:12'h0;
  
   clock_divisor clk_wiz_0_inst(
    .clk(clk),
    .clk1(clk_25MHz),
    .clk22(clk_22)
  );
  
  mem_addr_gen mem_addr_gen_inst(
  .clk(clk_22),
  .rst(rst),
  .h_cnt(h_cnt),
  .v_cnt(v_cnt),
  .pixel_addr(pixel_addr)
  );
  
  
  blk_mem_gen_0 blk_mem_gen_0_inst(
    .clka(clk_25MHz),
    .wea(0),
    .addra(pixel_addr),
    .dina(data[11:0]),
    .douta(pixel)
  );
  
  
  mem_addr_gen mem_addr_gen_inst_1(
      .clk(clk_22),
      .rst(rst),
      .h_cnt(h_cnt_1),
      .v_cnt(v_cnt_1),
      .pixel_addr(pixel_addr_1)
      );
  
  
      blk_mem_gen_1 blk_mem_gen_1_inst(
        .clka(clk_25MHz),
        .wea(0),
        .addra(pixel_addr_1),
        .dina(data_1[11:0]),
        .douta(pixel_1)
      ); 
  
  
  vga_controller   vga_inst(
    .pclk(clk_25MHz),
    .reset(rst),
    .hsync(hsync),
    .vsync(vsync),
    .valid(valid),
    .h_cnt(h_cnt),
    .v_cnt(v_cnt)
  );      
  endmodule
  </code></pre>
  
  <p>Since it can work in the right way using only one picture, I think the module vga_controller, clock_divisor, mem_addr_gen, and blk_mem_gen_0 won't have problems in the design of the module, therefore, I only post the details of my top module. Thanks!! </p>