title: Usage of $past in System Verilog Assertions
body: <p>I want to check if the current value of variable is '1' then the previous value of the variable should be '0'. I am using $past in System Verilog Assertions. Here I am checking if cal_frame_mode=1, then it's previous value of cal_frame_mode=0. My code is below. However, I am seeing assertion failure. When I check in the waveform it's behaving correctly. Assertion flags 2 clock after the the first check. How to stop this assertion after checking just one clock cycle?.</p>
  
  <pre><code>property p_NOP_2_RX_CAL;
    @(posedge clk)
    (cal_frame_mode==3'b001) |-&gt; ##2 $past(cal_frame_mode)==3'b000;  
  endproperty
  
  assert_nop2cal : assert property(p_NOP_2_RX_CAL);
  </code></pre>