title: Verilog: value(s) does not match array range, simulation mismatch
body: <p>The following code synthesizes and simulates correctly as far as I can tell, but XST is still giving the following <strong>warning:</strong> <code>value(s) does not match array range, simulation mismatch.</code> Is there something I'm missing?</p>
  
  <p>Tool used: Xilinx ISE Project Navigator (synthesizer:XST)
  FPGA: SPARTAN 3E</p>
  
  <pre><code>module error_example(
      input [47:0] data,
      input [2:0] sel,
      output [5:0] data_out
  );
  
     assign data_out = data[sel*6 +: 6];
  
  endmodule
  </code></pre>
  
  <p><code>WARNING:Xst:790 - "error_example.v" line 8: Index value(s) does not match array range, simulation mismatch.</code></p>
  
  <p>Like I said, this works and I've done the math:</p>
  
  <p><code>sel</code> can have values from 0 to 7,</p>
  
  <p>if <code>sel</code> is 0, then <code>data_out = data[5:0]</code>
  ...</p>
  
  <p>if <code>sel</code> is 7, then <code>data_out = data[47:42]</code></p>
  
  <p>Should I do something differently here? Is this a bug in XST?</p>