title: Is it possible that in MIPS an instruction's certain steps come before that of its predecessor in a pipelined structure?
body: <p>This is a problem about computer architecture and hope somebody has a clue. More specifically, it is about MIPS instruction pipelined flow. But I feel obscured about some aspects of it. Because I currently do not have enough reputation so I cannot post a image. </p>
  
  <ol>
  <li><p>Does an S (stall) mean no following instructions can utilize the time slot taken by the stall?</p></li>
  <li><p>Can two consecutive instructions both have X (execute) in the same time slot? </p></li>
  <li><p>Is it possible that the M (Memory Access) and W (Write Back) of an instruction come before that of its predecessor in a pipelined structure????</p></li>
  <li><p>In the situation of a loop and the last instruction is a repetition of the first instruction, why there are 2 F's (fetch) in the last instruction?</p></li>
  </ol>