title: Verilog: Using casex for synthesis
body: <p>I'm looking to implement a parallel case block that will check the value of a 16-bit register. In some cases, I need it to check for all 16 bits. However, in others, I only need to check a few. Is <strong><em>casex</em></strong> suitable in this scenario? If you hadn't already inferred, <strong><em>it is to be synthesized</em></strong>.</p>
  
  <p>It's part of a control matrix for a microprocessor. It's a Moore machine connected to an instruction register. Instructions are 16 bits wide. For some instructions, such as <strong><em>mov</em></strong>, the machine states are exactly the same, except the register/memory addressing is different. The instruction contains the information about what register or memory it's referencing, so I do not need to explicitly have a case for every possible instruction.</p>
  
  <p>For example, if my opcode was 1111, and the remaining 12 bits were addressing, I could simply use a case for 16'b1111xxxxxxxxxxxx.</p>
  
  <p>I'd like it to be parallel, and so I'm not using if-else statements. I'm unsure if this will work the way I intend it to. Any suggestions would be appreciated.</p>