title: Extending a simple makefile to support different implicit compiler flags
body: <p>I have been using a makefile that was fairly straightforward. I defined OBJS with a list of .cc files. I set up dependencies and include flags and appended all of those to $CXXFLAGS. It looks something like this:</p>
  
  <pre><code>SRCS = file1.cc file2.cc file3.cc
  OBJS = $(SRCS:.cc=.o)
  CXXFLAGS=some flags
  CXXFLAGS+=some include dirs
  $(mylib.so): $OBJS
      $CXX -shared -o $@ $^
  </code></pre>
  
  <p>mylib.so uses the CXXFLAGS (implicitly) and everything builds just fine.</p>
  
  <p>I have recently had the need to have mylib_1.so and mylib_2.so, in addition to mylib.so. Each .so depend on all the same .cc files, but the compiler flags are all different (including include directories). </p>
  
  <p>How do I get it so I can set the compiler flags based on the target .so? The problem that I have is that if I set CXXFLAGS more than once it gets overwritten. It's almost like I need an if/else situation. </p>
  
  <p>I tried doing something like setting three different flags, $CXXFLAGS1, $CXXFLAGS2, $CXXFLAGS3, and using those in the line</p>
  
  <pre><code>$(mylib1.so): $OBJS
      $CXX $(CXXFLAGS1) -shared -o $@ $^
  </code></pre>
  
  <p>but that does not work. </p>
  
  <p>How do I accomplish what I am trying to do? Is it better to have 3 separate makefiles? I did find a way to get it to work. I can stop using $OBJS and spell out the flags explicitly for each source file but this seems like a horrible idea in terms of scaling to size.</p>