title: Top level port with records in VHDL with multiple direction
body: <p>I want to use records as I have multiple ports which at the same time are composed by multiple signals. The issue is that some signals are in and some are out (AXI stream, specifically). </p>
  
  <p>I want to avoid doing this:</p>
  
  <pre><code>    port (
          s0_axis_tvalid : in STD_LOGIC;
          s0_axis_tdata  : in STD_LOGIC_VECTOR (Data_Width-1 downto 0);
          s0_axis_tlast  : in STD_LOGIC;
          s0_axis_tready : out STD_LOGIC;
  
          s1_axis_tvalid : in STD_LOGIC;
          s1_axis_tdata  : in STD_LOGIC_VECTOR (Data_Width-1 downto 0);
          s1_axis_tlast  : in STD_LOGIC;
          s1_axis_tready : out STD_LOGIC;
  
          m0_axis_tvalid : out STD_LOGIC;
          m0_axis_tdata  : out STD_LOGIC_VECTOR (Data_Width-1 downto 0);
          m0_axis_tlast  : out STD_LOGIC;
          m0_axis_tready : in STD_LOGIC);    
  </code></pre>
  
  <p>So, I want to have some records looking like this:</p>
  
  <pre><code>type AXIS_Slave is record
      s_axis_tvalid :  STD_LOGIC;
      s_axis_tdata  :  STD_LOGIC_VECTOR (Data_Width-1 downto 0);
      s_axis_tlast  :  STD_LOGIC;
      s_axis_tready :  STD_LOGIC;
  end record AXIS_Slave;
  
  type AXIS_Master is record
      s_axis_tvalid :  STD_LOGIC;
      s_axis_tdata  :  STD_LOGIC_VECTOR (Data_Width-1 downto 0);
      s_axis_tlast  :  STD_LOGIC;
      s_axis_tready :  STD_LOGIC;
  end record AXIS_Master;
  </code></pre>
  
  <p>Now, the port in my TOP's entity design should be:</p>
  
  <pre><code>Port (
      s0: AXIS_Slave;
      s1: AXIS_Slave;
      m0: AXIS_Master);
  </code></pre>
  
  <p>The problem is that I need to declare in the Port whether it is in or out but the direction of each signal should be defined in the record, which I believe is not allowed as I get a warning "Syntax error near in" or "Syntax error near out". </p>
  
  <p>So, how can I declare a type which has in and out signals? </p>