title: What is the difference between Verilog ! and ~?
body: <p>So it ended up that the bug that had kept me on for days, was a section of code that should have evaluated to False evaluating to True. My initial code went something like:</p>
  
  <pre><code>if(~x &amp;&amp; ~y) begin
      //do stuff
  end
  </code></pre>
  
  <p>i.e. If x is NOT ONE and y is NOT ONE then do stuff. Stepping through the debugger, I realized even though x was 1 the expression in the if-statement still resulted into TRUE and the subsequent code was executed. </p>
  
  <p>However, when I changed the statement to: </p>
  
  <pre><code>if(x == 0 &amp;&amp; y == 0) begin
  //do stuff
  end
  </code></pre>
  
  <p>and also tried: </p>
  
  <pre><code>if(!x &amp;&amp; !y) begin
  //do stuff
  end 
  </code></pre>
  
  <p>the code within the if-statement was not evaluated which was the expected behaviour. I understand that ~ is a bitwise negation and ! a logical negation, but shouldn't (~x &amp;&amp; ~y) and (!x &amp;&amp; !y) evaluate to the same thing? I'm afraid the codebase is too large, so I can't paste it here, but this was the only alteration I made to make the code to work as I intended. Thanks.</p>
  
  <hr>
  
  <p>In response, to one of the comments below, I have created a test-case to test this behaviour:</p>
  
  <pre><code>`timescale 10ns/1ns
  
  module test_negation();
          integer x, y;
  
      initial begin
          x = 1; y = 0;
  
          if(~x &amp;&amp; ~y) begin
              $display("%s", "First case executed");
          end
  
          if(!x &amp;&amp; !y) begin
              $display("%s", "Second case executed");
          end
  
          if(x == 0 &amp;&amp; y == 0) begin
              $display("%s", "Third case executed");
          end
      end endmodule
  </code></pre>
  
  <p>And strangely enough, "First case executed" is printed to confirm the original behaviour I observed.</p>