title: Verilog FIFO code written with different styles..one not working and another not working.Can someone explain
body: <p>I have written verilog code for fifo using fillcount to check as the means for checking if it is full or empty.
  There are 2 versions of the same code.
  One is whereI have a seprate always always block for reading,writing,empty /full ,fillcount,and one for incrementing the pointers.This works fine,I have tested it and it works fine.</p>
  
  <pre><code>module FIFO (clk, reset, data_in, put, get, data_out, fillcount, empty, full); 
  parameter DEPTHP2 = 8 ;
  parameter WIDTH = 8 ;
  input [WIDTH-1:0] data_in;
  input put, get, reset, clk; 
  output fillcount;
  output reg [WIDTH-1:0] data_out;
  output reg empty, full; 
  
  
  
  
  reg [3:0]fillcount ;
  reg [WIDTH-1:0] fifo_1[0:DEPTHP2-1];
  reg [2:0] rp,wp;
  
  
  always@(posedge clk or posedge reset)
  begin
     if( reset )
     begin
        wp &lt;= 0;
        rp &lt;= 0;
     end
     else
     begin
        if( !full &amp;&amp; put )    wp &lt;= wp + 1;
            else  wp &lt;= wp;
  
        if( !empty &amp;&amp; get )   rp &lt;= rp + 1;
        else rp &lt;= rp;
     end
  
  end
  
  always @(fillcount)
  begin
  if(fillcount==0)
    empty =1 ;
    else
    empty=0;
  
    if(fillcount==8)
     full=1;
     else
     full=0;
  end
  
  always @(posedge clk or posedge reset)
  begin
     if( reset )
         fillcount &lt;= 0;
  
     else if( (!full &amp;&amp; put) &amp;&amp; ( !empty &amp;&amp; get ) )
         fillcount &lt;= fillcount;
  
     else if( !full &amp;&amp; put )
         fillcount &lt;= fillcount + 1;
  
     else if( !empty &amp;&amp; get )
         fillcount &lt;= fillcount - 1;
     else
        fillcount &lt;= fillcount;
  end
  
  always @( posedge clk or posedge reset)
  begin:Reading
     if( reset )
        data_out &lt;= 0;
     else
     begin
        if( get &amp;&amp; !empty )
           data_out &lt;= fifo_1[rp];
  
        else
           data_out &lt;= data_out;
  
     end
  end
  
  always @(posedge clk)
  begin:Writing
  
     if( put &amp;&amp; !full )
        fifo_1[ wp ] &lt;= data_in;
  
     else
        fifo_1[ wp ] &lt;= fifo_1[ wp ];
  end
  
  endmodule
  </code></pre>
  
  <p>Another way is where I had combined the few always blocks together which effectng the logic(in my understanding!!)But it does not work for case when I try to read the data after writing immediately.It passes all other test cases.</p>
  
  <p>I am not sure what went wrong..
  It would be great if someone could point where I am going wrong.</p>
  
  <pre><code>//The code that is not working
  
  always@(posedge clk or posedge reset)
  begin:Writing
           if(reset)
          wp&lt;=0;
          else 
          if( put &amp;&amp; !full)
          begin
              fifo1[wp]&lt;=data_in;
              wp&lt;=wp+1;
          end
          else
          begin
              fifo1[wp]&lt;=fifo1[wp];
              wp&lt;=wp;
          end
  end
  
  
  always@(posedge clk or posedge reset)
  begin:Reading
      if(reset)
      begin
          rp&lt;=0;
          data_out&lt;=0;
      end
          else
      if(get &amp;&amp; !empty)
      begin
          data_out&lt;=fifo1[rp];
          rp&lt;=rp+1;
      end 
      else
      begin
          fifo1[rp]&lt;=fifo1[rp];
          rp&lt;=rp;
      end
  end
  
  always@(posedge clk or posedge reset)
  begin:Fillcount
      if(reset)
          fillcount&lt;=0;
          else
      if((!full &amp;&amp; put ) &amp;&amp; ( !empty &amp;&amp; get))
          fillcount&lt;=fillcount;
      else if(!full &amp;&amp; put)
          fillcount&lt;=fillcount+1;
      else if(!empty &amp;&amp; get)
          fillcount&lt;=fillcount-1;
      else
          fillcount&lt;=fillcount;
  
  end
  
  always@(fillcount)
  begin
      full=(fillcount==8);
      empty=(fillcount==0);
  end
  
  endmodule
  </code></pre>
  
  <p>Another question :
  The general way of coding in verilog as far as I have learned is to use fsm to draw the state diagram and use them..But I had a hard time when I try to code for the memory element like fifo,Tcam or double clock fifo.
  Is there any approach or  a way to do coding for these elements .</p>
  
  <p>Sorry for the long question</p>