title: Verilog syntax error in module declaration
body: <p>I am receiving a syntax error for the declaration of my second module, where I have indicated in the comments. I am using an online Verilog simulator so it does not tell me what kind of error. I'm really confused because I followed the same set up as the first module and I am not getting an error there. Does it have to do with reusing the variables? I tried changing them and it didn't seem to work.</p>
  
  <pre><code>    module MagnitudeComparator4Bit(input [3:0] a, input [3:0] b, output eq, output lt, output gt); 
  assign eq = a==b;
  assign lt = a &lt; b;
  assign gt = a &gt; b;
   endmodule
  
  module 8bitMagCompare(input [7:0] a, input [7:0] b, output EQ, output LT, output GT); //SYNTAX ERROR
  wire w1, w2, w3, w4;
  MagnitudeComparator4Bit MagComp1(a[7:4], b[7:4], w1, LT, GT);
  MagnitudeComparator4Bit MagComp2(a[3:0], b[3:0], w2, w3, w4);
  assign EQ = w1 &amp;&amp; w2;
  endmodule
  
  module MagCompareTB;
  reg a, b;
  wire EQ, LT, GT;
  
  8bitMagCompare testcompare(a, b, EQ, LT, GT);
  
  initial begin
  $monitor("%d A=%a, B=%b, EQ=%b, LT=%b, GT=%b", $time, a, b, EQ, LT, GT);
      #10 a = 00000000;
          b = 00000000;
      #10 a = 10000000;
          b = 00000000;
      #10 a = 00000000;
          b = 10000000;
  end
  endmodule
  </code></pre>