title: RISC-V - Software Interrupts
body: <p>I'm trying to implement a simple interrupt controller for my RV32I core. I believe I understand how an interrupt should be handled in RISC-V, and the role of the CSR registers in the process.</p>
  <p>RISC-V defines three sources of interrupts: External, Software and Timer. I understand how a timer and an external interrupt would generate. However, I do not understand how or what would generate a software interrupt. An instruction? A sequence of instructions? Maybe implementation defined flags? I have no idea.</p>
  <p>Could anyone give an example and the explanation of a software interrupt, preferably with the associated assembly code if it is relevant?</p>
  <p>Thanks in advance!</p>