title: Clock period in Verilog HDL always block
body: <p>This is from Cavanagh's Verilog HDL: Digital Design and Modeling.</p>
  
  <pre><code>//clock generation using initial and always statements
  
  module clk_gen2 (clk);
  
  output clk;
  reg clk;
  
  //initialize clock to 0
  initial
      clk = 1'b0;
  
  //toggle clock every 10 time units
  always
      #10 clk =~ clk;
  
  //determine length of simulation
  initial
      #100 $finish;
  
  endmodule
  </code></pre>
  
  <p>A part of its explanation says that</p>
  
  <blockquote>
    <p>[...] the always statement cycles the clock every 10 time units for a clock period of 20 time units.</p>
  </blockquote>
  
  <p>I got lost at 20 time units. Where did that come from?</p>