title: Variable length std_logic_vector initialization in VHDL
body: <p>I have a variable length vector <code>std_logic_vector(X downto 0)</code>. Now I'm trying to define a constant in my package for reset, such that the lower <code>X/2</code> bits are ones, and the others zero.</p>
  
  <p>For example, a 3 bit vector (<code>X=3</code>) would make the constant <code>"011"</code> and a 4 bit vector would give the constant <code>"0011"</code>.</p>
  
  <p>How can I do this in a VHDL package? 
  The code below explains what I am trying to do.</p>
  
  <pre><code>type Entry_Type is record
    state : std_logic_vector(X-1 downto 0);
  end record;
  constant Entry_Constant : Entry_Type := &lt;???&gt;;
  </code></pre>