title: Detect changes in std_logic vhdl
body: <p>I am trying to detect changes in the input signals of my Selector. When I find the first input that changed (either rising or falling edge), I give an index as output. When I try to synthesize my source code, I get an error "unsupported Clock statement". A also tried to use "rising_edge" and "falling_edge", but I got the same error.
  Here is my code</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  
  entity Selector is
  port (
  X1:  in std_logic;
  X2:  in std_logic;
  X3:  in std_logic;
  X4:  in std_logic;
  X5:  in std_logic;
  X6:  in std_logic;
  O:       out std_logic_vector(2 downto 0)
  );
  end Selector;
  
  
  architecture behave of Selector is
  begin
  process(X1,X2,X3,X4,X5,X6)
  begin
      if (X1'event) then
              O &lt;= "000";
      elsif (X2'event) then
              O &lt;= "001";
      elsif (X3'event) then
              O &lt;= "010";
      elsif (X4'event) then
              O &lt;= "011";
      elsif (X5'event) then
              O &lt;= "100";
      elsif (X6'event) then
              O &lt;= "101";
      else
              O &lt;= "000";
      end if;
  end process;
  end behave;
  </code></pre>
  
  <p>Is there an alternative solution for that?</p>