title: VHDL what does this mean? a <= a (6 downto 0) & '0'
body: <pre><code>signal a : std_logic_vector (7 downto 0) := (others =&gt; '0');
  
  a &lt;= a (6 downto 0) &amp; '0';
  </code></pre>
  
  <p>So I understand that <code>a</code> is a signal that is 8 bits and all of those bits are 0. Is the next line assigning bits 6 down to 0 to be zero again? </p>