title: Adding Even Parity bit and 2 stop bits to a 8 bits std_logic_vector
body: <p>Here is the code: In this the calculation for the parity bit is not done. Parity bit can be calculated using the for loop but is there any other short or better way to calculate the even parity bit in this context. 
  Is it somehow possible to use arrays instead of 8 TxDataReg std_logic_vector considering that after making arrays I wish to access bit by bit the array of 8 signals of 8 bits, bit by bit for sending the data in the uart_tx port? </p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  use IEEE.STD_LOGIC_SIGNED.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.NUMERIC_STD.ALL;
  
  entity Uart_tx is
      Port ( 
              tx_clk_in    : in  STD_LOGIC;
              reset        : in  STD_LOGIC;
              tx           : out STD_LOGIC;
              Rx_Data_in   : in  STD_LOGIC_VECTOR(63 downto 0)
  
            );
  end Uart_tx;
  
  architecture Behavioral of Uart_tx is   
  
  signal  Tx_Data      : STD_LOGIC_VECTOR(63 downto 0)    := "00000000";
  
  signal DataByteArray1 : std_logic_vector(7 downto 0) := (others =&gt; "00000000");
  signal DataByteArray2 : std_logic_vector(7 downto 0) := (others =&gt; "00000000");
  signal DataByteArray3 : std_logic_vector(7 downto 0) := (others =&gt; "00000000");
  signal DataByteArray4 : std_logic_vector(7 downto 0) := (others =&gt; "00000000");
  signal DataByteArray5 : std_logic_vector(7 downto 0) := (others =&gt; "00000000");
  signal DataByteArray6 : std_logic_vector(7 downto 0) := (others =&gt; "00000000");
  signal DataByteArray7 : std_logic_vector(7 downto 0) := (others =&gt; "00000000");
  signal DataByteArray8 : std_logic_vector(7 downto 0) := (others =&gt; "00000000");
  
  signal TxDataReg1 : std_logic_vector(10 downto 0) := (others =&gt; "00000000");
  signal TxDataReg2 : std_logic_vector(10 downto 0) := (others =&gt; "00000000");
  signal TxDataReg3 : std_logic_vector(10 downto 0) := (others =&gt; "00000000");
  signal TxDataReg4 : std_logic_vector(10 downto 0) := (others =&gt; "00000000");
  signal TxDataReg5 : std_logic_vector(10 downto 0) := (others =&gt; "00000000");
  signal TxDataReg6 : std_logic_vector(10 downto 0) := (others =&gt; "00000000");
  signal TxDataReg7 : std_logic_vector(10 downto 0) := (others =&gt; "00000000");
  signal TxDataReg8 : std_logic_vector(10 downto 0) := (others =&gt; "00000000");
  
  
  signal count : unsigned(2 downto 0) := (others =&gt; '0');
  signal one_bit : std_logic := '0';
  
  begin
  
  Tx_Data &lt;= Rx_Data_in;
  
  DataByteArray1 &lt;= Rx_Data_in(7 downto 0);
  DataByteArray2 &lt;= Rx_Data_in(15 downto 8);
  DataByteArray3 &lt;= Rx_Data_in(23 downto 16);
  DataByteArray4 &lt;= Rx_Data_in(31 downto 24);
  DataByteArray5 &lt;= Rx_Data_in(39 downto 32);
  DataByteArray6 &lt;= Rx_Data_in(47 downto 40);
  DataByteArray7 &lt;= Rx_Data_in(55 downto 48);
  DataByteArray8 &lt;= Rx_Data_in(63 downto 56);
  
  
  
  Process (tx_clk_in)
  begin 
  
  -- Calculate the parity bit 
  for i in 0 to 7 loop 
  
  one_bit = DataByteArray1(i);
  if one_bit = '1' then 
  count = count + 1;
  end if;
  end loop;
  -- For all the registers,one even parity &amp; two stop bits I am trying to add in the end
  if count mod 2 = 0 then 
  TxDataReg1 &lt;= DataByteArray1&amp;'0'&amp;'11';  -- I am not so sure that this works or not
  count &lt;= "000";
  else 
  TxDataReg1 &lt;= DataByteArray1&amp;'1'&amp;'11';
  count &lt;= "000";
  end if;
  
  -- Send the uart data from TxDataReg1,TxDataReg2 ...
  -- etc.
  end process;
  end behavioral;
  </code></pre>