title: Difference of SystemVerilog data types (reg, logic, bit)
body: <p>There are different data types in systemverilog that can be used like the following:</p>
  
  <pre><code>reg [31:0] data;
  logic [31:0] data;
  bit [31:0] data;
  </code></pre>
  
  <p>How does the three of them differ?</p>