title: Gate and Switch delay statements in real time or clock cycles (Verilog)?
body: <p>I've been reading through a <a href="http://www.ece.umd.edu/courses/enee359a/verilog_tutorial.pdf#page=55" rel="nofollow">nice tutorial</a> and have a quick question concerning something on pages 55-56. I'll just drag n drop the text below:</p>
  
  <pre><code>Gate and Switch delays
  In real circuits, logic gates have delays associated with them. Verilog provides the
  mechanism to associate delays with gates.
  
    *Rise, fall and Turn-off delays
    *Minimal, Typical, and Maximum delays.
  
  Rise Delay
    The rise delay is ... etc
  
  Min value
    The min value is the minimum delay value that the gate is expected to have.
  
  Typ Value
    ... similar to min value
  
  Max Value
    ... similar to min value
  </code></pre>
  
  <p>Question:</p>
  
  <p>So referring to the explanation for Min value (and Typ and Max alike), would one set the min value to a number of clock cycles (therefore integer value) or an actual real value like 10ns? Can I do both (choosing one or the other)?</p>
  
  <p>Thanks!</p>