title: Multiple Interrupt Senders in one peripheral in Qsys
body: <p>Using Qsys (Quartus II x64 15.0.1 build 150) I made a system with Nios2/e and several standard peripheral components. I also add my custom component with 1 MM-Slave and 2 Interrupt Senders. For each of them I set this slave as "Associated addressable interface" in Component editor during creation of _hw.tcl file.</p>
  
  <p>Qsys reports no errors or warnings, but then I tried to make BSP project in Eclipse using New | Nios 2 BSP project wizard. I select "SOPC Information File name", but "CPU" ComboBox remains empty and error appears: "No Nios II CPU Found". </p>
  
  <p>Then I launch BSP Editor from main menu: Nios 2 | BSP Editor and press File | New Nios 2 BSP. I again provide SOPC file and this tool found CPU, but also reports the error: "Can only have at most one IRQ associated with the following slaves of module "my_component" :  mm_slave."</p>
  
  <p>I then returned to Qsys and remove one of Interrupt Senders and this time everything works fine, but I need to generate more than one interrupt.</p>
  
  <p>So what to do if you have Nios2/e connected to custom peripheral with 1 MM-Slave and several Interrupt Senders?</p>
  
  <p>I have some ideas but don't like them:</p>
  
  <ol>
  <li><p>Add MM-Slave for each irq (it looks like waste of resources).</p></li>
  <li><p>Do not specify "Associated addressable interface" in Component editor (it is by the way works, but I don't know will it work properly all the time). What this option really do?
  <em>I was imprecise saying that it will work, sorry for that. In reality qsys and BSP can be generated but inside BSP's system.h IRQ number will be defined as -1, so it will not work.</em></p></li>
  <li><p>Merge all interrupts into one wire (they all will share the same priority).</p></li>
  <li><p>Configure Interrupt Sender to have irq signal with width more than 1 (Component Editors allows to do this but reports warning: "interrupt_sender: Signal irq_many[4] of type irq must have width [1]".) As with case 2 I don't know what will happen inside Altera's generators/compilers.
  <em>After Component Editor stage is finished Qsys doesn't accept such a system.</em></p></li>
  </ol>
  
  <p>Please help.</p>