title: calculate (and validate) ethernet FCS (crc32) in vhdl
body: <p>I'm using the <a href="http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,792&amp;Prod=S3EBOARD" rel="nofollow">Spartan 3E Starter Kit</a> and I'm trying to receive Ethernet frames on it via a 100 MBit link.</p>
  
  <p>For those who don't know, the board features a PHY chip, exposing the receiving clock with 25 MHz. I have (pretty much) verified that receiving works fine by buffering the received frames and resending them via a serial link.</p>
  
  <p>Furthermore, I'm using a <a href="http://outputlogic.com/?page_id=321" rel="nofollow">CRC32 generator from outputlogic.com</a>. I aggregate the received nybbles to bytes and forward them to the CRC. At the end of the frame, I latch the generated CRC and display it on the LCD, together with the CRC I found in the ethernet frame.</p>
  
  <p>However, (as you might have guessed) the two numbers do not match.</p>
  
  <pre><code>527edb0d  -- FCS extracted from the frame
  43a4d833  -- calculated using the CRC32 generator
  </code></pre>
  
  <p>The first one can also be verified by running the package through pythons crc32 function, both with the frame captured by wireshark and the frame captured and retrieved via serial port from the FPGA.</p>
  
  <p>I guess it must be something more or less trivial. <a href="http://pastebin.com/XnP9CS1c" rel="nofollow">I pasted the receiving process over here</a>. I stripped off everything which was not neccessary. When capturing the output via serial, I added a fifo (readily made unit from Xilinx) which latched at the same time as the CRC generator to get exactly the same bytes.</p>
  
  <p>Does anyone have an idea what's wrong with that?</p>