title: Why 'make' always rebuilds the target?
body: <p>My Makefile is:</p>
  
  <pre><code>OBJS = b.o c.o a.o
  FLAGS = -Wall -Werror
  CC = gcc
  
  test: $(OBJS)
      $(CC) $(FLAGS) $(OBJS) -o test
  b.o: b.c b.h
      $(CC) $(FLAGS) -c b.c
  a.o: a.c b.h c.h
      $(CC) $(FLAGS) -c a.c
  c.o: c.c c.h
      $(CC) $(FLAGS) -c c.c
  clean:
      rm a
      rm *.o
  all: test
  </code></pre>
  
  <p>If I do <code>make</code> then <code>make</code> again, it always rebuilds 'test'.  Why does it do this?</p>
  
  <p>Even if i do: <code>make a.o</code> it rebuilds... Im on linux if that helps.</p>
  
  <p>In windows if I change 'test' by 'test.exe' and '-o test' by '-o test.exe', it works fine.
  So I guess that for some reason 'make' in my linux cant check the datestamps of my files in the directory.</p>
  
  <p>I FIXED IT!
  The .c were created in Windows. I opened all .c and .h in vi, and without doing nothing save changes, and all worked. I think that the datestamp thing was fixed doing this.</p>