title: Others => '1' statement in Verilog
body: <p>I have used VHDL all my life and only been using Verilog for a short time, I have to create a logic in Verilog for a very large array and assign it to 1 or 0 depending on the condition of an input. </p>
  
  <p>Here is my VHDL code</p>
  
  <pre><code> if (data_track == '1' ) then
              my_array(MAX-1:MIN) &lt;= (others=&gt; '1');
   else
              my_array(MAX-1:MIN) &lt;= (others=&gt; '0');
   end if;
  </code></pre>
  
  <p>MAX and MIN are parameters for the block, set during the synthesis depending on the type of system we are accessing.</p>
  
  <p>Is there a way to do this in Verilog easily? </p>