title: system verilog bind used together with interface
body: <p>I defined an interface in system verilog and use bind statement to bind to internal RTL signals. I want to be able to force internal RTL signals through the interface. However, this is causing the RTL signal to go to 'x' if I don't force these signals explicitly, it seems bind to interface is having driving capability. I don't want RTL signal to change to 'x' when nothing is forcing it in this case, not sure what I am doing wrong here?</p>
  
  <p>my code looks like this with DUT being the design:</p>
  
  <pre><code>interface myInf(
     inout RTL_a,
     inout RTL_b 
  );
  
  bind DUT myInf myInf_inst(
     .RTL_a(DUT.a),
     .RTL_b(DUT.b)
  );
  
  bind DUT myDrv(myInf_inst);
  </code></pre>
  
  <p>where myDrv is a module which drives the ports on myInf.</p>
  
  <p>In this case, DUT.a and DUT.b are internal RTL signals, they have their driver from design, but I want to be able to force them if needed. however, these signals becoming 'x' when I am just binding them to myInf without actually driving them.</p>