title: How to assign a value to simulation time in system verilog
body: <p>I have a file with transactions, each has a time when it occurred.
  I want to run a SystemVerilog simulation, and "play" each transaction on its time </p>
  
  <p>However, I don't want to actually wait the clock cycles between the transactions. 
  Instead I want to assign transaction time (from the file) to the SystemVerilog simulation time (assignment should occur within 0 time).</p>
  
  <p>Is it possible to advance System Verilog simulation time this way ?
  If so - how ?</p>
  
  <p>Simplified version of the file :</p>
  
  <pre><code>TIME (ns)    |   TRANSACTION DATA   
      1        |     0x1, 0x2, 0x3
      5        |     0x4, 0x5, 0x6
     200       |     0xa, 0xb, 0xc
    10000      |     0xd, 0xe, 0xf
  </code></pre>
  
  <p>Thanks.
  Roi.</p>