title: Verilog Error: Must be connected to a structural net expression
body: <p>I'm getting the error: <code>output or inout port "Qout" must be connected to a structural net expression</code>. I commented the line the error occured in the below code (code is trimmed/condensed). I searched for an answer and it seems I can't assign a input/output port to a reg. I think one solution is to change Q to a wire, but Q is part of an always-block in my eightBitRegister module, so it must be a reg. How can I get around this error?</p>
  
  <pre><code>`timescale 1ns / 1ns
  
  module lab4_3(SW, KEY, LEDR);
      input [9:0] SW;
      input [3:0] KEY; 
      output [7:0] LEDR;
  
      eightBitRegister eight1(
                  .DATA_IN(SW[7:0]),
                  .parallelloadn(KEY[1]),
                  .rotateRight(KEY[2]),
                  .clock(KEY[0]),
                  .reset(SW[9]),
                  .Q(LEDR[7:0])       
      );      
  endmodule
  
  module eightBitRegister(DATA_IN, parallelloadn, rotateRight, reset, clock, Q);
      input [7:0] DATA_IN;
      input parallelloadn;
      input rotateRight;
      input reset;
      input clock;
      output[7:0] Q;
  
  
      register reg0(.Qout(Q[0]),  //GETTING ERROR HERE
                  .right(Q[1]),
                  .left(Q[7]),
                  .D(DATA_IN[0]),
                  .loadleft(rotateRight),
                  .loadn(parallelloadn),
                  .clk(clock),
                  .rst(reset));
  
     reg [7:0] Q;
      always @(*)
      begin
       case({parallelloadn,rotateRight})
          2'b00: Q = DATA_IN; 
          2'b01: Q = DATA_IN;  
          2'b11: Q = Q &gt;&gt; 1;
          2'b10: Q = Q &lt;&lt; 1;
       endcase
      end
  
  endmodule
  
  module register(Qout, right, left, D, loadleft, loadn, clk, rst);
      input right, left;
      input D;
      wire datato_dff, rotatedata;
      input loadleft, loadn;
      input clk, rst;
      output Qout;
  
  flipflop F0( 
      .d(datato_dff), 
      .q(Qout), 
      .clock(clk),
      .reset(rst) 
  );
  
  module flipflop(d, q, reset, clock); 
      input reset, clock;
      input d;
      output q;
      reg q;
      always @(posedge clock)
      begin
          if (reset == 1'b0) 
              q &lt;= 0; 
          else 
              q &lt;= d; 
      end
  
  endmodule
  </code></pre>