title: ARM bare-metal with MMU: write to non-cachable,non-bufferable mapped area fail
body: <p>I am ARM Cortex A9 CPU with 2 cores. But I just use 1 core and the other is just in a busy loop. I setup the MMU table using section (1MB per entry) like this:</p>
  
  <pre><code>0x00000000-0x14ffffff =&gt; 0x00000000-0x14ffffff (non-cachable, non-bufferable)
  0x15000000-0x24ffffff =&gt; 0x15000000-0x24ffffff (cachable, bufferable)
  0x25000000-0x94ffffff =&gt; 0x25000000-0x94ffffff (non-cachable, non-bufferable)
  0x15000000-0x24ffffff =&gt; 0x95000000-0xa4ffffff (non-cachable, non-bufferable)
  0xa5000000-0xffffffff =&gt; 0xa5000000-0xffffffff (non-cachable, non-bufferable)
  </code></pre>
  
  <p>It is rather simple. I just want to have a mirror of 256MB memory for non-cachable access. However, when I do several write to the the non-cachable memory section at 0x95000000-0xa4ffffff. I find the write is not actually written until I explicitly give a cache flush.</p>
  
  <p>Am I doing something wrong or this kind of mapping is not valid? If that is the case, I don't understand how Linux's ioremap will be working on ARM. It will be good if anyone can give some explanation to me. Thanks very much.</p>