title: How to reuse an instantiated module in verilog with updated inputs
body: <p>I have a module :</p>
  
  <pre><code>module abc(
    input  in1,
    input  in2,
    output in3
  );
  </code></pre>
  
  <p>Instantiating this module in another main module:</p>
  
  <pre><code>abc name_abc(in1, in2, out);
  </code></pre>
  
  <p>Now in1 is changed based on some other signal. From what I understand, the instantiation would have created a block of the logic, now I want to use the block already created but with different inputs or updated inputs. Is there a way to do this in verilog?</p>
  
  <p>What I want to do is :</p>
  
  <pre><code>abc name_abc(in1_updated, in2, out);
  </code></pre>