title: What is the memory map section in RISCV
body: <p>I'm familiar with MIPS architecture, and I've known that MIPS has memory section such as kseg0, kseg1. Which determine whether the segment can be cached or mapped. For example, you should locate some I/O devices(like UART) to the uncached segment.</p>
  
  <p>But I didn't find anything related in RISCV arch. So how does the RISCV OS know the address should be mapped or not? </p>
  
  <p>By the way: I know the value in satp CSR desrcibes the translation mode. When OS is running, the value must set other than "Bare(disabled MMU)" so that the OS can support the virtual memory. So if CPU access UART address, the value in satp is still not "Bare"? But it should be "Bare"?</p>