title: LLVM scheduling to prevent data hazards
body: <p>I'm trying to add scheduling to my backend in llvm to prevent data hazards. The backend is very similar to microblaze but with a lot of differences such as multiple delay slots for branching delays. Currently, each time llvm compiles code I always find data hazards especially for load and store instructions.
  I've looked at PPC and ARM backend scheduling but I couldn't figure out how to adapt it so I would like to make my own instead.
  I'd like to know how to get a list of the compiled instructions from llvm during the compilation process to sort the instructions and check for dependencies based on registers used.</p>
  
  <p>I'm currently clueless on this since I'm not a skilled C++ programmer. The CPU is pipelined and only has control hazards (branching) and data hazards.
  The CPU has 5 stages in pipeline but only instructions in stage 3 and 5 are able to use data from stage 1.
  I've setting latencies for my backend and it doesnt change anything.</p>