title: template error in Xilinx
body: <p>I have written a program in xilinx, this code compiles fine in <code>ModelSim</code> but I get this error when I compile it in xilinx.</p>
  
  <p><code>ERROR:Xst:899 -  line 78: The logic for &lt;iterator&gt; does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
  </code></p>
  
  <p>I don't know why I am getting this error. Here is the code:</p>
  
  <pre><code>module BcdCounter( input clk,input reset, output reg [3:0]out
  );
  
  reg [23:0]iterator;
  
  always @(posedge clk,negedge reset)
  begin
  
  if(~reset)
  begin
  
  out=0;
  iterator=0;
  
  end
  
  else
  // clock divider
  if(iterator==50000000) // 50Mhz clock divider
  begin
  
  out&lt;=out+1;
  iterator=0;
  
  end
  
  iterator=iterator+1;
  
  end
  
  
  endmodule
  </code></pre>
  
  <p>Regards</p>