title: specifying the filename in a makefile
body: <p>I'm new to this and trying to create a makefile where I could, for example, run:</p>
  
  <pre><code>make -f mymakefile testfile
  </code></pre>
  
  <p>and the makefile would find testfile.java (which exists in the directory I'm running from), compile it, and run the code. </p>
  
  <p>Instead, I must be confused with how automatic variables work and after working all afternoon I still get the error: </p>
  
  <pre><code>make: Nothing to be done for `testfile'.
  </code></pre>
  
  <p>Any help would be appreciated and my code is below:</p>
  
  <pre><code>JC=javac
  JVM=java
  JFLAGS= -g
  RM = rm -f
  CFLAGS =
  CXX = gcc
  NAME = *
  .SUFFIXES: .java .class
  
  all: run
  
  NAME: 
          $(CXX) $(CFLAGS) -o $^ $@
          echo $(NAME)
  
  $(NAME).class: $(NAME)
          $(JC) $(JFLAGS) $(NAME).java
  
  run: $(NAME).class
          $(JVM) $(NAME)
  
  .PHONY: clean
  clean:
          $(RM) $(NAME).class
  </code></pre>
  
  <p>I've tried just having it echo 'testfile' to better understand how automatic variables work, but I couldn't get that to work correctly either. </p>