title: inside operator to include every element of systemverilog enum
body: <p>Is there a way to use <code>inside</code> operator for every element of <code>enum</code>?
  for e.g. I've the following <code>enum</code>:</p>
  
  <pre><code>typedef enum {ADD, SUB, MUL, DIV, MOD} Instr_t;
  </code></pre>
  
  <p>While writing constraints or checking if received <code>opcode</code> is any one of the valid Instructions, is there an easier way
  I've tried the following:</p>
  
  <pre><code>if (opcode inside {Instr_t})
  </code></pre>
  
  <p>This fails and I need to use expanded <code>enum</code>:</p>
  
  <pre><code>if (opcode inside {ADD, SUB, MUL, DIV, MOD})
  </code></pre>
  
  <p>This is easy when <code>enum</code> is small but gets annoying with bigger <code>enum</code>, other way I could think is using <code>define</code>.</p>