title: 8 bit accumulator in verilog, output data type
body: <p>Here is my verilog code, and I keep getting the error where I have to connect my outputs(s and carry) to structural net expression. Here's the code:</p>
  
  <pre><code>module p2(SW,KEY0,KEY1,LEDR,HEX0,HEX1,HEX2);
   input [7:0] SW;
   input [7:0] LEDR;
   input KEY1,KEY0;
  
   output[6:0] HEX0,HEX1,HEX2;
  
   reg[7:0] s;
   reg carry;
  
   accumulator acm (SW[7:0],s,carry,KEY0,KEY1);
  
  endmodule 
  
  module accumulator (A, accum,overflow, clk, clr);
  
   input [7:0] A;
   input clk, clr;
   output [7:0] accum;
   output reg overflow;
  
   reg [7:0] accum;
  
   always@(clk) begin
      if(clk) begin
          {overflow,accum} &lt;= accum + A;
      end
      else if(~clr) begin
          accum = 8'b00000000;
      end
  end
  
  endmodule
  </code></pre>