title: SystemVerilog task that can force any signal in interface module
body: <pre><code>interface dut_if();
      logic       sig_a_i;
      logic [1:0] sig_b_i;
  endinterface
  
  module tb();
      dut_top dut(
          .sig_a_i  (vif.sig_a_i);
          .sig_b_i  (vif.sig_b_i);
      );
  
      dut_if vif();
  endmodule
  </code></pre>
  
  <p>How to create a <code>task()</code> method inside the <code>interface</code> class such that I can easily call it within my <code>test</code> class to <code>force</code>/<code>release</code> any DUT signal I like?</p>
  
  <pre><code>class dut_testA_vseq extends dut_base_vseq;
      ...
  
      virtual task body();
          p_sequencer.vif.force_dut_signal(0);
      endtask
  endclass
  </code></pre>
  
  <p>I'm new to SV and I don't know how to write <code>force_dut_signal()</code> that can cater to any signal (single bit or a bus).</p>
  
  <pre><code>task force_dut_signal(logic? port_name, bit? force_val) begin
      force port_name? = force_val;
  endtask
  </code></pre>
  
  <p>The <code>?</code> in the code snippet above are parts I don't know if possible or what.</p>
  
  <p>Thanks in advance!</p>