title: Syntax Error on '='
body: <p>I have the following Verilog HDL code. It is basically a two-bit adder that adds <code>a</code> and <code>b</code>, and has a PG unit, Carry-generate unit (<code>cg_unit</code>), and Sum unit (<code>s_unit</code>). The <code>ci</code> is the carry-in for the two-bit adder. <code>sel</code> is what activates the trojan, i.e. negates the value of <code>s[1]</code>. <code>coutminus1</code> and <code>cout</code> are simply the carry-out and the carry previous to the carryout, respectively.</p>
  
  <pre><code>module trojan
  (
    input [1:0] a, b,
    input ci, sel,
    output [1:0] s,
    output cout, coutminus1
  );
  
    wire [1:0] c, p, g;
    cla_pg_unit_2bits       pgu1(a, b, p, g);
    cla_cg_unit_2bits       cgu1(p, g, ci, c);
    cla_s_unit_2bits        su1(p, {c[0], ci}, s);
    coutminus1 = c[0];
    cout = c[1];
  
    always@(sel)
    begin
      if (sel == 1)
        assign s[1] = ~s[1];
      else
        assign s[1] = s[1];
    end
  endmodule
  </code></pre>
  
  <p>For some reason I get the following syntax error:</p>
  
  <pre><code>Following Verilog source has the following syntax error: token is '=' 
  coutminus1 = c[0];
             ^
  </code></pre>