title: Why is the wired or signal type (wor) disallowed for typedefs in SystemVerilog
body: <p>In SystemVerilog I CAN do</p>
  <pre><code>typedef logic [15:0] bus16;
  typedef reg [15:0] reg16;
  
  interface myif;
     bus16 mybus;
     wor [15:0] myotherbus;
  endinterface
  
  </code></pre>
  <p>But I CAN'T do</p>
  <pre><code>typedef wor [15:0] wor16;
  
  interface myif;
     wor16 myotherbus;
  endinterface
  
  </code></pre>
  <p>I get &quot;unknown variable declaration type&quot;</p>
  <p>It seems, at least in my Synplicity version, typedefs of 'wor' is not permitted.</p>
  <p>Is this a limitation defined in the IEEE1800 spec or is it perhaps a bug?</p>