title: Creating a JK Flip Flop module using an SR Flip Flop Module in Verilog
body: <p>I have written verilog modules for SR Latch, SR Flip Flop (by instantiating the SR Latch module), and JK Flip Flop (by instantiating the SR Latch module). I'm using Xilinx Vivado 2019 version for simulation and viewing output waveforms. The SR Latch and SR Flip flop modules work just fine and I'm getting the proper output waveforms also. I tried creating a JK Flip Flop Module by instantiating the SR Latch Module. But I just don't get the output waveforms. I don't know what is going wrong. I checked the Boolean expressions as well. Everything seems to be fine. Can someone please point out the error?</p>
  
  <p>Here are the codes.</p>
  
  <p><strong>SR Latch Module</strong></p>
  
  <pre><code>module sr_latch(s, r, q, qbar);
      input s, r;
      output q, qbar;
      nand(q, s, qbar);
      nand(qbar, r, q);
  endmodule
  </code></pre>
  
  <p><strong>SR Flip Flop Module using the SR Latch</strong></p>
  
  <pre><code>module sr_ff(s, r, clk, q, qbar);
      input s, r, clk;
      output q, qbar;
      reg t1, t2;
      always @(posedge clk)
          begin
              t1 &lt;= !(clk &amp; s);
              t2 &lt;= !(clk &amp; r);
          end
      sr_latch SRL(t1, t2, q, qbar);
  endmodule
  </code></pre>
  
  <p><strong>JK Flip Flop using SR Latch</strong></p>
  
  <pre><code>module jk_ff(j, k, clk, q, qbar);
      input j, k, clk;
      output q, qbar;
      reg t1, t2;
      always @(posedge clk)
          begin
              t1 &lt;= !(clk &amp; qbar &amp; j);
              t2 &lt;= !(clk &amp; q &amp; k);
          end
      sr_latch SRL(t2, t1, q, qbar);
  endmodule
  </code></pre>
  
  <p><strong>JK Flip Flop Testbench</strong></p>
  
  <pre><code>module jk_ff_tb();
      wire q, qbar;
      reg j, k, clk=1;
      integer i;
      jk_ff JKFF(j, k, clk, q, qbar);
      always #25 clk = !clk;
  
      initial
          begin
              for(i=0; i&lt;4; i=i+1)
                  begin
                      {j, k} &lt;= i; #50;
                  end
          $stop;
          end
  endmodule
  </code></pre>