title: What is the difference between the using force and without force in the forcing the signal in verilog?
body: <p>What is the difference between the using force and without force in the forcing the signal in verilog?</p>
  
  <p>here is a sample verilog </p>
  
  <pre><code>top();
  
  wire temp;
  reg temp2;
  
  endmodule
  </code></pre>
  
  <p>And I want to force that temp and temp2 signals as below.</p>
  
  <h1>case 1</h1>
  
  <pre><code>top();
  
  wire temp;
  reg temp2;
  
  initial begin
   top.temp = 1'b1;    
   top.temp2 = 1'b1;
  end
  
  endmodule
  </code></pre>
  
  <p>in this case, I've got some error like this.</p>
  
  <p>top.slwr_w = 1'b1;
           |
  ncvlog: *E,WANOTL : A net is not a legal lvalue in this context [9.3.1(IEEE)].</p>
  
  <p>If I want to use like this manner without 'force'
  Should I have to force only 'reg' not 'wire'?
  What am I supposed to do that if I want to force to wire without force?</p>
  
  <h1>case 2</h1>
  
  <pre><code>top();
  
  wire temp;
  reg temp2;
  
  initial begin
   force     top.temp = 1'b1;    
   force     top.temp2 = 1'b1;
  end
  
  endmodule
  </code></pre>
  
  <p>in this case, there is no error what I used with 'force'.</p>
  
  <p>Q1.Firstly, I want to know what is the  difference between case1 and case2 as force manner?</p>
  
  <p>Q2.and which case is the good manner?</p>