title: VHDL: Type of "variable" is incompatible with type of <=
body: <p>Could some explain why i get syntax error with this piece of code..</p>
  
  <pre><code>An &lt;= "1110" when anode = "00" else
  AN &lt;= "1101" when anode = "01" else
  An &lt;= "1011" when anode = "10" else 
  An &lt;= "0111" when anode = "11";
  
  segment &lt;= counter_1r    when anode = "00" else
  segment &lt;= counter_10r   when anode = "01" else
  segment &lt;= counter_100r  when anode = "10" else
  segment &lt;= counter_1000r When anode = "11";
  </code></pre>
  
  <p>it says </p>
  
  <pre><code>ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 181. Type of An is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 182. Type of An is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 183. Type of An is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 181. Type of An is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 182. Type of An is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 183. Type of An is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 186. Type of segment is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 187. Type of segment is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 188. Type of segment is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 186. Type of segment is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 187. Type of segment is incompatible with type of &lt;=.
  ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 188. Type of segment is incompatible with type of &lt;=.
  </code></pre>
  
  <p>Which i Don't understand, because In my code i've set all the affected element in my entity to be output, they are all using the same type. </p>
  
  <pre><code>PORT(
      CLK: in std_logic;
  --  LED: out std_logic_vector (7 downto 0);
  --  Switch: in std_logic_vector(7 downto 0);
      Segment: out std_logic_vector (7 downto 0); 
      AN: out std_logic_vector (3 downto 0) 
  );
  end Main;
  
  architecture Behavioral of Main is
      signal counter_1000:  integer range 0 to 9;
      signal counter_100:   integer range 0 to 9;
      signal counter_10:    integer range 0 to 9;
      signal counter_1:     integer range 0 to 9;
      signal counter_1r:    std_logic_vector(7 downto 0);
      signal counter_10r:   std_logic_vector(7 downto 0);
      signal counter_100r:  std_logic_vector(7 downto 0);
      signal counter_1000r: std_logic_vector(7 downto 0);
      signal prescaler:     integer range 0 to 50000000;
      signal limit:         integer range 0 to 50000000;
      signal Anode:         std_logic_vector(1 downto 0);
  begin
  </code></pre>