title: Can a constant expression ever be valid in a VHDL case statement?
body: <p>I recall that in Verilog it can be valid to use a constant in the expression of a case statement, but is it also valid in VHDL?</p>
  
  <pre><code>// Verilog example
  case(1'b1)                                
    A[2]:   Y&lt;=2'b11;  
    A[1]:   Y&lt;=2'b10;  
    A[0]:   Y&lt;=2'b01;  
    default:Y&lt;=2'b00;
  endcase
  </code></pre>