title: Functions in Makefile
body: <p>I am writing a Makefile with a lot of repetitive stuff, e.g.</p>
  
  <pre><code>debug_ifort_Linux:
          if [ $(UNAME) = Linux ]; then                           \
            $(MAKE) FC=ifort FFLAGS=$(difort) PETSC_FFLAGS="..."  \
                    TARGET=$@ LEXT="ifort_$(UNAME)" -e syst;      \
          else                                                    \
            echo $(err_arch);                                     \
            exit 1;                                               \
          fi
  </code></pre>
  
  <p>where the target 'syst' is defined, the variable 'UNAME' is defined (and is usually Linux, but might also by Cygwin or OSF1) and the variables 'difort' and 'err_arch' are also defined. This block of code is used very many times for different compiler targets (using a name convention of '<em></em>'). Since this is a huge amount of redundant code, I would like to be able to write it in a more simple manner. E.g., I would like to do something like this:</p>
  
  <pre><code>debug_ifort_Linux:
          compile(uname,compiler,flags,petsc_flags,target,lext)
  </code></pre>
  
  <p>where compile could be a function doing the code above based on the arguments. Does anyone have any idea how I could accomplish this?</p>