title: Place and route timing strategy
body: <p>This sounds very naive, but i would like your expert comments on the below pseudo-code. Which of the 2 methods below can achieve minimal place &amp; route timing when implemented in hardware.</p>
  
  <p><strong><em>Method:1</em></strong></p>
  
  <pre><code>control_proc: process(clk)
  begin
      if(clk'event and clk=='1') then
          if sig_delay == 1 then
              sig_ctrl &lt;= '1';
          else
              sig_ctrl &lt;= '0';
          end if;
  
      end if;
  end process
  
  
  delay_proc: process(clk)
  begin
      if(clk'event and clk=='1') then
          if &lt;some-condition&gt; then
              sig_delay &lt;= '1';
          else
              sig_delay &lt;= '0';
          end if;
      end if;
  end process
  </code></pre>
  
  <p><strong><em>Method:2</em></strong></p>
  
  <pre><code>control_single_proc: process(clk)
  begin
      if(clk'event and clk=='1') then
          if &lt;some-condition&gt; then
              sig_delay &lt;= '1';
          else
              sig_delay &lt;= '0';
          end if;
  
          if sig_delay == 1 then
              sig_ctrl &lt;= '1';
          else
              sig_ctrl &lt;= '0';
          end if;
  
      end if;
  end process
  </code></pre>
  
  <p>Note:
  sig_ctrl is used as a CE (chip enable) for another component in the hierarchy, which is kind of bit serialiser.</p>