title: How does SystemVerilog handle possible wildcard conflicts in case statements?
body: <p>When I write a case statement that includes wildcards for the cases, how are more or less specific cases handled?</p>
  
  <pre><code>always_comb case(selector)
      4'b0???: begin // Pick me if the msb is 0, unless the two lsb's are 01.
      end
      4'b0?01: begin // Pick me if the msb is 0 and the two lsb's are 01.
      end
      default: begin // Pick me if the msb is X or 1.
      end
  endcase
  </code></pre>
  
  <p>In the simplified example above, the first case (all wildcards) could be selected for any value of selector, but I want it to select the most specific possible case. Is that how cases are handled?</p>