title: VHDL function does not compile
body: <p>I am trying to define a function in VHDL but I get </p>
  
  <blockquote>
    <p>Error: tst.vhd(4): near "subtype": syntax error</p>
  </blockquote>
  
  <p>Here is the code</p>
  
  <pre><code>subtype word10 is bit_vector(9 downto 0);
  subtype word8 is bit_vector(7 downto 0);
  
  function tst (input : in word10) return word10 is
      variable tmp : word10;
      -- code here
      begin
  
      return tmp;
  end tst;
  
  entity tester is
  end;
  
  architecture tst of tester is
  begin
  end;
  </code></pre>
  
  <p>It is the first time I am coding in VHDL and I cant figure out what is the error.</p>
  
  <p>Any ideas?</p>