title: AXI4 (Lite) Narrow Burst vs. Unaligned Burst Clarification/Compatibility
body: <p>I'm currently writing an AXI4 master that is supposed to support AXI4 Lite (AXI4L) as well.</p>
  
  <p>My AXI4 master is receiving data from a 16-bit interface. This is on a Xilinx Spartan 6 FPGA and I plan on using the EDK AXI4 Interconnect IP, which has a minimum WDATA width of 32 bits.</p>
  
  <p>At first I wanted to use narrow burst, i.e. AWSIZE = x"01" (2 bytes in transfer). However, I found that Xilinx' <a href="http://www.xilinx.com/support/documentation/ip_documentation/axi_ref_guide/latest/ug761_axi_reference_guide.pdf" rel="nofollow">AXI Reference Guide UG761</a> states "narrow bursts [are] supported but [...] not recommended." Unaligned transactions are supposed to be supported.</p>
  
  <p>This had me thinking. Say I start an unaligned burst:</p>
  
  <ul>
  <li>AWLEN = x"01" (2 beats)</li>
  <li>AWSIZE = x"02" (4 bytes in transfer")</li>
  </ul>
  
  <p>And do the following:</p>
  
  <pre><code>AX (32-bit word #0: send hi16)
  XB (32-bit word #1: send lo16)
  </code></pre>
  
  <p>Where A, B are my 16 bit words that start off at an unaligned (2-byte aligned) address. X means WSTRB is deasserted for the indicated 16 bit.</p>
  
  <ul>
  <li>Is this supported or does this fall under the category "narrow burst" even through AWSIZE = x"02" (4 bytes in transfer) as opposed to AWSIZE = x"01" (2 bytes in transfer)?</li>
  </ul>
  
  <p>Now, if this was just for AXI4, I would probably not care as much about this use case, because AXI4 peripherals are required to use the WSTRB signals. However, the AXI Reference Guide UG761 states "[AXI4L] Slaves interface can elect to ignore WSTRB (assume all bytes valid)."</p>
  
  <p>I read <a href="http://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-Lite-GPIO-v1-01-b-Support-WSTB/td-p/336967" rel="nofollow">here</a> that many (but not all; and there is not list?) Xilinx AXI4L peripherals do elect to ignore WSTRB.</p>
  
  <ul>
  <li>Does this mean that I'm essentially barred from doing narrow burst ("not recommended") as well as unaligned bursts ("WSTRB can be ignored") or is there an easy way to unload some of the implementation work from my master into the interconnect, <em>guaranteeing</em> proper system behavior when accessing AXI4L peripherals?</li>
  </ul>