title: Overflow in SystemVerilog constraints
body: <p>Integer types in SystemVerilog, as in most languages, wrap around on overflow.  I was wondering if this is also true in constraints.  For example:</p>
  
  <pre><code>class Test;
    rand bit [3:0] a;
    rand bit [3:0] b;
  
    constraint c { a + b &lt;= 4'h6; }
  endclass;
  </code></pre>
  
  <p>When randomizing an object of this class, is it possible to get a solution where <code>a == 7</code> and <code>b == 12</code>, which would satisfy the constraint since 7 + 12 = 19 which wraps around to 3, and 3 is less than 6?</p>
  
  <p>If so, would it help to formulate the constraint as</p>
  
  <pre><code>constraint c { a + b &lt;= 6; }
  </code></pre>
  
  <p>where 6 is a 32-bit signed int and the sum is forced to be calculated with 32-bit precision?  (This of course is not a solution if the random variables are of type <code>int</code>)</p>