title: Atomic Block for reading vs ARM SysTicks
body: <p>I am currently porting my <a href="http://blog.blinkenlight.net/experiments/dcf77/dcf77-library/" rel="nofollow">DCF77 library</a> (you may find the <a href="https://github.com/udoklein/dcf77_library" rel="nofollow">source code at GitHub</a>) from Arduino (AVR based) to Arduino Due (ARM Cortex M3). I am an absolute beginner with the ARM platform.</p>
  
  <p>With the AVR based Arduino I can use <a href="http://www.nongnu.org/avr-libc/user-manual/group__util__atomic.html" rel="nofollow">avr-libc</a> to get atomic blocks. Basically this blocks all interrupts during the block and will allow interrupts later on again. For the AVR this was fine. Now for the ARM Cortex things start to get complicated. </p>
  
  <p>First of all: for the current uses of the library this approach would work as well. So my first question is: is there someting similar to the "ATOMIC" macros of avr-libc for ARM? Obviously other people have thought of <a href="http://www.keil.com/forum/12988/atomic-block-intterupts-proof-on-cortex-m3/" rel="nofollow">something in this directions.</a> Since I am using gcc I could enhance these macors to work almost exactly like the avr-libv ATOMIC macors. I already found some <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABEDCBC.html" rel="nofollow">CMSIS documentation</a> however this seems only to provide an "enable_irq" macro instead of a "restore_irq" macro.</p>
  
  <p>Question 1: is there any library out there (for gcc) that already does this?</p>
  
  <p>Because ARM has different priority interrupts I could establish the atomicity in different ways as well. In my case the "atomic" blocks must only make sure that they are not interrupted by the systick interrupt. So actually I would not need to block everything to make my blocks "atomic enough". Searching further I found an <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/ch01s02s01.html" rel="nofollow">ARM synchronization primitives article in the developer infocenter</a>. Especially there is a hint at <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/ch01s03s04.html" rel="nofollow">lockless programming</a>. According to the article this is an advanced concept and that there are many publications on it. Searching the net I found only general explanations of the concept, e.g. <a href="http://preshing.com/20120612/an-introduction-to-lock-free-programming/" rel="nofollow">here</a>. I assume that a lockless implementation would be very cool but at this time I feel not confident enough on ARM to implement this from scratch.</p>
  
  <p>Question 2: does anyone have some hints for me on lockless reads of memory blocks on ARM Cortex M3?</p>
  
  <p>As I already said I only need to protect the lower priority thread from sysTicks. So another option would be to disable sysTicks briefly. Since I am implementing a timing sensitive clock algorithm this must not slow down the overall sysTick frequency in the long run. Introducing some small jitter would be OK though. At this time I would find this most attractive.</p>
  
  <p>Question 3: is there any good way to block sysTick interrupts without losing any ticks?</p>
  
  <p>I also found the <a href="http://www.keil.com/pack/doc/cmsis/RTOS/html/group___c_m_s_i_s___r_t_o_s___semaphore_mgmt.html" rel="nofollow">CMSIS documentation for semaphores</a>. However I am somewhat overwhelmed. Especially I am wondering if I should use CMSIS and how to do this on an Arduino Due.</p>
  
  <p>Question 4: What would be my best option? Or where should I continue reading?</p>
  
  <p>Partial Answer:
  with the hint from Notlikethat I implemented</p>
  
  <pre><code>#if defined(ARDUINO_ARCH_AVR)
      #include &lt;util/atomic.h&gt;
      #define CRITICAL_SECTION ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
  
  #elif defined(ARDUINO_ARCH_SAM)
      // Workaround as suggested by Stackoverflow user "Notlikethat"
      // http://stackoverflow.com/questions/27998059/atomic-block-for-reading-vs-arm-systicks
  
      static inline int __int_disable_irq(void) {
          int primask;
          asm volatile("mrs %0, PRIMASK\n" : "=r"(primask));
          asm volatile("cpsid i\n");
          return primask &amp; 1;
      }
  
      static inline void __int_restore_irq(int *primask) {
          if (!(*primask)) {
              asm volatile ("" ::: "memory");
              asm volatile("cpsie i\n");
          }
      }
      // This critical section macro borrows heavily from
      // avr-libc util/atomic.h
      // --&gt; http://www.nongnu.org/avr-libc/user-manual/atomic_8h_source.html
      #define CRITICAL_SECTION for (int primask_save __attribute__((__cleanup__(__int_restore_irq))) = __int_disable_irq(), __ToDo = 1; __ToDo; __ToDo = 0)
  
  #else
      #error Unsupported controller architecture
  #endif
  </code></pre>
  
  <p>This macro does more or less what I need. However I find there is room for improvement as this blocks all interrupts although it would be sufficient to block only systicks. So Question 3 is still open.</p>