title: about Synplify VHDL (code imported from Xilinx ISE)
body: <p>I'm start to work with Synopsys Synplify. Import my Xilinx ISE project (fully work). </p>
  
  <p>Try to run and receive - "No matching overload for to_integer" for this line</p>
  
  <pre><code>rgb(7 downto 0) &lt;= color_lut(result_reg(to_integer(unsigned(x(2 downto 0))-1 )));
  </code></pre>
  
  <p>What can I do to adopt this piece for Synplify?</p>