title: How to create derived types of abstract data types in VHDL 2008?
body: <p>Using VHDL 2008 is there a way to define an abstract entity with a generic type that has ports of that type as well as unconstrained arrays or records derived from that base type? Something like this: </p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity COMP_EXCH is
    generic(type T;                             -- VHDL-2008 abstract generic base type
            function "&lt;"(L,R:T) return BOOLEAN; -- VHDL-2008 abstract generic function
            LATENCY:INTEGER:=0);
    port(I0,I1:in T;
         O:out T_VECTOR(0 to 1));
  end COMP_EXCH;
  
  architecture TEST of COMP_EXCH is
  begin
    O&lt;=(I1,I0) when I1&lt;I0 else (I0,I1);
  end TEST;
  </code></pre>
  
  <p>where T_VECTOR is: </p>
  
  <p>type T_VECTOR is array(INTEGER range &lt;>) of T;</p>
  
  <p>and T is an arbitrary abstract base type. The challenge is how to insert the definition of T_VECTOR, which depends on T after the generic where T is introduced but before the port where T_VECTOR is neeeded? How can both types be kept generic and abstract but have one be an unconstrained array of the other? Without abstract types one would use a package to achieve this, which would contain the type definitions of T and T_VECTOR but how can it be done with abstract types in VHDL 2008? </p>
  
  <p>I would like to be able to have a number of derived types like unconstrained arrays, or records (for example a complex record with real and imaginary fileds of type T) still remain abstract and use them to define abstract components like the example above. </p>