title: Can I generate a number of SystemVerilog properties within a loop?
body: <p>I have two packed arrays of signals and I need to create a property and associated assertion for that property that proves that the two arrays are identical under certain conditions.  I am formally verifying and the tool cannot prove both full arrays in a single property, so I need to split it up into individual elements.  So is there a way I can generate a properties for each element of the array using a loop?  At the moment my code is very verbose and hard to navigate.</p>
  
  <p>My code currently looks like this:</p>
  
  <pre><code>...
  property bb_3_4_p; 
    @(posedge clk)
       bb_seq  
       |=&gt;     
       bb_exp [3][4] == bb_rtl [3][4] ;
  endproperty
  
  property bb_3_5_p; 
    @(posedge clk)
       bb_seq  
       |=&gt;     
       bb_exp [3][5] == bb_rtl [3][5] ;
  endproperty
  
  property bb_3_6_p; 
    @(posedge clk)
       bb_seq  
       |=&gt;     
       bb_exp [3][6] == bb_rtl [3][6] ;
  endproperty
  ...
  
  ...
  assert_bb_3_4: assert property (bb_3_4_p);
  assert_bb_3_5: assert property (bb_3_5_p);
  assert_bb_3_6: assert property (bb_3_6_p);
  ...
  </code></pre>
  
  <p>This is sort of how I'd like my code to look like:</p>
  
  <pre><code>for (int i = 0; i &lt; 8; i++) 
    for (int j = 0; j &lt; 8; j++) 
    begin   
       property bb_[i]_[j]_p;
          @(posedge clk)
             bb_seq  
             |=&gt;     
             bb_exp [i][j] == bb_rtl [i][j] ;
       endproperty
       assert_bb_[i]_[j]: assert property (bb_[i]_[j]_p);
    end     
  </code></pre>