title: verilog port mapping syntax error
body: <pre><code>Error-[SE] Syntax error
        Following verilog source has syntax error :
        "design.sv", 5: token is '['
          mux4x1 inst1(.sel[0](k), .sel[1](j), .I[0](q), I[1](0), .I[2](1), 
        .I[3](qb), .y(W1));
                            ^
  
  1 error
  </code></pre>