title: Why am I not seeing an output when I synthesize?
body: <p>I have been working on a lab assignment that is practically complete, but am running into an issue where I am not seeing an output when synthesizing.  I have 7 blocks, that when tested individually display the correct output.  How is it that I wouldn't get any output at all when using the top module and test bench files?  Below is my top module, followed by my test bench as I suspect the problem may be there.  I've looked it over and can't pinpoint anything I may have done wrong.  Any help would be appreciated.</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity top_module is port(
      x,y : in std_logic_vector(7 downto 0);
      opcode : in std_logic_vector(2 downto 0);
      z : out std_logic_vector(7 downto 0)
      );
  end top_module;
  
  architecture behavior of top_module is
  
  signal bwAnd, bwOr, bwXor, add, subtract, bwComplement, mux_in1, mux_in2, mux_in3, mux_in4, mux_in5, mux_in6 : std_logic_vector(7 downto 0);
  
  
  component BW_And is port(
      x,y : in std_logic_vector(7 downto 0);
      z1 : out std_logic_vector(7 downto 0)
      );
  end component;
  
  component BW_Rr is port(
      x,y : in std_logic_vector(7 downto 0);
      z2 : out std_logic_vector(7 downto 0)
      );
  end component;
  
  component BW_Xor is port(
      x,y : in std_logic_vector(7 downto 0);
      z3 : out std_logic_vector(7 downto 0)
      );
  end component;
  
  component full_adder_8 is port(
      x,y : in std_logic_vector(7 downto 0);
      cin : in std_logic_vector(7 downto 0) := "00000000";
      sum, cout: out std_logic_vector(7 downto 0)
      );
  end component;
  
  component full_subtractor_8 is port(
      x,y : in std_logic_vector(7 downto 0);
      cin : in std_logic_vector(7 downto 0) := "11111111";
  difference, cout: out std_logic_vector(7 downto 0)
      );
  end component;
  
  component Complement is port(
      x : in std_logic_vector(7 downto 0);
      z4 : out std_logic_vector(7 downto 0)
      );
  end component;
  
  component mux is port(
      z1,z2,z3,sum,difference,z4 : in std_logic_vector(7 downto 0);
      opcode : in std_logic_vector(2 downto 0);
      mux_out : out std_logic_vector(7 downto 0)
      );
  end component;
  
  begin
  
  --instantiating components and mapping ports
  
  c0: BW_And port map(x =&gt; x, y =&gt; y, z1 =&gt; bwAnd);
  
  c1: BW_Or port map(x =&gt; x, y =&gt; y, z2 =&gt; bwOr);
  
  c2: BW_Xor port map(x =&gt; x, y =&gt; y, z3 =&gt; bwXor);
  
  c3: full_adder_8 port map(x =&gt; x, y =&gt; y, sum =&gt; add);
  
  c4: full_subtractor_8 port map(x =&gt; x, y =&gt; y, difference =&gt; subtract);
  
  c5: Complement port map(x =&gt; x, z4 =&gt; bwComplement);
  
  c6: mux port map(z1 =&gt; mux_in1, z2 =&gt; mux_in2, z3 =&gt; mux_in3, sum =&gt; mux_in4, difference =&gt; mux_in5, z4 =&gt;mux_in6, opcode =&gt; opcode, mux_out =&gt; z);
  
  end behavior;
  </code></pre>
  
  <p>Test Bench:</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity Lab4 is
  end Lab4;
  
  architecture behavior of Lab4 is
  
  component top_module is port(
      x,y : in std_logic_vector(7 downto 0);
      opcode : in std_logic_vector(2 downto 0);
      z : out std_logic_vector(7 downto 0)
      );
  end component;
  
  signal test_x : std_logic_vector(7 downto 0);
  signal test_y : std_logic_vector(7 downto 0);
  signal test_opcode : std_logic_vector(2 downto 0) := "000";
  signal test_z : std_logic_vector(7 downto 0);
  
  begin
  
      uut: top_module port map (x =&gt; test_x, y =&gt; test_y, opcode =&gt; test_opcode, z =&gt; test_z);
  
  sim_proc : process
  begin
  
      test_x &lt;= "00010100"; test_y &lt;= "11001111"; test_opcode &lt;= "000";
      wait for 100 ns;
      test_x &lt;= "00010100"; test_y &lt;= "11001111"; test_opcode &lt;= "001";
      wait for 100 ns;
      test_x &lt;= "00010100"; test_y &lt;= "11001111"; test_opcode &lt;= "010";
      wait for 100 ns;
      test_x &lt;= "00010100"; test_y &lt;= "11001111"; test_opcode &lt;= "011";
      wait for 100 ns;
      test_x &lt;= "00010100"; test_y &lt;= "11001111"; test_opcode &lt;= "100";
      wait for 100 ns;
      test_x &lt;= "00010100"; test_y &lt;= "11001111"; test_opcode &lt;= "101";
  
  end process;
  end behavior;
  </code></pre>
  
  <p>Entities for each component:</p>
  
  <pre><code>entity BW_And is port(
      x,y : in std_logic_vector(7 downto 0);
      z1 : out std_logic_vector(7 downto 0)
      );
  end BW_And;
  
  entity BW_Or is port(
      x,y : in std_logic_vector(7 downto 0);
      z2 : out std_logic_vector(7 downto 0)
      );
  end BW_Or;
  
  entity BW_Xor is port(
      x,y : in std_logic_vector(7 downto 0);
      z3 : out std_logic_vector(7 downto 0)
      );
  end BW_Xor;
  
  entity full_adder_8 is port(
      x,y : in std_logic_vector(7 downto 0);
      cin : in std_logic_vector(7 downto 0) := "00000000";
      sum, cout: out std_logic_vector(7 downto 0)
      );
  end full_adder_8;
  
  entity full_subtractor_8 is port(
      x,y : in std_logic_vector(7 downto 0);
      cin : in std_logic_vector(7 downto 0) := "11111111";
      difference, cout: out std_logic_vector(7 downto 0)
      );
  end full_subtractor_8;
  
  entity Complement is port(
      x : in std_logic_vector(7 downto 0);
      z4 : out std_logic_vector(7 downto 0)
      );
  end Complement;
  
  entity mux is port(
      z1,z2,z3,sum,difference,z4 : in std_logic_vector(7 downto 0);
      opcode : in std_logic_vector(2 downto 0);
      mux_out : out std_logic_vector(7 downto 0)
      );
  end mux;
  </code></pre>