title: SystemVerilog TypeDef Can;t index object with zero packed or unpacked array dimensions
body: <p>I am currently attempting to use TypeDef in SystemVerilog in order to define a new data structure object containing a 8 bit unsigned register and an 32-bit signed integer but I keep getting the error:</p>
  
  <p><em>Error (10053): Verilog HDL error at UART.v(35): can't index object "data" with zero packed or unpacked array dimensions</em></p>
  
  <p>I have recreated a simple implementation below where the topLevelModule instances a lowLevelModule which determines the values of both the integer and 8-bit unsigned register in which the structure is made up of and outputs them to the topLevelModule. </p>
  
  <p>Using a separate UART module I am attempting to send this structure/object (which is 40bits long) to  a host computer- to simplify the code below I have omitted this module and left out the majority of the non-associated code. </p>
  
  <pre><code>typedef struct {
              reg[7:0] identifier;
              integer currentSynapticWeight;
          } dataPacket;
  
  module topLevel(clk, reset, UART_TXD);
  
      input clk; // Clock Signal
      input reset; // Reset Signal
      output UART_TXD; // Output Signal
  
      dataPacket data; // Instance the dataPacket Object
  
      lowLevelModule LLM1(clk, reset, data);
  
      // CODE TO DRIVE THE UART CONNECTION OMMITED
  
  endmodule
  
  module lowLevelModule(clk, reset, data);
  
      input clk; // Clock Signal
      input reset; // Reset Signal
      output dataPacket data; // Instance the dataPacket Object
  
      reg[7:0] someUnsigned8BitUnsignedReg = 8'b10001000;
      integer someIntegerValue = 25;
  
      always @(*)
          begin
              data[39:32] = someUnsigned8BitUnsignedReg;
              data[31:0]  = someIntegerValue;
          end
  
  endmodule
  </code></pre>
  
  <p>Any help would be greatly appreciated, I am not sure if I have used TypeDef in the correct manor. </p>