title: How to modify the Verilog code to avoid multiple drivers?
body: <p>Quartus 11.0 says:</p>
  
  <blockquote>
    <p>Error (10028): Can't resolve multiple constant drivers for net "n[9]"</p>
  </blockquote>
  
  <p>for the following code:</p>
  
  <pre><code>module make_counter(h, clk, P);
  
  input wire h;
  input wire clk; 
  output wire P;
  reg r=1'b1;
  reg[9:0] n=10'b0000000000;
  
  always @(posedge h)
  begin
      n&lt;=0;
  end
  
  always @(negedge clk)
  begin
  if(n&lt;600) 
      n&lt;=n+1'b1;
  
  if(n==106)  
      r&lt;=1'b0;
  else if(n==517)  
      r&lt;=1'b1;
  else;
  end
  assign P=r;
  
  endmodule
  </code></pre>
  
  <hr>
  
  <p><a href="http://i.stack.imgur.com/k5Dmk.png" rel="nofollow">########### image is here ###########</a></p>
  
  <hr>
  
  <p>zhe image is what i want. when flag1 start set n=0, and count clk;
    when count to flag2, set P=0; when count to red arrow, set P=1;</p>