title: Are multiple non-nested if statements inside a VHDL process a bad practice?
body: <p>I use VHDL for a few months and I sometimes build that kind of process with <strong>non-nested</strong> if statements when I want some conditions to be evaluated sequentially : </p>
  
  <pre class="lang-vhdl prettyprint-override"><code>    process(clk)
      begin
          if rising_edge(clk) then
              if CONDITION1 then
                  (some instructions)
              end if;
  
              if CONDITION2 then
                  (some instructions)
              end if;
          end if;
      end process;
  </code></pre>
  
  <p>It seems to work well in both simulation and synthesis, but I hardly ever see that kind of structure when looking for examples on the web.
  I had doubts about the sequential execution of those statements but the IEEE Standard VHDL Language Reference Manual Std 1076-2008 states :</p>
  
  <blockquote>
    <p>Sequential statements are used to define algorithms for the execution
    of a subprogram or process; they execute in the order in which they
    appear.</p>
  </blockquote>
  
  <p>And the <code>if</code> statement is in the list of sequential statements.</p>
  
  <p>Why can't I find more examples of this? Is this a bad practice?</p>