title: Left Shift In Ring Counter
body: <pre><code>module RingCounter(
  
  input logic Clock,
  
  input logic Reset,
  
  output logic [3:0] Count
  
  );
  
  
  always_ff @(posedge Clock, posedge Reset)
  
  begin
  
  if (Reset) 
  
  Count &lt;= 4’d1;
  
  else 
  
  Count &lt;= {Count[2:0], Count[3]};
  
  end
  
  endmodule
  </code></pre>
  <p>I have the working code above for a 4-bit ring counter in SystemVerilog, but I am unsure how one line of it works as it wasn't clearly explained in the lecture.</p>
  <pre><code>Count &lt;= {Count[2:0], Count[3]};
  </code></pre>
  <p>Any help on explaining exactly what this line does would be much appreciated.</p>