title: Digital Logic - realizing full adder using NAND gates?
body: <p>I am stuck while solving this question,</p>
  
  <blockquote>
    <p>What is the minimum number of 2 input
    nand gates required to realize</p>
  </blockquote>
  
  <p>I found the answer when there is no limit on the number of inputs, but cant find the answer when the constraint "2 input nand gate" is specified". Any help would be appreciated.</p>