title: How to declare an output with multiple zeros in VHDL
body: <p>Hello i am trying to find a way to replace this command: <code>Bus_S &lt;= "0000000000000000000000000000000" &amp; Ne;</code> with something more convenient. Counting zeros one by one is not very sophisticated. The program is about an SLT unit for an ALU in mips. The SLT gets only 1 bit(MSB of an ADDSU32) and has an output of 32 bits all zeros but the first bit that depends on the Ne=MSB of ADDSU32. (plz ignore ALUop for the time being)</p>
  
  <pre><code>entity SLT_32x is
     Port ( Ne : in  STD_LOGIC;
           ALUop : in STD_LOGIC_VECTOR (1 downto 0);
           Bus_S : out  STD_LOGIC_VECTOR (31 downto 0));
  end SLT_32x;
  
  architecture Behavioral of SLT_32x is
  begin
    Bus_S &lt;= "0000000000000000000000000000000" &amp; Ne; 
  end Behavioral;
  </code></pre>
  
  <p>Is there a way to use (30 downto 0)='0' or something like that? Thanks.</p>