title: How to Model a delay in Verilog without # ? That can be synthesized
body: <p>I am looking to create an AND gate which gets the result after a delay of lets say 10ns an my clock is 500 ps. How will i delay the assignment without using # delays ?</p>
  
  <p>I have tried to make a counter which increments but how to model it so that it only starts when my input changes. Also the input won't change till the first output is evaluated and assigned. Initial Counter is 0 and lets say delay is 3'b111 so i want the counter to go from 1 to 3'b111 and then assign it to y. Inputs are a and b to the and gate.</p>
  
  <pre><code>always@(posedge clk)begin
    if (!reset) begin y &lt;=0; counter &lt;=0; end
    else begin
     counter &lt;= counter +1'b1;
     if(counter==delay)begin
       y &lt;= a &amp; b;
       counter &lt;=0;
    end
  end
  </code></pre>