title: vhdl input not used
body: <p>I'm trying to develop an 8-bit binary to BCD VHDL module, but the Xilinx suite is optimizing my <code>Bin_in</code> signal to always be ground. I've found several other threads that mention the similar problems (in different coding contexts) but the answers provided seem to concern algorithms where the complete truth table for the output isn't declared.  I've also found examples of an 8-bit to BCD converter with a similar algorithm as mine.  If I've developed my code correctly the process should run any time the <code>Bin_in</code> input changes, so I don't understand why the tools would optimize it out. Any info or help is much appreciated.</p>
  
  <p>This is the warning from synthesis:</p>
  
  <blockquote>
  <pre><code>WARNING:Xst:647 - Input &lt;Bin_in&lt;7:1&gt;&gt; is never used. This port will be
  preserved and left unconnected if it belongs to a top-level block or
  it belongs to a sub-block and the hierarchy of this sub-block is
  preserved.
  </code></pre>
  </blockquote>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  use IEEE.numeric_std.ALL;
  
  entity B8_to_4BCD is
  port (Bin_in : in std_logic_vector (7 downto 0);
        BCD0, BCD1, BCD2 : out std_logic_vector (3 downto 0)
       );
  
  end entity B8_to_4BCD;
  
  architecture Behavioral of B8_to_4BCD is
  
  begin
  
  --Sequential code follows, runs if Bin_in changes
  process (Bin_in)
  --Holders for Bin_in and output BCD
  variable input : std_logic_vector (7 downto 0);
  variable output : std_logic_vector (11 downto 0);
  
  begin
      input  := Bin_in;          --Assign Bin_in to input
      output := (others =&gt; '0'); --Set output to all zeroes
  
      for I in 1 to 8 loop
          --Check ones for greater than or equal to 5
          if output(3 downto 0) &gt;= "0101" then
              output(3 downto 0) := output(3 downto 0) + "0011";
  
          --Check tens for greater than or equal to 5
          elsif output(7 downto 4) &gt;= "0101" then
              output(7 downto 4) := output(7 downto 4) + "0011";
  
          --Check hundreds for greater than or equal to 5
          elsif output(11 downto 8) &gt;= "0101" then
              output(11 downto 8) := output(11 downto 8) + "0011";
          else
  
          end if;
  
          output := output(11 downto 1) &amp; input(7); --Shift output left one and move input(7) into LSB
          input := input(6 downto 0) &amp; '0';         --Shift input left one and pad with zero
  
      end loop;
  
      BCD0 &lt;= output(3 downto 0);
      BCD1 &lt;= output(7 downto 4);
      BCD2 &lt;= output(11 downto 8);
  
  end process;
  
  end Behavioral;
  </code></pre>