title: Automatic flag for compiler directive based on synthesis/simulation for xilinx/modelsim?
body: <p>I've got a large verilog project that I'm synthesizing onto a xilinx fpga and simulating in modelsim.  There are a few modules wherein I'd like to simulate one version of said module and synthesize another.  For example I have a parameterized reset debouncer, which counts a few milliseconds.  Clearly for simulation this is annoying so before I simulate I change the debounce count to something like 10 clock cycles.  Currently I have a flag (`define SIMULATION), which I comment out for synthesis.  Then in my modules I utilize compiler directives like 'ifdef to compile a different version of the deouncer depending on synthesis/simulation:</p>
  
  <pre><code> `ifdef SIMULATION
     button_debouncer #(1,5, 24)
  `else
     button_debouncer #(1,12000000,24)
  `endif
     resetdebounce(/**/
           // Outputs
           .debounced     (reset),
           // Inputs
           .clk           (clk),
           .button        (~reset_button));
  </code></pre>
  
  <p>While this works it requires that I comment in/out `define SIMULATION every time I switch from modlesim to ISE.  I often forget, waste time, etc, etc.</p>
  
  <p>Is there an automatic way to determine which tool is being used?  Eg I could say something like <code>ifdef XILINX or</code>ifdef MODELSIM instead of my `ifdef SIMULATION hack?  Thanks a lot!</p>