title: Passing hierarchy into a Verilog module
body: <p>I have a "watcher" module that is currently using global hierarchies inside it.  I need to instantiate a second instance of this with a second global hierarchy.</p>
  
  <p>Currently:</p>
  
  <pre><code>module watcher;
  wire sig = `HIER.sig;
  wire bar = `HIER.foo.bar;
  ...
  endmodule
  
  watcher w; // instantiation
  </code></pre>
  
  <p>Desired:</p>
  
  <pre><code>module watcher(input base_hier);
  wire sig = base_hier.sig;
  wire bar = base_hier.foo.bar;
  ...
  endmodule
  
  watcher w1(`HIER1); // instantiation
  watcher w2(`HIER2); // second instantiation, except with a different hierarchy
  </code></pre>
  
  <p>My best idea is to use vpp (the Verilog preprocessor) to brute-force generate two virtually-identical modules (one with each hierarchy), but is there a more elegant way?</p>