title: Passing Generics to Record Port Types
body: <p>I did recently start to use records for my port definitions, especially if I want to group signals that belong to a certain interface. However, the problem I'm facing here is that I cannot pass, say the width of a std_logic_vector, to the entity by means of a generic. So what I basically want to do is the following:</p>
  
  <pre><code>library ieee;
  use ieee.std_logic_1164.all;
  use work.math_pkg.all;
  
  package fifo_pkg is
  
    type fifo_in_type is record
      data_in : std_logic_vector(DATA_WIDTH_??- 1 downto 0);
      rd      : std_logic;
      wr      : std_logic;
    end record;
  
    type fifo_out_type is record
      data_out : std_logic_vector(DATA_WIDTH_?? - 1 downto 0);
      empty    : std_logic;
      full     : std_logic;
    end record;
  
    component fifo is
      generic
        (
          MIN_DEPTH  : integer;
          DATA_WIDTH : integer
          );
      port
        (
          clk   : in  std_logic;
          res_n : in  std_logic;
          i     : in  fifo_in_type;
          o     : out fifo_out_type
          );
    end component fifo;
  
  end fifo_pkg;   
  </code></pre>
  
  <p>So the ideal solutions would be when i can use the same generic in my record as i did in the entity. (So that DATA_WIDTH is the same as DATA_WIDTH_??). I know that this should work somehow with vhdl 2008, however my quartus II 11sp1 does not support generics in records.</p>
  
  <p>Is there an elegant way to achieve that kind of "generic passing" that is synthesizable? I know that one could just store a constant in the package, but then I cannot use the same fifo package to instantiate several fifo's with different widths.</p>
  
  <p>Thanks a million,
  T</p>