title: MIPS pipeline timing diagram
body: <p>I want to confirm whether the following timing diagram is correct for a MIPS 5 stage pipeline ( * = stalls ):</p>
  
  <pre><code>               |  1 |  2 |  3 |  4 |  5 |  6 |  7 |  8 |  9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
  LW R1, 0(R4)   | IF | ID | EX |  M |  W |    |    |    |    |    |    |    |    |    |    |    |
  LW R2, 400(R4) |    | IF | ID | EX |  M |  W |    |    |    |    |    |    |    |    |    |    |
  ADD1 R3,R1,R2  |    |    | IF | ID |  * |  * | EX |  M |  W |    |    |    |    |    |    |    |
  SW R3, 0(R4)   |    |    |    | IF |  * |  * | ID |  * |  * | EX |  M |  W |    |    |    |    |
  SUB R4,R4,#4   |    |    |    |    |    |    | IF |  * |  * | ID | EX |  M |  W |    |    |    |
  BNEZ R4, L1    |    |    |    |    |    |    |    |    |    | IF | ID |  * |  * | EX |  M |  W |
  </code></pre>
  
  <p>Comments:</p>
  
  <p>1) ADDI : ID is stalled 2 cycles so previous WB can complete</p>
  
  <p>2) SW : 2 stalls because ID can't begin, 2 more stalls for ID for previous WB to complete</p>
  
  <p>3) SUB : IF can't start till cycle # 7, ID has to wait till cycle 10 because of previous instruction</p>
  
  <p>4) BNEZ : IF can't start till cycle # 10, 2 stalls for ID so previous WB can complete</p>