title: Re-assigning a ```reg``` variable in always block
body: <p>I am confused about whether a <code>reg</code> variable can be re-assigned in an always block.
  First, i got the problem when tring to <code>run implementation</code> the following code in vivado.</p>
  <pre><code> module encoder83 (
      input [7:0] x,
      input en,
      output reg [2:0] y,
      output reg ind
  );
      integer  i;
  
      always @(*) begin
          if(en) begin
              ind = 1;
              casex (x)
                  8'b00000001 :  y = 3'b000;
                  8'b0000001x :  y = 3'b001;
                  8'b000001xx :  y = 3'b010;
                  8'b00001xxx :  y = 3'b011;
                  8'b0001xxxx :  y = 3'b100;
                  8'b001xxxxx :  y = 3'b101;
                  8'b01xxxxxx :  y = 3'b110;
                  8'b1xxxxxxx :  y = 3'b111; 
                  default : begin
                      y = 3'b000;
                      ind = 0;
                  end
              endcase
          end
          else y = 3'b000;
      end
  
  endmodule
  </code></pre>
  <p>But after i delete the 11th line <code>ind = 1;</code> , it becomes alright. The implementation can be completed.<br />
  However, the following code can also successfully finish <code>run implementation</code>.</p>
  <pre><code>module test(
      input in,
      output out
      );
      
      reg tmp;
      
      always @(*) begin
          tmp = 1;
          tmp = 2;
      end
      
  endmodule
  </code></pre>