title: command line arguments into make file
body: <p>I have a C file for which I want to give cmd line arguments.</p>
  
  <p>Say </p>
  
  <pre><code>$ make --argument1 
  </code></pre>
  
  <p>or something like this.</p>
  
  <p>So that in my main program I should be able to do argv[1] and be able to access the variable.</p>
  
  <p>I have tried looking for  ways of doing this. Is there actually a way of doing this?</p>
  
  <p>These were the relevant content I found on the GNULinux manual about make.</p>
  
  <blockquote>
    <p>variables defined on the command line are passed to the sub-make
    through MAKEFLAGS. Words in the value of MAKEFLAGS that contain ‘=’,
    make treats as variable definitions just as if they appeared on the
    command line.</p>
  </blockquote>
  
  <p>Is this what I need to read up more or is this in a different context?</p>
  
  <p>Do let me know.</p>