title: Critical sections in ARM
body: <p>I am experienced in implementing critical sections on the AVR family of processors, where all you do is disable interrupts (with a memory barrier of course), do the critical operation, and then reenable interrupts:</p>
  
  <pre><code>void my_critical_function()
  {
     cli();  //Disable interrupts
     // Mission critical code here
     sei();  //Enable interrupts
  }
  </code></pre>
  
  <p>Now my question is this:</p>
  
  <p>Does this simple method apply to the ARM architecture of processor as well?  I have heard things about the processor doing lookahead on the instructions, and other black magic, and was wondering primarily if these types of things could be problematic to this implementation of critical sections.</p>