title: Trying to automate the fpga build process in Xilinx using python scripts
body: <p>I want to automate the entire process of creating ngs,bit and mcs files in xilinx and have these files be automatically be associated with certain folders in the svn repository. What I need to know is that is there a log file that gets created in the back end of the Xilinx gui which records all the commands I run e.g open project,load file,synthesize etc.</p>
  
  <p>Also the other part that I have not been able to find is a log file that records the entire process of synthesis, map,place and route and generate programming file. Specially record any errors that the tool encountered during these processes.</p>
  
  <p>If any of you can point me to such files if they exist it would be great. I haven't gotten much out of my search but maybe I didn't look enough.</p>
  
  <p>Thanks!</p>