title: How does clock gating in RTL design work?
body: <p>I'm trying to understand how clock gating works in RTL design.</p>
  
  <p>I've an example wave here:</p>
  
  <p><a href="https://i.stack.imgur.com/XZCt0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/XZCt0.png" alt="enter image description here"></a></p>
  
  <p>Description:</p>
  
  <pre><code>1st signal is gated_clock
  2nd signal is clock_enable
  3rd signal is ungated_clock
  </code></pre>
  
  <p>So there are 3 cycles in this wave (let's say cycle 0,1,2). In cycle 0, clock_enable was low and gated_clock was turned off. In cycle 1 clock_enable goes high and in next cycle (cycle 2) gated_clock turns on. </p>
  
  <p>Now, during simulation I see some cases where an incoming data received at cycle 1 is properly being registered into the module that is gated by the clock (using gated_clock). It's kinda odd to me and I don't quite understand how it's possible.</p>
  
  <p>The logic is like this:</p>
  
  <pre><code>always_ff @(posedge gated_clock, negedge reset) begin
     if (~reset) begin
        some_val &lt;= 1'b0;
     end else begin
        if (in_valid==1'b1 &amp;&amp; in_ready==1'b1) begin
           some_val &lt;= in_val;
        end else begin
           some_val &lt;= 1'b0;
        end
     end
  end
  </code></pre>
  
  <p>So I'm seeing that if <code>in_valid</code> and <code>in_ready</code> was high in <code>cycle 1</code> then <code>some_val</code> will register the incoming <code>in_val</code> data and it'll be available in <code>cycle 2</code>. However in <code>cycle 1</code>, <code>gated_clock</code> was zero. So how did the in_val get sampled here? From what I understand, posedge <code>gated_clock</code> must be 1 if we want to flop <code>in_val</code> in <code>cycle 1</code> . </p>
  
  <p>I might be missing some core circuit level digital design concept. I'll really appreicate any help.</p>
  
  <p>Updated wave:
  <a href="https://i.stack.imgur.com/2bfSj.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/2bfSj.png" alt="enter image description here"></a></p>
  
  <pre><code>1st signal is gated_clock
  2nd signal is clock_enable
  3rd signal is ungated_clock
  4th signal is in_valid
  5th signal is in_ready
  6th signal is in_val
  7th signal is some_val
  </code></pre>
  
  <p>So here you will see at <code>cycle 0</code>, <code>gated_clock</code> is off but <code>in_val</code> and <code>in_ready</code> is high. The input data <code>in_val</code> is also high. In next cycle <code>some_val</code> goes high. So it looks like <code>in_val</code> captured in <code>cycle 0</code> even though <code>gated_clock</code> was off.</p>