title: Error (10500): VHDL
body: <p>i have problem with this code !!!</p>
  
  <pre><code>library ieee ;
  use ieee.std_logic_1164.all;
  
  entity tl2 is
      port( clk: in std_logic );
  end tl2;
  
  architecture ways2 of tl2 is
      component counter is
          generic(
              n: natural :=5
          ); port(
              clock:  in std_logic;
              clear:  in std_logic;
              count:  in std_logic;
              Q:  out std_logic_vector(n-1 downto 0)
          );
      end component;
  
      component tff is
          port(
              t: in  std_logic;
              clock: in std_logic;
              output: out std_logic
          );
      end component;
  
      signal x: std_logic;
      i: std_logic_vector(4 downto 0);
      ta , tb , tc: std_logic;
      tap , tbp , tcp: std_logic;
  
  begin
  
      counter4: counter port map( clk =&gt; clock , '0' =&gt; clear , '1' =&gt; count , i =&gt; Q);
      A: tff port map(clk =&gt; clock , ta =&gt; t , tap =&gt; output);
      B: tff port map(clk =&gt; clock , tb =&gt; t , tbp =&gt; output);
      C: tff port map(clk =&gt; clock , tc =&gt; t , tcp =&gt; output);
  
      process( i.ta,tb,tc )
      begin
          if( i="00011" or i="00110" or i="10101" ) then
              x &lt;= '1';
          end if;
          if( i="10101" ) then
              clear &lt;= '0';
          end if;
          ta &lt;= ((tbp and tcp and x)or(tap and tcp and x));
          tb &lt;= (not tap and tcp and x);
          tc &lt;= x;
  
      end process;
  
  end ways2;
  </code></pre>
  
  <hr>
  
  <p>user3139746 elaborated on the errors he was asking about in a comment in response to sharth's comment:</p>
  
  <blockquote>
    <p>thats error:Error (10500): VHDL syntax error at tl2.vhd(27) near text
    "i"; expecting "begin", or a declaration statement Error (10500): VHDL
    syntax error at tl2.vhd(33) near text "=>"; expecting ")", or "," – 
    user3139746 4 hours ago</p>
  </blockquote>
  
  <p>(This is an Altera error message)</p>