title: How are functions used in Verilog?
body: <p>In my FPGA/Verilog course, my professor just went over functions.</p>
  <p>He was saying that within functions, you write the code procedurally. Then, when you want to call the function, you can either call it within an always block (ie, procedurally), or you can call it with an assign statement.</p>
  <p>It doesn't make sense to me how a function can be written with procedural code, but then be called continuously.</p>
  <p>If anyone has any insight to this (probably) basic question, it is much appreciated.</p>