title: Make: compile object file twice in the same target
body: <p>I have the following simple problem in a Makefile:</p>
  
  <pre><code>%.o:: %.c
        gcc -o $@ -c $&lt;
  
  lib1.a: test.o
          ar -r $@ test.o
          rm *.o
  
  lib2.a: test.o
          ar -r $@ test.o
          rm *.o
  
  all: lib1.a lib2.a
  </code></pre>
  
  <p><code>make lib1.a</code> or <code>make lib2.a</code> work properly. However, <code>make all</code> gives:</p>
  
  <pre><code>gcc -o test.o -c test.c
  ar -r lib1.a test.o
  rm *.o
  ar -r lib2.a test.o
  ar: test.o: No such file or directory
  make: *** [lib2.a] Error 1
  </code></pre>
  
  <p>I need to do the <code>rm *.o</code> cause I want the object file to compile each time (in my real Makefile, I have a more complex use case where I compile with different flags).</p>
  
  <p>How can I fix this problem? It seems that <code>make</code> compiles the object file only once.</p>
  
  <p>I tried with <code>.PHONY</code> instead of doing the <code>rm</code>, but again, it compiles only once.</p>