title: How to convert a string to a variable name?
body: <p>I would like to have a construct like below to declare variable names based on a string queue. The below doesn't compile. So I would like to know if a similar approach is possible in Systemverilog.</p>
  
  <p>Below is a simplified version of what I want to actually implement.</p>
  
  <pre><code>`define declare_int(NAME) int ``NAME`` = 1;
  
  string str_q[$] = {"a", "b", "c"};
  foreach (str_q[i]) begin
     `declare_int(str_q[i])
  end
  </code></pre>
  
  <p><strong>NOTE</strong>: I am aware that <code>`declare_int(a)</code> will translate to <code>int a = 1;</code>. But as shown in the example above, I need a foreach loop to call this macro multiple times and so the input of the macro has to be some datatype, like a <code>string</code> in this case. The purpose is to auto-declare stuff as the queue changes with time.   </p>
  
  <p>In other words, how can I define the <code>`declare_int</code> macro so that <code>`declare_int("a")</code> translates to <code>int a = 1;</code>?</p>