title: Default type input and output signals SystemVerilog
body: <p>I'm trying to learn by myself SystemVerilog (I'm a university student and in my projects I've always used VHDL) and I have a question concerning data types. So far, I think I understood the differences, pro and cons between <code>reg</code>, <code>wire</code> and <code>logic</code> but I'm wondering, in this code snippet:</p>
  
  <pre><code>module example(
  
  input clk,
  input nrst,
  input nset,
  input up,
  input [3:0] preload,
  output [3:0] counter
  
  );
  </code></pre>
  
  <p>what's the default type assigned to inputs and outputs? Is it logic (as it is the best choice for "everyday" circuitry)?</p>