title: Passing parameters between Verilog modules
body: <p>I fairly new to Verilog and learning the ropes. I have some code which generates an 8 bit up-counter (module <em>counter.v</em>), which is then called by a top module (<em>top_module.v</em>). There is a simulation test fixture (<em>test_fixture.v</em>) which calls the top module for testing.</p>
  
  <p>I was trying to define the width of the counter using a parameter (<strong>parameter</strong> COUNTER_WIDTH) and was having difficulty doing so. A colleague fixed the code for me and it does now indeed work, but I want to understand a few things so I can understand what is actually going on.</p>
  
  <p>Here is the code for the counter module:</p>
  
  <pre><code>module counter
  #(parameter COUNTER_WIDTH = 8)
  (
      input wire CLK,
      input wire RST,
      input wire CE,
      output reg[COUNTER_WIDTH-1:0] out = {COUNTER_WIDTH{1'b0}}
      );
  
  
     always @(posedge CLK) begin
        if (RST == 1) begin
           out &lt;= {COUNTER_WIDTH{1'b0}};
        end else begin
        if (CE == 1) begin
           out &lt;= out + 1'b1;
        end
      end
    end
  endmodule
  </code></pre>
  
  <p>The top module:</p>
  
  <pre><code>module top_module
  #(parameter COUNTER_WIDTH = 8)
  (
      input wire CLK,
      input wire CE,
      input wire RST,
      output wire[COUNTER_WIDTH-1:0] out
      );
  
  counter #(
      .COUNTER_WIDTH(COUNTER_WIDTH)
      )
  counter_inst(
      .CLK(CLK),
      .RST(RST),
      .CE(CE),
      .out(out)
  );
  
  endmodule
  </code></pre>
  
  <p>And the test fixture:</p>
  
  <pre><code>module test_fixture();
  
  parameter COUNTER_WIDTH = 8;
  
  // inputs
  reg CLK = 0;
  reg RST = 0;
  reg CE = 0;
  
  // outputs
  wire [COUNTER_WIDTH-1:0] Q;
  
  // instance of top module to be tested
  top_module #(
      .COUNTER_WIDTH(COUNTER_WIDTH)
  ) 
  
  test_inst(
      .CLK(CLK),
      .RST(RST),
      .CE(CE),
      .out(Q)
  );
  endmodule
  </code></pre>
  
  <p>I think I'm fine with the counter module, but have a question about what is going on in top module/test fixture:</p>
  
  <ul>
  <li>It looks like the parameter COUNTER_WIDTH is declared in each module (#(parameter COUNTER_WIDTH = 8)), and then "connected to" (if that is the correct expression) the parameter declaration in the other module (e.g. #(.COUNTER_WIDTH(COUNTER_WIDTH)  )</li>
  <li>Is that understanding correct? If so, why do we have to declare the parameter within a module <em>and</em> connect it to a parameter within another module?</li>
  </ul>
  
  <p>Thanks in advance for your help!</p>