title: Issue with Logic in Verilog
body: <p>I'm trying to write a multiplier based on a design. It consists of two 16-bit inputs and the a single adder is used to calculate the partial product. The LSB of one input is AND'ed with the 16 bits of the other input and the output of the AND gate is repetitively added to the previous output. The Verilog code for it is below, but I seem to be having trouble with getting the outputs to work.</p>
  
  <pre><code>module datapath(output reg [31:15]p_high,
                  output reg [14:0]p_low,
                  input [15:0]x, y,
                  input clk); // reset, start, x_ce, y_ce, y_load_en, p_reset, 
                 //output done);
  
  reg [15:0]q0;
  reg [15:0]q1;
  reg [15:0]and_output;
  reg [16:0]sum, prev_sum; 
  reg d_in;
  reg [3:0] count_er;
  
  initial
   begin
        count_er &lt;= 0;
        sum &lt;= 17'b0;
        prev_sum &lt;= 17'b0;
   end
  
  always@(posedge clk)
  begin
          q0 &lt;= y;
          q1 &lt;= x;
          and_output &lt;= q0[count_er] &amp; q1;
          sum &lt;= and_output + prev_sum;    
          prev_sum &lt;= sum;
          p_high &lt;= sum;
          d_in &lt;= p_high[15];
          p_low[14] &lt;= d_in;
          p_low &lt;= p_low &gt;&gt; 1;
          count_er &lt;= count_er + 1;
   end
   endmodule
  </code></pre>
  
  <p><img src="https://i.stack.imgur.com/JCCu4.png" alt="enter image description here">
  I created a test bench to test the circuit and the first problem I see is that, the AND operation doesn't work as I want it to. The 16-bits of the x-operand are and'ed with the LSB of the y-operand. The y-operand is shifted by one bit after every clock cycle and the final product is calculated by successively adding the partial products. </p>
  
  <p>However, I am having trouble starting from the sum and prev_sum lines and their outputs are being displayed as xxxxxxxxxxxx.</p>