title: In a structural VHDL ROM, how can I have multiple word lines drive outputs?
body: <p>I'm writing a ROM in structural VHDL for a class of mine. The design takes a 6-bit address and runs it through a 6-to-64 binary decoder. Each decoder output enables or disables a single 6 bit word line made of tri-state inverters. The word line bit inputs are either '1' or '0' for each bit. Most importantly, every word line writes to the <em>same</em> output vector.</p>
  
  <p>When I check the syntax in Xilinx 9.2 it is fine, but when I synthesize I get this error: </p>
  
  <pre><code>ERROR:Xst:528 - Multi-source in Unit &lt;ufm6bit&gt; on signal &lt;N0&gt;
  Sources are: 
     Output signal of BUFT instance &lt;rom/word63rom/tri0/Z&gt;
     Output signal of BUFT instance &lt;rom/word62rom/tri0/Z&gt; 
     Output signal of BUFT instance &lt;rom/word...rom/tri0/Z&gt; 
     Output signal of BUFT instance &lt;rom/word00rom/tri0/Z&gt; 
  </code></pre>
  
  <p>I used a program to write the decoder VHDL so the port map is too big to put here (will put it on pastebin if you want). The word line looks like this:</p>
  
  <pre><code>entity tribuffer6 is
    PORT (
      A : in  std_logic_vector(5 downto 0);
      E : in  std_logic;
      Z : out std_logic_vector(5 downto 0));
  end tribuffer6;
  </code></pre>
  
  <p>and the 6 tribuffers it uses look like this:</p>
  
  <pre><code>entity tribuffer is
    Port ( A : in  std_logic;
           E : in  std_logic;
           Z : out std_logic);
  end tribuffer;
  
  architecture Behav of tribuffer is
  begin
  
    z &lt;= not a after 120 ps when e = '1' else
           'Z' after 120 ps;
  
  end Behav;
  </code></pre>
  
  <p>finally the wordlines are tied up like this:</p>
  
  <pre><code>SIGNAL dataline : std_logic_vector(5 downto 0);
  
  word00rom : tribuffer6 PORT MAP (
                           A=&gt;"000000",
                           Z=&gt;dataline,
                           E=&gt;word00en );
  word01rom : tribuffer6 PORT MAP (
                           A=&gt;"000000",
                           Z=&gt;dataline,
                           E=&gt;word01en );
  </code></pre>
  
  <p>It's obvious from the error that VHDL is not happy with having multiple drivers on that line, but there's no way I'm making 64 buffer vectors and chaining them together to defeat the checking. Nor would an OR tree 64-layers deep be practical. What do I have to do to get VHDL to be OK with this?</p>
  
  <p>Update:
  I should clarify a few things. The Xilinx 9.2 is a requirement for the class since it is free and my University is cheap. The only fundamental gates (and,or,not,nand,tristate) can be behavioral, everything else has to be structural. And it was the ROM that I generated the VHDL for, in C, because that would have been a lot of typing otherwise.</p>