title: Arrays as buffer VHDL
body: <p>I need to create a FIFO buffer in VHDL. I need to use a 2 dimensional array to storage data like (number of data)(n-bit data).</p>
  
  <p>If I create a single "big" array that storage for example 1000 entrys. Every new data clock I storage one slot. And every output data clock I output a data. What happen if this two clocks occour near at the same time?</p>
  
  <p>For example:</p>
  
  <pre><code>if rising_edge(INPUT_DATA) then
                      Register_Array(Counter_IN) &lt;= DataIN;
                      Counter_IN &lt;= Counter_IN + 1;
  end if;
  if rising_edge(OUTPUT_DATA) then
                      DataOUT &lt;= Register_Array(Counter_OUT);
                      Counter_OUT &lt;= Counter_OUT + 1;
  end if;
  </code></pre>
  
  <p>If it's possible to create a process like this, what happen if two clock are near at the same time?</p>
  
  <p>Consider I can't lose any data.</p>