title: In Verilog, how to "hold" the value of the rest of a register while modifying a single bit?
body: <p>In Verilog HDL, how can I enforce that the rest of a register file to be untouched while I'm modifying a single bit? Like in the following example,</p>
  
  <pre><code>reg [31:0] result;
  reg [31:0] next_result;
  reg [4:0] count;
  wire done;
  
  //some code here...
  
  result &lt;= 32'b0;
  
  always @* begin
  if(done==1'b1) begin
    next_result[count] &lt;= 1'b1;
  end
  end
  
  always @(posedge clock) begin
  result &lt;= next_result;
  //the rest of the sequential part, in which count increments...
  end
  </code></pre>
  
  <p>it turns out that result contains lots of <code>x</code>(unknown) values after several cycles, which means the register file is not held constant while I am modifying <code>result[count]</code>. Weird though, this problem is only present while I'm synthesizing, and everything goes just fine for simulation purposes. I wonder if there is some way to tell the synthesizer that I would like to "enforce" that not changing the rest of the register file.</p>