title: Define register in verilog
body: <p>In an interview for synopsys, I was as how you would define a 32 bit register in verilog.</p>
  
  <p>I had replied:</p>
  
  <pre><code>reg[31:0] reg1;
  </code></pre>
  
  <p>But the interviewer said this was wrong. Can anyone please tell me the answer to this?</p>