title: 4 bit magnitude comparator VHDL
body: <p>I have to make a 4bit magnitude comparator in VHDL with only concurrent statements (no if/else or case/when).</p>
  
  <pre><code>library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  entity Exercise is
  port (  A : in std_logic_vector (3 downto 0);
          B : in std_logic_vector (3 downto 0);
          Ag : out std_logic;
          Bg : out std_logic;
          AeqB: out std_logic
         );   
  end Exercise;
  
  architecture Comparator of Exercise is
  
  begin
      Ag &lt;= '1'when (A&gt;B) else '0'; 
      Bg &lt;= '1' when (B&gt;A) else '0';  --Problem: Here if i sumulate B="ZZZZ", Bg is 1, asi if B&gt;A 
      AeqB&lt;= '1' when (A=B) else '0'; 
  end Comparator; 
  </code></pre>
  
  <p>The problem is that i need to take in count all the other values of std_logic (U,X,Z,W,L,H,-), i know there is the <code>others</code> but cant figure it out how to make the comparator with <code>with/select</code> statement. </p>
  
  <p>Thanks</p>