title: What is the equivalent of 'Cache line size' in PCIE?
body: <p>In PCI configuration space, Cache line size indicates system cacheline size in units of DWORDs. This register must be implemented by master devices that can generate the Memory Write and Invalidate command. </p>
  
  <p>The value in this register is also used by master devices to determine whether to use Read, Read Line, or Read Multiple commands for accessing memory.</p>
  
  <p>Slave devices that want to allow memory bursting using cacheline wrap addressing mode must implement this register to know when a burst sequence wraps to the beginning of the cacheline.</p>
  
  <p>But this field is implemented by PCI Express devices as a read-write field for legacy compatibility purposes but has no effect on any PCI Express device behavior. </p>
  
  <p>Then how PCIe system implements memory-write-invalidate feature ?</p>