title: 64 bit LFSR design
body: <p>I have designed a 64 bit lfsr but I think its not showing random. Its kind of regular pattern. Can anyone please check my code and see if its correct. (TAP 64,63,61,60)</p>
  
  <pre><code> module lfsr (out, clk, rst);
  
   output reg [63:0] out;
   input clk, rst;
  
   wire feedback1,feedback2,feedback3;
  
   assign feedback1 = ~(out[63] ^ out[62]); 
   assign feedback2 = ~(out[62] ^ out[60]);
   assign feedback3 = ~(out[60] ^ out[59]);
  
   always @(posedge clk, posedge rst)
   begin
    if (rst)
       out = 64'b0;
    else
       out = {out[60:0],feedback3,feedback2,feedback1};
    end
   endmodule
  </code></pre>