title: GNU Make pattern to build output in different directory than src
body: <p>I'm trying to create a Makefile which places my <code>.o</code> files in a different directory than my source files. I'm trying to use a pattern rule so I don't have to create identical rules for each source &amp; object file.</p>
  
  <p>My project structure looks something like:</p>
  
  <pre><code>project/
   + Makefile
   + src/
     + main.cpp
     + video.cpp
   + Debug/
     + src/       [contents built via Makefile:]
       + main.o
       + video.o
  </code></pre>
  
  <p>My Makefile looks something like:</p>
  
  <pre><code>OBJDIR_DEBUG = Debug
  OBJ_DEBUG = $(OBJDIR_DEBUG)/src/main.o $(OBJDIR_DEBUG)/src/video.o
  
  all: $(OBJ_DEBUG)
  
  $(OBJ_DEBUG): %.o: %.cpp
      $(CXX) $(CFLAGS_DEBUG) $(INC_DEBUG) -c $&lt; -o $@
  </code></pre>
  
  <p>This doesn't work, because it looks for my source files at <code>Debug/src/*.cpp</code>.</p>
  
  <p>I've tried the following:</p>
  
  <pre><code># Broken: make: *** No rule to make target `Debug/src/main.cpp', needed by `Debug/src/main.o'.  Stop.
  # As a test, works if I change "%.cpp" to "Debug/src/main.cpp", though it obv. builds the wrong thing
  
  # Strip OBJDIR_DEBUG from the start of source files
  $(OBJ_DEBUG): %.o: $(patsubst $(OBJDIR_DEBUG)/%,%,%.cpp)
      $(CXX) $(CFLAGS_DEBUG) $(INC_DEBUG) -c $&lt; -o $@
  </code></pre>
  
  <h1> </h1>
  
  <pre><code># Broken:
  #   Makefile:70: target `src/main.o' doesn't match the target pattern
  #   Makefile:70: target `src/video.o' doesn't match the target pattern
  
  # Add OBJDIR_DEBUG in target rule
  OBJ = src/main.o src/video.o
  
  $(OBJ): $(OBJDIR_DEBUG)/%.o: %.cpp
      $(CXX) $(CFLAGS_DEBUG) $(INC_DEBUG) -c $&lt; -o $@
  </code></pre>