title: Verilog: Assigning a named generate loop's wire inside a for-loop
body: <p>I am getting a syntax error that I do not understand. It seems Verilog is being picky about an index being a variable in some sense, but I'm not sure exactly what is going on here or how to get around it without hardcoding.</p>
  
  <p>Here's my main module:</p>
  
  <pre><code>module mojo_top(
      // 50MHz clock input
      input clk,
      // Input from reset button (active low)
      input rst_n,
      // cclk input from AVR, high when AVR is ready
      input cclk,
      // Outputs to the 8 onboard LEDs
      output[7:0]led,
      // AVR SPI connections
      output spi_miso,
      input spi_ss,
      input spi_mosi,
      input spi_sck,
      // AVR ADC channel select
      output [3:0] spi_channel,
      // Serial connections
      input avr_tx, // AVR Tx =&gt; FPGA Rx
      output avr_rx, // AVR Rx =&gt; FPGA Tx
      input avr_rx_busy // AVR Rx buffer full
  
      );
  
  // these signals should be high-z when not used
  assign spi_miso = 1'bz;
  assign avr_rx = 1'bz;
  assign spi_channel = 4'bzzzz;
  
  wire rst = ~rst_n; // make reset active high
  
  genvar i;
  generate
    for (i=0; i&lt;4; i=i+1) begin: clocks
      wire clk_slow;
      slow_clock #(.FREQ(2**i)) clk1 (
        .clk(clk),
        .rst(rst),
        .clk_out(clk_slow)
      );
      assign led[i] = clk_slow;
    end
  endgenerate
  
  always @(*) begin
    for (k=0; k&lt;4; k=k+1) begin
      assign led[4+k] = clocks[k].clk_slow; // Why can't I do this?
    end
  end
  
  endmodule
  </code></pre>
  
  <p>I'm generating 4 clocks (1Hz, 2Hz, 4Hz, and 8Hz).In the always block at the end, I have this line: <code>led[4+k] = clocks[k].clk_slow;</code> to try to assign these 4 clocks each to a different led (<code>led[7:4]</code>).
  The error is complaining about the <code>.</code> after <code>clocks[k]</code>. I wondered if I'm not allowed to have a variable index on the right hand side, but when I put just <code>led[4+k] = clocks[k]</code>, there is no syntax error (though it obviously will get a different error when I build it).</p>
  
  <p>Why can I have <code>led[4+k] = clocks[k]</code> but not <code>led[4+k] = clocks[k].clk_slow</code>? Am I supposed to do this with a different syntax? Is it impossible to do it with a for-loop as I have here?</p>
  
  <p><strong>EDIT:</strong>
  In case anyone is wondering, here's the specific error I'm getting. Again, it looks like it's just complaining that I did anything once I indexed the specific generate block I wanted.</p>
  
  <p><code>Line 46, Column 24 : extraneous input '.' expecting {';', '[', '&lt;=', '*', '+', '-', '?', '&amp;', '|', '^', '~^', '^~', '/', '%', '==', '!=', '===', '!==', '&amp;&amp;', '||', '**', '&lt;', '&gt;', '&gt;=', '&gt;&gt;', '&lt;&lt;', '&gt;&gt;&gt;', '&lt;&lt;&lt;'}</code></p>
  
  <p>I should also mention that <code>led[4+k] = clocks[0].clk_slow</code> is okay. It lets me do <code>led[4+k] = clocks[0].clk_slow</code>, but not <code>led[4+k] = clocks[k].clk_slow</code>.</p>