title: Calling one module from another
body: <p>I am trying to call one of the 2 modules (fifo_test_1 or fifo_test_2) depending on the value of bit <code>data[0]</code> in the following Verilog code.</p>
  
  <pre><code>module VC_selector(data);
  
    input [10:0] data;
  
    always @ (data[0])
    begin
      if(~data[0])
      begin
        fifo_test_1 t1(.buf_in(data));
      end
      else if (data[0])
      begin
        fifo_test_2 t2 (.buf_in(data));
      end
    end
  endmodule
  </code></pre>
  
  <p>fifo_test_1 and fifo_test_2 modules are working fine. But the above code gives these errors:</p>
  
  <blockquote>
    <p>** Error: C:/Users/Swayam/Documents/VC_selector.v(8): Undefined variable: fifo_test_1.<br/>
    ** Error: C:/Users/Swayam/Documents/VC_selector.v(8): near "t1": syntax error, unexpected IDENTIFIER<br/>
    ** Error: C:/Users/Swayam/Documents/VC_selector.v(12): Undefined variable: fifo_test_2.<br/>
    ** Error: C:/Users/Swayam/Documents/VC_selector.v(12): near "t2": syntax error, unexpected IDENTIFIER</p>
  </blockquote>
  
  <p>Please help me debug the code.</p>