title: How to get MAX or MIN in Verilog?
body: <p>I want to build a simple module to compare two 2-bit numbers and get the maximum number in the output.</p>
  
  <p>I've used the code posted here: <a href="https://stackoverflow.com/questions/20599522/how-to-find-max-or-min-in-verilog-coding">How to find MAX or MIN in Verilog coding?</a></p>
  
  <pre><code>module max (input [1:0] a, 
              input [1:0] b, 
              output reg [1:0] out);
    always @* begin
      if (a&gt;b)
        out = a;
      else
        out = b;
    end
  endmodule
  </code></pre>
  
  <p>But the problem I have, is that the output "out" does not give me a 2-bit number, and also the code is not working well as you can see in the screenshot.</p>
  
  <p>This is the testbench I'm using:</p>
  
  <pre><code>`timescale 1ns/10ps
  module maxTB();
  reg [1:0] a, b;
  
  max dut (.a(a),.b(b),.out(out)); 
  
  initial
  begin
  a = 2'b1; b= 2'b0;
  #20 a = 2'b10;
  #40 b = 2'b11;
  #50 a = 2'b01;
  end
  endmodule
  </code></pre>
  
  <p><a href="https://i.stack.imgur.com/4dzyP.png" rel="nofollow noreferrer">modelsim screenshot</a></p>