title: "expected type void" - VHDL function error
body: <p>I've written a simple function which does log2 computation of any integer number and then "ceils" it to the next integer:</p>
  
  <pre><code>function log2ceil(intVal: integer) return natural is
      variable i        : natural;
      variable bitCount : natural;
  begin
  
      i := (intVal - 1);
      bitCount := 0;
  
      while (i &gt; 0) loop
          bitCount := bitCount + 1;
          i:=shiftRightInt(i,1);
      end loop;
  
      return bitCount;
  end log2ceil;
  </code></pre>
  
  <hr>
  
  <pre><code>function shiftRightInt(ValueToShift: integer; NrToShift:natural) return integer is
  begin
      return to_integer(shift_right(to_unsigned(ValueToShift, 32), NrToShift));
  end shiftRightInt; 
  </code></pre>
  
  <p>Works, fine. The problem is with the simulation. Every time I try to simulate it with a simple function call in a test bench:</p>
  
  <pre><code>stim: process
  begin
      wait for 10 ns;
      log2ceil(3);
      wait;
  end process;
  </code></pre>
  
  <p>it gives me following error:</p>
  
  <pre><code>ERROR: [VRFC 10-1472] type error near log2ceil ; expected type  void 
  </code></pre>
  
  <p>Why does it expect type Void? And how can I avoid getting this error?</p>