title: sequential execution in process statement in vhdl
body: <p>for process statement in vhdl, it is said that the order of execution inside a process statement is sequential. My question is that, please look at the code below first, are a, b and c signals assigned to their new values concurrently or sequentially in if statement which is in process statement?</p>
  
  <pre><code>   process(clk) is
     begin
     if rising_edge(clk) then
     a &lt;= b ;
     b &lt;= c ;
     c &lt;= a;
     end if;
     end process;
  </code></pre>
  
  <p>So if this is sequential, I must say that after the end of process, a is equal to b, b is equal to c and c is equal to b because we assigned b to a before we assigned a to c. However, this does seem not possible for hardware to do.</p>