title: What is need of Assign/Deassign in Verilog?
body: <p>I am here giving here 2 Verilog modules, which during simulation behaves same. But I don't understand that why to use <code>assign</code>/<code>deassign</code> in these modules, i.e. what is the difference between these 2 codes?</p>
  
  <pre><code>// Code 1 - Without assign-deassign
  module dff (q,qbar,clk,reset,d)
    input clk, reset, d;
    output reg q, qbar;
  
    always @ (posedge reset, negedge clk)
    begin
      if(reset)
      begin
        q=1;
        qbar=0;
      end
      else
      begin
        q=d;
        qbar=~d;
      end
    end
  endmodule
  
  // Code 2 - With assign-deassign
  module dff (q,qbar,clk,reset,d)
    input clk, reset, d;
    output reg q, qbar;
  
    always @ (negedge clk)
    begin
      q=d;
      qbar=~d;
    end
  
    always @ (reset)
    begin
      if(reset)
      begin
        assign q=1;
        assign qbar=0;
      end
      else
      begin
        deassign q;
        deassign qbar;
      end
    end
  endmodule
  </code></pre>