title: system verilog always within always
body: <p>I am wondering if this syntax is allowed</p>
  
  <pre><code>always_comb begin
      case (aaa)
      3'b000: always #(CLKREF_HALF_PERIOD + 5000ps) xclk=~xclk ;//000 at 80MHZ :
      3'b001: always #(3750ps + CLKREF_HALF_PERIOD) xclk=~xclk;//001 at 100MHZ
      3'b010: always #(1250ps + CLKREF_HALF_PERIOD) xclk=~xclk;//010 at 200MHZ
      3'b011: always #(0.252ns + CLKREF_HALF_PERIOD) xclk=~xclk;//011 at 333MHZ
      3'b100: always #(0.112ns + CLKREF_HALF_PERIOD) xclk=~xclk;//100 at 367MHZ
  
      default always #(CLKREF_HALF_PERIOD/1) xclk=~xclk;//default at 400MHZ   
              endcase 
  </code></pre>
  
  <p>I am getting compilation errors regarding the nested always within the cases. 
  i am trying to get the clock freq to change depending on the input of aaa.
  however the question is more of a question on "if an always within an always block is legal or not" </p>