title: How can I force Make to execute a recipe all the time
body: <p>The current Makefile has something like this:</p>
  
  <pre><code>target1 : lib1.a  lib2.a
  
  target2 : lib1.a  lib3.a
  
  target3 : lib3.a 
  
  lib1.a:
      $(MAKE) -C sub_dir all
  </code></pre>
  
  <p>I want to change this Makefile so that wherever a target depends on <code>lib1.a</code>, it always run the command "<code>$(MAKE) -C sub_dir all</code>", always. Another words, in the above example, target1 and target2 will always run "<code>$(MAKE) -C sub_dir all</code>". Is there any way I can do that?</p>
  
  <p>I know the following does not work:</p>
  
  <pre><code>target1 :  lib2.a
      $(MAKE) -C sub_dir all
  
  target2 :   lib3.a
      $(MAKE) -C sub_dir all
  
  target3 : lib3.a 
  </code></pre>
  
  <p>Because if lib2.a has no update, the the command does not run. I have one restriction, I only control lib1.a, I cannot change how lib2.a is built.</p>
  
  <p>Any help is appreciated!</p>
  
  <hr>
  
  <p><strong>UPDATE</strong>: I used the following solution:</p>
  
  <pre><code>target1 : lib1.a  lib2.a
  
  target2 : lib1.a  lib3.a
  
  target3 : lib3.a 
  
  lib1.a: relay
  
  .PHONY: relay
  relay:
      $(MAKE) -C sub_dir all
  </code></pre>
  
  <p>The <a href="https://www.gnu.org/software/make/manual/html_node/Force-Targets.html" rel="noreferrer">GNU Make help</a> says that FORCE is not as efficient as .PHONY, but from your explanation, it seems to me FORCE is better. Do I mis-understand?</p>