title: How to get rid of a fitter warning about LVDS complement pin?
body: <p>I have a clock input to the fan-out buffer which drives LVDS input to the bottom edge of PLL input. There are two pins - <code>AJ19</code> (active high) and a complementary <code>AK19</code> pin (active low). I am only interested in <code>AJ19</code>, so my top level module looks like this:</p>
  
  <pre><code>module top(clk, ...);
  ...
  endmodule
  </code></pre>
  
  <p>Here is my pinout for a <code>clk</code>:</p>
  
  <pre><code>set_instance_assignment -name IO_STANDARD LVDS -to clk
  set_location_assignment PIN_AJ19 -to clk
  set_location_assignment PIN_AK19 -to "clk(n)"
  </code></pre>
  
  <p>So far so good, but fitter is generating a very annoying warning that drives me crazy:</p>
  
  <pre><code>Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
  Warning (176674): Following 1 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
      Warning (176118): Pin "clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk(n)"
  </code></pre>
  
  <p>Altera's knowledge base suggested to actually define the clock as a pair (i.e. <code>input wire [1:0] clk</code>) to remove the warning. That doesn't quite help because then you get another warning, saying that input pin does not drive any logic.</p>
  
  <p>I have tried to disable this warning using <code>// altera message_off 176118</code>. That results in error because "176118" is not a valid message ID.</p>
  
  <p>Any suggestions on how to solve this problem?</p>