title: What's the best way to tell if a bus contains a single x in Verilog?
body: <p>I have a test bench that monitors a bus.  Some of the signals (bits) within the bus can be 1'bx.  For a variety of reasons, I need to know if any of the signals within the bus are 1'bx.  What's the best way to test (not for synthesis -- only for simulation purposes) if a bus contains any x's?  I had hoped that I could use a reduction OR and then use <code>===</code>, but this doesn't seem to work.</p>