title: How do fences atomize load-modify-store operations?
body: <p>I have read, putting a fence instruction after a load-modify-store one, like BTS, makes you can treat the second one atomic. But according to the Intel's documentation, the fence instructions are described as</p>
  <blockquote>
  <p>(MFENCE)</p>
  <p>Performs a serializing operation on all load-from-memory and
  store-to-memory instructions that were issued prior the MFENCE
  instruction. This serializing operation guarantees that every load
  and store instruction that precedes the MFENCE instruction in program
  order becomes globally visible before any load or store instruction
  that follows the MFENCE instruction.</p>
  </blockquote>
  <p>So, how does such behavior guarantee the mentioned &quot;atomicity&quot;?</p>
  <p>Specifically, if we have two simultaneous runs of the following code performed by distinct processors, how would the fence prevent from reading 0 into CF in both cases?</p>
  <pre><code>start memory assumption: [addr] contains the word 0
  
  BTS WORD PTR [addr], 0
  MFENCE
  </code></pre>