title: Verilog access specific bits
body: <p>I have problem in accessing 32 most significant and 32 least significant bits in Verilog. I have written the following code but I get the error "Illegal part-select expression" The point here is that I don't have access to a 64 bit register. Could you please help.</p>
  
  <pre><code>`MLT: begin
    if (multState==0) begin
      {C,Res}&lt;={A*B}[31:0];
      multState=1;
    end
    else
    begin
      {C,Res}&lt;={A*B}[63:32];
      multState=2;  
    end
  </code></pre>