title: ChiselTest: Cast a signed int to unsigned int for an expected value
body: <p>I'm having trouble identifying the correct method for converting a signed int to unsigned int for unit testing using the new ChiselTest framework.</p>
  <p>Here is the method I have been using to unit test an ALU (example is 16-bit), the problem is that it is not scalable:</p>
  <pre class="lang-scala prettyprint-override"><code>    test(new ALU) { c =&gt;
      ...
          /* Sub */
          c.io.ctl.poke(Control.ALU_SUB)
          c.io.src0.poke(4321.U)
          c.io.src1.poke(1234.U)
          c.io.out.expect(3087.U)
          c.io.src0.poke(1234.U)
          c.io.src1.poke(4321.U)
          c.io.out.expect(&quot;b_1111_0011_1111_0001&quot;.U) /* 2's compliment */
      }
  </code></pre>
  <p>The problem with this method is that when I generate a 32-bit ALU (which outputs an unsigned int), the unit test will fail because the string will zero extend to 32-bits using the hacky string method above...</p>
  <p>I'd like to rewrite the test like this:</p>
  <pre class="lang-scala prettyprint-override"><code>test(new ALU) { c =&gt;
      /* Sub */
      c.io.ctl.poke(Control.ALU_SUB)
      c.io.src0.poke(4321.U)
      c.io.src1.poke(1234.U)
      c.io.out.expect(3087.U)
      c.io.src0.poke(1234.U)
      c.io.src1.poke(4321.U)
      c.io.out.expect(-3087.S.asUInt)
  }
  </code></pre>
  <p>But, although the design does elaborate, I get the following error:</p>
  <pre class="lang-sh prettyprint-override"><code>[error] (run-main-9) chisel3.internal.ChiselException: Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox.
  [error] chisel3.internal.ChiselException: Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox.
  [error]         at chisel3.internal.throwException$.apply(Error.scala:85)
  [error]         at chisel3.internal.Builder$.forcedUserModule(Builder.scala:298)
  [error]         at chisel3.internal.Builder$.pushOp(Builder.scala:336)
  [error]         at chisel3.SInt.do_asUInt(Bits.scala:925)
  [error]         at cpu.alu$.$anonfun$new$2(Main.scala:26)
  [error]         at cpu.alu$.$anonfun$new$2$adapted(Main.scala:18)
  [error]         at chiseltest.backends.treadle.TreadleBackend.$anonfun$run$1(TreadleBackend.scala:144)
  [error]         at chiseltest.internal.ThreadedBackend$TesterThread$$anon$1.$anonfun$run$1(ThreadedBackend.scala:453)
  [error]         at chiseltest.backends.treadle.TreadleBackend.doTimescope(TreadleBackend.scala:103)
  [error]         at chiseltest.internal.ThreadedBackend$TesterThread$$anon$1.run(ThreadedBackend.scala:453)
  [error]         at java.lang.Thread.run(Thread.java:748)
  [error] stack trace is suppressed; run last Test / bgRunMain for the full output
  [error] Nonzero exit code: 1
  [error] (Test / runMain) Nonzero exit code: 1
  </code></pre>
  <p>I can't figure out the right way of addressing this. Any help would be much appreciated.</p>
  <p>For reference, the ALU is pretty simple, here is the ALU class:</p>
  <pre class="lang-scala prettyprint-override"><code>class ALU extends Module {
    val io = IO(new Bundle {
      val ctl   = Input(UInt(Control.ALU_BITWIDTH))
      val src0  = Input(UInt(Instructions.WORD_SIZE.W))
      val src1  = Input(UInt(Instructions.WORD_SIZE.W))
      val out   = Output(UInt(Instructions.WORD_SIZE.W))
    })
  
    val shift = io.src1(3,0).asUInt
  
    /* Lookup the operation to execute */
    io.out := MuxLookup(io.ctl, 0.U, Seq(
      Control.ALU_ADD -&gt; (io.src0 + io.src1),
      Control.ALU_SUB -&gt; (io.src0 - io.src1),
      Control.ALU_AND -&gt; (io.src0 &amp; io.src1),
      Control.ALU_OR  -&gt; (io.src0 | io.src1),
      Control.ALU_XOR -&gt; (io.src0 ^ io.src1),
      Control.ALU_NOT -&gt; (~io.src0),
      Control.ALU_SLL -&gt; (io.src0 &lt;&lt; shift),
      Control.ALU_SRL -&gt; (io.src0 &gt;&gt; shift),
    ))
  }
  </code></pre>