title: Alignment requirements for atomic x86 instructions vs. MS's InterlockedCompareExchange documentation?
body: <p>Microsoft offers the <a href="http://msdn.microsoft.com/en-us/library/ms683560%28VS.85%29.aspx" rel="nofollow noreferrer"><code>InterlockedCompareExchange</code></a> function for performing atomic compare-and-swap operations. There is also an <a href="https://msdn.microsoft.com/en-us/library/ttk2z1ws.aspx" rel="nofollow noreferrer"><code>_InterlockedCompareExchange</code></a> <em>intrinsic</em>.</p>
  
  <p>On x86 these are implemented using the <code>lock cmpxchg</code> instruction.</p>
  
  <p>However, reading through the documentation on these three approaches, they don't seem to agree on the alignment requirements.</p>
  
  <p>Intel's <a href="http://download.intel.com/design/intarch/manuals/24319101.pdf" rel="nofollow noreferrer">reference manual</a> says nothing about alignment (other than that <em>if</em> alignment checking is enabled and an unaligned memory reference is made, an exception is generated)</p>
  
  <p>I also looked up the <code>lock</code> prefix, which specifically states that</p>
  
  <blockquote>
    <p>The integrity of the LOCK prefix is <strong>not</strong> affected by the alignment of the memory field.</p>
  </blockquote>
  
  <p><em>(emphasis mine)</em></p>
  
  <p>So Intel seems to say that alignment is irrelevant. The operation will be atomic no matter what.</p>
  
  <p>The <code>_InterlockedCompareExchange</code> intrinsic documentation also says nothing about alignment, however the <code>InterlockedCompareExchange</code> <em>function</em> states that</p>
  
  <blockquote>
    <p>The parameters for this function must be aligned on a 32-bit boundary; otherwise, the function will behave unpredictably on multiprocessor x86 systems and any non-x86 systems.</p>
  </blockquote>
  
  <p>So what gives? 
  Are the alignment requirements for <code>InterlockedCompareExchange</code> just to make sure the function will work even on pre-486 CPU's where the <code>cmpxchg</code> instruction isn't available?
  That seems likely based on the above information, but I'd like to be sure before I rely on it. :)</p>
  
  <p>Or is alignment required by the ISA to guarantee atomicity, and I'm just looking the wrong places in Intel's reference manuals?</p>