title: VHDL mux 8:1 error in test bench
body: <p>it is 8x1mux vhdl program 
  main program working with no error,
  but in test their is some signal i,s ,y are shows error 
  and tell i,s,y are already declared.</p>
  
  <p><img src="https://i.stack.imgur.com/Tj75C.png" alt="test bench "></p>
  
  <p>error in test bench</p>
  
  <p><img src="https://i.stack.imgur.com/AhU6U.jpg" alt="enter image description here"></p>