title: Is initial synthesizable in ASIC?
body: <p>I haven't tried to synthesize myself but if someone could help to give a quick answer, that would be highly appreciated.</p>
  
  <p>For a regular RAM, I see people do this in their Verilog, but I am told that initial is not synthesizable in Synopsys Design Compiler and I wonder if there is a difference among tools. Or this is doable just for memory initialization.</p>
  
  <pre><code>initial begin
      for (count=0;count&lt;2048;count=count+1) RAM[count]=0;
  end
  </code></pre>
  
  <p>This is specifically targeting ASIC instead of FPGA or Xilinx. Thanks in advance!</p>