title: System Verilog - case with or
body: <p>How can I create case with or?</p>
  
  <p>Something like:</p>
  
  <pre><code>string str;
  
  case (str)
     "abc" || "dfg": begin
         //some code
     end
     "yfg": begin
         //some code
     end
     default: //some code
  endcase
  </code></pre>