title: Multiple VHDL component instantiation
body: <p>Following general question:</p>
  
  <p>How do I setup following System (Main) with three submodules (SubX, SubY, SubZ):</p>
  
  <pre><code>Main
    |______ SubX
    |         |_______SubZ
    |
    |______ SubZ
  </code></pre>
  
  <p>Here the code:</p>
  
  <pre><code>entity System is
      port (
          clk_clk                                : in  std_logic;     
          pwm    : OUT std_logic 
      );
  end entity System_Misc;
  
  architecture rtl of System is
      component SubX
          port(clk       : IN  STD_LOGIC;
               pwmSubX   : OUT STD_LOGIC;
      end component SubX;
  
      component SubZ
          port(clk       : IN  STD_LOGIC;
               pwmSubZ   : OUT STD_LOGIC;
      end component SubZ;
  
  
  begin
      component SubX
          port map(
              clk      =&gt; clk_clk,
              pwmSubX  =&gt; pwm
          );
  
      component SubZ
          port map(
              clk      =&gt; clk_clk,
              pwmSubZ  =&gt; pwm
          );
  
  
  end architecture rtl;
  </code></pre>
  
  <p>Is this approach correct because <strong>SubZ</strong> is instantiated in <em>Main</em> as well as in <strong>SubX</strong> (not showed here). If I do so, I get an error that I can not connect <em>pwmSubX</em> and <em>pwmSubZ</em> to the same output <strong>pwm</strong> (Main). 
  What is the correct way to solve this issue and/or how would you implement it?</p>
  
  <p>Thanks!</p>