title: What is the correct ARM64(AArch64) data memory barrier usage when reading 64bit timer value from two 32bit timer counters?
body: <p>For the sequence to read 64bit timer value from two 32bit timer counters mentioned in
  <a href="https://developer.arm.com/documentation/100400/0001/multiprocessing/global-timer/global-timer-registers" rel="nofollow noreferrer">https://developer.arm.com/documentation/100400/0001/multiprocessing/global-timer/global-timer-registers</a></p>
  <p>What is the correct way to insert ARM64 memory barriers between the reads?</p>
  <p>Is something like below proper? Can someone please explain how and what data memory barriers to use in this case?</p>
  <pre><code>do {
    high1 = read(base+4);
    asm volatile(&quot;dmb sy&quot;);
    low = read(base);
    asm volatile(&quot;dmb sy&quot;);
    high2 = read(base+4);
    asm volatile(&quot;dmb sy&quot;);
  } while (high2 != high1);
  </code></pre>
  <p>I know question on how to read 64bit timer already exists but there is no detail of memory barrier usage there and I need this for ARM machines - <a href="https://stackoverflow.com/questions/5162673/how-to-read-two-32bit-counters-as-a-64bit-integer-without-race-condition">How to read two 32bit counters as a 64bit integer without race condition</a></p>