title: Verification of Embedded Memory Systems using Efficient Memory Modeling

abstract:
  We describe verification techniques for embedded memory systems using
efficient memory modeling (EMM), without explicitly modeling each memory bit.
We extend our previously proposed approach of EMM in Bounded Model Checking
(BMC) for a single read/write port single memory system, to more commonly
occurring systems with multiple memories, having multiple read and write ports.
More importantly, we augment such EMM to providing correctness proofs, in
addition to finding real bugs as before. The novelties of our verification
approach are in a) combining EMM with proof-based abstraction that preserves
the correctness of a property up to a certain analysis depth of SAT-based BMC,
and b) modeling arbitrary initial memory state precisely and thereby, providing
inductive proofs using SAT-based BMC for embedded memory systems. Similar to
the previous approach, we construct a verification model by eliminating memory
arrays, but retaining the memory interface signals with their control logic and
adding constraints on those signals at every analysis depth to preserve the
data forwarding semantics. The size of these EMM constraints depends
quadratically on the number of memory accesses and the number of read and write
ports; and linearly on the address and data widths and the number of memories.
We show the effectiveness of our approach on several industry designs and
software programs.


title: Integration, Verification and Layout of a Complex Multimedia SOC

abstract:
  We present our experience of designing a single-chip controller for advanced
digital still camera from specification all the way to mass production. The
process involves collaboration with camera system designer, IP vendors, EDA
vendors, silicon wafer foundry, package and testing houses, and camera maker.
We also co-work with academic research groups to develop a JPEG codec IP and
memory BIST and SOC testing methodology. In this presentation, we cover the
problems encountered, our solutions, and lessons learned.


title: A generalization of Tverberg's Theorem

abstract:
  The well know theorem of Tverberg states that if n > (d+1)(r-1) then one can
partition any set of n points in R^d to r disjoint subsets whose convex hulls
have a common point. The numbers T(d,r) = (d + 1)(r - 1) + 1 are known as
Tverberg numbers. Reay asks the following question: if we add an additional
parameter k (1 < k < r+1) what is the minimal number of points we need in order
to guarantee that there exists an r partition of them such that any k of the r
convex hulls intersect. This minimal number is denoted by T(d,r,k). Reay
conjectured that T(d,r,k) = T(d,r) for all d,r and k. In this article we prove
that this is true for the following cases: when k > [ (d+3)/2 ]-1 or when d <
rk/(r-k)-1 and for the specific values d = 3; r = 4; k = 2 and d = 5; r = 3; k
= 2.


title: SOC Testing Methodology and Practice

abstract:
  On a commercial digital still camera (DSC) controller chip we practice a
novel SOC test integration platform, solving real problems in test scheduling,
test IO reduction, timing of functional test, scan IO sharing, embedded memory
built-in self-test (BIST), etc. The chip has been fabricated and tested
successfully by our approach. Test results justify that short test integration
cost, short test time, and small area overhead can be achieved. To support SOC
testing, a memory BIST compiler and an SOC testing integration system have been
developed.


title: Evolutionary Optimization in Code-Based Test Compression

abstract:
  We provide a general formulation for the code-based test compression problem
with fixed-length input blocks and propose a solution approach based on
Evolutionary Algorithms. In contrast to existing code-based methods, we allow
unspecified values in matching vectors, which allows encoding of arbitrary test
sets using a relatively small number of code-words. Experimental results for
both stuck-at and path delay fault test sets for ISCAS circuits demonstrate an
improvement compared to existing techniques.


title: An Application-Specific Design Methodology for STbus Crossbar Generation

abstract:
  As the communication requirements of current and future Multiprocessor
Systems on Chips (MPSoCs) continue to increase, scalable communication
architectures are needed to support the heavy communication demands of the
system. This is reflected in the recent trend that many of the standard bus
products such as STbus, have now introduced the capability of designing a
crossbar with multiple buses operating in parallel. The crossbar configuration
should be designed to closely match the application traffic characteristics and
performance requirements. In this work we address this issue of
application-specific design of optimal crossbar (using STbus crossbar
architecture), satisfying the performance requirements of the application and
optimal binding of cores onto the crossbar resources. We present a simulation
based design approach that is based on analysis of actual traffic trace of the
application, considering local variations in traffic rates, temporal overlap
among traffic streams and criticality of traffic streams. Our methodology is
applied to several MPSoC designs and the resulting crossbar platforms are
validated for performance by cycle-accurate SystemC simulation of the designs.
The experimental case studies show large reduction in packet latencies (up to
7x) and large crossbar component savings (up to 3.5x) compared to traditional
design approaches.


title:
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space
  Redundancy and Local Reconfiguration

abstract:
  As microfluidics-based biochips become more complex, manufacturing yield will
have significant influence on production volume and product cost. We propose an
interstitial redundancy approach to enhance the yield of biochips that are
based on droplet-based microfluidics. In this design method, spare cells are
placed in the interstitial sites within the microfluidic array, and they
replace neighboring faulty cells via local reconfiguration. The proposed design
method is evaluated using a set of concurrent real-life bioassays.


title:
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic
  Biochips

abstract:
  Microfluidics-based biochips are soon expected to revolutionize clinical
diagnosis, DNA sequencing, and other laboratory procedures involving molecular
biology. Most microfluidic biochips are based on the principle of continuous
fluid flow and they rely on permanently-etched microchannels, micropumps, and
microvalves. We focus here on the automated design of "digital" droplet-based
microfluidic biochips. In contrast to continuous-flow systems, digital
microfluidics offers dynamic reconfigurability; groups of cells in a
microfluidics array can be reconfigured to change their functionality during
the concurrent execution of a set of bioassays. We present a simulated
annealing-based technique for module placement in such biochips. The placement
procedure not only addresses chip area, but it also considers fault tolerance,
which allows a microfluidic module to be relocated elsewhere in the system when
a single cell is detected to be faulty. Simulation results are presented for a
case study involving the polymerase chain reaction.


title:
Bars in Disk-Dominated and Bulge-Dominated Galaxies at z~0: New Insights
  from ~3600 SDSS Galaxies

abstract:
  We present a study of large-scale bars in the local Universe, based on a
large sample of ~3692 galaxies, with -18.5 <= M_g < -22.0 mag and redshift 0.01
<= z < 0.03, drawn from the Sloan Digitized Sky Survey. Our sample includes
many galaxies that are disk-dominated and of late Hubble types. Both color cuts
and S\'ersic cuts yield a similar sample of ~2000 disk galaxies. We
characterize bars and disks by ellipse-fitting r-band images and applying
quantitative criteria. After excluding highly inclined ($>60^{\circ}$) systems,
we find the following results. (1) The optical r-band fraction (f_opt-r) of
barred galaxies, when averaged over the whole sample, is ~48%-52%. (2) When
galaxies are separated according to half light radius (r_e), or normalized
r_e/R_24, which is a measure of the bulge-to-disk (B/D) ratio, a remarkable
result is seen: f_opt-r rises sharply, from ~40% in galaxies that have small
r_e/R_24 and visually appear to host prominent bulges, to ~70% for galaxies
that have large r_e/R_24 and appear disk-dominated. (3) $f_{\rm opt-r}$ rises
for galaxies with bluer colors (by ~30%) and lower masses (by ~15%-20%). (4)
While hierarchical $\Lambda$CDM models of galaxy evolution models fail to
produce galaxies without classical bulges, our study finds that ~20% of disk
galaxies appear to be ``quasi-bulgeless''. (5) After applying the same cutoffs
in magnitude (M_V<-19.3 mag), bar size (a_bar >= 1.5 kpc), and bar ellipticity
(e_bar >=~0.4) that studies out to z~1 apply to ensure a complete sample,
adequate spatial resolution, and reliable bar identification, we obtain an
optical r-band bar fraction of 34%. This is comparable to the value reported at
z~0.2-1.0, implying that the optical bar fraction does not decline dramatically
by an order of magnitude in bright galaxies out to z~1. (abridged)


title: A Conversation with Shoutir Kishore Chatterjee

abstract:
  Shoutir Kishore Chatterjee was born in Ranchi, a small hill station in India,
on November 6, 1934. He received his B.Sc. in statistics from the Presidency
College, Calcutta, in 1954, and M.Sc. and Ph.D. degrees in statistics from the
University of Calcutta in 1956 and 1962, respectively. He was appointed a
lecturer in the Department of Statistics, University of Calcutta, in 1960 and
was a member of its faculty until his retirement as a professor in 1997.
Indeed, from the 1970s he steered the teaching and research activities of the
department for the next three decades. Professor Chatterjee was the National
Lecturer in Statistics (1985--1986) of the University Grants Commission, India,
the President of the Section of Statistics of the Indian Science Congress
(1989) and an Emeritus Scientist (1997--2000) of the Council of Scientific and
Industrial Research, India. Professor Chatterjee, affectionately known as SKC
to his students and admirers, is a truly exceptional person who embodies the
spirit of eternal India. He firmly believes that ``fulfillment in man's life
does not come from amassing a lot of money, after the threshold of what is
required for achieving a decent living is crossed. It does not come even from
peer recognition for intellectual achievements. Of course, one has to work and
toil a lot before one realizes these facts.''


title:
Many-body calculations of relativistic energy shifts for single- and
  double-valence atoms

abstract:
  Relativistic Hartree-Fock method together with many-body perturbation theory
and configuration interaction techniques are used to calculate relativistic
energy shifts for frequencies of the strong electric dipole transitions of C
III, C IV, Na I, Mg I, Mg II, Al II, Al III, Si IV, Ca II and Zn II. These
transitions are used for search of the variation of the fine structure constant
in quasar absorption spectra. The results are in good agreement with previous
calculations. The analysis of Breit contributions is also presented.


title: Congruences between modular forms and related modules

abstract:
  We fix $\ell$ a prime and let $M$ be an integer such that $\ell\not|M$; let
$f\in S_2(\Gamma_1(M\ell^2))$ be a newform supercuspidal of fixed type related
to the nebentypus, at $\ell$ and special at a finite set of primes. Let
$\TT^\psi$ be the local quaternionic Hecke algebra associated to $f$. The
algebra $\TT^\psi$ acts on a module $\mathcal M^\psi_f$ coming from the
cohomology of a Shimura curve. Applying the Taylor-Wiles criterion and a recent
Savitt's theorem, $\TT^\psi$ is the universal deformation ring of a global
Galois deformation problem associated to $\orho_f$. Moreover $\mathcal
M^\psi_f$ is free of rank 2 over $\TT^\psi$. If $f$ occurs at minimal level, by
a generalization of a Conrad, Diamond and Taylor's result and by the classical
Ihara's lemma, we prove a theorem of raising the level and a result about
congruence ideals. The extension of this results to the non minimal case is an
open problem.


title: CMOS-Based Biosensor Arrays

abstract:
  CMOS-based sensor array chips provide new and attractive features as compared
to today's standard tools for medical, diagnostic, and biotechnical
applications. Examples for molecule- and cell-based approaches and related
circuit design issues are discussed.


title: DVS for On-Chip Bus Designs Based on Timing Error Correction

abstract:
  On-chip buses are typically designed to meet performance constraints at
worst-case conditions, including process corner, temperature, IR-drop, and
neighboring net switching pattern. This can result in significant performance
slack at more typical operating conditions. In this paper, we propose a dynamic
voltage scaling (DVS) technique for buses, based on a double sampling latch
which can detect and correct for delay errors without the need for
retransmission. The proposed approach recovers the available slack at
non-worst-case operating points through more aggressive voltage scaling and
tracks changing conditions by monitoring the error recovery rate. Voltage
margins needed in traditional designs to accommodate worst-case performance
conditions are therefore eliminated, resulting in a significant improvement in
energy efficiency. The approach was implemented for a 6mm memory read bus
operating at 1.5GHz (0.13 $\mu$m technology node) and was simulated for a
number of benchmark programs. Even at the worst-case process and environment
conditions, energy gains of up to 17% are achieved, with error recovery rates
under 2.3%. At more typical process and environment conditions, energy gains
range from 35% to 45%, with a performance degradation under 2%. An analysis of
optimum interconnect architectures for maximizing energy gains with this
approach shows that the proposed approach performs well with technology
scaling.


title: Energy Bounds for Fault-Tolerant Nanoscale Designs

abstract:
  The problem of determining lower bounds for the energy cost of a given
nanoscale design is addressed via a complexity theory-based approach. This
paper provides a theoretical framework that is able to assess the trade-offs
existing in nanoscale designs between the amount of redundancy needed for a
given level of resilience to errors and the associated energy cost. Circuit
size, logic depth and error resilience are analyzed and brought together in a
theoretical framework that can be seamlessly integrated with automated
synthesis tools and can guide the design process of nanoscale systems comprised
of failure prone devices. The impact of redundancy addition on the switching
energy and its relationship with leakage energy is modeled in detail. Results
show that 99% error resilience is possible for fault-tolerant designs, but at
the expense of at least 40% more energy if individual gates fail independently
with probability of 1%.


title:
A Quality-of-Service Mechanism for Interconnection Networks in
  System-on-Chips

abstract:
  As Moore's Law continues to fuel the ability to build ever increasingly
complex system-on-chips (SoCs), achieving performance goals is rising as a
critical challenge to completing designs. In particular, the system
interconnect must efficiently service a diverse set of data flows with widely
ranging quality-of-service (QoS) requirements. However, the known solutions for
off-chip interconnects such as large-scale networks are not necessarily
applicable to the on-chip environment. Latency and memory constraints for
on-chip interconnects are quite different from larger-scale interconnects. This
paper introduces a novel on-chip interconnect arbitration scheme. We show how
this scheme can be distributed across a chip for high-speed implementation. We
compare the performance of the arbitration scheme with other known interconnect
arbitration schemes. Existing schemes typically focus heavily on either low
latency of service for some initiators, or alternatively on guaranteed
bandwidth delivery for other initiators. Our scheme allows service latency on
some initiators to be traded off smoothly against jitter bounds on other
initiators, while still delivering bandwidth guarantees. This scheme is a
subset of the QoS controls that are available in the SonicsMX? (SMX) product.


title: Applying UML and MDA to Real Systems Design

abstract:
  Traditionally system design has been made from a black box/functionality only
perspective which forces the developer to concentrate on how the functionality
can be decomposed and recomposed into so called components. While this
technique is well established and well known it does suffer fromsome drawbacks;
namely that the systems produced can often be forced into certain, incompatible
architectures, difficult to maintain or reuse and the code itself difficult to
debug. Now that ideas such as the OMG's Model Based Architecture (MDA) or Model
Based Engineering (MBE) and the ubiquitous modelling language UML are being
used (allegedly) and desired we face a number of challenges to existing
techniques.


title: The Challenges of Hardware Synthesis from C-Like Languages

abstract:
  MANY TECHNIQUES for synthesizing digital hardware from C-like languages have
been proposed, but none have emerged as successful as Verilog or VHDL for
register-transfer-level design. This paper looks at two of the fundamental
challenges: concurrency and timing control.


title: Reliability-Centric High-Level Synthesis

abstract:
  Importance of addressing soft errors in both safety critical applications and
commercial consumer products is increasing, mainly due to ever shrinking
geometries, higher-density circuits, and employment of power-saving techniques
such as voltage scaling and component shut-down. As a result, it is becoming
necessary to treat reliability as a first-class citizen in system design. In
particular, reliability decisions taken early in system design can have
significant benefits in terms of design quality. Motivated by this observation,
this paper presents a reliability-centric high-level synthesis approach that
addresses the soft error problem. The proposed approach tries to maximize
reliability of the design while observing the bounds on area and performance,
and makes use of our reliability characterization of hardware components such
as adders and multipliers. We implemented the proposed approach, performed
experiments with several designs, and compared the results with those obtained
by a prior proposal.


title: Reliable System Specification for Self-Checking Data-Paths

abstract:
  The design of reliable circuits has received a lot of attention in the past,
leading to the definition of several design techniques introducing fault
detection and fault tolerance properties in systems for critical
applications/environments. Such design methodologies tackled the problem at
different abstraction levels, from switch-level to logic, RT level, and more
recently to system level. Aim of this paper is to introduce a novel
system-level technique based on the redefinition of the operators functionality
in the system specification. This technique provides reliability properties to
the system data path, transparently with respect to the designer. Feasibility,
fault coverage, performance degradation and overheads are investigated on a FIR
circuit.


title: Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores

abstract:
  Many SOCs today contain both digital and analog embedded cores. Even though
the test cost for such mixed-signal SOCs is significantly higher than that for
digital SOCs, most prior research in this area has focused exclusively on
digital cores. We propose a low-cost test development methodology for
mixed-signal SOCs that allows the analog and digital cores to be tested in a
unified manner, thereby minimizing the overall test cost. The analog cores in
the SOC are wrapped such that they can be accessed using a digital test access
mechanism (TAM). We evaluate the impact of the use of analog test wrappers on
area overhead and test time. To reduce area overhead, we present an analog test
wrapper optimization technique, which is then combined with TAM optimization in
a cost-oriented heuristic approach for test scheduling. We also demonstrate the
feasibility of using analog wrappers by presenting transistor-level simulations
for an analog wrapper and a representative core. We present experimental
results on test scheduling for an ITC'02 benchmark SOC that has been augmented
with five analog cores.


title:
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of
  System Chips

abstract:
  Multi-site testing is a popular and effective way to increase test throughput
and reduce test costs. We present a test throughput model, in which we focus on
wafer testing, and consider parameters like test time, index time,
abort-on-fail, and contact yield. Conventional multi-site testing requires
sufficient ATE resources, such as ATE channels, to allow to test multiple SOCs
in parallel. In this paper, we design and optimize on-chip DfT, in order to
maximize the test throughput for a given SOC and ATE. The on-chip DfT consists
of an E-RPCT wrapper, and, for modular SOCs, module wrappers and TAMs. We
present experimental results for a Philips SOC and several ITC'02 SOC Test
Benchmarks.


title:
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based
  FPGAs

abstract:
  Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for
SRAM-based FPGA. However, one of the main challenges in achieving 100%
robustness in designs protected by TMR running on programmable platforms is to
prevent upsets in the routing from provoking undesirable connections between
signals from distinct redundant logic parts, which can generate an error in the
output. This paper investigates the optimal design of the TMR logic (e.g., by
cleverly inserting voters) to ensure robustness. Four different versions of a
TMR digital filter were analyzed by fault injection. Faults were randomly
inserted straight into the bitstream of the FPGA. The experimental results
presented in this paper demonstrate that the number and placement of voters in
the TMR design can directly affect the fault tolerance, ranging from 4.03% to
0.98% the number of upsets in the routing able to cause an error in the TMR
circuit.


title:
Functional Equivalence Checking for Verification of Algebraic
  Transformations on Array-Intensive Source Code

abstract:
  Development of energy and performance-efficient embedded software is
increasingly relying on application of complex transformations on the critical
parts of the source code. Designers applying such nontrivial source code
transformations are often faced with the problem of ensuring functional
equivalence of the original and transformed programs. Currently they have to
rely on incomplete and time-consuming simulation. Formal automatic verification
of the transformed program against the original is instead desirable. This
calls for equivalence checking tools similar to the ones available for
comparing digital circuits. We present such a tool to compare array-intensive
programs related through a combination of important global transformations like
expression propagations, loop and algebraic transformations. When the
transformed program fails to pass the equivalence check, the tool provides
specific feedback on the possible locations of errors.


title: RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power

abstract:
  This paper presents a novel repeater insertion algorithm for interconnect
power minimization. The novelty of our approach is in the judicious integration
of an analytical solver and a dynamic programming based method. Specifically,
the analytical solver chooses a concise repeater library and a small set of
repeater location candidates such that the dynamic programming algorithm can be
performed fast with little degradation of the solution quality. In comparison
with previously reported repeater insertion schemes, within comparable
runtimes, our approach achieves up to 37% higher power savings. Moreover, for
the same design quality, our scheme attains a speedup of two orders of
magnitude.


title:
An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer
  Types

abstract:
  Buffer insertion is a popular technique to reduce the interconnect delay. The
classic buffer insertion algorithm of van Ginneken has time complexity O(n^2),
where n is the number of buffer positions. Lillis, Cheng and Lin extended van
Ginneken's algorithm to allow b buffer types in time O (b^2 n^2). For modern
design libraries that contain hundreds of buffers, it is a serious challenge to
balance the speed and performance of the buffer insertion algorithm. In this
paper, we present a new algorithm that computes the optimal buffer insertion in
O (bn^2) time. The reduction is achieved by the observation that the (Q, C)
pairs of the candidates that generate the new candidates must form a convex
hull. On industrial test cases, the new algorithm is faster than the previous
best buffer insertion algorithms by orders of magnitude.


title: Cantilever-Based Biosensors in CMOS Technology

abstract:
  Single-chip CMOS-based biosensors that feature microcantilevers as transducer
elements are presented. The cantilevers are functionalized for the capturing of
specific analytes, e.g., proteins or DNA. The binding of the analyte changes
the mechanical properties of the cantilevers such as surface stress and
resonant frequency, which can be detected by an integrated Wheatstone bridge.
The monolithic integrated readout allows for a high signal-to-noise ratio,
lowers the sensitivity to external interference and enables autonomous device
operation.


title:
Memory Testing Under Different Stress Conditions: An Industrial
  Evaluation

abstract:
  This paper presents the effectiveness of various stress conditions (mainly
voltage and frequency) on detecting the resistive shorts and open defects in
deep sub-micron embedded memories in an industrial environment. Simulation
studies on very-low voltage, high voltage and at-speed testing show the need of
the stress conditions for high quality products; i.e., low defect-per-million
(DPM) level, which is driving the semiconductor market today. The above test
conditions have been validated to screen out bad devices on real silicon (a
test-chip) built on CMOS 0.18 um technology. IFA (inductive fault analysis)
based simulation technique leads to an efficient fault coverage and DPM
estimator, which helps the customers upfront to make decisions on test
algorithm implementations under different stress conditions in order to reduce
the number of test escapes.


title:
Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum
  Gates Using Multiple-Valued Logic and Group Theory

abstract:
  We propose an approach to optimally synthesize quantum circuits from
non-permutative quantum gates such as Controlled-Square-Root-of-Not (i.e.
Controlled-V). Our approach reduces the synthesis problem to multiple-valued
optimization and uses group theory. We devise a novel technique that transforms
the quantum logic synthesis problem from a multi-valued constrained
optimization problem to a group permutation problem. The transformation enables
us to utilize group theory to exploit the properties of the synthesis problem.
Assuming a cost of one for each two-qubit gate, we found all reversible
circuits with quantum costs of 4, 5, 6, etc, and give another algorithm to
realize these reversible circuits with quantum gates.


title: SAT-Based Complete Don't-Care Computation for Network Optimization

abstract:
  This paper describes an improved approach to Boolean network optimization
using internal don't-cares. The improvements concern the type of don't-cares
computed, their scope, and the computation method. Instead of the traditionally
used compatible observability don't-cares (CODCs), we introduce and justify the
use of complete don't-cares (CDC). To ensure the robustness of the don't-care
computation for very large industrial networks, a optional windowing scheme is
implemented that computes substantial subsets of the CDCs in reasonable time.
Finally, we give a SAT-based don't-care computation algorithm that is more
efficient than BDD-based algorithms. Experimental results confirm that these
improvements work well in practice. Complete don't-cares allow for a reduction
in the number of literals compared to the CODCs. Windowing guarantees
robustness, even for very large benchmarks on which previous methods could not
be applied. SAT reduces the runtime and enhances robustness, making don't-cares
affordable for a variety of other Boolean methods applied to the network.


title:
Avoiding closed timelike curves with a collapsing rotating null dust
  shell

abstract:
  We present an idealised model of gravitational collapse, describing a
collapsing rotating cylindrical shell of null dust in flat space, with the
metric of a spinning cosmic string as the exterior. We find that the shell
bounces before closed timelike curves can be formed. Our results also suggest
slightly different definitions for the mass and angular momentum of the string.


title: Statistical Timing Based Optimization using Gate Sizing

abstract:
  The increased dominance of intra-die process variations has motivated the
field of Statistical Static Timing Analysis (SSTA) and has raised the need for
SSTA-based circuit optimization. In this paper, we propose a new sensitivity
based, statistical gate sizing method. Since brute-force computation of the
change in circuit delay distribution to gate size change is computationally
expensive, we propose an efficient and exact pruning algorithm. The pruning
algorithm is based on a novel theory of perturbation bounds which are shown to
decrease as they propagate through the circuit. This allows pruning of gate
sensitivities without complete propagation of their perturbations. We apply our
proposed optimization algorithm to ISCAS benchmark circuits and demonstrate the
accuracy and efficiency of the proposed method. Our results show an improvement
of up to 10.5% in the 99-percentile circuit delay for the same circuit area,
using the proposed statistical optimizer and a run time improvement of up to
56x compared to the brute-force approach.


title: Automated Synthesis of Assertion Monitors using Visual Specifications

abstract:
  Automated synthesis of monitors from high-level properties plays a
significant role in assertion-based verification. We present here a methodology
to synthesize assertion monitors from visual specifications given in CESC
(Clocked Event Sequence Chart). CESC is a visual language designed for
specifying system level interactions involving single and multiple clock
domains. It has well-defined graphical and textual syntax and formal semantics
based on synchronous language paradigm enabling formal analysis of
specifications. In this paper we provide an overview of CESC language with few
illustrative examples. The algorithm for automated synthesis of assertion
monitors from CESC specifications is described. A few examples from standard
bus protocols (OCP-IP and AMBA) are presented to demonstrate the application of
monitor synthesis algorithm.


title:
Characterization of quantum angular-momentum fluctuations via principal
  components

abstract:
  We elaborate an approach to quantum fluctuations of angular momentum based on
the diagonalization of the covariance matrix in two versions: real symmetric
and complex Hermitian. At difference with previous approaches this is SU(2)
invariant and avoids any difficulty caused by nontrivial commutators.
Meaningful uncertainty relations are derived which are nontrivial even for
vanishing mean angular momentum. We apply this approach to some relevant
states.


title:
A Decompilation Approach to Partitioning Software for
  Microprocessor/FPGA Platforms

abstract:
  In this paper, we present a software compilation approach for
microprocessor/FPGA platforms that partitions a software binary onto custom
hardware implemented in the FPGA. Our approach imposes less restrictions on
software tool flow than previous compiler approaches, allowing software
designers to use any software language and compiler. Our approach uses a
back-end partitioning tool that utilizes decompilation techniques to recover
important high-level information, resulting in performance comparable to
high-level compiler-based approaches.


title:
A Prediction Packetizing Scheme for Reducing Channel Traffic in
  Transaction-Level Hardware/Software Co-Emulation

abstract:
  This paper presents a scheme for efficient channel usage between simulator
and accelerator where the accelerator models some RTL sub-blocks in the
accelerator-based hardware/software co-simulation while the simulator runs
transaction-level model of the remaining part of the whole chip being verified.
With conventional simulation accelerator, evaluations of simulator and
accelerator alternate at every valid simulation time, which results in poor
simulation performance due to startup overhead of simulator-accelerator channel
access. The startup overhead can be reduced by merging multiple transactions on
the channel into a single burst traffic. We propose a predictive packetizing
scheme for reducing channel traffic by merging as many transactions into a
burst traffic as possible based on 'prediction and rollback.' Under ideal
condition with 100% prediction accuracy, the proposed method shows a
performance gain of 1500% compared to the conventional one.


title:
A Register Allocation Algorithm in the Presence of Scalar Replacement
  for Fine-Grain Configurable Architectures

abstract:
  The aggressive application of scalar replacement to array references
substantially reduces the number of memory operations at the expense of a
possibly very large number of registers. In this paper we describe a register
allocation algorithm that assigns registers to scalar replaced array references
along the critical paths of a computation, in many cases exploiting the
opportunity for concurrent memory accesses. Experimental results, for a set of
image/signal processing code kernels, reveal that the proposed algorithm leads
to a substantial reduction of the number of execution cycles for the
corresponding hardware implementation on a contemporary
Field-Programmable-Gate-Array (FPGA) when compared to other greedy allocation
algorithms, in some cases, using even fewer number of registers.


title:
A Way Memoization Technique for Reducing Power Consumption of Caches in
  Application Specific Integrated Processors

abstract:
  This paper presents a technique for eliminating redundant cache-tag and
cache-way accesses to reduce power consumption. The basic idea is to keep a
small number of Most Recently Used (MRU) addresses in a Memory Address Buffer
(MAB) and to omit redundant tag and way accesses when there is a MAB-hit. Since
the approach keeps only tag and set-index values in the MAB, the energy and
area overheads are relatively small even for a MAB with a large number of
entries. Furthermore, the approach does not sacrifice the performance. In other
words, neither the cycle time nor the number of executed cycles increases. The
proposed technique has been applied to Fujitsu VLIW processor (FR-V) and its
power saving has been estimated using NanoSim. Experiments for 32kB 2-way set
associative caches show the power consumption of I-cache and D-cache can be
reduced by 40% and 50%, respectively.


title:
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable
  Architecture for Domain-Specific Optimization

abstract:
  Coarse-grained reconfigurable architectures aim to achieve both goals of high
performance and flexibility. However, existing reconfigurable array
architectures require many resources without considering the specific
application domain. Functional resources that take long latency and/or large
area can be pipelined and/or shared among the processing elements. Therefore
the hardware cost and the delay can be effectively reduced without any
performance degradation for some application domains. We suggest such
reconfigurable array architecture template and design space exploration flow
for domain-specific optimization. Experimental results show that our approach
is much more efficient both in performance and area compared to existing
reconfigurable architectures.


title:
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores
  using Dynamic Hardware/Software Partitioning

abstract:
  Field programmable gate arrays (FPGAs) provide designers with the ability to
quickly create hardware circuits. Increases in FPGA configurable logic capacity
and decreasing FPGA costs have enabled designers to more readily incorporate
FPGAs in their designs. FPGA vendors have begun providing configurable soft
processor cores that can be synthesized onto their FPGA products. While FPGAs
with soft processor cores provide designers with increased flexibility, such
processors typically have degraded performance and energy consumption compared
to hard-core processors. Previously, we proposed warp processing, a technique
capable of optimizing a software application by dynamically and transparently
re-implementing critical software kernels as custom circuits in on-chip
configurable logic. In this paper, we study the potential of a MicroBlaze
soft-core based warp processing system to eliminate the performance and energy
overhead of a soft-core processor compared to a hard-core processor. We
demonstrate that the soft-core based warp processor achieves average speedups
of 5.8 and energy reductions of 57% compared to the soft core alone. Our data
shows that a soft-core based warp processor yields performance and energy
consumption competitive with existing hard-core processors, thus expanding the
usefulness of soft processor cores on FPGAs to a broader range of applications.


title:
An Infrastructure to Functionally Test Designs Generated by Compilers
  Targeting FPGAs

abstract:
  This paper presents an infrastructure to test the functionality of the
specific architectures output by a high-level compiler targeting dynamically
reconfigurable hardware. It results in a suitable scheme to verify the
architectures generated by the compiler, each time new optimization techniques
are included or changes in the compiler are performed. We believe this kind of
infrastructure is important to verify, by functional simulation, further
research techniques, as far as compilation to Field-Programmable Gate Array
(FPGA) platforms is concerned.


title:
Energy- and Performance-Driven NoC Communication Architecture Synthesis
  Using a Decomposition Approach

abstract:
  In this paper, we present a methodology for customized communication
architecture synthesis that matches the communication requirements of the
target application. This is an important problem, particularly for
network-based implementations of complex applications. Our approach is based on
using frequently encountered generic communication primitives as an alphabet
capable of characterizing any given communication pattern. The proposed
algorithm searches through the entire design space for a solution that
minimizes the system total energy consumption, while satisfying the other
design constraints. Compared to the standard mesh architecture, the customized
architecture generated by the newly proposed approach shows about 36%
throughput increase and 51% reduction in the energy required to encrypt 128
bits of data with a standard encryption algorithm.


title: Discovery potential of the LHC for extended gauge symmetries

abstract:
  Many models of physics beyond the Standard Model are based on extended gauge
symmetries and predict the existence of new heavy particles, often at the TeV
scale. Such particles include heavy W and Z bosons, doubly charged higgses,
heavy majorana neutrinos, leptoquarks and heavy fermions. The discovery
potential of the LHC, which will start in 2008, for various particles predicted
in extended gauge theories will be described in this paper.


title: Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

abstract:
  This special session adresses the problems that designers face when
implementing analog and digital circuits in nanometer technologies. An
introductory embedded tutorial will give an overview of the design problems at
hand : the leakage power and process variability and their implications for
digital circuits and memories, and the reducing supply voltages, the design
productivity and signal integrity problems for embedded analog blocks. Next, a
panel of experts from both industrial semiconductor houses and design
companies, EDA vendors and research institutes will present and discuss with
the audience their opinions on whether the design road ends at marker "65nm" or
not.


title: HEBS: Histogram Equalization for Backlight Scaling

abstract:
  In this paper, a method is proposed for finding a pixel transformation
function that maximizes backlight dimming while maintaining a pre-specified
image distortion level for a liquid crystal display. This is achieved by
finding a pixel transformation function, which maps the original image
histogram to a new histogram with lower dynamic range. Next the contrast of the
transformed image is enhanced so as to compensate for brightness loss that
would arise from backlight dimming. The proposed approach relies on an accurate
definition of the image distortion which takes into account both the pixel
value differences and a model of the human visual system and is amenable to
highly efficient hardware realization. Experimental results show that the
histogram equalization for backlight scaling method results in about 45% power
saving with an effective distortion rate of 5% and 65% power saving for a 20%
distortion rate. This is significantly higher power savings compared to
previously reported backlight dimming approaches.


title: FPGA Architecture for Multi-Style Asynchronous Logic

abstract:
  This paper presents a novel FPGA architecture for implementing various styles
of asynchronous logic. The main objective is to break the dependency between
the FPGA architecture dedicated to asynchronous logic and the logic style. The
innovative aspects of the architecture are described. Moreover the structure is
well suited to be rebuilt and adapted to fit with further asynchronous logic
evolutions thanks to the architecture genericity. A full-adder was implemented
in different styles of logic to show the architecture flexibility.


title: An Accurate SER Estimation Method Based on Propagation Probability

abstract:
  In this paper, we present an accurate but very fast soft error rate (SER)
estimation technique for digital circuits based on error propagation
probability (EPP) computation. Experiments results and comparison of the
results with the random simulation technique show that our proposed method is
on average within 6% of the random simulation method and four to five orders of
magnitude faster.


title:
Improving the Process-Variation Tolerance of Digital Circuits Using Gate
  Sizing and Statistical Techniques

abstract:
  A new approach for enhancing the process-variation tolerance of digital
circuits is described. We extend recent advances in statistical timing analysis
into an optimization framework. Our objective is to reduce the performance
variance of a technology-mapped circuit where delays across elements are
represented by random variables which capture the manufacturing variations. We
introduce the notion of statistical critical paths, which account for both
means and variances of performance variation. An optimization engine is used to
size gates with a goal of reducing the timing variance along the statistical
critical paths. We apply a pair of nested statistical analysis methods
deploying a slower more accurate approach for tracking statistical critical
paths and a fast engine for evaluation of gate size assignments. We derive a
new approximation for the max operation on random variables which is deployed
for the faster inner engine. Circuit optimization is carried out using a
gain-based algorithm that terminates when constraints are satisfied or no
further improvements can be made. We show optimization results that demonstrate
an average of 72% reduction in performance variation at the expense of average
20% increase in design area.


title:
Assertion-Based Design Exploration of DVS in Network Processor
  Architectures

abstract:
  With the scaling of technology and higher requirements on performance and
functionality, power dissipation is becoming one of the major design
considerations in the development of network processors. In this paper, we use
an assertion-based methodology for system-level power/performance analysis to
study two dynamic voltage scaling (DVS) techniques, traffic-based DVS and
execution-based DVS, in a network processor model. Using the automatically
generated distribution analyzers, we analyze the power and performance
distributions and study their trade-offs for the two DVS policies with
different parameter settings such as threshold values and window sizes. We
discuss the optimal configurations of the two DVS policies under different
design requirements. By a set of experiments, we show that the assertion-based
trace analysis methodology is an efficient tool that can help a designer easily
compare and study optimal architectural configurations in a large design space.


title:
Circuit-Level Modeling for Concurrent Testing of Operational Defects due
  to Gate Oxide Breakdown

abstract:
  As device sizes shrink and current densities increase, the probability of
device failures due to gate oxide breakdown (OBD) also increases. To provide
designs that are tolerant to such failures, we must investigate and understand
the manifestations of this physical phenomenon at the circuit and system level.
In this paper, we develop a model for operational OBD defects, and we explore
how to test for faults due to OBD. For a NAND gate, we derive the necessary
input conditions that excite and detect errors due to OBD defects at the gate
level. We show that traditional pattern generators fail to exercise all of
these defects. Finally, we show that these test patterns can be propagated and
justified for a combinational circuit in a manner similar to traditional ATPG.


title: Optimized Generation of Data-Path from C Codes for FPGAs

abstract:
  FPGAs, as computing devices, offer significant speedup over microprocessors.
Furthermore, their configurability offers an advantage over traditional ASICs.
However, they do not yet enjoy high-level language programmability, as
microprocessors do. This has become the main obstacle for their wider
acceptance by application designers. ROCCC is a compiler designed to generate
circuits from C source code to execute on FPGAs, more specifically on CSoCs. It
generates RTL level HDLs from frequently executing kernels in an application.
In this paper, we describe ROCCC's system overview and focus on its data path
generation. We compare the performance of ROCCC-generated VHDL code with that
of Xilinx IPs. The synthesis result shows that ROCCC-generated circuit takes
around 2x ~ 3x area and runs at comparable clock rate.


title:
Multi-Placement Structures for Fast and Optimized Placement in Analog
  Circuit Synthesis

abstract:
  This paper presents the novel idea of multi-placement structures, for a fast
and optimized placement instantiation in analog circuit synthesis. These
structures need to be generated only once for a specific circuit topology. When
used in synthesis, these pre-generated structures instantiate various layout
floorplans for various sizes and parameters of a circuit. Unlike procedural
layout generators, they enable fast placement of circuits while keeping the
quality of the placements at a high level during a synthesis process. The fast
placement is a result of high speed instantiation resulting from the efficiency
of the multi-placement structure. The good quality of placements derive from
the extensive and intelligent search process that is used to build the
multi-placement structure. The target benchmarks of these structures are analog
circuits in the vicinity of 25 modules. An algorithm for the generation of such
multi-placement structures is presented. Experimental results show placement
execution times with an average of a few milliseconds making them usable during
layout-aware synthesis for optimized placements.


title: Noise Figure Evaluation Using Low Cost BIST

abstract:
  A technique for evaluating noise figure suitable for BIST implementation is
described. It is based on a low cost single-bit digitizer, which allows the
simultaneous evaluation of noise figure in several test points of the analog
circuit. The method is also able to benefit from SoC resources, like memory and
processing power. Theoretical background and experimental results are presented
in order to demonstrate the feasibility of the approach.


title: Specification Test Compaction for Analog Circuits and MEMS

abstract:
  Testing a non-digital integrated system against all of its specifications can
be quite expensive due to the elaborate test application and measurement setup
required. We propose to eliminate redundant tests by employing e-SVM based
statistical learning. Application of the proposed methodology to an operational
amplifier and a MEMS accelerometer reveal that redundant tests can be
statistically identified from a complete set of specification-based tests with
negligible error. Specifically, after eliminating five of eleven
specification-based tests for an operational amplifier, the defect escape and
yield loss is small at 0.6% and 0.9%, respectively. For the accelerometer,
defect escape of 0.2% and yield loss of 0.1% occurs when the hot and colt tests
are eliminated. For the accelerometer, this level of Compaction would reduce
test cost by more than half.


title: Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits

abstract:
  Nanometer circuits are becoming increasingly susceptible to soft-errors due
to alpha-particle and atmospheric neutron strikes as device scaling reduces
node capacitances and supply/threshold voltage scaling reduces noise margins.
It is becoming crucial to add soft-error tolerance estimation and optimization
to the design flow to handle the increasing susceptibility. The first part of
this paper presents a tool for accurate soft-error tolerance analysis of
nanometer circuits (ASERTA) that can be used to estimate the soft-error
tolerance of nanometer circuits consisting of millions of gates. The tolerance
estimates generated by the tool match SPICE generated estimates closely while
taking orders of magnitude less computation time. The second part of the paper
presents a tool for soft-error tolerance optimization of nanometer circuits
(SERTOPT) using the tolerance estimates generated by ASERTA. The tool finds
optimal sizes, channel lengths, supply voltages and threshold voltages to be
assigned to gates in a combinational circuit such that the soft-error tolerance
is increased while meeting the timing constraint. Experiments on ISCAS'85
benchmark circuits showed that soft-error rate of the optimized circuit
decreased by as much as 47% with marginal increase in circuit delay.


title: IEEE 1149.4 Compatible ABMs for Basic RF Measurements

abstract:
  An analogue testing standard IEEE 1149.4 is mainly targeted for low-frequency
testing. The problem studied in this paper is extending the standard also for
radio frequency testing. IEEE 1149.4 compatible measurement structures (ABMs)
developed in this study extract the information one is measuring from the radio
frequency signal and represent the result as a DC voltage level. The ABMs
presented in this paper are targeted for power and frequency measurements
operating in frequencies from 1 GHz to 2 GHz. The power measurement error
caused by temperature, supply voltage and process variations is roughly 2 dB
and the frequency measurement error is 0.1 GHz, respectively.


title:
Designer-Driven Topology Optimization for Pipelined Analog to Digital
  Converters

abstract:
  This paper suggests a practical "hybrid" synthesis methodology which
integrates designer-derived analytical models for system-level description with
simulation-based models at the circuit level. We show how to optimize
stage-resolution to minimize the power in a pipelined ADC. Exploration (via
detailed synthesis) of several ADC configurations is used to show that a
4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS
converter in a 0.25 $\mu$m CMOS process.


title:
Simulation Methodology for Analysis of Substrate Noise Impact on Analog
  / RF Circuits Including Interconnect Resistance

abstract:
  This paper reports a novel simulation methodology for analysis and prediction
of substrate noise impact on analog / RF circuits taking into account the role
of the parasitic resistance of the on-chip interconnect in the impact
mechanism. This methodology allows investigation of the role of the separate
devices (also parasitic devices) in the analog / RF circuit in the overall
impact. This way is revealed which devices have to be taken care of (shielding,
topology change) to protect the circuit against substrate noise. The developed
methodology is used to analyze impact of substrate noise on a 3 GHz LC-tank
Voltage Controlled Oscillator (VCO) designed in a high-ohmic 0.18 $\mu$m 1PM6
CMOS technology. For this VCO (in the investigated frequency range from DC to
15 MHz) impact is mainly caused by resistive coupling of noise from the
substrate to the non-ideal on-chip ground interconnect, resulting in analog
ground bounce and frequency modulation. Hence, the presented test-case reveals
the important role of the on-chip interconnect in the phenomenon of substrate
noise impact.


title: Systematic Figure of Merit Computation for the Design of Pipeline ADC

abstract:
  The emerging concept of SoC-AMS leads to research new top-down methodologies
to aid systems designers in sizing analog and mixed devices. This work applies
this idea to the high-level optimization of pipeline ADC. Considering a given
technology, it consists in comparing different configurations according to
their imperfections and their architectures without FFT computation or
time-consuming simulations. The final selection is based on a figure of merit.


title: Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits

abstract:
  This issue discusses the fault-trajectory approach suitability for fault
diagnosis on analog networks. Recent works have shown promising results
concerning a method based on this concept for ATPG for diagnosing faults on
analog networks. Such method relies on evolutionary techniques, where a generic
algorithm (GA) is coded to generate a set of optimum frequencies capable to
disclose faults.


title:
A New Independent Limit on the Cosmological Constant/Dark Energy from
  the Relativistic Bending of Light by Galaxies and Clusters of Galaxies

abstract:
  We derive new limits on the value of the cosmological constant, $\Lambda$,
based on the Einstein bending of light by systems where the lens is a distant
galaxy or a cluster of galaxies. We use an amended lens equation in which the
contribution of $\Lambda$ to the Einstein deflection angle is taken into
account and use observations of Einstein radii around several lens systems. We
use in our calculations a Schwarzschild-de Sitter vacuole exactly matched into
a Friedmann-Robertson-Walker background and show that a $\Lambda$-contribution
term appears in the deflection angle within the lens equation. We find that the
contribution of the $\Lambda$-term to the bending angle is larger than the
second-order term for many lens systems. Using these observations of bending
angles, we derive new limits on the value of $\Lambda$. These limits constitute
the best observational upper bound on $\Lambda$ after cosmological constraints
and are only two orders of magnitude away from the value determined by those
cosmological constraints.


title:
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated
  Oscillator Clock-Recovery Circuit

abstract:
  We present a complete top-down design of a low-power multi-channel clock
recovery circuit based on gated current-controlled oscillators. The flow
includes several tools and methods used to specify block constraints, to design
and verify the topology down to the transistor level, as well as to achieve a
power consumption as low as 5mW/Gbit/s. Statistical simulation is used to
estimate the achievable bit error rate in presence of phase and frequency
errors and to prove the feasibility of the concept. VHDL modeling provides
extensive verification of the topology. Thermal noise modeling based on
well-known concepts delivers design parameters for the device sizing and
biasing. We present two practical examples of possible design improvements
analyzed and implemented with this methodology.


title: Energy-Aware Routing for E-Textile Applications

abstract:
  As the scale of electronic devices shrinks, "electronic textiles"
(e-textiles) will make possible a wide variety of novel applications which are
currently unfeasible. Due to the wearability concerns, low-power techniques are
critical for e-textile applications. In this paper, we address the issue of the
energy-aware routing for e-textile platforms and propose an efficient algorithm
to solve it. The platform we consider consists of dedicated components for
e-textiles, including computational modules, dedicated transmission lines and
thin-film batteries on fiber substrates. Furthermore, we derive an analytical
upper bound for the achievable number of jobs completed over all possible
routing strategies. From a practical standpoint, for the Advanced Encryption
Standard (AES) cipher, the routing technique we propose achieves about fifty
percent of this analytical upper bound. Moreover, compared to the
non-energy-aware counterpart, our routing technique increases the number of
encryption jobs completed by one order of magnitude.


title:
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled
  Bulk-CMOS Logic Circuits

abstract:
  In nanometer scaled CMOS devices significant increase in the subthreshold,
the gate and the reverse biased junction band-to-band-tunneling (BTBT) leakage,
results in the large increase of total leakage power in a logic circuit.
Leakage components interact with each other in device level (through device
geometry, doping profile) and also in the circuit level (through node
voltages). Due to the circuit level interaction of the different leakage
components, the leakage of a logic gate strongly depends on the circuit
topology i.e. number and nature of the other logic gates connected to its input
and output. In this paper, for the first time, we have analyzed loading effect
on leakage and proposed a method to accurately estimate the total leakage in a
logic circuit, from its logic level description considering the impact of
loading and transistor stacking.


title: Strange hadron yields and ratios in heavy ion collisions at RHIC energy

abstract:
  Recent experimental data support the presence of quark coalescence in heavy
ion collisions at RHIC energies. Hadronization of quark matter and hadron
formation in heavy ion collisions can be described by the coalescence process,
and measured data are reproduced successfully. On the other hand, the
theoretical coalescence calculations are based on a non-relativistic
description. Here we investigate the robustness of the coalescence description,
using different wave-function overlap during hadron formation.


title: Leakage-Aware Interconnect for On-Chip Network

abstract:
  On-chip networks have been proposed as the interconnect fabric for future
systems-on-chip and multi-processors on chip. Power is one of the main
constraints of these systems and interconnect consumes a significant portion of
the power budget. In this paper, we propose four leakage-aware interconnect
schemes. Our schemes achieve 10.13%~63.57% active leakage savings and
12.35%~95.96% standby leakage savings across schemes while the delay penalty
ranges from 0% to 4.69%.


title:
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless
  Microsensor Networks: Modeling and Improvement Perspectives

abstract:
  Wireless microsensor networks, which have been the topic of intensive
research in recent years, are now emerging in industrial applications. An
important milestone in this transition has been the release of the IEEE
802.15.4 standard that specifies interoperable wireless physical and medium
access control layers targeted to sensor node radios. In this paper, we
evaluate the potential of an 802.15.4 radio for use in an ultra low power
sensor node operating in a dense network. Starting from measurements carried
out on the off-the-shelf radio, effective radio activation and link adaptation
policies are derived. It is shown that, in a typical sensor network scenario,
the average power per node can be reduced down to 211m mm mW. Next, the energy
consumption breakdown between the different phases of a packet transmission is
presented, indicating which part of the transceiver architecture can most
effectively be optimized in order to further reduce the radio power, enabling
self-powered wireless microsensor networks.


title: Smart Temperature Sensor for Thermal Testing of Cell-Based ICs

abstract:
  In this paper we present a simple and efficient built-in temperature sensor
for thermal monitoring of standard-cell based VLSI circuits. The proposed smart
temperature sensor uses a ring-oscillator composed of complex gates instead of
inverters to optimize their linearity. Simulation results from a 0.18$\mu$m
CMOS technology show that the non-linearity error of the sensor can be reduced
when an adequate set of standard logic gates is selected.


title:
Computational Intelligence Characterization Method of Semiconductor
  Device

abstract:
  Characterization of semiconductor devices is used to gather as much data
about the device as possible to determine weaknesses in design or trends in the
manufacturing process. In this paper, we propose a novel multiple trip point
characterization concept to overcome the constraint of single trip point
concept in device characterization phase. In addition, we use computational
intelligence techniques (e.g. neural network, fuzzy and genetic algorithm) to
further manipulate these sets of multiple trip point values and tests based on
semiconductor test equipments, Our experimental results demonstrate an
excellent design parameter variation analysis in device characterization phase,
as well as detection of a set of worst case tests that can provoke the worst
case variation, while traditional approach was not capable of detecting them.


title: Worst-Case and Average-Case Analysis of n-Detection Test Sets

abstract:
  Test sets that detect each target fault n times (n-detection test sets) are
typically generated for restricted values of n due to the increase in test set
size with n. We perform both a worst-case analysis and an average-case analysis
to check the effect of restricting n on the unmodeled fault coverage of an
(arbitrary) n-detection test set. Our analysis is independent of any particular
test set or test generation approach. It is based on a specific set of target
faults and a specific set of untargeted faults. It shows that, depending on the
circuit, very large values of n may be needed to guarantee the detection of all
the untargeted faults. We discuss the implications of these results.


title: A New Embedded Measurement Structure for eDRAM Capacitor

abstract:
  The embedded DRAM (eDRAM) is more and more used in System On Chip (SOC). The
integration of the DRAM capacitor process into a logic process is challenging
to get satisfactory yields. The specific process of DRAM capacitor and the low
capacitance value (~30F) of this device induce problems of process monitoring
and failure analysis. We propose a new test structure to measure the
capacitance value of each DRAM cell capacitor in a DRAM array. This concept has
been validated by simulation on a 0.18$\mu$m eDRAM technology.


title: Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling

abstract:
  This paper presents new fast exact feasibility tests for uniprocessor
real-time systems using preemptive EDF scheduling. Task sets which are accepted
by previously described sufficient tests will be evaluated in nearly the same
time as with the old tests by the new algorithms. Many task sets are not
accepted by the earlier tests despite them beeing feasible. These task sets
will be evaluated by the new algorithms a lot faster than with known exact
feasibility tests. Therefore it is possible to use them for many applications
for which only sufficient test are suitable. Additionally this paper shows that
the best previous known sufficient test, the best known feasibility bound and
the best known approximation algorithm can be derived from these new tests. In
result this leads to an integrated schedulability theory for EDF.


title: Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique

abstract:
  Complex applications implemented as Systems on Chip (SoCs) demand extensive
use of system level modeling and validation. Their implementation gathers a
large number of complex IP cores and advanced interconnection schemes, such as
hierarchical bus architectures or networks on chip (NoCs). Modeling
applications involves capturing its computation and communication
characteristics. Previously proposed communication weighted models (CWM)
consider only the application communication aspects. This work proposes a
communication dependence and computation model (CDCM) that can simultaneously
consider both aspects of an application. It presents a solution to the problem
of mapping applications on regular NoCs while considering execution time and
energy consumption. The use of CDCM is shown to provide estimated average
reductions of 40% in execution time, and 20% in energy consumption, for current
technologies.


title: Q-DPM: An Efficient Model-Free Dynamic Power Management Technique

abstract:
  When applying Dynamic Power Management (DPM) technique to pervasively
deployed embedded systems, the technique needs to be very efficient so that it
is feasible to implement the technique on low end processor and tight-budget
memory. Furthermore, it should have the capability to track time varying
behavior rapidly because the time varying is an inherent characteristic of real
world system. Existing methods, which are usually model-based, may not satisfy
the aforementioned requirements. In this paper, we propose a model-free DPM
technique based on Q-Learning. Q-DPM is much more efficient because it removes
the overhead of parameter estimator and mode-switch controller. Furthermore,
its policy optimization is performed via consecutive online trialing, which
also leads to very rapid response to time varying behavior.


title: A New Approach to Component Testing

abstract:
  Carefully tested electric/electronic components are a requirement for
effective hardware-in-the-loop tests and vehicle tests in automotive industry.
A new method for definition and execution of component tests is described. The
most important advantage of this method is independance from the test stand. It
therefore offers the oppportunity to build up knowledge over a long period of
time and the ability to share this knowledge with different partners.


title:
Measurement of the spatio-temporal distribution of harmonic and
  transient eddy currents in a liquid metal

abstract:
  Harmonic and transient eddy currents in a liquid metal positioned above an
excitation coil are determined by measuring the voltage drop in a simple
potential probe. The resulting spatio-temporal eddy current field is compared
with the corresponding analytical expressions for a conducting half-space.
Further, a deformation of the eddy current distribution due to a non-conducting
torus immersed into the liquid metal is measured and compared with numerical
results. The method can be generalized to arbitrary geometries, and might help
to validate numerical models for non-destructive testing and magnetic
inductance tomography.


title: Hardware Accelerated Power Estimation

abstract:
  In this paper, we present power emulation, a novel design paradigm that
utilizes hardware acceleration for the purpose of fast power estimation. Power
emulation is based on the observation that the functions necessary for power
estimation (power model evaluation, aggregation, etc.) can be implemented as
hardware circuits. Therefore, we can enhance any given design with "power
estimation hardware", map it to a prototyping platform, and exercise it with
any given test stimuli to obtain power consumption estimates. Our empirical
studies with industrial designs reveal that power emulation can achieve
significant speedups (10X to 500X) over state-of-the-art commercial
register-transfer level (RTL) power estimation tools.


title:
Efficient Solution of Language Equations Using Partitioned
  Representations

abstract:
  A class of discrete event synthesis problems can be reduced to solving
language equations f . X ⊆ S, where F is the fixed component and S the
specification. Sequential synthesis deals with FSMs when the automata for F and
S are prefix closed, and are naturally represented by multi-level networks with
latches. For this special case, we present an efficient computation, using
partitioned representations, of the most general prefix-closed solution of the
above class of language equations. The transition and the output relations of
the FSMs for F and S in their partitioned form are represented by the sets of
output and next state functions of the corresponding networks. Experimentally,
we show that using partitioned representations is much faster than using
monolithic representations, as well as applicable to larger problem instances.


title: Magnetohydrodynamics In The Context Of Nelson's Stochastic Mechanics

abstract:
  A simple generalization of the MHD model accounting for the fluctuations of
the configurations due to kinetic effects in plasmas in short times small
scales is considered. The velocity of conductive fluid and the magnetic field
are considerd as the stochastic fields (or random trial trajectories) for which
the classical MHD equations play the role of the mean field equations in the
spirit of stochastic mechanics of E. Nelson.


title: Embedded Automotive System Development Process

abstract:
  Model based design enables the automatic generation of final-build software
from models for high-volume automotive embedded systems. This paper presents a
framework of processes, methods and tools for the design of automotive embedded
systems. A steer-by-wire system serves as an example.


title:
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in
  SystemC

abstract:
  This paper presents the methodology and the modeling constructs we have
developed to capture the real time aspects of RTOS simulation models in a
System Level Design Language (SLDL) like SystemC. We describe these constructs
and show how they are used to build a simulation model of an RTOS kernel
targeting the $\mu$-ITRON OS specification standard.


title: An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories

abstract:
  Memory cores are usually the densest portion with the smallest feature size
in system-on-chip (SOC) designs. The reliability of memory cores thus has heavy
impact on the reliability of SOCs. Transparent test is one of useful technique
for improving the reliability of memories during life time. This paper presents
a systematic algorithm used for transforming a bit-oriented march test into a
transparent word-oriented march test. The transformed transparent march test
has shorter test complexity compared with that proposed in the previous works
[Theory of transparent BIST for RAMs, A transparent online memory test for
simultaneous detection of functional faults and soft errors in memories]. For
example, if a memory with 32-bit words is tested with March C-, time complexity
of the transparent word-oriented test transformed by the proposed scheme is
only about 56% or 19% time complexity of the transparent word-oriented test
converted by the scheme reported in [Theory of transparent BIST for RAMs] or [A
transparent online memory test for simultaneous detection of functional faults
and soft errors in memories], respectively.


title: Systematic Transaction Level Modeling of Embedded Systems with SystemC

abstract:
  This paper gives an overview of a transaction level modeling (TLM) design
flow for straightforward embedded system design with SystemC. The goal is to
systematically develop both application-specific HW and SW components of an
embedded system using the TLM approach, thus allowing for fast communication
architecture exploration, rapid prototyping and early embedded SW development.
To this end, we specify the lightweight transaction-based communication
protocol SHIP and present a methodology for automatic mapping of the
communication part of a system to a given architecture, including HW/SW
interfaces.


title:
Electroweak and QCD corrections to Higgs production via vector-boson
  fusion at the LHC

abstract:
  The radiative corrections of the strong and electroweak interactions are
calculated at next-to-leading order for Higgs-boson production in the
weak-boson-fusion channel at hadron colliders. Specifically, the calculation
includes all weak-boson fusion and quark--antiquark annihilation diagrams to
Higgs-boson production in association with two hard jets, including all
corresponding interferences. The results on the QCD corrections confirm that
previously made approximations of neglecting s-channel diagrams and
interferences are well suited for predictions of Higgs production with
dedicated vector-boson fusion cuts at the LHC. The electroweak corrections,
which also include real corrections from incoming photons and leading
heavy-Higgs-boson effects at two-loop order, are of the same size as the QCD
corrections, viz. typically at the level of 5-10% for a Higgs-boson mass up to
\sim 700 GeV. In general, both types of corrections do not simply rescale
differential distributions, but induce distortions at the level of 10%. The
discussed corrections have been implemented in a flexible Monte Carlo event
generator.


title:
On the Analysis of Reed Solomon Coding for Resilience to
  Transient/Permanent Faults in Highly Reliable Memories

abstract:
  Single Event Upsets (SEU) as well as permanent faults can significantly
affect the correct on-line operation of digital systems, such as memories and
microprocessors; a memory can be made resilient to permanent and transient
faults by using modular redundancy and coding. In this paper, different memory
systems are compared: these systems utilize simplex and duplex arrangements
with a combination of Reed Solomon coding and scrubbing. The memory systems and
their operations are analyzed by novel Markov chains to characterize
performance for dynamic reconfiguration as well as error detection and
correction under the occurrence of permanent and transient faults. For a
specific Reed Solomon code, the duplex arrangement allows to efficiently cope
with the occurrence of permanent faults, while the use of scrubbing allows to
cope with transient faults.


title:
Influence of Memory Hierarchies on Predictability for Time Constrained
  Embedded Software

abstract:
  Safety-critical embedded systems having to meet real-time constraints are
expected to be highly predictable in order to guarantee at design time that
certain timing deadlines will always be met. This requirement usually prevents
designers from utilizing caches due to their highly dynamic, thus hardly
predictable behavior. The integration of scratchpad memories represents an
alternative approach which allows the system to benefit from a performance gain
comparable to that of caches while at the same time maintaining predictability.
In this work, we compare the impact of scratchpad memories and caches on worst
case execution time (WCET) analysis results. We show that caches, despite
requiring complex techniques, can have a negative impact on the predicted WCET,
while the estimated WCET for scratchpad memories scales with the achieved
Performance gain at no extra analysis cost.


title:
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable
  Computing Platforms

abstract:
  In this work we consider battery powered portable systems which either have
Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable
processors as their main processing element. An application is modeled in the
form of a precedence task graph at a coarse level of granularity. We assume
that for each task in the task graph several unique design-points are available
which correspond to different hardware implementations for FPGAs and different
voltage-frequency combinations for processors. It is assumed that performance
and total power consumption estimates for each design-point are available for
any given portable platfrom, including the peripheral components such as memory
and display power usage. We present an iterative heuristic algorithm which
finds a sequence of tasks along with an appropriate design-point for each task,
such that a deadline is met and the amount of battery energy used is as small
as possible. A detailed illustrative example along with a case study of a
real-world application of a robotic arm controller which demonstrates the
usefulness of our algorithm is also presented.


title:
Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded
  Software by Abstract Interpretation

abstract:
  Static program analysis by abstract interpretation is an efficient method to
determine properties of embedded software. One example is value analysis, which
determines the values stored in the processor registers. Its results are used
as input to more advanced analyses, which ultimately yield information about
the stack usage and the timing behavior of embedded software.


title: Design of a Virtual Component Neutral Network-on-Chip Transaction Layer

abstract:
  Research studies have demonstrated the feasibility and advantages of
Network-on-Chip (NoC) over traditional bus-based architectures but have not
focused on compatibility communication standards. This paper describes a number
of issues faced when designing a VC-neutral NoC, i.e. compatible with standards
such as AHB 2.0, AXI, VCI, OCP, and various other proprietary protocols, and
how a layered approach to communication helps solve these issues.


title: Model Reuse through Hardware Design Patterns

abstract:
  Increasing reuse opportunities is a well-known problem for software designers
as well as for hardware designers. Nonetheless, current software and hardware
engineering practices have embraced different approaches to this problem.
Software designs are usually modelled after a set of proven solutions to
recurrent problems called design patterns. This approach differs from the
component-based reuse usually found in hardware designs: design patterns do not
specify unnecessary implementation details. Several authors have already
proposed translating structural design patterns concepts to hardware design. In
this paper we extend the discussion to behavioural design patterns.
Specifically, we describe how the hardware version of the Iterator can be used
to enhance model reuse.


title:
Design Method for Constant Power Consumption of Differential Logic
  Circuits

abstract:
  Side channel attacks are a major security concern for smart cards and other
embedded devices. They analyze the variations on the power consumption to find
the secret key of the encryption algorithm implemented within the security IC.
To address this issue, logic gates that have a constant power dissipation
independent of the input signals, are used in security ICs. This paper presents
a design methodology to create fully connected differential pull down networks.
Fully connected differential pull down networks are transistor networks that
for any complementary input combination connect all the internal nodes of the
network to one of the external nodes of the network. They are memoryless and
for that reason have a constant load capacitance and power consumption. This
type of networks is used in specialized logic gates to guarantee a constant
contribution of the internal nodes into the total power consumption of the
logic gate.


title:
Techniques for Fast Transient Fault Grading Based on Autonomous
  Emulation

abstract:
  Very deep submicron and nanometer technologies have increased notably
integrated circuit (IC) sensitiveness to radiation. Soft errors are currently
appearing into ICs working at earth surface. Hardened circuits are currently
required in many applications where Fault Tolerance (FT) was not a requirement
in the very near past. The use of platform FPGAs for the emulation of
single-event upset effects (SEU) is gaining attention in order to speed up the
FT evaluation. In this work, a new emulation system for FT evaluation with
respect to SEU effects is proposed, providing shorter evaluation times by
performing all the evaluation process in the FPGA and avoiding emulator-host
communication bottlenecks.


title:
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task
  Scheduling

abstract:
  A novel energy reduction strategy to maximally exploit the dynamic workload
variation is proposed for the offline voltage scheduling of preemptive systems.
The idea is to construct a fully-preemptive schedule that leads to minimum
energy consumption when the tasks take on approximately the average execution
cycles yet still guarantees no deadline violation during the worst-case
scenario. End-time for each sub-instance of the tasks obtained from the
schedule is used for the on-line dynamic voltage scaling (DVS) of the tasks.
For the tasks that normally require a small number of cycles but occasionally a
large number of cycles to complete, such a schedule provides more opportunities
for slack utilization and hence results in larger energy saving. The concept is
realized by formulating the problem as a Non-Linear Programming (NLP)
optimization problem. Experimental results show that, by using the proposed
scheme, the total energy consumption at runtime is reduced by as high as 60%
for randomly generated task sets when comparing with the static scheduling
approach only using worst case workload.


title: A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs

abstract:
  As technology scales down, the static power is expected to become a
significant fraction of the total power. The exponential dependence of static
power with the operating temperature makes the thermal profile estimation of
high-performance ICs a key issue to compute the total power dissipated in
next-generations. In this paper we present accurate and compact analytical
models to estimate the static power dissipation and the temperature of
operation of CMOS gates. The models are the fundamentals of a performance
estimation tool in which numerical procedures are avoided for any computation
to set a faster estimation and optimization. The models developed are compared
to measurements and SPICE simulations for a 0.12mm technology showing excellent
results.


title: Low Power Oriented CMOS Circuit Optimization Protocol

abstract:
  Low power oriented circuit optimization consists in selecting the best
alternative between gate sizing, buffer insertion and logic structure
transformation, for satisfying a delay constraint at minimum area cost. In this
paper we used a closed form model of delay in CMOS structures to define metrics
for a deterministic selection of the optimization alternative. The target is
delay constraint satisfaction with minimum area cost. We validate the design
space exploration method, defining maximum and minimum delay bounds on logical
paths. Then we adapt this method to a "constant sensitivity method" allowing to
size a circuit at minimum area under a delay constraint. An optimisation
protocol is finally defined to manage the trade-off performance constraint -
circuit structure. These methods are implemented in an optimization tool (POPS)
and validated by comparing on a 0.25$\mu$m process, the optimization efficiency
obtained on various benchmarks (ISCAS?85) to that resulting from an industrial
tool.


title: Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

abstract:
  This paper describes two research projects that develop new low-cost
techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals.
Each project uses commercially available components to keep costs low, yet
achieves performance characteristics comparable to (and in some ways exceeding)
more expensive ATE. A common CMOS FPGA-based logic core provides flexibility,
adaptability, and communication with controlling computers while customized
positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with
about $\pm$25ps timing accuracy.


title:
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for
  Standby Leakage Power Reduction

abstract:
  This paper presents a design flow for an improved selective
multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so
that plural MT-cells can share one switch transistor. We propose the design
methodology from RTL(Register Transfer Level) to final layout with optimizing
switch transistor structure.


title:
Logic Design for On-Chip Test Clock Generation - Implementation Details
  and Impact on Delay Test Quality

abstract:
  This paper addresses delay test for SOC devices with high frequency clock
domains. A logic design for on-chip high-speed clock generation, implemented to
avoid expensive test equipment, is described in detail. Techniques for on-chip
clock generation, meant to reduce test vector count and to increase test
quality, are discussed. ATPG results for the proposed techniques are given.


title: Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip

abstract:
  Many existing thermal management techniques focus on reducing the overall
power consumption of the chip, and do not address location-specific temperature
problems referred to as hotspots. We propose the use of dynamic runtime
reconfiguration to shift the hotspot-inducing computation periodically and make
the thermal profile more uniform. Our analysis shows that dynamic
reconfiguration is an effective technique in reducing hotspots for NoCs.


title:
Robust control of uncertain multi-inventory systems via Linear Matrix
  Inequality

abstract:
  We consider a continuous time linear multi inventory system with unknown
demands bounded within ellipsoids and controls bounded within ellipsoids or
polytopes. We address the problem of "-stabilizing the inventory since this
implies some reduction of the inventory costs. The main results are certain
conditions under which "-stabilizability is possible through a saturated linear
state feedback control. All the results are based on a Linear Matrix
Inequalities (LMIs) approach and on some recent techniques for the modeling and
analysis of polytopic systems with saturations.


title: Gravitational Anomaly and Hawking Radiation of Brane World Black Holes

abstract:
  We apply Wilczek and his collaborators' anomaly cancellation approach to the
3-dimensional Schwarzschild- and BTZ-like brane world black holes induced by
the generalized C metrics in the Randall-Sundrum scenario. Based on the fact
that the horizon of brane world black hole will extend into the bulk spacetime,
we do the calculation from the bulk generalized C metrics side and show that
this approach also reproduces the correct Hawking radiation for these brane
world black holes. Besides, since this approach does not involve the dynamical
equation, it also shows that the Hawking radiation is only a kinematic effect.


title: Relativistic hydrodynamics with strangeness production

abstract:
  The relativistic hydrodynamic approach is used to describe production of
strangeness and/or heavy quarks in ultrarelativistic heavy ion reactions.
Production processes are important ingredients of dissipative effects in the
hadronic liquid. Beyond viscosity also chemo- and thermo-diffusion processes
are considered. This also allows to specify chemical and thermal freeze-out
conditions.


title: A Conversation with Dorothy Gilford

abstract:
  In 1946, Public Law 588 of the 79th Congress established the Office of Naval
Research (ONR). Its mission was to plan, foster and encourage scientific
research in support of Naval problems. The establishment of ONR predates the
National Science Foundation and initiated the refocusing of scientific
infrastructure in the United States following World War II. At the time, ONR
was the only source for federal support of basic research in the United States.
Dorothy Gilford was one of the first Heads of the Probability and Statistics
program at the Office of Naval Research (1955 to 1962), and she went on to
serve as Director of the Mathematical Sciences Division (1962 to 1968). During
her time at ONR, Dorothy influenced many areas of statistics and mathematics
and was ahead of her time in promoting interdisciplinary projects. Dorothy
continued her career at the National Center for Education Statistics (1969 to
1974). She was active in starting international comparisons of education
outcomes in different countries, which has influenced educational policy in the
United States. Dorothy went on to serve in many capacities at the National
Academy of Sciences, including Director of Human Resources Studies (1975 to
1978), Senior Statistician on the Committee on National Statistics (1978 to
1988) and Director of the Board on International Comparative Studies in
Education (1988 to 1994). The following is a conversation we had with Dorothy
Gilford in March of 2004. We found her to be an interesting person and a
remarkable statistician. We hope you agree.


title:
Chiral behavior of pseudo-Goldstone boson masses and decay constants in
  2+1 flavor QCD

abstract:
  We present preliminary results for the chiral behavior of charged
pseudo-Goldstone-boson masses and decay constants. These are obtained in
simulations with N_f=2+1 flavors of tree-level, O(a)-improved Wilson sea
quarks. In these simulations, mesons are composed of either valence quarks
discretized in the same way as the sea quarks (unitary simulations) or of
overlap valence quarks (mixed-action simulations). We find that the chiral
behavior of the pseudoscalar meson masses in the mixed-action calculations
cannot be explained with continuum, partially-quenched chiral perturbation
theory. We show that the inclusion of O(a^2) unitarity violations in the chiral
expansion resolves this discrepancy and that the size of the unitarity
violations required are consistent with those which we observe in the
zero-momentum, scalar-isotriplet-meson propagator.


title: Constructing Spin Interference Devices from Nanometric Rings

abstract:
  The study of nanospintronic devices utilizing coherent transport through
molecular scale multiply-connected geometries in the presence of moderate
magnetic fields is presented. It is shown how two types of simple devices, spin
filters and spin splitters (or Stern-Gerlach devices) may be constructed from
molecular nanometric rings utilizing the Aharonov-Bohm effect. The current is
calculated within a single electron approximation and within a many-body master
equation approach where charging effects are accounted for in the Coulomb
Blockade regime. We provide rules and tools to develop and analyze efficient
spintronic devices based on nanometric interferometers.


title: Non-equilibrium nanothermodynamics

abstract:
  Entropy production for a system not in the thermodynamic limit is formulated
using Hill's nanothermodynamics, in which a macroscopic ensemble of such
systems is considered. External influence of the environment on the average
nanosystem is connected to irreversible work with an explicit formula based on
Jarzynsky equality. Entropy production retains its usual form as a sum of
products of fluxes and forces and Onsager's symmetry principle is proven to
hold for the average nanosystem if it is valid for the macroscopic ensemble, by
two methods. The first one provides expressions that relate the coefficients of
the two systems. The second gives a general condition for a system under a
external force to preserve Onsager's symmetry.


title: One-dimensional Model of a Gamma Klystron

abstract:
  A new scheme for amplification of coherent gamma rays is proposed. The key
elements are crystalline undulators - single crystals with periodically bent
crystallographic planes exposed to a high energy beam of charged particles
undergoing channeling inside the crystals. The scheme consists of two such
crystals separated by a vacuum gap. The beam passes the crystals successively.
The particles perform undulator motion inside the crystals following the
periodic shape of the crystallographic planes. Gamma rays passing the crystals
parallel to the beam get amplified due to interaction with the particles inside
the crystals. The term `gamma klystron' is proposed for the scheme because its
operational principles are similar to those of the optical klystron. A more
simple one-crystal scheme is considered as well for the sake of comparison. It
is shown that the gamma ray amplification in the klystron scheme can be reached
at considerably lower particle densities than in the one-crystal scheme,
provided that the gap between the crystals is sufficiently large.


title: The ground state phases of orbitally degenerate spinel oxides

abstract:
  I review the microscopic spin-orbital Hamiltonian and ground state properties
of spin one-half spinel oxides with threefold $t_{2g}$ orbital degeneracy. It
is shown that for any orbital configuration a ground state of corresponding
spin only Hamiltonian is infinitely degenerate in the classical limit. The
extensive classical degeneracy is lifted by the quantum nature of the spins, an
effect similar to order-out-of-disorder phenomenon by quantum fluctuations.
This drives the system to a non-magnetic spin-singlet dimer manifold with a
residual degeneracy due to relative orientation of dimers. The magneto-elastic
mechanism of lifting the ``orientational'' degeneracy is also briefly reviewed.


title: On the integrability of holomorphic vector fields

abstract:
  We determine topological and algebraic conditions for a germ of holomorphic
foliation $\mathcal F(X)$ induced by a generic vector field $X$ on
$(\mathbb{C}^{3},0)$ to have a holomorphic first integral, i.e., a germ of
holomorphic map $F \colon(\mathbb{C}^{3},0)\longrightarrow(\mathbb{C}^{2},0)$
such that the leaves of $\mathcal F(X)$ are contained in the level curves of
$F$.


title: Two-Loop Heavy-Flavor Contribution to Bhabha Scattering

abstract:
  We evaluate the two-loop QED corrections to the Bhabha scattering cross
section which involve the vacuum polarization by heavy fermions of arbitrary
mass m_f >> m_e. The results are valid for generic values of the Mandelstam
invariants s,t,u >> m_e^2.


title: Small-scale structure and dynamics of the lower solar atmosphere

abstract:
  The chromosphere of the quiet Sun is a highly intermittent and dynamic
phenomenon. Three-dimensional radiation (magneto-)hydrodynamic simulations
exhibit a mesh-like pattern of hot shock fronts and cool expanding post-shock
regions in the sub-canopy part of the inter-network. This domain might be
called "fluctosphere". The pattern is produced by propagating shock waves,
which are excited at the top of the convection zone and in the photospheric
overshoot layer. New high-resolution observations reveal a ubiquitous
small-scale pattern of bright structures and dark regions in-between. Although
it qualitatively resembles the picture seen in models, more observations - e.g.
with the future ALMA - are needed for thorough comparisons with present and
future models. Quantitative comparisons demand for synthetic intensity maps and
spectra for the three-dimensional (magneto-)hydrodynamic simulations. The
necessary radiative transfer calculations, which have to take into account
deviations from local thermodynamic equilibrium, are computationally very
involved so that no reliable results have been produced so far. Until this task
becomes feasible, we have to rely on careful qualitative comparisons of
simulations and observations. Here we discuss what effects have to be
considered for such a comparison. Nevertheless we are now on the verge of
assembling a comprehensive picture of the solar chromosphere in inter-network
regions as dynamic interplay of shock waves and structuring and guiding
magnetic fields.


title:
Periodicity-dependence of the ferroelectric properties in BiFeO3/SrTiO3
  multiferroic superlattices

abstract:
  Artificial superlattices of (BiFeO3)m(SrTiO3)m (m= 1 to 10 unit cells)
consisting of multiferroic BiFeO3 and insulating SrTiO3 layers were fabricated
on (100)-oriented SrTiO3 substrates by pulsed laser ablation. The remnant
polarization and leakage current behavior were studied varying the periodicity
(8-80A) of the superlattice. The leakage current was reduced by few orders of
magnitude on increase of periodicity compared to single layer BiFeO3 thin
films. Reduced leakage and intrinsic polarization hysteresis was observed and
was confirmed by PUND analysis for periodicities in the range 20-60A. The
leakage current was observed to be dominated by space charge limited conduction


title: The Hasse principle for pairs of diagonal cubic forms

abstract:
  By means of the Hardy-Littlewood method, we apply a new mean value theorem
for exponential sums to confirm the truth, over the rational numbers, of the
Hasse principle for pairs of diagonal cubic forms in thirteen or more
variables.


title: Leading Pollicott-Ruelle Resonances for Chaotic Area-Preserving Maps

abstract:
  Recent investigations in nonlinear sciences show that not only hyperbolic but
also mixed dynamical systems may exhibit exponential relaxation in the chaotic
regime. The relaxation rates, which lead the decay of probability distributions
and correlation functions, are related to the classical evolution resolvent
(Perron-Frobenius operator) pole logarithm, the so called Pollicott-Ruelle
resonances. In this Brief Report, the leading Pollicott-Ruelle resonances are
calculated analytically for a general class of area-preserving maps. Besides
the leading resonances related to the diffusive modes of momentum dynamics
(slow rate), we also calculate the leading faster rate, related to the angular
correlations. The analytical results are compared to the existing results in
the literature.