def write_core_registers_raw(self, reg_list, data_list):
        # Check and invalidate the cache. If the core is still running, just pass the writes
        # to our context.
        if self._check_cache():
            self._context.write_core_registers_raw(reg_list, data_list)
            return

        reg_list = self._convert_and_check_registers(reg_list)
        self._metrics.writes += len(reg_list)

        writing_cfbp = any(r for r in reg_list if r in self.CFBP_REGS)
        writing_xpsr = any(r for r in reg_list if r in self.XPSR_REGS)

        # Update cached register values.
        for i, r in enumerate(reg_list):
            v = data_list[i]
            self._cache[r] = v

        # Just remove all cached CFBP and XPSR based register values.
        if writing_cfbp:
            for r in self.CFBP_REGS:
                self._cache.pop(r, None)

        if writing_xpsr:
            for r in self.XPSR_REGS:
                self._cache.pop(r, None)

        # Write new register values to target.
        try:
            self._context.write_core_registers_raw(reg_list, data_list)
        except exceptions.CoreRegisterAccessError:
            # Invalidate cache on register write error just to be safe.
            self._reset_cache()
            raise