In this article, the phase noise of a closed-loop, phase-locked loop (PLL) synthesizer is simulated using Agilent RF Design Environment (RFDE) and Advanced Design System (ADS) tools. The critical sub-circuits, such as the voltage-controlled oscillator (VCO), phase frequency detector (PFD) and charge pump (CP) are simulated separately and then modeled using behavioral models. The simulation results match the measured data of the IC to the first order.
Phase-locked loops (PLLs) are used extensively as on-chip clock generators to synthesize and reshape a much-higher internal frequency using the external lower frequency. In data communications, for example, PLLs are used as clock-recovery systems, whereas in broadband optical communication networks, they are applied as clock and data recovery systems (CDR) to generate the clock and resynchronize the data from the received signal. PLLs are also used as frequency synthesizers in wireless communications, to synthesize an accurate frequency which can then be used to modulate or demodulate the real signals.
In all of these applications, the random temporal variation of the phase of the synthesized frequency, or jitter, is one of the most critical parameters characterizing PLL performance. Jitter and phase noise are different ways of referring to an undesired variation in the timing of events at the output of the PLL, and is difficult to predict with the small-signal analysis of traditional circuit simulators. Because the PLL generates repetitive switching events as an essential part of its operation, the noise performance must be evaluated in the presence of this large-signal behavior.
The periodic steady state (PSS) and PNoise analyses of Cadence's spectreRF solution are widely used to predict the noise performance of smaller circuits, like the voltage-controlled oscillator (VCO). In the case of a closed-loop PLL synthesizer though, the device gate count can easily reach 30,000 to 50,000, making it hard for the PSS analysis to converge on a result. In contrast, Agilent's RF Design Environment (RFDE) and Advanced Design System (ADS) tools feature behavioral models for every sub-circuit of the PLL synthesizer. The phase noise or jitter performance of each sub-circuit can be simulated separately with RFDE and parameters can be extracted for behavior modeling. Closed-loop simulation can then be performed using circuit envelope and takes only several seconds.
As opposed to a single tone on the spectrum, the synthesized output frequency of a PLL is subject to all sorts of noise, presented both in amplitude and phase. Most of the noise sources (e.g., flick (1/f), thermal and shot noise) are associated with devices. More comprehensive noise models also include power/ground, substrate noise coupling, signal inter-modulation, and sub-optimum biasing, just to name a few.
Due to the non-linear nature of an oscillator circuit, amplitude fluctuation is inherently limited and phase variation is therefore, of key importance. The long-term variation and short-term non-random variation in phase are usually due to an external reference source and discrete spurious signals, which can be removed or suppressed to a reasonable level by using appropriate techniques. The short-term random variation in phase is called phase noise, or jitter, and directly impacts the accuracy and stability of PLL performance. If the ideal output signal of the oscillator is considered as a sinusoidal waveform, (e.g., phasor), then the noise is a small perturbation added to this trajectory as shown in Equation 1 :
Modulation theory shows that phase noise can be represented as a sideband with symmetrically smaller amplitude at both sides of the carrier frequency. Intuitively, phase noise in the frequency domain can be viewed as the cycle-to-cycle jitter in the time domain, which changes the instantaneous zero-crossing of an otherwise perfect sinusoidal signal.
The sources of phase noise within a PLL synthesizer include:
- VCO phase noise
- Reference oscillator phase noise
- Thermal noise and device noise from components in the loop filter
- Noise from the digital dividers and phase detector
- Noises injected from the supplies and bias circuits
Noise sources 1 through 3 are well understood. They can usually be modeled with good accuracy using measured phase noise data for the VCO and reference, and conventional noise models from circuit theory for the loop filter. Noise from digital devices, dividers and the phase/frequency detector, on the other hand, is difficult to model and constrains the top-level simulation including all the analog and digital functional blocks.
Different approaches for characterizing the phase noise in electrical oscillators have been studied extensively. Lesson's model [Reference 1 ] was the first attempt to predict phase noise in oscillators. It is described according to Equation 2 :
These days, more complicated models are used to characterize oscillator performance. Razavi [Reference 2 ], for example, uses a linear time-invariant (LTI) model to describe the behavior of phase noise in oscillators, while Hajimiri [Reference 3 ] relies on a more accurate linear time-variant (LTV) model. Demir [Reference 4 ] derived a non-linear stochastic differential equation for phase error, and solves this equation in the presence of random perturbations.
To better understand PLL noise, consider a generic PLL as shown in Figure 1 .
Figure 1: The block diagram of a generic PLL with noise signals at different nodes.
(Click to enlarge image)
It includes a phase frequency detector (PFD), charge pump (CP), loop filter (LF), VCO, and frequency divider (FD). The noise transfer function of the close-loop PLL is derived as follows (Equation 3 through Equation 6 ):
(Click on any equation to enlarge it)
Figure 2: Noise contribution from individual blocks for close-loop PLL phase noise performance.
(Click to enlarge image)
Note that within the PLL loop bandwidth, the phase noise is typically dominated by the noise from the frequency dividers and phase detector. For frequencies well below the loop bandwidth, the phase noise plot typically flattens out resulting in the in-band phase noise floor. Outside of the loop bandwidth, VCO noise is the dominant factor.
Equation 3 and Equation 4 indicate that any noise from the input source and CP-based PFD is low-pass filtered. The noise due to static phase offset, contributed by the CP leakage current, can be kept low using good PFD and CP design techniques. The noise from the LF is shaped by a bandpass noise-transfer function, whereas the noise contribution from the VCO is high-pass filtered.
(Note: Part 2 of this article looks at Agilent ADS/RFDE capability and methodology, as well as results)
The authors wish to acknowledge the assistance of Andy Howard from Agilent Technologies on RFDE/ADS simulations, as well as the support of Carlos Cardenas from M/A-COM on simulation tools.
1. D.B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE , vol. 54, pp.329-330, 1966.
2. B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J Solid-State Circuits , vol. 31, pp. 331-343, Mar. 1996.
3. A. Hajimiri and T.H.Lee, “A general theory of phase noise in electrical oscillators,” IEEE J Solid-State Circuits , vol. 33, pp. 179-194, Feb. 1998.
4. A.Demir, A. Mehtotha, and J. Roychowdhury, “Phase Noise in oscillators; a unifying theory and numerical methods for characterization,” IEEE Trans. Circuits Syst. II , vol. 46, pp. 56-62, Jan. 1999.
About the Authors
Russ Kramer is an application engineer Agilent EEsof EDA, specializing in IC business development.
Yi Fang and Wei Zhang were with M/A-COM, Tyco Electronics, Morristown, NJ.