{"push_id":3766477772,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"43f919c04b6f6ce6bad1cf61d9e641147d5f4475","before":"1ee7b91646e82b0bca9d15d7e4627054d3ae588e","commits":[{"sha":"43f919c04b6f6ce6bad1cf61d9e641147d5f4475","author":{"name":"Eladash","email":"fdd7be8c7072c1c9f3c9551a38ea4e938ef7cf9f@gmail.com"},"message":"Fixup after #6143 (#6146)\n\n    vm::spu max address was overflowing resulting in issues, so cast to u64 where needed. Fixes #6145.\r\n    Use vm::get_addr instead of manually substructing vm::base(0) from pointer in texture cache code.\r\n    Prefer std::atomic_thread_fence over _mm_?fence(), adjust usage to be more correct.\r\n    Used sequantially consistent ordering in semaphore_release for TSX path as well.\r\n    Improved memory ordering for sys_rsx_context_iounmap/map.\r\n    Fixed sync bugs in HLE gcm because of not using atomic instructions.\r\n    Use release memory barrier in lwsync for PPU LLVM, according to this xbox360 programming guide lwsync is a hw release memory barrier.\r\n    Also use release barrier where lwsync was originally used in liblv2 sys_lwmutex and cellSync.\r\n    Use acquire barrier for isync instruction, see https://devblogs.microsoft.com/oldnewthing/20180814-00/?p=99485","distinct":true,"url":"https://api.github.com/repos/RPCS3/rpcs3/commits/43f919c04b6f6ce6bad1cf61d9e641147d5f4475"}]}
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