{"action":"created","issue":{"url":"https://api.github.com/repos/SpinalHDL/VexRiscv/issues/60","repository_url":"https://api.github.com/repos/SpinalHDL/VexRiscv","labels_url":"https://api.github.com/repos/SpinalHDL/VexRiscv/issues/60/labels{/name}","comments_url":"https://api.github.com/repos/SpinalHDL/VexRiscv/issues/60/comments","events_url":"https://api.github.com/repos/SpinalHDL/VexRiscv/issues/60/events","html_url":"https://github.com/SpinalHDL/VexRiscv/issues/60","id":415696170,"node_id":"MDU6SXNzdWU0MTU2OTYxNzA=","number":60,"title":"Linux on VexRiscv","user":{"login":"wm4","id":1387750,"node_id":"MDQ6VXNlcjEzODc3NTA=","avatar_url":"https://avatars0.githubusercontent.com/u/1387750?v=4","gravatar_id":"","url":"https://api.github.com/users/wm4","html_url":"https://github.com/wm4","followers_url":"https://api.github.com/users/wm4/followers","following_url":"https://api.github.com/users/wm4/following{/other_user}","gists_url":"https://api.github.com/users/wm4/gists{/gist_id}","starred_url":"https://api.github.com/users/wm4/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/wm4/subscriptions","organizations_url":"https://api.github.com/users/wm4/orgs","repos_url":"https://api.github.com/users/wm4/repos","events_url":"https://api.github.com/users/wm4/events{/privacy}","received_events_url":"https://api.github.com/users/wm4/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":{"login":"Dolu1990","id":4832082,"node_id":"MDQ6VXNlcjQ4MzIwODI=","avatar_url":"https://avatars0.githubusercontent.com/u/4832082?v=4","gravatar_id":"","url":"https://api.github.com/users/Dolu1990","html_url":"https://github.com/Dolu1990","followers_url":"https://api.github.com/users/Dolu1990/followers","following_url":"https://api.github.com/users/Dolu1990/following{/other_user}","gists_url":"https://api.github.com/users/Dolu1990/gists{/gist_id}","starred_url":"https://api.github.com/users/Dolu1990/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/Dolu1990/subscriptions","organizations_url":"https://api.github.com/users/Dolu1990/orgs","repos_url":"https://api.github.com/users/Dolu1990/repos","events_url":"https://api.github.com/users/Dolu1990/events{/privacy}","received_events_url":"https://api.github.com/users/Dolu1990/received_events","type":"User","site_admin":false},"assignees":[{"login":"Dolu1990","id":4832082,"node_id":"MDQ6VXNlcjQ4MzIwODI=","avatar_url":"https://avatars0.githubusercontent.com/u/4832082?v=4","gravatar_id":"","url":"https://api.github.com/users/Dolu1990","html_url":"https://github.com/Dolu1990","followers_url":"https://api.github.com/users/Dolu1990/followers","following_url":"https://api.github.com/users/Dolu1990/following{/other_user}","gists_url":"https://api.github.com/users/Dolu1990/gists{/gist_id}","starred_url":"https://api.github.com/users/Dolu1990/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/Dolu1990/subscriptions","organizations_url":"https://api.github.com/users/Dolu1990/orgs","repos_url":"https://api.github.com/users/Dolu1990/repos","events_url":"https://api.github.com/users/Dolu1990/events{/privacy}","received_events_url":"https://api.github.com/users/Dolu1990/received_events","type":"User","site_admin":false}],"milestone":null,"comments":234,"created_at":"2019-02-28T15:59:19Z","updated_at":"2019-03-31T21:34:32Z","closed_at":null,"author_association":"NONE","body":"My intention with creating this issue is collecting/sharing information and gauging interest about running Linux on VecRiscv. From what I know, VexRiscv is still missing functionality, and it won't work out of the box.\r\n\r\nA big problem is the MMU. Ideally, \"someone\" will hopefully write patches to add no-MMU support to Linux/RISC-V, but currently, a MMU is required. It appears VexRiscv has a partial MMU implementation using a software-filled TLB. There needs to be machine mode to walk the page tables and fill the TLBs, and I didn't find a reference implementation of that.\r\n\r\nAnother issue are atomics. Linux requires them currently. There seems to be partial support present in VexRiscv (a subset or so). Another possibility is patching the kernel not to use atomics if built without SMP support. There's also the question how much atomics support userspace typically requires.\r\n\r\nWithout doubt there are more issues that I don't know about.\r\n\r\nAntmicro apparently made a Linux port: https://github.com/antmicro/litex-rv32-linux-system https://github.com/antmicro/litex-linux-riscv\r\nI didn't know about this before and haven't managed to build the whole thing yet.\r\nUnfortunately, their Linux kernel repository does not include the git history. Here's a diff against the apparent base: https://0x0.st/z-li.diff\r\n\r\nPlease post any other information you know."},"comment":{"url":"https://api.github.com/repos/SpinalHDL/VexRiscv/issues/comments/478387328","html_url":"https://github.com/SpinalHDL/VexRiscv/issues/60#issuecomment-478387328","issue_url":"https://api.github.com/repos/SpinalHDL/VexRiscv/issues/60","id":478387328,"node_id":"MDEyOklzc3VlQ29tbWVudDQ3ODM4NzMyOA==","user":{"login":"roman3017","id":1292891,"node_id":"MDQ6VXNlcjEyOTI4OTE=","avatar_url":"https://avatars3.githubusercontent.com/u/1292891?v=4","gravatar_id":"","url":"https://api.github.com/users/roman3017","html_url":"https://github.com/roman3017","followers_url":"https://api.github.com/users/roman3017/followers","following_url":"https://api.github.com/users/roman3017/following{/other_user}","gists_url":"https://api.github.com/users/roman3017/gists{/gist_id}","starred_url":"https://api.github.com/users/roman3017/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/roman3017/subscriptions","organizations_url":"https://api.github.com/users/roman3017/orgs","repos_url":"https://api.github.com/users/roman3017/repos","events_url":"https://api.github.com/users/roman3017/events{/privacy}","received_events_url":"https://api.github.com/users/roman3017/received_events","type":"User","site_admin":false},"created_at":"2019-03-31T21:34:32Z","updated_at":"2019-03-31T21:34:32Z","author_association":"NONE","body":"After integrating the driver (had to add 4 files puts.h, puts.c, uart-litex.h and uart-litex.c) I am getting this FAILURE:\r\n```sh\r\n[    0.436000] io scheduler noop registered\r\n[    0.440000] io scheduler deadline registered\r\n[    0.440000] io scheduler cfq registered (default)\r\n[    0.440000] io scheduler mq-deadline registered\r\n[    0.440000] io scheduler kyber registered\r\nUnmapped peripheral access : addr=0xe0001804 wr=0 mask=0xf data=0x0x56200cadfcd8\r\nFAIL linux at PC=c02d091c\r\n\r\n****************************************************************\r\nHad simulate 61728599 clock cycles in 64.5692 s (956.007 Khz)\r\nFAILURE 1/1\r\n****************************************************************\r\n```\r\nLooking inside the probe the registers at 0xe0001800 are indeed not mapped. I guess litex maps driver registers elsewhere. This driver requires some work in order to read and map registers from DT."}}
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