{"action":"created","issue":{"url":"https://api.github.com/repos/ZishuoYang/UT-Backplane-mapping/issues/65","repository_url":"https://api.github.com/repos/ZishuoYang/UT-Backplane-mapping","labels_url":"https://api.github.com/repos/ZishuoYang/UT-Backplane-mapping/issues/65/labels{/name}","comments_url":"https://api.github.com/repos/ZishuoYang/UT-Backplane-mapping/issues/65/comments","events_url":"https://api.github.com/repos/ZishuoYang/UT-Backplane-mapping/issues/65/events","html_url":"https://github.com/ZishuoYang/UT-Backplane-mapping/issues/65","id":410914140,"node_id":"MDU6SXNzdWU0MTA5MTQxNDA=","number":65,"title":"to include control signals in the UT-system ASIC-Fiber mapping","user":{"login":"ZishuoYang","id":12600353,"node_id":"MDQ6VXNlcjEyNjAwMzUz","avatar_url":"https://avatars3.githubusercontent.com/u/12600353?v=4","gravatar_id":"","url":"https://api.github.com/users/ZishuoYang","html_url":"https://github.com/ZishuoYang","followers_url":"https://api.github.com/users/ZishuoYang/followers","following_url":"https://api.github.com/users/ZishuoYang/following{/other_user}","gists_url":"https://api.github.com/users/ZishuoYang/gists{/gist_id}","starred_url":"https://api.github.com/users/ZishuoYang/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ZishuoYang/subscriptions","organizations_url":"https://api.github.com/users/ZishuoYang/orgs","repos_url":"https://api.github.com/users/ZishuoYang/repos","events_url":"https://api.github.com/users/ZishuoYang/events{/privacy}","received_events_url":"https://api.github.com/users/ZishuoYang/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":3,"created_at":"2019-02-15T19:36:00Z","updated_at":"2019-02-19T18:52:54Z","closed_at":null,"author_association":"OWNER","body":"As titled, to extend the current fiber mapping header and include:\r\n- DCB channel for `DC_OUT_RCLK#_P` (for JP signal e.g. `P#_EAST_CLK_P`)\r\n- DCB channel for `EC_HYB_i2C_SCL_#` (for JP signal e.g. `P#_EAST_I2C_SCL_P`)\r\n- DCB channel for `EC_HYB_i2C_SDA_#` (for JP signal e.g. `P#_EAST_I2C_SDA_P`)\r\n- DCB channel for `EC_RESET_GPIO_#` (for JP signal e.g. `P#_EAST_RESET_P`)\r\n- DCB channel for `MC_TFC#_P` (for JP signal e.g. `P#_EAST_TFC_P`)\r\n- DCB channel for `EC_ADC_#` (for JP signal e.g. `P#_EAST_THERMISTOR_P`)\r\n\r\n*Note that each set of these channels is for one 4-ASIC group (e.g. P1_EAST).*\r\n\r\n"},"comment":{"url":"https://api.github.com/repos/ZishuoYang/UT-Backplane-mapping/issues/comments/465262777","html_url":"https://github.com/ZishuoYang/UT-Backplane-mapping/issues/65#issuecomment-465262777","issue_url":"https://api.github.com/repos/ZishuoYang/UT-Backplane-mapping/issues/65","id":465262777,"node_id":"MDEyOklzc3VlQ29tbWVudDQ2NTI2Mjc3Nw==","user":{"login":"yipengsun","id":33738176,"node_id":"MDQ6VXNlcjMzNzM4MTc2","avatar_url":"https://avatars0.githubusercontent.com/u/33738176?v=4","gravatar_id":"","url":"https://api.github.com/users/yipengsun","html_url":"https://github.com/yipengsun","followers_url":"https://api.github.com/users/yipengsun/followers","following_url":"https://api.github.com/users/yipengsun/following{/other_user}","gists_url":"https://api.github.com/users/yipengsun/gists{/gist_id}","starred_url":"https://api.github.com/users/yipengsun/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/yipengsun/subscriptions","organizations_url":"https://api.github.com/users/yipengsun/orgs","repos_url":"https://api.github.com/users/yipengsun/repos","events_url":"https://api.github.com/users/yipengsun/events{/privacy}","received_events_url":"https://api.github.com/users/yipengsun/received_events","type":"User","site_admin":false},"created_at":"2019-02-19T18:52:54Z","updated_at":"2019-02-19T18:52:54Z","author_association":"CONTRIBUTOR","body":"For these `EC_ADC` channels, we need to update the `AltiumNetlistGen.py` so that they have correct netnames, because they should be connected to `JT`, instead of `GND`."}}
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