{"push_id":3273634239,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"95da4b86ed1781013c1ef29d505c15c669cca474","before":"aab380fa40c70c7978a480e6c80959be1a1aa737","commits":[{"sha":"7188558b790405d367160176cf6ad3f0b6fa7fd0","author":{"name":"Matt Arsenault","email":"788c14eeffa2067e120409a238fa186a04f20a10@amd.com"},"message":"GlobalISel: Fix moreElementsToNextPow2\n\nThis was completely broken. The condition was inverted, and changed\nthe element type for vectors of pointers.\n\nFixes bug 40592.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353069 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/7188558b790405d367160176cf6ad3f0b6fa7fd0"},{"sha":"95da4b86ed1781013c1ef29d505c15c669cca474","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"[X86] Add ST0 as an implicit def/use of x87 load/store instructions during FP stackifying.\n\nThese instructions implicitly operate on ST0, but we don't currently add that information to the MachineInstr. We also don't add it the tablegen definitions either.\n\nFor the most part this doesn't cause any problems because the stackifying occurs after register allocation. All the instructions are marked as having side effects so the postRA scheduler won't reorder them amongst themselves.\n\nBut nothing stops inline assembly using X87 instructions from being reordered around other x87 instructions if that inline assembly wasn't marked volatile.\n\nThe two test cases I've identified so far in PR40539 involve loads and stores used to set up the inline assembly or capture the results of the inline assembly ending up in the wrong order.\n\nThis patch adds implicit ST0 uses/defs to the load/store instructions to prevent this from happening.\n\nI plan to fix all of the FP instructions, but the binops are bit trickier to get right. So I've chosen fixing the known test cases as a good first step.\n\nI think we also need to update the tablegen descriptions so MS inline assembly infers the right clobbers, but I haven't checked that yet.\n\nDifferential Revision: https://reviews.llvm.org/D57644\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353070 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-mirror/llvm/commits/95da4b86ed1781013c1ef29d505c15c669cca474"}]}
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