{"action":"created","issue":{"url":"https://api.github.com/repos/goldshakil/FPGA_XILINIX/issues/2","repository_url":"https://api.github.com/repos/goldshakil/FPGA_XILINIX","labels_url":"https://api.github.com/repos/goldshakil/FPGA_XILINIX/issues/2/labels{/name}","comments_url":"https://api.github.com/repos/goldshakil/FPGA_XILINIX/issues/2/comments","events_url":"https://api.github.com/repos/goldshakil/FPGA_XILINIX/issues/2/events","html_url":"https://github.com/goldshakil/FPGA_XILINIX/issues/2","id":520569349,"node_id":"MDU6SXNzdWU1MjA1NjkzNDk=","number":2,"title":"Goal 2 - Deadline: 15th Nov","user":{"login":"goldshakil","id":48248272,"node_id":"MDQ6VXNlcjQ4MjQ4Mjcy","avatar_url":"https://avatars3.githubusercontent.com/u/48248272?v=4","gravatar_id":"","url":"https://api.github.com/users/goldshakil","html_url":"https://github.com/goldshakil","followers_url":"https://api.github.com/users/goldshakil/followers","following_url":"https://api.github.com/users/goldshakil/following{/other_user}","gists_url":"https://api.github.com/users/goldshakil/gists{/gist_id}","starred_url":"https://api.github.com/users/goldshakil/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/goldshakil/subscriptions","organizations_url":"https://api.github.com/users/goldshakil/orgs","repos_url":"https://api.github.com/users/goldshakil/repos","events_url":"https://api.github.com/users/goldshakil/events{/privacy}","received_events_url":"https://api.github.com/users/goldshakil/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2019-11-10T08:15:52Z","updated_at":"2019-11-22T01:48:45Z","closed_at":"2019-11-22T01:48:45Z","author_association":"OWNER","body":"1) Test the LCD on the FPGA and show numbers on it.\r\n2) check the syntax of the verilog module\r\n3) check the configuration file (.ucf) file.\r\n\r\n\r\n* (.ucf) file is the file responsible for initializing the ports it stands for USER CONSTRAINT FILE\r\nReferences:\r\n https://www.youtube.com/watch?v=UjrBo_EyKXE\r\nhttps://www.youtube.com/watch?v=v2CM8RaEeQU\r\nhttps://www.youtube.com/watch?v=2Bvf1GdutFI\r\nPINOUT data sheet:\r\nhttps://www.xilinx.com/support/documentation/user_guides/ug385.pdf"},"comment":{"url":"https://api.github.com/repos/goldshakil/FPGA_XILINIX/issues/comments/557351137","html_url":"https://github.com/goldshakil/FPGA_XILINIX/issues/2#issuecomment-557351137","issue_url":"https://api.github.com/repos/goldshakil/FPGA_XILINIX/issues/2","id":557351137,"node_id":"MDEyOklzc3VlQ29tbWVudDU1NzM1MTEzNw==","user":{"login":"goldshakil","id":48248272,"node_id":"MDQ6VXNlcjQ4MjQ4Mjcy","avatar_url":"https://avatars3.githubusercontent.com/u/48248272?v=4","gravatar_id":"","url":"https://api.github.com/users/goldshakil","html_url":"https://github.com/goldshakil","followers_url":"https://api.github.com/users/goldshakil/followers","following_url":"https://api.github.com/users/goldshakil/following{/other_user}","gists_url":"https://api.github.com/users/goldshakil/gists{/gist_id}","starred_url":"https://api.github.com/users/goldshakil/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/goldshakil/subscriptions","organizations_url":"https://api.github.com/users/goldshakil/orgs","repos_url":"https://api.github.com/users/goldshakil/repos","events_url":"https://api.github.com/users/goldshakil/events{/privacy}","received_events_url":"https://api.github.com/users/goldshakil/received_events","type":"User","site_admin":false},"created_at":"2019-11-22T01:48:45Z","updated_at":"2019-11-22T01:48:45Z","author_association":"OWNER","body":"done."}}
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