{"push_id":2639594562,"size":3,"distinct_size":3,"ref":"refs/heads/master","head":"98cf9a93c7ac36f71afac7af82e99822ff6c72a5","before":"262f55c33c781f0d761dee14c7c763a37556aa3c","commits":[{"sha":"f48bb3571f3587e79f2ed03de731cdb2f88be767","author":{"name":"Roman Tereshin","email":"9f5605aa7534078ac143ef848e29fbf210f38d66@apple.com"},"message":"[MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs()\n\nApparently, MachineInstr class definition as well as pretty much all of\nthe machine passes assume that the only kind of MachineInstr's operands\nthat is variadic for variadic opcodes is explicit non-definitions.\n\nIn particular, this assumption is made by MachineInstr::defs(), uses(),\nand explicit_uses() methods, as well as by MachineCSE pass.\n\nThe assumption is incorrect judging from at least TableGen backend\nimplementation, that recognizes variable_ops in OutOperandList, and the\nvery existence of G_UNMERGE_VALUES generic opcode, or ARM load multiple\ninstructions, all of which have variadic defs.\n\nIn particular, MachineCSE pass breaks MIR with CSE'able G_UNMERGE_VALUES\ninstructions in it.\n\nThis commit implements MachineInstr::getNumExplicitDefs() similar to\npre-existing MachineInstr::getNumExplicitOperands(), fixes\nMachineInstr::defs(), uses(), and explicit_uses(), and fixes MachineCSE\npass.\n\nAs the issue addressed seems to affect only machine passes that could be\nran mid-GlobalISel pipeline at the moment, the other passes aren't fixed\nby this commit, like MachineLICM: that could be done on per-pass basis\nwhen (if ever) they get adopted for GlobalISel.\n\nReviewed By: arsenm\n\nDifferential Revision: https://reviews.llvm.org/D45640\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334520 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/f48bb3571f3587e79f2ed03de731cdb2f88be767"},{"sha":"0bb5aa97efd2cf87ed12c5a6a4083340b79c6d05","author":{"name":"Konstantin Zhuravlyov","email":"237b71dc3aa2b03e82075d578a7ddace3cbd7f67@outlook.com"},"message":"AMDHSA/NFC: Code object v3 updates (additional):\n\n- Move section selection and alignment to AMDGPUAsmPrinter\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334521 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/0bb5aa97efd2cf87ed12c5a6a4083340b79c6d05"},{"sha":"98cf9a93c7ac36f71afac7af82e99822ff6c72a5","author":{"name":"Reid Kleckner","email":"ab3c2931970baa67c6d76cdeb719744d873e09ef@google.com"},"message":"[MS][ARM64] Hoist __ImageBase handling into TargetLoweringObjectFileCOFF\n\nAll COFF targets should use @IMGREL32 relocations for symbol differences\nagainst __ImageBase. Do the same for getSectionForConstant, so that\nimmediates lowered to globals get merged across TUs.\n\nPatch by Chris January\n\nDifferential Revision: https://reviews.llvm.org/D47783\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334523 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/98cf9a93c7ac36f71afac7af82e99822ff6c72a5"}]}
{"actor":{"display_login":"earl"}}