{"push_id":2422379602,"size":1,"distinct_size":1,"ref":"refs/heads/system_allct","head":"5e46b5fd9462b7ac2e549b3e20a97c8fa0214225","before":"a3ed60dffc7fc7af95364efaffa672cc6f98f6dc","commits":[{"sha":"5e46b5fd9462b7ac2e549b3e20a97c8fa0214225","author":{"name":"Stefan Wallentowitz","email":"6fe76ede026e27600863a1ff38da4e776dcaecdf@wallentowitz.de"},"message":"Examples: Nexys4 FPGA generalize allct\n\nAs long as you use local memory as BRAM (and not emulated with\nexternal memory) it is now possible to configure arbitrary mesh\ndimensions.\n\nTo be fully flexible (LMEM_EXTERNAL && TILES!=4) the AXI interconnect\nneeds to be fixed.","distinct":true,"url":"https://api.github.com/repos/optimsoc/optimsoc/commits/5e46b5fd9462b7ac2e549b3e20a97c8fa0214225"}]}
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