{"action":"created","comment":{"url":"https://api.github.com/repos/ebecz/vhdl-project-euler/pulls/comments/172061280","pull_request_review_id":101016697,"id":172061280,"diff_hunk":"@@ -14,59 +14,92 @@ entity P001 is\n end P001;\n \n architecture behaviour of P001 is\n-\ttype conv_states is (waiting, init, converting);\n-\tsignal state : conv_states := waiting;\n-\tsignal internal_input : unsigned(15 downto 0);\n-\tsignal counter: unsigned(15 downto 0);\n+\ttype conv_states is (waiting, converting);\n+\n+\tsignal state: conv_states := waiting;\n+\tsignal internal_input: unsigned(15 downto 0);\n+\tsignal counter: unsigned(15 downto 0) := x\"0001\";\n \tsignal sum: unsigned(31 downto 0);\n \tsignal counter_0_to_2: integer range 0 to 2;\n \tsignal counter_0_to_4: integer range 0 to 4;\n+\n+\tsignal state_next: conv_states := waiting;\n+\tsignal internal_input_next : unsigned(15 downto 0);\n+\tsignal counter_next: unsigned(15 downto 0) := x\"0001\";\n+\tsignal sum_next: unsigned(31 downto 0);\n+\tsignal counter_0_to_2_next: integer range 0 to 2;\n+\tsignal counter_0_to_4_next: integer range 0 to 4;\n+\n begin\n \tprocess (clk, rst_n)\n \tbegin\n \t\tif rst_n = '0' then\n-\t\t\tstate     <= init;\n-\t\t\tcounter   <= x\"0001\";\n-\t\t\tsum       <= x\"00000000\";\n-\t\t\tresult    <= (others => '0');\n-\t\t\tbusy      <= '1';\n-\t\t\tcounter_0_to_2 <= 0;\t\n+\t\t\tstate          <= waiting;\n+\t\t\tcounter        <= x\"0001\";\n+\t\t\tsum            <= x\"00000000\";\n+\t\t\tcounter_0_to_2 <= 0;\n \t\t\tcounter_0_to_4 <= 0;\n+\t\t\tinternal_input <= (others => '0');\n \t\telsif rising_edge(clk) then\n-\t\t\tcase state is\n-\t\t\t\twhen init =>\n-\t\t\t\t\tinternal_input <= unsigned(input);\n-\t\t\t\t\tstate  <= converting;\n-\t\t\t\twhen converting =>\n-\n-\t\t\t\t\tif counter = internal_input then\n-\t\t\t\t\t\tstate <= waiting;\n-\t\t\t\t\t\tresult <= std_logic_vector(sum);\n-\t\t\t\t\telsif (counter_0_to_2 = 2) or (counter_0_to_4 = 4) then\n-\t\t\t\t\t\tsum  <= sum + counter;\n+\t\t\tstate          <= state_next;\n+\t\t\tinternal_input <= internal_input_next;\n+\t\t\tcounter        <= counter_next;\n+\t\t\tsum            <= sum_next;\n+\t\t\tcounter_0_to_2 <= counter_0_to_2_next;\n+\t\t\tcounter_0_to_4 <= counter_0_to_4_next;\n+\t\tend if;\n+\tend process;\n+\n+\tprocess (state, internal_input, counter, sum, counter_0_to_2, counter_0_to_4, input)\n+\tbegin\n+\t\tcase state is\n+\t\t\twhen converting =>\n+\n+\t\t\t\tbusy <= '1';","path":"P001/P001.vhdl","position":66,"original_position":66,"commit_id":"35854be2306f572a8830f693e93c60b88239bcd9","original_commit_id":"35854be2306f572a8830f693e93c60b88239bcd9","user":{"login":"davi-b","id":26119943,"avatar_url":"https://avatars3.githubusercontent.com/u/26119943?v=4","gravatar_id":"","url":"https://api.github.com/users/davi-b","html_url":"https://github.com/davi-b","followers_url":"https://api.github.com/users/davi-b/followers","following_url":"https://api.github.com/users/davi-b/following{/other_user}","gists_url":"https://api.github.com/users/davi-b/gists{/gist_id}","starred_url":"https://api.github.com/users/davi-b/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/davi-b/subscriptions","organizations_url":"https://api.github.com/users/davi-b/orgs","repos_url":"https://api.github.com/users/davi-b/repos","events_url":"https://api.github.com/users/davi-b/events{/privacy}","received_events_url":"https://api.github.com/users/davi-b/received_events","type":"User","site_admin":false},"body":"Unless really necessary, outputs should be registered.\r\nIn the previous version of the code, all outputs were regiostered because they were set under a *rising_edge* clause.\r\nNow **result** and **busy** are set inside the combinational process.\r\nI suggest to create to registers for result and busy, set **result_next** and **busy_next** inside the combinational process, update result and busy inside the sequential process. Then you can set the outputs busy and result outside both process  in two lines like this:\r\n```vhdl\r\nresult_o <= result;\r\nbusy_o <= busy;\r\n```\r\nThis adds the advantage that you will be able to read the output value in your code if you so desire, by reading the register, since in VHDL you cannot directly read the output port.\r\n","created_at":"2018-03-04T19:37:58Z","updated_at":"2018-03-04T19:50:14Z","html_url":"https://github.com/ebecz/vhdl-project-euler/pull/7#discussion_r172061280","pull_request_url":"https://api.github.com/repos/ebecz/vhdl-project-euler/pulls/7","author_association":"COLLABORATOR","_links":{"self":{"href":"https://api.github.com/repos/ebecz/vhdl-project-euler/pulls/comments/172061280"},"html":{"href":"https://github.com/ebecz/vhdl-project-euler/pull/7#discussion_r172061280"},"pull_request":{"href":"https://api.github.com/repos/ebecz/vhdl-project-euler/pulls/7"}}},"pull_request":{"url":"https://api.github.com/repos/ebecz/vhdl-project-euler/pulls/7","id":172723097,"html_url":"https://github.com/ebecz/vhdl-project-euler/pull/7","diff_url":"https://github.com/ebecz/vhdl-project-euler/pull/7.diff","patch_url":"https://github.com/ebecz/vhdl-project-euler/pull/7.patch","issue_url":"https://api.github.com/repos/ebecz/vhdl-project-euler/issues/7","number":7,"state":"open","locked":false,"title":"P001: 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