{"push_id":2553105555,"size":5,"distinct_size":5,"ref":"refs/heads/softfloat/fcvt-and-arm-ahp-fixes-v3","head":"bdf00a2510fccc283a1a483e5a3f6d5d19792092","before":"e049b8f9d38d0b4d9ff98312daa2a9e6e3973951","commits":[{"sha":"31d5406800eb4f32f2e844a24504a8bf4c75f8b0","author":{"name":"Alex Bennée","email":"97ce1413105b2e68f811413f1ea07a68d9e5b40a@linaro.org"},"message":"fpu/softfloat: int_to_float ensure r fully initialised\n\nReported by Coverity (CID1390635). We ensure this for uint_to_float\nlater on so we might as well mirror that.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>","distinct":true,"url":"https://api.github.com/repos/stsquad/qemu/commits/31d5406800eb4f32f2e844a24504a8bf4c75f8b0"},{"sha":"0bc5b2bcaa0337f7beabb400f180fb64c4c6a9be","author":{"name":"Alex Bennée","email":"97ce1413105b2e68f811413f1ea07a68d9e5b40a@linaro.org"},"message":"fpu/softfloat: re-factor float to float conversions\n\nThis allows us to delete a lot of additional boilerplate code which is\nno longer needed. Currently the ieee flag is ignored (everything is\nassumed to be ieee). Handling for ARM AHP will be in the next patch.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\n\n---\nv2\n  - pass FloatFmt to float_to_float instead of sizes\n  - split AHP handling to another patch\n  - use rth's suggested re-packing (+ setting .exp)\nv3\n  - also rm extractFloat16Sign","distinct":true,"url":"https://api.github.com/repos/stsquad/qemu/commits/0bc5b2bcaa0337f7beabb400f180fb64c4c6a9be"},{"sha":"048f0d82cba19ff3e8cf54444369bc809d9d4316","author":{"name":"Alex Bennée","email":"97ce1413105b2e68f811413f1ea07a68d9e5b40a@linaro.org"},"message":"fpu/softfloat: support ARM Alternative half-precision\n\nFor float16 ARM supports an alternative half-precision format which\nsacrifices the ability to represent NaN/Inf in return for a higher\ndynamic range. To support this I've added an additional\nFloatFmt (float16_params_ahp).\n\nThe new FloatFmt flag (arm_althp) is then used to modify the behaviour\nof canonicalize and round_canonical with respect to representation and\nexception raising.\n\nFinally the float16_to_floatN and floatN_to_float16 conversion\nroutines select the new alternative FloatFmt when !ieee.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\n\n---\nv3\n  - squash NaN to 0 if destination is AHP F16","distinct":true,"url":"https://api.github.com/repos/stsquad/qemu/commits/048f0d82cba19ff3e8cf54444369bc809d9d4316"},{"sha":"5a3b386d19e5ccd5c6e74410d7a4b890bfbeb625","author":{"name":"Alex Bennée","email":"97ce1413105b2e68f811413f1ea07a68d9e5b40a@linaro.org"},"message":"target/arm: convert conversion helpers to fpst/ahp_flag\n\nInstead of passing env and leaving it up to the helper to get the\nright fpstatus we pass it explicitly. There was already a get_fpstatus\nhelper for neon for the 32 bit code. We also add an get_ahp_flag() for\npassing the state of the alternative FP16 format flag. This leaves\nscope for later tracking the AHP state in translation flags.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>","distinct":true,"url":"https://api.github.com/repos/stsquad/qemu/commits/5a3b386d19e5ccd5c6e74410d7a4b890bfbeb625"},{"sha":"bdf00a2510fccc283a1a483e5a3f6d5d19792092","author":{"name":"Alex Bennée","email":"97ce1413105b2e68f811413f1ea07a68d9e5b40a@linaro.org"},"message":"target/arm: squash FZ16 behaviour for conversions\n\nThe ARM ARM specifies FZ16 is suppressed for conversions. Rather than\npushing this logic into the softfloat code we can simply save the FZ\nstate and temporarily disable it for the softfloat call.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>","distinct":true,"url":"https://api.github.com/repos/stsquad/qemu/commits/bdf00a2510fccc283a1a483e5a3f6d5d19792092"}]}
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