{"push_id":3143016815,"size":41,"distinct_size":3,"ref":"refs/heads/work","head":"fa35098fc38e1ce1c7b8bca8d3d04c8fd21c29c7","before":"767ef876e2dca7f50840448652b0c4589d5465ad","commits":[{"sha":"e835f5f5d2f17da895fa685d2b71e8f97873b2cb","author":{"name":"Peter Fang","email":"8ecc31808e31f667eddddc37fffe00ec03284adb@intel.com"},"message":"dm: enforce data size when accessing PCI BARs\n\nAlways enforce data size when using BAR access functions.\n\nCurrently, the size serves as a hint to the BAR access functions and\nthese functions are expected to behave accordingly. Some of the access\nfunctions, e.g. virtio ones, don't always truncate the data but expect\nthe caller to take care of the data size. This causes problems with\nOVMF's virtio drivers during I/O instruction emulation because RAX can\ncontain junk bits that shouldn't be written to the device.\n\nv1 -> v2:\n- improve readability\n\nTracked-On: #1935\nSigned-off-by: Peter Fang <peter.fang@intel.com>\nAcked-by: Anthony Xu <anthony.xu@intel.com>","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/e835f5f5d2f17da895fa685d2b71e8f97873b2cb"},{"sha":"fbaecde6bb325cdfaaa2fed99fe177f26eb7d505","author":{"name":"Yang Liang","email":"214e236e3d6ff091a059753f8b300300cfdabb1d@intel.com"},"message":"DM USB: xHCI: Fix banned API issue.\n\nIn USB mediator, sscanf, strtok and atoi API is banned, so replace them\nwith permitted API function.\n\nTracked-On: #1254\nSigned-off-by: Yang Liang <liang3.yang@intel.com>\nReviewed-by: Xiaoguang Wu <xiaoguang.wu@intel.com>\nReviewed-by: Shuo Liu <shuo.a.liu@intel.com>\nReviewed-by: Yonghua Huang <yonghua.huang@intel.com>\nAcked-by: Yu Wang <yu1.wang@intel.com>","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/fbaecde6bb325cdfaaa2fed99fe177f26eb7d505"},{"sha":"e574879501d8e4e761c80a377b585e9ac12b99c5","author":{"name":"coneypo","email":"051bbd62e46417d1c4b9421bab1a4eda6432ccf0@gmail.com"},"message":"doc: update the doc of using AGL as UOS","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/e574879501d8e4e761c80a377b585e9ac12b99c5"},{"sha":"c51394c39d5a6eb57990c97b6c4cfb8e29d32981","author":{"name":"Xie Zhengtian","email":"051bbd62e46417d1c4b9421bab1a4eda6432ccf0@gmail.com"},"message":"doc: update the doc of AGL as UOS","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/c51394c39d5a6eb57990c97b6c4cfb8e29d32981"},{"sha":"73161f910ffcdb172def4e85848fc7b3e2ff7025","author":{"name":"Xie Zhengtian","email":"051bbd62e46417d1c4b9421bab1a4eda6432ccf0@gmail.com"},"message":"Update using_agl_as_uos.rst","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/73161f910ffcdb172def4e85848fc7b3e2ff7025"},{"sha":"2be939f3d1019e9c983afe7589f5dc42e9996067","author":{"name":"Xie Zhengtian","email":"051bbd62e46417d1c4b9421bab1a4eda6432ccf0@gmail.com"},"message":"Doc: add \"Deploy the UOS kernel modules for AGL\"","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/2be939f3d1019e9c983afe7589f5dc42e9996067"},{"sha":"d56e2c29e0a3a582f90f7f0d50d8a141b9cbc69b","author":{"name":"Xie Zhengtian","email":"051bbd62e46417d1c4b9421bab1a4eda6432ccf0@gmail.com"},"message":"Doc: update the steps","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/d56e2c29e0a3a582f90f7f0d50d8a141b9cbc69b"},{"sha":"c3a4a5d44d07a0617c1f9a4b6d2c434c5c9fc108","author":{"name":"Xie Zhengtian","email":"051bbd62e46417d1c4b9421bab1a4eda6432ccf0@gmail.com"},"message":"Doc: add \"$\" for code","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/c3a4a5d44d07a0617c1f9a4b6d2c434c5c9fc108"},{"sha":"2d9e478c9131786ad4675ee0b27da4f0949ad023","author":{"name":"Xie Zhengtian","email":"051bbd62e46417d1c4b9421bab1a4eda6432ccf0@gmail.com"},"message":"Doc: delete the step of downloading UOS's kernel","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/2d9e478c9131786ad4675ee0b27da4f0949ad023"},{"sha":"40f375b421a3e2f63fbab1cebe02af9c0606c744","author":{"name":"Xie Zhengtian","email":"051bbd62e46417d1c4b9421bab1a4eda6432ccf0@gmail.com"},"message":"Doc: modify the note of UOS kernel modules","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/40f375b421a3e2f63fbab1cebe02af9c0606c744"},{"sha":"07309fdc55f2295fc5066e6c2d6fa9f6372db9b9","author":{"name":"Xie Zhengtian","email":"051bbd62e46417d1c4b9421bab1a4eda6432ccf0@gmail.com"},"message":"doc: update some statements","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/07309fdc55f2295fc5066e6c2d6fa9f6372db9b9"},{"sha":"302494cb80002f8d52da186777b8b66a661e8c70","author":{"name":"Xie Zhengtian","email":"051bbd62e46417d1c4b9421bab1a4eda6432ccf0@gmail.com"},"message":"doc: update some statements","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/302494cb80002f8d52da186777b8b66a661e8c70"},{"sha":"9e917057e9882258d64f1e0e72a61ea72bae2666","author":{"name":"Min Lim","email":"d164f1b169e80cefb19bd3338673627450f5af10@intel.com"},"message":"profiling: split profiling_vmexit_handler into two functions\n\nThis patch fixes incorrect vm_id captured when sampling PMU data. Currently,\nthe vm_id gets attributed to ACRN hypervisor, rather than actual guest vm_id.\n\nThe issue is identified that the existing code captures the guest vm info\nafter vmexit_hander function is completed, in which the profiling module\npoints its context to VMM. When the vmexit happens by PMI, the guest context\nshould be captured so that the attribution to proper guest vm can happen.\n\nThis change will also allow to capture more accurate TSC when vmexit happens.\n\nTracked-On: #2043\nSigned-off-by: Min Lim <min.yeol.lim@intel.com>\nAcked-by: Eddie Dong <eddie.dong@intel.com>","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/9e917057e9882258d64f1e0e72a61ea72bae2666"},{"sha":"9a7d32f02401eb8f2600d616885aeef4d03643bf","author":{"name":"Jason Chen CJ","email":"f8cc00b4fb081090517cb2a50f235ddc9a440bf5@intel.com"},"message":"modularization: reorg the bsp_boot_init & cpu_secondary_init\n\nreorg both init functions, separate the initilization of different\ncomponents.\n\nv2:\n- separate into 2 patches, 1 for reorg, 1 for pure move.\n\nTracked-On: #1842\nSigned-off-by: Jason Chen CJ <jason.cj.chen@intel.com>\nAcked-by: Xu, Anthony <anthony.xu@intel.com>","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/9a7d32f02401eb8f2600d616885aeef4d03643bf"},{"sha":"2d469a5e5ff7dcc1c7903e1146fb848d7ed955b8","author":{"name":"Jason Chen CJ","email":"f8cc00b4fb081090517cb2a50f235ddc9a440bf5@intel.com"},"message":"modularization: hypervisor initilization component\n\nhypervisor initilization component triggered by boot component,\nand it calls different components initilization functions from\nthe highest layer.\n\nthis patch added init.c and move reorged cpu init functions into\nit, keep hardware management functions in cpu.c but move other\ncomponents' init function into init.c.\n\nthe hypervisor initilization components will call:\n- init_cpu_pre\n- init_cpu_post\n- init_bsp\n- init_debug_pre\n- init_debug_post\n- init_guest\n- init_passthru\n- enter_guest_mode\n\nthe hypervisor initilization component include files:\narch/x86/init.c\ninclude/arch/x86/init.h\n\nthis component is higest layer, so there is no reverse dependencies for it.\n\nv2:\n- separate into 2 patches, 1 for reorg, 1 for pure move.\n\nTracked-On: #1842\nSigned-off-by: Jason Chen CJ <jason.cj.chen@intel.com>\nAcked-by: Xu, Anthony <anthony.xu@intel.com>","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/2d469a5e5ff7dcc1c7903e1146fb848d7ed955b8"},{"sha":"6b998580d6984dd1fea024bdd4fffed993d04bc5","author":{"name":"yingbinx","email":"2f0a2c557c4f5c7a531bdc6b116853c21aa12aef@intel.com"},"message":"Fix KW issues for tpm_emulator\n\nThere are several KW issues which uninitialized variables\nare used. This patch will fix those KW issues.\n\nSigned-off-by: weideng <wei.a.deng@intel.com>\nSigned-off-by: yingbinx <yingbinx.zeng@intel.com>","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/6b998580d6984dd1fea024bdd4fffed993d04bc5"},{"sha":"a958fea7a45d51355228dd9bb04ce4579f69d43b","author":{"name":"Zide Chen","email":"09a0dff98440d5beac510b9e43a2f53ed7511963@intel.com"},"message":"hv: emulate IA32_TSC_ADJUST MSR\n\nIntercept IA32_TSC_ADJUST MSR so that writing IA32_TSC_ADJUST from the\nguests won't impact the TSC in root mode or potentially other vCPUs in\nthe same pCPU.\n\n- MSR TSC_ADJUST needs to be isolated between normal and secure world,\n  so it's included in NUM_WORLD_MSRS.\n- Upon writing to either IA32_TSC_ADJUST or IA32_TSC from the guests,\n  don't write to physical MSRS so it won't impact the host side, but\n  update the TSC offset VM-execution control.\n- don't need to intercept rdmsr for IA32_TIME_STAMP_COUNTER.\n- add the missing statement in save_world_ctx() to save the tsc_offset\n  during world switch.\n\nTracked-On: #1867\nSigned-off-by: Zide Chen <zide.chen@intel.com>\nAcked-by: Anthony Xu <anthony.xu@intel.com>","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/a958fea7a45d51355228dd9bb04ce4579f69d43b"},{"sha":"4131d46f84294cd4d00cb256310f6a762cc94121","author":{"name":"Li, Fei1","email":"e618fc15a8e1faf12378e7754d602fb0fa79d0e8@intel.com"},"message":"hv: remove goto in ept_violation_vmexit_handler\n\nUsing goto leads the code to be difficult to read and maintain\n\nTracked-On: #861\nSigned-off-by: Li, Fei1 <fei1.li@intel.com>","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/4131d46f84294cd4d00cb256310f6a762cc94121"},{"sha":"e114ea7e5da44f4a54be3176714dfd23a63094c7","author":{"name":"Li, Fei1","email":"e618fc15a8e1faf12378e7754d602fb0fa79d0e8@intel.com"},"message":"hv: timer: fix procedure has more than one exit point\n\nRefine add_timer/timer_init to only one exit point\n\nTracked-On: #861\nSigned-off-by: Li, Fei1 <fei1.li@intel.com>","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/e114ea7e5da44f4a54be3176714dfd23a63094c7"},{"sha":"e066774a1c8add6d43bfd8441698337d48e6ca56","author":{"name":"Li, Fei1","email":"e618fc15a8e1faf12378e7754d602fb0fa79d0e8@intel.com"},"message":"hv: refine strnlen_s/strstr_s to only one exit point\n\nFix procedure has more than one exit point\n\nTracked-On: #861\nSigned-off-by: Li, Fei1 <fei1.li@intel.com>","distinct":false,"url":"https://api.github.com/repos/mcao6/acrn-hypervisor/commits/e066774a1c8add6d43bfd8441698337d48e6ca56"}]}
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