{"push_id":2621789283,"size":15,"distinct_size":15,"ref":"refs/heads/amd-common","head":"8e93ed23a43b3807b8d5963fdc8ffe255ea0413e","before":"3488bacb6e2335190b3b3ba47fcc89a55f890d6b","commits":[{"sha":"912ef7aa018c672beb208b6169813925dbe845c9","author":{"name":"Craig Topper","email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@intel.com"},"message":"[X86] Make all instructions that operate on MMX types, but were added after the initial MMX support via one of the SSE features flags make them require the MMX feature as well.\n\nPassing -mattr=-mmx needs to disable these instructions since the MMX register class won't have been set up. But we don't want -mattr=-mmx to disable SSE so we have to do it separately.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333984 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/912ef7aa018c672beb208b6169813925dbe845c9"},{"sha":"3c5de91faa1e7d778c63385323fdc144de821303","author":{"name":"Alexander Ivchenko","email":"2c04cd96101bf19c6b7b8726113da8b7d294b669@intel.com"},"message":"[X86][CET] Shadow stack fix for setjmp/longjmp\n\nThis is the new version of D46181, allowing setjmp/longjmp\nto work correctly with the Intel CET shadow stack by storing\nSSP on setjmp and fixing it on longjmp. The patch has been\nupdated to use the cf-protection-return module flag instead\nof HasSHSTK, and the bug that caused D46181 to be reverted\nhas been fixed with the test expanded to track that fix.\n\npatch by mike.dvoretsky\n\nDifferential Revision: https://reviews.llvm.org/D47311\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333990 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/3c5de91faa1e7d778c63385323fdc144de821303"},{"sha":"7fd3761e18c887b5ae49dd06a79d8219e69a1064","author":{"name":"Peter Smith","email":"53c7352ee073ca33af0154303b3d5ac4294a55bf@linaro.org"},"message":"[MC][ARM] Correct Thumb BL instruction range\n\nThe Thumb BL range is + or - either 16 Megabytes or 4 Megabytes depending\non whether the CPU supports Thumb2 or the v8-m baseline ops. The existing\ncheck for BL range is incorrectly set at +- 32 Megabytes. This change\ncorrects the higher range and uses the lower range if the featurebits\ndon't have the necessary support for it.\n\nDifferential Revision: https://reviews.llvm.org/D46305\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333991 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/7fd3761e18c887b5ae49dd06a79d8219e69a1064"},{"sha":"c08e3f7298d53451ec250a8bf6213a3d1118c654","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[X86][SSE] Add basic PACKUS support to X86TargetLowering::computeKnownBitsForTargetNode\n\nHelps improve analysis of saturation ops\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333995 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/c08e3f7298d53451ec250a8bf6213a3d1118c654"},{"sha":"13e7624a748b043d21d4b0d25bf526cbca581334","author":{"name":"Peter Smith","email":"53c7352ee073ca33af0154303b3d5ac4294a55bf@linaro.org"},"message":"[MC][ARM] Add range checking for Thumb2 resolved fixups.\n\nWhen the branch target of a Thumb2 unconditional or conditonal branch is\nresolved at assembly time, no range checking is performed on the result\nleading to incorrect immediates. This change adds a range check:\n+- 16 Megabytes for unconditional branches, +- 1 Megabyte for the\nconditional branch.\n\nDifferential Revision: https://reviews.llvm.org/D46306\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333997 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/13e7624a748b043d21d4b0d25bf526cbca581334"},{"sha":"b00bb39e2388f97bc956537270e6e09fffd28f85","author":{"name":"Gabor Buella","email":"cebd756dede555dd7c4270e7fb862bd2ac0ff5c4@intel.com"},"message":"[X86] NFC Refactor some code in InstPrinters\n\nSummary:\nBringing some come duplicated in the AT&T and the Intel printers\ninto a common parent class.\n\nReviewers: craig.topper\n\nReviewed By: craig.topper\n\nDifferential Revision: https://reviews.llvm.org/D47682\n\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334005 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/b00bb39e2388f97bc956537270e6e09fffd28f85"},{"sha":"3f2a06592b378a2d713ef30a82ae0716a1d9224c","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[X86][SSE] Add target shuffle support to X86TargetLowering::computeKnownBitsForTargetNode\n\nIdeally we'd use resolveTargetShuffleInputs to handle faux shuffles as well but:\n(a) that code path doesn't handle general/pre-legalized ops/types very well.\n(b) I'm concerned about the compute time as they recurse to calls to computeKnownBits/ComputeNumSignBits which would need depth limiting somehow.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334007 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/3f2a06592b378a2d713ef30a82ae0716a1d9224c"},{"sha":"bed775073b82a4898b170613755abadd450b0157","author":{"name":"Clement Courbet","email":"18a6ad33eeb00c3a39b33c2572bde72aa7e82ab1@google.com"},"message":"[llvm-exegesis] Add instructions to BenchmarkResult Key.\n\nWe want llvm-exegesis to explore instructions (effect of initial register values, effect of operand selection). To enable this a BenchmarkResult muststore all the relevant data in its key. This patch starts adding such data. Here we simply allow to store the generated instructions, following patches will add operands and initial values for registers.\n\nhttps://reviews.llvm.org/D47764\n\nAuthored by: Guilluame Chatelet\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334008 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/bed775073b82a4898b170613755abadd450b0157"},{"sha":"a518a5e97ec05be53fa53734c3ae3807006b82fe","author":{"name":"Simon Pilgrim","email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk"},"message":"[X86][SSE] Fix line endings for shuffle-vs-trunc tests. NFCI.\n\nStrip native eol property which we don't use in this folder.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334010 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/a518a5e97ec05be53fa53734c3ae3807006b82fe"},{"sha":"8b13d9fafa15ed8290ed01b37fe02a2a3063551a","author":{"name":"Hiroshi Inoue","email":"a2f6a8ea319c80e629c0fd6f31e552ada183b2d5@jp.ibm.com"},"message":"[PowerPC] reduce rotate in BitPermutationSelector\n\nBitPermutationSelector builds the output value by repeating rotate-and-mask instructions with input registers.\nHere, we may avoid one rotate instruction if we start building from an input register that does not require rotation.\n\nFor example of the test case bitfieldinsert.ll, it first rotates left r4 by 8 bits and then inserts some bits from r5 without rotation.\nThis can be executed by one rlwimi instruction, which rotates r4 by 8 bits and inserts its bits into r5.\n\nThis patch adds a check for rotation amounts in the comparator used in sorting to process the input without rotation first.\n\nDifferential Revision: https://reviews.llvm.org/D47765\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334011 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/8b13d9fafa15ed8290ed01b37fe02a2a3063551a"},{"sha":"19eacef7de19bf8f2c2d75b46c3375b804bed090","author":{"name":"Krzysztof Parzyszek","email":"c75c6ffbe1757b9a0c4a980ebbd301c4f55ecd30@codeaurora.org"},"message":"[Hexagon] Minor cleanups in isel lowering\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334015 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/19eacef7de19bf8f2c2d75b46c3375b804bed090"},{"sha":"d117450d6abb27902d88bff0d930ab6b4d2a464f","author":{"name":"Gabor Buella","email":"cebd756dede555dd7c4270e7fb862bd2ac0ff5c4@intel.com"},"message":"[X86] NFC Fix typo introduced in r328016 HSI->HDI\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334016 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/d117450d6abb27902d88bff0d930ab6b4d2a464f"},{"sha":"afeab7264c95d3db509ab2861ef39b80871a1641","author":{"name":"Jenkins","email":"65f48432a179cd87fe914a5a7f7e60a506981f53@amd.com"},"message":"Merge branch master into amd-master","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/afeab7264c95d3db509ab2861ef39b80871a1641"},{"sha":"e04da8521610c4cac12ca1c00724801de473dfb6","author":{"name":"Jenkins","email":"65f48432a179cd87fe914a5a7f7e60a506981f53@amd.com"},"message":"Merge branch amd-master into amd-common","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/e04da8521610c4cac12ca1c00724801de473dfb6"},{"sha":"8e93ed23a43b3807b8d5963fdc8ffe255ea0413e","author":{"name":"Jenkins","email":"65f48432a179cd87fe914a5a7f7e60a506981f53@amd.com"},"message":"Merge branch amd-common into amd-common","distinct":true,"url":"https://api.github.com/repos/RadeonOpenCompute/llvm/commits/8e93ed23a43b3807b8d5963fdc8ffe255ea0413e"}]}
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