{"action":"opened","issue":{"url":"https://api.github.com/repos/m-labs/nmigen/issues/5","repository_url":"https://api.github.com/repos/m-labs/nmigen","labels_url":"https://api.github.com/repos/m-labs/nmigen/issues/5/labels{/name}","comments_url":"https://api.github.com/repos/m-labs/nmigen/issues/5/comments","events_url":"https://api.github.com/repos/m-labs/nmigen/issues/5/events","html_url":"https://github.com/m-labs/nmigen/issues/5","id":391204454,"node_id":"MDU6SXNzdWUzOTEyMDQ0NTQ=","number":5,"title":"Detect multiple drivers in different hierarchical modules","user":{"login":"whitequark","id":54771,"node_id":"MDQ6VXNlcjU0Nzcx","avatar_url":"https://avatars1.githubusercontent.com/u/54771?v=4","gravatar_id":"","url":"https://api.github.com/users/whitequark","html_url":"https://github.com/whitequark","followers_url":"https://api.github.com/users/whitequark/followers","following_url":"https://api.github.com/users/whitequark/following{/other_user}","gists_url":"https://api.github.com/users/whitequark/gists{/gist_id}","starred_url":"https://api.github.com/users/whitequark/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/whitequark/subscriptions","organizations_url":"https://api.github.com/users/whitequark/orgs","repos_url":"https://api.github.com/users/whitequark/repos","events_url":"https://api.github.com/users/whitequark/events{/privacy}","received_events_url":"https://api.github.com/users/whitequark/received_events","type":"User","site_admin":false},"labels":[{"id":1160977836,"node_id":"MDU6TGFiZWwxMTYwOTc3ODM2","url":"https://api.github.com/repos/m-labs/nmigen/labels/bug","name":"bug","color":"f7c6c7","default":true}],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2018-12-14T17:43:13Z","updated_at":"2018-12-14T17:43:13Z","closed_at":null,"author_association":"MEMBER","body":"Right now nMigen silently generates invalid Verilog for that. It should (eventually) auto-flatten the hierarchy, but at least this should be detected."}}
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