{"push_id":2501136587,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"0e88a2b48056f47019dd98b56aedcbe254304cda","before":"ab85265c93fa43c87a7c6d4632ec6af79036eabe","commits":[{"sha":"0e88a2b48056f47019dd98b56aedcbe254304cda","author":{"name":"Sander de Smalen","email":"cfb2bb6ce14dfe626ffa26d9d86d8d43a3b39961@arm.com"},"message":"[AArch64][AsmParser] Extend RegOp with integrated 'shift/extend'.\n\nSummary:\nIn some cases the shift/extend needs to be explicitly parsed together\nwith the register, rather than as a separate operand. This is needed\nfor addressing modes where the instruction as a whole dictates the\nscaling/extend, rather than specific bits in the instruction.\nBy parsing them as a single operand, we avoid the need to pass an\nextra operand in all CodeGen patterns (because all operands need to\nhave an associated value), and we avoid the need to update TableGen to\naccept operands that have no associated bits in the instruction.\n\nAn added benefit of parsing them together is that the assembler\ncan give a sensible diagnostic if the scaling is not correct.\n\nThis is patch [2/4] in a series to add assembler/disassembler support for\nSVE's contiguous LD1 (scalar+scalar) instructions:\n- Patch [1/4]: https://reviews.llvm.org/D45687\n- Patch [2/4]: https://reviews.llvm.org/D45688\n- Patch [3/4]: https://reviews.llvm.org/D45689\n- Patch [4/4]: https://reviews.llvm.org/D45690\n\nReviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro\n\nReviewed By: fhahn, SjoerdMeijer\n\nSubscribers: kristof.beyls, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D45688","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project-submodule/commits/0e88a2b48056f47019dd98b56aedcbe254304cda"}]}
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